Johannes Stratmann
added support for LPC4088
Fork of
QEI_hw
by 
Hexley Ball
Revision 3:9279a8f154c8, committed 2016-03-02
- Comitter:
- JojoS
- Date:
- Wed Mar 02 10:37:13 2016 +0000
- Parent:
- 2:53f8ae2cf502
- Commit message:
- ported to LPC4088;
Changed in this revision
| qeihw.cpp | Show annotated file Show diff for this revision Revisions of this file |
| qeihw.h | Show annotated file Show diff for this revision Revisions of this file |
--- a/qeihw.cpp Tue Dec 28 19:32:07 2010 +0000
+++ b/qeihw.cpp Wed Mar 02 10:37:13 2016 +0000
@@ -13,6 +13,7 @@
* @author hb
**************************************************************************/
#include "mbed.h"
+#include "pinmap.h"
#include "qeihw.h"
QEIHW *QEIHW::instance;
@@ -25,8 +26,9 @@
* @param _invinx Invert index. When = 1, inverts the sense of the index signal
* @return None
**********************************************************************/
-QEIHW::QEIHW(uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx)
+QEIHW::QEIHW(uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx, uint32_t _crespi)
{
+#ifdef TARGET_LPC1768
/* Set up clock and power for QEI module */
LPC_SC->PCONP |= PCONP_QEI_ENABLE;
@@ -73,6 +75,58 @@
// Clear any pending ints
LPC_QEI->QEICLR = QEI_INTCLR_BITMASK; // Set the "clear" bits for for all sources in the Interrupt clear register
+#elif TARGET_LPC4088
+ /* Set up clock and power for QEI module */
+ LPC_SC->PCONP |= PCONP_QEI_ENABLE;
+
+ /* The clock for theQEI module is set to FCCLK, PCLKSEL{4:0] = 0x1 */
+ LPC_SC->PCLKSEL = LPC_SC->PCLKSEL & ~(0x1fUL<<0) | ((PCLKSEL_CCLK_DIV_1 & 0x1fUL)<<0);
+
+ /* Assign the pins. They are hard-coded, not user-selected. The index
+ * pin is assigned, even though it is not easily accessed on the mbed.
+ * As it may be unconnected, it is given a pull-up resistor to minimize
+ * power drain.
+ */
+ // MCI0 (PhA)
+ pin_function(P1_20, 3); // P1.20 = QEI_PHA
+ pin_mode(P1_20, PullUp);
+
+ // MCI1 (PhB)
+ pin_function(P1_23, 3); // P1.23 = QEI_PHB
+ pin_mode(P1_23, PullUp);
+
+ // MCI2 (Index)
+ pin_function(P1_24, 3); // P1.23 = QEI_IDX
+ pin_mode(P1_24, PullUp);
+
+ // Initialize all remaining values in QEI peripheral
+ LPC_QEI->CON = QEI_CON_RESP | QEI_CON_RESV | QEI_CON_RESI;
+ LPC_QEI->MAXPOS = 0xFFFFFFFF; // Default value
+ LPC_QEI->CMPOS0 = 0x00;
+ LPC_QEI->CMPOS1 = 0x00;
+ LPC_QEI->CMPOS2 = 0x00;
+ LPC_QEI->INXCMP0 = 0x00;
+ LPC_QEI->INXCMP1 = 0x00;
+ LPC_QEI->LOAD = 0x00;
+ LPC_QEI->VELCOMP = 0x00;
+ LPC_QEI->FILTERPHA = 0; // Bypass Filter for PHA
+ LPC_QEI->FILTERPHB = 0; // Bypass Filter for PHB
+ LPC_QEI->FILTERINX = 0; // Bypass Filter for INDEX
+
+ // Set QEI configuration value corresponding to the call parameters
+ LPC_QEI->CONF = (
+ ((_dirinv << 0) & 1) | \
+ ((_sigmode << 1) & 2) | \
+ ((_capmode << 2) & 4) | \
+ ((_invinx << 3) & 8) | \
+ ((_crespi << 4) & 16) );
+
+ // Mask all int sources
+ LPC_QEI->IEC = QEI_IECLR_BITMASK; // Set the "clear" bits for all sources in the IE clear register
+
+ // Clear any pending ints
+ LPC_QEI->CLR = QEI_INTCLR_BITMASK; // Set the "clear" bits for for all sources in the Interrupt clear register
+#endif
/* preemption = 1, sub-priority = 1 */
NVIC_SetPriority(QEI_IRQn, ((0x01<<3)|0x01));
@@ -98,7 +152,11 @@
**********************************************************************/
void QEIHW::Reset(uint32_t ulResetType)
{
+#ifdef TARGET_LPC1768
LPC_QEI->QEICON = ulResetType;
+#elif TARGET_LPC4088
+ LPC_QEI->CON = ulResetType;
+#endif
}
/*********************************************************************//**
@@ -112,6 +170,7 @@
/* Turn off clock and power for QEI module */
LPC_SC->PCONP &= PCONP_QEI_DISABLE;
+#ifdef TARGET_LPC1768
/* Return pins to their default assignment (PINSEL = 0, PINMODE = PULLDOWN) */
// MCI0 (PhA) -> LED-2 (p1.20)
LPC_PINCON->PINSEL3 &= PINSEL3_MCI0_MASK;
@@ -124,6 +183,16 @@
// MCI2 (Index) -> p1.24
LPC_PINCON->PINSEL3 &= PINSEL3_MCI2_MASK;
LPC_PINCON->PINMODE3 = (LPC_PINCON->PINMODE3 & PINMODE3_MCI2_MASK) | PINMODE3_GPIO1p24;
+#elif TARGET_LPC4088
+ pin_function(P1_20, 0);
+ pin_mode(P1_20, PullDown);
+
+ pin_function(P1_23, 0);
+ pin_mode(P1_23, PullDown);
+
+ pin_function(P1_24, 0);
+ pin_mode(P1_24, PullDown);
+#endif
}
/*********************************************************************//**
@@ -133,7 +202,11 @@
**********************************************************************/
FlagStatus QEIHW::Direction()
{
+#ifdef TARGET_LPC1768
return ((LPC_QEI->QEISTAT & QEI_STATUS_DIR) ? SET : RESET);
+#elif TARGET_LPC4088
+ return ((LPC_QEI->STAT & QEI_STATUS_DIR) ? SET : RESET);
+#endif
}
/*********************************************************************//**
@@ -143,7 +216,11 @@
**********************************************************************/
uint32_t QEIHW::GetPosition()
{
+#ifdef TARGET_LPC1768
return (LPC_QEI->QEIPOS);
+#elif TARGET_LPC4088
+ return (LPC_QEI->POS);
+#endif
}
/*********************************************************************//**
@@ -154,7 +231,11 @@
**********************************************************************/
void QEIHW::SetMaxPosition(uint32_t ulMaxPos)
{
+#ifdef TARGET_LPC1768
LPC_QEI->QEIMAXPOS = ulMaxPos;
+#elif TARGET_LPC4088
+ LPC_QEI->MAXPOS = ulMaxPos;
+#endif
}
/*********************************************************************//**
@@ -192,7 +273,11 @@
**********************************************************************/
void QEIHW::SetIndexComp( uint32_t ulIndexComp)
{
+#ifdef TARGET_LPC1768
LPC_QEI->INXCMP = ulIndexComp;
+#elif TARGET_LPC4088
+ LPC_QEI->INXCMP0 = ulIndexComp;
+#endif
}
/*********************************************************************//**
@@ -203,7 +288,11 @@
**********************************************************************/
void QEIHW::SetVelocityTimerReload( uint32_t ulReloadValue)
{
- LPC_QEI->QEILOAD = ulReloadValue;
+#ifdef TARGET_LPC1768
+ LPC_QEI->QEILOAD = ulReloadValue;
+#elif TARGET_LPC4088
+ LPC_QEI->LOAD = ulReloadValue;
+#endif
}
/*********************************************************************//**
@@ -219,12 +308,17 @@
//Work out CCLK
uint32_t m = (LPC_SC->PLL0CFG & 0xFFFF) + 1;
uint32_t n = (LPC_SC->PLL0CFG >> 16) + 1;
+#ifdef TARGET_LPC1768
uint32_t cclkdiv = LPC_SC->CCLKCFG + 1;
+#elif TARGET_LPC4088
+ uint32_t cclkdiv = (LPC_SC->CCLKSEL & 0x1f) + 1;
+#endif
uint32_t Fcco = (2 * m * XTAL_FREQ) / n;
uint32_t cclk = Fcco / cclkdiv;
+#ifdef TARGET_LPC1768
// div = CLKPWR_GetPCLKSEL(ClkType);
div = LPC_SC->PCLKSEL1 & PCLKSEL1_PCLK_QEI_MASK;
switch (div)
@@ -247,7 +341,17 @@
}
cclk /=div;
cclk =((uint64_t)cclk / (1000000/ulReloadValue)) - 1;
+
LPC_QEI->QEILOAD = (uint32_t) cclk;
+
+#elif TARGET_LPC4088
+ div = LPC_SC->PCLKSEL & PCLKSEL1_PCLK_QEI_MASK;
+ if (div != 0)
+ cclk /=div;
+ cclk =((uint64_t)cclk / (1000000/ulReloadValue)) - 1;
+
+ LPC_QEI->LOAD = (uint32_t) cclk;
+#endif
}
/*********************************************************************//**
@@ -257,7 +361,11 @@
**********************************************************************/
uint32_t QEIHW::GetTimer()
{
+#ifdef TARGET_LPC1768
return (LPC_QEI->QEITIME);
+#elif TARGET_LPC4088
+ return (LPC_QEI->TIME);
+#endif
}
/*********************************************************************//**
@@ -267,7 +375,11 @@
**********************************************************************/
uint32_t QEIHW::GetVelocity()
{
+#ifdef TARGET_LPC1768
return (LPC_QEI->QEIVEL);
+#elif TARGET_LPC4088
+ return (LPC_QEI->VEL);
+#endif
}
/*********************************************************************//**
@@ -279,7 +391,11 @@
**********************************************************************/
uint32_t QEIHW::GetVelocityCap()
{
+#ifdef TARGET_LPC1768
return (LPC_QEI->QEICAP);
+#elif TARGET_LPC4088
+ return (LPC_QEI->CAP);
+#endif
}
/*********************************************************************//**
@@ -302,7 +418,13 @@
**********************************************************************/
void QEIHW::SetDigiFilter( uint32_t ulSamplingPulse)
{
+#ifdef TARGET_LPC1768
LPC_QEI->FILTER = ulSamplingPulse;
+#elif TARGET_LPC4088
+ LPC_QEI->FILTERPHA = ulSamplingPulse;
+ LPC_QEI->FILTERPHB = ulSamplingPulse;
+ LPC_QEI->FILTERINX = ulSamplingPulse;
+#endif
}
/*********************************************************************//**
@@ -331,7 +453,11 @@
**********************************************************************/
FlagStatus QEIHW::GetIntStatus( uint32_t ulIntType)
{
+#ifdef TARGET_LPC1768
return((LPC_QEI->QEIINTSTAT & ulIntType) ? SET : RESET);
+#elif TARGET_LPC4088
+ return((LPC_QEI->INTSTAT & ulIntType) ? SET : RESET);
+#endif
}
/*********************************************************************//**
@@ -362,11 +488,19 @@
**********************************************************************/
void QEIHW::IntCmd( uint32_t ulIntType, FunctionalState NewState)
{
+#ifdef TARGET_LPC1768
if (NewState == ENABLE) {
LPC_QEI->QEIIES = ulIntType;
} else {
LPC_QEI->QEIIEC = ulIntType;
}
+#elif TARGET_LPC4088
+ if (NewState == ENABLE) {
+ LPC_QEI->IES = ulIntType;
+ } else {
+ LPC_QEI->IEC = ulIntType;
+ }
+#endif
}
/*********************************************************************//**
@@ -394,7 +528,11 @@
**********************************************************************/
void QEIHW::IntSet( uint32_t ulIntType)
{
+#ifdef TARGET_LPC1768
LPC_QEI->QEISET = ulIntType;
+#elif TARGET_LPC4088
+ LPC_QEI->SET = ulIntType;
+#endif
}
/*********************************************************************//**
@@ -422,7 +560,11 @@
**********************************************************************/
void QEIHW::IntClear( uint32_t ulIntType)
{
+#ifdef TARGET_LPC1768
LPC_QEI->QEICLR = ulIntType;
+#elif TARGET_LPC4088
+ LPC_QEI->CLR = ulIntType;
+#endif
}
/*********************************************************************//**
@@ -444,10 +586,16 @@
//Work out CCLK
uint32_t m = (LPC_SC->PLL0CFG & 0xFFFF) + 1;
uint32_t n = (LPC_SC->PLL0CFG >> 16) + 1;
+#ifdef TARGET_LPC1768
uint32_t cclkdiv = LPC_SC->CCLKCFG + 1;
+#elif TARGET_LPC4088
+ uint32_t cclkdiv = (LPC_SC->CCLKSEL & 0x1f) + 1;
+#endif
uint32_t Fcco = (2 * m * XTAL_FREQ) / n;
uint32_t cclk = Fcco / cclkdiv;
+
+#ifdef TARGET_LPC1768
// div = CLKPWR_GetPCLKSEL(ClkType);
div = LPC_SC->PCLKSEL1 & PCLKSEL1_PCLK_QEI_MASK;
switch (div)
@@ -468,8 +616,8 @@
div = 8;
break;
}
- cclk /= div;
-
+ cclk /=div;
+
// Get Timer load value (velocity capture period)
Load = (uint64_t)(LPC_QEI->QEILOAD + 1);
// Get Edge
@@ -477,6 +625,21 @@
// Calculate RPM
rpm = ((( uint64_t)cclk * ulVelCapValue * 60) / (Load * ulPPR * edges));
+#elif TARGET_LPC4088
+ div = LPC_SC->PCLKSEL & PCLKSEL1_PCLK_QEI_MASK;
+ if (div != 0)
+ cclk /=div;
+
+ // Get Timer load value (velocity capture period)
+ Load = (uint64_t)(LPC_QEI->LOAD + 1);
+ // Get Edge
+ edges = (uint64_t)((LPC_QEI->CONF & QEI_CONF_CAPMODE) ? 4 : 2);
+ // Calculate RPM
+ rpm = ((( uint64_t)cclk * ulVelCapValue * 60) / (Load * ulPPR * edges));
+#endif
+
+
+
return (uint32_t)(rpm);
}
@@ -569,6 +732,7 @@
{
int32_t i;
+#ifdef TARGET_LPC1768
//User defined interrupt handlers. Check all possible sources, dispatch to corresponding non-null service routines.
for(i = 0; i < 13; i++) {
if(LPC_QEI->QEIINTSTAT & ((uint32_t)(1<<i)) ) {
@@ -577,6 +741,16 @@
}
}
}
+#elif TARGET_LPC4088
+ //User defined interrupt handlers. Check all possible sources, dispatch to corresponding non-null service routines.
+ for(i = 0; i < 16; i++) {
+ if(LPC_QEI->INTSTAT & ((uint32_t)(1<<i)) ) {
+ if (_qei_isr[i] != NULL) {
+ _qei_isr[i]();
+ }
+ }
+ }
+#endif
return;
}
--- a/qeihw.h Tue Dec 28 19:32:07 2010 +0000
+++ b/qeihw.h Wed Mar 02 10:37:13 2016 +0000
@@ -76,8 +76,9 @@
* @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
* @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
* @param _invinx Invert index. When = 1, inverts the sense of the index signal
+ * @param _crespi Reset Position on Index. When = 1, resets position counter on index signal
*/
- QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx);
+ QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx, uint32_t _crespi=0);
/** Resets value for each type of QEI value, such as velocity, position, etc.
*
@@ -416,29 +417,37 @@
void Qeiisr(void);
static QEIHW *instance;
+#ifdef TARGET_LPC1768
void(*_qei_isr[13])();
-
+#elif TARGET_LPC4088
+void(*_qei_isr[16])();
+#endif
/* Private Macros ------------------------------------------------------------- */
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/* Quadrature Encoder Interface Control Register Definition --------------------- */
/*********************************************************************//**
- * Macro defines for QEI Control register
+ * Macro defines for QEI Control register LPC1768, LPC4088
**********************************************************************/
#define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
-#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
+#define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
#define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
#define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
-#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
+#define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
/*********************************************************************//**
* Macro defines for QEI Configuration register
**********************************************************************/
-#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
+#define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
#define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
#define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
-#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
+#define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
+#ifdef TARGET_LPC1768
#define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_CONF_CRESPI ((uint32_t)(1<<4)) /**< reset ounter on index */
+#define QEI_CONF_BITMASK ((uint32_t)(0x1F)) /**< QEI Configuration register bit-mask */
+#endif
/*********************************************************************//**
* Macro defines for QEI Status register
@@ -450,143 +459,193 @@
/*********************************************************************//**
* Macro defines for QEI Interrupt Status register
**********************************************************************/
-#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
-#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
-#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
-#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
-#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
-#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
-#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
- index count */
-#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
- both the POS0_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
- both the POS1_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
- both the POS2_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
+#define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
+#define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
+#define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
+#define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
+#define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
+ both the POS0_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
+ both the POS1_Int bit is set and the REV_Int is set */
+#define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
+ both the POS2_Int bit is set and the REV_Int is set */
+#ifdef TARGET_LPC1768
+#define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_INTSTAT_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_INTSTAT_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_INTSTAT_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_INTSTAT_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
/*********************************************************************//**
* Macro defines for QEI Interrupt Set register
**********************************************************************/
-#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
-#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
-#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
-#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
- index count */
-#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
+#define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
+#define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
+#define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
+#define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
+#ifdef TARGET_LPC1768
+#define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_INTSET_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_INTSET_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_INTSET_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_INTSET_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
+
/*********************************************************************//**
* Macro defines for QEI Interrupt Clear register
**********************************************************************/
-#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
-#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
-#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
-#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
- index count */
-#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
+#define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
+#define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
+#define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
+#define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
+#ifdef TARGET_LPC1768
+#define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_INTCLR_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_INTCLR_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_INTCLR_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable register
**********************************************************************/
-#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
- index count */
-#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
+#define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#ifdef TARGET_LPC1768
+#define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_INTEN_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_INTEN_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_INTEN_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_INTEN_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Set register
**********************************************************************/
-#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
- index count */
-#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
+#define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
+#ifdef TARGET_LPC1768
+#define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_IESET_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_IESET_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_IESET_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_IESET_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
/*********************************************************************//**
* Macro defines for QEI Interrupt Enable Clear register
**********************************************************************/
-#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
- current position */
-#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
- current position */
-#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
- current position */
-#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
- index count */
-#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
+#define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
+#define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
+#define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
+#define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
+#define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
+#define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
+#define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
+ current position */
+#define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
+ current position */
+#define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
+ current position */
+#define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
+ index count */
+#define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
+#define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
+#define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
+#ifdef TARGET_LPC1768
+#define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
+#elif TARGET_LPC4088
+#define QEI_IECLR_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
+#define QEI_IECLR_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
+#define QEI_IECLR_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
+ the forward direction, or through zero to MAXPOS in the reverse direction. */
+#define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
+#endif
+
/*********************************************************************//**
* Macro defines for PCONP register QEI-related bits
**********************************************************************/
-#define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
-#define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
+#define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
+#define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
/*********************************************************************//**
* Macro defines for PCLKSELx register QEI-related bits
@@ -595,10 +654,16 @@
#define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
#define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
#define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
+#ifdef TARGET_LPC1768
#define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
+#elif TARGET_LPC4088
+#define PCLKSEL1_PCLK_QEI_MASK (0x1fUL) /**< PCLK_QEI PCLK_QEI bit field mask */
+#endif
+
/*********************************************************************//**
- * Macro defines for PINSEL3 register QEI-related bits
+ * Macro defines for PINSEL3 register QEI-related bits (LPC1768 only)
**********************************************************************/
+#ifdef TARGET_LPC1768
#define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
#define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
#define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
@@ -607,7 +672,7 @@
#define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
/*********************************************************************//**
- * Macro defines for PINMODE3 register QEI-related bits
+ * Macro defines for PINMODE3 register QEI-related bits(LPC1768 only)
**********************************************************************/
#define PIN_PULL_UP 0UL
#define PIN_REPEATER 1UL
@@ -625,7 +690,7 @@
#define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
#define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
#define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
-
+#endif
};