Johannes Stratmann / QEI_hw

added support for LPC4088

Fork of QEI_hw by Hexley Ball

qeihw.h@3:9279a8f154c8, 2016-03-02 (annotated)

Committer:
JojoS
Date:
Wed Mar 02 10:37:13 2016 +0000
Revision:
3:9279a8f154c8
Parent:
1:018226f83d80 
ported to LPC4088;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hexley 0:20a27391f6dc 1 /* mbed Library - QEIhw
hexley 0:20a27391f6dc 2 * Copyright (c) 2010, hball
hexley 0:20a27391f6dc 3 * released under MIT license http://mbed.org/licence/mit
hexley 0:20a27391f6dc 4 */
hexley 0:20a27391f6dc 5
hexley 0:20a27391f6dc 6 /***********************************************************************//**
hexley 0:20a27391f6dc 7 * @file qeihw.h
hexley 0:20a27391f6dc 8 * @brief Header file for the qeihw driver. Adapted from the CMSIS
hexley 0:20a27391f6dc 9 * header, lpc17xx_qei.h, v 2.0
hexley 0:20a27391f6dc 10 * @version 0.0
hexley 0:20a27391f6dc 11 * @date 10 Dec 2010
hexley 0:20a27391f6dc 12 * @author hb
hexley 0:20a27391f6dc 13 **************************************************************************/
hexley 0:20a27391f6dc 14
hexley 0:20a27391f6dc 15
hexley 0:20a27391f6dc 16 #ifndef MBED_QEIHW_H
hexley 0:20a27391f6dc 17 #define MBED_QEIHW_H
hexley 0:20a27391f6dc 18
hexley 0:20a27391f6dc 19 /* Includes ------------------------------------------------------------------- */
hexley 0:20a27391f6dc 20 #include "mbed.h"
hexley 0:20a27391f6dc 21
hexley 0:20a27391f6dc 22
hexley 0:20a27391f6dc 23 /* Public Types --------------------------------------------------------------- */
hexley 0:20a27391f6dc 24
hexley 0:20a27391f6dc 25 /* Flag Status type definition */
hexley 0:20a27391f6dc 26 typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
hexley 0:20a27391f6dc 27
hexley 0:20a27391f6dc 28 /* Functional State Definition */
hexley 0:20a27391f6dc 29 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
hexley 0:20a27391f6dc 30
hexley 0:20a27391f6dc 31
hexley 0:20a27391f6dc 32 /* Other definitions */
hexley 0:20a27391f6dc 33 #define XTAL_FREQ 12000000
hexley 0:20a27391f6dc 34
hexley 0:20a27391f6dc 35 /* Public Functions ----------------------------------------------------------- */
hexley 0:20a27391f6dc 36 /** @defgroup QEI_Public_Functions QEI Public Functions
hexley 0:20a27391f6dc 37 */
hexley 1:018226f83d80 38
hexley 1:018226f83d80 39 /** QEI hardware interface class
hexley 1:018226f83d80 40 * Requires mbed hardware modification: connect
hexley 1:018226f83d80 41 * encoder PhA to p1.20, and PhB to p1.23.
hexley 1:018226f83d80 42 *
hexley 1:018226f83d80 43 * Example:
hexley 1:018226f83d80 44 * @code
hexley 1:018226f83d80 45 * // Display changes in encoder position and direction
hexley 1:018226f83d80 46 #include "mbed.h"
hexley 1:018226f83d80 47 * #include "qeihw.h"
hexley 1:018226f83d80 48 *
hexley 1:018226f83d80 49 * DigitalOut led1(LED1);
hexley 1:018226f83d80 50 * DigitalOut led3(LED3);
hexley 1:018226f83d80 51 * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE );
hexley 1:018226f83d80 52 *
hexley 1:018226f83d80 53 * int main() {
hexley 1:018226f83d80 54 * int32_t temp, position = 0;
hexley 1:018226f83d80 55 * qei.SetDigiFilter(480UL);
hexley 1:018226f83d80 56 * qei.SetMaxPosition(0xFFFFFFFF);
hexley 1:018226f83d80 57 *
hexley 1:018226f83d80 58 * while(1) {
hexley 1:018226f83d80 59 * while(position == (temp = qei.GetPosition()) );
hexley 1:018226f83d80 60 * position = temp;
hexley 1:018226f83d80 61 * printf("New position = %d.\r\n", temp);
hexley 1:018226f83d80 62 * led1 = qei.Direction() == SET ? 1 : 0;
hexley 1:018226f83d80 63 * led3 = !led1;
hexley 1:018226f83d80 64 * wait(0.1);
hexley 1:018226f83d80 65 * }
hexley 1:018226f83d80 66 * }
hexley 1:018226f83d80 67 * @endcode
hexley 1:018226f83d80 68 */
hexley 1:018226f83d80 69
hexley 0:20a27391f6dc 70 class QEIHW {
hexley 0:20a27391f6dc 71 public:
hexley 0:20a27391f6dc 72
hexley 0:20a27391f6dc 73 /** Create a QEI object and configure it
hexley 0:20a27391f6dc 74 *
hexley 0:20a27391f6dc 75 * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit
hexley 0:20a27391f6dc 76 * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
hexley 0:20a27391f6dc 77 * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
hexley 0:20a27391f6dc 78 * @param _invinx Invert index. When = 1, inverts the sense of the index signal
JojoS 3:9279a8f154c8 79 * @param _crespi Reset Position on Index. When = 1, resets position counter on index signal
hexley 0:20a27391f6dc 80 */
JojoS 3:9279a8f154c8 81 QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx, uint32_t _crespi=0);
hexley 0:20a27391f6dc 82
hexley 0:20a27391f6dc 83 /** Resets value for each type of QEI value, such as velocity, position, etc.
hexley 0:20a27391f6dc 84 *
hexley 0:20a27391f6dc 85 * @param[in] ulResetType QEI Reset Type, should be one of the following:
hexley 0:20a27391f6dc 86 * - QEI_RESET_POS: Reset Position Counter
hexley 0:20a27391f6dc 87 * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
hexley 0:20a27391f6dc 88 * - QEI_RESET_VEL: Reset Velocity
hexley 0:20a27391f6dc 89 * - QEI_RESET_IDX: Reset Index Counter
hexley 0:20a27391f6dc 90 */
hexley 0:20a27391f6dc 91 void Reset(uint32_t ulResetType);
hexley 0:20a27391f6dc 92
hexley 0:20a27391f6dc 93 /** Powers down the QEI block, returns pins to GPIO mode
hexley 0:20a27391f6dc 94 *
hexley 0:20a27391f6dc 95 */
hexley 0:20a27391f6dc 96 void DeInit();
hexley 0:20a27391f6dc 97
hexley 0:20a27391f6dc 98 /** Report direction (QEISTAT bit DIR)
hexley 0:20a27391f6dc 99 *
hexley 0:20a27391f6dc 100 * @return State of the DIR bit (SET or RESET)
hexley 0:20a27391f6dc 101 */
hexley 0:20a27391f6dc 102 FlagStatus Direction();
hexley 0:20a27391f6dc 103
hexley 0:20a27391f6dc 104 /**
hexley 0:20a27391f6dc 105 * @brief Get current position value in QEI peripheral
hexley 0:20a27391f6dc 106 *
hexley 0:20a27391f6dc 107 * @return Current position value of QEI peripheral
hexley 0:20a27391f6dc 108 */
hexley 0:20a27391f6dc 109 uint32_t GetPosition();
hexley 0:20a27391f6dc 110
hexley 0:20a27391f6dc 111 /** Set max position value for QEI peripheral
hexley 0:20a27391f6dc 112 *
hexley 0:20a27391f6dc 113 * @param[in] ulMaxPos Max position value to set
hexley 0:20a27391f6dc 114 * @return None
hexley 0:20a27391f6dc 115 */
hexley 0:20a27391f6dc 116 void SetMaxPosition(uint32_t ulMaxPos);
hexley 0:20a27391f6dc 117
hexley 0:20a27391f6dc 118 /** Set position compare value for QEI peripheral
hexley 0:20a27391f6dc 119 * @param[in] bPosCompCh Compare Position channel, should be:
hexley 0:20a27391f6dc 120 * - QEI_COMPPOS_CH_0: QEI compare position channel 0
hexley 0:20a27391f6dc 121 * - QEI_COMPPOS_CH_1: QEI compare position channel 1
hexley 0:20a27391f6dc 122 * - QEI_COMPPOS_CH_2: QEI compare position channel 2
hexley 0:20a27391f6dc 123 * @param[in] ulPosComp Compare Position value to set
hexley 0:20a27391f6dc 124 * @return None
hexley 0:20a27391f6dc 125 */
hexley 0:20a27391f6dc 126 void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp);
hexley 0:20a27391f6dc 127
hexley 0:20a27391f6dc 128 /** Get current index counter of QEI peripheral
hexley 0:20a27391f6dc 129 *
hexley 0:20a27391f6dc 130 * @return Current value of QEI index counter
hexley 0:20a27391f6dc 131 */
hexley 0:20a27391f6dc 132 uint32_t GetIndex();
hexley 0:20a27391f6dc 133
hexley 0:20a27391f6dc 134 /** Set value for index compare in QEI peripheral
hexley 0:20a27391f6dc 135 * @param[in] ulIndexComp Compare Index Value to set
hexley 0:20a27391f6dc 136 * @return None
hexley 0:20a27391f6dc 137 */
hexley 0:20a27391f6dc 138 void SetIndexComp( uint32_t ulIndexComp);
hexley 0:20a27391f6dc 139
hexley 0:20a27391f6dc 140 /** Set Velocity timer reload value
hexley 0:20a27391f6dc 141 *
hexley 0:20a27391f6dc 142 * @param[in] ulReloadValue Velocity timer reload count
hexley 0:20a27391f6dc 143 * @return None
hexley 0:20a27391f6dc 144 */
hexley 0:20a27391f6dc 145 void SetVelocityTimerReload( uint32_t ulReloadValue);
hexley 0:20a27391f6dc 146
hexley 0:20a27391f6dc 147 /** Set Velocity timer reload value in microseconds
hexley 0:20a27391f6dc 148 *
hexley 0:20a27391f6dc 149 * @param[in] ulReloadValue Velocity timer reload count
hexley 0:20a27391f6dc 150 * @return None
hexley 0:20a27391f6dc 151 */
hexley 0:20a27391f6dc 152 void SetVelocityTimerReload_us( uint32_t ulReloadValue);
hexley 0:20a27391f6dc 153
hexley 0:20a27391f6dc 154 /** Get current timer counter in QEI peripheral
hexley 0:20a27391f6dc 155 *
hexley 0:20a27391f6dc 156 * @return Current timer counter in QEI peripheral
hexley 0:20a27391f6dc 157 */
hexley 0:20a27391f6dc 158 uint32_t GetTimer();
hexley 0:20a27391f6dc 159
hexley 0:20a27391f6dc 160 /** Get current velocity pulse counter in current time period
hexley 0:20a27391f6dc 161 *
hexley 0:20a27391f6dc 162 * @return Current velocity pulse counter value
hexley 0:20a27391f6dc 163 */
hexley 0:20a27391f6dc 164 uint32_t GetVelocity();
hexley 0:20a27391f6dc 165
hexley 0:20a27391f6dc 166 /** Get the most recently measured velocity of the QEI. When
hexley 0:20a27391f6dc 167 * the Velocity timer in QEI is over-flow, the current velocity
hexley 0:20a27391f6dc 168 * value will be loaded into Velocity Capture register.
hexley 0:20a27391f6dc 169 *
hexley 0:20a27391f6dc 170 * @return The most recently measured velocity value
hexley 0:20a27391f6dc 171 */
hexley 0:20a27391f6dc 172 uint32_t GetVelocityCap();
hexley 0:20a27391f6dc 173
hexley 0:20a27391f6dc 174 /** Set Velocity Compare value for QEI peripheral
hexley 0:20a27391f6dc 175 *
hexley 0:20a27391f6dc 176 * @param[in] ulVelComp Compare Velocity value to set
hexley 0:20a27391f6dc 177 * @return None
hexley 0:20a27391f6dc 178 */
hexley 0:20a27391f6dc 179 void SetVelocityComp( uint32_t ulVelComp);
hexley 0:20a27391f6dc 180
hexley 0:20a27391f6dc 181 /** Set value of sampling count for the digital filter in
hexley 0:20a27391f6dc 182 * QEI peripheral
hexley 0:20a27391f6dc 183 *
hexley 0:20a27391f6dc 184 * @param[in] ulSamplingPulse Value of sampling count to set
hexley 0:20a27391f6dc 185 * @return None
hexley 0:20a27391f6dc 186 */
hexley 0:20a27391f6dc 187 void SetDigiFilter( uint32_t ulSamplingPulse);
hexley 0:20a27391f6dc 188
hexley 0:20a27391f6dc 189 /** Check whether if specified interrupt flag status in QEI
hexley 0:20a27391f6dc 190 * peripheral is set or not
hexley 0:20a27391f6dc 191 *
hexley 0:20a27391f6dc 192 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 193 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 194 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 195 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 196 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 197 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 198 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 199 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 200 current position interrupt
hexley 0:20a27391f6dc 201 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 202 current position interrupt
hexley 0:20a27391f6dc 203 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 204 current position interrupt
hexley 0:20a27391f6dc 205 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 206 index count interrupt
hexley 0:20a27391f6dc 207 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 208 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 209 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 210 * @return New State of specified interrupt flag status (SET or RESET)
hexley 0:20a27391f6dc 211 */
hexley 0:20a27391f6dc 212 FlagStatus GetIntStatus( uint32_t ulIntType);
hexley 0:20a27391f6dc 213
hexley 0:20a27391f6dc 214 /** Enable/Disable specified interrupt in QEI peripheral
hexley 0:20a27391f6dc 215 *
hexley 0:20a27391f6dc 216 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 217 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 218 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 219 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 220 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 221 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 222 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 223 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 224 * current position interrupt
hexley 0:20a27391f6dc 225 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 226 * current position interrupt
hexley 0:20a27391f6dc 227 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 228 * current position interrupt
hexley 0:20a27391f6dc 229 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 230 * index count interrupt
hexley 0:20a27391f6dc 231 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 232 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 233 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 234 * @param[in] NewState New function state, should be:
hexley 0:20a27391f6dc 235 * - DISABLE
hexley 0:20a27391f6dc 236 * - ENABLE
hexley 0:20a27391f6dc 237 * @return None
hexley 0:20a27391f6dc 238 */
hexley 0:20a27391f6dc 239 void IntCmd( uint32_t ulIntType, FunctionalState NewState);
hexley 0:20a27391f6dc 240
hexley 0:20a27391f6dc 241 /** Asserts specified interrupt in QEI peripheral
hexley 0:20a27391f6dc 242 *
hexley 0:20a27391f6dc 243 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 244 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 245 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 246 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 247 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 248 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 249 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 250 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 251 current position interrupt
hexley 0:20a27391f6dc 252 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 253 current position interrupt
hexley 0:20a27391f6dc 254 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 255 current position interrupt
hexley 0:20a27391f6dc 256 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 257 index count interrupt
hexley 0:20a27391f6dc 258 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 259 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 260 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 261 * @return None
hexley 0:20a27391f6dc 262 */
hexley 0:20a27391f6dc 263 void IntSet( uint32_t ulIntType);
hexley 0:20a27391f6dc 264
hexley 0:20a27391f6dc 265 /** De-asserts specified interrupt (pending) in QEI peripheral
hexley 0:20a27391f6dc 266 *
hexley 0:20a27391f6dc 267 * @param[in] ulIntType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 268 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 269 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 270 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 271 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 272 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 273 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 274 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 275 current position interrupt
hexley 0:20a27391f6dc 276 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 277 current position interrupt
hexley 0:20a27391f6dc 278 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 279 current position interrupt
hexley 0:20a27391f6dc 280 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 281 index count interrupt
hexley 0:20a27391f6dc 282 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 283 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 284 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 285 * @return None
hexley 0:20a27391f6dc 286 */
hexley 0:20a27391f6dc 287 void IntClear( uint32_t ulIntType);
hexley 0:20a27391f6dc 288
hexley 0:20a27391f6dc 289 /** Append interrupt handler for specific QEI interrupt source
hexley 0:20a27391f6dc 290 *
hexley 0:20a27391f6dc 291 * @param[in] ulISRType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 292 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 293 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 294 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 295 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 296 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 297 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 298 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 299 * current position interrupt
hexley 0:20a27391f6dc 300 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 301 * current position interrupt
hexley 0:20a27391f6dc 302 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 303 * current position interrupt
hexley 0:20a27391f6dc 304 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 305 * index count interrupt
hexley 0:20a27391f6dc 306 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 307 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 308 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 309 *
hexley 0:20a27391f6dc 310 * @return none
hexley 0:20a27391f6dc 311 */
hexley 0:20a27391f6dc 312 void AppendISR(uint32_t ulISRType, void(*fptr)(void));
hexley 0:20a27391f6dc 313
hexley 0:20a27391f6dc 314 /** Unappend interrupt handler for specific QEI interrupt source
hexley 0:20a27391f6dc 315 *
hexley 0:20a27391f6dc 316 * @param[in] ulISRType Interrupt Flag Status type, should be:
hexley 0:20a27391f6dc 317 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
hexley 0:20a27391f6dc 318 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
hexley 0:20a27391f6dc 319 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
hexley 0:20a27391f6dc 320 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
hexley 0:20a27391f6dc 321 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
hexley 0:20a27391f6dc 322 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
hexley 0:20a27391f6dc 323 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
hexley 0:20a27391f6dc 324 * current position interrupt
hexley 0:20a27391f6dc 325 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
hexley 0:20a27391f6dc 326 * current position interrupt
hexley 0:20a27391f6dc 327 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
hexley 0:20a27391f6dc 328 * current position interrupt
hexley 0:20a27391f6dc 329 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
hexley 0:20a27391f6dc 330 * index count interrupt
hexley 0:20a27391f6dc 331 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
hexley 0:20a27391f6dc 332 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
hexley 0:20a27391f6dc 333 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
hexley 0:20a27391f6dc 334 *
hexley 0:20a27391f6dc 335 * @return none
hexley 0:20a27391f6dc 336 */
hexley 0:20a27391f6dc 337 void UnAppendISR(uint32_t ulISRType);
hexley 0:20a27391f6dc 338
hexley 0:20a27391f6dc 339
hexley 0:20a27391f6dc 340 /**
hexley 0:20a27391f6dc 341 * @brief Calculates the actual velocity in RPM passed via velocity
hexley 0:20a27391f6dc 342 * capture value and Pulse Per Revolution (of the encoder) value
hexley 0:20a27391f6dc 343 * parameter input.
hexley 0:20a27391f6dc 344 *
hexley 0:20a27391f6dc 345 * @param[in] ulVelCapValue Velocity capture input value that can
hexley 0:20a27391f6dc 346 * be got from QEI_GetVelocityCap() function
hexley 0:20a27391f6dc 347 * @param[in] ulPPR Pulse per round of encoder
hexley 0:20a27391f6dc 348 * @return The actual value of velocity in RPM (Revolutions per minute)
hexley 0:20a27391f6dc 349 */
hexley 0:20a27391f6dc 350 uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR);
hexley 0:20a27391f6dc 351
hexley 0:20a27391f6dc 352
hexley 0:20a27391f6dc 353 /* Public Macros -------------------------------------------------------------- */
hexley 0:20a27391f6dc 354 /* QEI Reset types */
hexley 0:20a27391f6dc 355 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
hexley 0:20a27391f6dc 356 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
hexley 0:20a27391f6dc 357 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
hexley 0:20a27391f6dc 358 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
hexley 0:20a27391f6dc 359
hexley 0:20a27391f6dc 360 /* QEI Direction Invert Type Option */
hexley 0:20a27391f6dc 361 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
hexley 0:20a27391f6dc 362 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
hexley 0:20a27391f6dc 363
hexley 0:20a27391f6dc 364 /* QEI Signal Mode Option */
hexley 0:20a27391f6dc 365 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
hexley 0:20a27391f6dc 366 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
hexley 0:20a27391f6dc 367
hexley 0:20a27391f6dc 368 /* QEI Capture Mode Option */
hexley 0:20a27391f6dc 369 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
hexley 0:20a27391f6dc 370 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
hexley 0:20a27391f6dc 371
hexley 0:20a27391f6dc 372 /* QEI Invert Index Signal Option */
hexley 0:20a27391f6dc 373 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
hexley 0:20a27391f6dc 374 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
hexley 0:20a27391f6dc 375
hexley 0:20a27391f6dc 376 /* QEI timer reload option */
hexley 0:20a27391f6dc 377 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
hexley 0:20a27391f6dc 378 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
hexley 0:20a27391f6dc 379
hexley 0:20a27391f6dc 380 /* QEI Flag Status type */
hexley 0:20a27391f6dc 381 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
hexley 0:20a27391f6dc 382
hexley 0:20a27391f6dc 383 /* QEI Compare Position channel option */
hexley 0:20a27391f6dc 384 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
hexley 0:20a27391f6dc 385 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
hexley 0:20a27391f6dc 386 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
hexley 0:20a27391f6dc 387
hexley 0:20a27391f6dc 388 /* QEI interrupt flag type */
hexley 0:20a27391f6dc 389 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
hexley 0:20a27391f6dc 390 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
hexley 0:20a27391f6dc 391 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
hexley 0:20a27391f6dc 392 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
hexley 0:20a27391f6dc 393 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
hexley 0:20a27391f6dc 394 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
hexley 0:20a27391f6dc 395 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
hexley 0:20a27391f6dc 396 current position interrupt */
hexley 0:20a27391f6dc 397 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
hexley 0:20a27391f6dc 398 current position interrupt */
hexley 0:20a27391f6dc 399 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
hexley 0:20a27391f6dc 400 current position interrupt */
hexley 0:20a27391f6dc 401 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
hexley 0:20a27391f6dc 402 index count interrupt */
hexley 0:20a27391f6dc 403 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
hexley 0:20a27391f6dc 404 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
hexley 0:20a27391f6dc 405 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
hexley 0:20a27391f6dc 406
hexley 0:20a27391f6dc 407 /* QEI Process position reporting options */
hexley 0:20a27391f6dc 408 #define QEI_PROCESS_OPERATE 0;
hexley 0:20a27391f6dc 409 #define QEI_PROCESS_RESET 1;
hexley 0:20a27391f6dc 410 #define QEI_PROCESS_INCREMENTAL 0;
hexley 0:20a27391f6dc 411 #define QEI_PROCESS_ACCUMULATE 1;
hexley 0:20a27391f6dc 412 #define QEI_PROCESS_LINEAR 0;
hexley 0:20a27391f6dc 413 #define QEI_PROCESS_WEIGHTED 1;
hexley 0:20a27391f6dc 414
hexley 0:20a27391f6dc 415 private:
hexley 0:20a27391f6dc 416 static void _Qeiisr(void);
hexley 0:20a27391f6dc 417 void Qeiisr(void);
hexley 0:20a27391f6dc 418 static QEIHW *instance;
hexley 0:20a27391f6dc 419
JojoS 3:9279a8f154c8 420 #ifdef TARGET_LPC1768
hexley 0:20a27391f6dc 421 void(*_qei_isr[13])();
JojoS 3:9279a8f154c8 422 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 423 void(*_qei_isr[16])();
JojoS 3:9279a8f154c8 424 #endif
hexley 0:20a27391f6dc 425
hexley 0:20a27391f6dc 426 /* Private Macros ------------------------------------------------------------- */
hexley 0:20a27391f6dc 427 /* --------------------- BIT DEFINITIONS -------------------------------------- */
hexley 0:20a27391f6dc 428 /* Quadrature Encoder Interface Control Register Definition --------------------- */
hexley 0:20a27391f6dc 429 /*********************************************************************//**
JojoS 3:9279a8f154c8 430 * Macro defines for QEI Control register LPC1768, LPC4088
hexley 0:20a27391f6dc 431 **********************************************************************/
hexley 0:20a27391f6dc 432 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
JojoS 3:9279a8f154c8 433 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
hexley 0:20a27391f6dc 434 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
hexley 0:20a27391f6dc 435 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
JojoS 3:9279a8f154c8 436 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
hexley 0:20a27391f6dc 437
hexley 0:20a27391f6dc 438 /*********************************************************************//**
hexley 0:20a27391f6dc 439 * Macro defines for QEI Configuration register
hexley 0:20a27391f6dc 440 **********************************************************************/
JojoS 3:9279a8f154c8 441 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
hexley 0:20a27391f6dc 442 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
hexley 0:20a27391f6dc 443 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
JojoS 3:9279a8f154c8 444 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
JojoS 3:9279a8f154c8 445 #ifdef TARGET_LPC1768
hexley 0:20a27391f6dc 446 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
JojoS 3:9279a8f154c8 447 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 448 #define QEI_CONF_CRESPI ((uint32_t)(1<<4)) /**< reset ounter on index */
JojoS 3:9279a8f154c8 449 #define QEI_CONF_BITMASK ((uint32_t)(0x1F)) /**< QEI Configuration register bit-mask */
JojoS 3:9279a8f154c8 450 #endif
hexley 0:20a27391f6dc 451
hexley 0:20a27391f6dc 452 /*********************************************************************//**
hexley 0:20a27391f6dc 453 * Macro defines for QEI Status register
hexley 0:20a27391f6dc 454 **********************************************************************/
hexley 0:20a27391f6dc 455 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
hexley 0:20a27391f6dc 456 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
hexley 0:20a27391f6dc 457
hexley 0:20a27391f6dc 458 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
hexley 0:20a27391f6dc 459 /*********************************************************************//**
hexley 0:20a27391f6dc 460 * Macro defines for QEI Interrupt Status register
hexley 0:20a27391f6dc 461 **********************************************************************/
JojoS 3:9279a8f154c8 462 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 463 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 464 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 465 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 466 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 467 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 468 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 469 current position */
JojoS 3:9279a8f154c8 470 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 471 current position */
JojoS 3:9279a8f154c8 472 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 473 current position */
JojoS 3:9279a8f154c8 474 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 475 index count */
JojoS 3:9279a8f154c8 476 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
JojoS 3:9279a8f154c8 477 both the POS0_Int bit is set and the REV_Int is set */
JojoS 3:9279a8f154c8 478 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
JojoS 3:9279a8f154c8 479 both the POS1_Int bit is set and the REV_Int is set */
JojoS 3:9279a8f154c8 480 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
JojoS 3:9279a8f154c8 481 both the POS2_Int bit is set and the REV_Int is set */
JojoS 3:9279a8f154c8 482 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 483 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 484 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 485 #define QEI_INTSTAT_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 486 #define QEI_INTSTAT_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 487 #define QEI_INTSTAT_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 488 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 489 #define QEI_INTSTAT_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 490 #endif
hexley 0:20a27391f6dc 491
hexley 0:20a27391f6dc 492 /*********************************************************************//**
hexley 0:20a27391f6dc 493 * Macro defines for QEI Interrupt Set register
hexley 0:20a27391f6dc 494 **********************************************************************/
JojoS 3:9279a8f154c8 495 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 496 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 497 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 498 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 499 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 500 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 501 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 502 current position */
JojoS 3:9279a8f154c8 503 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 504 current position */
JojoS 3:9279a8f154c8 505 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 506 current position */
JojoS 3:9279a8f154c8 507 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 508 index count */
JojoS 3:9279a8f154c8 509 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
JojoS 3:9279a8f154c8 510 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
JojoS 3:9279a8f154c8 511 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
JojoS 3:9279a8f154c8 512 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 513 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 514 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 515 #define QEI_INTSET_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 516 #define QEI_INTSET_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 517 #define QEI_INTSET_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 518 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 519 #define QEI_INTSET_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 520 #endif
JojoS 3:9279a8f154c8 521
hexley 0:20a27391f6dc 522
hexley 0:20a27391f6dc 523 /*********************************************************************//**
hexley 0:20a27391f6dc 524 * Macro defines for QEI Interrupt Clear register
hexley 0:20a27391f6dc 525 **********************************************************************/
JojoS 3:9279a8f154c8 526 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 527 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 528 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 529 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 530 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 531 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 532 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 533 current position */
JojoS 3:9279a8f154c8 534 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 535 current position */
JojoS 3:9279a8f154c8 536 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 537 current position */
JojoS 3:9279a8f154c8 538 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 539 index count */
JojoS 3:9279a8f154c8 540 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
JojoS 3:9279a8f154c8 541 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
JojoS 3:9279a8f154c8 542 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
JojoS 3:9279a8f154c8 543 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 544 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 545 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 546 #define QEI_INTCLR_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 547 #define QEI_INTCLR_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 548 #define QEI_INTCLR_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 549 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 550 #define QEI_INTCLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 551 #endif
hexley 0:20a27391f6dc 552
hexley 0:20a27391f6dc 553 /*********************************************************************//**
hexley 0:20a27391f6dc 554 * Macro defines for QEI Interrupt Enable register
hexley 0:20a27391f6dc 555 **********************************************************************/
JojoS 3:9279a8f154c8 556 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 557 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 558 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 559 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 560 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 561 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 562 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 563 current position */
JojoS 3:9279a8f154c8 564 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 565 current position */
JojoS 3:9279a8f154c8 566 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 567 current position */
JojoS 3:9279a8f154c8 568 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 569 index count */
JojoS 3:9279a8f154c8 570 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
JojoS 3:9279a8f154c8 571 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
JojoS 3:9279a8f154c8 572 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
JojoS 3:9279a8f154c8 573 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 574 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 575 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 576 #define QEI_INTEN_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 577 #define QEI_INTEN_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 578 #define QEI_INTEN_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 579 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 580 #define QEI_INTEN_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 581 #endif
hexley 0:20a27391f6dc 582
hexley 0:20a27391f6dc 583 /*********************************************************************//**
hexley 0:20a27391f6dc 584 * Macro defines for QEI Interrupt Enable Set register
hexley 0:20a27391f6dc 585 **********************************************************************/
JojoS 3:9279a8f154c8 586 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 587 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 588 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 589 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 590 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 591 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 592 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 593 current position */
JojoS 3:9279a8f154c8 594 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 595 current position */
JojoS 3:9279a8f154c8 596 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 597 current position */
JojoS 3:9279a8f154c8 598 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 599 index count */
JojoS 3:9279a8f154c8 600 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
JojoS 3:9279a8f154c8 601 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
JojoS 3:9279a8f154c8 602 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
JojoS 3:9279a8f154c8 603 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 604 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 605 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 606 #define QEI_IESET_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 607 #define QEI_IESET_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 608 #define QEI_IESET_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 609 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 610 #define QEI_IESET_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 611 #endif
hexley 0:20a27391f6dc 612
hexley 0:20a27391f6dc 613 /*********************************************************************//**
hexley 0:20a27391f6dc 614 * Macro defines for QEI Interrupt Enable Clear register
hexley 0:20a27391f6dc 615 **********************************************************************/
JojoS 3:9279a8f154c8 616 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
JojoS 3:9279a8f154c8 617 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
JojoS 3:9279a8f154c8 618 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
JojoS 3:9279a8f154c8 619 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
JojoS 3:9279a8f154c8 620 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
JojoS 3:9279a8f154c8 621 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
JojoS 3:9279a8f154c8 622 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
JojoS 3:9279a8f154c8 623 current position */
JojoS 3:9279a8f154c8 624 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
JojoS 3:9279a8f154c8 625 current position */
JojoS 3:9279a8f154c8 626 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
JojoS 3:9279a8f154c8 627 current position */
JojoS 3:9279a8f154c8 628 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
JojoS 3:9279a8f154c8 629 index count */
JojoS 3:9279a8f154c8 630 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
JojoS 3:9279a8f154c8 631 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
JojoS 3:9279a8f154c8 632 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
JojoS 3:9279a8f154c8 633 #ifdef TARGET_LPC1768
JojoS 3:9279a8f154c8 634 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 635 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 636 #define QEI_IECLR_REV1_Int ((uint32_t)(1<<13)) /**< Indicates that the index compare 1value is equal to the current index count. */
JojoS 3:9279a8f154c8 637 #define QEI_IECLR_REV2_Int ((uint32_t)(1<<14)) /**< Indicates that the index compare 2 value is equal to the current index count. */
JojoS 3:9279a8f154c8 638 #define QEI_IECLR_MAXPOS_INT_Int ((uint32_t)(1<<15)) /**< Indicates that the current position count goes through the MAXPOS value to zero in
JojoS 3:9279a8f154c8 639 the forward direction, or through zero to MAXPOS in the reverse direction. */
JojoS 3:9279a8f154c8 640 #define QEI_IECLR_BITMASK ((uint32_t)(0xFFFF)) /**< QEI Interrupt Status register bit-mask */
JojoS 3:9279a8f154c8 641 #endif
JojoS 3:9279a8f154c8 642
hexley 0:20a27391f6dc 643
hexley 0:20a27391f6dc 644 /*********************************************************************//**
hexley 0:20a27391f6dc 645 * Macro defines for PCONP register QEI-related bits
hexley 0:20a27391f6dc 646 **********************************************************************/
JojoS 3:9279a8f154c8 647 #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
JojoS 3:9279a8f154c8 648 #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
hexley 0:20a27391f6dc 649
hexley 0:20a27391f6dc 650 /*********************************************************************//**
hexley 0:20a27391f6dc 651 * Macro defines for PCLKSELx register QEI-related bits
hexley 0:20a27391f6dc 652 **********************************************************************/
hexley 0:20a27391f6dc 653 #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */
hexley 0:20a27391f6dc 654 #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
hexley 0:20a27391f6dc 655 #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
hexley 0:20a27391f6dc 656 #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
JojoS 3:9279a8f154c8 657 #ifdef TARGET_LPC1768
hexley 0:20a27391f6dc 658 #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
JojoS 3:9279a8f154c8 659 #elif TARGET_LPC4088
JojoS 3:9279a8f154c8 660 #define PCLKSEL1_PCLK_QEI_MASK (0x1fUL) /**< PCLK_QEI PCLK_QEI bit field mask */
JojoS 3:9279a8f154c8 661 #endif
JojoS 3:9279a8f154c8 662
hexley 0:20a27391f6dc 663 /*********************************************************************//**
JojoS 3:9279a8f154c8 664 * Macro defines for PINSEL3 register QEI-related bits (LPC1768 only)
hexley 0:20a27391f6dc 665 **********************************************************************/
JojoS 3:9279a8f154c8 666 #ifdef TARGET_LPC1768
hexley 0:20a27391f6dc 667 #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
hexley 0:20a27391f6dc 668 #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
hexley 0:20a27391f6dc 669 #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
hexley 0:20a27391f6dc 670 #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */
hexley 0:20a27391f6dc 671 #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */
hexley 0:20a27391f6dc 672 #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
hexley 0:20a27391f6dc 673
hexley 0:20a27391f6dc 674 /*********************************************************************//**
JojoS 3:9279a8f154c8 675 * Macro defines for PINMODE3 register QEI-related bits(LPC1768 only)
hexley 0:20a27391f6dc 676 **********************************************************************/
hexley 0:20a27391f6dc 677 #define PIN_PULL_UP 0UL
hexley 0:20a27391f6dc 678 #define PIN_REPEATER 1UL
hexley 0:20a27391f6dc 679 #define PIN_NORESISTOR 2UL
hexley 0:20a27391f6dc 680 #define PIN_PULL_DOWN 3UL
hexley 0:20a27391f6dc 681
hexley 0:20a27391f6dc 682 #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */
hexley 0:20a27391f6dc 683 #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */
hexley 0:20a27391f6dc 684 #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */
hexley 0:20a27391f6dc 685
hexley 0:20a27391f6dc 686 #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */
hexley 0:20a27391f6dc 687 #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */
hexley 0:20a27391f6dc 688 #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */
hexley 0:20a27391f6dc 689
hexley 0:20a27391f6dc 690 #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
hexley 0:20a27391f6dc 691 #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
hexley 0:20a27391f6dc 692 #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
JojoS 3:9279a8f154c8 693 #endif
hexley 0:20a27391f6dc 694 };
hexley 0:20a27391f6dc 695
hexley 0:20a27391f6dc 696
hexley 0:20a27391f6dc 697 #endif /* MBED_QEI_H */
hexley 0:20a27391f6dc 698 /* --------------------------------- End Of File ------------------------------ */