Revision 0:7088bc4c9949, committed 2018-05-31

Comitter:

Joelpallent

Date:

Thu May 31 19:30:01 2018 +0000

Commit message:

c

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ADC.c	Thu May 31 19:30:01 2018 +0000
@@ -0,0 +1,24 @@
+#include "ADC.h"
+
+
+
+void init_ADC(void)
+{
+    RCC->AHB1ENR|=RCC_AHB1ENR_GPIOCEN;  //GPIOC clock enable
+    ADC_input_port->MODER|=(3u<<(2*ADC_input_pin)); //ADC input pin is analogue mode
+    
+    RCC->APB2ENR|=RCC_APB2ENR_ADC1EN;       //ADC clock enable
+    ADC1->SQR1&=~ADC_SQR1_L;                        //set number of conversions per sequence to 1
+    ADC1->SQR3&=~ADC_SQR3_SQ1;                  //clear channel select bits
+    ADC1->SQR3|=ADC_Channel;                        //set channel
+    ADC1->CR2|=ADC_CR2_ADON;                        //enable ADC
+    
+}
+
+
+unsigned short read_adc(void)
+{
+    ADC1->CR2|=ADC_CR2_SWSTART;         //start ADC conversion
+    while((ADC1->SR&ADC_SR_EOC)==0);    //wait for ADC conversion complete
+    return ADC1->DR;                    //return converted value
+}
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/ADC.h	Thu May 31 19:30:01 2018 +0000
@@ -0,0 +1,12 @@
+#ifndef _ADC_H
+#define _ADC_H
+#include <stm32f4xx.h>
+
+#define ADC_input_port      GPIOC
+#define ADC_input_pin           0
+#define ADC_Channel             10
+
+void init_ADC(void);
+unsigned short read_adc(void);
+#endif 
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/PLL_Config.c	Thu May 31 19:30:01 2018 +0000
@@ -0,0 +1,54 @@
+#include <stm32f4xx.h>
+
+void PLL_Config(void)
+{
+    
+
+//*******************************************************************************
+//*            PLL (clocked by HSI) used as System clock source                 *
+//*                         By Stuart MacVeigh                                  *
+//*******************************************************************************
+
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;  //enable power interface clock source
+    PWR->CR |= PWR_CR_VOS;
+
+    
+        #define PLL_N   180         //SYSTEM CLOCK SPEED (FCY (MHz))
+        #define HSI     16000000    //INTERAL OSC FREQUENCY
+        
+        #define PLL_M   (HSI/2000000)       //Fcy = Fxtal x PLL_N/(PLL_P x PLL_M)
+        #define PLL_P   2
+        #define PLL_Q   7
+    // HCLK = SYSCLK / 1
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;        //CORE CLOCK = 180MHZ
+    
+    // PCLK2 = HCLK / 2
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV4;       //PERIPHERAL CLOCK 2 = 180MHZ/4 = 45MHZ, THIS IS BECAUSE THE SPI MODULES (AND POSSIBLY OTHERS) DO NOT OPERATE PROPERLY WHEN PCLK > 42MHZ
+    
+    // PCLK1 = HCLK / 4
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;       //PERIPHERAL CLOCK 1 = 180MHZ/4 = 45MHZ, THIS IS BECAUSE THE SPI MODULES (AND POSSIBLY OTHERS) DO NOT OPERATE PROPERLY WHEN PCLK > 42MHZ
+
+    // Configure the main PLL
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
+
+    // Enable the main PLL
+    RCC->CR |= RCC_CR_PLLON;
+
+    // Wait till the main PLL is ready
+    while(!(RCC->CR & RCC_CR_PLLRDY));
+   
+    // Configure Flash prefetch, Instruction cache, Data cache and wait state
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+    // Select the main PLL as system clock source
+    RCC->CFGR &=~ RCC_CFGR_SW;
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    // Wait till the main PLL is used as system clock source
+    while ((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    
+//******************************************************************************
+//*            END PLL (CLOCKED BY HSI) SETUP CODE                             *
+//******************************************************************************
+    
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TEST.cpp	Thu May 31 19:30:01 2018 +0000
@@ -0,0 +1,31 @@
+#include <stm32f4xx.h>
+#include <stdio.h>
+#include "ADC.h"
+#include "PLL_Config.c"
+#include "ADC.c"
+
+
+float adc_data_f = 0;
+unsigned short ADC_DATA = 0;
+
+int main(void)
+{
+    
+    //PLL_Config();
+    SystemCoreClockUpdate();
+    
+    init_ADC();     //config ADC
+    
+    while(1)
+    {
+        ADC_DATA=read_adc();            //read value from ADC
+        
+        adc_data_f=(float)ADC_DATA;
+        adc_data_f/=1000.0f;
+        adc_data_f = adc_data_f*0.80513;
+        printf("voltage = %0.2fv\n " , adc_data_f );
+        
+        
+    }
+    
+}
\ No newline at end of file

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Thu May 31 19:30:01 2018 +0000
@@ -0,0 +1,1 @@
+https://os.mbed.com/users/mbed_official/code/mbed/builds/5aab5a7997ee
\ No newline at end of file