Joel Pallent / Mbed 2 deprecated Elec241-adc

c

Dependencies:   mbed

PLL_Config.c@0:7088bc4c9949, 2018-05-31 (annotated)

Committer:
Joelpallent
Date:
Thu May 31 19:30:01 2018 +0000
Revision:
0:7088bc4c9949
c

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Joelpallent 0:7088bc4c9949 1 #include <stm32f4xx.h>
Joelpallent 0:7088bc4c9949 2
Joelpallent 0:7088bc4c9949 3 void PLL_Config(void)
Joelpallent 0:7088bc4c9949 4 {
Joelpallent 0:7088bc4c9949 5
Joelpallent 0:7088bc4c9949 6
Joelpallent 0:7088bc4c9949 7 //*******************************************************************************
Joelpallent 0:7088bc4c9949 8 //* PLL (clocked by HSI) used as System clock source *
Joelpallent 0:7088bc4c9949 9 //* By Stuart MacVeigh *
Joelpallent 0:7088bc4c9949 10 //*******************************************************************************
Joelpallent 0:7088bc4c9949 11
Joelpallent 0:7088bc4c9949 12 RCC->APB1ENR |= RCC_APB1ENR_PWREN; //enable power interface clock source
Joelpallent 0:7088bc4c9949 13 PWR->CR |= PWR_CR_VOS;
Joelpallent 0:7088bc4c9949 14
Joelpallent 0:7088bc4c9949 15
Joelpallent 0:7088bc4c9949 16 #define PLL_N 180 //SYSTEM CLOCK SPEED (FCY (MHz))
Joelpallent 0:7088bc4c9949 17 #define HSI 16000000 //INTERAL OSC FREQUENCY
Joelpallent 0:7088bc4c9949 18
Joelpallent 0:7088bc4c9949 19 #define PLL_M (HSI/2000000) //Fcy = Fxtal x PLL_N/(PLL_P x PLL_M)
Joelpallent 0:7088bc4c9949 20 #define PLL_P 2
Joelpallent 0:7088bc4c9949 21 #define PLL_Q 7
Joelpallent 0:7088bc4c9949 22 // HCLK = SYSCLK / 1
Joelpallent 0:7088bc4c9949 23 RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //CORE CLOCK = 180MHZ
Joelpallent 0:7088bc4c9949 24
Joelpallent 0:7088bc4c9949 25 // PCLK2 = HCLK / 2
Joelpallent 0:7088bc4c9949 26 RCC->CFGR |= RCC_CFGR_PPRE2_DIV4; //PERIPHERAL CLOCK 2 = 180MHZ/4 = 45MHZ, THIS IS BECAUSE THE SPI MODULES (AND POSSIBLY OTHERS) DO NOT OPERATE PROPERLY WHEN PCLK > 42MHZ
Joelpallent 0:7088bc4c9949 27
Joelpallent 0:7088bc4c9949 28 // PCLK1 = HCLK / 4
Joelpallent 0:7088bc4c9949 29 RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; //PERIPHERAL CLOCK 1 = 180MHZ/4 = 45MHZ, THIS IS BECAUSE THE SPI MODULES (AND POSSIBLY OTHERS) DO NOT OPERATE PROPERLY WHEN PCLK > 42MHZ
Joelpallent 0:7088bc4c9949 30
Joelpallent 0:7088bc4c9949 31 // Configure the main PLL
Joelpallent 0:7088bc4c9949 32 RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
Joelpallent 0:7088bc4c9949 33
Joelpallent 0:7088bc4c9949 34 // Enable the main PLL
Joelpallent 0:7088bc4c9949 35 RCC->CR |= RCC_CR_PLLON;
Joelpallent 0:7088bc4c9949 36
Joelpallent 0:7088bc4c9949 37 // Wait till the main PLL is ready
Joelpallent 0:7088bc4c9949 38 while(!(RCC->CR & RCC_CR_PLLRDY));
Joelpallent 0:7088bc4c9949 39
Joelpallent 0:7088bc4c9949 40 // Configure Flash prefetch, Instruction cache, Data cache and wait state
Joelpallent 0:7088bc4c9949 41 FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
Joelpallent 0:7088bc4c9949 42
Joelpallent 0:7088bc4c9949 43 // Select the main PLL as system clock source
Joelpallent 0:7088bc4c9949 44 RCC->CFGR &=~ RCC_CFGR_SW;
Joelpallent 0:7088bc4c9949 45 RCC->CFGR |= RCC_CFGR_SW_PLL;
Joelpallent 0:7088bc4c9949 46
Joelpallent 0:7088bc4c9949 47 // Wait till the main PLL is used as system clock source
Joelpallent 0:7088bc4c9949 48 while ((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
Joelpallent 0:7088bc4c9949 49
Joelpallent 0:7088bc4c9949 50 //******************************************************************************
Joelpallent 0:7088bc4c9949 51 //* END PLL (CLOCKED BY HSI) SETUP CODE *
Joelpallent 0:7088bc4c9949 52 //******************************************************************************
Joelpallent 0:7088bc4c9949 53
Joelpallent 0:7088bc4c9949 54 }