QSPIFBlockDevice.h

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2016 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 #ifndef MBED_QSPIF_BLOCK_DEVICE_H
00017 #define MBED_QSPIF_BLOCK_DEVICE_H
00018 
00019 
00020 #define DEVICE_QSPI 1
00021 
00022 #include <mbed.h>
00023 #include "BlockDevice.h"
00024 #include "QSPI.h"
00025 
00026 #define QSPIF_MAX_REGIONS   4
00027 
00028 class QSPIFBlockDevice : public BlockDevice {
00029 public:
00030     /** Creates a QSPIFBlockDevice on a SPI bus specified by pins
00031      *
00032      *  @param mosi     SPI master out, slave in pin
00033      *  @param miso     SPI master in, slave out pin
00034      *  @param sclk     SPI clock pin
00035      *  @param csel     SPI chip select pin
00036      *  @param freq     Clock speed of the SPI bus (defaults to 40MHz)
00037      */
00038 
00039     /** Creates a QSPIFBlockDevice on an SPI bus specified by pins
00040      *
00041      *  io0-io3 is used to specify the Pins used for Quad SPI mode
00042      *
00043      *  @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
00044      *  @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
00045      *  @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
00046      *  @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
00047      *  @param sclk QSPI Clock pin
00048      *  @param csel QSPI chip select pin
00049      *  @param clock_mode specifies the SPI Clock Polarity mode(Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
00050      *         default value = 0
00051      *  @param freq Clock frequency of the SPI bus (defaults to 40MHz)
00052      *
00053      */
00054     QSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName csel, int clock_mode,
00055                      int freq = 40000000);
00056 
00057     /** Initialize a block device
00058      *
00059      *  @return         0 on success or a negative error code on failure
00060      */
00061     virtual int init();
00062 
00063     /** Deinitialize a block device
00064      *
00065      *  @return         0 on success or a negative error code on failure
00066      */
00067     virtual int deinit();
00068 
00069     /** Read blocks from a block device
00070      *
00071      *  @param buffer   Buffer to write blocks to
00072      *  @param addr     Address of block to begin reading from
00073      *  @param size     Size to read in bytes, must be a multiple of read block size
00074      *  @return         0 on success, negative error code on failure
00075      */
00076     virtual int read(void *buffer, bd_addr_t addr, bd_size_t size);
00077 
00078     /** Program blocks to a block device
00079      *
00080      *  The blocks must have been erased prior to being programmed
00081      *
00082      *  @param buffer   Buffer of data to write to blocks
00083      *  @param addr     Address of block to begin writing to
00084      *  @param size     Size to write in bytes, must be a multiple of program block size
00085      *  @return         0 on success, negative error code on failure
00086      */
00087     virtual int program(const void *buffer, bd_addr_t addr, bd_size_t size);
00088 
00089     /** Erase blocks on a block device
00090      *
00091      *  The state of an erased block is undefined until it has been programmed
00092      *
00093      *  @param addr     Address of block to begin erasing
00094      *  @param size     Size to erase in bytes, must be a multiple of erase block size
00095      *  @return         0 on success, negative error code on failure
00096      */
00097     virtual int erase(bd_addr_t addr, bd_size_t size);
00098 
00099     /** Get the size of a readable block
00100      *
00101      *  @return         Size of a readable block in bytes
00102      */
00103     virtual bd_size_t get_read_size() const;
00104 
00105     /** Get the size of a programable block
00106      *
00107      *  @return         Size of a programable block in bytes
00108      *  @note Must be a multiple of the read size
00109      */
00110     virtual bd_size_t get_program_size() const;
00111 
00112     /** Get the size of a eraseable block
00113      *
00114      *  @return         Size of a eraseable block in bytes
00115      *  @note Must be a multiple of the program size
00116      */
00117     virtual bd_size_t get_erase_size() const;
00118 
00119     /** Get the size of a eraseable block
00120      *
00121      *  @param addr     Address of block queried for erase sector size
00122      *  @return         Size of a eraseable sector in bytes
00123      *  @note Must be a multiple of the program size
00124      */
00125     bd_size_t get_erase_size(bd_addr_t addr);
00126 
00127     /** Get the total size of the underlying device
00128      *
00129      *  @return         Size of the underlying device in bytes
00130      */
00131     virtual bd_size_t size() const;
00132 
00133 private:
00134     // Internal functions
00135 
00136     /********************************/
00137     /*   Calls to QSPI Driver APIs  */
00138     /********************************/
00139     // Send Program => Write command to Driver
00140     qspi_status_t _qspiSendProgramCommand(unsigned int progInstruction, const void *buffer, bd_addr_t addr,
00141                                           bd_size_t *size);
00142 
00143     // Send Read command to Driver
00144     qspi_status_t _qspiSendReadCommand(unsigned int readInstruction, void *buffer, bd_addr_t addr, bd_size_t size);
00145 
00146     // Send Erase => command_transfer command to Driver
00147     qspi_status_t _qspiSendEraseCommand(unsigned int eraseInstruction, bd_addr_t addr, bd_size_t size);
00148 
00149     // Send Generic command_transfer command to Driver
00150     qspi_status_t _qspiSendGeneralCommand(unsigned int instructionint, bd_addr_t addr, const char *tx_buffer,
00151                                           size_t tx_length, const char *rx_buffer, size_t rx_length);
00152 
00153     // Send Bus configure_format command to Driver
00154     qspi_status_t _qspiConfiureFormat(qspi_bus_width_t inst_width, qspi_bus_width_t address_width,
00155                                       qspi_address_size_t address_size, qspi_bus_width_t alt_width, qspi_alt_size_t alt_size, qspi_bus_width_t data_width,
00156                                       int dummy_cycles);
00157 
00158     // Send set_frequency command to Driver
00159     qspi_status_t _qspiSetFrequency(int freq);
00160     /********************************/
00161 
00162 
00163     // Verify registers and Reset Flash Memory
00164     int _resetFlashMem();
00165 
00166     // Configure Write Enable in Status Register
00167     int _setWriteEnable();
00168 
00169     // Wait on status register until write not-in-progress
00170     bool _isMemReady();
00171 
00172 
00173     /* SFDP Detection and Parsing Functions */
00174     /****************************************/
00175     int _sfdpParseSFDPHeaders(uint32_t& basic_table_addr, size_t& basic_table_size,
00176                               uint32_t& sector_map_table_addr, size_t& sector_map_table_size);
00177     int _sfdpParseBasicParamTable(uint32_t basic_table_addr, size_t basic_table_size);
00178     int _sfdpParseSectorMapTable(uint32_t sector_map_table_addr, size_t sector_map_table_size);
00179     int _sfdpDetectBestBusReadMode(uint8_t *basicParamTablePtr, bool& setQuadEnable, bool& isQPIMode,
00180                                    unsigned int& readInst);
00181     int _sfdpSetQuadEnabled(uint8_t *basicParamTablePtr);
00182     int _sfdpSetQPIEnabled(uint8_t *basicParamTablePtr);
00183     int _sfdpDetectPageSize(uint8_t *basicParamTablePtr);
00184     int _sfdpDetectEraseTypesInstAndSize(uint8_t *basicParamTablePtr, unsigned int& erase4KInst,
00185                                          unsigned int *eraseTypeInstArr, unsigned int *eraseTypeSizeArr);
00186 
00187     /* Utilities Functions */
00188     /***********************/
00189     int _utilsFindAddrRegion(int offset);
00190     int _utilsIterateNextLargestEraseType(uint8_t& bitfield, int size, int offset, int boundry);
00191     int _utilsMathPower(int base, int exp);
00192 
00193 private:
00194 
00195     // QSPI Driver Object
00196     QSPI _qspi;
00197     //DigitalOut _cs;
00198     bool is_initialized;
00199     static SingletonPtr<PlatformMutex> _mutex;
00200 
00201     // Command Instructions
00202     unsigned int _readInstruction;
00203     unsigned int _progInstruction;
00204     unsigned int _eraseInstruction;
00205     unsigned int _erase4KInst;
00206     unsigned int _eraseTypeInstArr[4];
00207     unsigned int _eraseTypeSizeArr[4];
00208 
00209     // Sector Regions Map
00210     int _regions_count; //number of regions
00211     int _region_size_bytes[QSPIF_MAX_REGIONS]; //regions size
00212     int _region_high_boundary[QSPIF_MAX_REGIONS]; //region high address offset boundary
00213     uint8_t _region_erase_types[QSPIF_MAX_REGIONS]; //region erase type
00214     int _minCommonEraseType; // minimal common erase size for all regions (-1 if none)
00215     int _minCommonEraseSize; // minimal common erase size for all regions
00216 
00217     int _pageSizeBytes; // Page size - 256 Bytes default
00218     bd_size_t _deviceSizeBytes;
00219 
00220     // Bus speed configuration
00221     qspi_bus_width_t _inst_width; //Bus width for Instruction phase
00222     qspi_bus_width_t _address_width; //Bus width for Address phase
00223     qspi_address_size_t _address_size;
00224     qspi_bus_width_t _alt_width; //Bus width for Alt phase
00225     qspi_alt_size_t _alt_size;
00226     qspi_bus_width_t _data_width; //Bus width for Data phase
00227     int _dummy_and_mode_cycles;
00228 
00229 
00230 };
00231 
00232 #endif