Jasper Lee / mbed_helloworld

change some io settings for TWR-K22F-120M

Dependents:   twr_helloworld

TARGET_NUCLEO_F072RB/stm32f072xb.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:
Jasper_lee
Date:
Tue Dec 23 03:35:08 2014 +0000
Revision:
0:b16d94660a33
change some io setting used in TWR-K22F120M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jasper_lee 0:b16d94660a33 1 /**
Jasper_lee 0:b16d94660a33 2 ******************************************************************************
Jasper_lee 0:b16d94660a33 3 * @file stm32f072xb.h
Jasper_lee 0:b16d94660a33 4 * @author MCD Application Team
Jasper_lee 0:b16d94660a33 5 * @version V2.1.0
Jasper_lee 0:b16d94660a33 6 * @date 03-Oct-2014
Jasper_lee 0:b16d94660a33 7 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
Jasper_lee 0:b16d94660a33 8 *
Jasper_lee 0:b16d94660a33 9 * This file contains:
Jasper_lee 0:b16d94660a33 10 * - Data structures and the address mapping for all peripherals
Jasper_lee 0:b16d94660a33 11 * - Peripheral's registers declarations and bits definition
Jasper_lee 0:b16d94660a33 12 * - Macros to access peripheral’s registers hardware
Jasper_lee 0:b16d94660a33 13 *
Jasper_lee 0:b16d94660a33 14 ******************************************************************************
Jasper_lee 0:b16d94660a33 15 * @attention
Jasper_lee 0:b16d94660a33 16 *
Jasper_lee 0:b16d94660a33 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Jasper_lee 0:b16d94660a33 18 *
Jasper_lee 0:b16d94660a33 19 * Redistribution and use in source and binary forms, with or without modification,
Jasper_lee 0:b16d94660a33 20 * are permitted provided that the following conditions are met:
Jasper_lee 0:b16d94660a33 21 * 1. Redistributions of source code must retain the above copyright notice,
Jasper_lee 0:b16d94660a33 22 * this list of conditions and the following disclaimer.
Jasper_lee 0:b16d94660a33 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Jasper_lee 0:b16d94660a33 24 * this list of conditions and the following disclaimer in the documentation
Jasper_lee 0:b16d94660a33 25 * and/or other materials provided with the distribution.
Jasper_lee 0:b16d94660a33 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Jasper_lee 0:b16d94660a33 27 * may be used to endorse or promote products derived from this software
Jasper_lee 0:b16d94660a33 28 * without specific prior written permission.
Jasper_lee 0:b16d94660a33 29 *
Jasper_lee 0:b16d94660a33 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jasper_lee 0:b16d94660a33 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jasper_lee 0:b16d94660a33 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jasper_lee 0:b16d94660a33 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Jasper_lee 0:b16d94660a33 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Jasper_lee 0:b16d94660a33 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Jasper_lee 0:b16d94660a33 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Jasper_lee 0:b16d94660a33 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Jasper_lee 0:b16d94660a33 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Jasper_lee 0:b16d94660a33 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jasper_lee 0:b16d94660a33 40 *
Jasper_lee 0:b16d94660a33 41 ******************************************************************************
Jasper_lee 0:b16d94660a33 42 */
Jasper_lee 0:b16d94660a33 43
Jasper_lee 0:b16d94660a33 44 /** @addtogroup CMSIS_Device
Jasper_lee 0:b16d94660a33 45 * @{
Jasper_lee 0:b16d94660a33 46 */
Jasper_lee 0:b16d94660a33 47
Jasper_lee 0:b16d94660a33 48 /** @addtogroup stm32f072xb
Jasper_lee 0:b16d94660a33 49 * @{
Jasper_lee 0:b16d94660a33 50 */
Jasper_lee 0:b16d94660a33 51
Jasper_lee 0:b16d94660a33 52 #ifndef __STM32F072xB_H
Jasper_lee 0:b16d94660a33 53 #define __STM32F072xB_H
Jasper_lee 0:b16d94660a33 54
Jasper_lee 0:b16d94660a33 55 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 56 extern "C" {
Jasper_lee 0:b16d94660a33 57 #endif /* __cplusplus */
Jasper_lee 0:b16d94660a33 58
Jasper_lee 0:b16d94660a33 59 /** @addtogroup Configuration_section_for_CMSIS
Jasper_lee 0:b16d94660a33 60 * @{
Jasper_lee 0:b16d94660a33 61 */
Jasper_lee 0:b16d94660a33 62
Jasper_lee 0:b16d94660a33 63 /**
Jasper_lee 0:b16d94660a33 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Jasper_lee 0:b16d94660a33 65 */
Jasper_lee 0:b16d94660a33 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Jasper_lee 0:b16d94660a33 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Jasper_lee 0:b16d94660a33 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Jasper_lee 0:b16d94660a33 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Jasper_lee 0:b16d94660a33 70
Jasper_lee 0:b16d94660a33 71 /**
Jasper_lee 0:b16d94660a33 72 * @}
Jasper_lee 0:b16d94660a33 73 */
Jasper_lee 0:b16d94660a33 74
Jasper_lee 0:b16d94660a33 75 /** @addtogroup Peripheral_interrupt_number_definition
Jasper_lee 0:b16d94660a33 76 * @{
Jasper_lee 0:b16d94660a33 77 */
Jasper_lee 0:b16d94660a33 78
Jasper_lee 0:b16d94660a33 79 /**
Jasper_lee 0:b16d94660a33 80 * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
Jasper_lee 0:b16d94660a33 81 */
Jasper_lee 0:b16d94660a33 82 typedef enum
Jasper_lee 0:b16d94660a33 83 {
Jasper_lee 0:b16d94660a33 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Jasper_lee 0:b16d94660a33 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Jasper_lee 0:b16d94660a33 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Jasper_lee 0:b16d94660a33 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Jasper_lee 0:b16d94660a33 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Jasper_lee 0:b16d94660a33 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Jasper_lee 0:b16d94660a33 90
Jasper_lee 0:b16d94660a33 91 /****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
Jasper_lee 0:b16d94660a33 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Jasper_lee 0:b16d94660a33 93 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
Jasper_lee 0:b16d94660a33 94 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Jasper_lee 0:b16d94660a33 95 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Jasper_lee 0:b16d94660a33 96 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
Jasper_lee 0:b16d94660a33 97 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Jasper_lee 0:b16d94660a33 98 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Jasper_lee 0:b16d94660a33 99 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Jasper_lee 0:b16d94660a33 100 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
Jasper_lee 0:b16d94660a33 101 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Jasper_lee 0:b16d94660a33 102 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
Jasper_lee 0:b16d94660a33 103 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
Jasper_lee 0:b16d94660a33 104 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
Jasper_lee 0:b16d94660a33 105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
Jasper_lee 0:b16d94660a33 106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Jasper_lee 0:b16d94660a33 107 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
Jasper_lee 0:b16d94660a33 108 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Jasper_lee 0:b16d94660a33 109 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
Jasper_lee 0:b16d94660a33 110 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
Jasper_lee 0:b16d94660a33 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Jasper_lee 0:b16d94660a33 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
Jasper_lee 0:b16d94660a33 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Jasper_lee 0:b16d94660a33 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Jasper_lee 0:b16d94660a33 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Jasper_lee 0:b16d94660a33 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
Jasper_lee 0:b16d94660a33 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Jasper_lee 0:b16d94660a33 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
Jasper_lee 0:b16d94660a33 119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Jasper_lee 0:b16d94660a33 120 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
Jasper_lee 0:b16d94660a33 121 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
Jasper_lee 0:b16d94660a33 122 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
Jasper_lee 0:b16d94660a33 123 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
Jasper_lee 0:b16d94660a33 124 } IRQn_Type;
Jasper_lee 0:b16d94660a33 125
Jasper_lee 0:b16d94660a33 126 /**
Jasper_lee 0:b16d94660a33 127 * @}
Jasper_lee 0:b16d94660a33 128 */
Jasper_lee 0:b16d94660a33 129
Jasper_lee 0:b16d94660a33 130 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Jasper_lee 0:b16d94660a33 131 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Jasper_lee 0:b16d94660a33 132 #include <stdint.h>
Jasper_lee 0:b16d94660a33 133
Jasper_lee 0:b16d94660a33 134 /** @addtogroup Peripheral_registers_structures
Jasper_lee 0:b16d94660a33 135 * @{
Jasper_lee 0:b16d94660a33 136 */
Jasper_lee 0:b16d94660a33 137
Jasper_lee 0:b16d94660a33 138 /**
Jasper_lee 0:b16d94660a33 139 * @brief Analog to Digital Converter
Jasper_lee 0:b16d94660a33 140 */
Jasper_lee 0:b16d94660a33 141
Jasper_lee 0:b16d94660a33 142 typedef struct
Jasper_lee 0:b16d94660a33 143 {
Jasper_lee 0:b16d94660a33 144 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Jasper_lee 0:b16d94660a33 145 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Jasper_lee 0:b16d94660a33 146 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Jasper_lee 0:b16d94660a33 147 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Jasper_lee 0:b16d94660a33 148 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Jasper_lee 0:b16d94660a33 149 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Jasper_lee 0:b16d94660a33 150 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Jasper_lee 0:b16d94660a33 151 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Jasper_lee 0:b16d94660a33 152 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Jasper_lee 0:b16d94660a33 153 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Jasper_lee 0:b16d94660a33 154 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Jasper_lee 0:b16d94660a33 155 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Jasper_lee 0:b16d94660a33 156 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Jasper_lee 0:b16d94660a33 157 }ADC_TypeDef;
Jasper_lee 0:b16d94660a33 158
Jasper_lee 0:b16d94660a33 159 typedef struct
Jasper_lee 0:b16d94660a33 160 {
Jasper_lee 0:b16d94660a33 161 __IO uint32_t CCR;
Jasper_lee 0:b16d94660a33 162 }ADC_Common_TypeDef;
Jasper_lee 0:b16d94660a33 163
Jasper_lee 0:b16d94660a33 164 /**
Jasper_lee 0:b16d94660a33 165 * @brief Controller Area Network TxMailBox
Jasper_lee 0:b16d94660a33 166 */
Jasper_lee 0:b16d94660a33 167 typedef struct
Jasper_lee 0:b16d94660a33 168 {
Jasper_lee 0:b16d94660a33 169 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Jasper_lee 0:b16d94660a33 170 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Jasper_lee 0:b16d94660a33 171 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Jasper_lee 0:b16d94660a33 172 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Jasper_lee 0:b16d94660a33 173 }CAN_TxMailBox_TypeDef;
Jasper_lee 0:b16d94660a33 174
Jasper_lee 0:b16d94660a33 175 /**
Jasper_lee 0:b16d94660a33 176 * @brief Controller Area Network FIFOMailBox
Jasper_lee 0:b16d94660a33 177 */
Jasper_lee 0:b16d94660a33 178 typedef struct
Jasper_lee 0:b16d94660a33 179 {
Jasper_lee 0:b16d94660a33 180 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Jasper_lee 0:b16d94660a33 181 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Jasper_lee 0:b16d94660a33 182 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Jasper_lee 0:b16d94660a33 183 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Jasper_lee 0:b16d94660a33 184 }CAN_FIFOMailBox_TypeDef;
Jasper_lee 0:b16d94660a33 185
Jasper_lee 0:b16d94660a33 186 /**
Jasper_lee 0:b16d94660a33 187 * @brief Controller Area Network FilterRegister
Jasper_lee 0:b16d94660a33 188 */
Jasper_lee 0:b16d94660a33 189 typedef struct
Jasper_lee 0:b16d94660a33 190 {
Jasper_lee 0:b16d94660a33 191 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Jasper_lee 0:b16d94660a33 192 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Jasper_lee 0:b16d94660a33 193 }CAN_FilterRegister_TypeDef;
Jasper_lee 0:b16d94660a33 194
Jasper_lee 0:b16d94660a33 195 /**
Jasper_lee 0:b16d94660a33 196 * @brief Controller Area Network
Jasper_lee 0:b16d94660a33 197 */
Jasper_lee 0:b16d94660a33 198 typedef struct
Jasper_lee 0:b16d94660a33 199 {
Jasper_lee 0:b16d94660a33 200 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 201 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 202 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 203 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 204 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 205 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 206 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 207 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 208 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Jasper_lee 0:b16d94660a33 209 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Jasper_lee 0:b16d94660a33 210 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Jasper_lee 0:b16d94660a33 211 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Jasper_lee 0:b16d94660a33 212 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Jasper_lee 0:b16d94660a33 213 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Jasper_lee 0:b16d94660a33 214 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Jasper_lee 0:b16d94660a33 215 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Jasper_lee 0:b16d94660a33 216 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Jasper_lee 0:b16d94660a33 217 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Jasper_lee 0:b16d94660a33 218 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Jasper_lee 0:b16d94660a33 219 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Jasper_lee 0:b16d94660a33 220 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Jasper_lee 0:b16d94660a33 221 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Jasper_lee 0:b16d94660a33 222 }CAN_TypeDef;
Jasper_lee 0:b16d94660a33 223
Jasper_lee 0:b16d94660a33 224 /**
Jasper_lee 0:b16d94660a33 225 * @brief HDMI-CEC
Jasper_lee 0:b16d94660a33 226 */
Jasper_lee 0:b16d94660a33 227
Jasper_lee 0:b16d94660a33 228 typedef struct
Jasper_lee 0:b16d94660a33 229 {
Jasper_lee 0:b16d94660a33 230 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Jasper_lee 0:b16d94660a33 231 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Jasper_lee 0:b16d94660a33 232 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Jasper_lee 0:b16d94660a33 233 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Jasper_lee 0:b16d94660a33 234 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Jasper_lee 0:b16d94660a33 235 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Jasper_lee 0:b16d94660a33 236 }CEC_TypeDef;
Jasper_lee 0:b16d94660a33 237
Jasper_lee 0:b16d94660a33 238 /**
Jasper_lee 0:b16d94660a33 239 * @brief Comparator
Jasper_lee 0:b16d94660a33 240 */
Jasper_lee 0:b16d94660a33 241
Jasper_lee 0:b16d94660a33 242 typedef struct
Jasper_lee 0:b16d94660a33 243 {
Jasper_lee 0:b16d94660a33 244 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 245 }COMP1_2_TypeDef;
Jasper_lee 0:b16d94660a33 246
Jasper_lee 0:b16d94660a33 247 typedef struct
Jasper_lee 0:b16d94660a33 248 {
Jasper_lee 0:b16d94660a33 249 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 250 }COMP_TypeDef;
Jasper_lee 0:b16d94660a33 251
Jasper_lee 0:b16d94660a33 252 /**
Jasper_lee 0:b16d94660a33 253 * @brief CRC calculation unit
Jasper_lee 0:b16d94660a33 254 */
Jasper_lee 0:b16d94660a33 255
Jasper_lee 0:b16d94660a33 256 typedef struct
Jasper_lee 0:b16d94660a33 257 {
Jasper_lee 0:b16d94660a33 258 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 259 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 260 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Jasper_lee 0:b16d94660a33 261 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Jasper_lee 0:b16d94660a33 262 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 263 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Jasper_lee 0:b16d94660a33 264 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 265 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 266 }CRC_TypeDef;
Jasper_lee 0:b16d94660a33 267
Jasper_lee 0:b16d94660a33 268 /**
Jasper_lee 0:b16d94660a33 269 * @brief Clock Recovery System
Jasper_lee 0:b16d94660a33 270 */
Jasper_lee 0:b16d94660a33 271 typedef struct
Jasper_lee 0:b16d94660a33 272 {
Jasper_lee 0:b16d94660a33 273 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 274 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 275 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 276 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 277 }CRS_TypeDef;
Jasper_lee 0:b16d94660a33 278
Jasper_lee 0:b16d94660a33 279 /**
Jasper_lee 0:b16d94660a33 280 * @brief Digital to Analog Converter
Jasper_lee 0:b16d94660a33 281 */
Jasper_lee 0:b16d94660a33 282
Jasper_lee 0:b16d94660a33 283 typedef struct
Jasper_lee 0:b16d94660a33 284 {
Jasper_lee 0:b16d94660a33 285 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 286 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 287 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 288 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 289 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 290 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 291 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 292 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 293 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 294 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 295 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 296 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Jasper_lee 0:b16d94660a33 297 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Jasper_lee 0:b16d94660a33 298 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Jasper_lee 0:b16d94660a33 299 }DAC_TypeDef;
Jasper_lee 0:b16d94660a33 300
Jasper_lee 0:b16d94660a33 301 /**
Jasper_lee 0:b16d94660a33 302 * @brief Debug MCU
Jasper_lee 0:b16d94660a33 303 */
Jasper_lee 0:b16d94660a33 304
Jasper_lee 0:b16d94660a33 305 typedef struct
Jasper_lee 0:b16d94660a33 306 {
Jasper_lee 0:b16d94660a33 307 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 308 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 309 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 310 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 311 }DBGMCU_TypeDef;
Jasper_lee 0:b16d94660a33 312
Jasper_lee 0:b16d94660a33 313 /**
Jasper_lee 0:b16d94660a33 314 * @brief DMA Controller
Jasper_lee 0:b16d94660a33 315 */
Jasper_lee 0:b16d94660a33 316
Jasper_lee 0:b16d94660a33 317 typedef struct
Jasper_lee 0:b16d94660a33 318 {
Jasper_lee 0:b16d94660a33 319 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Jasper_lee 0:b16d94660a33 320 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Jasper_lee 0:b16d94660a33 321 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Jasper_lee 0:b16d94660a33 322 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Jasper_lee 0:b16d94660a33 323 }DMA_Channel_TypeDef;
Jasper_lee 0:b16d94660a33 324
Jasper_lee 0:b16d94660a33 325 typedef struct
Jasper_lee 0:b16d94660a33 326 {
Jasper_lee 0:b16d94660a33 327 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 328 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 329 }DMA_TypeDef;
Jasper_lee 0:b16d94660a33 330
Jasper_lee 0:b16d94660a33 331 /**
Jasper_lee 0:b16d94660a33 332 * @brief External Interrupt/Event Controller
Jasper_lee 0:b16d94660a33 333 */
Jasper_lee 0:b16d94660a33 334
Jasper_lee 0:b16d94660a33 335 typedef struct
Jasper_lee 0:b16d94660a33 336 {
Jasper_lee 0:b16d94660a33 337 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 338 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 339 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 340 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 341 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 342 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 343 }EXTI_TypeDef;
Jasper_lee 0:b16d94660a33 344
Jasper_lee 0:b16d94660a33 345 /**
Jasper_lee 0:b16d94660a33 346 * @brief FLASH Registers
Jasper_lee 0:b16d94660a33 347 */
Jasper_lee 0:b16d94660a33 348 typedef struct
Jasper_lee 0:b16d94660a33 349 {
Jasper_lee 0:b16d94660a33 350 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 351 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 352 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 353 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 354 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 355 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 356 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Jasper_lee 0:b16d94660a33 357 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 358 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 359 }FLASH_TypeDef;
Jasper_lee 0:b16d94660a33 360
Jasper_lee 0:b16d94660a33 361
Jasper_lee 0:b16d94660a33 362 /**
Jasper_lee 0:b16d94660a33 363 * @brief Option Bytes Registers
Jasper_lee 0:b16d94660a33 364 */
Jasper_lee 0:b16d94660a33 365 typedef struct
Jasper_lee 0:b16d94660a33 366 {
Jasper_lee 0:b16d94660a33 367 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 368 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Jasper_lee 0:b16d94660a33 369 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 370 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Jasper_lee 0:b16d94660a33 371 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 372 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Jasper_lee 0:b16d94660a33 373 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 374 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
Jasper_lee 0:b16d94660a33 375 }OB_TypeDef;
Jasper_lee 0:b16d94660a33 376
Jasper_lee 0:b16d94660a33 377 /**
Jasper_lee 0:b16d94660a33 378 * @brief General Purpose I/O
Jasper_lee 0:b16d94660a33 379 */
Jasper_lee 0:b16d94660a33 380
Jasper_lee 0:b16d94660a33 381 typedef struct
Jasper_lee 0:b16d94660a33 382 {
Jasper_lee 0:b16d94660a33 383 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 384 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 385 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 386 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 387 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 388 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 389 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Jasper_lee 0:b16d94660a33 390 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 391 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Jasper_lee 0:b16d94660a33 392 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 393 }GPIO_TypeDef;
Jasper_lee 0:b16d94660a33 394
Jasper_lee 0:b16d94660a33 395 /**
Jasper_lee 0:b16d94660a33 396 * @brief SysTem Configuration
Jasper_lee 0:b16d94660a33 397 */
Jasper_lee 0:b16d94660a33 398
Jasper_lee 0:b16d94660a33 399 typedef struct
Jasper_lee 0:b16d94660a33 400 {
Jasper_lee 0:b16d94660a33 401 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 402 uint32_t RESERVED; /*!< Reserved, 0x04 */
Jasper_lee 0:b16d94660a33 403 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Jasper_lee 0:b16d94660a33 404 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 405 }SYSCFG_TypeDef;
Jasper_lee 0:b16d94660a33 406
Jasper_lee 0:b16d94660a33 407 /**
Jasper_lee 0:b16d94660a33 408 * @brief Inter-integrated Circuit Interface
Jasper_lee 0:b16d94660a33 409 */
Jasper_lee 0:b16d94660a33 410
Jasper_lee 0:b16d94660a33 411 typedef struct
Jasper_lee 0:b16d94660a33 412 {
Jasper_lee 0:b16d94660a33 413 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 414 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 415 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 416 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 417 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 418 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 419 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 420 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 421 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 422 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 423 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 424 }I2C_TypeDef;
Jasper_lee 0:b16d94660a33 425
Jasper_lee 0:b16d94660a33 426 /**
Jasper_lee 0:b16d94660a33 427 * @brief Independent WATCHDOG
Jasper_lee 0:b16d94660a33 428 */
Jasper_lee 0:b16d94660a33 429
Jasper_lee 0:b16d94660a33 430 typedef struct
Jasper_lee 0:b16d94660a33 431 {
Jasper_lee 0:b16d94660a33 432 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 433 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 434 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 435 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 436 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 437 }IWDG_TypeDef;
Jasper_lee 0:b16d94660a33 438
Jasper_lee 0:b16d94660a33 439 /**
Jasper_lee 0:b16d94660a33 440 * @brief Power Control
Jasper_lee 0:b16d94660a33 441 */
Jasper_lee 0:b16d94660a33 442
Jasper_lee 0:b16d94660a33 443 typedef struct
Jasper_lee 0:b16d94660a33 444 {
Jasper_lee 0:b16d94660a33 445 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 446 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 447 }PWR_TypeDef;
Jasper_lee 0:b16d94660a33 448
Jasper_lee 0:b16d94660a33 449 /**
Jasper_lee 0:b16d94660a33 450 * @brief Reset and Clock Control
Jasper_lee 0:b16d94660a33 451 */
Jasper_lee 0:b16d94660a33 452 typedef struct
Jasper_lee 0:b16d94660a33 453 {
Jasper_lee 0:b16d94660a33 454 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 455 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 456 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 457 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 458 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 459 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 460 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 461 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 462 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 463 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 464 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 465 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Jasper_lee 0:b16d94660a33 466 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Jasper_lee 0:b16d94660a33 467 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Jasper_lee 0:b16d94660a33 468 }RCC_TypeDef;
Jasper_lee 0:b16d94660a33 469
Jasper_lee 0:b16d94660a33 470 /**
Jasper_lee 0:b16d94660a33 471 * @brief Real-Time Clock
Jasper_lee 0:b16d94660a33 472 */
Jasper_lee 0:b16d94660a33 473
Jasper_lee 0:b16d94660a33 474 typedef struct
Jasper_lee 0:b16d94660a33 475 {
Jasper_lee 0:b16d94660a33 476 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 477 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 478 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 479 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 480 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 481 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 482 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 483 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 484 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 485 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 486 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 487 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Jasper_lee 0:b16d94660a33 488 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Jasper_lee 0:b16d94660a33 489 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Jasper_lee 0:b16d94660a33 490 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Jasper_lee 0:b16d94660a33 491 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Jasper_lee 0:b16d94660a33 492 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Jasper_lee 0:b16d94660a33 493 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Jasper_lee 0:b16d94660a33 494 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
Jasper_lee 0:b16d94660a33 495 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
Jasper_lee 0:b16d94660a33 496 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Jasper_lee 0:b16d94660a33 497 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Jasper_lee 0:b16d94660a33 498 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Jasper_lee 0:b16d94660a33 499 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Jasper_lee 0:b16d94660a33 500 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Jasper_lee 0:b16d94660a33 501 }RTC_TypeDef;
Jasper_lee 0:b16d94660a33 502
Jasper_lee 0:b16d94660a33 503 /**
Jasper_lee 0:b16d94660a33 504 * @brief Serial Peripheral Interface
Jasper_lee 0:b16d94660a33 505 */
Jasper_lee 0:b16d94660a33 506
Jasper_lee 0:b16d94660a33 507 typedef struct
Jasper_lee 0:b16d94660a33 508 {
Jasper_lee 0:b16d94660a33 509 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 510 uint16_t RESERVED0; /*!< Reserved, 0x02 */
Jasper_lee 0:b16d94660a33 511 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 512 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Jasper_lee 0:b16d94660a33 513 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 514 uint16_t RESERVED2; /*!< Reserved, 0x0A */
Jasper_lee 0:b16d94660a33 515 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 516 uint16_t RESERVED3; /*!< Reserved, 0x0E */
Jasper_lee 0:b16d94660a33 517 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 518 uint16_t RESERVED4; /*!< Reserved, 0x12 */
Jasper_lee 0:b16d94660a33 519 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 520 uint16_t RESERVED5; /*!< Reserved, 0x16 */
Jasper_lee 0:b16d94660a33 521 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 522 uint16_t RESERVED6; /*!< Reserved, 0x1A */
Jasper_lee 0:b16d94660a33 523 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 524 uint16_t RESERVED7; /*!< Reserved, 0x1E */
Jasper_lee 0:b16d94660a33 525 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 526 uint16_t RESERVED8; /*!< Reserved, 0x22 */
Jasper_lee 0:b16d94660a33 527 }SPI_TypeDef;
Jasper_lee 0:b16d94660a33 528
Jasper_lee 0:b16d94660a33 529 /**
Jasper_lee 0:b16d94660a33 530 * @brief TIM
Jasper_lee 0:b16d94660a33 531 */
Jasper_lee 0:b16d94660a33 532 typedef struct
Jasper_lee 0:b16d94660a33 533 {
Jasper_lee 0:b16d94660a33 534 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 535 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 536 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 537 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 538 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 539 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 540 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 541 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 542 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 543 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 544 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 545 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Jasper_lee 0:b16d94660a33 546 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Jasper_lee 0:b16d94660a33 547 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Jasper_lee 0:b16d94660a33 548 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Jasper_lee 0:b16d94660a33 549 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Jasper_lee 0:b16d94660a33 550 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Jasper_lee 0:b16d94660a33 551 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Jasper_lee 0:b16d94660a33 552 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Jasper_lee 0:b16d94660a33 553 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Jasper_lee 0:b16d94660a33 554 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Jasper_lee 0:b16d94660a33 555 }TIM_TypeDef;
Jasper_lee 0:b16d94660a33 556
Jasper_lee 0:b16d94660a33 557 /**
Jasper_lee 0:b16d94660a33 558 * @brief Touch Sensing Controller (TSC)
Jasper_lee 0:b16d94660a33 559 */
Jasper_lee 0:b16d94660a33 560 typedef struct
Jasper_lee 0:b16d94660a33 561 {
Jasper_lee 0:b16d94660a33 562 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 563 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 564 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 565 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 566 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 567 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 568 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 569 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 570 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 571 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 572 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 573 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Jasper_lee 0:b16d94660a33 574 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Jasper_lee 0:b16d94660a33 575 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Jasper_lee 0:b16d94660a33 576 }TSC_TypeDef;
Jasper_lee 0:b16d94660a33 577
Jasper_lee 0:b16d94660a33 578 /**
Jasper_lee 0:b16d94660a33 579 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Jasper_lee 0:b16d94660a33 580 */
Jasper_lee 0:b16d94660a33 581
Jasper_lee 0:b16d94660a33 582 typedef struct
Jasper_lee 0:b16d94660a33 583 {
Jasper_lee 0:b16d94660a33 584 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 585 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 586 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 587 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 588 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 589 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 590 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 591 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 592 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Jasper_lee 0:b16d94660a33 593 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Jasper_lee 0:b16d94660a33 594 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Jasper_lee 0:b16d94660a33 595 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Jasper_lee 0:b16d94660a33 596 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Jasper_lee 0:b16d94660a33 597 }USART_TypeDef;
Jasper_lee 0:b16d94660a33 598
Jasper_lee 0:b16d94660a33 599 /**
Jasper_lee 0:b16d94660a33 600 * @brief Universal Serial Bus Full Speed Device
Jasper_lee 0:b16d94660a33 601 */
Jasper_lee 0:b16d94660a33 602
Jasper_lee 0:b16d94660a33 603 typedef struct
Jasper_lee 0:b16d94660a33 604 {
Jasper_lee 0:b16d94660a33 605 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 606 __IO uint16_t RESERVED0; /*!< Reserved */
Jasper_lee 0:b16d94660a33 607 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 608 __IO uint16_t RESERVED1; /*!< Reserved */
Jasper_lee 0:b16d94660a33 609 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 610 __IO uint16_t RESERVED2; /*!< Reserved */
Jasper_lee 0:b16d94660a33 611 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Jasper_lee 0:b16d94660a33 612 __IO uint16_t RESERVED3; /*!< Reserved */
Jasper_lee 0:b16d94660a33 613 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Jasper_lee 0:b16d94660a33 614 __IO uint16_t RESERVED4; /*!< Reserved */
Jasper_lee 0:b16d94660a33 615 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Jasper_lee 0:b16d94660a33 616 __IO uint16_t RESERVED5; /*!< Reserved */
Jasper_lee 0:b16d94660a33 617 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Jasper_lee 0:b16d94660a33 618 __IO uint16_t RESERVED6; /*!< Reserved */
Jasper_lee 0:b16d94660a33 619 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Jasper_lee 0:b16d94660a33 620 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Jasper_lee 0:b16d94660a33 621 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Jasper_lee 0:b16d94660a33 622 __IO uint16_t RESERVED8; /*!< Reserved */
Jasper_lee 0:b16d94660a33 623 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Jasper_lee 0:b16d94660a33 624 __IO uint16_t RESERVED9; /*!< Reserved */
Jasper_lee 0:b16d94660a33 625 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Jasper_lee 0:b16d94660a33 626 __IO uint16_t RESERVEDA; /*!< Reserved */
Jasper_lee 0:b16d94660a33 627 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Jasper_lee 0:b16d94660a33 628 __IO uint16_t RESERVEDB; /*!< Reserved */
Jasper_lee 0:b16d94660a33 629 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Jasper_lee 0:b16d94660a33 630 __IO uint16_t RESERVEDC; /*!< Reserved */
Jasper_lee 0:b16d94660a33 631 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
Jasper_lee 0:b16d94660a33 632 __IO uint16_t RESERVEDD; /*!< Reserved */
Jasper_lee 0:b16d94660a33 633 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
Jasper_lee 0:b16d94660a33 634 __IO uint16_t RESERVEDE; /*!< Reserved */
Jasper_lee 0:b16d94660a33 635 }USB_TypeDef;
Jasper_lee 0:b16d94660a33 636
Jasper_lee 0:b16d94660a33 637 /**
Jasper_lee 0:b16d94660a33 638 * @brief Window WATCHDOG
Jasper_lee 0:b16d94660a33 639 */
Jasper_lee 0:b16d94660a33 640 typedef struct
Jasper_lee 0:b16d94660a33 641 {
Jasper_lee 0:b16d94660a33 642 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Jasper_lee 0:b16d94660a33 643 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Jasper_lee 0:b16d94660a33 644 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Jasper_lee 0:b16d94660a33 645 }WWDG_TypeDef;
Jasper_lee 0:b16d94660a33 646
Jasper_lee 0:b16d94660a33 647 /**
Jasper_lee 0:b16d94660a33 648 * @}
Jasper_lee 0:b16d94660a33 649 */
Jasper_lee 0:b16d94660a33 650
Jasper_lee 0:b16d94660a33 651 /** @addtogroup Peripheral_memory_map
Jasper_lee 0:b16d94660a33 652 * @{
Jasper_lee 0:b16d94660a33 653 */
Jasper_lee 0:b16d94660a33 654
Jasper_lee 0:b16d94660a33 655 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Jasper_lee 0:b16d94660a33 656 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Jasper_lee 0:b16d94660a33 657 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Jasper_lee 0:b16d94660a33 658
Jasper_lee 0:b16d94660a33 659 /*!< Peripheral memory map */
Jasper_lee 0:b16d94660a33 660 #define APBPERIPH_BASE PERIPH_BASE
Jasper_lee 0:b16d94660a33 661 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Jasper_lee 0:b16d94660a33 662 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Jasper_lee 0:b16d94660a33 663
Jasper_lee 0:b16d94660a33 664 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Jasper_lee 0:b16d94660a33 665 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Jasper_lee 0:b16d94660a33 666 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Jasper_lee 0:b16d94660a33 667 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
Jasper_lee 0:b16d94660a33 668 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Jasper_lee 0:b16d94660a33 669 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Jasper_lee 0:b16d94660a33 670 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Jasper_lee 0:b16d94660a33 671 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Jasper_lee 0:b16d94660a33 672 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Jasper_lee 0:b16d94660a33 673 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Jasper_lee 0:b16d94660a33 674 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
Jasper_lee 0:b16d94660a33 675 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
Jasper_lee 0:b16d94660a33 676 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Jasper_lee 0:b16d94660a33 677 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Jasper_lee 0:b16d94660a33 678 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
Jasper_lee 0:b16d94660a33 679 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
Jasper_lee 0:b16d94660a33 680 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
Jasper_lee 0:b16d94660a33 681 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
Jasper_lee 0:b16d94660a33 682 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Jasper_lee 0:b16d94660a33 683 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
Jasper_lee 0:b16d94660a33 684 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
Jasper_lee 0:b16d94660a33 685
Jasper_lee 0:b16d94660a33 686 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Jasper_lee 0:b16d94660a33 687 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
Jasper_lee 0:b16d94660a33 688 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Jasper_lee 0:b16d94660a33 689 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Jasper_lee 0:b16d94660a33 690 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Jasper_lee 0:b16d94660a33 691 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Jasper_lee 0:b16d94660a33 692 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Jasper_lee 0:b16d94660a33 693 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Jasper_lee 0:b16d94660a33 694 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Jasper_lee 0:b16d94660a33 695 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Jasper_lee 0:b16d94660a33 696 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Jasper_lee 0:b16d94660a33 697 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Jasper_lee 0:b16d94660a33 698
Jasper_lee 0:b16d94660a33 699 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Jasper_lee 0:b16d94660a33 700 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Jasper_lee 0:b16d94660a33 701 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Jasper_lee 0:b16d94660a33 702 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Jasper_lee 0:b16d94660a33 703 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Jasper_lee 0:b16d94660a33 704 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Jasper_lee 0:b16d94660a33 705 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Jasper_lee 0:b16d94660a33 706 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Jasper_lee 0:b16d94660a33 707
Jasper_lee 0:b16d94660a33 708 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Jasper_lee 0:b16d94660a33 709 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Jasper_lee 0:b16d94660a33 710 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
Jasper_lee 0:b16d94660a33 711 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Jasper_lee 0:b16d94660a33 712 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
Jasper_lee 0:b16d94660a33 713
Jasper_lee 0:b16d94660a33 714 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Jasper_lee 0:b16d94660a33 715 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Jasper_lee 0:b16d94660a33 716 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Jasper_lee 0:b16d94660a33 717 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Jasper_lee 0:b16d94660a33 718 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
Jasper_lee 0:b16d94660a33 719 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Jasper_lee 0:b16d94660a33 720
Jasper_lee 0:b16d94660a33 721 /**
Jasper_lee 0:b16d94660a33 722 * @}
Jasper_lee 0:b16d94660a33 723 */
Jasper_lee 0:b16d94660a33 724
Jasper_lee 0:b16d94660a33 725 /** @addtogroup Peripheral_declaration
Jasper_lee 0:b16d94660a33 726 * @{
Jasper_lee 0:b16d94660a33 727 */
Jasper_lee 0:b16d94660a33 728
Jasper_lee 0:b16d94660a33 729 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Jasper_lee 0:b16d94660a33 730 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Jasper_lee 0:b16d94660a33 731 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Jasper_lee 0:b16d94660a33 732 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Jasper_lee 0:b16d94660a33 733 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Jasper_lee 0:b16d94660a33 734 #define RTC ((RTC_TypeDef *) RTC_BASE)
Jasper_lee 0:b16d94660a33 735 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Jasper_lee 0:b16d94660a33 736 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Jasper_lee 0:b16d94660a33 737 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Jasper_lee 0:b16d94660a33 738 #define USART2 ((USART_TypeDef *) USART2_BASE)
Jasper_lee 0:b16d94660a33 739 #define USART3 ((USART_TypeDef *) USART3_BASE)
Jasper_lee 0:b16d94660a33 740 #define USART4 ((USART_TypeDef *) USART4_BASE)
Jasper_lee 0:b16d94660a33 741 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Jasper_lee 0:b16d94660a33 742 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Jasper_lee 0:b16d94660a33 743 #define CAN ((CAN_TypeDef *) CAN_BASE)
Jasper_lee 0:b16d94660a33 744 #define CRS ((CRS_TypeDef *) CRS_BASE)
Jasper_lee 0:b16d94660a33 745 #define PWR ((PWR_TypeDef *) PWR_BASE)
Jasper_lee 0:b16d94660a33 746 #define DAC ((DAC_TypeDef *) DAC_BASE)
Jasper_lee 0:b16d94660a33 747 #define CEC ((CEC_TypeDef *) CEC_BASE)
Jasper_lee 0:b16d94660a33 748 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Jasper_lee 0:b16d94660a33 749 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
Jasper_lee 0:b16d94660a33 750 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
Jasper_lee 0:b16d94660a33 751 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
Jasper_lee 0:b16d94660a33 752 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Jasper_lee 0:b16d94660a33 753 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Jasper_lee 0:b16d94660a33 754 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Jasper_lee 0:b16d94660a33 755 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Jasper_lee 0:b16d94660a33 756 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Jasper_lee 0:b16d94660a33 757 #define USART1 ((USART_TypeDef *) USART1_BASE)
Jasper_lee 0:b16d94660a33 758 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Jasper_lee 0:b16d94660a33 759 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Jasper_lee 0:b16d94660a33 760 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Jasper_lee 0:b16d94660a33 761 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Jasper_lee 0:b16d94660a33 762 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Jasper_lee 0:b16d94660a33 763 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Jasper_lee 0:b16d94660a33 764 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Jasper_lee 0:b16d94660a33 765 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Jasper_lee 0:b16d94660a33 766 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Jasper_lee 0:b16d94660a33 767 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Jasper_lee 0:b16d94660a33 768 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Jasper_lee 0:b16d94660a33 769 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Jasper_lee 0:b16d94660a33 770 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Jasper_lee 0:b16d94660a33 771 #define OB ((OB_TypeDef *) OB_BASE)
Jasper_lee 0:b16d94660a33 772 #define RCC ((RCC_TypeDef *) RCC_BASE)
Jasper_lee 0:b16d94660a33 773 #define CRC ((CRC_TypeDef *) CRC_BASE)
Jasper_lee 0:b16d94660a33 774 #define TSC ((TSC_TypeDef *) TSC_BASE)
Jasper_lee 0:b16d94660a33 775 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Jasper_lee 0:b16d94660a33 776 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Jasper_lee 0:b16d94660a33 777 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Jasper_lee 0:b16d94660a33 778 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Jasper_lee 0:b16d94660a33 779 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Jasper_lee 0:b16d94660a33 780 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Jasper_lee 0:b16d94660a33 781 #define USB ((USB_TypeDef *) USB_BASE)
Jasper_lee 0:b16d94660a33 782 /**
Jasper_lee 0:b16d94660a33 783 * @}
Jasper_lee 0:b16d94660a33 784 */
Jasper_lee 0:b16d94660a33 785
Jasper_lee 0:b16d94660a33 786 /** @addtogroup Exported_constants
Jasper_lee 0:b16d94660a33 787 * @{
Jasper_lee 0:b16d94660a33 788 */
Jasper_lee 0:b16d94660a33 789
Jasper_lee 0:b16d94660a33 790 /** @addtogroup Peripheral_Registers_Bits_Definition
Jasper_lee 0:b16d94660a33 791 * @{
Jasper_lee 0:b16d94660a33 792 */
Jasper_lee 0:b16d94660a33 793
Jasper_lee 0:b16d94660a33 794 /******************************************************************************/
Jasper_lee 0:b16d94660a33 795 /* Peripheral Registers Bits Definition */
Jasper_lee 0:b16d94660a33 796 /******************************************************************************/
Jasper_lee 0:b16d94660a33 797 /******************************************************************************/
Jasper_lee 0:b16d94660a33 798 /* */
Jasper_lee 0:b16d94660a33 799 /* Analog to Digital Converter (ADC) */
Jasper_lee 0:b16d94660a33 800 /* */
Jasper_lee 0:b16d94660a33 801 /******************************************************************************/
Jasper_lee 0:b16d94660a33 802 /******************** Bits definition for ADC_ISR register ******************/
Jasper_lee 0:b16d94660a33 803 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
Jasper_lee 0:b16d94660a33 804 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
Jasper_lee 0:b16d94660a33 805 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
Jasper_lee 0:b16d94660a33 806 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
Jasper_lee 0:b16d94660a33 807 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
Jasper_lee 0:b16d94660a33 808 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
Jasper_lee 0:b16d94660a33 809
Jasper_lee 0:b16d94660a33 810 /* Old EOSEQ bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 811 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Jasper_lee 0:b16d94660a33 812
Jasper_lee 0:b16d94660a33 813 /******************** Bits definition for ADC_IER register ******************/
Jasper_lee 0:b16d94660a33 814 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
Jasper_lee 0:b16d94660a33 815 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
Jasper_lee 0:b16d94660a33 816 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
Jasper_lee 0:b16d94660a33 817 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
Jasper_lee 0:b16d94660a33 818 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
Jasper_lee 0:b16d94660a33 819 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
Jasper_lee 0:b16d94660a33 820
Jasper_lee 0:b16d94660a33 821 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 822 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Jasper_lee 0:b16d94660a33 823
Jasper_lee 0:b16d94660a33 824 /******************** Bits definition for ADC_CR register *******************/
Jasper_lee 0:b16d94660a33 825 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
Jasper_lee 0:b16d94660a33 826 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
Jasper_lee 0:b16d94660a33 827 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
Jasper_lee 0:b16d94660a33 828 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
Jasper_lee 0:b16d94660a33 829 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
Jasper_lee 0:b16d94660a33 830
Jasper_lee 0:b16d94660a33 831 /******************* Bits definition for ADC_CFGR1 register *****************/
Jasper_lee 0:b16d94660a33 832 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Jasper_lee 0:b16d94660a33 833 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 834 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 835 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 836 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 837 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Jasper_lee 0:b16d94660a33 838 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Jasper_lee 0:b16d94660a33 839 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
Jasper_lee 0:b16d94660a33 840 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
Jasper_lee 0:b16d94660a33 841 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
Jasper_lee 0:b16d94660a33 842 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
Jasper_lee 0:b16d94660a33 843 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
Jasper_lee 0:b16d94660a33 844 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
Jasper_lee 0:b16d94660a33 845 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Jasper_lee 0:b16d94660a33 846 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 847 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 848 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Jasper_lee 0:b16d94660a33 849 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 850 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 851 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 852 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
Jasper_lee 0:b16d94660a33 853 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
Jasper_lee 0:b16d94660a33 854 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 855 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 856 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
Jasper_lee 0:b16d94660a33 857 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
Jasper_lee 0:b16d94660a33 858 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
Jasper_lee 0:b16d94660a33 859
Jasper_lee 0:b16d94660a33 860 /* Old WAIT bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 861 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Jasper_lee 0:b16d94660a33 862
Jasper_lee 0:b16d94660a33 863 /******************* Bits definition for ADC_CFGR2 register *****************/
Jasper_lee 0:b16d94660a33 864 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
Jasper_lee 0:b16d94660a33 865 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
Jasper_lee 0:b16d94660a33 866 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
Jasper_lee 0:b16d94660a33 867
Jasper_lee 0:b16d94660a33 868 /* Old bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 869 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
Jasper_lee 0:b16d94660a33 870 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
Jasper_lee 0:b16d94660a33 871
Jasper_lee 0:b16d94660a33 872 /****************** Bit definition for ADC_SMPR register ********************/
Jasper_lee 0:b16d94660a33 873 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
Jasper_lee 0:b16d94660a33 874 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 875 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 876 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 877
Jasper_lee 0:b16d94660a33 878 /* Old bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 879 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
Jasper_lee 0:b16d94660a33 880 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 881 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 882 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 883
Jasper_lee 0:b16d94660a33 884 /******************* Bit definition for ADC_TR register ********************/
Jasper_lee 0:b16d94660a33 885 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
Jasper_lee 0:b16d94660a33 886 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Jasper_lee 0:b16d94660a33 887
Jasper_lee 0:b16d94660a33 888 /* Old bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 889 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
Jasper_lee 0:b16d94660a33 890 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
Jasper_lee 0:b16d94660a33 891
Jasper_lee 0:b16d94660a33 892 /****************** Bit definition for ADC_CHSELR register ******************/
Jasper_lee 0:b16d94660a33 893 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
Jasper_lee 0:b16d94660a33 894 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
Jasper_lee 0:b16d94660a33 895 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
Jasper_lee 0:b16d94660a33 896 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
Jasper_lee 0:b16d94660a33 897 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
Jasper_lee 0:b16d94660a33 898 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
Jasper_lee 0:b16d94660a33 899 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
Jasper_lee 0:b16d94660a33 900 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
Jasper_lee 0:b16d94660a33 901 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
Jasper_lee 0:b16d94660a33 902 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
Jasper_lee 0:b16d94660a33 903 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
Jasper_lee 0:b16d94660a33 904 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
Jasper_lee 0:b16d94660a33 905 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
Jasper_lee 0:b16d94660a33 906 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
Jasper_lee 0:b16d94660a33 907 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
Jasper_lee 0:b16d94660a33 908 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
Jasper_lee 0:b16d94660a33 909 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
Jasper_lee 0:b16d94660a33 910 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
Jasper_lee 0:b16d94660a33 911 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
Jasper_lee 0:b16d94660a33 912
Jasper_lee 0:b16d94660a33 913 /******************** Bit definition for ADC_DR register ********************/
Jasper_lee 0:b16d94660a33 914 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Jasper_lee 0:b16d94660a33 915
Jasper_lee 0:b16d94660a33 916 /******************* Bit definition for ADC_CCR register ********************/
Jasper_lee 0:b16d94660a33 917 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
Jasper_lee 0:b16d94660a33 918 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
Jasper_lee 0:b16d94660a33 919 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
Jasper_lee 0:b16d94660a33 920
Jasper_lee 0:b16d94660a33 921 /******************************************************************************/
Jasper_lee 0:b16d94660a33 922 /* */
Jasper_lee 0:b16d94660a33 923 /* Controller Area Network (CAN ) */
Jasper_lee 0:b16d94660a33 924 /* */
Jasper_lee 0:b16d94660a33 925 /******************************************************************************/
Jasper_lee 0:b16d94660a33 926 /*!<CAN control and status registers */
Jasper_lee 0:b16d94660a33 927 /******************* Bit definition for CAN_MCR register ********************/
Jasper_lee 0:b16d94660a33 928 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Jasper_lee 0:b16d94660a33 929 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Jasper_lee 0:b16d94660a33 930 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Jasper_lee 0:b16d94660a33 931 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Jasper_lee 0:b16d94660a33 932 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Jasper_lee 0:b16d94660a33 933 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Jasper_lee 0:b16d94660a33 934 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Jasper_lee 0:b16d94660a33 935 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Jasper_lee 0:b16d94660a33 936 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Jasper_lee 0:b16d94660a33 937
Jasper_lee 0:b16d94660a33 938 /******************* Bit definition for CAN_MSR register ********************/
Jasper_lee 0:b16d94660a33 939 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
Jasper_lee 0:b16d94660a33 940 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
Jasper_lee 0:b16d94660a33 941 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
Jasper_lee 0:b16d94660a33 942 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
Jasper_lee 0:b16d94660a33 943 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
Jasper_lee 0:b16d94660a33 944 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
Jasper_lee 0:b16d94660a33 945 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
Jasper_lee 0:b16d94660a33 946 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
Jasper_lee 0:b16d94660a33 947 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
Jasper_lee 0:b16d94660a33 948
Jasper_lee 0:b16d94660a33 949 /******************* Bit definition for CAN_TSR register ********************/
Jasper_lee 0:b16d94660a33 950 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Jasper_lee 0:b16d94660a33 951 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Jasper_lee 0:b16d94660a33 952 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Jasper_lee 0:b16d94660a33 953 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Jasper_lee 0:b16d94660a33 954 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Jasper_lee 0:b16d94660a33 955 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Jasper_lee 0:b16d94660a33 956 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Jasper_lee 0:b16d94660a33 957 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Jasper_lee 0:b16d94660a33 958 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Jasper_lee 0:b16d94660a33 959 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Jasper_lee 0:b16d94660a33 960 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Jasper_lee 0:b16d94660a33 961 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Jasper_lee 0:b16d94660a33 962 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Jasper_lee 0:b16d94660a33 963 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Jasper_lee 0:b16d94660a33 964 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Jasper_lee 0:b16d94660a33 965 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Jasper_lee 0:b16d94660a33 966
Jasper_lee 0:b16d94660a33 967 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Jasper_lee 0:b16d94660a33 968 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Jasper_lee 0:b16d94660a33 969 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Jasper_lee 0:b16d94660a33 970 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Jasper_lee 0:b16d94660a33 971
Jasper_lee 0:b16d94660a33 972 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Jasper_lee 0:b16d94660a33 973 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Jasper_lee 0:b16d94660a33 974 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Jasper_lee 0:b16d94660a33 975 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Jasper_lee 0:b16d94660a33 976
Jasper_lee 0:b16d94660a33 977 /******************* Bit definition for CAN_RF0R register *******************/
Jasper_lee 0:b16d94660a33 978 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
Jasper_lee 0:b16d94660a33 979 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
Jasper_lee 0:b16d94660a33 980 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
Jasper_lee 0:b16d94660a33 981 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
Jasper_lee 0:b16d94660a33 982
Jasper_lee 0:b16d94660a33 983 /******************* Bit definition for CAN_RF1R register *******************/
Jasper_lee 0:b16d94660a33 984 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
Jasper_lee 0:b16d94660a33 985 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
Jasper_lee 0:b16d94660a33 986 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
Jasper_lee 0:b16d94660a33 987 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
Jasper_lee 0:b16d94660a33 988
Jasper_lee 0:b16d94660a33 989 /******************** Bit definition for CAN_IER register *******************/
Jasper_lee 0:b16d94660a33 990 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Jasper_lee 0:b16d94660a33 991 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Jasper_lee 0:b16d94660a33 992 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Jasper_lee 0:b16d94660a33 993 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Jasper_lee 0:b16d94660a33 994 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Jasper_lee 0:b16d94660a33 995 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Jasper_lee 0:b16d94660a33 996 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Jasper_lee 0:b16d94660a33 997 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Jasper_lee 0:b16d94660a33 998 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Jasper_lee 0:b16d94660a33 999 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Jasper_lee 0:b16d94660a33 1000 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Jasper_lee 0:b16d94660a33 1001 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Jasper_lee 0:b16d94660a33 1002 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Jasper_lee 0:b16d94660a33 1003 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Jasper_lee 0:b16d94660a33 1004
Jasper_lee 0:b16d94660a33 1005 /******************** Bit definition for CAN_ESR register *******************/
Jasper_lee 0:b16d94660a33 1006 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Jasper_lee 0:b16d94660a33 1007 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Jasper_lee 0:b16d94660a33 1008 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Jasper_lee 0:b16d94660a33 1009
Jasper_lee 0:b16d94660a33 1010 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Jasper_lee 0:b16d94660a33 1011 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 1012 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 1013 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 1014
Jasper_lee 0:b16d94660a33 1015 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Jasper_lee 0:b16d94660a33 1016 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Jasper_lee 0:b16d94660a33 1017
Jasper_lee 0:b16d94660a33 1018 /******************* Bit definition for CAN_BTR register ********************/
Jasper_lee 0:b16d94660a33 1019 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Jasper_lee 0:b16d94660a33 1020 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Jasper_lee 0:b16d94660a33 1021 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
Jasper_lee 0:b16d94660a33 1022 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
Jasper_lee 0:b16d94660a33 1023 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
Jasper_lee 0:b16d94660a33 1024 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
Jasper_lee 0:b16d94660a33 1025 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Jasper_lee 0:b16d94660a33 1026 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
Jasper_lee 0:b16d94660a33 1027 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
Jasper_lee 0:b16d94660a33 1028 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
Jasper_lee 0:b16d94660a33 1029 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Jasper_lee 0:b16d94660a33 1030 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
Jasper_lee 0:b16d94660a33 1031 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
Jasper_lee 0:b16d94660a33 1032 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Jasper_lee 0:b16d94660a33 1033 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Jasper_lee 0:b16d94660a33 1034
Jasper_lee 0:b16d94660a33 1035 /*!<Mailbox registers */
Jasper_lee 0:b16d94660a33 1036 /****************** Bit definition for CAN_TI0R register ********************/
Jasper_lee 0:b16d94660a33 1037 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Jasper_lee 0:b16d94660a33 1038 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Jasper_lee 0:b16d94660a33 1039 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Jasper_lee 0:b16d94660a33 1040 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Jasper_lee 0:b16d94660a33 1041 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Jasper_lee 0:b16d94660a33 1042
Jasper_lee 0:b16d94660a33 1043 /****************** Bit definition for CAN_TDT0R register *******************/
Jasper_lee 0:b16d94660a33 1044 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Jasper_lee 0:b16d94660a33 1045 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Jasper_lee 0:b16d94660a33 1046 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Jasper_lee 0:b16d94660a33 1047
Jasper_lee 0:b16d94660a33 1048 /****************** Bit definition for CAN_TDL0R register *******************/
Jasper_lee 0:b16d94660a33 1049 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Jasper_lee 0:b16d94660a33 1050 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Jasper_lee 0:b16d94660a33 1051 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Jasper_lee 0:b16d94660a33 1052 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Jasper_lee 0:b16d94660a33 1053
Jasper_lee 0:b16d94660a33 1054 /****************** Bit definition for CAN_TDH0R register *******************/
Jasper_lee 0:b16d94660a33 1055 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Jasper_lee 0:b16d94660a33 1056 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Jasper_lee 0:b16d94660a33 1057 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Jasper_lee 0:b16d94660a33 1058 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Jasper_lee 0:b16d94660a33 1059
Jasper_lee 0:b16d94660a33 1060 /******************* Bit definition for CAN_TI1R register *******************/
Jasper_lee 0:b16d94660a33 1061 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Jasper_lee 0:b16d94660a33 1062 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Jasper_lee 0:b16d94660a33 1063 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Jasper_lee 0:b16d94660a33 1064 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Jasper_lee 0:b16d94660a33 1065 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Jasper_lee 0:b16d94660a33 1066
Jasper_lee 0:b16d94660a33 1067 /******************* Bit definition for CAN_TDT1R register ******************/
Jasper_lee 0:b16d94660a33 1068 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Jasper_lee 0:b16d94660a33 1069 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Jasper_lee 0:b16d94660a33 1070 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Jasper_lee 0:b16d94660a33 1071
Jasper_lee 0:b16d94660a33 1072 /******************* Bit definition for CAN_TDL1R register ******************/
Jasper_lee 0:b16d94660a33 1073 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Jasper_lee 0:b16d94660a33 1074 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Jasper_lee 0:b16d94660a33 1075 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Jasper_lee 0:b16d94660a33 1076 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Jasper_lee 0:b16d94660a33 1077
Jasper_lee 0:b16d94660a33 1078 /******************* Bit definition for CAN_TDH1R register ******************/
Jasper_lee 0:b16d94660a33 1079 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Jasper_lee 0:b16d94660a33 1080 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Jasper_lee 0:b16d94660a33 1081 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Jasper_lee 0:b16d94660a33 1082 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Jasper_lee 0:b16d94660a33 1083
Jasper_lee 0:b16d94660a33 1084 /******************* Bit definition for CAN_TI2R register *******************/
Jasper_lee 0:b16d94660a33 1085 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Jasper_lee 0:b16d94660a33 1086 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Jasper_lee 0:b16d94660a33 1087 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Jasper_lee 0:b16d94660a33 1088 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Jasper_lee 0:b16d94660a33 1089 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Jasper_lee 0:b16d94660a33 1090
Jasper_lee 0:b16d94660a33 1091 /******************* Bit definition for CAN_TDT2R register ******************/
Jasper_lee 0:b16d94660a33 1092 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Jasper_lee 0:b16d94660a33 1093 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Jasper_lee 0:b16d94660a33 1094 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Jasper_lee 0:b16d94660a33 1095
Jasper_lee 0:b16d94660a33 1096 /******************* Bit definition for CAN_TDL2R register ******************/
Jasper_lee 0:b16d94660a33 1097 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Jasper_lee 0:b16d94660a33 1098 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Jasper_lee 0:b16d94660a33 1099 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Jasper_lee 0:b16d94660a33 1100 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Jasper_lee 0:b16d94660a33 1101
Jasper_lee 0:b16d94660a33 1102 /******************* Bit definition for CAN_TDH2R register ******************/
Jasper_lee 0:b16d94660a33 1103 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Jasper_lee 0:b16d94660a33 1104 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Jasper_lee 0:b16d94660a33 1105 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Jasper_lee 0:b16d94660a33 1106 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Jasper_lee 0:b16d94660a33 1107
Jasper_lee 0:b16d94660a33 1108 /******************* Bit definition for CAN_RI0R register *******************/
Jasper_lee 0:b16d94660a33 1109 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Jasper_lee 0:b16d94660a33 1110 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Jasper_lee 0:b16d94660a33 1111 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Jasper_lee 0:b16d94660a33 1112 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Jasper_lee 0:b16d94660a33 1113
Jasper_lee 0:b16d94660a33 1114 /******************* Bit definition for CAN_RDT0R register ******************/
Jasper_lee 0:b16d94660a33 1115 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Jasper_lee 0:b16d94660a33 1116 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Jasper_lee 0:b16d94660a33 1117 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Jasper_lee 0:b16d94660a33 1118
Jasper_lee 0:b16d94660a33 1119 /******************* Bit definition for CAN_RDL0R register ******************/
Jasper_lee 0:b16d94660a33 1120 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Jasper_lee 0:b16d94660a33 1121 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Jasper_lee 0:b16d94660a33 1122 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Jasper_lee 0:b16d94660a33 1123 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Jasper_lee 0:b16d94660a33 1124
Jasper_lee 0:b16d94660a33 1125 /******************* Bit definition for CAN_RDH0R register ******************/
Jasper_lee 0:b16d94660a33 1126 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Jasper_lee 0:b16d94660a33 1127 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Jasper_lee 0:b16d94660a33 1128 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Jasper_lee 0:b16d94660a33 1129 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Jasper_lee 0:b16d94660a33 1130
Jasper_lee 0:b16d94660a33 1131 /******************* Bit definition for CAN_RI1R register *******************/
Jasper_lee 0:b16d94660a33 1132 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Jasper_lee 0:b16d94660a33 1133 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Jasper_lee 0:b16d94660a33 1134 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Jasper_lee 0:b16d94660a33 1135 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Jasper_lee 0:b16d94660a33 1136
Jasper_lee 0:b16d94660a33 1137 /******************* Bit definition for CAN_RDT1R register ******************/
Jasper_lee 0:b16d94660a33 1138 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Jasper_lee 0:b16d94660a33 1139 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Jasper_lee 0:b16d94660a33 1140 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Jasper_lee 0:b16d94660a33 1141
Jasper_lee 0:b16d94660a33 1142 /******************* Bit definition for CAN_RDL1R register ******************/
Jasper_lee 0:b16d94660a33 1143 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Jasper_lee 0:b16d94660a33 1144 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Jasper_lee 0:b16d94660a33 1145 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Jasper_lee 0:b16d94660a33 1146 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Jasper_lee 0:b16d94660a33 1147
Jasper_lee 0:b16d94660a33 1148 /******************* Bit definition for CAN_RDH1R register ******************/
Jasper_lee 0:b16d94660a33 1149 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Jasper_lee 0:b16d94660a33 1150 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Jasper_lee 0:b16d94660a33 1151 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Jasper_lee 0:b16d94660a33 1152 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Jasper_lee 0:b16d94660a33 1153
Jasper_lee 0:b16d94660a33 1154 /*!<CAN filter registers */
Jasper_lee 0:b16d94660a33 1155 /******************* Bit definition for CAN_FMR register ********************/
Jasper_lee 0:b16d94660a33 1156 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
Jasper_lee 0:b16d94660a33 1157
Jasper_lee 0:b16d94660a33 1158 /******************* Bit definition for CAN_FM1R register *******************/
Jasper_lee 0:b16d94660a33 1159 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
Jasper_lee 0:b16d94660a33 1160 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
Jasper_lee 0:b16d94660a33 1161 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
Jasper_lee 0:b16d94660a33 1162 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
Jasper_lee 0:b16d94660a33 1163 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
Jasper_lee 0:b16d94660a33 1164 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
Jasper_lee 0:b16d94660a33 1165 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
Jasper_lee 0:b16d94660a33 1166 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
Jasper_lee 0:b16d94660a33 1167 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
Jasper_lee 0:b16d94660a33 1168 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
Jasper_lee 0:b16d94660a33 1169 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
Jasper_lee 0:b16d94660a33 1170 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
Jasper_lee 0:b16d94660a33 1171 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
Jasper_lee 0:b16d94660a33 1172 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
Jasper_lee 0:b16d94660a33 1173 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
Jasper_lee 0:b16d94660a33 1174
Jasper_lee 0:b16d94660a33 1175 /******************* Bit definition for CAN_FS1R register *******************/
Jasper_lee 0:b16d94660a33 1176 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
Jasper_lee 0:b16d94660a33 1177 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Jasper_lee 0:b16d94660a33 1178 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Jasper_lee 0:b16d94660a33 1179 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Jasper_lee 0:b16d94660a33 1180 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Jasper_lee 0:b16d94660a33 1181 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Jasper_lee 0:b16d94660a33 1182 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Jasper_lee 0:b16d94660a33 1183 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Jasper_lee 0:b16d94660a33 1184 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Jasper_lee 0:b16d94660a33 1185 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Jasper_lee 0:b16d94660a33 1186 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Jasper_lee 0:b16d94660a33 1187 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Jasper_lee 0:b16d94660a33 1188 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Jasper_lee 0:b16d94660a33 1189 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Jasper_lee 0:b16d94660a33 1190 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Jasper_lee 0:b16d94660a33 1191
Jasper_lee 0:b16d94660a33 1192 /****************** Bit definition for CAN_FFA1R register *******************/
Jasper_lee 0:b16d94660a33 1193 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
Jasper_lee 0:b16d94660a33 1194 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
Jasper_lee 0:b16d94660a33 1195 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
Jasper_lee 0:b16d94660a33 1196 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
Jasper_lee 0:b16d94660a33 1197 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
Jasper_lee 0:b16d94660a33 1198 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
Jasper_lee 0:b16d94660a33 1199 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
Jasper_lee 0:b16d94660a33 1200 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
Jasper_lee 0:b16d94660a33 1201 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
Jasper_lee 0:b16d94660a33 1202 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
Jasper_lee 0:b16d94660a33 1203 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
Jasper_lee 0:b16d94660a33 1204 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
Jasper_lee 0:b16d94660a33 1205 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
Jasper_lee 0:b16d94660a33 1206 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
Jasper_lee 0:b16d94660a33 1207 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
Jasper_lee 0:b16d94660a33 1208
Jasper_lee 0:b16d94660a33 1209 /******************* Bit definition for CAN_FA1R register *******************/
Jasper_lee 0:b16d94660a33 1210 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
Jasper_lee 0:b16d94660a33 1211 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
Jasper_lee 0:b16d94660a33 1212 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
Jasper_lee 0:b16d94660a33 1213 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
Jasper_lee 0:b16d94660a33 1214 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
Jasper_lee 0:b16d94660a33 1215 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
Jasper_lee 0:b16d94660a33 1216 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
Jasper_lee 0:b16d94660a33 1217 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
Jasper_lee 0:b16d94660a33 1218 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
Jasper_lee 0:b16d94660a33 1219 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
Jasper_lee 0:b16d94660a33 1220 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
Jasper_lee 0:b16d94660a33 1221 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
Jasper_lee 0:b16d94660a33 1222 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
Jasper_lee 0:b16d94660a33 1223 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
Jasper_lee 0:b16d94660a33 1224 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
Jasper_lee 0:b16d94660a33 1225
Jasper_lee 0:b16d94660a33 1226 /******************* Bit definition for CAN_F0R1 register *******************/
Jasper_lee 0:b16d94660a33 1227 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1228 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1229 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1230 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1231 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1232 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1233 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1234 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1235 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1236 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1237 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1238 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1239 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1240 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1241 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1242 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1243 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1244 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1245 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1246 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1247 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1248 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1249 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1250 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1251 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1252 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1253 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1254 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1255 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1256 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1257 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1258 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1259
Jasper_lee 0:b16d94660a33 1260 /******************* Bit definition for CAN_F1R1 register *******************/
Jasper_lee 0:b16d94660a33 1261 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1262 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1263 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1264 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1265 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1266 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1267 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1268 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1269 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1270 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1271 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1272 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1273 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1274 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1275 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1276 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1277 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1278 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1279 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1280 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1281 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1282 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1283 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1284 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1285 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1286 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1287 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1288 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1289 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1290 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1291 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1292 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1293
Jasper_lee 0:b16d94660a33 1294 /******************* Bit definition for CAN_F2R1 register *******************/
Jasper_lee 0:b16d94660a33 1295 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1296 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1297 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1298 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1299 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1300 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1301 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1302 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1303 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1304 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1305 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1306 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1307 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1308 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1309 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1310 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1311 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1312 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1313 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1314 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1315 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1316 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1317 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1318 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1319 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1320 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1321 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1322 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1323 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1324 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1325 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1326 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1327
Jasper_lee 0:b16d94660a33 1328 /******************* Bit definition for CAN_F3R1 register *******************/
Jasper_lee 0:b16d94660a33 1329 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1330 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1331 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1332 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1333 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1334 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1335 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1336 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1337 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1338 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1339 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1340 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1341 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1342 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1343 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1344 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1345 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1346 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1347 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1348 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1349 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1350 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1351 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1352 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1353 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1354 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1355 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1356 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1357 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1358 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1359 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1360 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1361
Jasper_lee 0:b16d94660a33 1362 /******************* Bit definition for CAN_F4R1 register *******************/
Jasper_lee 0:b16d94660a33 1363 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1364 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1365 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1366 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1367 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1368 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1369 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1370 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1371 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1372 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1373 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1374 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1375 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1376 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1377 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1378 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1379 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1380 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1381 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1382 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1383 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1384 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1385 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1386 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1387 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1388 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1389 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1390 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1391 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1392 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1393 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1394 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1395
Jasper_lee 0:b16d94660a33 1396 /******************* Bit definition for CAN_F5R1 register *******************/
Jasper_lee 0:b16d94660a33 1397 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1398 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1399 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1400 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1401 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1402 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1403 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1404 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1405 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1406 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1407 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1408 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1409 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1410 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1411 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1412 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1413 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1414 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1415 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1416 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1417 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1418 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1419 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1420 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1421 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1422 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1423 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1424 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1425 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1426 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1427 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1428 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1429
Jasper_lee 0:b16d94660a33 1430 /******************* Bit definition for CAN_F6R1 register *******************/
Jasper_lee 0:b16d94660a33 1431 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1432 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1433 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1434 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1435 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1436 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1437 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1438 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1439 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1440 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1441 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1442 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1443 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1444 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1445 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1446 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1447 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1448 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1449 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1450 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1451 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1452 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1453 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1454 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1455 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1456 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1457 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1458 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1459 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1460 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1461 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1462 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1463
Jasper_lee 0:b16d94660a33 1464 /******************* Bit definition for CAN_F7R1 register *******************/
Jasper_lee 0:b16d94660a33 1465 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1466 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1467 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1468 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1469 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1470 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1471 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1472 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1473 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1474 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1475 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1476 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1477 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1478 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1479 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1480 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1481 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1482 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1483 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1484 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1485 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1486 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1487 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1488 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1489 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1490 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1491 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1492 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1493 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1494 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1495 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1496 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1497
Jasper_lee 0:b16d94660a33 1498 /******************* Bit definition for CAN_F8R1 register *******************/
Jasper_lee 0:b16d94660a33 1499 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1500 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1501 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1502 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1503 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1504 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1505 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1506 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1507 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1508 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1509 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1510 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1511 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1512 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1513 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1514 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1515 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1516 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1517 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1518 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1519 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1520 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1521 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1522 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1523 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1524 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1525 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1526 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1527 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1528 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1529 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1530 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1531
Jasper_lee 0:b16d94660a33 1532 /******************* Bit definition for CAN_F9R1 register *******************/
Jasper_lee 0:b16d94660a33 1533 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1534 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1535 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1536 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1537 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1538 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1539 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1540 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1541 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1542 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1543 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1544 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1545 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1546 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1547 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1548 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1549 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1550 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1551 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1552 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1553 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1554 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1555 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1556 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1557 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1558 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1559 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1560 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1561 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1562 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1563 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1564 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1565
Jasper_lee 0:b16d94660a33 1566 /******************* Bit definition for CAN_F10R1 register ******************/
Jasper_lee 0:b16d94660a33 1567 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1568 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1569 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1570 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1571 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1572 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1573 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1574 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1575 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1576 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1577 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1578 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1579 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1580 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1581 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1582 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1583 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1584 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1585 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1586 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1587 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1588 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1589 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1590 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1591 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1592 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1593 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1594 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1595 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1596 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1597 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1598 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1599
Jasper_lee 0:b16d94660a33 1600 /******************* Bit definition for CAN_F11R1 register ******************/
Jasper_lee 0:b16d94660a33 1601 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1602 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1603 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1604 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1605 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1606 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1607 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1608 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1609 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1610 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1611 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1612 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1613 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1614 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1615 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1616 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1617 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1618 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1619 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1620 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1621 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1622 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1623 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1624 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1625 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1626 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1627 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1628 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1629 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1630 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1631 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1632 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1633
Jasper_lee 0:b16d94660a33 1634 /******************* Bit definition for CAN_F12R1 register ******************/
Jasper_lee 0:b16d94660a33 1635 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1636 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1637 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1638 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1639 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1640 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1641 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1642 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1643 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1644 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1645 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1646 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1647 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1648 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1649 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1650 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1651 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1652 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1653 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1654 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1655 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1656 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1657 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1658 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1659 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1660 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1661 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1662 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1663 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1664 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1665 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1666 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1667
Jasper_lee 0:b16d94660a33 1668 /******************* Bit definition for CAN_F13R1 register ******************/
Jasper_lee 0:b16d94660a33 1669 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1670 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1671 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1672 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1673 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1674 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1675 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1676 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1677 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1678 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1679 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1680 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1681 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1682 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1683 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1684 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1685 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1686 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1687 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1688 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1689 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1690 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1691 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1692 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1693 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1694 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1695 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1696 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1697 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1698 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1699 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1700 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1701
Jasper_lee 0:b16d94660a33 1702 /******************* Bit definition for CAN_F0R2 register *******************/
Jasper_lee 0:b16d94660a33 1703 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1704 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1705 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1706 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1707 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1708 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1709 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1710 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1711 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1712 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1713 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1714 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1715 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1716 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1717 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1718 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1719 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1720 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1721 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1722 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1723 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1724 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1725 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1726 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1727 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1728 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1729 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1730 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1731 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1732 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1733 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1734 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1735
Jasper_lee 0:b16d94660a33 1736 /******************* Bit definition for CAN_F1R2 register *******************/
Jasper_lee 0:b16d94660a33 1737 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1738 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1739 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1740 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1741 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1742 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1743 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1744 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1745 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1746 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1747 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1748 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1749 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1750 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1751 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1752 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1753 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1754 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1755 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1756 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1757 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1758 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1759 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1760 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1761 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1762 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1763 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1764 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1765 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1766 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1767 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1768 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1769
Jasper_lee 0:b16d94660a33 1770 /******************* Bit definition for CAN_F2R2 register *******************/
Jasper_lee 0:b16d94660a33 1771 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1772 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1773 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1774 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1775 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1776 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1777 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1778 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1779 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1780 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1781 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1782 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1783 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1784 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1785 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1786 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1787 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1788 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1789 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1790 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1791 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1792 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1793 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1794 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1795 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1796 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1797 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1798 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1799 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1800 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1801 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1802 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1803
Jasper_lee 0:b16d94660a33 1804 /******************* Bit definition for CAN_F3R2 register *******************/
Jasper_lee 0:b16d94660a33 1805 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1806 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1807 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1808 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1809 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1810 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1811 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1812 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1813 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1814 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1815 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1816 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1817 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1818 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1819 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1820 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1821 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1822 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1823 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1824 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1825 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1826 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1827 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1828 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1829 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1830 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1831 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1832 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1833 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1834 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1835 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1836 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1837
Jasper_lee 0:b16d94660a33 1838 /******************* Bit definition for CAN_F4R2 register *******************/
Jasper_lee 0:b16d94660a33 1839 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1840 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1841 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1842 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1843 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1844 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1845 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1846 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1847 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1848 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1849 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1850 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1851 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1852 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1853 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1854 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1855 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1856 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1857 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1858 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1859 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1860 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1861 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1862 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1863 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1864 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1865 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1866 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1867 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1868 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1869 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1870 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1871
Jasper_lee 0:b16d94660a33 1872 /******************* Bit definition for CAN_F5R2 register *******************/
Jasper_lee 0:b16d94660a33 1873 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1874 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1875 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1876 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1877 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1878 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1879 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1880 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1881 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1882 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1883 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1884 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1885 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1886 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1887 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1888 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1889 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1890 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1891 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1892 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1893 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1894 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1895 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1896 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1897 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1898 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1899 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1900 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1901 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1902 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1903 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1904 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1905
Jasper_lee 0:b16d94660a33 1906 /******************* Bit definition for CAN_F6R2 register *******************/
Jasper_lee 0:b16d94660a33 1907 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1908 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1909 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1910 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1911 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1912 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1913 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1914 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1915 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1916 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1917 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1918 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1919 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1920 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1921 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1922 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1923 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1924 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1925 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1926 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1927 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1928 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1929 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1930 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1931 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1932 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1933 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1934 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1935 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1936 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1937 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1938 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1939
Jasper_lee 0:b16d94660a33 1940 /******************* Bit definition for CAN_F7R2 register *******************/
Jasper_lee 0:b16d94660a33 1941 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1942 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1943 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1944 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1945 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1946 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1947 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1948 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1949 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1950 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1951 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1952 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1953 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1954 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1955 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1956 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1957 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1958 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1959 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1960 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1961 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1962 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1963 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1964 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1965 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 1966 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 1967 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 1968 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 1969 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 1970 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 1971 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 1972 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 1973
Jasper_lee 0:b16d94660a33 1974 /******************* Bit definition for CAN_F8R2 register *******************/
Jasper_lee 0:b16d94660a33 1975 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 1976 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 1977 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 1978 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 1979 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 1980 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 1981 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 1982 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 1983 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 1984 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 1985 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 1986 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 1987 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 1988 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 1989 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 1990 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 1991 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 1992 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 1993 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 1994 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 1995 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 1996 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 1997 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 1998 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 1999 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2000 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2001 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2002 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2003 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2004 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2005 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2006 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2007
Jasper_lee 0:b16d94660a33 2008 /******************* Bit definition for CAN_F9R2 register *******************/
Jasper_lee 0:b16d94660a33 2009 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 2010 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 2011 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 2012 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 2013 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 2014 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 2015 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 2016 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 2017 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 2018 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 2019 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 2020 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 2021 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 2022 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 2023 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 2024 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 2025 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 2026 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 2027 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 2028 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 2029 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 2030 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 2031 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 2032 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 2033 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2034 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2035 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2036 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2037 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2038 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2039 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2040 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2041
Jasper_lee 0:b16d94660a33 2042 /******************* Bit definition for CAN_F10R2 register ******************/
Jasper_lee 0:b16d94660a33 2043 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 2044 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 2045 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 2046 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 2047 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 2048 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 2049 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 2050 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 2051 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 2052 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 2053 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 2054 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 2055 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 2056 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 2057 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 2058 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 2059 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 2060 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 2061 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 2062 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 2063 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 2064 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 2065 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 2066 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 2067 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2068 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2069 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2070 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2071 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2072 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2073 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2074 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2075
Jasper_lee 0:b16d94660a33 2076 /******************* Bit definition for CAN_F11R2 register ******************/
Jasper_lee 0:b16d94660a33 2077 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 2078 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 2079 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 2080 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 2081 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 2082 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 2083 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 2084 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 2085 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 2086 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 2087 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 2088 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 2089 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 2090 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 2091 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 2092 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 2093 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 2094 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 2095 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 2096 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 2097 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 2098 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 2099 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 2100 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 2101 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2102 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2103 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2104 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2105 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2106 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2107 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2108 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2109
Jasper_lee 0:b16d94660a33 2110 /******************* Bit definition for CAN_F12R2 register ******************/
Jasper_lee 0:b16d94660a33 2111 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 2112 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 2113 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 2114 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 2115 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 2116 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 2117 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 2118 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 2119 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 2120 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 2121 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 2122 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 2123 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 2124 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 2125 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 2126 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 2127 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 2128 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 2129 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 2130 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 2131 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 2132 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 2133 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 2134 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 2135 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2136 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2137 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2138 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2139 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2140 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2141 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2142 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2143
Jasper_lee 0:b16d94660a33 2144 /******************* Bit definition for CAN_F13R2 register ******************/
Jasper_lee 0:b16d94660a33 2145 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Jasper_lee 0:b16d94660a33 2146 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Jasper_lee 0:b16d94660a33 2147 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Jasper_lee 0:b16d94660a33 2148 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Jasper_lee 0:b16d94660a33 2149 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Jasper_lee 0:b16d94660a33 2150 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Jasper_lee 0:b16d94660a33 2151 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Jasper_lee 0:b16d94660a33 2152 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Jasper_lee 0:b16d94660a33 2153 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Jasper_lee 0:b16d94660a33 2154 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Jasper_lee 0:b16d94660a33 2155 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Jasper_lee 0:b16d94660a33 2156 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Jasper_lee 0:b16d94660a33 2157 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Jasper_lee 0:b16d94660a33 2158 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Jasper_lee 0:b16d94660a33 2159 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Jasper_lee 0:b16d94660a33 2160 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Jasper_lee 0:b16d94660a33 2161 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Jasper_lee 0:b16d94660a33 2162 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Jasper_lee 0:b16d94660a33 2163 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Jasper_lee 0:b16d94660a33 2164 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Jasper_lee 0:b16d94660a33 2165 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Jasper_lee 0:b16d94660a33 2166 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Jasper_lee 0:b16d94660a33 2167 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Jasper_lee 0:b16d94660a33 2168 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Jasper_lee 0:b16d94660a33 2169 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Jasper_lee 0:b16d94660a33 2170 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Jasper_lee 0:b16d94660a33 2171 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Jasper_lee 0:b16d94660a33 2172 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Jasper_lee 0:b16d94660a33 2173 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Jasper_lee 0:b16d94660a33 2174 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Jasper_lee 0:b16d94660a33 2175 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Jasper_lee 0:b16d94660a33 2176 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Jasper_lee 0:b16d94660a33 2177
Jasper_lee 0:b16d94660a33 2178 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2179 /* */
Jasper_lee 0:b16d94660a33 2180 /* HDMI-CEC (CEC) */
Jasper_lee 0:b16d94660a33 2181 /* */
Jasper_lee 0:b16d94660a33 2182 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2183
Jasper_lee 0:b16d94660a33 2184 /******************* Bit definition for CEC_CR register *********************/
Jasper_lee 0:b16d94660a33 2185 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
Jasper_lee 0:b16d94660a33 2186 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
Jasper_lee 0:b16d94660a33 2187 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
Jasper_lee 0:b16d94660a33 2188
Jasper_lee 0:b16d94660a33 2189 /******************* Bit definition for CEC_CFGR register *******************/
Jasper_lee 0:b16d94660a33 2190 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
Jasper_lee 0:b16d94660a33 2191 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
Jasper_lee 0:b16d94660a33 2192 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
Jasper_lee 0:b16d94660a33 2193 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
Jasper_lee 0:b16d94660a33 2194 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
Jasper_lee 0:b16d94660a33 2195 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
Jasper_lee 0:b16d94660a33 2196 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
Jasper_lee 0:b16d94660a33 2197 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
Jasper_lee 0:b16d94660a33 2198 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
Jasper_lee 0:b16d94660a33 2199
Jasper_lee 0:b16d94660a33 2200 /******************* Bit definition for CEC_TXDR register *******************/
Jasper_lee 0:b16d94660a33 2201 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
Jasper_lee 0:b16d94660a33 2202
Jasper_lee 0:b16d94660a33 2203 /******************* Bit definition for CEC_RXDR register *******************/
Jasper_lee 0:b16d94660a33 2204 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
Jasper_lee 0:b16d94660a33 2205
Jasper_lee 0:b16d94660a33 2206 /******************* Bit definition for CEC_ISR register ********************/
Jasper_lee 0:b16d94660a33 2207 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
Jasper_lee 0:b16d94660a33 2208 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
Jasper_lee 0:b16d94660a33 2209 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
Jasper_lee 0:b16d94660a33 2210 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
Jasper_lee 0:b16d94660a33 2211 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
Jasper_lee 0:b16d94660a33 2212 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
Jasper_lee 0:b16d94660a33 2213 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
Jasper_lee 0:b16d94660a33 2214 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
Jasper_lee 0:b16d94660a33 2215 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
Jasper_lee 0:b16d94660a33 2216 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
Jasper_lee 0:b16d94660a33 2217 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
Jasper_lee 0:b16d94660a33 2218 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
Jasper_lee 0:b16d94660a33 2219 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
Jasper_lee 0:b16d94660a33 2220
Jasper_lee 0:b16d94660a33 2221 /******************* Bit definition for CEC_IER register ********************/
Jasper_lee 0:b16d94660a33 2222 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
Jasper_lee 0:b16d94660a33 2223 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
Jasper_lee 0:b16d94660a33 2224 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
Jasper_lee 0:b16d94660a33 2225 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
Jasper_lee 0:b16d94660a33 2226 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
Jasper_lee 0:b16d94660a33 2227 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
Jasper_lee 0:b16d94660a33 2228 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
Jasper_lee 0:b16d94660a33 2229 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
Jasper_lee 0:b16d94660a33 2230 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
Jasper_lee 0:b16d94660a33 2231 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
Jasper_lee 0:b16d94660a33 2232 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
Jasper_lee 0:b16d94660a33 2233 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
Jasper_lee 0:b16d94660a33 2234 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
Jasper_lee 0:b16d94660a33 2235
Jasper_lee 0:b16d94660a33 2236
Jasper_lee 0:b16d94660a33 2237 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2238 /* */
Jasper_lee 0:b16d94660a33 2239 /* Analog Comparators (COMP) */
Jasper_lee 0:b16d94660a33 2240 /* */
Jasper_lee 0:b16d94660a33 2241 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2242 /*********************** Bit definition for COMP_CSR register ***************/
Jasper_lee 0:b16d94660a33 2243 /* COMP1 bits definition */
Jasper_lee 0:b16d94660a33 2244 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
Jasper_lee 0:b16d94660a33 2245 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
Jasper_lee 0:b16d94660a33 2246 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
Jasper_lee 0:b16d94660a33 2247 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
Jasper_lee 0:b16d94660a33 2248 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
Jasper_lee 0:b16d94660a33 2249 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
Jasper_lee 0:b16d94660a33 2250 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
Jasper_lee 0:b16d94660a33 2251 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
Jasper_lee 0:b16d94660a33 2252 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
Jasper_lee 0:b16d94660a33 2253 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
Jasper_lee 0:b16d94660a33 2254 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
Jasper_lee 0:b16d94660a33 2255 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
Jasper_lee 0:b16d94660a33 2256 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
Jasper_lee 0:b16d94660a33 2257 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
Jasper_lee 0:b16d94660a33 2258 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
Jasper_lee 0:b16d94660a33 2259 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
Jasper_lee 0:b16d94660a33 2260 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
Jasper_lee 0:b16d94660a33 2261 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
Jasper_lee 0:b16d94660a33 2262 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
Jasper_lee 0:b16d94660a33 2263 /* COMP2 bits definition */
Jasper_lee 0:b16d94660a33 2264 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
Jasper_lee 0:b16d94660a33 2265 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
Jasper_lee 0:b16d94660a33 2266 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
Jasper_lee 0:b16d94660a33 2267 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
Jasper_lee 0:b16d94660a33 2268 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
Jasper_lee 0:b16d94660a33 2269 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
Jasper_lee 0:b16d94660a33 2270 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
Jasper_lee 0:b16d94660a33 2271 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
Jasper_lee 0:b16d94660a33 2272 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
Jasper_lee 0:b16d94660a33 2273 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
Jasper_lee 0:b16d94660a33 2274 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
Jasper_lee 0:b16d94660a33 2275 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
Jasper_lee 0:b16d94660a33 2276 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
Jasper_lee 0:b16d94660a33 2277 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
Jasper_lee 0:b16d94660a33 2278 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
Jasper_lee 0:b16d94660a33 2279 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
Jasper_lee 0:b16d94660a33 2280 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
Jasper_lee 0:b16d94660a33 2281 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
Jasper_lee 0:b16d94660a33 2282 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
Jasper_lee 0:b16d94660a33 2283 /* COMPx bits definition */
Jasper_lee 0:b16d94660a33 2284 #define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
Jasper_lee 0:b16d94660a33 2285 #define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
Jasper_lee 0:b16d94660a33 2286 #define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
Jasper_lee 0:b16d94660a33 2287 #define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
Jasper_lee 0:b16d94660a33 2288 #define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
Jasper_lee 0:b16d94660a33 2289 #define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
Jasper_lee 0:b16d94660a33 2290 #define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
Jasper_lee 0:b16d94660a33 2291 #define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
Jasper_lee 0:b16d94660a33 2292 #define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
Jasper_lee 0:b16d94660a33 2293 #define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
Jasper_lee 0:b16d94660a33 2294 #define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
Jasper_lee 0:b16d94660a33 2295 #define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
Jasper_lee 0:b16d94660a33 2296 #define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
Jasper_lee 0:b16d94660a33 2297 #define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
Jasper_lee 0:b16d94660a33 2298 #define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
Jasper_lee 0:b16d94660a33 2299 #define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
Jasper_lee 0:b16d94660a33 2300 #define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
Jasper_lee 0:b16d94660a33 2301 #define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
Jasper_lee 0:b16d94660a33 2302
Jasper_lee 0:b16d94660a33 2303 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2304 /* */
Jasper_lee 0:b16d94660a33 2305 /* CRC calculation unit (CRC) */
Jasper_lee 0:b16d94660a33 2306 /* */
Jasper_lee 0:b16d94660a33 2307 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2308 /******************* Bit definition for CRC_DR register *********************/
Jasper_lee 0:b16d94660a33 2309 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Jasper_lee 0:b16d94660a33 2310
Jasper_lee 0:b16d94660a33 2311 /******************* Bit definition for CRC_IDR register ********************/
Jasper_lee 0:b16d94660a33 2312 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
Jasper_lee 0:b16d94660a33 2313
Jasper_lee 0:b16d94660a33 2314 /******************** Bit definition for CRC_CR register ********************/
Jasper_lee 0:b16d94660a33 2315 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Jasper_lee 0:b16d94660a33 2316 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
Jasper_lee 0:b16d94660a33 2317 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
Jasper_lee 0:b16d94660a33 2318 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
Jasper_lee 0:b16d94660a33 2319 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Jasper_lee 0:b16d94660a33 2320 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
Jasper_lee 0:b16d94660a33 2321 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
Jasper_lee 0:b16d94660a33 2322 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Jasper_lee 0:b16d94660a33 2323
Jasper_lee 0:b16d94660a33 2324 /******************* Bit definition for CRC_INIT register *******************/
Jasper_lee 0:b16d94660a33 2325 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Jasper_lee 0:b16d94660a33 2326
Jasper_lee 0:b16d94660a33 2327 /******************* Bit definition for CRC_POL register ********************/
Jasper_lee 0:b16d94660a33 2328 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
Jasper_lee 0:b16d94660a33 2329
Jasper_lee 0:b16d94660a33 2330 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2331 /* */
Jasper_lee 0:b16d94660a33 2332 /* CRS Clock Recovery System */
Jasper_lee 0:b16d94660a33 2333 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2334
Jasper_lee 0:b16d94660a33 2335 /******************* Bit definition for CRS_CR register *********************/
Jasper_lee 0:b16d94660a33 2336 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
Jasper_lee 0:b16d94660a33 2337 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
Jasper_lee 0:b16d94660a33 2338 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
Jasper_lee 0:b16d94660a33 2339 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
Jasper_lee 0:b16d94660a33 2340 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
Jasper_lee 0:b16d94660a33 2341 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
Jasper_lee 0:b16d94660a33 2342 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
Jasper_lee 0:b16d94660a33 2343 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
Jasper_lee 0:b16d94660a33 2344
Jasper_lee 0:b16d94660a33 2345 /******************* Bit definition for CRS_CFGR register *********************/
Jasper_lee 0:b16d94660a33 2346 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
Jasper_lee 0:b16d94660a33 2347 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
Jasper_lee 0:b16d94660a33 2348
Jasper_lee 0:b16d94660a33 2349 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
Jasper_lee 0:b16d94660a33 2350 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
Jasper_lee 0:b16d94660a33 2351 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
Jasper_lee 0:b16d94660a33 2352 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
Jasper_lee 0:b16d94660a33 2353
Jasper_lee 0:b16d94660a33 2354 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
Jasper_lee 0:b16d94660a33 2355 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
Jasper_lee 0:b16d94660a33 2356 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
Jasper_lee 0:b16d94660a33 2357
Jasper_lee 0:b16d94660a33 2358 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
Jasper_lee 0:b16d94660a33 2359
Jasper_lee 0:b16d94660a33 2360 /******************* Bit definition for CRS_ISR register *********************/
Jasper_lee 0:b16d94660a33 2361 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
Jasper_lee 0:b16d94660a33 2362 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
Jasper_lee 0:b16d94660a33 2363 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
Jasper_lee 0:b16d94660a33 2364 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
Jasper_lee 0:b16d94660a33 2365 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
Jasper_lee 0:b16d94660a33 2366 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
Jasper_lee 0:b16d94660a33 2367 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
Jasper_lee 0:b16d94660a33 2368 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
Jasper_lee 0:b16d94660a33 2369 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
Jasper_lee 0:b16d94660a33 2370
Jasper_lee 0:b16d94660a33 2371 /******************* Bit definition for CRS_ICR register *********************/
Jasper_lee 0:b16d94660a33 2372 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
Jasper_lee 0:b16d94660a33 2373 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
Jasper_lee 0:b16d94660a33 2374 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
Jasper_lee 0:b16d94660a33 2375 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
Jasper_lee 0:b16d94660a33 2376
Jasper_lee 0:b16d94660a33 2377 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2378 /* */
Jasper_lee 0:b16d94660a33 2379 /* Digital to Analog Converter (DAC) */
Jasper_lee 0:b16d94660a33 2380 /* */
Jasper_lee 0:b16d94660a33 2381 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2382 /******************** Bit definition for DAC_CR register ********************/
Jasper_lee 0:b16d94660a33 2383 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
Jasper_lee 0:b16d94660a33 2384 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
Jasper_lee 0:b16d94660a33 2385 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
Jasper_lee 0:b16d94660a33 2386
Jasper_lee 0:b16d94660a33 2387 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Jasper_lee 0:b16d94660a33 2388 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2389 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2390 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 2391
Jasper_lee 0:b16d94660a33 2392 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Jasper_lee 0:b16d94660a33 2393 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2394 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2395
Jasper_lee 0:b16d94660a33 2396 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Jasper_lee 0:b16d94660a33 2397 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2398 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2399 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 2400 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 2401
Jasper_lee 0:b16d94660a33 2402 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
Jasper_lee 0:b16d94660a33 2403 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
Jasper_lee 0:b16d94660a33 2404
Jasper_lee 0:b16d94660a33 2405 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
Jasper_lee 0:b16d94660a33 2406 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
Jasper_lee 0:b16d94660a33 2407 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
Jasper_lee 0:b16d94660a33 2408
Jasper_lee 0:b16d94660a33 2409 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
Jasper_lee 0:b16d94660a33 2410 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2411 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2412 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 2413
Jasper_lee 0:b16d94660a33 2414 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Jasper_lee 0:b16d94660a33 2415 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2416 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2417
Jasper_lee 0:b16d94660a33 2418 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Jasper_lee 0:b16d94660a33 2419 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2420 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2421 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 2422 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 2423
Jasper_lee 0:b16d94660a33 2424 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
Jasper_lee 0:b16d94660a33 2425 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
Jasper_lee 0:b16d94660a33 2426
Jasper_lee 0:b16d94660a33 2427 /***************** Bit definition for DAC_SWTRIGR register ******************/
Jasper_lee 0:b16d94660a33 2428 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
Jasper_lee 0:b16d94660a33 2429 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
Jasper_lee 0:b16d94660a33 2430
Jasper_lee 0:b16d94660a33 2431 /***************** Bit definition for DAC_DHR12R1 register ******************/
Jasper_lee 0:b16d94660a33 2432 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2433
Jasper_lee 0:b16d94660a33 2434 /***************** Bit definition for DAC_DHR12L1 register ******************/
Jasper_lee 0:b16d94660a33 2435 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Jasper_lee 0:b16d94660a33 2436
Jasper_lee 0:b16d94660a33 2437 /****************** Bit definition for DAC_DHR8R1 register ******************/
Jasper_lee 0:b16d94660a33 2438 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2439
Jasper_lee 0:b16d94660a33 2440 /***************** Bit definition for DAC_DHR12R2 register ******************/
Jasper_lee 0:b16d94660a33 2441 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2442
Jasper_lee 0:b16d94660a33 2443 /***************** Bit definition for DAC_DHR12L2 register ******************/
Jasper_lee 0:b16d94660a33 2444 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
Jasper_lee 0:b16d94660a33 2445
Jasper_lee 0:b16d94660a33 2446 /****************** Bit definition for DAC_DHR8R2 register ******************/
Jasper_lee 0:b16d94660a33 2447 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2448
Jasper_lee 0:b16d94660a33 2449 /***************** Bit definition for DAC_DHR12RD register ******************/
Jasper_lee 0:b16d94660a33 2450 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2451 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2452
Jasper_lee 0:b16d94660a33 2453 /***************** Bit definition for DAC_DHR12LD register ******************/
Jasper_lee 0:b16d94660a33 2454 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
Jasper_lee 0:b16d94660a33 2455 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
Jasper_lee 0:b16d94660a33 2456
Jasper_lee 0:b16d94660a33 2457 /****************** Bit definition for DAC_DHR8RD register ******************/
Jasper_lee 0:b16d94660a33 2458 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2459 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
Jasper_lee 0:b16d94660a33 2460
Jasper_lee 0:b16d94660a33 2461 /******************* Bit definition for DAC_DOR1 register *******************/
Jasper_lee 0:b16d94660a33 2462 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
Jasper_lee 0:b16d94660a33 2463
Jasper_lee 0:b16d94660a33 2464 /******************* Bit definition for DAC_DOR2 register *******************/
Jasper_lee 0:b16d94660a33 2465 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
Jasper_lee 0:b16d94660a33 2466
Jasper_lee 0:b16d94660a33 2467 /******************** Bit definition for DAC_SR register ********************/
Jasper_lee 0:b16d94660a33 2468 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
Jasper_lee 0:b16d94660a33 2469 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
Jasper_lee 0:b16d94660a33 2470
Jasper_lee 0:b16d94660a33 2471 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2472 /* */
Jasper_lee 0:b16d94660a33 2473 /* Debug MCU (DBGMCU) */
Jasper_lee 0:b16d94660a33 2474 /* */
Jasper_lee 0:b16d94660a33 2475 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2476
Jasper_lee 0:b16d94660a33 2477 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Jasper_lee 0:b16d94660a33 2478 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Jasper_lee 0:b16d94660a33 2479
Jasper_lee 0:b16d94660a33 2480 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Jasper_lee 0:b16d94660a33 2481 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2482 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2483 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 2484 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 2485 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Jasper_lee 0:b16d94660a33 2486 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Jasper_lee 0:b16d94660a33 2487 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Jasper_lee 0:b16d94660a33 2488 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Jasper_lee 0:b16d94660a33 2489 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Jasper_lee 0:b16d94660a33 2490 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Jasper_lee 0:b16d94660a33 2491 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Jasper_lee 0:b16d94660a33 2492 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Jasper_lee 0:b16d94660a33 2493 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Jasper_lee 0:b16d94660a33 2494 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Jasper_lee 0:b16d94660a33 2495 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Jasper_lee 0:b16d94660a33 2496 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Jasper_lee 0:b16d94660a33 2497
Jasper_lee 0:b16d94660a33 2498 /****************** Bit definition for DBGMCU_CR register *******************/
Jasper_lee 0:b16d94660a33 2499 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Jasper_lee 0:b16d94660a33 2500 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Jasper_lee 0:b16d94660a33 2501
Jasper_lee 0:b16d94660a33 2502 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Jasper_lee 0:b16d94660a33 2503 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2504 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2505 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2506 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2507 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2508 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
Jasper_lee 0:b16d94660a33 2509 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
Jasper_lee 0:b16d94660a33 2510 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
Jasper_lee 0:b16d94660a33 2511 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Jasper_lee 0:b16d94660a33 2512 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
Jasper_lee 0:b16d94660a33 2513
Jasper_lee 0:b16d94660a33 2514 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Jasper_lee 0:b16d94660a33 2515 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2516 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2517 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2518 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
Jasper_lee 0:b16d94660a33 2519
Jasper_lee 0:b16d94660a33 2520 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2521 /* */
Jasper_lee 0:b16d94660a33 2522 /* DMA Controller (DMA) */
Jasper_lee 0:b16d94660a33 2523 /* */
Jasper_lee 0:b16d94660a33 2524 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2525 /******************* Bit definition for DMA_ISR register ********************/
Jasper_lee 0:b16d94660a33 2526 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2527 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2528 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2529 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2530 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2531 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2532 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2533 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2534 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2535 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2536 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2537 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2538 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2539 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2540 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2541 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2542 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2543 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2544 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2545 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2546 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2547 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2548 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2549 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2550 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
Jasper_lee 0:b16d94660a33 2551 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
Jasper_lee 0:b16d94660a33 2552 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
Jasper_lee 0:b16d94660a33 2553 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
Jasper_lee 0:b16d94660a33 2554
Jasper_lee 0:b16d94660a33 2555 /******************* Bit definition for DMA_IFCR register *******************/
Jasper_lee 0:b16d94660a33 2556 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2557 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2558 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2559 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2560 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2561 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2562 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2563 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2564 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2565 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2566 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2567 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2568 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2569 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2570 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2571 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2572 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2573 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2574 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2575 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2576 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2577 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2578 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2579 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2580 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
Jasper_lee 0:b16d94660a33 2581 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
Jasper_lee 0:b16d94660a33 2582 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
Jasper_lee 0:b16d94660a33 2583 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
Jasper_lee 0:b16d94660a33 2584
Jasper_lee 0:b16d94660a33 2585 /******************* Bit definition for DMA_CCR register ********************/
Jasper_lee 0:b16d94660a33 2586 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Jasper_lee 0:b16d94660a33 2587 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Jasper_lee 0:b16d94660a33 2588 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Jasper_lee 0:b16d94660a33 2589 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Jasper_lee 0:b16d94660a33 2590 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Jasper_lee 0:b16d94660a33 2591 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Jasper_lee 0:b16d94660a33 2592 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Jasper_lee 0:b16d94660a33 2593 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Jasper_lee 0:b16d94660a33 2594
Jasper_lee 0:b16d94660a33 2595 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Jasper_lee 0:b16d94660a33 2596 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2597 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2598
Jasper_lee 0:b16d94660a33 2599 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Jasper_lee 0:b16d94660a33 2600 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2601 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2602
Jasper_lee 0:b16d94660a33 2603 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Jasper_lee 0:b16d94660a33 2604 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 2605 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 2606
Jasper_lee 0:b16d94660a33 2607 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Jasper_lee 0:b16d94660a33 2608
Jasper_lee 0:b16d94660a33 2609 /****************** Bit definition for DMA_CNDTR register *******************/
Jasper_lee 0:b16d94660a33 2610 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Jasper_lee 0:b16d94660a33 2611
Jasper_lee 0:b16d94660a33 2612 /****************** Bit definition for DMA_CPAR register ********************/
Jasper_lee 0:b16d94660a33 2613 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Jasper_lee 0:b16d94660a33 2614
Jasper_lee 0:b16d94660a33 2615 /****************** Bit definition for DMA_CMAR register ********************/
Jasper_lee 0:b16d94660a33 2616 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Jasper_lee 0:b16d94660a33 2617
Jasper_lee 0:b16d94660a33 2618 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2619 /* */
Jasper_lee 0:b16d94660a33 2620 /* External Interrupt/Event Controller (EXTI) */
Jasper_lee 0:b16d94660a33 2621 /* */
Jasper_lee 0:b16d94660a33 2622 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2623 /******************* Bit definition for EXTI_IMR register *******************/
Jasper_lee 0:b16d94660a33 2624 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Jasper_lee 0:b16d94660a33 2625 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Jasper_lee 0:b16d94660a33 2626 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Jasper_lee 0:b16d94660a33 2627 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Jasper_lee 0:b16d94660a33 2628 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Jasper_lee 0:b16d94660a33 2629 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Jasper_lee 0:b16d94660a33 2630 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Jasper_lee 0:b16d94660a33 2631 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Jasper_lee 0:b16d94660a33 2632 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Jasper_lee 0:b16d94660a33 2633 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Jasper_lee 0:b16d94660a33 2634 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Jasper_lee 0:b16d94660a33 2635 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Jasper_lee 0:b16d94660a33 2636 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Jasper_lee 0:b16d94660a33 2637 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Jasper_lee 0:b16d94660a33 2638 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Jasper_lee 0:b16d94660a33 2639 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Jasper_lee 0:b16d94660a33 2640 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Jasper_lee 0:b16d94660a33 2641 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Jasper_lee 0:b16d94660a33 2642 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Jasper_lee 0:b16d94660a33 2643 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Jasper_lee 0:b16d94660a33 2644 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Jasper_lee 0:b16d94660a33 2645 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Jasper_lee 0:b16d94660a33 2646 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
Jasper_lee 0:b16d94660a33 2647 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
Jasper_lee 0:b16d94660a33 2648
Jasper_lee 0:b16d94660a33 2649 /****************** Bit definition for EXTI_EMR register ********************/
Jasper_lee 0:b16d94660a33 2650 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Jasper_lee 0:b16d94660a33 2651 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Jasper_lee 0:b16d94660a33 2652 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Jasper_lee 0:b16d94660a33 2653 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Jasper_lee 0:b16d94660a33 2654 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Jasper_lee 0:b16d94660a33 2655 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Jasper_lee 0:b16d94660a33 2656 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Jasper_lee 0:b16d94660a33 2657 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Jasper_lee 0:b16d94660a33 2658 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Jasper_lee 0:b16d94660a33 2659 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Jasper_lee 0:b16d94660a33 2660 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Jasper_lee 0:b16d94660a33 2661 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Jasper_lee 0:b16d94660a33 2662 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Jasper_lee 0:b16d94660a33 2663 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Jasper_lee 0:b16d94660a33 2664 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Jasper_lee 0:b16d94660a33 2665 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Jasper_lee 0:b16d94660a33 2666 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Jasper_lee 0:b16d94660a33 2667 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Jasper_lee 0:b16d94660a33 2668 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Jasper_lee 0:b16d94660a33 2669 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Jasper_lee 0:b16d94660a33 2670 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Jasper_lee 0:b16d94660a33 2671 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Jasper_lee 0:b16d94660a33 2672 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
Jasper_lee 0:b16d94660a33 2673 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
Jasper_lee 0:b16d94660a33 2674
Jasper_lee 0:b16d94660a33 2675 /******************* Bit definition for EXTI_RTSR register ******************/
Jasper_lee 0:b16d94660a33 2676 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Jasper_lee 0:b16d94660a33 2677 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Jasper_lee 0:b16d94660a33 2678 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Jasper_lee 0:b16d94660a33 2679 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Jasper_lee 0:b16d94660a33 2680 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Jasper_lee 0:b16d94660a33 2681 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Jasper_lee 0:b16d94660a33 2682 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Jasper_lee 0:b16d94660a33 2683 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Jasper_lee 0:b16d94660a33 2684 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Jasper_lee 0:b16d94660a33 2685 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Jasper_lee 0:b16d94660a33 2686 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Jasper_lee 0:b16d94660a33 2687 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Jasper_lee 0:b16d94660a33 2688 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Jasper_lee 0:b16d94660a33 2689 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Jasper_lee 0:b16d94660a33 2690 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Jasper_lee 0:b16d94660a33 2691 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Jasper_lee 0:b16d94660a33 2692 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Jasper_lee 0:b16d94660a33 2693 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Jasper_lee 0:b16d94660a33 2694 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Jasper_lee 0:b16d94660a33 2695
Jasper_lee 0:b16d94660a33 2696 /******************* Bit definition for EXTI_FTSR register *******************/
Jasper_lee 0:b16d94660a33 2697 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Jasper_lee 0:b16d94660a33 2698 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Jasper_lee 0:b16d94660a33 2699 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Jasper_lee 0:b16d94660a33 2700 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Jasper_lee 0:b16d94660a33 2701 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Jasper_lee 0:b16d94660a33 2702 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Jasper_lee 0:b16d94660a33 2703 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Jasper_lee 0:b16d94660a33 2704 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Jasper_lee 0:b16d94660a33 2705 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Jasper_lee 0:b16d94660a33 2706 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Jasper_lee 0:b16d94660a33 2707 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Jasper_lee 0:b16d94660a33 2708 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Jasper_lee 0:b16d94660a33 2709 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Jasper_lee 0:b16d94660a33 2710 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Jasper_lee 0:b16d94660a33 2711 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Jasper_lee 0:b16d94660a33 2712 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Jasper_lee 0:b16d94660a33 2713 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Jasper_lee 0:b16d94660a33 2714 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Jasper_lee 0:b16d94660a33 2715 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Jasper_lee 0:b16d94660a33 2716
Jasper_lee 0:b16d94660a33 2717 /******************* Bit definition for EXTI_SWIER register *******************/
Jasper_lee 0:b16d94660a33 2718 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Jasper_lee 0:b16d94660a33 2719 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Jasper_lee 0:b16d94660a33 2720 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Jasper_lee 0:b16d94660a33 2721 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Jasper_lee 0:b16d94660a33 2722 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Jasper_lee 0:b16d94660a33 2723 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Jasper_lee 0:b16d94660a33 2724 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Jasper_lee 0:b16d94660a33 2725 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Jasper_lee 0:b16d94660a33 2726 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Jasper_lee 0:b16d94660a33 2727 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Jasper_lee 0:b16d94660a33 2728 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Jasper_lee 0:b16d94660a33 2729 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Jasper_lee 0:b16d94660a33 2730 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Jasper_lee 0:b16d94660a33 2731 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Jasper_lee 0:b16d94660a33 2732 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Jasper_lee 0:b16d94660a33 2733 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Jasper_lee 0:b16d94660a33 2734 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Jasper_lee 0:b16d94660a33 2735 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Jasper_lee 0:b16d94660a33 2736 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Jasper_lee 0:b16d94660a33 2737
Jasper_lee 0:b16d94660a33 2738 /****************** Bit definition for EXTI_PR register *********************/
Jasper_lee 0:b16d94660a33 2739 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
Jasper_lee 0:b16d94660a33 2740 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
Jasper_lee 0:b16d94660a33 2741 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
Jasper_lee 0:b16d94660a33 2742 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
Jasper_lee 0:b16d94660a33 2743 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
Jasper_lee 0:b16d94660a33 2744 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
Jasper_lee 0:b16d94660a33 2745 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
Jasper_lee 0:b16d94660a33 2746 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
Jasper_lee 0:b16d94660a33 2747 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
Jasper_lee 0:b16d94660a33 2748 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
Jasper_lee 0:b16d94660a33 2749 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
Jasper_lee 0:b16d94660a33 2750 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
Jasper_lee 0:b16d94660a33 2751 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
Jasper_lee 0:b16d94660a33 2752 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
Jasper_lee 0:b16d94660a33 2753 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
Jasper_lee 0:b16d94660a33 2754 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
Jasper_lee 0:b16d94660a33 2755 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
Jasper_lee 0:b16d94660a33 2756 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
Jasper_lee 0:b16d94660a33 2757 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
Jasper_lee 0:b16d94660a33 2758
Jasper_lee 0:b16d94660a33 2759 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2760 /* */
Jasper_lee 0:b16d94660a33 2761 /* FLASH and Option Bytes Registers */
Jasper_lee 0:b16d94660a33 2762 /* */
Jasper_lee 0:b16d94660a33 2763 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2764
Jasper_lee 0:b16d94660a33 2765 /******************* Bit definition for FLASH_ACR register ******************/
Jasper_lee 0:b16d94660a33 2766 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
Jasper_lee 0:b16d94660a33 2767
Jasper_lee 0:b16d94660a33 2768 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Jasper_lee 0:b16d94660a33 2769 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Jasper_lee 0:b16d94660a33 2770
Jasper_lee 0:b16d94660a33 2771 /****************** Bit definition for FLASH_KEYR register ******************/
Jasper_lee 0:b16d94660a33 2772 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Jasper_lee 0:b16d94660a33 2773
Jasper_lee 0:b16d94660a33 2774 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Jasper_lee 0:b16d94660a33 2775 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Jasper_lee 0:b16d94660a33 2776
Jasper_lee 0:b16d94660a33 2777 /****************** FLASH Keys **********************************************/
Jasper_lee 0:b16d94660a33 2778 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
Jasper_lee 0:b16d94660a33 2779 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Jasper_lee 0:b16d94660a33 2780 to unlock the write access to the FPEC. */
Jasper_lee 0:b16d94660a33 2781
Jasper_lee 0:b16d94660a33 2782 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
Jasper_lee 0:b16d94660a33 2783 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Jasper_lee 0:b16d94660a33 2784 unlock the write access to the option byte block */
Jasper_lee 0:b16d94660a33 2785
Jasper_lee 0:b16d94660a33 2786 /****************** Bit definition for FLASH_SR register *******************/
Jasper_lee 0:b16d94660a33 2787 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Jasper_lee 0:b16d94660a33 2788 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Jasper_lee 0:b16d94660a33 2789 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Jasper_lee 0:b16d94660a33 2790 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Jasper_lee 0:b16d94660a33 2791 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Jasper_lee 0:b16d94660a33 2792
Jasper_lee 0:b16d94660a33 2793 /******************* Bit definition for FLASH_CR register *******************/
Jasper_lee 0:b16d94660a33 2794 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Jasper_lee 0:b16d94660a33 2795 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Jasper_lee 0:b16d94660a33 2796 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Jasper_lee 0:b16d94660a33 2797 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Jasper_lee 0:b16d94660a33 2798 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Jasper_lee 0:b16d94660a33 2799 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Jasper_lee 0:b16d94660a33 2800 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Jasper_lee 0:b16d94660a33 2801 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Jasper_lee 0:b16d94660a33 2802 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Jasper_lee 0:b16d94660a33 2803 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Jasper_lee 0:b16d94660a33 2804 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
Jasper_lee 0:b16d94660a33 2805
Jasper_lee 0:b16d94660a33 2806 /******************* Bit definition for FLASH_AR register *******************/
Jasper_lee 0:b16d94660a33 2807 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Jasper_lee 0:b16d94660a33 2808
Jasper_lee 0:b16d94660a33 2809 /****************** Bit definition for FLASH_OBR register *******************/
Jasper_lee 0:b16d94660a33 2810 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Jasper_lee 0:b16d94660a33 2811 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Jasper_lee 0:b16d94660a33 2812 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
Jasper_lee 0:b16d94660a33 2813
Jasper_lee 0:b16d94660a33 2814 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
Jasper_lee 0:b16d94660a33 2815 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Jasper_lee 0:b16d94660a33 2816 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Jasper_lee 0:b16d94660a33 2817 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Jasper_lee 0:b16d94660a33 2818 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Jasper_lee 0:b16d94660a33 2819 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
Jasper_lee 0:b16d94660a33 2820
Jasper_lee 0:b16d94660a33 2821 /* Old BOOT1 bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 2822 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Jasper_lee 0:b16d94660a33 2823
Jasper_lee 0:b16d94660a33 2824 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 2825 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Jasper_lee 0:b16d94660a33 2826
Jasper_lee 0:b16d94660a33 2827 /****************** Bit definition for FLASH_WRPR register ******************/
Jasper_lee 0:b16d94660a33 2828 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
Jasper_lee 0:b16d94660a33 2829
Jasper_lee 0:b16d94660a33 2830 /*----------------------------------------------------------------------------*/
Jasper_lee 0:b16d94660a33 2831
Jasper_lee 0:b16d94660a33 2832 /****************** Bit definition for OB_RDP register **********************/
Jasper_lee 0:b16d94660a33 2833 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Jasper_lee 0:b16d94660a33 2834 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Jasper_lee 0:b16d94660a33 2835
Jasper_lee 0:b16d94660a33 2836 /****************** Bit definition for OB_USER register *********************/
Jasper_lee 0:b16d94660a33 2837 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Jasper_lee 0:b16d94660a33 2838 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Jasper_lee 0:b16d94660a33 2839
Jasper_lee 0:b16d94660a33 2840 /****************** Bit definition for OB_WRP0 register *********************/
Jasper_lee 0:b16d94660a33 2841 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Jasper_lee 0:b16d94660a33 2842 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Jasper_lee 0:b16d94660a33 2843
Jasper_lee 0:b16d94660a33 2844 /****************** Bit definition for OB_WRP1 register *********************/
Jasper_lee 0:b16d94660a33 2845 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Jasper_lee 0:b16d94660a33 2846 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Jasper_lee 0:b16d94660a33 2847
Jasper_lee 0:b16d94660a33 2848 /****************** Bit definition for OB_WRP2 register *********************/
Jasper_lee 0:b16d94660a33 2849 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Jasper_lee 0:b16d94660a33 2850 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Jasper_lee 0:b16d94660a33 2851
Jasper_lee 0:b16d94660a33 2852 /****************** Bit definition for OB_WRP3 register *********************/
Jasper_lee 0:b16d94660a33 2853 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
Jasper_lee 0:b16d94660a33 2854 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
Jasper_lee 0:b16d94660a33 2855
Jasper_lee 0:b16d94660a33 2856 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2857 /* */
Jasper_lee 0:b16d94660a33 2858 /* General Purpose IOs (GPIO) */
Jasper_lee 0:b16d94660a33 2859 /* */
Jasper_lee 0:b16d94660a33 2860 /******************************************************************************/
Jasper_lee 0:b16d94660a33 2861 /******************* Bit definition for GPIO_MODER register *****************/
Jasper_lee 0:b16d94660a33 2862 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Jasper_lee 0:b16d94660a33 2863 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 2864 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 2865 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Jasper_lee 0:b16d94660a33 2866 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 2867 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 2868 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Jasper_lee 0:b16d94660a33 2869 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 2870 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 2871 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Jasper_lee 0:b16d94660a33 2872 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 2873 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 2874 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Jasper_lee 0:b16d94660a33 2875 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 2876 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 2877 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Jasper_lee 0:b16d94660a33 2878 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 2879 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 2880 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Jasper_lee 0:b16d94660a33 2881 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 2882 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 2883 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Jasper_lee 0:b16d94660a33 2884 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 2885 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 2886 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Jasper_lee 0:b16d94660a33 2887 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 2888 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 2889 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Jasper_lee 0:b16d94660a33 2890 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 2891 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 2892 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 2893 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 2894 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 2895 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Jasper_lee 0:b16d94660a33 2896 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 2897 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 2898 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Jasper_lee 0:b16d94660a33 2899 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 2900 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 2901 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Jasper_lee 0:b16d94660a33 2902 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 2903 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 2904 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Jasper_lee 0:b16d94660a33 2905 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Jasper_lee 0:b16d94660a33 2906 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Jasper_lee 0:b16d94660a33 2907 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Jasper_lee 0:b16d94660a33 2908 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Jasper_lee 0:b16d94660a33 2909 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 2910
Jasper_lee 0:b16d94660a33 2911 /****************** Bit definition for GPIO_OTYPER register *****************/
Jasper_lee 0:b16d94660a33 2912 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 2913 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 2914 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 2915 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 2916 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 2917 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 2918 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 2919 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 2920 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 2921 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 2922 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 2923 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 2924 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 2925 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 2926 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 2927 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 2928
Jasper_lee 0:b16d94660a33 2929 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Jasper_lee 0:b16d94660a33 2930 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Jasper_lee 0:b16d94660a33 2931 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 2932 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 2933 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Jasper_lee 0:b16d94660a33 2934 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 2935 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 2936 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Jasper_lee 0:b16d94660a33 2937 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 2938 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 2939 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Jasper_lee 0:b16d94660a33 2940 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 2941 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 2942 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Jasper_lee 0:b16d94660a33 2943 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 2944 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 2945 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Jasper_lee 0:b16d94660a33 2946 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 2947 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 2948 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Jasper_lee 0:b16d94660a33 2949 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 2950 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 2951 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Jasper_lee 0:b16d94660a33 2952 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 2953 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 2954 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Jasper_lee 0:b16d94660a33 2955 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 2956 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 2957 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Jasper_lee 0:b16d94660a33 2958 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 2959 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 2960 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 2961 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 2962 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 2963 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Jasper_lee 0:b16d94660a33 2964 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 2965 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 2966 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Jasper_lee 0:b16d94660a33 2967 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 2968 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 2969 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Jasper_lee 0:b16d94660a33 2970 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 2971 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 2972 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Jasper_lee 0:b16d94660a33 2973 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Jasper_lee 0:b16d94660a33 2974 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Jasper_lee 0:b16d94660a33 2975 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Jasper_lee 0:b16d94660a33 2976 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Jasper_lee 0:b16d94660a33 2977 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 2978
Jasper_lee 0:b16d94660a33 2979 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 2980 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Jasper_lee 0:b16d94660a33 2981 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Jasper_lee 0:b16d94660a33 2982 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Jasper_lee 0:b16d94660a33 2983 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Jasper_lee 0:b16d94660a33 2984 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Jasper_lee 0:b16d94660a33 2985 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Jasper_lee 0:b16d94660a33 2986 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Jasper_lee 0:b16d94660a33 2987 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Jasper_lee 0:b16d94660a33 2988 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Jasper_lee 0:b16d94660a33 2989 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Jasper_lee 0:b16d94660a33 2990 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Jasper_lee 0:b16d94660a33 2991 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Jasper_lee 0:b16d94660a33 2992 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Jasper_lee 0:b16d94660a33 2993 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Jasper_lee 0:b16d94660a33 2994 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Jasper_lee 0:b16d94660a33 2995 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Jasper_lee 0:b16d94660a33 2996 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Jasper_lee 0:b16d94660a33 2997 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Jasper_lee 0:b16d94660a33 2998 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Jasper_lee 0:b16d94660a33 2999 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Jasper_lee 0:b16d94660a33 3000 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Jasper_lee 0:b16d94660a33 3001 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Jasper_lee 0:b16d94660a33 3002 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Jasper_lee 0:b16d94660a33 3003 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Jasper_lee 0:b16d94660a33 3004 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Jasper_lee 0:b16d94660a33 3005 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Jasper_lee 0:b16d94660a33 3006 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Jasper_lee 0:b16d94660a33 3007 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Jasper_lee 0:b16d94660a33 3008 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Jasper_lee 0:b16d94660a33 3009 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Jasper_lee 0:b16d94660a33 3010 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Jasper_lee 0:b16d94660a33 3011 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Jasper_lee 0:b16d94660a33 3012 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Jasper_lee 0:b16d94660a33 3013 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Jasper_lee 0:b16d94660a33 3014 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Jasper_lee 0:b16d94660a33 3015 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Jasper_lee 0:b16d94660a33 3016 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Jasper_lee 0:b16d94660a33 3017 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Jasper_lee 0:b16d94660a33 3018 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Jasper_lee 0:b16d94660a33 3019 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Jasper_lee 0:b16d94660a33 3020 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Jasper_lee 0:b16d94660a33 3021 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Jasper_lee 0:b16d94660a33 3022 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Jasper_lee 0:b16d94660a33 3023 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Jasper_lee 0:b16d94660a33 3024 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Jasper_lee 0:b16d94660a33 3025 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Jasper_lee 0:b16d94660a33 3026 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Jasper_lee 0:b16d94660a33 3027 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Jasper_lee 0:b16d94660a33 3028
Jasper_lee 0:b16d94660a33 3029 /******************* Bit definition for GPIO_PUPDR register ******************/
Jasper_lee 0:b16d94660a33 3030 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Jasper_lee 0:b16d94660a33 3031 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3032 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3033 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Jasper_lee 0:b16d94660a33 3034 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3035 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3036 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Jasper_lee 0:b16d94660a33 3037 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3038 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3039 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Jasper_lee 0:b16d94660a33 3040 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3041 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3042 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Jasper_lee 0:b16d94660a33 3043 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3044 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3045 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Jasper_lee 0:b16d94660a33 3046 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3047 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3048 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Jasper_lee 0:b16d94660a33 3049 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3050 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3051 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Jasper_lee 0:b16d94660a33 3052 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3053 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3054 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Jasper_lee 0:b16d94660a33 3055 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3056 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3057 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Jasper_lee 0:b16d94660a33 3058 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3059 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3060 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 3061 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3062 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3063 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Jasper_lee 0:b16d94660a33 3064 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3065 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 3066 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Jasper_lee 0:b16d94660a33 3067 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 3068 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 3069 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Jasper_lee 0:b16d94660a33 3070 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 3071 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 3072 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Jasper_lee 0:b16d94660a33 3073 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Jasper_lee 0:b16d94660a33 3074 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Jasper_lee 0:b16d94660a33 3075 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Jasper_lee 0:b16d94660a33 3076 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Jasper_lee 0:b16d94660a33 3077 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 3078
Jasper_lee 0:b16d94660a33 3079 /******************* Bit definition for GPIO_IDR register *******************/
Jasper_lee 0:b16d94660a33 3080 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3081 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3082 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3083 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3084 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3085 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3086 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3087 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3088 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3089 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3090 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3091 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3092 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3093 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3094 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3095 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3096
Jasper_lee 0:b16d94660a33 3097 /****************** Bit definition for GPIO_ODR register ********************/
Jasper_lee 0:b16d94660a33 3098 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3099 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3100 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3101 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3102 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3103 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3104 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3105 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3106 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3107 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3108 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3109 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3110 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3111 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3112 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3113 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3114
Jasper_lee 0:b16d94660a33 3115 /****************** Bit definition for GPIO_BSRR register ********************/
Jasper_lee 0:b16d94660a33 3116 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3117 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3118 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3119 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3120 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3121 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3122 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3123 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3124 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3125 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3126 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3127 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3128 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3129 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3130 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3131 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3132 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3133 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3134 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3135 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3136 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3137 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3138 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3139 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 3140 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 3141 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 3142 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 3143 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 3144 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Jasper_lee 0:b16d94660a33 3145 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Jasper_lee 0:b16d94660a33 3146 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Jasper_lee 0:b16d94660a33 3147 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 3148
Jasper_lee 0:b16d94660a33 3149 /****************** Bit definition for GPIO_LCKR register ********************/
Jasper_lee 0:b16d94660a33 3150 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3151 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3152 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3153 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3154 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3155 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3156 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3157 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3158 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3159 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3160 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3161 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3162 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3163 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3164 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3165 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3166 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3167
Jasper_lee 0:b16d94660a33 3168 /****************** Bit definition for GPIO_AFRL register ********************/
Jasper_lee 0:b16d94660a33 3169 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3170 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Jasper_lee 0:b16d94660a33 3171 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3172 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Jasper_lee 0:b16d94660a33 3173 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3174 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Jasper_lee 0:b16d94660a33 3175 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Jasper_lee 0:b16d94660a33 3176 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Jasper_lee 0:b16d94660a33 3177
Jasper_lee 0:b16d94660a33 3178 /****************** Bit definition for GPIO_AFRH register ********************/
Jasper_lee 0:b16d94660a33 3179 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3180 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Jasper_lee 0:b16d94660a33 3181 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3182 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Jasper_lee 0:b16d94660a33 3183 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3184 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Jasper_lee 0:b16d94660a33 3185 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Jasper_lee 0:b16d94660a33 3186 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Jasper_lee 0:b16d94660a33 3187
Jasper_lee 0:b16d94660a33 3188 /****************** Bit definition for GPIO_BRR register *********************/
Jasper_lee 0:b16d94660a33 3189 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3190 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3191 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3192 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3193 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3194 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3195 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3196 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3197 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3198 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3199 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3200 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3201 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3202 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3203 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3204 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3205
Jasper_lee 0:b16d94660a33 3206 /******************************************************************************/
Jasper_lee 0:b16d94660a33 3207 /* */
Jasper_lee 0:b16d94660a33 3208 /* Inter-integrated Circuit Interface (I2C) */
Jasper_lee 0:b16d94660a33 3209 /* */
Jasper_lee 0:b16d94660a33 3210 /******************************************************************************/
Jasper_lee 0:b16d94660a33 3211
Jasper_lee 0:b16d94660a33 3212 /******************* Bit definition for I2C_CR1 register *******************/
Jasper_lee 0:b16d94660a33 3213 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Jasper_lee 0:b16d94660a33 3214 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Jasper_lee 0:b16d94660a33 3215 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Jasper_lee 0:b16d94660a33 3216 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Jasper_lee 0:b16d94660a33 3217 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Jasper_lee 0:b16d94660a33 3218 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Jasper_lee 0:b16d94660a33 3219 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Jasper_lee 0:b16d94660a33 3220 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Jasper_lee 0:b16d94660a33 3221 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Jasper_lee 0:b16d94660a33 3222 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Jasper_lee 0:b16d94660a33 3223 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Jasper_lee 0:b16d94660a33 3224 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Jasper_lee 0:b16d94660a33 3225 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Jasper_lee 0:b16d94660a33 3226 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Jasper_lee 0:b16d94660a33 3227 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Jasper_lee 0:b16d94660a33 3228 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Jasper_lee 0:b16d94660a33 3229 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Jasper_lee 0:b16d94660a33 3230 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Jasper_lee 0:b16d94660a33 3231 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Jasper_lee 0:b16d94660a33 3232 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Jasper_lee 0:b16d94660a33 3233 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Jasper_lee 0:b16d94660a33 3234
Jasper_lee 0:b16d94660a33 3235 /****************** Bit definition for I2C_CR2 register ********************/
Jasper_lee 0:b16d94660a33 3236 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Jasper_lee 0:b16d94660a33 3237 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Jasper_lee 0:b16d94660a33 3238 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Jasper_lee 0:b16d94660a33 3239 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Jasper_lee 0:b16d94660a33 3240 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Jasper_lee 0:b16d94660a33 3241 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Jasper_lee 0:b16d94660a33 3242 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Jasper_lee 0:b16d94660a33 3243 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Jasper_lee 0:b16d94660a33 3244 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Jasper_lee 0:b16d94660a33 3245 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Jasper_lee 0:b16d94660a33 3246 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Jasper_lee 0:b16d94660a33 3247
Jasper_lee 0:b16d94660a33 3248 /******************* Bit definition for I2C_OAR1 register ******************/
Jasper_lee 0:b16d94660a33 3249 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Jasper_lee 0:b16d94660a33 3250 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Jasper_lee 0:b16d94660a33 3251 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Jasper_lee 0:b16d94660a33 3252
Jasper_lee 0:b16d94660a33 3253 /******************* Bit definition for I2C_OAR2 register ******************/
Jasper_lee 0:b16d94660a33 3254 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Jasper_lee 0:b16d94660a33 3255 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Jasper_lee 0:b16d94660a33 3256 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Jasper_lee 0:b16d94660a33 3257
Jasper_lee 0:b16d94660a33 3258 /******************* Bit definition for I2C_TIMINGR register ****************/
Jasper_lee 0:b16d94660a33 3259 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Jasper_lee 0:b16d94660a33 3260 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Jasper_lee 0:b16d94660a33 3261 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Jasper_lee 0:b16d94660a33 3262 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Jasper_lee 0:b16d94660a33 3263 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Jasper_lee 0:b16d94660a33 3264
Jasper_lee 0:b16d94660a33 3265 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Jasper_lee 0:b16d94660a33 3266 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Jasper_lee 0:b16d94660a33 3267 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Jasper_lee 0:b16d94660a33 3268 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Jasper_lee 0:b16d94660a33 3269 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Jasper_lee 0:b16d94660a33 3270 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Jasper_lee 0:b16d94660a33 3271
Jasper_lee 0:b16d94660a33 3272 /****************** Bit definition for I2C_ISR register ********************/
Jasper_lee 0:b16d94660a33 3273 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Jasper_lee 0:b16d94660a33 3274 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Jasper_lee 0:b16d94660a33 3275 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Jasper_lee 0:b16d94660a33 3276 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Jasper_lee 0:b16d94660a33 3277 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Jasper_lee 0:b16d94660a33 3278 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Jasper_lee 0:b16d94660a33 3279 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Jasper_lee 0:b16d94660a33 3280 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Jasper_lee 0:b16d94660a33 3281 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Jasper_lee 0:b16d94660a33 3282 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Jasper_lee 0:b16d94660a33 3283 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Jasper_lee 0:b16d94660a33 3284 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Jasper_lee 0:b16d94660a33 3285 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Jasper_lee 0:b16d94660a33 3286 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Jasper_lee 0:b16d94660a33 3287 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Jasper_lee 0:b16d94660a33 3288 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Jasper_lee 0:b16d94660a33 3289 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Jasper_lee 0:b16d94660a33 3290
Jasper_lee 0:b16d94660a33 3291 /****************** Bit definition for I2C_ICR register ********************/
Jasper_lee 0:b16d94660a33 3292 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Jasper_lee 0:b16d94660a33 3293 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Jasper_lee 0:b16d94660a33 3294 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Jasper_lee 0:b16d94660a33 3295 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Jasper_lee 0:b16d94660a33 3296 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Jasper_lee 0:b16d94660a33 3297 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Jasper_lee 0:b16d94660a33 3298 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Jasper_lee 0:b16d94660a33 3299 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Jasper_lee 0:b16d94660a33 3300 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Jasper_lee 0:b16d94660a33 3301
Jasper_lee 0:b16d94660a33 3302 /****************** Bit definition for I2C_PECR register *******************/
Jasper_lee 0:b16d94660a33 3303 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Jasper_lee 0:b16d94660a33 3304
Jasper_lee 0:b16d94660a33 3305 /****************** Bit definition for I2C_RXDR register *********************/
Jasper_lee 0:b16d94660a33 3306 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Jasper_lee 0:b16d94660a33 3307
Jasper_lee 0:b16d94660a33 3308 /****************** Bit definition for I2C_TXDR register *******************/
Jasper_lee 0:b16d94660a33 3309 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Jasper_lee 0:b16d94660a33 3310
Jasper_lee 0:b16d94660a33 3311 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3312 /* */
Jasper_lee 0:b16d94660a33 3313 /* Independent WATCHDOG (IWDG) */
Jasper_lee 0:b16d94660a33 3314 /* */
Jasper_lee 0:b16d94660a33 3315 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3316 /******************* Bit definition for IWDG_KR register *******************/
Jasper_lee 0:b16d94660a33 3317 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
Jasper_lee 0:b16d94660a33 3318
Jasper_lee 0:b16d94660a33 3319 /******************* Bit definition for IWDG_PR register *******************/
Jasper_lee 0:b16d94660a33 3320 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
Jasper_lee 0:b16d94660a33 3321 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3322 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3323 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3324
Jasper_lee 0:b16d94660a33 3325 /******************* Bit definition for IWDG_RLR register ******************/
Jasper_lee 0:b16d94660a33 3326 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
Jasper_lee 0:b16d94660a33 3327
Jasper_lee 0:b16d94660a33 3328 /******************* Bit definition for IWDG_SR register *******************/
Jasper_lee 0:b16d94660a33 3329 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Jasper_lee 0:b16d94660a33 3330 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Jasper_lee 0:b16d94660a33 3331 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Jasper_lee 0:b16d94660a33 3332
Jasper_lee 0:b16d94660a33 3333 /******************* Bit definition for IWDG_KR register *******************/
Jasper_lee 0:b16d94660a33 3334 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Jasper_lee 0:b16d94660a33 3335
Jasper_lee 0:b16d94660a33 3336 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3337 /* */
Jasper_lee 0:b16d94660a33 3338 /* Power Control (PWR) */
Jasper_lee 0:b16d94660a33 3339 /* */
Jasper_lee 0:b16d94660a33 3340 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3341
Jasper_lee 0:b16d94660a33 3342 /******************** Bit definition for PWR_CR register *******************/
Jasper_lee 0:b16d94660a33 3343 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Jasper_lee 0:b16d94660a33 3344 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Jasper_lee 0:b16d94660a33 3345 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Jasper_lee 0:b16d94660a33 3346 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Jasper_lee 0:b16d94660a33 3347 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Jasper_lee 0:b16d94660a33 3348
Jasper_lee 0:b16d94660a33 3349 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Jasper_lee 0:b16d94660a33 3350 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3351 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3352 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3353
Jasper_lee 0:b16d94660a33 3354 /*!< PVD level configuration */
Jasper_lee 0:b16d94660a33 3355 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Jasper_lee 0:b16d94660a33 3356 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Jasper_lee 0:b16d94660a33 3357 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Jasper_lee 0:b16d94660a33 3358 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Jasper_lee 0:b16d94660a33 3359 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Jasper_lee 0:b16d94660a33 3360 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Jasper_lee 0:b16d94660a33 3361 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Jasper_lee 0:b16d94660a33 3362 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Jasper_lee 0:b16d94660a33 3363
Jasper_lee 0:b16d94660a33 3364 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Jasper_lee 0:b16d94660a33 3365
Jasper_lee 0:b16d94660a33 3366 /******************* Bit definition for PWR_CSR register *******************/
Jasper_lee 0:b16d94660a33 3367 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Jasper_lee 0:b16d94660a33 3368 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Jasper_lee 0:b16d94660a33 3369 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Jasper_lee 0:b16d94660a33 3370 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
Jasper_lee 0:b16d94660a33 3371
Jasper_lee 0:b16d94660a33 3372 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Jasper_lee 0:b16d94660a33 3373 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Jasper_lee 0:b16d94660a33 3374 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
Jasper_lee 0:b16d94660a33 3375 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
Jasper_lee 0:b16d94660a33 3376 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
Jasper_lee 0:b16d94660a33 3377 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
Jasper_lee 0:b16d94660a33 3378 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
Jasper_lee 0:b16d94660a33 3379 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
Jasper_lee 0:b16d94660a33 3380
Jasper_lee 0:b16d94660a33 3381 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3382 /* */
Jasper_lee 0:b16d94660a33 3383 /* Reset and Clock Control */
Jasper_lee 0:b16d94660a33 3384 /* */
Jasper_lee 0:b16d94660a33 3385 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3386
Jasper_lee 0:b16d94660a33 3387 /******************** Bit definition for RCC_CR register *******************/
Jasper_lee 0:b16d94660a33 3388 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Jasper_lee 0:b16d94660a33 3389 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Jasper_lee 0:b16d94660a33 3390
Jasper_lee 0:b16d94660a33 3391 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Jasper_lee 0:b16d94660a33 3392 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 3393 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 3394 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 3395 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 3396 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 3397
Jasper_lee 0:b16d94660a33 3398 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Jasper_lee 0:b16d94660a33 3399 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 3400 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 3401 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 3402 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 3403 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 3404 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Jasper_lee 0:b16d94660a33 3405 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Jasper_lee 0:b16d94660a33 3406 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Jasper_lee 0:b16d94660a33 3407
Jasper_lee 0:b16d94660a33 3408 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Jasper_lee 0:b16d94660a33 3409 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Jasper_lee 0:b16d94660a33 3410 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Jasper_lee 0:b16d94660a33 3411 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Jasper_lee 0:b16d94660a33 3412 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Jasper_lee 0:b16d94660a33 3413 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Jasper_lee 0:b16d94660a33 3414
Jasper_lee 0:b16d94660a33 3415 /******************** Bit definition for RCC_CFGR register *****************/
Jasper_lee 0:b16d94660a33 3416 /*!< SW configuration */
Jasper_lee 0:b16d94660a33 3417 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Jasper_lee 0:b16d94660a33 3418 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3419 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3420
Jasper_lee 0:b16d94660a33 3421 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Jasper_lee 0:b16d94660a33 3422 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Jasper_lee 0:b16d94660a33 3423 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Jasper_lee 0:b16d94660a33 3424 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
Jasper_lee 0:b16d94660a33 3425
Jasper_lee 0:b16d94660a33 3426 /*!< SWS configuration */
Jasper_lee 0:b16d94660a33 3427 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Jasper_lee 0:b16d94660a33 3428 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3429 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3430
Jasper_lee 0:b16d94660a33 3431 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Jasper_lee 0:b16d94660a33 3432 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Jasper_lee 0:b16d94660a33 3433 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Jasper_lee 0:b16d94660a33 3434 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
Jasper_lee 0:b16d94660a33 3435
Jasper_lee 0:b16d94660a33 3436 /*!< HPRE configuration */
Jasper_lee 0:b16d94660a33 3437 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Jasper_lee 0:b16d94660a33 3438 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3439 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3440 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3441 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 3442
Jasper_lee 0:b16d94660a33 3443 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Jasper_lee 0:b16d94660a33 3444 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Jasper_lee 0:b16d94660a33 3445 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Jasper_lee 0:b16d94660a33 3446 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Jasper_lee 0:b16d94660a33 3447 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Jasper_lee 0:b16d94660a33 3448 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Jasper_lee 0:b16d94660a33 3449 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Jasper_lee 0:b16d94660a33 3450 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Jasper_lee 0:b16d94660a33 3451 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Jasper_lee 0:b16d94660a33 3452
Jasper_lee 0:b16d94660a33 3453 /*!< PPRE configuration */
Jasper_lee 0:b16d94660a33 3454 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
Jasper_lee 0:b16d94660a33 3455 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3456 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3457 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3458
Jasper_lee 0:b16d94660a33 3459 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Jasper_lee 0:b16d94660a33 3460 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Jasper_lee 0:b16d94660a33 3461 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Jasper_lee 0:b16d94660a33 3462 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Jasper_lee 0:b16d94660a33 3463 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Jasper_lee 0:b16d94660a33 3464
Jasper_lee 0:b16d94660a33 3465 /*!< ADCPPRE configuration */
Jasper_lee 0:b16d94660a33 3466 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
Jasper_lee 0:b16d94660a33 3467
Jasper_lee 0:b16d94660a33 3468 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
Jasper_lee 0:b16d94660a33 3469 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
Jasper_lee 0:b16d94660a33 3470
Jasper_lee 0:b16d94660a33 3471 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
Jasper_lee 0:b16d94660a33 3472 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Jasper_lee 0:b16d94660a33 3473 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
Jasper_lee 0:b16d94660a33 3474 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Jasper_lee 0:b16d94660a33 3475 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
Jasper_lee 0:b16d94660a33 3476
Jasper_lee 0:b16d94660a33 3477 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Jasper_lee 0:b16d94660a33 3478 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Jasper_lee 0:b16d94660a33 3479 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Jasper_lee 0:b16d94660a33 3480
Jasper_lee 0:b16d94660a33 3481 /*!< PLLMUL configuration */
Jasper_lee 0:b16d94660a33 3482 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Jasper_lee 0:b16d94660a33 3483 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3484 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3485 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3486 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 3487
Jasper_lee 0:b16d94660a33 3488 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Jasper_lee 0:b16d94660a33 3489 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Jasper_lee 0:b16d94660a33 3490 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Jasper_lee 0:b16d94660a33 3491 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Jasper_lee 0:b16d94660a33 3492 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Jasper_lee 0:b16d94660a33 3493 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Jasper_lee 0:b16d94660a33 3494 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Jasper_lee 0:b16d94660a33 3495 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Jasper_lee 0:b16d94660a33 3496 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Jasper_lee 0:b16d94660a33 3497 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Jasper_lee 0:b16d94660a33 3498 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Jasper_lee 0:b16d94660a33 3499 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Jasper_lee 0:b16d94660a33 3500 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Jasper_lee 0:b16d94660a33 3501 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Jasper_lee 0:b16d94660a33 3502 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Jasper_lee 0:b16d94660a33 3503
Jasper_lee 0:b16d94660a33 3504 /*!< USB configuration */
Jasper_lee 0:b16d94660a33 3505 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
Jasper_lee 0:b16d94660a33 3506
Jasper_lee 0:b16d94660a33 3507 /*!< MCO configuration */
Jasper_lee 0:b16d94660a33 3508 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Jasper_lee 0:b16d94660a33 3509 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3510 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3511 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3512 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 3513
Jasper_lee 0:b16d94660a33 3514 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Jasper_lee 0:b16d94660a33 3515 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3516 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3517 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3518 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3519 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3520 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3521 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Jasper_lee 0:b16d94660a33 3522 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
Jasper_lee 0:b16d94660a33 3523
Jasper_lee 0:b16d94660a33 3524 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Jasper_lee 0:b16d94660a33 3525 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Jasper_lee 0:b16d94660a33 3526 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Jasper_lee 0:b16d94660a33 3527 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Jasper_lee 0:b16d94660a33 3528 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Jasper_lee 0:b16d94660a33 3529 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Jasper_lee 0:b16d94660a33 3530 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Jasper_lee 0:b16d94660a33 3531 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Jasper_lee 0:b16d94660a33 3532 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Jasper_lee 0:b16d94660a33 3533
Jasper_lee 0:b16d94660a33 3534 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Jasper_lee 0:b16d94660a33 3535
Jasper_lee 0:b16d94660a33 3536 /*!<****************** Bit definition for RCC_CIR register *****************/
Jasper_lee 0:b16d94660a33 3537 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3538 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3539 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3540 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3541 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3542 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3543 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
Jasper_lee 0:b16d94660a33 3544 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Jasper_lee 0:b16d94660a33 3545 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3546 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3547 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3548 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3549 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3550 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3551 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
Jasper_lee 0:b16d94660a33 3552 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3553 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3554 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3555 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3556 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3557 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3558 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
Jasper_lee 0:b16d94660a33 3559 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Jasper_lee 0:b16d94660a33 3560
Jasper_lee 0:b16d94660a33 3561 /***************** Bit definition for RCC_APB2RSTR register ****************/
Jasper_lee 0:b16d94660a33 3562 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
Jasper_lee 0:b16d94660a33 3563 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
Jasper_lee 0:b16d94660a33 3564 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
Jasper_lee 0:b16d94660a33 3565 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
Jasper_lee 0:b16d94660a33 3566 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
Jasper_lee 0:b16d94660a33 3567 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
Jasper_lee 0:b16d94660a33 3568 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
Jasper_lee 0:b16d94660a33 3569 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
Jasper_lee 0:b16d94660a33 3570 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
Jasper_lee 0:b16d94660a33 3571
Jasper_lee 0:b16d94660a33 3572 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 3573 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Jasper_lee 0:b16d94660a33 3574
Jasper_lee 0:b16d94660a33 3575 /***************** Bit definition for RCC_APB1RSTR register ****************/
Jasper_lee 0:b16d94660a33 3576 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
Jasper_lee 0:b16d94660a33 3577 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
Jasper_lee 0:b16d94660a33 3578 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
Jasper_lee 0:b16d94660a33 3579 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
Jasper_lee 0:b16d94660a33 3580 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
Jasper_lee 0:b16d94660a33 3581 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
Jasper_lee 0:b16d94660a33 3582 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
Jasper_lee 0:b16d94660a33 3583 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
Jasper_lee 0:b16d94660a33 3584 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
Jasper_lee 0:b16d94660a33 3585 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
Jasper_lee 0:b16d94660a33 3586 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
Jasper_lee 0:b16d94660a33 3587 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
Jasper_lee 0:b16d94660a33 3588 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
Jasper_lee 0:b16d94660a33 3589 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
Jasper_lee 0:b16d94660a33 3590 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
Jasper_lee 0:b16d94660a33 3591 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
Jasper_lee 0:b16d94660a33 3592 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
Jasper_lee 0:b16d94660a33 3593 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
Jasper_lee 0:b16d94660a33 3594
Jasper_lee 0:b16d94660a33 3595 /****************** Bit definition for RCC_AHBENR register *****************/
Jasper_lee 0:b16d94660a33 3596 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Jasper_lee 0:b16d94660a33 3597 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Jasper_lee 0:b16d94660a33 3598 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Jasper_lee 0:b16d94660a33 3599 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Jasper_lee 0:b16d94660a33 3600 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Jasper_lee 0:b16d94660a33 3601 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Jasper_lee 0:b16d94660a33 3602 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Jasper_lee 0:b16d94660a33 3603 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
Jasper_lee 0:b16d94660a33 3604 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
Jasper_lee 0:b16d94660a33 3605 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Jasper_lee 0:b16d94660a33 3606 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
Jasper_lee 0:b16d94660a33 3607
Jasper_lee 0:b16d94660a33 3608 /* Old Bit definition maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 3609 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Jasper_lee 0:b16d94660a33 3610 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Jasper_lee 0:b16d94660a33 3611
Jasper_lee 0:b16d94660a33 3612 /***************** Bit definition for RCC_APB2ENR register *****************/
Jasper_lee 0:b16d94660a33 3613 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
Jasper_lee 0:b16d94660a33 3614 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
Jasper_lee 0:b16d94660a33 3615 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Jasper_lee 0:b16d94660a33 3616 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Jasper_lee 0:b16d94660a33 3617 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Jasper_lee 0:b16d94660a33 3618 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
Jasper_lee 0:b16d94660a33 3619 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Jasper_lee 0:b16d94660a33 3620 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Jasper_lee 0:b16d94660a33 3621 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
Jasper_lee 0:b16d94660a33 3622
Jasper_lee 0:b16d94660a33 3623 /* Old Bit definition maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 3624 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Jasper_lee 0:b16d94660a33 3625 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Jasper_lee 0:b16d94660a33 3626
Jasper_lee 0:b16d94660a33 3627 /***************** Bit definition for RCC_APB1ENR register *****************/
Jasper_lee 0:b16d94660a33 3628 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
Jasper_lee 0:b16d94660a33 3629 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Jasper_lee 0:b16d94660a33 3630 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
Jasper_lee 0:b16d94660a33 3631 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
Jasper_lee 0:b16d94660a33 3632 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
Jasper_lee 0:b16d94660a33 3633 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Jasper_lee 0:b16d94660a33 3634 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
Jasper_lee 0:b16d94660a33 3635 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
Jasper_lee 0:b16d94660a33 3636 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
Jasper_lee 0:b16d94660a33 3637 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
Jasper_lee 0:b16d94660a33 3638 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
Jasper_lee 0:b16d94660a33 3639 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
Jasper_lee 0:b16d94660a33 3640 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
Jasper_lee 0:b16d94660a33 3641 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
Jasper_lee 0:b16d94660a33 3642 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
Jasper_lee 0:b16d94660a33 3643 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Jasper_lee 0:b16d94660a33 3644 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
Jasper_lee 0:b16d94660a33 3645 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
Jasper_lee 0:b16d94660a33 3646
Jasper_lee 0:b16d94660a33 3647 /******************* Bit definition for RCC_BDCR register ******************/
Jasper_lee 0:b16d94660a33 3648 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Jasper_lee 0:b16d94660a33 3649 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Jasper_lee 0:b16d94660a33 3650 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Jasper_lee 0:b16d94660a33 3651
Jasper_lee 0:b16d94660a33 3652 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Jasper_lee 0:b16d94660a33 3653 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3654 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3655
Jasper_lee 0:b16d94660a33 3656 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Jasper_lee 0:b16d94660a33 3657 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3658 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3659
Jasper_lee 0:b16d94660a33 3660 /*!< RTC configuration */
Jasper_lee 0:b16d94660a33 3661 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Jasper_lee 0:b16d94660a33 3662 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Jasper_lee 0:b16d94660a33 3663 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Jasper_lee 0:b16d94660a33 3664 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Jasper_lee 0:b16d94660a33 3665
Jasper_lee 0:b16d94660a33 3666 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Jasper_lee 0:b16d94660a33 3667 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Jasper_lee 0:b16d94660a33 3668
Jasper_lee 0:b16d94660a33 3669 /******************* Bit definition for RCC_CSR register *******************/
Jasper_lee 0:b16d94660a33 3670 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Jasper_lee 0:b16d94660a33 3671 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Jasper_lee 0:b16d94660a33 3672 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
Jasper_lee 0:b16d94660a33 3673 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Jasper_lee 0:b16d94660a33 3674 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Jasper_lee 0:b16d94660a33 3675 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Jasper_lee 0:b16d94660a33 3676 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Jasper_lee 0:b16d94660a33 3677 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Jasper_lee 0:b16d94660a33 3678 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Jasper_lee 0:b16d94660a33 3679 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Jasper_lee 0:b16d94660a33 3680 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Jasper_lee 0:b16d94660a33 3681
Jasper_lee 0:b16d94660a33 3682 /* Old Bit definition maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 3683 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Jasper_lee 0:b16d94660a33 3684
Jasper_lee 0:b16d94660a33 3685 /******************* Bit definition for RCC_AHBRSTR register ***************/
Jasper_lee 0:b16d94660a33 3686 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
Jasper_lee 0:b16d94660a33 3687 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
Jasper_lee 0:b16d94660a33 3688 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
Jasper_lee 0:b16d94660a33 3689 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
Jasper_lee 0:b16d94660a33 3690 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
Jasper_lee 0:b16d94660a33 3691 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
Jasper_lee 0:b16d94660a33 3692 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
Jasper_lee 0:b16d94660a33 3693
Jasper_lee 0:b16d94660a33 3694 /* Old Bit definition maintained for legacy purpose */
Jasper_lee 0:b16d94660a33 3695 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
Jasper_lee 0:b16d94660a33 3696
Jasper_lee 0:b16d94660a33 3697 /******************* Bit definition for RCC_CFGR2 register *****************/
Jasper_lee 0:b16d94660a33 3698 /*!< PREDIV configuration */
Jasper_lee 0:b16d94660a33 3699 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Jasper_lee 0:b16d94660a33 3700 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3701 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3702 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 3703 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 3704
Jasper_lee 0:b16d94660a33 3705 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Jasper_lee 0:b16d94660a33 3706 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Jasper_lee 0:b16d94660a33 3707 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Jasper_lee 0:b16d94660a33 3708 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Jasper_lee 0:b16d94660a33 3709 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Jasper_lee 0:b16d94660a33 3710 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Jasper_lee 0:b16d94660a33 3711 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Jasper_lee 0:b16d94660a33 3712 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Jasper_lee 0:b16d94660a33 3713 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Jasper_lee 0:b16d94660a33 3714 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Jasper_lee 0:b16d94660a33 3715 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Jasper_lee 0:b16d94660a33 3716 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Jasper_lee 0:b16d94660a33 3717 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Jasper_lee 0:b16d94660a33 3718 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Jasper_lee 0:b16d94660a33 3719 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Jasper_lee 0:b16d94660a33 3720 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Jasper_lee 0:b16d94660a33 3721
Jasper_lee 0:b16d94660a33 3722 /******************* Bit definition for RCC_CFGR3 register *****************/
Jasper_lee 0:b16d94660a33 3723 /*!< USART1 Clock source selection */
Jasper_lee 0:b16d94660a33 3724 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Jasper_lee 0:b16d94660a33 3725 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3726 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3727
Jasper_lee 0:b16d94660a33 3728 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
Jasper_lee 0:b16d94660a33 3729 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Jasper_lee 0:b16d94660a33 3730 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Jasper_lee 0:b16d94660a33 3731 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Jasper_lee 0:b16d94660a33 3732
Jasper_lee 0:b16d94660a33 3733 /*!< I2C1 Clock source selection */
Jasper_lee 0:b16d94660a33 3734 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Jasper_lee 0:b16d94660a33 3735
Jasper_lee 0:b16d94660a33 3736 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Jasper_lee 0:b16d94660a33 3737 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Jasper_lee 0:b16d94660a33 3738
Jasper_lee 0:b16d94660a33 3739 /*!< CEC Clock source selection */
Jasper_lee 0:b16d94660a33 3740 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
Jasper_lee 0:b16d94660a33 3741
Jasper_lee 0:b16d94660a33 3742 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
Jasper_lee 0:b16d94660a33 3743 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
Jasper_lee 0:b16d94660a33 3744
Jasper_lee 0:b16d94660a33 3745 /*!< USB Clock source selection */
Jasper_lee 0:b16d94660a33 3746 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
Jasper_lee 0:b16d94660a33 3747
Jasper_lee 0:b16d94660a33 3748 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
Jasper_lee 0:b16d94660a33 3749 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
Jasper_lee 0:b16d94660a33 3750
Jasper_lee 0:b16d94660a33 3751 /*!< USART2 Clock source selection */
Jasper_lee 0:b16d94660a33 3752 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
Jasper_lee 0:b16d94660a33 3753 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 3754 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 3755
Jasper_lee 0:b16d94660a33 3756 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
Jasper_lee 0:b16d94660a33 3757 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
Jasper_lee 0:b16d94660a33 3758 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
Jasper_lee 0:b16d94660a33 3759 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
Jasper_lee 0:b16d94660a33 3760
Jasper_lee 0:b16d94660a33 3761 /******************* Bit definition for RCC_CR2 register *******************/
Jasper_lee 0:b16d94660a33 3762 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
Jasper_lee 0:b16d94660a33 3763 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
Jasper_lee 0:b16d94660a33 3764 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
Jasper_lee 0:b16d94660a33 3765 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
Jasper_lee 0:b16d94660a33 3766 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
Jasper_lee 0:b16d94660a33 3767 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
Jasper_lee 0:b16d94660a33 3768 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
Jasper_lee 0:b16d94660a33 3769 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
Jasper_lee 0:b16d94660a33 3770
Jasper_lee 0:b16d94660a33 3771 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3772 /* */
Jasper_lee 0:b16d94660a33 3773 /* Real-Time Clock (RTC) */
Jasper_lee 0:b16d94660a33 3774 /* */
Jasper_lee 0:b16d94660a33 3775 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 3776 /******************** Bits definition for RTC_TR register ******************/
Jasper_lee 0:b16d94660a33 3777 #define RTC_TR_PM ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3778 #define RTC_TR_HT ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 3779 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3780 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3781 #define RTC_TR_HU ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3782 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3783 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3784 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3785 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3786 #define RTC_TR_MNT ((uint32_t)0x00007000)
Jasper_lee 0:b16d94660a33 3787 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3788 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3789 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3790 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3791 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3792 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3793 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3794 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3795 #define RTC_TR_ST ((uint32_t)0x00000070)
Jasper_lee 0:b16d94660a33 3796 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3797 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3798 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3799 #define RTC_TR_SU ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3800 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3801 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3802 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3803 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3804
Jasper_lee 0:b16d94660a33 3805 /******************** Bits definition for RTC_DR register ******************/
Jasper_lee 0:b16d94660a33 3806 #define RTC_DR_YT ((uint32_t)0x00F00000)
Jasper_lee 0:b16d94660a33 3807 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3808 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3809 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3810 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 3811 #define RTC_DR_YU ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3812 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3813 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3814 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3815 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3816 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Jasper_lee 0:b16d94660a33 3817 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3818 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3819 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3820 #define RTC_DR_MT ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3821 #define RTC_DR_MU ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3822 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3823 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3824 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3825 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3826 #define RTC_DR_DT ((uint32_t)0x00000030)
Jasper_lee 0:b16d94660a33 3827 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3828 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3829 #define RTC_DR_DU ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3830 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3831 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3832 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3833 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3834
Jasper_lee 0:b16d94660a33 3835 /******************** Bits definition for RTC_CR register ******************/
Jasper_lee 0:b16d94660a33 3836 #define RTC_CR_COE ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 3837 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Jasper_lee 0:b16d94660a33 3838 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3839 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3840 #define RTC_CR_POL ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3841 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3842 #define RTC_CR_BCK ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3843 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3844 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3845 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3846 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3847 #define RTC_CR_TSE ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3848 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3849 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3850 #define RTC_CR_FMT ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3851 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3852 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3853 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3854 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Jasper_lee 0:b16d94660a33 3855 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3856 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3857 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3858
Jasper_lee 0:b16d94660a33 3859 /******************** Bits definition for RTC_ISR register *****************/
Jasper_lee 0:b16d94660a33 3860 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3861 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3862 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3863 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3864 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3865 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3866 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3867 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3868 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3869 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3870 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3871 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3872 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3873 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3874 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3875
Jasper_lee 0:b16d94660a33 3876 /******************** Bits definition for RTC_PRER register ****************/
Jasper_lee 0:b16d94660a33 3877 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Jasper_lee 0:b16d94660a33 3878 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Jasper_lee 0:b16d94660a33 3879
Jasper_lee 0:b16d94660a33 3880 /******************** Bits definition for RTC_WUTR register ****************/
Jasper_lee 0:b16d94660a33 3881 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Jasper_lee 0:b16d94660a33 3882
Jasper_lee 0:b16d94660a33 3883 /******************** Bits definition for RTC_ALRMAR register **************/
Jasper_lee 0:b16d94660a33 3884 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 3885 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Jasper_lee 0:b16d94660a33 3886 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Jasper_lee 0:b16d94660a33 3887 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Jasper_lee 0:b16d94660a33 3888 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Jasper_lee 0:b16d94660a33 3889 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Jasper_lee 0:b16d94660a33 3890 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 3891 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 3892 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 3893 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 3894 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Jasper_lee 0:b16d94660a33 3895 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3896 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 3897 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3898 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3899 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3900 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3901 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3902 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3903 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3904 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3905 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Jasper_lee 0:b16d94660a33 3906 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3907 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3908 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3909 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3910 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3911 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3912 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3913 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3914 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 3915 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Jasper_lee 0:b16d94660a33 3916 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3917 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3918 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3919 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3920 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3921 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3922 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3923 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3924
Jasper_lee 0:b16d94660a33 3925 /******************** Bits definition for RTC_WPR register *****************/
Jasper_lee 0:b16d94660a33 3926 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Jasper_lee 0:b16d94660a33 3927
Jasper_lee 0:b16d94660a33 3928 /******************** Bits definition for RTC_SSR register *****************/
Jasper_lee 0:b16d94660a33 3929 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Jasper_lee 0:b16d94660a33 3930
Jasper_lee 0:b16d94660a33 3931 /******************** Bits definition for RTC_SHIFTR register **************/
Jasper_lee 0:b16d94660a33 3932 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Jasper_lee 0:b16d94660a33 3933 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Jasper_lee 0:b16d94660a33 3934
Jasper_lee 0:b16d94660a33 3935 /******************** Bits definition for RTC_TSTR register ****************/
Jasper_lee 0:b16d94660a33 3936 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Jasper_lee 0:b16d94660a33 3937 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Jasper_lee 0:b16d94660a33 3938 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Jasper_lee 0:b16d94660a33 3939 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Jasper_lee 0:b16d94660a33 3940 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Jasper_lee 0:b16d94660a33 3941 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Jasper_lee 0:b16d94660a33 3942 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Jasper_lee 0:b16d94660a33 3943 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 3944 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Jasper_lee 0:b16d94660a33 3945 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Jasper_lee 0:b16d94660a33 3946 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3947 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3948 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3949 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3950 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3951 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3952 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3953 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3954 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Jasper_lee 0:b16d94660a33 3955 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3956 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3957 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3958 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3959 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3960 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3961 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3962 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3963
Jasper_lee 0:b16d94660a33 3964 /******************** Bits definition for RTC_TSDR register ****************/
Jasper_lee 0:b16d94660a33 3965 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Jasper_lee 0:b16d94660a33 3966 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3967 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3968 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3969 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 3970 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Jasper_lee 0:b16d94660a33 3971 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 3972 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 3973 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 3974 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 3975 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Jasper_lee 0:b16d94660a33 3976 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3977 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3978 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Jasper_lee 0:b16d94660a33 3979 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3980 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3981 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3982 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3983
Jasper_lee 0:b16d94660a33 3984 /******************** Bits definition for RTC_TSSSR register ***************/
Jasper_lee 0:b16d94660a33 3985 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Jasper_lee 0:b16d94660a33 3986
Jasper_lee 0:b16d94660a33 3987 /******************** Bits definition for RTC_CALR register ****************/
Jasper_lee 0:b16d94660a33 3988 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 3989 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 3990 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 3991 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Jasper_lee 0:b16d94660a33 3992 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 3993 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 3994 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 3995 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 3996 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 3997 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 3998 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 3999 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 4000 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 4001
Jasper_lee 0:b16d94660a33 4002 /******************** Bits definition for RTC_TAFCR register ***************/
Jasper_lee 0:b16d94660a33 4003 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Jasper_lee 0:b16d94660a33 4004 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Jasper_lee 0:b16d94660a33 4005 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Jasper_lee 0:b16d94660a33 4006 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Jasper_lee 0:b16d94660a33 4007 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Jasper_lee 0:b16d94660a33 4008 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Jasper_lee 0:b16d94660a33 4009 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Jasper_lee 0:b16d94660a33 4010 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Jasper_lee 0:b16d94660a33 4011 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Jasper_lee 0:b16d94660a33 4012 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Jasper_lee 0:b16d94660a33 4013 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Jasper_lee 0:b16d94660a33 4014 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Jasper_lee 0:b16d94660a33 4015 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Jasper_lee 0:b16d94660a33 4016 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
Jasper_lee 0:b16d94660a33 4017 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
Jasper_lee 0:b16d94660a33 4018 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Jasper_lee 0:b16d94660a33 4019 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Jasper_lee 0:b16d94660a33 4020 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Jasper_lee 0:b16d94660a33 4021 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Jasper_lee 0:b16d94660a33 4022 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Jasper_lee 0:b16d94660a33 4023
Jasper_lee 0:b16d94660a33 4024 /******************** Bits definition for RTC_ALRMASSR register ************/
Jasper_lee 0:b16d94660a33 4025 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Jasper_lee 0:b16d94660a33 4026 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Jasper_lee 0:b16d94660a33 4027 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Jasper_lee 0:b16d94660a33 4028 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Jasper_lee 0:b16d94660a33 4029 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Jasper_lee 0:b16d94660a33 4030 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Jasper_lee 0:b16d94660a33 4031
Jasper_lee 0:b16d94660a33 4032 /******************** Bits definition for RTC_BKP0R register ***************/
Jasper_lee 0:b16d94660a33 4033 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Jasper_lee 0:b16d94660a33 4034
Jasper_lee 0:b16d94660a33 4035 /******************** Bits definition for RTC_BKP1R register ***************/
Jasper_lee 0:b16d94660a33 4036 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Jasper_lee 0:b16d94660a33 4037
Jasper_lee 0:b16d94660a33 4038 /******************** Bits definition for RTC_BKP2R register ***************/
Jasper_lee 0:b16d94660a33 4039 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Jasper_lee 0:b16d94660a33 4040
Jasper_lee 0:b16d94660a33 4041 /******************** Bits definition for RTC_BKP3R register ***************/
Jasper_lee 0:b16d94660a33 4042 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Jasper_lee 0:b16d94660a33 4043
Jasper_lee 0:b16d94660a33 4044 /******************** Bits definition for RTC_BKP4R register ***************/
Jasper_lee 0:b16d94660a33 4045 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Jasper_lee 0:b16d94660a33 4046
Jasper_lee 0:b16d94660a33 4047 /******************** Number of backup registers ******************************/
Jasper_lee 0:b16d94660a33 4048 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
Jasper_lee 0:b16d94660a33 4049
Jasper_lee 0:b16d94660a33 4050 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4051 /* */
Jasper_lee 0:b16d94660a33 4052 /* Serial Peripheral Interface (SPI) */
Jasper_lee 0:b16d94660a33 4053 /* */
Jasper_lee 0:b16d94660a33 4054 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4055 /******************* Bit definition for SPI_CR1 register *******************/
Jasper_lee 0:b16d94660a33 4056 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Jasper_lee 0:b16d94660a33 4057 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Jasper_lee 0:b16d94660a33 4058 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Jasper_lee 0:b16d94660a33 4059 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Jasper_lee 0:b16d94660a33 4060 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4061 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4062 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 4063 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Jasper_lee 0:b16d94660a33 4064 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Jasper_lee 0:b16d94660a33 4065 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Jasper_lee 0:b16d94660a33 4066 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Jasper_lee 0:b16d94660a33 4067 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Jasper_lee 0:b16d94660a33 4068 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Jasper_lee 0:b16d94660a33 4069 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Jasper_lee 0:b16d94660a33 4070 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Jasper_lee 0:b16d94660a33 4071 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Jasper_lee 0:b16d94660a33 4072 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Jasper_lee 0:b16d94660a33 4073
Jasper_lee 0:b16d94660a33 4074 /******************* Bit definition for SPI_CR2 register *******************/
Jasper_lee 0:b16d94660a33 4075 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Jasper_lee 0:b16d94660a33 4076 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Jasper_lee 0:b16d94660a33 4077 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Jasper_lee 0:b16d94660a33 4078 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Jasper_lee 0:b16d94660a33 4079 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Jasper_lee 0:b16d94660a33 4080 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Jasper_lee 0:b16d94660a33 4081 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Jasper_lee 0:b16d94660a33 4082 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Jasper_lee 0:b16d94660a33 4083 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Jasper_lee 0:b16d94660a33 4084 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4085 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4086 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 4087 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 4088 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Jasper_lee 0:b16d94660a33 4089 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Jasper_lee 0:b16d94660a33 4090 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Jasper_lee 0:b16d94660a33 4091
Jasper_lee 0:b16d94660a33 4092 /******************** Bit definition for SPI_SR register *******************/
Jasper_lee 0:b16d94660a33 4093 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Jasper_lee 0:b16d94660a33 4094 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Jasper_lee 0:b16d94660a33 4095 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Jasper_lee 0:b16d94660a33 4096 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Jasper_lee 0:b16d94660a33 4097 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Jasper_lee 0:b16d94660a33 4098 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Jasper_lee 0:b16d94660a33 4099 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Jasper_lee 0:b16d94660a33 4100 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Jasper_lee 0:b16d94660a33 4101 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Jasper_lee 0:b16d94660a33 4102 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Jasper_lee 0:b16d94660a33 4103 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4104 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4105 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Jasper_lee 0:b16d94660a33 4106 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4107 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4108
Jasper_lee 0:b16d94660a33 4109 /******************** Bit definition for SPI_DR register *******************/
Jasper_lee 0:b16d94660a33 4110 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
Jasper_lee 0:b16d94660a33 4111
Jasper_lee 0:b16d94660a33 4112 /******************* Bit definition for SPI_CRCPR register *****************/
Jasper_lee 0:b16d94660a33 4113 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
Jasper_lee 0:b16d94660a33 4114
Jasper_lee 0:b16d94660a33 4115 /****************** Bit definition for SPI_RXCRCR register *****************/
Jasper_lee 0:b16d94660a33 4116 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
Jasper_lee 0:b16d94660a33 4117
Jasper_lee 0:b16d94660a33 4118 /****************** Bit definition for SPI_TXCRCR register *****************/
Jasper_lee 0:b16d94660a33 4119 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
Jasper_lee 0:b16d94660a33 4120
Jasper_lee 0:b16d94660a33 4121 /****************** Bit definition for SPI_I2SCFGR register ****************/
Jasper_lee 0:b16d94660a33 4122 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Jasper_lee 0:b16d94660a33 4123 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Jasper_lee 0:b16d94660a33 4124 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4125 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4126 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Jasper_lee 0:b16d94660a33 4127 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Jasper_lee 0:b16d94660a33 4128 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4129 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4130 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Jasper_lee 0:b16d94660a33 4131 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Jasper_lee 0:b16d94660a33 4132 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4133 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4134 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Jasper_lee 0:b16d94660a33 4135 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Jasper_lee 0:b16d94660a33 4136
Jasper_lee 0:b16d94660a33 4137 /****************** Bit definition for SPI_I2SPR register ******************/
Jasper_lee 0:b16d94660a33 4138 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Jasper_lee 0:b16d94660a33 4139 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Jasper_lee 0:b16d94660a33 4140 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Jasper_lee 0:b16d94660a33 4141
Jasper_lee 0:b16d94660a33 4142 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4143 /* */
Jasper_lee 0:b16d94660a33 4144 /* System Configuration (SYSCFG) */
Jasper_lee 0:b16d94660a33 4145 /* */
Jasper_lee 0:b16d94660a33 4146 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4147 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Jasper_lee 0:b16d94660a33 4148 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Jasper_lee 0:b16d94660a33 4149 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
Jasper_lee 0:b16d94660a33 4150 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
Jasper_lee 0:b16d94660a33 4151
Jasper_lee 0:b16d94660a33 4152 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
Jasper_lee 0:b16d94660a33 4153 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
Jasper_lee 0:b16d94660a33 4154 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
Jasper_lee 0:b16d94660a33 4155 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
Jasper_lee 0:b16d94660a33 4156 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
Jasper_lee 0:b16d94660a33 4157 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
Jasper_lee 0:b16d94660a33 4158 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
Jasper_lee 0:b16d94660a33 4159 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
Jasper_lee 0:b16d94660a33 4160 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
Jasper_lee 0:b16d94660a33 4161 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
Jasper_lee 0:b16d94660a33 4162 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
Jasper_lee 0:b16d94660a33 4163 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
Jasper_lee 0:b16d94660a33 4164 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
Jasper_lee 0:b16d94660a33 4165 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
Jasper_lee 0:b16d94660a33 4166 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
Jasper_lee 0:b16d94660a33 4167
Jasper_lee 0:b16d94660a33 4168 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Jasper_lee 0:b16d94660a33 4169 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Jasper_lee 0:b16d94660a33 4170 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Jasper_lee 0:b16d94660a33 4171 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Jasper_lee 0:b16d94660a33 4172 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Jasper_lee 0:b16d94660a33 4173 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
Jasper_lee 0:b16d94660a33 4174
Jasper_lee 0:b16d94660a33 4175 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Jasper_lee 0:b16d94660a33 4176 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
Jasper_lee 0:b16d94660a33 4177 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
Jasper_lee 0:b16d94660a33 4178 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
Jasper_lee 0:b16d94660a33 4179 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
Jasper_lee 0:b16d94660a33 4180
Jasper_lee 0:b16d94660a33 4181 /**
Jasper_lee 0:b16d94660a33 4182 * @brief EXTI0 configuration
Jasper_lee 0:b16d94660a33 4183 */
Jasper_lee 0:b16d94660a33 4184 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
Jasper_lee 0:b16d94660a33 4185 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
Jasper_lee 0:b16d94660a33 4186 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
Jasper_lee 0:b16d94660a33 4187 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
Jasper_lee 0:b16d94660a33 4188 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
Jasper_lee 0:b16d94660a33 4189 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
Jasper_lee 0:b16d94660a33 4190
Jasper_lee 0:b16d94660a33 4191 /**
Jasper_lee 0:b16d94660a33 4192 * @brief EXTI1 configuration
Jasper_lee 0:b16d94660a33 4193 */
Jasper_lee 0:b16d94660a33 4194 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
Jasper_lee 0:b16d94660a33 4195 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
Jasper_lee 0:b16d94660a33 4196 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
Jasper_lee 0:b16d94660a33 4197 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
Jasper_lee 0:b16d94660a33 4198 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
Jasper_lee 0:b16d94660a33 4199 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
Jasper_lee 0:b16d94660a33 4200
Jasper_lee 0:b16d94660a33 4201 /**
Jasper_lee 0:b16d94660a33 4202 * @brief EXTI2 configuration
Jasper_lee 0:b16d94660a33 4203 */
Jasper_lee 0:b16d94660a33 4204 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
Jasper_lee 0:b16d94660a33 4205 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
Jasper_lee 0:b16d94660a33 4206 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
Jasper_lee 0:b16d94660a33 4207 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
Jasper_lee 0:b16d94660a33 4208 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
Jasper_lee 0:b16d94660a33 4209 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
Jasper_lee 0:b16d94660a33 4210
Jasper_lee 0:b16d94660a33 4211 /**
Jasper_lee 0:b16d94660a33 4212 * @brief EXTI3 configuration
Jasper_lee 0:b16d94660a33 4213 */
Jasper_lee 0:b16d94660a33 4214 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
Jasper_lee 0:b16d94660a33 4215 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
Jasper_lee 0:b16d94660a33 4216 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
Jasper_lee 0:b16d94660a33 4217 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
Jasper_lee 0:b16d94660a33 4218 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
Jasper_lee 0:b16d94660a33 4219 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
Jasper_lee 0:b16d94660a33 4220
Jasper_lee 0:b16d94660a33 4221 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Jasper_lee 0:b16d94660a33 4222 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
Jasper_lee 0:b16d94660a33 4223 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
Jasper_lee 0:b16d94660a33 4224 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
Jasper_lee 0:b16d94660a33 4225 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
Jasper_lee 0:b16d94660a33 4226
Jasper_lee 0:b16d94660a33 4227 /**
Jasper_lee 0:b16d94660a33 4228 * @brief EXTI4 configuration
Jasper_lee 0:b16d94660a33 4229 */
Jasper_lee 0:b16d94660a33 4230 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
Jasper_lee 0:b16d94660a33 4231 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
Jasper_lee 0:b16d94660a33 4232 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
Jasper_lee 0:b16d94660a33 4233 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
Jasper_lee 0:b16d94660a33 4234 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
Jasper_lee 0:b16d94660a33 4235 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
Jasper_lee 0:b16d94660a33 4236
Jasper_lee 0:b16d94660a33 4237 /**
Jasper_lee 0:b16d94660a33 4238 * @brief EXTI5 configuration
Jasper_lee 0:b16d94660a33 4239 */
Jasper_lee 0:b16d94660a33 4240 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
Jasper_lee 0:b16d94660a33 4241 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
Jasper_lee 0:b16d94660a33 4242 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
Jasper_lee 0:b16d94660a33 4243 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
Jasper_lee 0:b16d94660a33 4244 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
Jasper_lee 0:b16d94660a33 4245 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
Jasper_lee 0:b16d94660a33 4246
Jasper_lee 0:b16d94660a33 4247 /**
Jasper_lee 0:b16d94660a33 4248 * @brief EXTI6 configuration
Jasper_lee 0:b16d94660a33 4249 */
Jasper_lee 0:b16d94660a33 4250 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
Jasper_lee 0:b16d94660a33 4251 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
Jasper_lee 0:b16d94660a33 4252 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
Jasper_lee 0:b16d94660a33 4253 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
Jasper_lee 0:b16d94660a33 4254 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
Jasper_lee 0:b16d94660a33 4255 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
Jasper_lee 0:b16d94660a33 4256
Jasper_lee 0:b16d94660a33 4257 /**
Jasper_lee 0:b16d94660a33 4258 * @brief EXTI7 configuration
Jasper_lee 0:b16d94660a33 4259 */
Jasper_lee 0:b16d94660a33 4260 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
Jasper_lee 0:b16d94660a33 4261 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
Jasper_lee 0:b16d94660a33 4262 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
Jasper_lee 0:b16d94660a33 4263 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
Jasper_lee 0:b16d94660a33 4264 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
Jasper_lee 0:b16d94660a33 4265 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
Jasper_lee 0:b16d94660a33 4266
Jasper_lee 0:b16d94660a33 4267 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Jasper_lee 0:b16d94660a33 4268 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
Jasper_lee 0:b16d94660a33 4269 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
Jasper_lee 0:b16d94660a33 4270 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
Jasper_lee 0:b16d94660a33 4271 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
Jasper_lee 0:b16d94660a33 4272
Jasper_lee 0:b16d94660a33 4273 /**
Jasper_lee 0:b16d94660a33 4274 * @brief EXTI8 configuration
Jasper_lee 0:b16d94660a33 4275 */
Jasper_lee 0:b16d94660a33 4276 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
Jasper_lee 0:b16d94660a33 4277 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
Jasper_lee 0:b16d94660a33 4278 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
Jasper_lee 0:b16d94660a33 4279 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
Jasper_lee 0:b16d94660a33 4280 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
Jasper_lee 0:b16d94660a33 4281
Jasper_lee 0:b16d94660a33 4282 /**
Jasper_lee 0:b16d94660a33 4283 * @brief EXTI9 configuration
Jasper_lee 0:b16d94660a33 4284 */
Jasper_lee 0:b16d94660a33 4285 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
Jasper_lee 0:b16d94660a33 4286 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
Jasper_lee 0:b16d94660a33 4287 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
Jasper_lee 0:b16d94660a33 4288 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
Jasper_lee 0:b16d94660a33 4289 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
Jasper_lee 0:b16d94660a33 4290 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
Jasper_lee 0:b16d94660a33 4291
Jasper_lee 0:b16d94660a33 4292 /**
Jasper_lee 0:b16d94660a33 4293 * @brief EXTI10 configuration
Jasper_lee 0:b16d94660a33 4294 */
Jasper_lee 0:b16d94660a33 4295 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
Jasper_lee 0:b16d94660a33 4296 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
Jasper_lee 0:b16d94660a33 4297 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
Jasper_lee 0:b16d94660a33 4298 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
Jasper_lee 0:b16d94660a33 4299 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
Jasper_lee 0:b16d94660a33 4300 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
Jasper_lee 0:b16d94660a33 4301
Jasper_lee 0:b16d94660a33 4302 /**
Jasper_lee 0:b16d94660a33 4303 * @brief EXTI11 configuration
Jasper_lee 0:b16d94660a33 4304 */
Jasper_lee 0:b16d94660a33 4305 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
Jasper_lee 0:b16d94660a33 4306 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
Jasper_lee 0:b16d94660a33 4307 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
Jasper_lee 0:b16d94660a33 4308 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
Jasper_lee 0:b16d94660a33 4309 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
Jasper_lee 0:b16d94660a33 4310
Jasper_lee 0:b16d94660a33 4311 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Jasper_lee 0:b16d94660a33 4312 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
Jasper_lee 0:b16d94660a33 4313 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
Jasper_lee 0:b16d94660a33 4314 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
Jasper_lee 0:b16d94660a33 4315 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
Jasper_lee 0:b16d94660a33 4316
Jasper_lee 0:b16d94660a33 4317 /**
Jasper_lee 0:b16d94660a33 4318 * @brief EXTI12 configuration
Jasper_lee 0:b16d94660a33 4319 */
Jasper_lee 0:b16d94660a33 4320 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
Jasper_lee 0:b16d94660a33 4321 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
Jasper_lee 0:b16d94660a33 4322 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
Jasper_lee 0:b16d94660a33 4323 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
Jasper_lee 0:b16d94660a33 4324 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
Jasper_lee 0:b16d94660a33 4325
Jasper_lee 0:b16d94660a33 4326 /**
Jasper_lee 0:b16d94660a33 4327 * @brief EXTI13 configuration
Jasper_lee 0:b16d94660a33 4328 */
Jasper_lee 0:b16d94660a33 4329 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
Jasper_lee 0:b16d94660a33 4330 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
Jasper_lee 0:b16d94660a33 4331 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
Jasper_lee 0:b16d94660a33 4332 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
Jasper_lee 0:b16d94660a33 4333 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
Jasper_lee 0:b16d94660a33 4334
Jasper_lee 0:b16d94660a33 4335 /**
Jasper_lee 0:b16d94660a33 4336 * @brief EXTI14 configuration
Jasper_lee 0:b16d94660a33 4337 */
Jasper_lee 0:b16d94660a33 4338 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
Jasper_lee 0:b16d94660a33 4339 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
Jasper_lee 0:b16d94660a33 4340 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
Jasper_lee 0:b16d94660a33 4341 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
Jasper_lee 0:b16d94660a33 4342 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
Jasper_lee 0:b16d94660a33 4343
Jasper_lee 0:b16d94660a33 4344 /**
Jasper_lee 0:b16d94660a33 4345 * @brief EXTI15 configuration
Jasper_lee 0:b16d94660a33 4346 */
Jasper_lee 0:b16d94660a33 4347 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
Jasper_lee 0:b16d94660a33 4348 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
Jasper_lee 0:b16d94660a33 4349 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
Jasper_lee 0:b16d94660a33 4350 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
Jasper_lee 0:b16d94660a33 4351 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
Jasper_lee 0:b16d94660a33 4352
Jasper_lee 0:b16d94660a33 4353 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Jasper_lee 0:b16d94660a33 4354 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Jasper_lee 0:b16d94660a33 4355 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Jasper_lee 0:b16d94660a33 4356 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
Jasper_lee 0:b16d94660a33 4357 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Jasper_lee 0:b16d94660a33 4358 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Jasper_lee 0:b16d94660a33 4359
Jasper_lee 0:b16d94660a33 4360 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4361 /* */
Jasper_lee 0:b16d94660a33 4362 /* Timers (TIM) */
Jasper_lee 0:b16d94660a33 4363 /* */
Jasper_lee 0:b16d94660a33 4364 /*****************************************************************************/
Jasper_lee 0:b16d94660a33 4365 /******************* Bit definition for TIM_CR1 register *******************/
Jasper_lee 0:b16d94660a33 4366 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Jasper_lee 0:b16d94660a33 4367 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Jasper_lee 0:b16d94660a33 4368 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Jasper_lee 0:b16d94660a33 4369 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Jasper_lee 0:b16d94660a33 4370 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Jasper_lee 0:b16d94660a33 4371
Jasper_lee 0:b16d94660a33 4372 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Jasper_lee 0:b16d94660a33 4373 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4374 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4375
Jasper_lee 0:b16d94660a33 4376 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Jasper_lee 0:b16d94660a33 4377
Jasper_lee 0:b16d94660a33 4378 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Jasper_lee 0:b16d94660a33 4379 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4380 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4381
Jasper_lee 0:b16d94660a33 4382 /******************* Bit definition for TIM_CR2 register *******************/
Jasper_lee 0:b16d94660a33 4383 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Jasper_lee 0:b16d94660a33 4384 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Jasper_lee 0:b16d94660a33 4385 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Jasper_lee 0:b16d94660a33 4386
Jasper_lee 0:b16d94660a33 4387 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Jasper_lee 0:b16d94660a33 4388 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4389 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4390 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4391
Jasper_lee 0:b16d94660a33 4392 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Jasper_lee 0:b16d94660a33 4393 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Jasper_lee 0:b16d94660a33 4394 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Jasper_lee 0:b16d94660a33 4395 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Jasper_lee 0:b16d94660a33 4396 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Jasper_lee 0:b16d94660a33 4397 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Jasper_lee 0:b16d94660a33 4398 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Jasper_lee 0:b16d94660a33 4399 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Jasper_lee 0:b16d94660a33 4400
Jasper_lee 0:b16d94660a33 4401 /******************* Bit definition for TIM_SMCR register ******************/
Jasper_lee 0:b16d94660a33 4402 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Jasper_lee 0:b16d94660a33 4403 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4404 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4405 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4406
Jasper_lee 0:b16d94660a33 4407 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Jasper_lee 0:b16d94660a33 4408
Jasper_lee 0:b16d94660a33 4409 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Jasper_lee 0:b16d94660a33 4410 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4411 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4412 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4413
Jasper_lee 0:b16d94660a33 4414 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Jasper_lee 0:b16d94660a33 4415
Jasper_lee 0:b16d94660a33 4416 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Jasper_lee 0:b16d94660a33 4417 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4418 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4419 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4420 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4421
Jasper_lee 0:b16d94660a33 4422 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Jasper_lee 0:b16d94660a33 4423 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4424 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4425
Jasper_lee 0:b16d94660a33 4426 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Jasper_lee 0:b16d94660a33 4427 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Jasper_lee 0:b16d94660a33 4428
Jasper_lee 0:b16d94660a33 4429 /******************* Bit definition for TIM_DIER register ******************/
Jasper_lee 0:b16d94660a33 4430 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Jasper_lee 0:b16d94660a33 4431 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Jasper_lee 0:b16d94660a33 4432 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Jasper_lee 0:b16d94660a33 4433 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Jasper_lee 0:b16d94660a33 4434 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Jasper_lee 0:b16d94660a33 4435 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Jasper_lee 0:b16d94660a33 4436 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Jasper_lee 0:b16d94660a33 4437 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Jasper_lee 0:b16d94660a33 4438 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Jasper_lee 0:b16d94660a33 4439 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Jasper_lee 0:b16d94660a33 4440 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Jasper_lee 0:b16d94660a33 4441 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Jasper_lee 0:b16d94660a33 4442 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Jasper_lee 0:b16d94660a33 4443 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Jasper_lee 0:b16d94660a33 4444 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Jasper_lee 0:b16d94660a33 4445
Jasper_lee 0:b16d94660a33 4446 /******************** Bit definition for TIM_SR register *******************/
Jasper_lee 0:b16d94660a33 4447 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Jasper_lee 0:b16d94660a33 4448 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Jasper_lee 0:b16d94660a33 4449 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Jasper_lee 0:b16d94660a33 4450 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Jasper_lee 0:b16d94660a33 4451 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Jasper_lee 0:b16d94660a33 4452 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Jasper_lee 0:b16d94660a33 4453 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Jasper_lee 0:b16d94660a33 4454 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Jasper_lee 0:b16d94660a33 4455 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Jasper_lee 0:b16d94660a33 4456 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Jasper_lee 0:b16d94660a33 4457 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Jasper_lee 0:b16d94660a33 4458 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Jasper_lee 0:b16d94660a33 4459
Jasper_lee 0:b16d94660a33 4460 /******************* Bit definition for TIM_EGR register *******************/
Jasper_lee 0:b16d94660a33 4461 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Jasper_lee 0:b16d94660a33 4462 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Jasper_lee 0:b16d94660a33 4463 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Jasper_lee 0:b16d94660a33 4464 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Jasper_lee 0:b16d94660a33 4465 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Jasper_lee 0:b16d94660a33 4466 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Jasper_lee 0:b16d94660a33 4467 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Jasper_lee 0:b16d94660a33 4468 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Jasper_lee 0:b16d94660a33 4469
Jasper_lee 0:b16d94660a33 4470 /****************** Bit definition for TIM_CCMR1 register ******************/
Jasper_lee 0:b16d94660a33 4471 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Jasper_lee 0:b16d94660a33 4472 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4473 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4474
Jasper_lee 0:b16d94660a33 4475 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Jasper_lee 0:b16d94660a33 4476 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Jasper_lee 0:b16d94660a33 4477
Jasper_lee 0:b16d94660a33 4478 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Jasper_lee 0:b16d94660a33 4479 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4480 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4481 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4482
Jasper_lee 0:b16d94660a33 4483 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Jasper_lee 0:b16d94660a33 4484
Jasper_lee 0:b16d94660a33 4485 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Jasper_lee 0:b16d94660a33 4486 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4487 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4488
Jasper_lee 0:b16d94660a33 4489 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Jasper_lee 0:b16d94660a33 4490 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Jasper_lee 0:b16d94660a33 4491
Jasper_lee 0:b16d94660a33 4492 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Jasper_lee 0:b16d94660a33 4493 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4494 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4495 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4496
Jasper_lee 0:b16d94660a33 4497 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Jasper_lee 0:b16d94660a33 4498
Jasper_lee 0:b16d94660a33 4499 /*---------------------------------------------------------------------------*/
Jasper_lee 0:b16d94660a33 4500
Jasper_lee 0:b16d94660a33 4501 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Jasper_lee 0:b16d94660a33 4502 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4503 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4504
Jasper_lee 0:b16d94660a33 4505 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Jasper_lee 0:b16d94660a33 4506 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4507 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4508 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4509 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4510
Jasper_lee 0:b16d94660a33 4511 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Jasper_lee 0:b16d94660a33 4512 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4513 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4514
Jasper_lee 0:b16d94660a33 4515 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Jasper_lee 0:b16d94660a33 4516 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4517 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4518 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4519 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4520
Jasper_lee 0:b16d94660a33 4521 /****************** Bit definition for TIM_CCMR2 register ******************/
Jasper_lee 0:b16d94660a33 4522 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Jasper_lee 0:b16d94660a33 4523 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4524 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4525
Jasper_lee 0:b16d94660a33 4526 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Jasper_lee 0:b16d94660a33 4527 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Jasper_lee 0:b16d94660a33 4528
Jasper_lee 0:b16d94660a33 4529 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Jasper_lee 0:b16d94660a33 4530 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4531 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4532 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4533
Jasper_lee 0:b16d94660a33 4534 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Jasper_lee 0:b16d94660a33 4535
Jasper_lee 0:b16d94660a33 4536 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Jasper_lee 0:b16d94660a33 4537 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4538 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4539
Jasper_lee 0:b16d94660a33 4540 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Jasper_lee 0:b16d94660a33 4541 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Jasper_lee 0:b16d94660a33 4542
Jasper_lee 0:b16d94660a33 4543 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Jasper_lee 0:b16d94660a33 4544 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4545 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4546 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4547
Jasper_lee 0:b16d94660a33 4548 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Jasper_lee 0:b16d94660a33 4549
Jasper_lee 0:b16d94660a33 4550 /*---------------------------------------------------------------------------*/
Jasper_lee 0:b16d94660a33 4551
Jasper_lee 0:b16d94660a33 4552 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Jasper_lee 0:b16d94660a33 4553 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4554 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4555
Jasper_lee 0:b16d94660a33 4556 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Jasper_lee 0:b16d94660a33 4557 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4558 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4559 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4560 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4561
Jasper_lee 0:b16d94660a33 4562 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Jasper_lee 0:b16d94660a33 4563 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4564 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4565
Jasper_lee 0:b16d94660a33 4566 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Jasper_lee 0:b16d94660a33 4567 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4568 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4569 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4570 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4571
Jasper_lee 0:b16d94660a33 4572 /******************* Bit definition for TIM_CCER register ******************/
Jasper_lee 0:b16d94660a33 4573 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Jasper_lee 0:b16d94660a33 4574 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Jasper_lee 0:b16d94660a33 4575 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Jasper_lee 0:b16d94660a33 4576 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Jasper_lee 0:b16d94660a33 4577 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Jasper_lee 0:b16d94660a33 4578 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Jasper_lee 0:b16d94660a33 4579 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Jasper_lee 0:b16d94660a33 4580 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Jasper_lee 0:b16d94660a33 4581 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Jasper_lee 0:b16d94660a33 4582 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Jasper_lee 0:b16d94660a33 4583 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Jasper_lee 0:b16d94660a33 4584 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Jasper_lee 0:b16d94660a33 4585 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Jasper_lee 0:b16d94660a33 4586 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Jasper_lee 0:b16d94660a33 4587 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Jasper_lee 0:b16d94660a33 4588
Jasper_lee 0:b16d94660a33 4589 /******************* Bit definition for TIM_CNT register *******************/
Jasper_lee 0:b16d94660a33 4590 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Jasper_lee 0:b16d94660a33 4591
Jasper_lee 0:b16d94660a33 4592 /******************* Bit definition for TIM_PSC register *******************/
Jasper_lee 0:b16d94660a33 4593 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Jasper_lee 0:b16d94660a33 4594
Jasper_lee 0:b16d94660a33 4595 /******************* Bit definition for TIM_ARR register *******************/
Jasper_lee 0:b16d94660a33 4596 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Jasper_lee 0:b16d94660a33 4597
Jasper_lee 0:b16d94660a33 4598 /******************* Bit definition for TIM_RCR register *******************/
Jasper_lee 0:b16d94660a33 4599 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Jasper_lee 0:b16d94660a33 4600
Jasper_lee 0:b16d94660a33 4601 /******************* Bit definition for TIM_CCR1 register ******************/
Jasper_lee 0:b16d94660a33 4602 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Jasper_lee 0:b16d94660a33 4603
Jasper_lee 0:b16d94660a33 4604 /******************* Bit definition for TIM_CCR2 register ******************/
Jasper_lee 0:b16d94660a33 4605 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Jasper_lee 0:b16d94660a33 4606
Jasper_lee 0:b16d94660a33 4607 /******************* Bit definition for TIM_CCR3 register ******************/
Jasper_lee 0:b16d94660a33 4608 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Jasper_lee 0:b16d94660a33 4609
Jasper_lee 0:b16d94660a33 4610 /******************* Bit definition for TIM_CCR4 register ******************/
Jasper_lee 0:b16d94660a33 4611 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Jasper_lee 0:b16d94660a33 4612
Jasper_lee 0:b16d94660a33 4613 /******************* Bit definition for TIM_BDTR register ******************/
Jasper_lee 0:b16d94660a33 4614 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Jasper_lee 0:b16d94660a33 4615 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4616 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4617 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4618 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4619 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 4620 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Jasper_lee 0:b16d94660a33 4621 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Jasper_lee 0:b16d94660a33 4622 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Jasper_lee 0:b16d94660a33 4623
Jasper_lee 0:b16d94660a33 4624 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Jasper_lee 0:b16d94660a33 4625 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4626 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4627
Jasper_lee 0:b16d94660a33 4628 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Jasper_lee 0:b16d94660a33 4629 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Jasper_lee 0:b16d94660a33 4630 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Jasper_lee 0:b16d94660a33 4631 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Jasper_lee 0:b16d94660a33 4632 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Jasper_lee 0:b16d94660a33 4633 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Jasper_lee 0:b16d94660a33 4634
Jasper_lee 0:b16d94660a33 4635 /******************* Bit definition for TIM_DCR register *******************/
Jasper_lee 0:b16d94660a33 4636 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Jasper_lee 0:b16d94660a33 4637 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4638 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4639 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4640 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4641 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 4642
Jasper_lee 0:b16d94660a33 4643 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Jasper_lee 0:b16d94660a33 4644 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4645 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4646 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4647 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4648 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 4649
Jasper_lee 0:b16d94660a33 4650 /******************* Bit definition for TIM_DMAR register ******************/
Jasper_lee 0:b16d94660a33 4651 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Jasper_lee 0:b16d94660a33 4652
Jasper_lee 0:b16d94660a33 4653 /******************* Bit definition for TIM14_OR register ********************/
Jasper_lee 0:b16d94660a33 4654 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Jasper_lee 0:b16d94660a33 4655 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4656 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4657
Jasper_lee 0:b16d94660a33 4658 /******************************************************************************/
Jasper_lee 0:b16d94660a33 4659 /* */
Jasper_lee 0:b16d94660a33 4660 /* Touch Sensing Controller (TSC) */
Jasper_lee 0:b16d94660a33 4661 /* */
Jasper_lee 0:b16d94660a33 4662 /******************************************************************************/
Jasper_lee 0:b16d94660a33 4663 /******************* Bit definition for TSC_CR register *********************/
Jasper_lee 0:b16d94660a33 4664 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
Jasper_lee 0:b16d94660a33 4665 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
Jasper_lee 0:b16d94660a33 4666 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
Jasper_lee 0:b16d94660a33 4667 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
Jasper_lee 0:b16d94660a33 4668 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
Jasper_lee 0:b16d94660a33 4669
Jasper_lee 0:b16d94660a33 4670 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
Jasper_lee 0:b16d94660a33 4671 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4672 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4673 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4674
Jasper_lee 0:b16d94660a33 4675 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Jasper_lee 0:b16d94660a33 4676 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4677 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4678 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4679
Jasper_lee 0:b16d94660a33 4680 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
Jasper_lee 0:b16d94660a33 4681 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
Jasper_lee 0:b16d94660a33 4682
Jasper_lee 0:b16d94660a33 4683 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Jasper_lee 0:b16d94660a33 4684 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4685 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4686 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4687 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4688 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 4689 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Jasper_lee 0:b16d94660a33 4690 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Jasper_lee 0:b16d94660a33 4691
Jasper_lee 0:b16d94660a33 4692 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Jasper_lee 0:b16d94660a33 4693 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4694 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4695 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4696 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4697
Jasper_lee 0:b16d94660a33 4698 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Jasper_lee 0:b16d94660a33 4699 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 4700 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 4701 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 4702 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 4703
Jasper_lee 0:b16d94660a33 4704 /******************* Bit definition for TSC_IER register ********************/
Jasper_lee 0:b16d94660a33 4705 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
Jasper_lee 0:b16d94660a33 4706 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
Jasper_lee 0:b16d94660a33 4707
Jasper_lee 0:b16d94660a33 4708 /******************* Bit definition for TSC_ICR register ********************/
Jasper_lee 0:b16d94660a33 4709 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
Jasper_lee 0:b16d94660a33 4710 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
Jasper_lee 0:b16d94660a33 4711
Jasper_lee 0:b16d94660a33 4712 /******************* Bit definition for TSC_ISR register ********************/
Jasper_lee 0:b16d94660a33 4713 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
Jasper_lee 0:b16d94660a33 4714 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
Jasper_lee 0:b16d94660a33 4715
Jasper_lee 0:b16d94660a33 4716 /******************* Bit definition for TSC_IOHCR register ******************/
Jasper_lee 0:b16d94660a33 4717 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4718 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4719 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4720 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4721 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4722 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4723 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4724 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4725 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4726 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4727 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4728 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4729 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4730 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4731 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4732 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4733 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4734 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4735 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4736 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4737 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4738 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4739 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4740 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4741 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4742 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4743 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4744 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4745 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4746 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4747 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4748 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Jasper_lee 0:b16d94660a33 4749
Jasper_lee 0:b16d94660a33 4750 /******************* Bit definition for TSC_IOASCR register *****************/
Jasper_lee 0:b16d94660a33 4751 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4752 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4753 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4754 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4755 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4756 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4757 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4758 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4759 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4760 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4761 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4762 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4763 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4764 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4765 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4766 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4767 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4768 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4769 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4770 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4771 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4772 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4773 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4774 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4775 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4776 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4777 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4778 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4779 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
Jasper_lee 0:b16d94660a33 4780 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
Jasper_lee 0:b16d94660a33 4781 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
Jasper_lee 0:b16d94660a33 4782 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
Jasper_lee 0:b16d94660a33 4783
Jasper_lee 0:b16d94660a33 4784 /******************* Bit definition for TSC_IOSCR register ******************/
Jasper_lee 0:b16d94660a33 4785 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4786 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4787 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4788 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4789 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4790 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4791 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4792 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4793 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4794 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4795 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4796 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4797 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4798 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4799 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4800 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4801 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4802 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4803 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4804 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4805 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4806 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4807 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4808 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4809 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4810 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4811 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4812 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4813 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
Jasper_lee 0:b16d94660a33 4814 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
Jasper_lee 0:b16d94660a33 4815 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
Jasper_lee 0:b16d94660a33 4816 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
Jasper_lee 0:b16d94660a33 4817
Jasper_lee 0:b16d94660a33 4818 /******************* Bit definition for TSC_IOCCR register ******************/
Jasper_lee 0:b16d94660a33 4819 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4820 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4821 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4822 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4823 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4824 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4825 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4826 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4827 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4828 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4829 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4830 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4831 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4832 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4833 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4834 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4835 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4836 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4837 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4838 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4839 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4840 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4841 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4842 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4843 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4844 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4845 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4846 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4847 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
Jasper_lee 0:b16d94660a33 4848 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
Jasper_lee 0:b16d94660a33 4849 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
Jasper_lee 0:b16d94660a33 4850 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
Jasper_lee 0:b16d94660a33 4851
Jasper_lee 0:b16d94660a33 4852 /******************* Bit definition for TSC_IOGCSR register *****************/
Jasper_lee 0:b16d94660a33 4853 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
Jasper_lee 0:b16d94660a33 4854 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
Jasper_lee 0:b16d94660a33 4855 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
Jasper_lee 0:b16d94660a33 4856 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
Jasper_lee 0:b16d94660a33 4857 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
Jasper_lee 0:b16d94660a33 4858 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
Jasper_lee 0:b16d94660a33 4859 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
Jasper_lee 0:b16d94660a33 4860 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
Jasper_lee 0:b16d94660a33 4861 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
Jasper_lee 0:b16d94660a33 4862 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
Jasper_lee 0:b16d94660a33 4863 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
Jasper_lee 0:b16d94660a33 4864 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
Jasper_lee 0:b16d94660a33 4865 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
Jasper_lee 0:b16d94660a33 4866 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
Jasper_lee 0:b16d94660a33 4867 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
Jasper_lee 0:b16d94660a33 4868 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
Jasper_lee 0:b16d94660a33 4869
Jasper_lee 0:b16d94660a33 4870 /******************* Bit definition for TSC_IOGXCR register *****************/
Jasper_lee 0:b16d94660a33 4871 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
Jasper_lee 0:b16d94660a33 4872
Jasper_lee 0:b16d94660a33 4873 /******************************************************************************/
Jasper_lee 0:b16d94660a33 4874 /* */
Jasper_lee 0:b16d94660a33 4875 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Jasper_lee 0:b16d94660a33 4876 /* */
Jasper_lee 0:b16d94660a33 4877 /******************************************************************************/
Jasper_lee 0:b16d94660a33 4878 /****************** Bit definition for USART_CR1 register *******************/
Jasper_lee 0:b16d94660a33 4879 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Jasper_lee 0:b16d94660a33 4880 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
Jasper_lee 0:b16d94660a33 4881 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Jasper_lee 0:b16d94660a33 4882 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Jasper_lee 0:b16d94660a33 4883 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Jasper_lee 0:b16d94660a33 4884 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Jasper_lee 0:b16d94660a33 4885 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Jasper_lee 0:b16d94660a33 4886 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Jasper_lee 0:b16d94660a33 4887 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Jasper_lee 0:b16d94660a33 4888 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Jasper_lee 0:b16d94660a33 4889 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Jasper_lee 0:b16d94660a33 4890 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Jasper_lee 0:b16d94660a33 4891 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Jasper_lee 0:b16d94660a33 4892 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Jasper_lee 0:b16d94660a33 4893 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Jasper_lee 0:b16d94660a33 4894 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Jasper_lee 0:b16d94660a33 4895 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Jasper_lee 0:b16d94660a33 4896 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4897 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4898 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 4899 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 4900 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Jasper_lee 0:b16d94660a33 4901 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Jasper_lee 0:b16d94660a33 4902 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4903 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4904 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 4905 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Jasper_lee 0:b16d94660a33 4906 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Jasper_lee 0:b16d94660a33 4907 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Jasper_lee 0:b16d94660a33 4908 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Jasper_lee 0:b16d94660a33 4909 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
Jasper_lee 0:b16d94660a33 4910 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
Jasper_lee 0:b16d94660a33 4911
Jasper_lee 0:b16d94660a33 4912 /****************** Bit definition for USART_CR2 register *******************/
Jasper_lee 0:b16d94660a33 4913 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Jasper_lee 0:b16d94660a33 4914 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Jasper_lee 0:b16d94660a33 4915 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Jasper_lee 0:b16d94660a33 4916 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Jasper_lee 0:b16d94660a33 4917 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Jasper_lee 0:b16d94660a33 4918 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Jasper_lee 0:b16d94660a33 4919 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Jasper_lee 0:b16d94660a33 4920 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Jasper_lee 0:b16d94660a33 4921 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4922 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4923 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Jasper_lee 0:b16d94660a33 4924 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Jasper_lee 0:b16d94660a33 4925 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Jasper_lee 0:b16d94660a33 4926 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Jasper_lee 0:b16d94660a33 4927 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Jasper_lee 0:b16d94660a33 4928 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Jasper_lee 0:b16d94660a33 4929 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Jasper_lee 0:b16d94660a33 4930 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Jasper_lee 0:b16d94660a33 4931 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4932 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4933 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Jasper_lee 0:b16d94660a33 4934 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Jasper_lee 0:b16d94660a33 4935
Jasper_lee 0:b16d94660a33 4936 /****************** Bit definition for USART_CR3 register *******************/
Jasper_lee 0:b16d94660a33 4937 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Jasper_lee 0:b16d94660a33 4938 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Jasper_lee 0:b16d94660a33 4939 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Jasper_lee 0:b16d94660a33 4940 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Jasper_lee 0:b16d94660a33 4941 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Jasper_lee 0:b16d94660a33 4942 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Jasper_lee 0:b16d94660a33 4943 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Jasper_lee 0:b16d94660a33 4944 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Jasper_lee 0:b16d94660a33 4945 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Jasper_lee 0:b16d94660a33 4946 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Jasper_lee 0:b16d94660a33 4947 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Jasper_lee 0:b16d94660a33 4948 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Jasper_lee 0:b16d94660a33 4949 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Jasper_lee 0:b16d94660a33 4950 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Jasper_lee 0:b16d94660a33 4951 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Jasper_lee 0:b16d94660a33 4952 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Jasper_lee 0:b16d94660a33 4953 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Jasper_lee 0:b16d94660a33 4954 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4955 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4956 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Jasper_lee 0:b16d94660a33 4957 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Jasper_lee 0:b16d94660a33 4958 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Jasper_lee 0:b16d94660a33 4959 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Jasper_lee 0:b16d94660a33 4960 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
Jasper_lee 0:b16d94660a33 4961
Jasper_lee 0:b16d94660a33 4962 /****************** Bit definition for USART_BRR register *******************/
Jasper_lee 0:b16d94660a33 4963 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Jasper_lee 0:b16d94660a33 4964 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Jasper_lee 0:b16d94660a33 4965
Jasper_lee 0:b16d94660a33 4966 /****************** Bit definition for USART_GTPR register ******************/
Jasper_lee 0:b16d94660a33 4967 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Jasper_lee 0:b16d94660a33 4968 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Jasper_lee 0:b16d94660a33 4969
Jasper_lee 0:b16d94660a33 4970
Jasper_lee 0:b16d94660a33 4971 /******************* Bit definition for USART_RTOR register *****************/
Jasper_lee 0:b16d94660a33 4972 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Jasper_lee 0:b16d94660a33 4973 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Jasper_lee 0:b16d94660a33 4974
Jasper_lee 0:b16d94660a33 4975 /******************* Bit definition for USART_RQR register ******************/
Jasper_lee 0:b16d94660a33 4976 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Jasper_lee 0:b16d94660a33 4977 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Jasper_lee 0:b16d94660a33 4978 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Jasper_lee 0:b16d94660a33 4979 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Jasper_lee 0:b16d94660a33 4980 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
Jasper_lee 0:b16d94660a33 4981
Jasper_lee 0:b16d94660a33 4982 /******************* Bit definition for USART_ISR register ******************/
Jasper_lee 0:b16d94660a33 4983 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Jasper_lee 0:b16d94660a33 4984 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Jasper_lee 0:b16d94660a33 4985 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Jasper_lee 0:b16d94660a33 4986 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Jasper_lee 0:b16d94660a33 4987 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Jasper_lee 0:b16d94660a33 4988 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Jasper_lee 0:b16d94660a33 4989 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Jasper_lee 0:b16d94660a33 4990 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Jasper_lee 0:b16d94660a33 4991 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Jasper_lee 0:b16d94660a33 4992 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Jasper_lee 0:b16d94660a33 4993 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Jasper_lee 0:b16d94660a33 4994 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Jasper_lee 0:b16d94660a33 4995 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Jasper_lee 0:b16d94660a33 4996 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Jasper_lee 0:b16d94660a33 4997 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Jasper_lee 0:b16d94660a33 4998 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Jasper_lee 0:b16d94660a33 4999 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Jasper_lee 0:b16d94660a33 5000 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Jasper_lee 0:b16d94660a33 5001 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Jasper_lee 0:b16d94660a33 5002 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Jasper_lee 0:b16d94660a33 5003 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Jasper_lee 0:b16d94660a33 5004 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Jasper_lee 0:b16d94660a33 5005
Jasper_lee 0:b16d94660a33 5006 /******************* Bit definition for USART_ICR register ******************/
Jasper_lee 0:b16d94660a33 5007 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Jasper_lee 0:b16d94660a33 5008 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Jasper_lee 0:b16d94660a33 5009 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Jasper_lee 0:b16d94660a33 5010 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Jasper_lee 0:b16d94660a33 5011 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Jasper_lee 0:b16d94660a33 5012 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Jasper_lee 0:b16d94660a33 5013 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Jasper_lee 0:b16d94660a33 5014 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Jasper_lee 0:b16d94660a33 5015 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Jasper_lee 0:b16d94660a33 5016 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Jasper_lee 0:b16d94660a33 5017 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Jasper_lee 0:b16d94660a33 5018 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Jasper_lee 0:b16d94660a33 5019
Jasper_lee 0:b16d94660a33 5020 /******************* Bit definition for USART_RDR register ******************/
Jasper_lee 0:b16d94660a33 5021 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Jasper_lee 0:b16d94660a33 5022
Jasper_lee 0:b16d94660a33 5023 /******************* Bit definition for USART_TDR register ******************/
Jasper_lee 0:b16d94660a33 5024 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Jasper_lee 0:b16d94660a33 5025
Jasper_lee 0:b16d94660a33 5026 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5027 /* */
Jasper_lee 0:b16d94660a33 5028 /* USB Device General registers */
Jasper_lee 0:b16d94660a33 5029 /* */
Jasper_lee 0:b16d94660a33 5030 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5031 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
Jasper_lee 0:b16d94660a33 5032 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
Jasper_lee 0:b16d94660a33 5033 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
Jasper_lee 0:b16d94660a33 5034 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
Jasper_lee 0:b16d94660a33 5035 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
Jasper_lee 0:b16d94660a33 5036 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
Jasper_lee 0:b16d94660a33 5037 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
Jasper_lee 0:b16d94660a33 5038
Jasper_lee 0:b16d94660a33 5039 /**************************** ISTR interrupt events *************************/
Jasper_lee 0:b16d94660a33 5040 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
Jasper_lee 0:b16d94660a33 5041 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
Jasper_lee 0:b16d94660a33 5042 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
Jasper_lee 0:b16d94660a33 5043 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
Jasper_lee 0:b16d94660a33 5044 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
Jasper_lee 0:b16d94660a33 5045 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
Jasper_lee 0:b16d94660a33 5046 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
Jasper_lee 0:b16d94660a33 5047 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
Jasper_lee 0:b16d94660a33 5048 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
Jasper_lee 0:b16d94660a33 5049 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
Jasper_lee 0:b16d94660a33 5050 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
Jasper_lee 0:b16d94660a33 5051
Jasper_lee 0:b16d94660a33 5052 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Jasper_lee 0:b16d94660a33 5053 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Jasper_lee 0:b16d94660a33 5054 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Jasper_lee 0:b16d94660a33 5055 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Jasper_lee 0:b16d94660a33 5056 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Jasper_lee 0:b16d94660a33 5057 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Jasper_lee 0:b16d94660a33 5058 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Jasper_lee 0:b16d94660a33 5059 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Jasper_lee 0:b16d94660a33 5060 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
Jasper_lee 0:b16d94660a33 5061
Jasper_lee 0:b16d94660a33 5062 /************************* CNTR control register bits definitions ***********/
Jasper_lee 0:b16d94660a33 5063 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
Jasper_lee 0:b16d94660a33 5064 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
Jasper_lee 0:b16d94660a33 5065 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
Jasper_lee 0:b16d94660a33 5066 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
Jasper_lee 0:b16d94660a33 5067 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
Jasper_lee 0:b16d94660a33 5068 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
Jasper_lee 0:b16d94660a33 5069 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
Jasper_lee 0:b16d94660a33 5070 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
Jasper_lee 0:b16d94660a33 5071 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
Jasper_lee 0:b16d94660a33 5072 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
Jasper_lee 0:b16d94660a33 5073 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
Jasper_lee 0:b16d94660a33 5074 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
Jasper_lee 0:b16d94660a33 5075 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
Jasper_lee 0:b16d94660a33 5076 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
Jasper_lee 0:b16d94660a33 5077 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
Jasper_lee 0:b16d94660a33 5078
Jasper_lee 0:b16d94660a33 5079 /************************* BCDR control register bits definitions ***********/
Jasper_lee 0:b16d94660a33 5080 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
Jasper_lee 0:b16d94660a33 5081 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
Jasper_lee 0:b16d94660a33 5082 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
Jasper_lee 0:b16d94660a33 5083 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
Jasper_lee 0:b16d94660a33 5084 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
Jasper_lee 0:b16d94660a33 5085 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
Jasper_lee 0:b16d94660a33 5086 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
Jasper_lee 0:b16d94660a33 5087 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
Jasper_lee 0:b16d94660a33 5088 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
Jasper_lee 0:b16d94660a33 5089
Jasper_lee 0:b16d94660a33 5090 /*************************** LPM register bits definitions ******************/
Jasper_lee 0:b16d94660a33 5091 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
Jasper_lee 0:b16d94660a33 5092 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
Jasper_lee 0:b16d94660a33 5093 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
Jasper_lee 0:b16d94660a33 5094 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
Jasper_lee 0:b16d94660a33 5095
Jasper_lee 0:b16d94660a33 5096 /******************** FNR Frame Number Register bit definitions ************/
Jasper_lee 0:b16d94660a33 5097 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
Jasper_lee 0:b16d94660a33 5098 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
Jasper_lee 0:b16d94660a33 5099 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
Jasper_lee 0:b16d94660a33 5100 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
Jasper_lee 0:b16d94660a33 5101 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
Jasper_lee 0:b16d94660a33 5102
Jasper_lee 0:b16d94660a33 5103 /******************** DADDR Device ADDRess bit definitions ****************/
Jasper_lee 0:b16d94660a33 5104 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
Jasper_lee 0:b16d94660a33 5105 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
Jasper_lee 0:b16d94660a33 5106
Jasper_lee 0:b16d94660a33 5107 /****************************** Endpoint register *************************/
Jasper_lee 0:b16d94660a33 5108 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Jasper_lee 0:b16d94660a33 5109 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
Jasper_lee 0:b16d94660a33 5110 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
Jasper_lee 0:b16d94660a33 5111 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
Jasper_lee 0:b16d94660a33 5112 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
Jasper_lee 0:b16d94660a33 5113 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
Jasper_lee 0:b16d94660a33 5114 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
Jasper_lee 0:b16d94660a33 5115 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
Jasper_lee 0:b16d94660a33 5116 /* bit positions */
Jasper_lee 0:b16d94660a33 5117 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
Jasper_lee 0:b16d94660a33 5118 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
Jasper_lee 0:b16d94660a33 5119 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
Jasper_lee 0:b16d94660a33 5120 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
Jasper_lee 0:b16d94660a33 5121 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
Jasper_lee 0:b16d94660a33 5122 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
Jasper_lee 0:b16d94660a33 5123 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
Jasper_lee 0:b16d94660a33 5124 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
Jasper_lee 0:b16d94660a33 5125 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
Jasper_lee 0:b16d94660a33 5126 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
Jasper_lee 0:b16d94660a33 5127
Jasper_lee 0:b16d94660a33 5128 /* EndPoint REGister MASK (no toggle fields) */
Jasper_lee 0:b16d94660a33 5129 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Jasper_lee 0:b16d94660a33 5130 /*!< EP_TYPE[1:0] EndPoint TYPE */
Jasper_lee 0:b16d94660a33 5131 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
Jasper_lee 0:b16d94660a33 5132 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
Jasper_lee 0:b16d94660a33 5133 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
Jasper_lee 0:b16d94660a33 5134 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
Jasper_lee 0:b16d94660a33 5135 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
Jasper_lee 0:b16d94660a33 5136 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
Jasper_lee 0:b16d94660a33 5137
Jasper_lee 0:b16d94660a33 5138 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Jasper_lee 0:b16d94660a33 5139 /*!< STAT_TX[1:0] STATus for TX transfer */
Jasper_lee 0:b16d94660a33 5140 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
Jasper_lee 0:b16d94660a33 5141 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
Jasper_lee 0:b16d94660a33 5142 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
Jasper_lee 0:b16d94660a33 5143 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
Jasper_lee 0:b16d94660a33 5144 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
Jasper_lee 0:b16d94660a33 5145 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
Jasper_lee 0:b16d94660a33 5146 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Jasper_lee 0:b16d94660a33 5147 /*!< STAT_RX[1:0] STATus for RX transfer */
Jasper_lee 0:b16d94660a33 5148 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
Jasper_lee 0:b16d94660a33 5149 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
Jasper_lee 0:b16d94660a33 5150 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
Jasper_lee 0:b16d94660a33 5151 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
Jasper_lee 0:b16d94660a33 5152 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
Jasper_lee 0:b16d94660a33 5153 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
Jasper_lee 0:b16d94660a33 5154 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Jasper_lee 0:b16d94660a33 5155
Jasper_lee 0:b16d94660a33 5156 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5157 /* */
Jasper_lee 0:b16d94660a33 5158 /* Window WATCHDOG (WWDG) */
Jasper_lee 0:b16d94660a33 5159 /* */
Jasper_lee 0:b16d94660a33 5160 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5161 /******************* Bit definition for WWDG_CR register ********************/
Jasper_lee 0:b16d94660a33 5162 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Jasper_lee 0:b16d94660a33 5163 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 5164 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 5165 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 5166 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 5167 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 5168 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Jasper_lee 0:b16d94660a33 5169 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Jasper_lee 0:b16d94660a33 5170
Jasper_lee 0:b16d94660a33 5171 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Jasper_lee 0:b16d94660a33 5172
Jasper_lee 0:b16d94660a33 5173 /******************* Bit definition for WWDG_CFR register *******************/
Jasper_lee 0:b16d94660a33 5174 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Jasper_lee 0:b16d94660a33 5175 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 5176 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 5177 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Jasper_lee 0:b16d94660a33 5178 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Jasper_lee 0:b16d94660a33 5179 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Jasper_lee 0:b16d94660a33 5180 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Jasper_lee 0:b16d94660a33 5181 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Jasper_lee 0:b16d94660a33 5182
Jasper_lee 0:b16d94660a33 5183 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Jasper_lee 0:b16d94660a33 5184 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Jasper_lee 0:b16d94660a33 5185 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Jasper_lee 0:b16d94660a33 5186
Jasper_lee 0:b16d94660a33 5187 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Jasper_lee 0:b16d94660a33 5188
Jasper_lee 0:b16d94660a33 5189 /******************* Bit definition for WWDG_SR register ********************/
Jasper_lee 0:b16d94660a33 5190 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Jasper_lee 0:b16d94660a33 5191
Jasper_lee 0:b16d94660a33 5192 /**
Jasper_lee 0:b16d94660a33 5193 * @}
Jasper_lee 0:b16d94660a33 5194 */
Jasper_lee 0:b16d94660a33 5195
Jasper_lee 0:b16d94660a33 5196 /**
Jasper_lee 0:b16d94660a33 5197 * @}
Jasper_lee 0:b16d94660a33 5198 */
Jasper_lee 0:b16d94660a33 5199
Jasper_lee 0:b16d94660a33 5200
Jasper_lee 0:b16d94660a33 5201 /** @addtogroup Exported_macro
Jasper_lee 0:b16d94660a33 5202 * @{
Jasper_lee 0:b16d94660a33 5203 */
Jasper_lee 0:b16d94660a33 5204
Jasper_lee 0:b16d94660a33 5205 /****************************** ADC Instances *********************************/
Jasper_lee 0:b16d94660a33 5206 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Jasper_lee 0:b16d94660a33 5207
Jasper_lee 0:b16d94660a33 5208 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Jasper_lee 0:b16d94660a33 5209
Jasper_lee 0:b16d94660a33 5210 /******************************* CAN Instances ********************************/
Jasper_lee 0:b16d94660a33 5211 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
Jasper_lee 0:b16d94660a33 5212
Jasper_lee 0:b16d94660a33 5213 /****************************** COMP Instances *********************************/
Jasper_lee 0:b16d94660a33 5214 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Jasper_lee 0:b16d94660a33 5215 ((INSTANCE) == COMP2))
Jasper_lee 0:b16d94660a33 5216
Jasper_lee 0:b16d94660a33 5217 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
Jasper_lee 0:b16d94660a33 5218
Jasper_lee 0:b16d94660a33 5219 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
Jasper_lee 0:b16d94660a33 5220
Jasper_lee 0:b16d94660a33 5221 /****************************** CEC Instances *********************************/
Jasper_lee 0:b16d94660a33 5222 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
Jasper_lee 0:b16d94660a33 5223
Jasper_lee 0:b16d94660a33 5224 /****************************** CRC Instances *********************************/
Jasper_lee 0:b16d94660a33 5225 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Jasper_lee 0:b16d94660a33 5226
Jasper_lee 0:b16d94660a33 5227 /******************************* DAC Instances ********************************/
Jasper_lee 0:b16d94660a33 5228 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Jasper_lee 0:b16d94660a33 5229
Jasper_lee 0:b16d94660a33 5230 /******************************* DMA Instances ******************************/
Jasper_lee 0:b16d94660a33 5231 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Jasper_lee 0:b16d94660a33 5232 ((INSTANCE) == DMA1_Channel2) || \
Jasper_lee 0:b16d94660a33 5233 ((INSTANCE) == DMA1_Channel3) || \
Jasper_lee 0:b16d94660a33 5234 ((INSTANCE) == DMA1_Channel4) || \
Jasper_lee 0:b16d94660a33 5235 ((INSTANCE) == DMA1_Channel5) || \
Jasper_lee 0:b16d94660a33 5236 ((INSTANCE) == DMA1_Channel6) || \
Jasper_lee 0:b16d94660a33 5237 ((INSTANCE) == DMA1_Channel7))
Jasper_lee 0:b16d94660a33 5238
Jasper_lee 0:b16d94660a33 5239 /****************************** GPIO Instances ********************************/
Jasper_lee 0:b16d94660a33 5240 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Jasper_lee 0:b16d94660a33 5241 ((INSTANCE) == GPIOB) || \
Jasper_lee 0:b16d94660a33 5242 ((INSTANCE) == GPIOC) || \
Jasper_lee 0:b16d94660a33 5243 ((INSTANCE) == GPIOD) || \
Jasper_lee 0:b16d94660a33 5244 ((INSTANCE) == GPIOE) || \
Jasper_lee 0:b16d94660a33 5245 ((INSTANCE) == GPIOF))
Jasper_lee 0:b16d94660a33 5246
Jasper_lee 0:b16d94660a33 5247 /****************************** GPIO Lock Instances ****************************/
Jasper_lee 0:b16d94660a33 5248 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Jasper_lee 0:b16d94660a33 5249 ((INSTANCE) == GPIOB))
Jasper_lee 0:b16d94660a33 5250
Jasper_lee 0:b16d94660a33 5251 /****************************** I2C Instances *********************************/
Jasper_lee 0:b16d94660a33 5252 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Jasper_lee 0:b16d94660a33 5253 ((INSTANCE) == I2C2))
Jasper_lee 0:b16d94660a33 5254
Jasper_lee 0:b16d94660a33 5255 /****************************** I2S Instances *********************************/
Jasper_lee 0:b16d94660a33 5256 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Jasper_lee 0:b16d94660a33 5257 ((INSTANCE) == SPI2))
Jasper_lee 0:b16d94660a33 5258
Jasper_lee 0:b16d94660a33 5259 /****************************** IWDG Instances ********************************/
Jasper_lee 0:b16d94660a33 5260 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Jasper_lee 0:b16d94660a33 5261
Jasper_lee 0:b16d94660a33 5262 /****************************** RTC Instances *********************************/
Jasper_lee 0:b16d94660a33 5263 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Jasper_lee 0:b16d94660a33 5264
Jasper_lee 0:b16d94660a33 5265 /****************************** SMBUS Instances *********************************/
Jasper_lee 0:b16d94660a33 5266 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Jasper_lee 0:b16d94660a33 5267
Jasper_lee 0:b16d94660a33 5268 /****************************** SPI Instances *********************************/
Jasper_lee 0:b16d94660a33 5269 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Jasper_lee 0:b16d94660a33 5270 ((INSTANCE) == SPI2))
Jasper_lee 0:b16d94660a33 5271
Jasper_lee 0:b16d94660a33 5272 /****************************** TIM Instances *********************************/
Jasper_lee 0:b16d94660a33 5273 #define IS_TIM_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5274 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5275 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5276 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5277 ((INSTANCE) == TIM6) || \
Jasper_lee 0:b16d94660a33 5278 ((INSTANCE) == TIM7) || \
Jasper_lee 0:b16d94660a33 5279 ((INSTANCE) == TIM14) || \
Jasper_lee 0:b16d94660a33 5280 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5281 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5282 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5283
Jasper_lee 0:b16d94660a33 5284 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5285 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5286 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5287 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5288 ((INSTANCE) == TIM14) || \
Jasper_lee 0:b16d94660a33 5289 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5290 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5291 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5292
Jasper_lee 0:b16d94660a33 5293 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5294 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5295 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5296 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5297 ((INSTANCE) == TIM15))
Jasper_lee 0:b16d94660a33 5298
Jasper_lee 0:b16d94660a33 5299 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5300 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5301 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5302 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5303
Jasper_lee 0:b16d94660a33 5304 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5305 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5306 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5307 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5308
Jasper_lee 0:b16d94660a33 5309 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5310 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5311 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5312 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5313
Jasper_lee 0:b16d94660a33 5314 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5315 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5316 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5317 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5318
Jasper_lee 0:b16d94660a33 5319 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5320 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5321 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5322 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5323 ((INSTANCE) == TIM15))
Jasper_lee 0:b16d94660a33 5324
Jasper_lee 0:b16d94660a33 5325 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5326 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5327 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5328 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5329 ((INSTANCE) == TIM15))
Jasper_lee 0:b16d94660a33 5330
Jasper_lee 0:b16d94660a33 5331 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5332 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5333 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5334 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5335
Jasper_lee 0:b16d94660a33 5336 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5337 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5338 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5339 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5340
Jasper_lee 0:b16d94660a33 5341 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5342 (((INSTANCE) == TIM1))
Jasper_lee 0:b16d94660a33 5343
Jasper_lee 0:b16d94660a33 5344 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5345 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5346 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5347 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5348
Jasper_lee 0:b16d94660a33 5349 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5350 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5351 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5352 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5353 ((INSTANCE) == TIM6) || \
Jasper_lee 0:b16d94660a33 5354 ((INSTANCE) == TIM7) || \
Jasper_lee 0:b16d94660a33 5355 ((INSTANCE) == TIM15))
Jasper_lee 0:b16d94660a33 5356
Jasper_lee 0:b16d94660a33 5357 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5358 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5359 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5360 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5361 ((INSTANCE) == TIM15))
Jasper_lee 0:b16d94660a33 5362
Jasper_lee 0:b16d94660a33 5363 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5364 ((INSTANCE) == TIM2)
Jasper_lee 0:b16d94660a33 5365
Jasper_lee 0:b16d94660a33 5366 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5367 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5368 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5369 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5370 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5371 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5372 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5373
Jasper_lee 0:b16d94660a33 5374 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5375 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5376 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5377 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5378 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5379
Jasper_lee 0:b16d94660a33 5380 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Jasper_lee 0:b16d94660a33 5381 ((((INSTANCE) == TIM1) && \
Jasper_lee 0:b16d94660a33 5382 (((CHANNEL) == TIM_CHANNEL_1) || \
Jasper_lee 0:b16d94660a33 5383 ((CHANNEL) == TIM_CHANNEL_2) || \
Jasper_lee 0:b16d94660a33 5384 ((CHANNEL) == TIM_CHANNEL_3) || \
Jasper_lee 0:b16d94660a33 5385 ((CHANNEL) == TIM_CHANNEL_4))) \
Jasper_lee 0:b16d94660a33 5386 || \
Jasper_lee 0:b16d94660a33 5387 (((INSTANCE) == TIM2) && \
Jasper_lee 0:b16d94660a33 5388 (((CHANNEL) == TIM_CHANNEL_1) || \
Jasper_lee 0:b16d94660a33 5389 ((CHANNEL) == TIM_CHANNEL_2) || \
Jasper_lee 0:b16d94660a33 5390 ((CHANNEL) == TIM_CHANNEL_3) || \
Jasper_lee 0:b16d94660a33 5391 ((CHANNEL) == TIM_CHANNEL_4))) \
Jasper_lee 0:b16d94660a33 5392 || \
Jasper_lee 0:b16d94660a33 5393 (((INSTANCE) == TIM3) && \
Jasper_lee 0:b16d94660a33 5394 (((CHANNEL) == TIM_CHANNEL_1) || \
Jasper_lee 0:b16d94660a33 5395 ((CHANNEL) == TIM_CHANNEL_2) || \
Jasper_lee 0:b16d94660a33 5396 ((CHANNEL) == TIM_CHANNEL_3) || \
Jasper_lee 0:b16d94660a33 5397 ((CHANNEL) == TIM_CHANNEL_4))) \
Jasper_lee 0:b16d94660a33 5398 || \
Jasper_lee 0:b16d94660a33 5399 (((INSTANCE) == TIM14) && \
Jasper_lee 0:b16d94660a33 5400 (((CHANNEL) == TIM_CHANNEL_1))) \
Jasper_lee 0:b16d94660a33 5401 || \
Jasper_lee 0:b16d94660a33 5402 (((INSTANCE) == TIM15) && \
Jasper_lee 0:b16d94660a33 5403 (((CHANNEL) == TIM_CHANNEL_1) || \
Jasper_lee 0:b16d94660a33 5404 ((CHANNEL) == TIM_CHANNEL_2))) \
Jasper_lee 0:b16d94660a33 5405 || \
Jasper_lee 0:b16d94660a33 5406 (((INSTANCE) == TIM16) && \
Jasper_lee 0:b16d94660a33 5407 (((CHANNEL) == TIM_CHANNEL_1))) \
Jasper_lee 0:b16d94660a33 5408 || \
Jasper_lee 0:b16d94660a33 5409 (((INSTANCE) == TIM17) && \
Jasper_lee 0:b16d94660a33 5410 (((CHANNEL) == TIM_CHANNEL_1))))
Jasper_lee 0:b16d94660a33 5411
Jasper_lee 0:b16d94660a33 5412 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Jasper_lee 0:b16d94660a33 5413 ((((INSTANCE) == TIM1) && \
Jasper_lee 0:b16d94660a33 5414 (((CHANNEL) == TIM_CHANNEL_1) || \
Jasper_lee 0:b16d94660a33 5415 ((CHANNEL) == TIM_CHANNEL_2) || \
Jasper_lee 0:b16d94660a33 5416 ((CHANNEL) == TIM_CHANNEL_3))) \
Jasper_lee 0:b16d94660a33 5417 || \
Jasper_lee 0:b16d94660a33 5418 (((INSTANCE) == TIM15) && \
Jasper_lee 0:b16d94660a33 5419 ((CHANNEL) == TIM_CHANNEL_1)) \
Jasper_lee 0:b16d94660a33 5420 || \
Jasper_lee 0:b16d94660a33 5421 (((INSTANCE) == TIM16) && \
Jasper_lee 0:b16d94660a33 5422 ((CHANNEL) == TIM_CHANNEL_1)) \
Jasper_lee 0:b16d94660a33 5423 || \
Jasper_lee 0:b16d94660a33 5424 (((INSTANCE) == TIM17) && \
Jasper_lee 0:b16d94660a33 5425 ((CHANNEL) == TIM_CHANNEL_1)))
Jasper_lee 0:b16d94660a33 5426
Jasper_lee 0:b16d94660a33 5427 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5428 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5429 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5430 ((INSTANCE) == TIM3))
Jasper_lee 0:b16d94660a33 5431
Jasper_lee 0:b16d94660a33 5432 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5433 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5434 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5435 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5436 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5437
Jasper_lee 0:b16d94660a33 5438 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5439 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5440 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5441 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5442 ((INSTANCE) == TIM14) || \
Jasper_lee 0:b16d94660a33 5443 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5444 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5445 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5446
Jasper_lee 0:b16d94660a33 5447 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5448 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5449 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5450 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5451 ((INSTANCE) == TIM6) || \
Jasper_lee 0:b16d94660a33 5452 ((INSTANCE) == TIM7) || \
Jasper_lee 0:b16d94660a33 5453 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5454 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5455 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5456
Jasper_lee 0:b16d94660a33 5457 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5458 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5459 ((INSTANCE) == TIM2) || \
Jasper_lee 0:b16d94660a33 5460 ((INSTANCE) == TIM3) || \
Jasper_lee 0:b16d94660a33 5461 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5462 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5463 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5464
Jasper_lee 0:b16d94660a33 5465 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5466 (((INSTANCE) == TIM1) || \
Jasper_lee 0:b16d94660a33 5467 ((INSTANCE) == TIM15) || \
Jasper_lee 0:b16d94660a33 5468 ((INSTANCE) == TIM16) || \
Jasper_lee 0:b16d94660a33 5469 ((INSTANCE) == TIM17))
Jasper_lee 0:b16d94660a33 5470
Jasper_lee 0:b16d94660a33 5471 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Jasper_lee 0:b16d94660a33 5472 ((INSTANCE) == TIM14)
Jasper_lee 0:b16d94660a33 5473
Jasper_lee 0:b16d94660a33 5474 /****************************** TSC Instances *********************************/
Jasper_lee 0:b16d94660a33 5475 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
Jasper_lee 0:b16d94660a33 5476
Jasper_lee 0:b16d94660a33 5477 /*********************** UART Instances : IRDA mode ***************************/
Jasper_lee 0:b16d94660a33 5478 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5479 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5480
Jasper_lee 0:b16d94660a33 5481 /********************* UART Instances : Smard card mode ***********************/
Jasper_lee 0:b16d94660a33 5482 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5483 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5484
Jasper_lee 0:b16d94660a33 5485 /******************** USART Instances : Synchronous mode **********************/
Jasper_lee 0:b16d94660a33 5486 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5487 ((INSTANCE) == USART2) || \
Jasper_lee 0:b16d94660a33 5488 ((INSTANCE) == USART3) || \
Jasper_lee 0:b16d94660a33 5489 ((INSTANCE) == USART4))
Jasper_lee 0:b16d94660a33 5490
Jasper_lee 0:b16d94660a33 5491 /******************** USART Instances : auto Baud rate detection **************/
Jasper_lee 0:b16d94660a33 5492 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5493 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5494
Jasper_lee 0:b16d94660a33 5495 /******************** UART Instances : Asynchronous mode **********************/
Jasper_lee 0:b16d94660a33 5496 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5497 ((INSTANCE) == USART2) || \
Jasper_lee 0:b16d94660a33 5498 ((INSTANCE) == USART3) || \
Jasper_lee 0:b16d94660a33 5499 ((INSTANCE) == USART4))
Jasper_lee 0:b16d94660a33 5500
Jasper_lee 0:b16d94660a33 5501 /******************** UART Instances : Half-Duplex mode **********************/
Jasper_lee 0:b16d94660a33 5502 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5503 ((INSTANCE) == USART2) || \
Jasper_lee 0:b16d94660a33 5504 ((INSTANCE) == USART3) || \
Jasper_lee 0:b16d94660a33 5505 ((INSTANCE) == USART4))
Jasper_lee 0:b16d94660a33 5506
Jasper_lee 0:b16d94660a33 5507 /****************** UART Instances : Hardware Flow control ********************/
Jasper_lee 0:b16d94660a33 5508 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5509 ((INSTANCE) == USART2) || \
Jasper_lee 0:b16d94660a33 5510 ((INSTANCE) == USART3) || \
Jasper_lee 0:b16d94660a33 5511 ((INSTANCE) == USART4))
Jasper_lee 0:b16d94660a33 5512
Jasper_lee 0:b16d94660a33 5513 /****************** UART Instances : LIN mode ********************/
Jasper_lee 0:b16d94660a33 5514 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5515 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5516
Jasper_lee 0:b16d94660a33 5517 /****************** UART Instances : wakeup from stop mode ********************/
Jasper_lee 0:b16d94660a33 5518 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5519 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5520
Jasper_lee 0:b16d94660a33 5521 /****************** UART Instances : Auto Baud Rate detection ********************/
Jasper_lee 0:b16d94660a33 5522 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5523 ((INSTANCE) == USART2))
Jasper_lee 0:b16d94660a33 5524
Jasper_lee 0:b16d94660a33 5525 /****************** UART Instances : Driver enable detection ********************/
Jasper_lee 0:b16d94660a33 5526 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Jasper_lee 0:b16d94660a33 5527 ((INSTANCE) == USART2) || \
Jasper_lee 0:b16d94660a33 5528 ((INSTANCE) == USART3) || \
Jasper_lee 0:b16d94660a33 5529 ((INSTANCE) == USART4))
Jasper_lee 0:b16d94660a33 5530
Jasper_lee 0:b16d94660a33 5531 /****************************** USB Instances ********************************/
Jasper_lee 0:b16d94660a33 5532 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Jasper_lee 0:b16d94660a33 5533
Jasper_lee 0:b16d94660a33 5534 /****************************** WWDG Instances ********************************/
Jasper_lee 0:b16d94660a33 5535 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Jasper_lee 0:b16d94660a33 5536
Jasper_lee 0:b16d94660a33 5537 /**
Jasper_lee 0:b16d94660a33 5538 * @}
Jasper_lee 0:b16d94660a33 5539 */
Jasper_lee 0:b16d94660a33 5540
Jasper_lee 0:b16d94660a33 5541
Jasper_lee 0:b16d94660a33 5542 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5543 /* For a painless codes migration between the STM32F0xx device product */
Jasper_lee 0:b16d94660a33 5544 /* lines, the aliases defined below are put in place to overcome the */
Jasper_lee 0:b16d94660a33 5545 /* differences in the interrupt handlers and IRQn definitions. */
Jasper_lee 0:b16d94660a33 5546 /* No need to update developed interrupt code when moving across */
Jasper_lee 0:b16d94660a33 5547 /* product lines within the same STM32F0 Family */
Jasper_lee 0:b16d94660a33 5548 /******************************************************************************/
Jasper_lee 0:b16d94660a33 5549
Jasper_lee 0:b16d94660a33 5550 /* Aliases for __IRQn */
Jasper_lee 0:b16d94660a33 5551 #define PVD_IRQn PVD_VDDIO2_IRQn
Jasper_lee 0:b16d94660a33 5552 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
Jasper_lee 0:b16d94660a33 5553 #define RCC_IRQn RCC_CRS_IRQn
Jasper_lee 0:b16d94660a33 5554 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
Jasper_lee 0:b16d94660a33 5555 #define ADC1_IRQn ADC1_COMP_IRQn
Jasper_lee 0:b16d94660a33 5556 #define TIM6_IRQn TIM6_DAC_IRQn
Jasper_lee 0:b16d94660a33 5557
Jasper_lee 0:b16d94660a33 5558 /* Aliases for __IRQHandler */
Jasper_lee 0:b16d94660a33 5559 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
Jasper_lee 0:b16d94660a33 5560 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
Jasper_lee 0:b16d94660a33 5561 #define RCC_IRQHandler RCC_CRS_IRQHandler
Jasper_lee 0:b16d94660a33 5562 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
Jasper_lee 0:b16d94660a33 5563 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
Jasper_lee 0:b16d94660a33 5564 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
Jasper_lee 0:b16d94660a33 5565
Jasper_lee 0:b16d94660a33 5566 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 5567 }
Jasper_lee 0:b16d94660a33 5568 #endif /* __cplusplus */
Jasper_lee 0:b16d94660a33 5569
Jasper_lee 0:b16d94660a33 5570 #endif /* __STM32F072xB_H */
Jasper_lee 0:b16d94660a33 5571
Jasper_lee 0:b16d94660a33 5572 /**
Jasper_lee 0:b16d94660a33 5573 * @}
Jasper_lee 0:b16d94660a33 5574 */
Jasper_lee 0:b16d94660a33 5575
Jasper_lee 0:b16d94660a33 5576 /**
Jasper_lee 0:b16d94660a33 5577 * @}
Jasper_lee 0:b16d94660a33 5578 */
Jasper_lee 0:b16d94660a33 5579
Jasper_lee 0:b16d94660a33 5580 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/