mbed_helloworld - change some io settings for TWR-K22F-120M

Users » Jasper_lee » Code » mbed_helloworld

change some io settings for TWR-K22F-120M

TARGET_NUCLEO_F030R8/stm32f030x8.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:: Jasper_lee
Date:: Tue Dec 23 03:35:08 2014 +0000
Revision:: 0:b16d94660a33

change some io setting used in TWR-K22F120M

Who changed what in which revision?

User	Revision	Line number	New contents of line
Jasper_lee	0:b16d94660a33	1	/**
Jasper_lee	0:b16d94660a33	2	******************************************************************************
Jasper_lee	0:b16d94660a33	3	* @file stm32f030x8.h
Jasper_lee	0:b16d94660a33	4	* @author MCD Application Team
Jasper_lee	0:b16d94660a33	5	* @version V2.1.0
Jasper_lee	0:b16d94660a33	6	* @date 03-Oct-2014
Jasper_lee	0:b16d94660a33	7	* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
Jasper_lee	0:b16d94660a33	8	*
Jasper_lee	0:b16d94660a33	9	* This file contains:
Jasper_lee	0:b16d94660a33	10	* - Data structures and the address mapping for all peripherals
Jasper_lee	0:b16d94660a33	11	* - Peripheral's registers declarations and bits definition
Jasper_lee	0:b16d94660a33	12	* - Macros to access peripherals registers hardware
Jasper_lee	0:b16d94660a33	13	*
Jasper_lee	0:b16d94660a33	14	******************************************************************************
Jasper_lee	0:b16d94660a33	15	* @attention
Jasper_lee	0:b16d94660a33	16	*
Jasper_lee	0:b16d94660a33	17	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Jasper_lee	0:b16d94660a33	18	*
Jasper_lee	0:b16d94660a33	19	* Redistribution and use in source and binary forms, with or without modification,
Jasper_lee	0:b16d94660a33	20	* are permitted provided that the following conditions are met:
Jasper_lee	0:b16d94660a33	21	* 1. Redistributions of source code must retain the above copyright notice,
Jasper_lee	0:b16d94660a33	22	* this list of conditions and the following disclaimer.
Jasper_lee	0:b16d94660a33	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
Jasper_lee	0:b16d94660a33	24	* this list of conditions and the following disclaimer in the documentation
Jasper_lee	0:b16d94660a33	25	* and/or other materials provided with the distribution.
Jasper_lee	0:b16d94660a33	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Jasper_lee	0:b16d94660a33	27	* may be used to endorse or promote products derived from this software
Jasper_lee	0:b16d94660a33	28	* without specific prior written permission.
Jasper_lee	0:b16d94660a33	29	*
Jasper_lee	0:b16d94660a33	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Jasper_lee	0:b16d94660a33	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Jasper_lee	0:b16d94660a33	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jasper_lee	0:b16d94660a33	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Jasper_lee	0:b16d94660a33	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Jasper_lee	0:b16d94660a33	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Jasper_lee	0:b16d94660a33	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Jasper_lee	0:b16d94660a33	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Jasper_lee	0:b16d94660a33	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Jasper_lee	0:b16d94660a33	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jasper_lee	0:b16d94660a33	40	*
Jasper_lee	0:b16d94660a33	41	******************************************************************************
Jasper_lee	0:b16d94660a33	42	*/
Jasper_lee	0:b16d94660a33	43
Jasper_lee	0:b16d94660a33	44	/** @addtogroup CMSIS_Device
Jasper_lee	0:b16d94660a33	45	* @{
Jasper_lee	0:b16d94660a33	46	*/
Jasper_lee	0:b16d94660a33	47
Jasper_lee	0:b16d94660a33	48	/** @addtogroup stm32f030x8
Jasper_lee	0:b16d94660a33	49	* @{
Jasper_lee	0:b16d94660a33	50	*/
Jasper_lee	0:b16d94660a33	51
Jasper_lee	0:b16d94660a33	52	#ifndef __STM32F030x8_H
Jasper_lee	0:b16d94660a33	53	#define __STM32F030x8_H
Jasper_lee	0:b16d94660a33	54
Jasper_lee	0:b16d94660a33	55	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	56	extern "C" {
Jasper_lee	0:b16d94660a33	57	#endif /* __cplusplus */
Jasper_lee	0:b16d94660a33	58
Jasper_lee	0:b16d94660a33	59	/** @addtogroup Configuration_section_for_CMSIS
Jasper_lee	0:b16d94660a33	60	* @{
Jasper_lee	0:b16d94660a33	61	*/
Jasper_lee	0:b16d94660a33	62
Jasper_lee	0:b16d94660a33	63	/**
Jasper_lee	0:b16d94660a33	64	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Jasper_lee	0:b16d94660a33	65	*/
Jasper_lee	0:b16d94660a33	66	#define __CM0_REV 0 /!< Core Revision r0p0 /
Jasper_lee	0:b16d94660a33	67	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
Jasper_lee	0:b16d94660a33	68	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
Jasper_lee	0:b16d94660a33	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Jasper_lee	0:b16d94660a33	70
Jasper_lee	0:b16d94660a33	71	/**
Jasper_lee	0:b16d94660a33	72	* @}
Jasper_lee	0:b16d94660a33	73	*/
Jasper_lee	0:b16d94660a33	74
Jasper_lee	0:b16d94660a33	75	/** @addtogroup Peripheral_interrupt_number_definition
Jasper_lee	0:b16d94660a33	76	* @{
Jasper_lee	0:b16d94660a33	77	*/
Jasper_lee	0:b16d94660a33	78
Jasper_lee	0:b16d94660a33	79	/**
Jasper_lee	0:b16d94660a33	80	* @brief STM32F030x8 device Interrupt Number Definition
Jasper_lee	0:b16d94660a33	81	*/
Jasper_lee	0:b16d94660a33	82	typedef enum
Jasper_lee	0:b16d94660a33	83	{
Jasper_lee	0:b16d94660a33	84	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
Jasper_lee	0:b16d94660a33	85	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Jasper_lee	0:b16d94660a33	86	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
Jasper_lee	0:b16d94660a33	87	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
Jasper_lee	0:b16d94660a33	88	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
Jasper_lee	0:b16d94660a33	89	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
Jasper_lee	0:b16d94660a33	90
Jasper_lee	0:b16d94660a33	91	/**** STM32F030x8 specific Interrupt Numbers ************************************************************/
Jasper_lee	0:b16d94660a33	92	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Jasper_lee	0:b16d94660a33	93	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
Jasper_lee	0:b16d94660a33	94	FLASH_IRQn = 3, /!< FLASH global Interrupt /
Jasper_lee	0:b16d94660a33	95	RCC_IRQn = 4, /!< RCC global Interrupt /
Jasper_lee	0:b16d94660a33	96	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
Jasper_lee	0:b16d94660a33	97	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
Jasper_lee	0:b16d94660a33	98	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
Jasper_lee	0:b16d94660a33	99	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
Jasper_lee	0:b16d94660a33	100	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
Jasper_lee	0:b16d94660a33	101	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
Jasper_lee	0:b16d94660a33	102	ADC1_IRQn = 12, /!< ADC1 global Interrupt /
Jasper_lee	0:b16d94660a33	103	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
Jasper_lee	0:b16d94660a33	104	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
Jasper_lee	0:b16d94660a33	105	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
Jasper_lee	0:b16d94660a33	106	TIM6_IRQn = 17, /!< TIM6 global Interrupt /
Jasper_lee	0:b16d94660a33	107	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
Jasper_lee	0:b16d94660a33	108	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
Jasper_lee	0:b16d94660a33	109	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
Jasper_lee	0:b16d94660a33	110	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
Jasper_lee	0:b16d94660a33	111	I2C1_IRQn = 23, /!< I2C1 Event Interrupt /
Jasper_lee	0:b16d94660a33	112	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
Jasper_lee	0:b16d94660a33	113	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
Jasper_lee	0:b16d94660a33	114	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
Jasper_lee	0:b16d94660a33	115	USART1_IRQn = 27, /!< USART1 global Interrupt /
Jasper_lee	0:b16d94660a33	116	USART2_IRQn = 28 /!< USART2 global Interrupt /
Jasper_lee	0:b16d94660a33	117	} IRQn_Type;
Jasper_lee	0:b16d94660a33	118
Jasper_lee	0:b16d94660a33	119	/**
Jasper_lee	0:b16d94660a33	120	* @}
Jasper_lee	0:b16d94660a33	121	*/
Jasper_lee	0:b16d94660a33	122
Jasper_lee	0:b16d94660a33	123	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Jasper_lee	0:b16d94660a33	124	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
Jasper_lee	0:b16d94660a33	125	#include <stdint.h>
Jasper_lee	0:b16d94660a33	126
Jasper_lee	0:b16d94660a33	127	/** @addtogroup Peripheral_registers_structures
Jasper_lee	0:b16d94660a33	128	* @{
Jasper_lee	0:b16d94660a33	129	*/
Jasper_lee	0:b16d94660a33	130
Jasper_lee	0:b16d94660a33	131	/**
Jasper_lee	0:b16d94660a33	132	* @brief Analog to Digital Converter
Jasper_lee	0:b16d94660a33	133	*/
Jasper_lee	0:b16d94660a33	134
Jasper_lee	0:b16d94660a33	135	typedef struct
Jasper_lee	0:b16d94660a33	136	{
Jasper_lee	0:b16d94660a33	137	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
Jasper_lee	0:b16d94660a33	138	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
Jasper_lee	0:b16d94660a33	139	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
Jasper_lee	0:b16d94660a33	140	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
Jasper_lee	0:b16d94660a33	141	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
Jasper_lee	0:b16d94660a33	142	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
Jasper_lee	0:b16d94660a33	143	uint32_t RESERVED1; /!< Reserved, 0x18 /
Jasper_lee	0:b16d94660a33	144	uint32_t RESERVED2; /!< Reserved, 0x1C /
Jasper_lee	0:b16d94660a33	145	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
Jasper_lee	0:b16d94660a33	146	uint32_t RESERVED3; /!< Reserved, 0x24 /
Jasper_lee	0:b16d94660a33	147	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
Jasper_lee	0:b16d94660a33	148	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
Jasper_lee	0:b16d94660a33	149	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
Jasper_lee	0:b16d94660a33	150	}ADC_TypeDef;
Jasper_lee	0:b16d94660a33	151
Jasper_lee	0:b16d94660a33	152	typedef struct
Jasper_lee	0:b16d94660a33	153	{
Jasper_lee	0:b16d94660a33	154	__IO uint32_t CCR;
Jasper_lee	0:b16d94660a33	155	}ADC_Common_TypeDef;
Jasper_lee	0:b16d94660a33	156
Jasper_lee	0:b16d94660a33	157	/**
Jasper_lee	0:b16d94660a33	158	* @brief CRC calculation unit
Jasper_lee	0:b16d94660a33	159	*/
Jasper_lee	0:b16d94660a33	160
Jasper_lee	0:b16d94660a33	161	typedef struct
Jasper_lee	0:b16d94660a33	162	{
Jasper_lee	0:b16d94660a33	163	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	164	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	165	uint8_t RESERVED0; /!< Reserved, 0x05 /
Jasper_lee	0:b16d94660a33	166	uint16_t RESERVED1; /!< Reserved, 0x06 /
Jasper_lee	0:b16d94660a33	167	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	168	uint32_t RESERVED2; /!< Reserved, 0x0C /
Jasper_lee	0:b16d94660a33	169	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	170	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	171	}CRC_TypeDef;
Jasper_lee	0:b16d94660a33	172
Jasper_lee	0:b16d94660a33	173	/**
Jasper_lee	0:b16d94660a33	174	* @brief Debug MCU
Jasper_lee	0:b16d94660a33	175	*/
Jasper_lee	0:b16d94660a33	176
Jasper_lee	0:b16d94660a33	177	typedef struct
Jasper_lee	0:b16d94660a33	178	{
Jasper_lee	0:b16d94660a33	179	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	180	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	181	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	182	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	183	}DBGMCU_TypeDef;
Jasper_lee	0:b16d94660a33	184
Jasper_lee	0:b16d94660a33	185	/**
Jasper_lee	0:b16d94660a33	186	* @brief DMA Controller
Jasper_lee	0:b16d94660a33	187	*/
Jasper_lee	0:b16d94660a33	188
Jasper_lee	0:b16d94660a33	189	typedef struct
Jasper_lee	0:b16d94660a33	190	{
Jasper_lee	0:b16d94660a33	191	__IO uint32_t CCR; /!< DMA channel x configuration register /
Jasper_lee	0:b16d94660a33	192	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
Jasper_lee	0:b16d94660a33	193	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
Jasper_lee	0:b16d94660a33	194	__IO uint32_t CMAR; /!< DMA channel x memory address register /
Jasper_lee	0:b16d94660a33	195	}DMA_Channel_TypeDef;
Jasper_lee	0:b16d94660a33	196
Jasper_lee	0:b16d94660a33	197	typedef struct
Jasper_lee	0:b16d94660a33	198	{
Jasper_lee	0:b16d94660a33	199	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	200	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	201	}DMA_TypeDef;
Jasper_lee	0:b16d94660a33	202
Jasper_lee	0:b16d94660a33	203	/**
Jasper_lee	0:b16d94660a33	204	* @brief External Interrupt/Event Controller
Jasper_lee	0:b16d94660a33	205	*/
Jasper_lee	0:b16d94660a33	206
Jasper_lee	0:b16d94660a33	207	typedef struct
Jasper_lee	0:b16d94660a33	208	{
Jasper_lee	0:b16d94660a33	209	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	210	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	211	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	212	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	213	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	214	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	215	}EXTI_TypeDef;
Jasper_lee	0:b16d94660a33	216
Jasper_lee	0:b16d94660a33	217	/**
Jasper_lee	0:b16d94660a33	218	* @brief FLASH Registers
Jasper_lee	0:b16d94660a33	219	*/
Jasper_lee	0:b16d94660a33	220	typedef struct
Jasper_lee	0:b16d94660a33	221	{
Jasper_lee	0:b16d94660a33	222	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	223	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	224	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	225	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	226	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	227	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	228	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
Jasper_lee	0:b16d94660a33	229	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	230	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	231	}FLASH_TypeDef;
Jasper_lee	0:b16d94660a33	232
Jasper_lee	0:b16d94660a33	233
Jasper_lee	0:b16d94660a33	234	/**
Jasper_lee	0:b16d94660a33	235	* @brief Option Bytes Registers
Jasper_lee	0:b16d94660a33	236	*/
Jasper_lee	0:b16d94660a33	237	typedef struct
Jasper_lee	0:b16d94660a33	238	{
Jasper_lee	0:b16d94660a33	239	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	240	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
Jasper_lee	0:b16d94660a33	241	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	242	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
Jasper_lee	0:b16d94660a33	243	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	244	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
Jasper_lee	0:b16d94660a33	245	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	246	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
Jasper_lee	0:b16d94660a33	247	}OB_TypeDef;
Jasper_lee	0:b16d94660a33	248
Jasper_lee	0:b16d94660a33	249	/**
Jasper_lee	0:b16d94660a33	250	* @brief General Purpose I/O
Jasper_lee	0:b16d94660a33	251	*/
Jasper_lee	0:b16d94660a33	252
Jasper_lee	0:b16d94660a33	253	typedef struct
Jasper_lee	0:b16d94660a33	254	{
Jasper_lee	0:b16d94660a33	255	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	256	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	257	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	258	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	259	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	260	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	261	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
Jasper_lee	0:b16d94660a33	262	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	263	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
Jasper_lee	0:b16d94660a33	264	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	265	}GPIO_TypeDef;
Jasper_lee	0:b16d94660a33	266
Jasper_lee	0:b16d94660a33	267	/**
Jasper_lee	0:b16d94660a33	268	* @brief SysTem Configuration
Jasper_lee	0:b16d94660a33	269	*/
Jasper_lee	0:b16d94660a33	270
Jasper_lee	0:b16d94660a33	271	typedef struct
Jasper_lee	0:b16d94660a33	272	{
Jasper_lee	0:b16d94660a33	273	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	274	uint32_t RESERVED; /!< Reserved, 0x04 /
Jasper_lee	0:b16d94660a33	275	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
Jasper_lee	0:b16d94660a33	276	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	277	}SYSCFG_TypeDef;
Jasper_lee	0:b16d94660a33	278
Jasper_lee	0:b16d94660a33	279	/**
Jasper_lee	0:b16d94660a33	280	* @brief Inter-integrated Circuit Interface
Jasper_lee	0:b16d94660a33	281	*/
Jasper_lee	0:b16d94660a33	282
Jasper_lee	0:b16d94660a33	283	typedef struct
Jasper_lee	0:b16d94660a33	284	{
Jasper_lee	0:b16d94660a33	285	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	286	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	287	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	288	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	289	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	290	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	291	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	292	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	293	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	294	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
Jasper_lee	0:b16d94660a33	295	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	296	}I2C_TypeDef;
Jasper_lee	0:b16d94660a33	297
Jasper_lee	0:b16d94660a33	298	/**
Jasper_lee	0:b16d94660a33	299	* @brief Independent WATCHDOG
Jasper_lee	0:b16d94660a33	300	*/
Jasper_lee	0:b16d94660a33	301
Jasper_lee	0:b16d94660a33	302	typedef struct
Jasper_lee	0:b16d94660a33	303	{
Jasper_lee	0:b16d94660a33	304	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	305	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	306	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	307	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	308	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	309	}IWDG_TypeDef;
Jasper_lee	0:b16d94660a33	310
Jasper_lee	0:b16d94660a33	311	/**
Jasper_lee	0:b16d94660a33	312	* @brief Power Control
Jasper_lee	0:b16d94660a33	313	*/
Jasper_lee	0:b16d94660a33	314
Jasper_lee	0:b16d94660a33	315	typedef struct
Jasper_lee	0:b16d94660a33	316	{
Jasper_lee	0:b16d94660a33	317	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	318	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	319	}PWR_TypeDef;
Jasper_lee	0:b16d94660a33	320
Jasper_lee	0:b16d94660a33	321	/**
Jasper_lee	0:b16d94660a33	322	* @brief Reset and Clock Control
Jasper_lee	0:b16d94660a33	323	*/
Jasper_lee	0:b16d94660a33	324	typedef struct
Jasper_lee	0:b16d94660a33	325	{
Jasper_lee	0:b16d94660a33	326	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	327	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	328	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	329	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	330	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	331	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	332	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	333	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	334	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	335	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
Jasper_lee	0:b16d94660a33	336	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	337	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
Jasper_lee	0:b16d94660a33	338	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
Jasper_lee	0:b16d94660a33	339	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
Jasper_lee	0:b16d94660a33	340	}RCC_TypeDef;
Jasper_lee	0:b16d94660a33	341
Jasper_lee	0:b16d94660a33	342	/**
Jasper_lee	0:b16d94660a33	343	* @brief Real-Time Clock
Jasper_lee	0:b16d94660a33	344	*/
Jasper_lee	0:b16d94660a33	345
Jasper_lee	0:b16d94660a33	346	typedef struct
Jasper_lee	0:b16d94660a33	347	{
Jasper_lee	0:b16d94660a33	348	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	349	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	350	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	351	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	352	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	353	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	354	uint32_t RESERVED2; /!< Reserved, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	355	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	356	uint32_t RESERVED3; /!< Reserved, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	357	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Jasper_lee	0:b16d94660a33	358	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	359	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Jasper_lee	0:b16d94660a33	360	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Jasper_lee	0:b16d94660a33	361	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Jasper_lee	0:b16d94660a33	362	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Jasper_lee	0:b16d94660a33	363	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
Jasper_lee	0:b16d94660a33	364	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
Jasper_lee	0:b16d94660a33	365	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
Jasper_lee	0:b16d94660a33	366	}RTC_TypeDef;
Jasper_lee	0:b16d94660a33	367
Jasper_lee	0:b16d94660a33	368	/**
Jasper_lee	0:b16d94660a33	369	* @brief Serial Peripheral Interface
Jasper_lee	0:b16d94660a33	370	*/
Jasper_lee	0:b16d94660a33	371
Jasper_lee	0:b16d94660a33	372	typedef struct
Jasper_lee	0:b16d94660a33	373	{
Jasper_lee	0:b16d94660a33	374	__IO uint16_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	375	uint16_t RESERVED0; /!< Reserved, 0x02 /
Jasper_lee	0:b16d94660a33	376	__IO uint16_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	377	uint16_t RESERVED1; /!< Reserved, 0x06 /
Jasper_lee	0:b16d94660a33	378	__IO uint16_t SR; /!< SPI Status register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	379	uint16_t RESERVED2; /!< Reserved, 0x0A /
Jasper_lee	0:b16d94660a33	380	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	381	uint16_t RESERVED3; /!< Reserved, 0x0E /
Jasper_lee	0:b16d94660a33	382	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	383	uint16_t RESERVED4; /!< Reserved, 0x12 /
Jasper_lee	0:b16d94660a33	384	__IO uint16_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	385	uint16_t RESERVED5; /!< Reserved, 0x16 /
Jasper_lee	0:b16d94660a33	386	__IO uint16_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	387	uint16_t RESERVED6; /!< Reserved, 0x1A /
Jasper_lee	0:b16d94660a33	388	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	389	uint16_t RESERVED7; /!< Reserved, 0x1E /
Jasper_lee	0:b16d94660a33	390	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	391	uint16_t RESERVED8; /!< Reserved, 0x22 /
Jasper_lee	0:b16d94660a33	392	}SPI_TypeDef;
Jasper_lee	0:b16d94660a33	393
Jasper_lee	0:b16d94660a33	394	/**
Jasper_lee	0:b16d94660a33	395	* @brief TIM
Jasper_lee	0:b16d94660a33	396	*/
Jasper_lee	0:b16d94660a33	397	typedef struct
Jasper_lee	0:b16d94660a33	398	{
Jasper_lee	0:b16d94660a33	399	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	400	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	401	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	402	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	403	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	404	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	405	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	406	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	407	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	408	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Jasper_lee	0:b16d94660a33	409	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	410	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Jasper_lee	0:b16d94660a33	411	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
Jasper_lee	0:b16d94660a33	412	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Jasper_lee	0:b16d94660a33	413	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Jasper_lee	0:b16d94660a33	414	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Jasper_lee	0:b16d94660a33	415	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Jasper_lee	0:b16d94660a33	416	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
Jasper_lee	0:b16d94660a33	417	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Jasper_lee	0:b16d94660a33	418	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
Jasper_lee	0:b16d94660a33	419	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Jasper_lee	0:b16d94660a33	420	}TIM_TypeDef;
Jasper_lee	0:b16d94660a33	421
Jasper_lee	0:b16d94660a33	422
Jasper_lee	0:b16d94660a33	423	/**
Jasper_lee	0:b16d94660a33	424	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Jasper_lee	0:b16d94660a33	425	*/
Jasper_lee	0:b16d94660a33	426
Jasper_lee	0:b16d94660a33	427	typedef struct
Jasper_lee	0:b16d94660a33	428	{
Jasper_lee	0:b16d94660a33	429	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	430	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	431	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	432	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
Jasper_lee	0:b16d94660a33	433	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
Jasper_lee	0:b16d94660a33	434	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
Jasper_lee	0:b16d94660a33	435	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
Jasper_lee	0:b16d94660a33	436	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
Jasper_lee	0:b16d94660a33	437	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
Jasper_lee	0:b16d94660a33	438	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
Jasper_lee	0:b16d94660a33	439	uint16_t RESERVED1; /!< Reserved, 0x26 /
Jasper_lee	0:b16d94660a33	440	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
Jasper_lee	0:b16d94660a33	441	uint16_t RESERVED2; /!< Reserved, 0x2A /
Jasper_lee	0:b16d94660a33	442	}USART_TypeDef;
Jasper_lee	0:b16d94660a33	443
Jasper_lee	0:b16d94660a33	444	/**
Jasper_lee	0:b16d94660a33	445	* @brief Window WATCHDOG
Jasper_lee	0:b16d94660a33	446	*/
Jasper_lee	0:b16d94660a33	447	typedef struct
Jasper_lee	0:b16d94660a33	448	{
Jasper_lee	0:b16d94660a33	449	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Jasper_lee	0:b16d94660a33	450	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Jasper_lee	0:b16d94660a33	451	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Jasper_lee	0:b16d94660a33	452	}WWDG_TypeDef;
Jasper_lee	0:b16d94660a33	453
Jasper_lee	0:b16d94660a33	454	/**
Jasper_lee	0:b16d94660a33	455	* @}
Jasper_lee	0:b16d94660a33	456	*/
Jasper_lee	0:b16d94660a33	457
Jasper_lee	0:b16d94660a33	458	/** @addtogroup Peripheral_memory_map
Jasper_lee	0:b16d94660a33	459	* @{
Jasper_lee	0:b16d94660a33	460	*/
Jasper_lee	0:b16d94660a33	461
Jasper_lee	0:b16d94660a33	462	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
Jasper_lee	0:b16d94660a33	463	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
Jasper_lee	0:b16d94660a33	464	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
Jasper_lee	0:b16d94660a33	465
Jasper_lee	0:b16d94660a33	466	/!< Peripheral memory map /
Jasper_lee	0:b16d94660a33	467	#define APBPERIPH_BASE PERIPH_BASE
Jasper_lee	0:b16d94660a33	468	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Jasper_lee	0:b16d94660a33	469	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Jasper_lee	0:b16d94660a33	470
Jasper_lee	0:b16d94660a33	471	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Jasper_lee	0:b16d94660a33	472	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Jasper_lee	0:b16d94660a33	473	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Jasper_lee	0:b16d94660a33	474	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Jasper_lee	0:b16d94660a33	475	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Jasper_lee	0:b16d94660a33	476	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Jasper_lee	0:b16d94660a33	477	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Jasper_lee	0:b16d94660a33	478	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Jasper_lee	0:b16d94660a33	479	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Jasper_lee	0:b16d94660a33	480	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Jasper_lee	0:b16d94660a33	481	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Jasper_lee	0:b16d94660a33	482	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Jasper_lee	0:b16d94660a33	483	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Jasper_lee	0:b16d94660a33	484	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Jasper_lee	0:b16d94660a33	485	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Jasper_lee	0:b16d94660a33	486	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Jasper_lee	0:b16d94660a33	487	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Jasper_lee	0:b16d94660a33	488	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Jasper_lee	0:b16d94660a33	489	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
Jasper_lee	0:b16d94660a33	490	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Jasper_lee	0:b16d94660a33	491	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Jasper_lee	0:b16d94660a33	492	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Jasper_lee	0:b16d94660a33	493
Jasper_lee	0:b16d94660a33	494	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Jasper_lee	0:b16d94660a33	495	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Jasper_lee	0:b16d94660a33	496	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Jasper_lee	0:b16d94660a33	497	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Jasper_lee	0:b16d94660a33	498	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Jasper_lee	0:b16d94660a33	499	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Jasper_lee	0:b16d94660a33	500
Jasper_lee	0:b16d94660a33	501	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Jasper_lee	0:b16d94660a33	502	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
Jasper_lee	0:b16d94660a33	503	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
Jasper_lee	0:b16d94660a33	504	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Jasper_lee	0:b16d94660a33	505
Jasper_lee	0:b16d94660a33	506	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Jasper_lee	0:b16d94660a33	507	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Jasper_lee	0:b16d94660a33	508	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Jasper_lee	0:b16d94660a33	509	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
Jasper_lee	0:b16d94660a33	510	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Jasper_lee	0:b16d94660a33	511
Jasper_lee	0:b16d94660a33	512	/**
Jasper_lee	0:b16d94660a33	513	* @}
Jasper_lee	0:b16d94660a33	514	*/
Jasper_lee	0:b16d94660a33	515
Jasper_lee	0:b16d94660a33	516	/** @addtogroup Peripheral_declaration
Jasper_lee	0:b16d94660a33	517	* @{
Jasper_lee	0:b16d94660a33	518	*/
Jasper_lee	0:b16d94660a33	519
Jasper_lee	0:b16d94660a33	520	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Jasper_lee	0:b16d94660a33	521	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Jasper_lee	0:b16d94660a33	522	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Jasper_lee	0:b16d94660a33	523	#define RTC ((RTC_TypeDef *) RTC_BASE)
Jasper_lee	0:b16d94660a33	524	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Jasper_lee	0:b16d94660a33	525	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Jasper_lee	0:b16d94660a33	526	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Jasper_lee	0:b16d94660a33	527	#define USART2 ((USART_TypeDef *) USART2_BASE)
Jasper_lee	0:b16d94660a33	528	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Jasper_lee	0:b16d94660a33	529	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Jasper_lee	0:b16d94660a33	530	#define PWR ((PWR_TypeDef *) PWR_BASE)
Jasper_lee	0:b16d94660a33	531	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Jasper_lee	0:b16d94660a33	532	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Jasper_lee	0:b16d94660a33	533	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Jasper_lee	0:b16d94660a33	534	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Jasper_lee	0:b16d94660a33	535	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Jasper_lee	0:b16d94660a33	536	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Jasper_lee	0:b16d94660a33	537	#define USART1 ((USART_TypeDef *) USART1_BASE)
Jasper_lee	0:b16d94660a33	538	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Jasper_lee	0:b16d94660a33	539	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Jasper_lee	0:b16d94660a33	540	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Jasper_lee	0:b16d94660a33	541	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Jasper_lee	0:b16d94660a33	542	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Jasper_lee	0:b16d94660a33	543	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Jasper_lee	0:b16d94660a33	544	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Jasper_lee	0:b16d94660a33	545	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Jasper_lee	0:b16d94660a33	546	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Jasper_lee	0:b16d94660a33	547	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Jasper_lee	0:b16d94660a33	548	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Jasper_lee	0:b16d94660a33	549	#define OB ((OB_TypeDef *) OB_BASE)
Jasper_lee	0:b16d94660a33	550	#define RCC ((RCC_TypeDef *) RCC_BASE)
Jasper_lee	0:b16d94660a33	551	#define CRC ((CRC_TypeDef *) CRC_BASE)
Jasper_lee	0:b16d94660a33	552	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Jasper_lee	0:b16d94660a33	553	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Jasper_lee	0:b16d94660a33	554	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Jasper_lee	0:b16d94660a33	555	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Jasper_lee	0:b16d94660a33	556	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Jasper_lee	0:b16d94660a33	557
Jasper_lee	0:b16d94660a33	558	/**
Jasper_lee	0:b16d94660a33	559	* @}
Jasper_lee	0:b16d94660a33	560	*/
Jasper_lee	0:b16d94660a33	561
Jasper_lee	0:b16d94660a33	562	/** @addtogroup Exported_constants
Jasper_lee	0:b16d94660a33	563	* @{
Jasper_lee	0:b16d94660a33	564	*/
Jasper_lee	0:b16d94660a33	565
Jasper_lee	0:b16d94660a33	566	/** @addtogroup Peripheral_Registers_Bits_Definition
Jasper_lee	0:b16d94660a33	567	* @{
Jasper_lee	0:b16d94660a33	568	*/
Jasper_lee	0:b16d94660a33	569
Jasper_lee	0:b16d94660a33	570	/******************************************************************************/
Jasper_lee	0:b16d94660a33	571	/* Peripheral Registers Bits Definition */
Jasper_lee	0:b16d94660a33	572	/******************************************************************************/
Jasper_lee	0:b16d94660a33	573	/******************************************************************************/
Jasper_lee	0:b16d94660a33	574	/* */
Jasper_lee	0:b16d94660a33	575	/* Analog to Digital Converter (ADC) */
Jasper_lee	0:b16d94660a33	576	/* */
Jasper_lee	0:b16d94660a33	577	/******************************************************************************/
Jasper_lee	0:b16d94660a33	578	/****************** Bits definition for ADC_ISR register ****************/
Jasper_lee	0:b16d94660a33	579	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
Jasper_lee	0:b16d94660a33	580	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
Jasper_lee	0:b16d94660a33	581	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
Jasper_lee	0:b16d94660a33	582	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
Jasper_lee	0:b16d94660a33	583	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
Jasper_lee	0:b16d94660a33	584	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
Jasper_lee	0:b16d94660a33	585
Jasper_lee	0:b16d94660a33	586	/* Old EOSEQ bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	587	#define ADC_ISR_EOS ADC_ISR_EOSEQ
Jasper_lee	0:b16d94660a33	588
Jasper_lee	0:b16d94660a33	589	/****************** Bits definition for ADC_IER register ****************/
Jasper_lee	0:b16d94660a33	590	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
Jasper_lee	0:b16d94660a33	591	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
Jasper_lee	0:b16d94660a33	592	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
Jasper_lee	0:b16d94660a33	593	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
Jasper_lee	0:b16d94660a33	594	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
Jasper_lee	0:b16d94660a33	595	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
Jasper_lee	0:b16d94660a33	596
Jasper_lee	0:b16d94660a33	597	/* Old EOSEQIE bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	598	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
Jasper_lee	0:b16d94660a33	599
Jasper_lee	0:b16d94660a33	600	/****************** Bits definition for ADC_CR register *****************/
Jasper_lee	0:b16d94660a33	601	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
Jasper_lee	0:b16d94660a33	602	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
Jasper_lee	0:b16d94660a33	603	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
Jasper_lee	0:b16d94660a33	604	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
Jasper_lee	0:b16d94660a33	605	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
Jasper_lee	0:b16d94660a33	606
Jasper_lee	0:b16d94660a33	607	/***************** Bits definition for ADC_CFGR1 register ***************/
Jasper_lee	0:b16d94660a33	608	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
Jasper_lee	0:b16d94660a33	609	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	610	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	611	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	612	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	613	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
Jasper_lee	0:b16d94660a33	614	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
Jasper_lee	0:b16d94660a33	615	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
Jasper_lee	0:b16d94660a33	616	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
Jasper_lee	0:b16d94660a33	617	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
Jasper_lee	0:b16d94660a33	618	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
Jasper_lee	0:b16d94660a33	619	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
Jasper_lee	0:b16d94660a33	620	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
Jasper_lee	0:b16d94660a33	621	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
Jasper_lee	0:b16d94660a33	622	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	623	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	624	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
Jasper_lee	0:b16d94660a33	625	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	626	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	627	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	628	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
Jasper_lee	0:b16d94660a33	629	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
Jasper_lee	0:b16d94660a33	630	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	631	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	632	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
Jasper_lee	0:b16d94660a33	633	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
Jasper_lee	0:b16d94660a33	634	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
Jasper_lee	0:b16d94660a33	635
Jasper_lee	0:b16d94660a33	636	/* Old WAIT bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	637	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Jasper_lee	0:b16d94660a33	638
Jasper_lee	0:b16d94660a33	639	/***************** Bits definition for ADC_CFGR2 register ***************/
Jasper_lee	0:b16d94660a33	640	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
Jasper_lee	0:b16d94660a33	641	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
Jasper_lee	0:b16d94660a33	642	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
Jasper_lee	0:b16d94660a33	643
Jasper_lee	0:b16d94660a33	644	/* Old bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	645	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
Jasper_lee	0:b16d94660a33	646	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
Jasper_lee	0:b16d94660a33	647
Jasper_lee	0:b16d94660a33	648	/**************** Bit definition for ADC_SMPR register ******************/
Jasper_lee	0:b16d94660a33	649	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
Jasper_lee	0:b16d94660a33	650	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	651	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	652	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	653
Jasper_lee	0:b16d94660a33	654	/* Old bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	655	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
Jasper_lee	0:b16d94660a33	656	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
Jasper_lee	0:b16d94660a33	657	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
Jasper_lee	0:b16d94660a33	658	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
Jasper_lee	0:b16d94660a33	659
Jasper_lee	0:b16d94660a33	660	/***************** Bit definition for ADC_TR register ******************/
Jasper_lee	0:b16d94660a33	661	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
Jasper_lee	0:b16d94660a33	662	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
Jasper_lee	0:b16d94660a33	663
Jasper_lee	0:b16d94660a33	664	/* Old bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	665	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
Jasper_lee	0:b16d94660a33	666	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
Jasper_lee	0:b16d94660a33	667
Jasper_lee	0:b16d94660a33	668	/**************** Bit definition for ADC_CHSELR register ****************/
Jasper_lee	0:b16d94660a33	669	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
Jasper_lee	0:b16d94660a33	670	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
Jasper_lee	0:b16d94660a33	671	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
Jasper_lee	0:b16d94660a33	672	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
Jasper_lee	0:b16d94660a33	673	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
Jasper_lee	0:b16d94660a33	674	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
Jasper_lee	0:b16d94660a33	675	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
Jasper_lee	0:b16d94660a33	676	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
Jasper_lee	0:b16d94660a33	677	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
Jasper_lee	0:b16d94660a33	678	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
Jasper_lee	0:b16d94660a33	679	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
Jasper_lee	0:b16d94660a33	680	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
Jasper_lee	0:b16d94660a33	681	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
Jasper_lee	0:b16d94660a33	682	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
Jasper_lee	0:b16d94660a33	683	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
Jasper_lee	0:b16d94660a33	684	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
Jasper_lee	0:b16d94660a33	685	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
Jasper_lee	0:b16d94660a33	686	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
Jasper_lee	0:b16d94660a33	687	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
Jasper_lee	0:b16d94660a33	688
Jasper_lee	0:b16d94660a33	689	/****************** Bit definition for ADC_DR register ******************/
Jasper_lee	0:b16d94660a33	690	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
Jasper_lee	0:b16d94660a33	691
Jasper_lee	0:b16d94660a33	692	/***************** Bit definition for ADC_CCR register ******************/
Jasper_lee	0:b16d94660a33	693	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
Jasper_lee	0:b16d94660a33	694	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
Jasper_lee	0:b16d94660a33	695	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
Jasper_lee	0:b16d94660a33	696
Jasper_lee	0:b16d94660a33	697	/******************************************************************************/
Jasper_lee	0:b16d94660a33	698	/* */
Jasper_lee	0:b16d94660a33	699	/* CRC calculation unit (CRC) */
Jasper_lee	0:b16d94660a33	700	/* */
Jasper_lee	0:b16d94660a33	701	/******************************************************************************/
Jasper_lee	0:b16d94660a33	702	/***************** Bit definition for CRC_DR register *******************/
Jasper_lee	0:b16d94660a33	703	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
Jasper_lee	0:b16d94660a33	704
Jasper_lee	0:b16d94660a33	705	/***************** Bit definition for CRC_IDR register ******************/
Jasper_lee	0:b16d94660a33	706	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
Jasper_lee	0:b16d94660a33	707
Jasper_lee	0:b16d94660a33	708	/****************** Bit definition for CRC_CR register ******************/
Jasper_lee	0:b16d94660a33	709	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
Jasper_lee	0:b16d94660a33	710	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
Jasper_lee	0:b16d94660a33	711	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
Jasper_lee	0:b16d94660a33	712	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
Jasper_lee	0:b16d94660a33	713	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
Jasper_lee	0:b16d94660a33	714
Jasper_lee	0:b16d94660a33	715	/***************** Bit definition for CRC_INIT register *****************/
Jasper_lee	0:b16d94660a33	716	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
Jasper_lee	0:b16d94660a33	717
Jasper_lee	0:b16d94660a33	718	/******************************************************************************/
Jasper_lee	0:b16d94660a33	719	/* */
Jasper_lee	0:b16d94660a33	720	/* Debug MCU (DBGMCU) */
Jasper_lee	0:b16d94660a33	721	/* */
Jasper_lee	0:b16d94660a33	722	/******************************************************************************/
Jasper_lee	0:b16d94660a33	723
Jasper_lee	0:b16d94660a33	724	/************** Bit definition for DBGMCU_IDCODE register ***************/
Jasper_lee	0:b16d94660a33	725	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
Jasper_lee	0:b16d94660a33	726
Jasper_lee	0:b16d94660a33	727	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
Jasper_lee	0:b16d94660a33	728	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	729	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	730	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	731	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	732	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
Jasper_lee	0:b16d94660a33	733	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
Jasper_lee	0:b16d94660a33	734	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
Jasper_lee	0:b16d94660a33	735	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
Jasper_lee	0:b16d94660a33	736	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
Jasper_lee	0:b16d94660a33	737	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
Jasper_lee	0:b16d94660a33	738	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
Jasper_lee	0:b16d94660a33	739	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
Jasper_lee	0:b16d94660a33	740	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
Jasper_lee	0:b16d94660a33	741	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
Jasper_lee	0:b16d94660a33	742	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
Jasper_lee	0:b16d94660a33	743	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
Jasper_lee	0:b16d94660a33	744
Jasper_lee	0:b16d94660a33	745	/**************** Bit definition for DBGMCU_CR register *****************/
Jasper_lee	0:b16d94660a33	746	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
Jasper_lee	0:b16d94660a33	747	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
Jasper_lee	0:b16d94660a33	748
Jasper_lee	0:b16d94660a33	749	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
Jasper_lee	0:b16d94660a33	750	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	751	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	752	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	753	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
Jasper_lee	0:b16d94660a33	754	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
Jasper_lee	0:b16d94660a33	755	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
Jasper_lee	0:b16d94660a33	756	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
Jasper_lee	0:b16d94660a33	757
Jasper_lee	0:b16d94660a33	758	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
Jasper_lee	0:b16d94660a33	759	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	760	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	761	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	762	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
Jasper_lee	0:b16d94660a33	763
Jasper_lee	0:b16d94660a33	764	/******************************************************************************/
Jasper_lee	0:b16d94660a33	765	/* */
Jasper_lee	0:b16d94660a33	766	/* DMA Controller (DMA) */
Jasper_lee	0:b16d94660a33	767	/* */
Jasper_lee	0:b16d94660a33	768	/******************************************************************************/
Jasper_lee	0:b16d94660a33	769	/***************** Bit definition for DMA_ISR register ******************/
Jasper_lee	0:b16d94660a33	770	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
Jasper_lee	0:b16d94660a33	771	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
Jasper_lee	0:b16d94660a33	772	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
Jasper_lee	0:b16d94660a33	773	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
Jasper_lee	0:b16d94660a33	774	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
Jasper_lee	0:b16d94660a33	775	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
Jasper_lee	0:b16d94660a33	776	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
Jasper_lee	0:b16d94660a33	777	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
Jasper_lee	0:b16d94660a33	778	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
Jasper_lee	0:b16d94660a33	779	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
Jasper_lee	0:b16d94660a33	780	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
Jasper_lee	0:b16d94660a33	781	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
Jasper_lee	0:b16d94660a33	782	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
Jasper_lee	0:b16d94660a33	783	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
Jasper_lee	0:b16d94660a33	784	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
Jasper_lee	0:b16d94660a33	785	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
Jasper_lee	0:b16d94660a33	786	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
Jasper_lee	0:b16d94660a33	787	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
Jasper_lee	0:b16d94660a33	788	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
Jasper_lee	0:b16d94660a33	789	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
Jasper_lee	0:b16d94660a33	790
Jasper_lee	0:b16d94660a33	791	/***************** Bit definition for DMA_IFCR register *****************/
Jasper_lee	0:b16d94660a33	792	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
Jasper_lee	0:b16d94660a33	793	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
Jasper_lee	0:b16d94660a33	794	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
Jasper_lee	0:b16d94660a33	795	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
Jasper_lee	0:b16d94660a33	796	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
Jasper_lee	0:b16d94660a33	797	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
Jasper_lee	0:b16d94660a33	798	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
Jasper_lee	0:b16d94660a33	799	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
Jasper_lee	0:b16d94660a33	800	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
Jasper_lee	0:b16d94660a33	801	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
Jasper_lee	0:b16d94660a33	802	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
Jasper_lee	0:b16d94660a33	803	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
Jasper_lee	0:b16d94660a33	804	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
Jasper_lee	0:b16d94660a33	805	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
Jasper_lee	0:b16d94660a33	806	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
Jasper_lee	0:b16d94660a33	807	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
Jasper_lee	0:b16d94660a33	808	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
Jasper_lee	0:b16d94660a33	809	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
Jasper_lee	0:b16d94660a33	810	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
Jasper_lee	0:b16d94660a33	811	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
Jasper_lee	0:b16d94660a33	812
Jasper_lee	0:b16d94660a33	813	/***************** Bit definition for DMA_CCR register ******************/
Jasper_lee	0:b16d94660a33	814	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
Jasper_lee	0:b16d94660a33	815	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
Jasper_lee	0:b16d94660a33	816	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
Jasper_lee	0:b16d94660a33	817	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
Jasper_lee	0:b16d94660a33	818	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
Jasper_lee	0:b16d94660a33	819	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
Jasper_lee	0:b16d94660a33	820	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
Jasper_lee	0:b16d94660a33	821	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
Jasper_lee	0:b16d94660a33	822
Jasper_lee	0:b16d94660a33	823	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
Jasper_lee	0:b16d94660a33	824	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	825	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	826
Jasper_lee	0:b16d94660a33	827	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
Jasper_lee	0:b16d94660a33	828	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	829	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	830
Jasper_lee	0:b16d94660a33	831	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
Jasper_lee	0:b16d94660a33	832	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	833	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	834
Jasper_lee	0:b16d94660a33	835	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
Jasper_lee	0:b16d94660a33	836
Jasper_lee	0:b16d94660a33	837	/**************** Bit definition for DMA_CNDTR register *****************/
Jasper_lee	0:b16d94660a33	838	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
Jasper_lee	0:b16d94660a33	839
Jasper_lee	0:b16d94660a33	840	/**************** Bit definition for DMA_CPAR register ******************/
Jasper_lee	0:b16d94660a33	841	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Jasper_lee	0:b16d94660a33	842
Jasper_lee	0:b16d94660a33	843	/**************** Bit definition for DMA_CMAR register ******************/
Jasper_lee	0:b16d94660a33	844	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Jasper_lee	0:b16d94660a33	845
Jasper_lee	0:b16d94660a33	846	/******************************************************************************/
Jasper_lee	0:b16d94660a33	847	/* */
Jasper_lee	0:b16d94660a33	848	/* External Interrupt/Event Controller (EXTI) */
Jasper_lee	0:b16d94660a33	849	/* */
Jasper_lee	0:b16d94660a33	850	/******************************************************************************/
Jasper_lee	0:b16d94660a33	851	/***************** Bit definition for EXTI_IMR register *****************/
Jasper_lee	0:b16d94660a33	852	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
Jasper_lee	0:b16d94660a33	853	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
Jasper_lee	0:b16d94660a33	854	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
Jasper_lee	0:b16d94660a33	855	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
Jasper_lee	0:b16d94660a33	856	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
Jasper_lee	0:b16d94660a33	857	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
Jasper_lee	0:b16d94660a33	858	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
Jasper_lee	0:b16d94660a33	859	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
Jasper_lee	0:b16d94660a33	860	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
Jasper_lee	0:b16d94660a33	861	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
Jasper_lee	0:b16d94660a33	862	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
Jasper_lee	0:b16d94660a33	863	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
Jasper_lee	0:b16d94660a33	864	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
Jasper_lee	0:b16d94660a33	865	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
Jasper_lee	0:b16d94660a33	866	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
Jasper_lee	0:b16d94660a33	867	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
Jasper_lee	0:b16d94660a33	868	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
Jasper_lee	0:b16d94660a33	869	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
Jasper_lee	0:b16d94660a33	870	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
Jasper_lee	0:b16d94660a33	871	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
Jasper_lee	0:b16d94660a33	872	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
Jasper_lee	0:b16d94660a33	873	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
Jasper_lee	0:b16d94660a33	874	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
Jasper_lee	0:b16d94660a33	875	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
Jasper_lee	0:b16d94660a33	876
Jasper_lee	0:b16d94660a33	877	/**************** Bit definition for EXTI_EMR register ******************/
Jasper_lee	0:b16d94660a33	878	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
Jasper_lee	0:b16d94660a33	879	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
Jasper_lee	0:b16d94660a33	880	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
Jasper_lee	0:b16d94660a33	881	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
Jasper_lee	0:b16d94660a33	882	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
Jasper_lee	0:b16d94660a33	883	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
Jasper_lee	0:b16d94660a33	884	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
Jasper_lee	0:b16d94660a33	885	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
Jasper_lee	0:b16d94660a33	886	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
Jasper_lee	0:b16d94660a33	887	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
Jasper_lee	0:b16d94660a33	888	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
Jasper_lee	0:b16d94660a33	889	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
Jasper_lee	0:b16d94660a33	890	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
Jasper_lee	0:b16d94660a33	891	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
Jasper_lee	0:b16d94660a33	892	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
Jasper_lee	0:b16d94660a33	893	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
Jasper_lee	0:b16d94660a33	894	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
Jasper_lee	0:b16d94660a33	895	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
Jasper_lee	0:b16d94660a33	896	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
Jasper_lee	0:b16d94660a33	897	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
Jasper_lee	0:b16d94660a33	898	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
Jasper_lee	0:b16d94660a33	899	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
Jasper_lee	0:b16d94660a33	900	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
Jasper_lee	0:b16d94660a33	901	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
Jasper_lee	0:b16d94660a33	902
Jasper_lee	0:b16d94660a33	903	/***************** Bit definition for EXTI_RTSR register ****************/
Jasper_lee	0:b16d94660a33	904	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
Jasper_lee	0:b16d94660a33	905	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
Jasper_lee	0:b16d94660a33	906	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
Jasper_lee	0:b16d94660a33	907	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
Jasper_lee	0:b16d94660a33	908	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
Jasper_lee	0:b16d94660a33	909	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
Jasper_lee	0:b16d94660a33	910	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
Jasper_lee	0:b16d94660a33	911	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
Jasper_lee	0:b16d94660a33	912	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
Jasper_lee	0:b16d94660a33	913	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
Jasper_lee	0:b16d94660a33	914	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
Jasper_lee	0:b16d94660a33	915	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
Jasper_lee	0:b16d94660a33	916	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
Jasper_lee	0:b16d94660a33	917	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
Jasper_lee	0:b16d94660a33	918	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
Jasper_lee	0:b16d94660a33	919	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
Jasper_lee	0:b16d94660a33	920	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
Jasper_lee	0:b16d94660a33	921	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
Jasper_lee	0:b16d94660a33	922	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
Jasper_lee	0:b16d94660a33	923
Jasper_lee	0:b16d94660a33	924	/***************** Bit definition for EXTI_FTSR register *****************/
Jasper_lee	0:b16d94660a33	925	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
Jasper_lee	0:b16d94660a33	926	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
Jasper_lee	0:b16d94660a33	927	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
Jasper_lee	0:b16d94660a33	928	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
Jasper_lee	0:b16d94660a33	929	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
Jasper_lee	0:b16d94660a33	930	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
Jasper_lee	0:b16d94660a33	931	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
Jasper_lee	0:b16d94660a33	932	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
Jasper_lee	0:b16d94660a33	933	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
Jasper_lee	0:b16d94660a33	934	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
Jasper_lee	0:b16d94660a33	935	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
Jasper_lee	0:b16d94660a33	936	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
Jasper_lee	0:b16d94660a33	937	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
Jasper_lee	0:b16d94660a33	938	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
Jasper_lee	0:b16d94660a33	939	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
Jasper_lee	0:b16d94660a33	940	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
Jasper_lee	0:b16d94660a33	941	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
Jasper_lee	0:b16d94660a33	942	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
Jasper_lee	0:b16d94660a33	943	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
Jasper_lee	0:b16d94660a33	944
Jasper_lee	0:b16d94660a33	945	/***************** Bit definition for EXTI_SWIER register *****************/
Jasper_lee	0:b16d94660a33	946	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
Jasper_lee	0:b16d94660a33	947	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
Jasper_lee	0:b16d94660a33	948	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
Jasper_lee	0:b16d94660a33	949	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
Jasper_lee	0:b16d94660a33	950	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
Jasper_lee	0:b16d94660a33	951	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
Jasper_lee	0:b16d94660a33	952	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
Jasper_lee	0:b16d94660a33	953	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
Jasper_lee	0:b16d94660a33	954	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
Jasper_lee	0:b16d94660a33	955	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
Jasper_lee	0:b16d94660a33	956	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
Jasper_lee	0:b16d94660a33	957	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
Jasper_lee	0:b16d94660a33	958	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
Jasper_lee	0:b16d94660a33	959	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
Jasper_lee	0:b16d94660a33	960	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
Jasper_lee	0:b16d94660a33	961	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
Jasper_lee	0:b16d94660a33	962	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
Jasper_lee	0:b16d94660a33	963	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
Jasper_lee	0:b16d94660a33	964	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
Jasper_lee	0:b16d94660a33	965
Jasper_lee	0:b16d94660a33	966	/**************** Bit definition for EXTI_PR register *******************/
Jasper_lee	0:b16d94660a33	967	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
Jasper_lee	0:b16d94660a33	968	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
Jasper_lee	0:b16d94660a33	969	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
Jasper_lee	0:b16d94660a33	970	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
Jasper_lee	0:b16d94660a33	971	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
Jasper_lee	0:b16d94660a33	972	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
Jasper_lee	0:b16d94660a33	973	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
Jasper_lee	0:b16d94660a33	974	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
Jasper_lee	0:b16d94660a33	975	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
Jasper_lee	0:b16d94660a33	976	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
Jasper_lee	0:b16d94660a33	977	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
Jasper_lee	0:b16d94660a33	978	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
Jasper_lee	0:b16d94660a33	979	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
Jasper_lee	0:b16d94660a33	980	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
Jasper_lee	0:b16d94660a33	981	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
Jasper_lee	0:b16d94660a33	982	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
Jasper_lee	0:b16d94660a33	983	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
Jasper_lee	0:b16d94660a33	984	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
Jasper_lee	0:b16d94660a33	985	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
Jasper_lee	0:b16d94660a33	986
Jasper_lee	0:b16d94660a33	987	/******************************************************************************/
Jasper_lee	0:b16d94660a33	988	/* */
Jasper_lee	0:b16d94660a33	989	/* FLASH and Option Bytes Registers */
Jasper_lee	0:b16d94660a33	990	/* */
Jasper_lee	0:b16d94660a33	991	/******************************************************************************/
Jasper_lee	0:b16d94660a33	992
Jasper_lee	0:b16d94660a33	993	/***************** Bit definition for FLASH_ACR register ****************/
Jasper_lee	0:b16d94660a33	994	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
Jasper_lee	0:b16d94660a33	995
Jasper_lee	0:b16d94660a33	996	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
Jasper_lee	0:b16d94660a33	997	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
Jasper_lee	0:b16d94660a33	998
Jasper_lee	0:b16d94660a33	999	/**************** Bit definition for FLASH_KEYR register ****************/
Jasper_lee	0:b16d94660a33	1000	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
Jasper_lee	0:b16d94660a33	1001
Jasper_lee	0:b16d94660a33	1002	/*************** Bit definition for FLASH_OPTKEYR register **************/
Jasper_lee	0:b16d94660a33	1003	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
Jasper_lee	0:b16d94660a33	1004
Jasper_lee	0:b16d94660a33	1005	/**************** FLASH Keys ********************************************/
Jasper_lee	0:b16d94660a33	1006	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
Jasper_lee	0:b16d94660a33	1007	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Jasper_lee	0:b16d94660a33	1008	to unlock the write access to the FPEC. */
Jasper_lee	0:b16d94660a33	1009
Jasper_lee	0:b16d94660a33	1010	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
Jasper_lee	0:b16d94660a33	1011	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Jasper_lee	0:b16d94660a33	1012	unlock the write access to the option byte block */
Jasper_lee	0:b16d94660a33	1013
Jasper_lee	0:b16d94660a33	1014	/**************** Bit definition for FLASH_SR register *****************/
Jasper_lee	0:b16d94660a33	1015	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
Jasper_lee	0:b16d94660a33	1016	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
Jasper_lee	0:b16d94660a33	1017	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
Jasper_lee	0:b16d94660a33	1018	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
Jasper_lee	0:b16d94660a33	1019	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
Jasper_lee	0:b16d94660a33	1020
Jasper_lee	0:b16d94660a33	1021	/***************** Bit definition for FLASH_CR register *****************/
Jasper_lee	0:b16d94660a33	1022	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
Jasper_lee	0:b16d94660a33	1023	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
Jasper_lee	0:b16d94660a33	1024	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
Jasper_lee	0:b16d94660a33	1025	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
Jasper_lee	0:b16d94660a33	1026	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
Jasper_lee	0:b16d94660a33	1027	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
Jasper_lee	0:b16d94660a33	1028	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
Jasper_lee	0:b16d94660a33	1029	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
Jasper_lee	0:b16d94660a33	1030	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
Jasper_lee	0:b16d94660a33	1031	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
Jasper_lee	0:b16d94660a33	1032	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
Jasper_lee	0:b16d94660a33	1033
Jasper_lee	0:b16d94660a33	1034	/***************** Bit definition for FLASH_AR register *****************/
Jasper_lee	0:b16d94660a33	1035	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
Jasper_lee	0:b16d94660a33	1036
Jasper_lee	0:b16d94660a33	1037	/**************** Bit definition for FLASH_OBR register *****************/
Jasper_lee	0:b16d94660a33	1038	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
Jasper_lee	0:b16d94660a33	1039	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
Jasper_lee	0:b16d94660a33	1040	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
Jasper_lee	0:b16d94660a33	1041
Jasper_lee	0:b16d94660a33	1042	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
Jasper_lee	0:b16d94660a33	1043	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
Jasper_lee	0:b16d94660a33	1044	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
Jasper_lee	0:b16d94660a33	1045	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
Jasper_lee	0:b16d94660a33	1046	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
Jasper_lee	0:b16d94660a33	1047	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
Jasper_lee	0:b16d94660a33	1048
Jasper_lee	0:b16d94660a33	1049	/* Old BOOT1 bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1050	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Jasper_lee	0:b16d94660a33	1051
Jasper_lee	0:b16d94660a33	1052	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1053	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Jasper_lee	0:b16d94660a33	1054
Jasper_lee	0:b16d94660a33	1055	/**************** Bit definition for FLASH_WRPR register ****************/
Jasper_lee	0:b16d94660a33	1056	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
Jasper_lee	0:b16d94660a33	1057
Jasper_lee	0:b16d94660a33	1058	/----------------------------------------------------------------------------/
Jasper_lee	0:b16d94660a33	1059
Jasper_lee	0:b16d94660a33	1060	/**************** Bit definition for OB_RDP register ********************/
Jasper_lee	0:b16d94660a33	1061	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
Jasper_lee	0:b16d94660a33	1062	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
Jasper_lee	0:b16d94660a33	1063
Jasper_lee	0:b16d94660a33	1064	/**************** Bit definition for OB_USER register *******************/
Jasper_lee	0:b16d94660a33	1065	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
Jasper_lee	0:b16d94660a33	1066	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
Jasper_lee	0:b16d94660a33	1067
Jasper_lee	0:b16d94660a33	1068	/**************** Bit definition for OB_WRP0 register *******************/
Jasper_lee	0:b16d94660a33	1069	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
Jasper_lee	0:b16d94660a33	1070	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
Jasper_lee	0:b16d94660a33	1071
Jasper_lee	0:b16d94660a33	1072	/**************** Bit definition for OB_WRP1 register *******************/
Jasper_lee	0:b16d94660a33	1073	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
Jasper_lee	0:b16d94660a33	1074	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
Jasper_lee	0:b16d94660a33	1075
Jasper_lee	0:b16d94660a33	1076	/******************************************************************************/
Jasper_lee	0:b16d94660a33	1077	/* */
Jasper_lee	0:b16d94660a33	1078	/* General Purpose IOs (GPIO) */
Jasper_lee	0:b16d94660a33	1079	/* */
Jasper_lee	0:b16d94660a33	1080	/******************************************************************************/
Jasper_lee	0:b16d94660a33	1081	/***************** Bit definition for GPIO_MODER register ***************/
Jasper_lee	0:b16d94660a33	1082	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Jasper_lee	0:b16d94660a33	1083	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1084	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1085	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Jasper_lee	0:b16d94660a33	1086	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1087	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1088	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Jasper_lee	0:b16d94660a33	1089	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1090	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1091	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Jasper_lee	0:b16d94660a33	1092	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1093	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1094	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Jasper_lee	0:b16d94660a33	1095	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1096	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1097	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Jasper_lee	0:b16d94660a33	1098	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1099	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1100	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Jasper_lee	0:b16d94660a33	1101	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1102	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1103	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Jasper_lee	0:b16d94660a33	1104	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1105	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1106	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Jasper_lee	0:b16d94660a33	1107	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1108	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1109	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Jasper_lee	0:b16d94660a33	1110	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1111	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1112	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	1113	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1114	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1115	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Jasper_lee	0:b16d94660a33	1116	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1117	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1118	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Jasper_lee	0:b16d94660a33	1119	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	1120	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	1121	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Jasper_lee	0:b16d94660a33	1122	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	1123	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	1124	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Jasper_lee	0:b16d94660a33	1125	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Jasper_lee	0:b16d94660a33	1126	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Jasper_lee	0:b16d94660a33	1127	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Jasper_lee	0:b16d94660a33	1128	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Jasper_lee	0:b16d94660a33	1129	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	1130
Jasper_lee	0:b16d94660a33	1131	/**************** Bit definition for GPIO_OTYPER register ***************/
Jasper_lee	0:b16d94660a33	1132	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1133	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1134	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1135	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1136	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1137	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1138	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1139	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1140	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1141	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1142	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1143	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1144	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1145	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1146	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1147	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1148
Jasper_lee	0:b16d94660a33	1149	/************** Bit definition for GPIO_OSPEEDR register ****************/
Jasper_lee	0:b16d94660a33	1150	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Jasper_lee	0:b16d94660a33	1151	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1152	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1153	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Jasper_lee	0:b16d94660a33	1154	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1155	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1156	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Jasper_lee	0:b16d94660a33	1157	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1158	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1159	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Jasper_lee	0:b16d94660a33	1160	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1161	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1162	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Jasper_lee	0:b16d94660a33	1163	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1164	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1165	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Jasper_lee	0:b16d94660a33	1166	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1167	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1168	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Jasper_lee	0:b16d94660a33	1169	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1170	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1171	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Jasper_lee	0:b16d94660a33	1172	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1173	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1174	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Jasper_lee	0:b16d94660a33	1175	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1176	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1177	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Jasper_lee	0:b16d94660a33	1178	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1179	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1180	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	1181	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1182	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1183	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Jasper_lee	0:b16d94660a33	1184	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1185	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1186	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Jasper_lee	0:b16d94660a33	1187	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	1188	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	1189	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Jasper_lee	0:b16d94660a33	1190	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	1191	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	1192	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Jasper_lee	0:b16d94660a33	1193	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Jasper_lee	0:b16d94660a33	1194	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Jasper_lee	0:b16d94660a33	1195	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Jasper_lee	0:b16d94660a33	1196	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Jasper_lee	0:b16d94660a33	1197	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	1198
Jasper_lee	0:b16d94660a33	1199	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1200	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Jasper_lee	0:b16d94660a33	1201	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Jasper_lee	0:b16d94660a33	1202	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Jasper_lee	0:b16d94660a33	1203	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Jasper_lee	0:b16d94660a33	1204	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Jasper_lee	0:b16d94660a33	1205	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Jasper_lee	0:b16d94660a33	1206	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Jasper_lee	0:b16d94660a33	1207	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Jasper_lee	0:b16d94660a33	1208	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Jasper_lee	0:b16d94660a33	1209	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Jasper_lee	0:b16d94660a33	1210	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Jasper_lee	0:b16d94660a33	1211	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Jasper_lee	0:b16d94660a33	1212	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Jasper_lee	0:b16d94660a33	1213	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Jasper_lee	0:b16d94660a33	1214	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Jasper_lee	0:b16d94660a33	1215	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Jasper_lee	0:b16d94660a33	1216	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Jasper_lee	0:b16d94660a33	1217	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Jasper_lee	0:b16d94660a33	1218	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Jasper_lee	0:b16d94660a33	1219	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Jasper_lee	0:b16d94660a33	1220	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Jasper_lee	0:b16d94660a33	1221	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Jasper_lee	0:b16d94660a33	1222	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Jasper_lee	0:b16d94660a33	1223	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Jasper_lee	0:b16d94660a33	1224	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Jasper_lee	0:b16d94660a33	1225	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Jasper_lee	0:b16d94660a33	1226	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Jasper_lee	0:b16d94660a33	1227	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Jasper_lee	0:b16d94660a33	1228	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Jasper_lee	0:b16d94660a33	1229	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Jasper_lee	0:b16d94660a33	1230	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Jasper_lee	0:b16d94660a33	1231	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Jasper_lee	0:b16d94660a33	1232	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Jasper_lee	0:b16d94660a33	1233	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Jasper_lee	0:b16d94660a33	1234	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Jasper_lee	0:b16d94660a33	1235	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Jasper_lee	0:b16d94660a33	1236	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Jasper_lee	0:b16d94660a33	1237	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Jasper_lee	0:b16d94660a33	1238	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Jasper_lee	0:b16d94660a33	1239	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Jasper_lee	0:b16d94660a33	1240	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Jasper_lee	0:b16d94660a33	1241	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Jasper_lee	0:b16d94660a33	1242	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Jasper_lee	0:b16d94660a33	1243	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Jasper_lee	0:b16d94660a33	1244	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Jasper_lee	0:b16d94660a33	1245	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Jasper_lee	0:b16d94660a33	1246	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Jasper_lee	0:b16d94660a33	1247	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Jasper_lee	0:b16d94660a33	1248
Jasper_lee	0:b16d94660a33	1249	/***************** Bit definition for GPIO_PUPDR register ****************/
Jasper_lee	0:b16d94660a33	1250	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Jasper_lee	0:b16d94660a33	1251	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1252	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1253	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Jasper_lee	0:b16d94660a33	1254	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1255	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1256	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Jasper_lee	0:b16d94660a33	1257	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1258	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1259	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Jasper_lee	0:b16d94660a33	1260	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1261	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1262	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Jasper_lee	0:b16d94660a33	1263	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1264	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1265	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Jasper_lee	0:b16d94660a33	1266	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1267	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1268	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Jasper_lee	0:b16d94660a33	1269	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1270	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1271	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Jasper_lee	0:b16d94660a33	1272	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1273	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1274	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Jasper_lee	0:b16d94660a33	1275	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1276	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1277	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Jasper_lee	0:b16d94660a33	1278	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1279	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1280	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	1281	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1282	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1283	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Jasper_lee	0:b16d94660a33	1284	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1285	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1286	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Jasper_lee	0:b16d94660a33	1287	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	1288	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	1289	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Jasper_lee	0:b16d94660a33	1290	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	1291	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	1292	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Jasper_lee	0:b16d94660a33	1293	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Jasper_lee	0:b16d94660a33	1294	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Jasper_lee	0:b16d94660a33	1295	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Jasper_lee	0:b16d94660a33	1296	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Jasper_lee	0:b16d94660a33	1297	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	1298
Jasper_lee	0:b16d94660a33	1299	/***************** Bit definition for GPIO_IDR register *****************/
Jasper_lee	0:b16d94660a33	1300	#define GPIO_IDR_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1301	#define GPIO_IDR_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1302	#define GPIO_IDR_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1303	#define GPIO_IDR_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1304	#define GPIO_IDR_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1305	#define GPIO_IDR_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1306	#define GPIO_IDR_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1307	#define GPIO_IDR_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1308	#define GPIO_IDR_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1309	#define GPIO_IDR_9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1310	#define GPIO_IDR_10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1311	#define GPIO_IDR_11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1312	#define GPIO_IDR_12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1313	#define GPIO_IDR_13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1314	#define GPIO_IDR_14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1315	#define GPIO_IDR_15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1316
Jasper_lee	0:b16d94660a33	1317	/**************** Bit definition for GPIO_ODR register ******************/
Jasper_lee	0:b16d94660a33	1318	#define GPIO_ODR_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1319	#define GPIO_ODR_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1320	#define GPIO_ODR_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1321	#define GPIO_ODR_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1322	#define GPIO_ODR_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1323	#define GPIO_ODR_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1324	#define GPIO_ODR_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1325	#define GPIO_ODR_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1326	#define GPIO_ODR_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1327	#define GPIO_ODR_9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1328	#define GPIO_ODR_10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1329	#define GPIO_ODR_11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1330	#define GPIO_ODR_12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1331	#define GPIO_ODR_13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1332	#define GPIO_ODR_14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1333	#define GPIO_ODR_15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1334
Jasper_lee	0:b16d94660a33	1335	/**************** Bit definition for GPIO_BSRR register ******************/
Jasper_lee	0:b16d94660a33	1336	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1337	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1338	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1339	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1340	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1341	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1342	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1343	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1344	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1345	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1346	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1347	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1348	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1349	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1350	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1351	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1352	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1353	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1354	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1355	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1356	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1357	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1358	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1359	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1360	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	1361	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	1362	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	1363	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	1364	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Jasper_lee	0:b16d94660a33	1365	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Jasper_lee	0:b16d94660a33	1366	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Jasper_lee	0:b16d94660a33	1367	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	1368
Jasper_lee	0:b16d94660a33	1369	/**************** Bit definition for GPIO_LCKR register ******************/
Jasper_lee	0:b16d94660a33	1370	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1371	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1372	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1373	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1374	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1375	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1376	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1377	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1378	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1379	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1380	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1381	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1382	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1383	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1384	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1385	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1386	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1387
Jasper_lee	0:b16d94660a33	1388	/**************** Bit definition for GPIO_AFRL register ******************/
Jasper_lee	0:b16d94660a33	1389	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	1390	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Jasper_lee	0:b16d94660a33	1391	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	1392	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Jasper_lee	0:b16d94660a33	1393	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	1394	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Jasper_lee	0:b16d94660a33	1395	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Jasper_lee	0:b16d94660a33	1396	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Jasper_lee	0:b16d94660a33	1397
Jasper_lee	0:b16d94660a33	1398	/**************** Bit definition for GPIO_AFRH register ******************/
Jasper_lee	0:b16d94660a33	1399	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	1400	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Jasper_lee	0:b16d94660a33	1401	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	1402	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Jasper_lee	0:b16d94660a33	1403	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	1404	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Jasper_lee	0:b16d94660a33	1405	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Jasper_lee	0:b16d94660a33	1406	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Jasper_lee	0:b16d94660a33	1407
Jasper_lee	0:b16d94660a33	1408	/**************** Bit definition for GPIO_BRR register *******************/
Jasper_lee	0:b16d94660a33	1409	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1410	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1411	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1412	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1413	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1414	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1415	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1416	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1417	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1418	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1419	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1420	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1421	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1422	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1423	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1424	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1425
Jasper_lee	0:b16d94660a33	1426	/******************************************************************************/
Jasper_lee	0:b16d94660a33	1427	/* */
Jasper_lee	0:b16d94660a33	1428	/* Inter-integrated Circuit Interface (I2C) */
Jasper_lee	0:b16d94660a33	1429	/* */
Jasper_lee	0:b16d94660a33	1430	/******************************************************************************/
Jasper_lee	0:b16d94660a33	1431
Jasper_lee	0:b16d94660a33	1432	/***************** Bit definition for I2C_CR1 register *****************/
Jasper_lee	0:b16d94660a33	1433	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
Jasper_lee	0:b16d94660a33	1434	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
Jasper_lee	0:b16d94660a33	1435	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
Jasper_lee	0:b16d94660a33	1436	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
Jasper_lee	0:b16d94660a33	1437	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
Jasper_lee	0:b16d94660a33	1438	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
Jasper_lee	0:b16d94660a33	1439	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
Jasper_lee	0:b16d94660a33	1440	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
Jasper_lee	0:b16d94660a33	1441	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
Jasper_lee	0:b16d94660a33	1442	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
Jasper_lee	0:b16d94660a33	1443	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
Jasper_lee	0:b16d94660a33	1444	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
Jasper_lee	0:b16d94660a33	1445	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
Jasper_lee	0:b16d94660a33	1446	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
Jasper_lee	0:b16d94660a33	1447	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
Jasper_lee	0:b16d94660a33	1448	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
Jasper_lee	0:b16d94660a33	1449	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
Jasper_lee	0:b16d94660a33	1450	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
Jasper_lee	0:b16d94660a33	1451	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
Jasper_lee	0:b16d94660a33	1452	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
Jasper_lee	0:b16d94660a33	1453	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
Jasper_lee	0:b16d94660a33	1454
Jasper_lee	0:b16d94660a33	1455	/**************** Bit definition for I2C_CR2 register ******************/
Jasper_lee	0:b16d94660a33	1456	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
Jasper_lee	0:b16d94660a33	1457	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
Jasper_lee	0:b16d94660a33	1458	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
Jasper_lee	0:b16d94660a33	1459	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
Jasper_lee	0:b16d94660a33	1460	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
Jasper_lee	0:b16d94660a33	1461	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
Jasper_lee	0:b16d94660a33	1462	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
Jasper_lee	0:b16d94660a33	1463	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
Jasper_lee	0:b16d94660a33	1464	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
Jasper_lee	0:b16d94660a33	1465	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
Jasper_lee	0:b16d94660a33	1466	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
Jasper_lee	0:b16d94660a33	1467
Jasper_lee	0:b16d94660a33	1468	/***************** Bit definition for I2C_OAR1 register ****************/
Jasper_lee	0:b16d94660a33	1469	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
Jasper_lee	0:b16d94660a33	1470	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
Jasper_lee	0:b16d94660a33	1471	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
Jasper_lee	0:b16d94660a33	1472
Jasper_lee	0:b16d94660a33	1473	/***************** Bit definition for I2C_OAR2 register ****************/
Jasper_lee	0:b16d94660a33	1474	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
Jasper_lee	0:b16d94660a33	1475	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
Jasper_lee	0:b16d94660a33	1476	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
Jasper_lee	0:b16d94660a33	1477
Jasper_lee	0:b16d94660a33	1478	/***************** Bit definition for I2C_TIMINGR register **************/
Jasper_lee	0:b16d94660a33	1479	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
Jasper_lee	0:b16d94660a33	1480	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
Jasper_lee	0:b16d94660a33	1481	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
Jasper_lee	0:b16d94660a33	1482	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
Jasper_lee	0:b16d94660a33	1483	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
Jasper_lee	0:b16d94660a33	1484
Jasper_lee	0:b16d94660a33	1485	/***************** Bit definition for I2C_TIMEOUTR register **************/
Jasper_lee	0:b16d94660a33	1486	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
Jasper_lee	0:b16d94660a33	1487	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
Jasper_lee	0:b16d94660a33	1488	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
Jasper_lee	0:b16d94660a33	1489	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
Jasper_lee	0:b16d94660a33	1490	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
Jasper_lee	0:b16d94660a33	1491
Jasper_lee	0:b16d94660a33	1492	/**************** Bit definition for I2C_ISR register ******************/
Jasper_lee	0:b16d94660a33	1493	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
Jasper_lee	0:b16d94660a33	1494	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
Jasper_lee	0:b16d94660a33	1495	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
Jasper_lee	0:b16d94660a33	1496	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
Jasper_lee	0:b16d94660a33	1497	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
Jasper_lee	0:b16d94660a33	1498	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
Jasper_lee	0:b16d94660a33	1499	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
Jasper_lee	0:b16d94660a33	1500	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
Jasper_lee	0:b16d94660a33	1501	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
Jasper_lee	0:b16d94660a33	1502	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
Jasper_lee	0:b16d94660a33	1503	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
Jasper_lee	0:b16d94660a33	1504	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
Jasper_lee	0:b16d94660a33	1505	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
Jasper_lee	0:b16d94660a33	1506	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
Jasper_lee	0:b16d94660a33	1507	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
Jasper_lee	0:b16d94660a33	1508	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
Jasper_lee	0:b16d94660a33	1509	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
Jasper_lee	0:b16d94660a33	1510
Jasper_lee	0:b16d94660a33	1511	/**************** Bit definition for I2C_ICR register ******************/
Jasper_lee	0:b16d94660a33	1512	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
Jasper_lee	0:b16d94660a33	1513	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
Jasper_lee	0:b16d94660a33	1514	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
Jasper_lee	0:b16d94660a33	1515	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
Jasper_lee	0:b16d94660a33	1516	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
Jasper_lee	0:b16d94660a33	1517	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
Jasper_lee	0:b16d94660a33	1518	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
Jasper_lee	0:b16d94660a33	1519	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
Jasper_lee	0:b16d94660a33	1520	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
Jasper_lee	0:b16d94660a33	1521
Jasper_lee	0:b16d94660a33	1522	/**************** Bit definition for I2C_PECR register *****************/
Jasper_lee	0:b16d94660a33	1523	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
Jasper_lee	0:b16d94660a33	1524
Jasper_lee	0:b16d94660a33	1525	/**************** Bit definition for I2C_RXDR register *******************/
Jasper_lee	0:b16d94660a33	1526	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
Jasper_lee	0:b16d94660a33	1527
Jasper_lee	0:b16d94660a33	1528	/**************** Bit definition for I2C_TXDR register *****************/
Jasper_lee	0:b16d94660a33	1529	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
Jasper_lee	0:b16d94660a33	1530
Jasper_lee	0:b16d94660a33	1531	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1532	/* */
Jasper_lee	0:b16d94660a33	1533	/* Independent WATCHDOG (IWDG) */
Jasper_lee	0:b16d94660a33	1534	/* */
Jasper_lee	0:b16d94660a33	1535	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1536	/***************** Bit definition for IWDG_KR register *****************/
Jasper_lee	0:b16d94660a33	1537	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
Jasper_lee	0:b16d94660a33	1538
Jasper_lee	0:b16d94660a33	1539	/***************** Bit definition for IWDG_PR register *****************/
Jasper_lee	0:b16d94660a33	1540	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
Jasper_lee	0:b16d94660a33	1541	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1542	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1543	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1544
Jasper_lee	0:b16d94660a33	1545	/***************** Bit definition for IWDG_RLR register ****************/
Jasper_lee	0:b16d94660a33	1546	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
Jasper_lee	0:b16d94660a33	1547
Jasper_lee	0:b16d94660a33	1548	/***************** Bit definition for IWDG_SR register *****************/
Jasper_lee	0:b16d94660a33	1549	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
Jasper_lee	0:b16d94660a33	1550	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
Jasper_lee	0:b16d94660a33	1551	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
Jasper_lee	0:b16d94660a33	1552
Jasper_lee	0:b16d94660a33	1553	/***************** Bit definition for IWDG_KR register *****************/
Jasper_lee	0:b16d94660a33	1554	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
Jasper_lee	0:b16d94660a33	1555
Jasper_lee	0:b16d94660a33	1556	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1557	/* */
Jasper_lee	0:b16d94660a33	1558	/* Power Control (PWR) */
Jasper_lee	0:b16d94660a33	1559	/* */
Jasper_lee	0:b16d94660a33	1560	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1561
Jasper_lee	0:b16d94660a33	1562	/****************** Bit definition for PWR_CR register *****************/
Jasper_lee	0:b16d94660a33	1563	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
Jasper_lee	0:b16d94660a33	1564	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
Jasper_lee	0:b16d94660a33	1565	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
Jasper_lee	0:b16d94660a33	1566	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
Jasper_lee	0:b16d94660a33	1567	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
Jasper_lee	0:b16d94660a33	1568
Jasper_lee	0:b16d94660a33	1569	/***************** Bit definition for PWR_CSR register *****************/
Jasper_lee	0:b16d94660a33	1570	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
Jasper_lee	0:b16d94660a33	1571	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
Jasper_lee	0:b16d94660a33	1572	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
Jasper_lee	0:b16d94660a33	1573	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
Jasper_lee	0:b16d94660a33	1574
Jasper_lee	0:b16d94660a33	1575	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1576	/* */
Jasper_lee	0:b16d94660a33	1577	/* Reset and Clock Control */
Jasper_lee	0:b16d94660a33	1578	/* */
Jasper_lee	0:b16d94660a33	1579	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1580
Jasper_lee	0:b16d94660a33	1581	/****************** Bit definition for RCC_CR register *****************/
Jasper_lee	0:b16d94660a33	1582	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
Jasper_lee	0:b16d94660a33	1583	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
Jasper_lee	0:b16d94660a33	1584
Jasper_lee	0:b16d94660a33	1585	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
Jasper_lee	0:b16d94660a33	1586	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	1587	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	1588	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	1589	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	1590	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	1591
Jasper_lee	0:b16d94660a33	1592	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
Jasper_lee	0:b16d94660a33	1593	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	1594	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	1595	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	1596	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	1597	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	1598	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
Jasper_lee	0:b16d94660a33	1599	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
Jasper_lee	0:b16d94660a33	1600	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
Jasper_lee	0:b16d94660a33	1601
Jasper_lee	0:b16d94660a33	1602	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
Jasper_lee	0:b16d94660a33	1603	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
Jasper_lee	0:b16d94660a33	1604	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
Jasper_lee	0:b16d94660a33	1605	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
Jasper_lee	0:b16d94660a33	1606	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
Jasper_lee	0:b16d94660a33	1607	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
Jasper_lee	0:b16d94660a33	1608
Jasper_lee	0:b16d94660a33	1609	/****************** Bit definition for RCC_CFGR register ***************/
Jasper_lee	0:b16d94660a33	1610	/!< SW configuration /
Jasper_lee	0:b16d94660a33	1611	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
Jasper_lee	0:b16d94660a33	1612	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1613	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1614
Jasper_lee	0:b16d94660a33	1615	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
Jasper_lee	0:b16d94660a33	1616	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
Jasper_lee	0:b16d94660a33	1617	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
Jasper_lee	0:b16d94660a33	1618
Jasper_lee	0:b16d94660a33	1619	/!< SWS configuration /
Jasper_lee	0:b16d94660a33	1620	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
Jasper_lee	0:b16d94660a33	1621	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1622	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1623
Jasper_lee	0:b16d94660a33	1624	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
Jasper_lee	0:b16d94660a33	1625	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
Jasper_lee	0:b16d94660a33	1626	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
Jasper_lee	0:b16d94660a33	1627
Jasper_lee	0:b16d94660a33	1628	/!< HPRE configuration /
Jasper_lee	0:b16d94660a33	1629	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
Jasper_lee	0:b16d94660a33	1630	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1631	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1632	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1633	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	1634
Jasper_lee	0:b16d94660a33	1635	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
Jasper_lee	0:b16d94660a33	1636	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
Jasper_lee	0:b16d94660a33	1637	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
Jasper_lee	0:b16d94660a33	1638	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
Jasper_lee	0:b16d94660a33	1639	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
Jasper_lee	0:b16d94660a33	1640	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
Jasper_lee	0:b16d94660a33	1641	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
Jasper_lee	0:b16d94660a33	1642	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
Jasper_lee	0:b16d94660a33	1643	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
Jasper_lee	0:b16d94660a33	1644
Jasper_lee	0:b16d94660a33	1645	/!< PPRE configuration /
Jasper_lee	0:b16d94660a33	1646	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
Jasper_lee	0:b16d94660a33	1647	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1648	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1649	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1650
Jasper_lee	0:b16d94660a33	1651	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Jasper_lee	0:b16d94660a33	1652	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
Jasper_lee	0:b16d94660a33	1653	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
Jasper_lee	0:b16d94660a33	1654	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
Jasper_lee	0:b16d94660a33	1655	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
Jasper_lee	0:b16d94660a33	1656
Jasper_lee	0:b16d94660a33	1657	/!< ADCPPRE configuration /
Jasper_lee	0:b16d94660a33	1658	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
Jasper_lee	0:b16d94660a33	1659
Jasper_lee	0:b16d94660a33	1660	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
Jasper_lee	0:b16d94660a33	1661	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
Jasper_lee	0:b16d94660a33	1662
Jasper_lee	0:b16d94660a33	1663	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
Jasper_lee	0:b16d94660a33	1664	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Jasper_lee	0:b16d94660a33	1665	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
Jasper_lee	0:b16d94660a33	1666
Jasper_lee	0:b16d94660a33	1667	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
Jasper_lee	0:b16d94660a33	1668	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
Jasper_lee	0:b16d94660a33	1669	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
Jasper_lee	0:b16d94660a33	1670
Jasper_lee	0:b16d94660a33	1671	/!< PLLMUL configuration /
Jasper_lee	0:b16d94660a33	1672	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
Jasper_lee	0:b16d94660a33	1673	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1674	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1675	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1676	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	1677
Jasper_lee	0:b16d94660a33	1678	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
Jasper_lee	0:b16d94660a33	1679	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
Jasper_lee	0:b16d94660a33	1680	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
Jasper_lee	0:b16d94660a33	1681	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
Jasper_lee	0:b16d94660a33	1682	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
Jasper_lee	0:b16d94660a33	1683	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
Jasper_lee	0:b16d94660a33	1684	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
Jasper_lee	0:b16d94660a33	1685	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
Jasper_lee	0:b16d94660a33	1686	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
Jasper_lee	0:b16d94660a33	1687	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
Jasper_lee	0:b16d94660a33	1688	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
Jasper_lee	0:b16d94660a33	1689	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
Jasper_lee	0:b16d94660a33	1690	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
Jasper_lee	0:b16d94660a33	1691	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
Jasper_lee	0:b16d94660a33	1692	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
Jasper_lee	0:b16d94660a33	1693
Jasper_lee	0:b16d94660a33	1694	/!< MCO configuration /
Jasper_lee	0:b16d94660a33	1695	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
Jasper_lee	0:b16d94660a33	1696	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1697	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1698	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1699	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	1700
Jasper_lee	0:b16d94660a33	1701	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Jasper_lee	0:b16d94660a33	1702	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1703	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1704	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1705	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1706	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1707	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
Jasper_lee	0:b16d94660a33	1708	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
Jasper_lee	0:b16d94660a33	1709
Jasper_lee	0:b16d94660a33	1710	/!<*************** Bit definition for RCC_CIR register ***************/
Jasper_lee	0:b16d94660a33	1711	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1712	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1713	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1714	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1715	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1716	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
Jasper_lee	0:b16d94660a33	1717	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
Jasper_lee	0:b16d94660a33	1718	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1719	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1720	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1721	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1722	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1723	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
Jasper_lee	0:b16d94660a33	1724	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1725	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1726	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1727	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1728	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1729	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
Jasper_lee	0:b16d94660a33	1730	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
Jasper_lee	0:b16d94660a33	1731
Jasper_lee	0:b16d94660a33	1732	/*************** Bit definition for RCC_APB2RSTR register **************/
Jasper_lee	0:b16d94660a33	1733	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
Jasper_lee	0:b16d94660a33	1734	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
Jasper_lee	0:b16d94660a33	1735	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
Jasper_lee	0:b16d94660a33	1736	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
Jasper_lee	0:b16d94660a33	1737	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
Jasper_lee	0:b16d94660a33	1738	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
Jasper_lee	0:b16d94660a33	1739	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
Jasper_lee	0:b16d94660a33	1740	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
Jasper_lee	0:b16d94660a33	1741	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
Jasper_lee	0:b16d94660a33	1742
Jasper_lee	0:b16d94660a33	1743	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
Jasper_lee	0:b16d94660a33	1744	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Jasper_lee	0:b16d94660a33	1745
Jasper_lee	0:b16d94660a33	1746	/*************** Bit definition for RCC_APB1RSTR register **************/
Jasper_lee	0:b16d94660a33	1747	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
Jasper_lee	0:b16d94660a33	1748	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
Jasper_lee	0:b16d94660a33	1749	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
Jasper_lee	0:b16d94660a33	1750	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
Jasper_lee	0:b16d94660a33	1751	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
Jasper_lee	0:b16d94660a33	1752	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
Jasper_lee	0:b16d94660a33	1753	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
Jasper_lee	0:b16d94660a33	1754	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
Jasper_lee	0:b16d94660a33	1755	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
Jasper_lee	0:b16d94660a33	1756
Jasper_lee	0:b16d94660a33	1757	/**************** Bit definition for RCC_AHBENR register ***************/
Jasper_lee	0:b16d94660a33	1758	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
Jasper_lee	0:b16d94660a33	1759	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
Jasper_lee	0:b16d94660a33	1760	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
Jasper_lee	0:b16d94660a33	1761	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
Jasper_lee	0:b16d94660a33	1762	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
Jasper_lee	0:b16d94660a33	1763	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
Jasper_lee	0:b16d94660a33	1764	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
Jasper_lee	0:b16d94660a33	1765	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
Jasper_lee	0:b16d94660a33	1766	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
Jasper_lee	0:b16d94660a33	1767
Jasper_lee	0:b16d94660a33	1768	/* Old Bit definition maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1769	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
Jasper_lee	0:b16d94660a33	1770	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
Jasper_lee	0:b16d94660a33	1771
Jasper_lee	0:b16d94660a33	1772	/*************** Bit definition for RCC_APB2ENR register ***************/
Jasper_lee	0:b16d94660a33	1773	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
Jasper_lee	0:b16d94660a33	1774	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
Jasper_lee	0:b16d94660a33	1775	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
Jasper_lee	0:b16d94660a33	1776	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
Jasper_lee	0:b16d94660a33	1777	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
Jasper_lee	0:b16d94660a33	1778	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
Jasper_lee	0:b16d94660a33	1779	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
Jasper_lee	0:b16d94660a33	1780	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
Jasper_lee	0:b16d94660a33	1781	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
Jasper_lee	0:b16d94660a33	1782
Jasper_lee	0:b16d94660a33	1783	/* Old Bit definition maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1784	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
Jasper_lee	0:b16d94660a33	1785	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
Jasper_lee	0:b16d94660a33	1786
Jasper_lee	0:b16d94660a33	1787	/*************** Bit definition for RCC_APB1ENR register ***************/
Jasper_lee	0:b16d94660a33	1788	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
Jasper_lee	0:b16d94660a33	1789	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
Jasper_lee	0:b16d94660a33	1790	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
Jasper_lee	0:b16d94660a33	1791	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
Jasper_lee	0:b16d94660a33	1792	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
Jasper_lee	0:b16d94660a33	1793	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
Jasper_lee	0:b16d94660a33	1794	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
Jasper_lee	0:b16d94660a33	1795	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
Jasper_lee	0:b16d94660a33	1796	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
Jasper_lee	0:b16d94660a33	1797
Jasper_lee	0:b16d94660a33	1798	/***************** Bit definition for RCC_BDCR register ****************/
Jasper_lee	0:b16d94660a33	1799	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
Jasper_lee	0:b16d94660a33	1800	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
Jasper_lee	0:b16d94660a33	1801	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
Jasper_lee	0:b16d94660a33	1802
Jasper_lee	0:b16d94660a33	1803	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
Jasper_lee	0:b16d94660a33	1804	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1805	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1806
Jasper_lee	0:b16d94660a33	1807	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
Jasper_lee	0:b16d94660a33	1808	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1809	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1810
Jasper_lee	0:b16d94660a33	1811	/!< RTC configuration /
Jasper_lee	0:b16d94660a33	1812	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Jasper_lee	0:b16d94660a33	1813	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
Jasper_lee	0:b16d94660a33	1814	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
Jasper_lee	0:b16d94660a33	1815	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
Jasper_lee	0:b16d94660a33	1816
Jasper_lee	0:b16d94660a33	1817	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
Jasper_lee	0:b16d94660a33	1818	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
Jasper_lee	0:b16d94660a33	1819
Jasper_lee	0:b16d94660a33	1820	/***************** Bit definition for RCC_CSR register *****************/
Jasper_lee	0:b16d94660a33	1821	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
Jasper_lee	0:b16d94660a33	1822	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
Jasper_lee	0:b16d94660a33	1823	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
Jasper_lee	0:b16d94660a33	1824	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
Jasper_lee	0:b16d94660a33	1825	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
Jasper_lee	0:b16d94660a33	1826	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
Jasper_lee	0:b16d94660a33	1827	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
Jasper_lee	0:b16d94660a33	1828	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
Jasper_lee	0:b16d94660a33	1829	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
Jasper_lee	0:b16d94660a33	1830	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
Jasper_lee	0:b16d94660a33	1831	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
Jasper_lee	0:b16d94660a33	1832
Jasper_lee	0:b16d94660a33	1833	/* Old Bit definition maintained for legacy purpose */
Jasper_lee	0:b16d94660a33	1834	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
Jasper_lee	0:b16d94660a33	1835
Jasper_lee	0:b16d94660a33	1836	/***************** Bit definition for RCC_AHBRSTR register *************/
Jasper_lee	0:b16d94660a33	1837	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
Jasper_lee	0:b16d94660a33	1838	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
Jasper_lee	0:b16d94660a33	1839	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
Jasper_lee	0:b16d94660a33	1840	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
Jasper_lee	0:b16d94660a33	1841	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
Jasper_lee	0:b16d94660a33	1842
Jasper_lee	0:b16d94660a33	1843	/***************** Bit definition for RCC_CFGR2 register ***************/
Jasper_lee	0:b16d94660a33	1844	/!< PREDIV configuration /
Jasper_lee	0:b16d94660a33	1845	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
Jasper_lee	0:b16d94660a33	1846	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1847	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1848	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	1849	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	1850
Jasper_lee	0:b16d94660a33	1851	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
Jasper_lee	0:b16d94660a33	1852	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
Jasper_lee	0:b16d94660a33	1853	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
Jasper_lee	0:b16d94660a33	1854	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
Jasper_lee	0:b16d94660a33	1855	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
Jasper_lee	0:b16d94660a33	1856	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
Jasper_lee	0:b16d94660a33	1857	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
Jasper_lee	0:b16d94660a33	1858	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
Jasper_lee	0:b16d94660a33	1859	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
Jasper_lee	0:b16d94660a33	1860	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
Jasper_lee	0:b16d94660a33	1861	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
Jasper_lee	0:b16d94660a33	1862	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
Jasper_lee	0:b16d94660a33	1863	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
Jasper_lee	0:b16d94660a33	1864	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
Jasper_lee	0:b16d94660a33	1865	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
Jasper_lee	0:b16d94660a33	1866	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
Jasper_lee	0:b16d94660a33	1867
Jasper_lee	0:b16d94660a33	1868	/***************** Bit definition for RCC_CFGR3 register ***************/
Jasper_lee	0:b16d94660a33	1869	/!< USART1 Clock source selection /
Jasper_lee	0:b16d94660a33	1870	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
Jasper_lee	0:b16d94660a33	1871	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1872	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1873
Jasper_lee	0:b16d94660a33	1874	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
Jasper_lee	0:b16d94660a33	1875	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
Jasper_lee	0:b16d94660a33	1876	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
Jasper_lee	0:b16d94660a33	1877	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
Jasper_lee	0:b16d94660a33	1878
Jasper_lee	0:b16d94660a33	1879	/!< I2C1 Clock source selection /
Jasper_lee	0:b16d94660a33	1880	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
Jasper_lee	0:b16d94660a33	1881
Jasper_lee	0:b16d94660a33	1882	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
Jasper_lee	0:b16d94660a33	1883	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
Jasper_lee	0:b16d94660a33	1884
Jasper_lee	0:b16d94660a33	1885	/!< USART2 Clock source selection /
Jasper_lee	0:b16d94660a33	1886	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
Jasper_lee	0:b16d94660a33	1887	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	1888	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	1889
Jasper_lee	0:b16d94660a33	1890	#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART2 clock source /
Jasper_lee	0:b16d94660a33	1891	#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /!< System clock selected as USART2 clock source /
Jasper_lee	0:b16d94660a33	1892	#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /!< LSE oscillator clock used as USART2 clock source /
Jasper_lee	0:b16d94660a33	1893	#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /!< HSI oscillator clock used as USART2 clock source /
Jasper_lee	0:b16d94660a33	1894
Jasper_lee	0:b16d94660a33	1895	/***************** Bit definition for RCC_CR2 register *****************/
Jasper_lee	0:b16d94660a33	1896	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
Jasper_lee	0:b16d94660a33	1897	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
Jasper_lee	0:b16d94660a33	1898	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
Jasper_lee	0:b16d94660a33	1899	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
Jasper_lee	0:b16d94660a33	1900	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
Jasper_lee	0:b16d94660a33	1901
Jasper_lee	0:b16d94660a33	1902	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1903	/* */
Jasper_lee	0:b16d94660a33	1904	/* Real-Time Clock (RTC) */
Jasper_lee	0:b16d94660a33	1905	/* */
Jasper_lee	0:b16d94660a33	1906	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	1907	/****************** Bits definition for RTC_TR register ****************/
Jasper_lee	0:b16d94660a33	1908	#define RTC_TR_PM ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1909	#define RTC_TR_HT ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	1910	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1911	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1912	#define RTC_TR_HU ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	1913	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1914	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1915	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1916	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1917	#define RTC_TR_MNT ((uint32_t)0x00007000)
Jasper_lee	0:b16d94660a33	1918	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1919	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1920	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1921	#define RTC_TR_MNU ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	1922	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1923	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1924	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1925	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1926	#define RTC_TR_ST ((uint32_t)0x00000070)
Jasper_lee	0:b16d94660a33	1927	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1928	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1929	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1930	#define RTC_TR_SU ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	1931	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1932	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1933	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1934	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1935
Jasper_lee	0:b16d94660a33	1936	/****************** Bits definition for RTC_DR register ****************/
Jasper_lee	0:b16d94660a33	1937	#define RTC_DR_YT ((uint32_t)0x00F00000)
Jasper_lee	0:b16d94660a33	1938	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1939	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1940	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1941	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1942	#define RTC_DR_YU ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	1943	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1944	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1945	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1946	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1947	#define RTC_DR_WDU ((uint32_t)0x0000E000)
Jasper_lee	0:b16d94660a33	1948	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1949	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1950	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1951	#define RTC_DR_MT ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1952	#define RTC_DR_MU ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	1953	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1954	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	1955	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	1956	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1957	#define RTC_DR_DT ((uint32_t)0x00000030)
Jasper_lee	0:b16d94660a33	1958	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1959	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1960	#define RTC_DR_DU ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	1961	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1962	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	1963	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	1964	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1965
Jasper_lee	0:b16d94660a33	1966	/****************** Bits definition for RTC_CR register ****************/
Jasper_lee	0:b16d94660a33	1967	#define RTC_CR_COE ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	1968	#define RTC_CR_OSEL ((uint32_t)0x00600000)
Jasper_lee	0:b16d94660a33	1969	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	1970	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	1971	#define RTC_CR_POL ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	1972	#define RTC_CR_COSEL ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	1973	#define RTC_CR_BCK ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	1974	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	1975	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1976	#define RTC_CR_TSIE ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	1977	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1978	#define RTC_CR_TSE ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1979	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1980	#define RTC_CR_FMT ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1981	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1982	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1983	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1984
Jasper_lee	0:b16d94660a33	1985	/****************** Bits definition for RTC_ISR register ***************/
Jasper_lee	0:b16d94660a33	1986	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	1987	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	1988	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	1989	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	1990	#define RTC_ISR_TSF ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	1991	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	1992	#define RTC_ISR_INIT ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	1993	#define RTC_ISR_INITF ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	1994	#define RTC_ISR_RSF ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	1995	#define RTC_ISR_INITS ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	1996	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	1997	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	1998
Jasper_lee	0:b16d94660a33	1999	/****************** Bits definition for RTC_PRER register **************/
Jasper_lee	0:b16d94660a33	2000	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Jasper_lee	0:b16d94660a33	2001	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Jasper_lee	0:b16d94660a33	2002
Jasper_lee	0:b16d94660a33	2003	/****************** Bits definition for RTC_ALRMAR register ************/
Jasper_lee	0:b16d94660a33	2004	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	2005	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Jasper_lee	0:b16d94660a33	2006	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Jasper_lee	0:b16d94660a33	2007	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Jasper_lee	0:b16d94660a33	2008	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Jasper_lee	0:b16d94660a33	2009	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Jasper_lee	0:b16d94660a33	2010	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	2011	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	2012	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	2013	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	2014	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Jasper_lee	0:b16d94660a33	2015	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	2016	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	2017	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	2018	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	2019	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	2020	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	2021	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	2022	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	2023	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	2024	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	2025	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Jasper_lee	0:b16d94660a33	2026	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	2027	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	2028	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	2029	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	2030	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	2031	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	2032	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	2033	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	2034	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	2035	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Jasper_lee	0:b16d94660a33	2036	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	2037	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	2038	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	2039	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	2040	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	2041	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	2042	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	2043	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	2044
Jasper_lee	0:b16d94660a33	2045	/****************** Bits definition for RTC_WPR register ***************/
Jasper_lee	0:b16d94660a33	2046	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
Jasper_lee	0:b16d94660a33	2047
Jasper_lee	0:b16d94660a33	2048	/****************** Bits definition for RTC_SSR register ***************/
Jasper_lee	0:b16d94660a33	2049	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Jasper_lee	0:b16d94660a33	2050
Jasper_lee	0:b16d94660a33	2051	/****************** Bits definition for RTC_SHIFTR register ************/
Jasper_lee	0:b16d94660a33	2052	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Jasper_lee	0:b16d94660a33	2053	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Jasper_lee	0:b16d94660a33	2054
Jasper_lee	0:b16d94660a33	2055	/****************** Bits definition for RTC_TSTR register **************/
Jasper_lee	0:b16d94660a33	2056	#define RTC_TSTR_PM ((uint32_t)0x00400000)
Jasper_lee	0:b16d94660a33	2057	#define RTC_TSTR_HT ((uint32_t)0x00300000)
Jasper_lee	0:b16d94660a33	2058	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Jasper_lee	0:b16d94660a33	2059	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Jasper_lee	0:b16d94660a33	2060	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
Jasper_lee	0:b16d94660a33	2061	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Jasper_lee	0:b16d94660a33	2062	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Jasper_lee	0:b16d94660a33	2063	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	2064	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Jasper_lee	0:b16d94660a33	2065	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
Jasper_lee	0:b16d94660a33	2066	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	2067	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	2068	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	2069	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	2070	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	2071	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	2072	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	2073	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	2074	#define RTC_TSTR_ST ((uint32_t)0x00000070)
Jasper_lee	0:b16d94660a33	2075	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	2076	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	2077	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	2078	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	2079	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	2080	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	2081	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	2082	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	2083
Jasper_lee	0:b16d94660a33	2084	/****************** Bits definition for RTC_TSDR register **************/
Jasper_lee	0:b16d94660a33	2085	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Jasper_lee	0:b16d94660a33	2086	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	2087	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	2088	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	2089	#define RTC_TSDR_MT ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	2090	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
Jasper_lee	0:b16d94660a33	2091	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	2092	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	2093	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	2094	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	2095	#define RTC_TSDR_DT ((uint32_t)0x00000030)
Jasper_lee	0:b16d94660a33	2096	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	2097	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	2098	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
Jasper_lee	0:b16d94660a33	2099	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	2100	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	2101	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	2102	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	2103
Jasper_lee	0:b16d94660a33	2104	/****************** Bits definition for RTC_TSSSR register *************/
Jasper_lee	0:b16d94660a33	2105	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Jasper_lee	0:b16d94660a33	2106
Jasper_lee	0:b16d94660a33	2107	/****************** Bits definition for RTC_CALR register **************/
Jasper_lee	0:b16d94660a33	2108	#define RTC_CALR_CALP ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	2109	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	2110	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	2111	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
Jasper_lee	0:b16d94660a33	2112	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	2113	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	2114	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	2115	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	2116	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	2117	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Jasper_lee	0:b16d94660a33	2118	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Jasper_lee	0:b16d94660a33	2119	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	2120	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	2121
Jasper_lee	0:b16d94660a33	2122	/****************** Bits definition for RTC_TAFCR register *************/
Jasper_lee	0:b16d94660a33	2123	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Jasper_lee	0:b16d94660a33	2124	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Jasper_lee	0:b16d94660a33	2125	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Jasper_lee	0:b16d94660a33	2126	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Jasper_lee	0:b16d94660a33	2127	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Jasper_lee	0:b16d94660a33	2128	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Jasper_lee	0:b16d94660a33	2129	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Jasper_lee	0:b16d94660a33	2130	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Jasper_lee	0:b16d94660a33	2131	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Jasper_lee	0:b16d94660a33	2132	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Jasper_lee	0:b16d94660a33	2133	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Jasper_lee	0:b16d94660a33	2134	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Jasper_lee	0:b16d94660a33	2135	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Jasper_lee	0:b16d94660a33	2136	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Jasper_lee	0:b16d94660a33	2137	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Jasper_lee	0:b16d94660a33	2138	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Jasper_lee	0:b16d94660a33	2139	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Jasper_lee	0:b16d94660a33	2140	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Jasper_lee	0:b16d94660a33	2141
Jasper_lee	0:b16d94660a33	2142	/****************** Bits definition for RTC_ALRMASSR register **********/
Jasper_lee	0:b16d94660a33	2143	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Jasper_lee	0:b16d94660a33	2144	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Jasper_lee	0:b16d94660a33	2145	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Jasper_lee	0:b16d94660a33	2146	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Jasper_lee	0:b16d94660a33	2147	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Jasper_lee	0:b16d94660a33	2148	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Jasper_lee	0:b16d94660a33	2149
Jasper_lee	0:b16d94660a33	2150	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2151	/* */
Jasper_lee	0:b16d94660a33	2152	/* Serial Peripheral Interface (SPI) */
Jasper_lee	0:b16d94660a33	2153	/* */
Jasper_lee	0:b16d94660a33	2154	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2155	/***************** Bit definition for SPI_CR1 register *****************/
Jasper_lee	0:b16d94660a33	2156	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
Jasper_lee	0:b16d94660a33	2157	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
Jasper_lee	0:b16d94660a33	2158	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
Jasper_lee	0:b16d94660a33	2159	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
Jasper_lee	0:b16d94660a33	2160	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2161	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2162	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	2163	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
Jasper_lee	0:b16d94660a33	2164	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
Jasper_lee	0:b16d94660a33	2165	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
Jasper_lee	0:b16d94660a33	2166	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
Jasper_lee	0:b16d94660a33	2167	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
Jasper_lee	0:b16d94660a33	2168	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
Jasper_lee	0:b16d94660a33	2169	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
Jasper_lee	0:b16d94660a33	2170	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
Jasper_lee	0:b16d94660a33	2171	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
Jasper_lee	0:b16d94660a33	2172	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
Jasper_lee	0:b16d94660a33	2173
Jasper_lee	0:b16d94660a33	2174	/***************** Bit definition for SPI_CR2 register *****************/
Jasper_lee	0:b16d94660a33	2175	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
Jasper_lee	0:b16d94660a33	2176	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
Jasper_lee	0:b16d94660a33	2177	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
Jasper_lee	0:b16d94660a33	2178	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
Jasper_lee	0:b16d94660a33	2179	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
Jasper_lee	0:b16d94660a33	2180	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
Jasper_lee	0:b16d94660a33	2181	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
Jasper_lee	0:b16d94660a33	2182	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
Jasper_lee	0:b16d94660a33	2183	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
Jasper_lee	0:b16d94660a33	2184	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2185	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2186	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	2187	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	2188	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
Jasper_lee	0:b16d94660a33	2189	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
Jasper_lee	0:b16d94660a33	2190	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
Jasper_lee	0:b16d94660a33	2191
Jasper_lee	0:b16d94660a33	2192	/****************** Bit definition for SPI_SR register *****************/
Jasper_lee	0:b16d94660a33	2193	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
Jasper_lee	0:b16d94660a33	2194	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
Jasper_lee	0:b16d94660a33	2195	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
Jasper_lee	0:b16d94660a33	2196	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
Jasper_lee	0:b16d94660a33	2197	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
Jasper_lee	0:b16d94660a33	2198	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
Jasper_lee	0:b16d94660a33	2199	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
Jasper_lee	0:b16d94660a33	2200	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
Jasper_lee	0:b16d94660a33	2201	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
Jasper_lee	0:b16d94660a33	2202	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
Jasper_lee	0:b16d94660a33	2203	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2204	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2205	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
Jasper_lee	0:b16d94660a33	2206	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2207	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2208
Jasper_lee	0:b16d94660a33	2209	/****************** Bit definition for SPI_DR register *****************/
Jasper_lee	0:b16d94660a33	2210	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
Jasper_lee	0:b16d94660a33	2211
Jasper_lee	0:b16d94660a33	2212	/***************** Bit definition for SPI_CRCPR register ***************/
Jasper_lee	0:b16d94660a33	2213	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
Jasper_lee	0:b16d94660a33	2214
Jasper_lee	0:b16d94660a33	2215	/**************** Bit definition for SPI_RXCRCR register ***************/
Jasper_lee	0:b16d94660a33	2216	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
Jasper_lee	0:b16d94660a33	2217
Jasper_lee	0:b16d94660a33	2218	/**************** Bit definition for SPI_TXCRCR register ***************/
Jasper_lee	0:b16d94660a33	2219	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
Jasper_lee	0:b16d94660a33	2220
Jasper_lee	0:b16d94660a33	2221	/**************** Bit definition for SPI_I2SCFGR register **************/
Jasper_lee	0:b16d94660a33	2222	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
Jasper_lee	0:b16d94660a33	2223	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
Jasper_lee	0:b16d94660a33	2224	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2225	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2226	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
Jasper_lee	0:b16d94660a33	2227	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
Jasper_lee	0:b16d94660a33	2228	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2229	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2230	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
Jasper_lee	0:b16d94660a33	2231	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
Jasper_lee	0:b16d94660a33	2232	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2233	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2234	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
Jasper_lee	0:b16d94660a33	2235	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
Jasper_lee	0:b16d94660a33	2236
Jasper_lee	0:b16d94660a33	2237	/**************** Bit definition for SPI_I2SPR register ****************/
Jasper_lee	0:b16d94660a33	2238	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
Jasper_lee	0:b16d94660a33	2239	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
Jasper_lee	0:b16d94660a33	2240	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
Jasper_lee	0:b16d94660a33	2241
Jasper_lee	0:b16d94660a33	2242	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2243	/* */
Jasper_lee	0:b16d94660a33	2244	/* System Configuration (SYSCFG) */
Jasper_lee	0:b16d94660a33	2245	/* */
Jasper_lee	0:b16d94660a33	2246	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2247	/*************** Bit definition for SYSCFG_CFGR1 register **************/
Jasper_lee	0:b16d94660a33	2248	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
Jasper_lee	0:b16d94660a33	2249	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
Jasper_lee	0:b16d94660a33	2250	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
Jasper_lee	0:b16d94660a33	2251
Jasper_lee	0:b16d94660a33	2252	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /!< DMA remap mask /
Jasper_lee	0:b16d94660a33	2253	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
Jasper_lee	0:b16d94660a33	2254	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
Jasper_lee	0:b16d94660a33	2255	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
Jasper_lee	0:b16d94660a33	2256	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
Jasper_lee	0:b16d94660a33	2257	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
Jasper_lee	0:b16d94660a33	2258
Jasper_lee	0:b16d94660a33	2259	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
Jasper_lee	0:b16d94660a33	2260	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
Jasper_lee	0:b16d94660a33	2261	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
Jasper_lee	0:b16d94660a33	2262	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
Jasper_lee	0:b16d94660a33	2263
Jasper_lee	0:b16d94660a33	2264	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
Jasper_lee	0:b16d94660a33	2265	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
Jasper_lee	0:b16d94660a33	2266	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
Jasper_lee	0:b16d94660a33	2267	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
Jasper_lee	0:b16d94660a33	2268	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
Jasper_lee	0:b16d94660a33	2269
Jasper_lee	0:b16d94660a33	2270	/**
Jasper_lee	0:b16d94660a33	2271	* @brief EXTI0 configuration
Jasper_lee	0:b16d94660a33	2272	*/
Jasper_lee	0:b16d94660a33	2273	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
Jasper_lee	0:b16d94660a33	2274	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
Jasper_lee	0:b16d94660a33	2275	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
Jasper_lee	0:b16d94660a33	2276	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
Jasper_lee	0:b16d94660a33	2277	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
Jasper_lee	0:b16d94660a33	2278
Jasper_lee	0:b16d94660a33	2279	/**
Jasper_lee	0:b16d94660a33	2280	* @brief EXTI1 configuration
Jasper_lee	0:b16d94660a33	2281	*/
Jasper_lee	0:b16d94660a33	2282	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
Jasper_lee	0:b16d94660a33	2283	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
Jasper_lee	0:b16d94660a33	2284	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
Jasper_lee	0:b16d94660a33	2285	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
Jasper_lee	0:b16d94660a33	2286	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
Jasper_lee	0:b16d94660a33	2287
Jasper_lee	0:b16d94660a33	2288	/**
Jasper_lee	0:b16d94660a33	2289	* @brief EXTI2 configuration
Jasper_lee	0:b16d94660a33	2290	*/
Jasper_lee	0:b16d94660a33	2291	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
Jasper_lee	0:b16d94660a33	2292	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
Jasper_lee	0:b16d94660a33	2293	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
Jasper_lee	0:b16d94660a33	2294	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
Jasper_lee	0:b16d94660a33	2295	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
Jasper_lee	0:b16d94660a33	2296
Jasper_lee	0:b16d94660a33	2297	/**
Jasper_lee	0:b16d94660a33	2298	* @brief EXTI3 configuration
Jasper_lee	0:b16d94660a33	2299	*/
Jasper_lee	0:b16d94660a33	2300	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
Jasper_lee	0:b16d94660a33	2301	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
Jasper_lee	0:b16d94660a33	2302	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
Jasper_lee	0:b16d94660a33	2303	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
Jasper_lee	0:b16d94660a33	2304	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
Jasper_lee	0:b16d94660a33	2305
Jasper_lee	0:b16d94660a33	2306	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
Jasper_lee	0:b16d94660a33	2307	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
Jasper_lee	0:b16d94660a33	2308	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
Jasper_lee	0:b16d94660a33	2309	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
Jasper_lee	0:b16d94660a33	2310	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
Jasper_lee	0:b16d94660a33	2311
Jasper_lee	0:b16d94660a33	2312	/**
Jasper_lee	0:b16d94660a33	2313	* @brief EXTI4 configuration
Jasper_lee	0:b16d94660a33	2314	*/
Jasper_lee	0:b16d94660a33	2315	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
Jasper_lee	0:b16d94660a33	2316	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
Jasper_lee	0:b16d94660a33	2317	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
Jasper_lee	0:b16d94660a33	2318	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
Jasper_lee	0:b16d94660a33	2319	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
Jasper_lee	0:b16d94660a33	2320
Jasper_lee	0:b16d94660a33	2321	/**
Jasper_lee	0:b16d94660a33	2322	* @brief EXTI5 configuration
Jasper_lee	0:b16d94660a33	2323	*/
Jasper_lee	0:b16d94660a33	2324	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
Jasper_lee	0:b16d94660a33	2325	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
Jasper_lee	0:b16d94660a33	2326	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
Jasper_lee	0:b16d94660a33	2327	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
Jasper_lee	0:b16d94660a33	2328	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
Jasper_lee	0:b16d94660a33	2329
Jasper_lee	0:b16d94660a33	2330	/**
Jasper_lee	0:b16d94660a33	2331	* @brief EXTI6 configuration
Jasper_lee	0:b16d94660a33	2332	*/
Jasper_lee	0:b16d94660a33	2333	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
Jasper_lee	0:b16d94660a33	2334	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
Jasper_lee	0:b16d94660a33	2335	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
Jasper_lee	0:b16d94660a33	2336	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
Jasper_lee	0:b16d94660a33	2337	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
Jasper_lee	0:b16d94660a33	2338
Jasper_lee	0:b16d94660a33	2339	/**
Jasper_lee	0:b16d94660a33	2340	* @brief EXTI7 configuration
Jasper_lee	0:b16d94660a33	2341	*/
Jasper_lee	0:b16d94660a33	2342	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
Jasper_lee	0:b16d94660a33	2343	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
Jasper_lee	0:b16d94660a33	2344	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
Jasper_lee	0:b16d94660a33	2345	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
Jasper_lee	0:b16d94660a33	2346	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
Jasper_lee	0:b16d94660a33	2347
Jasper_lee	0:b16d94660a33	2348	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
Jasper_lee	0:b16d94660a33	2349	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
Jasper_lee	0:b16d94660a33	2350	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
Jasper_lee	0:b16d94660a33	2351	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
Jasper_lee	0:b16d94660a33	2352	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
Jasper_lee	0:b16d94660a33	2353
Jasper_lee	0:b16d94660a33	2354	/**
Jasper_lee	0:b16d94660a33	2355	* @brief EXTI8 configuration
Jasper_lee	0:b16d94660a33	2356	*/
Jasper_lee	0:b16d94660a33	2357	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
Jasper_lee	0:b16d94660a33	2358	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
Jasper_lee	0:b16d94660a33	2359	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
Jasper_lee	0:b16d94660a33	2360	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
Jasper_lee	0:b16d94660a33	2361	#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!< PF[8] pin /
Jasper_lee	0:b16d94660a33	2362
Jasper_lee	0:b16d94660a33	2363	/**
Jasper_lee	0:b16d94660a33	2364	* @brief EXTI9 configuration
Jasper_lee	0:b16d94660a33	2365	*/
Jasper_lee	0:b16d94660a33	2366	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
Jasper_lee	0:b16d94660a33	2367	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
Jasper_lee	0:b16d94660a33	2368	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
Jasper_lee	0:b16d94660a33	2369	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
Jasper_lee	0:b16d94660a33	2370	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
Jasper_lee	0:b16d94660a33	2371
Jasper_lee	0:b16d94660a33	2372	/**
Jasper_lee	0:b16d94660a33	2373	* @brief EXTI10 configuration
Jasper_lee	0:b16d94660a33	2374	*/
Jasper_lee	0:b16d94660a33	2375	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
Jasper_lee	0:b16d94660a33	2376	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
Jasper_lee	0:b16d94660a33	2377	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
Jasper_lee	0:b16d94660a33	2378	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
Jasper_lee	0:b16d94660a33	2379	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
Jasper_lee	0:b16d94660a33	2380
Jasper_lee	0:b16d94660a33	2381	/**
Jasper_lee	0:b16d94660a33	2382	* @brief EXTI11 configuration
Jasper_lee	0:b16d94660a33	2383	*/
Jasper_lee	0:b16d94660a33	2384	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
Jasper_lee	0:b16d94660a33	2385	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
Jasper_lee	0:b16d94660a33	2386	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
Jasper_lee	0:b16d94660a33	2387	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
Jasper_lee	0:b16d94660a33	2388	#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!< PF[11] pin /
Jasper_lee	0:b16d94660a33	2389
Jasper_lee	0:b16d94660a33	2390	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
Jasper_lee	0:b16d94660a33	2391	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
Jasper_lee	0:b16d94660a33	2392	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
Jasper_lee	0:b16d94660a33	2393	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
Jasper_lee	0:b16d94660a33	2394	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
Jasper_lee	0:b16d94660a33	2395
Jasper_lee	0:b16d94660a33	2396	/**
Jasper_lee	0:b16d94660a33	2397	* @brief EXTI12 configuration
Jasper_lee	0:b16d94660a33	2398	*/
Jasper_lee	0:b16d94660a33	2399	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
Jasper_lee	0:b16d94660a33	2400	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
Jasper_lee	0:b16d94660a33	2401	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
Jasper_lee	0:b16d94660a33	2402	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
Jasper_lee	0:b16d94660a33	2403	#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!< PF[12] pin /
Jasper_lee	0:b16d94660a33	2404
Jasper_lee	0:b16d94660a33	2405	/**
Jasper_lee	0:b16d94660a33	2406	* @brief EXTI13 configuration
Jasper_lee	0:b16d94660a33	2407	*/
Jasper_lee	0:b16d94660a33	2408	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
Jasper_lee	0:b16d94660a33	2409	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
Jasper_lee	0:b16d94660a33	2410	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
Jasper_lee	0:b16d94660a33	2411	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
Jasper_lee	0:b16d94660a33	2412	#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!< PF[13] pin /
Jasper_lee	0:b16d94660a33	2413
Jasper_lee	0:b16d94660a33	2414	/**
Jasper_lee	0:b16d94660a33	2415	* @brief EXTI14 configuration
Jasper_lee	0:b16d94660a33	2416	*/
Jasper_lee	0:b16d94660a33	2417	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
Jasper_lee	0:b16d94660a33	2418	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
Jasper_lee	0:b16d94660a33	2419	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
Jasper_lee	0:b16d94660a33	2420	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
Jasper_lee	0:b16d94660a33	2421	#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!< PF[14] pin /
Jasper_lee	0:b16d94660a33	2422
Jasper_lee	0:b16d94660a33	2423	/**
Jasper_lee	0:b16d94660a33	2424	* @brief EXTI15 configuration
Jasper_lee	0:b16d94660a33	2425	*/
Jasper_lee	0:b16d94660a33	2426	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
Jasper_lee	0:b16d94660a33	2427	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
Jasper_lee	0:b16d94660a33	2428	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
Jasper_lee	0:b16d94660a33	2429	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
Jasper_lee	0:b16d94660a33	2430	#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!< PF[15] pin /
Jasper_lee	0:b16d94660a33	2431
Jasper_lee	0:b16d94660a33	2432	/*************** Bit definition for SYSCFG_CFGR2 register **************/
Jasper_lee	0:b16d94660a33	2433	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
Jasper_lee	0:b16d94660a33	2434	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
Jasper_lee	0:b16d94660a33	2435	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
Jasper_lee	0:b16d94660a33	2436	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
Jasper_lee	0:b16d94660a33	2437
Jasper_lee	0:b16d94660a33	2438	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2439	/* */
Jasper_lee	0:b16d94660a33	2440	/* Timers (TIM) */
Jasper_lee	0:b16d94660a33	2441	/* */
Jasper_lee	0:b16d94660a33	2442	/*****************************************************************************/
Jasper_lee	0:b16d94660a33	2443	/***************** Bit definition for TIM_CR1 register *****************/
Jasper_lee	0:b16d94660a33	2444	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
Jasper_lee	0:b16d94660a33	2445	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
Jasper_lee	0:b16d94660a33	2446	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
Jasper_lee	0:b16d94660a33	2447	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
Jasper_lee	0:b16d94660a33	2448	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
Jasper_lee	0:b16d94660a33	2449
Jasper_lee	0:b16d94660a33	2450	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
Jasper_lee	0:b16d94660a33	2451	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2452	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2453
Jasper_lee	0:b16d94660a33	2454	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
Jasper_lee	0:b16d94660a33	2455
Jasper_lee	0:b16d94660a33	2456	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
Jasper_lee	0:b16d94660a33	2457	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2458	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2459
Jasper_lee	0:b16d94660a33	2460	/***************** Bit definition for TIM_CR2 register *****************/
Jasper_lee	0:b16d94660a33	2461	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
Jasper_lee	0:b16d94660a33	2462	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
Jasper_lee	0:b16d94660a33	2463	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
Jasper_lee	0:b16d94660a33	2464
Jasper_lee	0:b16d94660a33	2465	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
Jasper_lee	0:b16d94660a33	2466	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2467	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2468	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2469
Jasper_lee	0:b16d94660a33	2470	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
Jasper_lee	0:b16d94660a33	2471	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
Jasper_lee	0:b16d94660a33	2472	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
Jasper_lee	0:b16d94660a33	2473	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
Jasper_lee	0:b16d94660a33	2474	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
Jasper_lee	0:b16d94660a33	2475	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
Jasper_lee	0:b16d94660a33	2476	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
Jasper_lee	0:b16d94660a33	2477	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
Jasper_lee	0:b16d94660a33	2478
Jasper_lee	0:b16d94660a33	2479	/***************** Bit definition for TIM_SMCR register ****************/
Jasper_lee	0:b16d94660a33	2480	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
Jasper_lee	0:b16d94660a33	2481	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2482	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2483	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2484
Jasper_lee	0:b16d94660a33	2485	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
Jasper_lee	0:b16d94660a33	2486
Jasper_lee	0:b16d94660a33	2487	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
Jasper_lee	0:b16d94660a33	2488	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2489	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2490	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2491
Jasper_lee	0:b16d94660a33	2492	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
Jasper_lee	0:b16d94660a33	2493
Jasper_lee	0:b16d94660a33	2494	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
Jasper_lee	0:b16d94660a33	2495	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2496	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2497	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2498	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2499
Jasper_lee	0:b16d94660a33	2500	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
Jasper_lee	0:b16d94660a33	2501	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2502	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2503
Jasper_lee	0:b16d94660a33	2504	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
Jasper_lee	0:b16d94660a33	2505	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
Jasper_lee	0:b16d94660a33	2506
Jasper_lee	0:b16d94660a33	2507	/***************** Bit definition for TIM_DIER register ****************/
Jasper_lee	0:b16d94660a33	2508	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
Jasper_lee	0:b16d94660a33	2509	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
Jasper_lee	0:b16d94660a33	2510	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
Jasper_lee	0:b16d94660a33	2511	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
Jasper_lee	0:b16d94660a33	2512	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
Jasper_lee	0:b16d94660a33	2513	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
Jasper_lee	0:b16d94660a33	2514	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
Jasper_lee	0:b16d94660a33	2515	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
Jasper_lee	0:b16d94660a33	2516	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
Jasper_lee	0:b16d94660a33	2517	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
Jasper_lee	0:b16d94660a33	2518	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
Jasper_lee	0:b16d94660a33	2519	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
Jasper_lee	0:b16d94660a33	2520	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
Jasper_lee	0:b16d94660a33	2521	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
Jasper_lee	0:b16d94660a33	2522	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
Jasper_lee	0:b16d94660a33	2523
Jasper_lee	0:b16d94660a33	2524	/****************** Bit definition for TIM_SR register *****************/
Jasper_lee	0:b16d94660a33	2525	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
Jasper_lee	0:b16d94660a33	2526	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
Jasper_lee	0:b16d94660a33	2527	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
Jasper_lee	0:b16d94660a33	2528	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
Jasper_lee	0:b16d94660a33	2529	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
Jasper_lee	0:b16d94660a33	2530	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
Jasper_lee	0:b16d94660a33	2531	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
Jasper_lee	0:b16d94660a33	2532	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
Jasper_lee	0:b16d94660a33	2533	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
Jasper_lee	0:b16d94660a33	2534	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
Jasper_lee	0:b16d94660a33	2535	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
Jasper_lee	0:b16d94660a33	2536	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
Jasper_lee	0:b16d94660a33	2537
Jasper_lee	0:b16d94660a33	2538	/***************** Bit definition for TIM_EGR register *****************/
Jasper_lee	0:b16d94660a33	2539	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
Jasper_lee	0:b16d94660a33	2540	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
Jasper_lee	0:b16d94660a33	2541	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
Jasper_lee	0:b16d94660a33	2542	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
Jasper_lee	0:b16d94660a33	2543	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
Jasper_lee	0:b16d94660a33	2544	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
Jasper_lee	0:b16d94660a33	2545	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
Jasper_lee	0:b16d94660a33	2546	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
Jasper_lee	0:b16d94660a33	2547
Jasper_lee	0:b16d94660a33	2548	/**************** Bit definition for TIM_CCMR1 register ****************/
Jasper_lee	0:b16d94660a33	2549	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Jasper_lee	0:b16d94660a33	2550	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2551	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2552
Jasper_lee	0:b16d94660a33	2553	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
Jasper_lee	0:b16d94660a33	2554	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
Jasper_lee	0:b16d94660a33	2555
Jasper_lee	0:b16d94660a33	2556	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Jasper_lee	0:b16d94660a33	2557	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2558	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2559	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2560
Jasper_lee	0:b16d94660a33	2561	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
Jasper_lee	0:b16d94660a33	2562
Jasper_lee	0:b16d94660a33	2563	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Jasper_lee	0:b16d94660a33	2564	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2565	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2566
Jasper_lee	0:b16d94660a33	2567	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
Jasper_lee	0:b16d94660a33	2568	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
Jasper_lee	0:b16d94660a33	2569
Jasper_lee	0:b16d94660a33	2570	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Jasper_lee	0:b16d94660a33	2571	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2572	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2573	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2574
Jasper_lee	0:b16d94660a33	2575	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
Jasper_lee	0:b16d94660a33	2576
Jasper_lee	0:b16d94660a33	2577	/---------------------------------------------------------------------------/
Jasper_lee	0:b16d94660a33	2578
Jasper_lee	0:b16d94660a33	2579	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Jasper_lee	0:b16d94660a33	2580	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2581	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2582
Jasper_lee	0:b16d94660a33	2583	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Jasper_lee	0:b16d94660a33	2584	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2585	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2586	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2587	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2588
Jasper_lee	0:b16d94660a33	2589	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Jasper_lee	0:b16d94660a33	2590	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2591	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2592
Jasper_lee	0:b16d94660a33	2593	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Jasper_lee	0:b16d94660a33	2594	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2595	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2596	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2597	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2598
Jasper_lee	0:b16d94660a33	2599	/**************** Bit definition for TIM_CCMR2 register ****************/
Jasper_lee	0:b16d94660a33	2600	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Jasper_lee	0:b16d94660a33	2601	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2602	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2603
Jasper_lee	0:b16d94660a33	2604	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
Jasper_lee	0:b16d94660a33	2605	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
Jasper_lee	0:b16d94660a33	2606
Jasper_lee	0:b16d94660a33	2607	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Jasper_lee	0:b16d94660a33	2608	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2609	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2610	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2611
Jasper_lee	0:b16d94660a33	2612	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
Jasper_lee	0:b16d94660a33	2613
Jasper_lee	0:b16d94660a33	2614	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Jasper_lee	0:b16d94660a33	2615	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2616	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2617
Jasper_lee	0:b16d94660a33	2618	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
Jasper_lee	0:b16d94660a33	2619	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
Jasper_lee	0:b16d94660a33	2620
Jasper_lee	0:b16d94660a33	2621	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Jasper_lee	0:b16d94660a33	2622	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2623	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2624	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2625
Jasper_lee	0:b16d94660a33	2626	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
Jasper_lee	0:b16d94660a33	2627
Jasper_lee	0:b16d94660a33	2628	/---------------------------------------------------------------------------/
Jasper_lee	0:b16d94660a33	2629
Jasper_lee	0:b16d94660a33	2630	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Jasper_lee	0:b16d94660a33	2631	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2632	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2633
Jasper_lee	0:b16d94660a33	2634	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Jasper_lee	0:b16d94660a33	2635	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2636	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2637	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2638	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2639
Jasper_lee	0:b16d94660a33	2640	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Jasper_lee	0:b16d94660a33	2641	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2642	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2643
Jasper_lee	0:b16d94660a33	2644	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Jasper_lee	0:b16d94660a33	2645	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2646	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2647	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2648	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2649
Jasper_lee	0:b16d94660a33	2650	/***************** Bit definition for TIM_CCER register ****************/
Jasper_lee	0:b16d94660a33	2651	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
Jasper_lee	0:b16d94660a33	2652	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
Jasper_lee	0:b16d94660a33	2653	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
Jasper_lee	0:b16d94660a33	2654	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
Jasper_lee	0:b16d94660a33	2655	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
Jasper_lee	0:b16d94660a33	2656	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
Jasper_lee	0:b16d94660a33	2657	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
Jasper_lee	0:b16d94660a33	2658	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
Jasper_lee	0:b16d94660a33	2659	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
Jasper_lee	0:b16d94660a33	2660	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
Jasper_lee	0:b16d94660a33	2661	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
Jasper_lee	0:b16d94660a33	2662	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
Jasper_lee	0:b16d94660a33	2663	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
Jasper_lee	0:b16d94660a33	2664	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
Jasper_lee	0:b16d94660a33	2665	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
Jasper_lee	0:b16d94660a33	2666
Jasper_lee	0:b16d94660a33	2667	/***************** Bit definition for TIM_CNT register *****************/
Jasper_lee	0:b16d94660a33	2668	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
Jasper_lee	0:b16d94660a33	2669
Jasper_lee	0:b16d94660a33	2670	/***************** Bit definition for TIM_PSC register *****************/
Jasper_lee	0:b16d94660a33	2671	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
Jasper_lee	0:b16d94660a33	2672
Jasper_lee	0:b16d94660a33	2673	/***************** Bit definition for TIM_ARR register *****************/
Jasper_lee	0:b16d94660a33	2674	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
Jasper_lee	0:b16d94660a33	2675
Jasper_lee	0:b16d94660a33	2676	/***************** Bit definition for TIM_RCR register *****************/
Jasper_lee	0:b16d94660a33	2677	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
Jasper_lee	0:b16d94660a33	2678
Jasper_lee	0:b16d94660a33	2679	/***************** Bit definition for TIM_CCR1 register ****************/
Jasper_lee	0:b16d94660a33	2680	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
Jasper_lee	0:b16d94660a33	2681
Jasper_lee	0:b16d94660a33	2682	/***************** Bit definition for TIM_CCR2 register ****************/
Jasper_lee	0:b16d94660a33	2683	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
Jasper_lee	0:b16d94660a33	2684
Jasper_lee	0:b16d94660a33	2685	/***************** Bit definition for TIM_CCR3 register ****************/
Jasper_lee	0:b16d94660a33	2686	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
Jasper_lee	0:b16d94660a33	2687
Jasper_lee	0:b16d94660a33	2688	/***************** Bit definition for TIM_CCR4 register ****************/
Jasper_lee	0:b16d94660a33	2689	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
Jasper_lee	0:b16d94660a33	2690
Jasper_lee	0:b16d94660a33	2691	/***************** Bit definition for TIM_BDTR register ****************/
Jasper_lee	0:b16d94660a33	2692	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
Jasper_lee	0:b16d94660a33	2693	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2694	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2695	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2696	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2697	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	2698	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
Jasper_lee	0:b16d94660a33	2699	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
Jasper_lee	0:b16d94660a33	2700	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
Jasper_lee	0:b16d94660a33	2701
Jasper_lee	0:b16d94660a33	2702	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
Jasper_lee	0:b16d94660a33	2703	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2704	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2705
Jasper_lee	0:b16d94660a33	2706	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
Jasper_lee	0:b16d94660a33	2707	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
Jasper_lee	0:b16d94660a33	2708	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
Jasper_lee	0:b16d94660a33	2709	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
Jasper_lee	0:b16d94660a33	2710	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
Jasper_lee	0:b16d94660a33	2711	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
Jasper_lee	0:b16d94660a33	2712
Jasper_lee	0:b16d94660a33	2713	/***************** Bit definition for TIM_DCR register *****************/
Jasper_lee	0:b16d94660a33	2714	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
Jasper_lee	0:b16d94660a33	2715	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2716	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2717	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2718	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2719	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	2720
Jasper_lee	0:b16d94660a33	2721	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
Jasper_lee	0:b16d94660a33	2722	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2723	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2724	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2725	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2726	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	2727
Jasper_lee	0:b16d94660a33	2728	/***************** Bit definition for TIM_DMAR register ****************/
Jasper_lee	0:b16d94660a33	2729	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
Jasper_lee	0:b16d94660a33	2730
Jasper_lee	0:b16d94660a33	2731	/***************** Bit definition for TIM14_OR register ******************/
Jasper_lee	0:b16d94660a33	2732	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
Jasper_lee	0:b16d94660a33	2733	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2734	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2735
Jasper_lee	0:b16d94660a33	2736
Jasper_lee	0:b16d94660a33	2737	/******************************************************************************/
Jasper_lee	0:b16d94660a33	2738	/* */
Jasper_lee	0:b16d94660a33	2739	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Jasper_lee	0:b16d94660a33	2740	/* */
Jasper_lee	0:b16d94660a33	2741	/******************************************************************************/
Jasper_lee	0:b16d94660a33	2742	/**************** Bit definition for USART_CR1 register *****************/
Jasper_lee	0:b16d94660a33	2743	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
Jasper_lee	0:b16d94660a33	2744	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
Jasper_lee	0:b16d94660a33	2745	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
Jasper_lee	0:b16d94660a33	2746	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
Jasper_lee	0:b16d94660a33	2747	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
Jasper_lee	0:b16d94660a33	2748	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
Jasper_lee	0:b16d94660a33	2749	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
Jasper_lee	0:b16d94660a33	2750	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
Jasper_lee	0:b16d94660a33	2751	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
Jasper_lee	0:b16d94660a33	2752	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
Jasper_lee	0:b16d94660a33	2753	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
Jasper_lee	0:b16d94660a33	2754	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
Jasper_lee	0:b16d94660a33	2755	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
Jasper_lee	0:b16d94660a33	2756	#define USART_CR1_M ((uint32_t)0x00001000) /!< SmartCard Length /
Jasper_lee	0:b16d94660a33	2757	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
Jasper_lee	0:b16d94660a33	2758	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
Jasper_lee	0:b16d94660a33	2759	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
Jasper_lee	0:b16d94660a33	2760	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
Jasper_lee	0:b16d94660a33	2761	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2762	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2763	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	2764	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	2765	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
Jasper_lee	0:b16d94660a33	2766	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
Jasper_lee	0:b16d94660a33	2767	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2768	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2769	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	2770	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
Jasper_lee	0:b16d94660a33	2771	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
Jasper_lee	0:b16d94660a33	2772	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
Jasper_lee	0:b16d94660a33	2773	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
Jasper_lee	0:b16d94660a33	2774
Jasper_lee	0:b16d94660a33	2775	/**************** Bit definition for USART_CR2 register *****************/
Jasper_lee	0:b16d94660a33	2776	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
Jasper_lee	0:b16d94660a33	2777	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
Jasper_lee	0:b16d94660a33	2778	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
Jasper_lee	0:b16d94660a33	2779	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
Jasper_lee	0:b16d94660a33	2780	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
Jasper_lee	0:b16d94660a33	2781	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
Jasper_lee	0:b16d94660a33	2782	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
Jasper_lee	0:b16d94660a33	2783	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
Jasper_lee	0:b16d94660a33	2784	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2785	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2786	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
Jasper_lee	0:b16d94660a33	2787	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
Jasper_lee	0:b16d94660a33	2788	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
Jasper_lee	0:b16d94660a33	2789	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
Jasper_lee	0:b16d94660a33	2790	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
Jasper_lee	0:b16d94660a33	2791	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
Jasper_lee	0:b16d94660a33	2792	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
Jasper_lee	0:b16d94660a33	2793	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
Jasper_lee	0:b16d94660a33	2794	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2795	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2796	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
Jasper_lee	0:b16d94660a33	2797	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
Jasper_lee	0:b16d94660a33	2798
Jasper_lee	0:b16d94660a33	2799	/**************** Bit definition for USART_CR3 register *****************/
Jasper_lee	0:b16d94660a33	2800	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
Jasper_lee	0:b16d94660a33	2801	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
Jasper_lee	0:b16d94660a33	2802	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
Jasper_lee	0:b16d94660a33	2803	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
Jasper_lee	0:b16d94660a33	2804	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
Jasper_lee	0:b16d94660a33	2805	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
Jasper_lee	0:b16d94660a33	2806	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
Jasper_lee	0:b16d94660a33	2807	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
Jasper_lee	0:b16d94660a33	2808	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
Jasper_lee	0:b16d94660a33	2809	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
Jasper_lee	0:b16d94660a33	2810	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
Jasper_lee	0:b16d94660a33	2811	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
Jasper_lee	0:b16d94660a33	2812	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
Jasper_lee	0:b16d94660a33	2813	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
Jasper_lee	0:b16d94660a33	2814	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
Jasper_lee	0:b16d94660a33	2815	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
Jasper_lee	0:b16d94660a33	2816	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
Jasper_lee	0:b16d94660a33	2817	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2818	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2819	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
Jasper_lee	0:b16d94660a33	2820	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
Jasper_lee	0:b16d94660a33	2821	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
Jasper_lee	0:b16d94660a33	2822	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
Jasper_lee	0:b16d94660a33	2823	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
Jasper_lee	0:b16d94660a33	2824
Jasper_lee	0:b16d94660a33	2825	/**************** Bit definition for USART_BRR register *****************/
Jasper_lee	0:b16d94660a33	2826	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
Jasper_lee	0:b16d94660a33	2827	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
Jasper_lee	0:b16d94660a33	2828
Jasper_lee	0:b16d94660a33	2829	/**************** Bit definition for USART_GTPR register ****************/
Jasper_lee	0:b16d94660a33	2830	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
Jasper_lee	0:b16d94660a33	2831	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
Jasper_lee	0:b16d94660a33	2832
Jasper_lee	0:b16d94660a33	2833
Jasper_lee	0:b16d94660a33	2834	/***************** Bit definition for USART_RTOR register ***************/
Jasper_lee	0:b16d94660a33	2835	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
Jasper_lee	0:b16d94660a33	2836	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
Jasper_lee	0:b16d94660a33	2837
Jasper_lee	0:b16d94660a33	2838	/***************** Bit definition for USART_RQR register ****************/
Jasper_lee	0:b16d94660a33	2839	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
Jasper_lee	0:b16d94660a33	2840	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
Jasper_lee	0:b16d94660a33	2841	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
Jasper_lee	0:b16d94660a33	2842	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
Jasper_lee	0:b16d94660a33	2843	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
Jasper_lee	0:b16d94660a33	2844
Jasper_lee	0:b16d94660a33	2845	/***************** Bit definition for USART_ISR register ****************/
Jasper_lee	0:b16d94660a33	2846	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
Jasper_lee	0:b16d94660a33	2847	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
Jasper_lee	0:b16d94660a33	2848	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
Jasper_lee	0:b16d94660a33	2849	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
Jasper_lee	0:b16d94660a33	2850	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
Jasper_lee	0:b16d94660a33	2851	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
Jasper_lee	0:b16d94660a33	2852	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
Jasper_lee	0:b16d94660a33	2853	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
Jasper_lee	0:b16d94660a33	2854	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
Jasper_lee	0:b16d94660a33	2855	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
Jasper_lee	0:b16d94660a33	2856	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
Jasper_lee	0:b16d94660a33	2857	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
Jasper_lee	0:b16d94660a33	2858	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
Jasper_lee	0:b16d94660a33	2859	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
Jasper_lee	0:b16d94660a33	2860	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
Jasper_lee	0:b16d94660a33	2861	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
Jasper_lee	0:b16d94660a33	2862	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
Jasper_lee	0:b16d94660a33	2863	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
Jasper_lee	0:b16d94660a33	2864	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
Jasper_lee	0:b16d94660a33	2865	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
Jasper_lee	0:b16d94660a33	2866	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
Jasper_lee	0:b16d94660a33	2867	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
Jasper_lee	0:b16d94660a33	2868
Jasper_lee	0:b16d94660a33	2869	/***************** Bit definition for USART_ICR register ****************/
Jasper_lee	0:b16d94660a33	2870	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
Jasper_lee	0:b16d94660a33	2871	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
Jasper_lee	0:b16d94660a33	2872	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
Jasper_lee	0:b16d94660a33	2873	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
Jasper_lee	0:b16d94660a33	2874	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
Jasper_lee	0:b16d94660a33	2875	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
Jasper_lee	0:b16d94660a33	2876	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
Jasper_lee	0:b16d94660a33	2877	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
Jasper_lee	0:b16d94660a33	2878	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
Jasper_lee	0:b16d94660a33	2879	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
Jasper_lee	0:b16d94660a33	2880	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
Jasper_lee	0:b16d94660a33	2881	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
Jasper_lee	0:b16d94660a33	2882
Jasper_lee	0:b16d94660a33	2883	/***************** Bit definition for USART_RDR register ****************/
Jasper_lee	0:b16d94660a33	2884	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
Jasper_lee	0:b16d94660a33	2885
Jasper_lee	0:b16d94660a33	2886	/***************** Bit definition for USART_TDR register ****************/
Jasper_lee	0:b16d94660a33	2887	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
Jasper_lee	0:b16d94660a33	2888
Jasper_lee	0:b16d94660a33	2889	/******************************************************************************/
Jasper_lee	0:b16d94660a33	2890	/* */
Jasper_lee	0:b16d94660a33	2891	/* Window WATCHDOG (WWDG) */
Jasper_lee	0:b16d94660a33	2892	/* */
Jasper_lee	0:b16d94660a33	2893	/******************************************************************************/
Jasper_lee	0:b16d94660a33	2894	/***************** Bit definition for WWDG_CR register ******************/
Jasper_lee	0:b16d94660a33	2895	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
Jasper_lee	0:b16d94660a33	2896	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2897	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2898	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2899	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2900	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	2901	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
Jasper_lee	0:b16d94660a33	2902	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
Jasper_lee	0:b16d94660a33	2903
Jasper_lee	0:b16d94660a33	2904	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
Jasper_lee	0:b16d94660a33	2905
Jasper_lee	0:b16d94660a33	2906	/***************** Bit definition for WWDG_CFR register *****************/
Jasper_lee	0:b16d94660a33	2907	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
Jasper_lee	0:b16d94660a33	2908	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2909	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2910	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
Jasper_lee	0:b16d94660a33	2911	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
Jasper_lee	0:b16d94660a33	2912	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
Jasper_lee	0:b16d94660a33	2913	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
Jasper_lee	0:b16d94660a33	2914	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
Jasper_lee	0:b16d94660a33	2915
Jasper_lee	0:b16d94660a33	2916	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
Jasper_lee	0:b16d94660a33	2917	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
Jasper_lee	0:b16d94660a33	2918	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
Jasper_lee	0:b16d94660a33	2919
Jasper_lee	0:b16d94660a33	2920	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
Jasper_lee	0:b16d94660a33	2921
Jasper_lee	0:b16d94660a33	2922	/***************** Bit definition for WWDG_SR register ******************/
Jasper_lee	0:b16d94660a33	2923	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
Jasper_lee	0:b16d94660a33	2924
Jasper_lee	0:b16d94660a33	2925	/**
Jasper_lee	0:b16d94660a33	2926	* @}
Jasper_lee	0:b16d94660a33	2927	*/
Jasper_lee	0:b16d94660a33	2928
Jasper_lee	0:b16d94660a33	2929	/**
Jasper_lee	0:b16d94660a33	2930	* @}
Jasper_lee	0:b16d94660a33	2931	*/
Jasper_lee	0:b16d94660a33	2932
Jasper_lee	0:b16d94660a33	2933
Jasper_lee	0:b16d94660a33	2934	/** @addtogroup Exported_macro
Jasper_lee	0:b16d94660a33	2935	* @{
Jasper_lee	0:b16d94660a33	2936	*/
Jasper_lee	0:b16d94660a33	2937
Jasper_lee	0:b16d94660a33	2938	/**************************** ADC Instances *******************************/
Jasper_lee	0:b16d94660a33	2939	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Jasper_lee	0:b16d94660a33	2940
Jasper_lee	0:b16d94660a33	2941	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Jasper_lee	0:b16d94660a33	2942
Jasper_lee	0:b16d94660a33	2943	/**************************** CRC Instances *******************************/
Jasper_lee	0:b16d94660a33	2944	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Jasper_lee	0:b16d94660a33	2945
Jasper_lee	0:b16d94660a33	2946	/***************************** DMA Instances ****************************/
Jasper_lee	0:b16d94660a33	2947	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
Jasper_lee	0:b16d94660a33	2948	((INSTANCE) == DMA1_Channel2) \|\| \
Jasper_lee	0:b16d94660a33	2949	((INSTANCE) == DMA1_Channel3) \|\| \
Jasper_lee	0:b16d94660a33	2950	((INSTANCE) == DMA1_Channel4) \|\| \
Jasper_lee	0:b16d94660a33	2951	((INSTANCE) == DMA1_Channel5))
Jasper_lee	0:b16d94660a33	2952
Jasper_lee	0:b16d94660a33	2953	/**************************** GPIO Instances ******************************/
Jasper_lee	0:b16d94660a33	2954	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Jasper_lee	0:b16d94660a33	2955	((INSTANCE) == GPIOB) \|\| \
Jasper_lee	0:b16d94660a33	2956	((INSTANCE) == GPIOC) \|\| \
Jasper_lee	0:b16d94660a33	2957	((INSTANCE) == GPIOD) \|\| \
Jasper_lee	0:b16d94660a33	2958	((INSTANCE) == GPIOF))
Jasper_lee	0:b16d94660a33	2959
Jasper_lee	0:b16d94660a33	2960	/**************************** GPIO Lock Instances **************************/
Jasper_lee	0:b16d94660a33	2961	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Jasper_lee	0:b16d94660a33	2962	((INSTANCE) == GPIOB))
Jasper_lee	0:b16d94660a33	2963
Jasper_lee	0:b16d94660a33	2964	/**************************** I2C Instances *******************************/
Jasper_lee	0:b16d94660a33	2965	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
Jasper_lee	0:b16d94660a33	2966	((INSTANCE) == I2C2))
Jasper_lee	0:b16d94660a33	2967
Jasper_lee	0:b16d94660a33	2968	/**************************** IWDG Instances ******************************/
Jasper_lee	0:b16d94660a33	2969	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Jasper_lee	0:b16d94660a33	2970
Jasper_lee	0:b16d94660a33	2971	/**************************** RTC Instances *******************************/
Jasper_lee	0:b16d94660a33	2972	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Jasper_lee	0:b16d94660a33	2973
Jasper_lee	0:b16d94660a33	2974	/**************************** SMBUS Instances *******************************/
Jasper_lee	0:b16d94660a33	2975	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Jasper_lee	0:b16d94660a33	2976
Jasper_lee	0:b16d94660a33	2977	/**************************** SPI Instances *******************************/
Jasper_lee	0:b16d94660a33	2978	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
Jasper_lee	0:b16d94660a33	2979	((INSTANCE) == SPI2))
Jasper_lee	0:b16d94660a33	2980
Jasper_lee	0:b16d94660a33	2981	/**************************** TIM Instances *******************************/
Jasper_lee	0:b16d94660a33	2982	#define IS_TIM_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	2983	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	2984	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	2985	((INSTANCE) == TIM6) \|\| \
Jasper_lee	0:b16d94660a33	2986	((INSTANCE) == TIM14) \|\| \
Jasper_lee	0:b16d94660a33	2987	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	2988	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	2989	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	2990
Jasper_lee	0:b16d94660a33	2991	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	2992	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	2993	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	2994	((INSTANCE) == TIM14) \|\| \
Jasper_lee	0:b16d94660a33	2995	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	2996	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	2997	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	2998
Jasper_lee	0:b16d94660a33	2999	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3000	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3001	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3002	((INSTANCE) == TIM15))
Jasper_lee	0:b16d94660a33	3003
Jasper_lee	0:b16d94660a33	3004	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3005	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3006	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3007
Jasper_lee	0:b16d94660a33	3008	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3009	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3010	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3011
Jasper_lee	0:b16d94660a33	3012	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3013	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3014	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3015
Jasper_lee	0:b16d94660a33	3016	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3017	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3018	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3019
Jasper_lee	0:b16d94660a33	3020	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3021	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3022	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3023	((INSTANCE) == TIM15))
Jasper_lee	0:b16d94660a33	3024
Jasper_lee	0:b16d94660a33	3025	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3026	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3027	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3028	((INSTANCE) == TIM15))
Jasper_lee	0:b16d94660a33	3029
Jasper_lee	0:b16d94660a33	3030	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3031	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3032	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3033
Jasper_lee	0:b16d94660a33	3034	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3035	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3036	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3037
Jasper_lee	0:b16d94660a33	3038	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3039	(((INSTANCE) == TIM1))
Jasper_lee	0:b16d94660a33	3040
Jasper_lee	0:b16d94660a33	3041	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3042	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3043	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3044
Jasper_lee	0:b16d94660a33	3045	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3046	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3047	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3048	((INSTANCE) == TIM15))
Jasper_lee	0:b16d94660a33	3049
Jasper_lee	0:b16d94660a33	3050	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3051	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3052	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3053	((INSTANCE) == TIM15))
Jasper_lee	0:b16d94660a33	3054
Jasper_lee	0:b16d94660a33	3055	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
Jasper_lee	0:b16d94660a33	3056
Jasper_lee	0:b16d94660a33	3057	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3058	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3059	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3060	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3061	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3062	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3063
Jasper_lee	0:b16d94660a33	3064	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3065	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3066	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3067	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3068	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3069
Jasper_lee	0:b16d94660a33	3070	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Jasper_lee	0:b16d94660a33	3071	((((INSTANCE) == TIM1) && \
Jasper_lee	0:b16d94660a33	3072	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Jasper_lee	0:b16d94660a33	3073	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Jasper_lee	0:b16d94660a33	3074	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Jasper_lee	0:b16d94660a33	3075	((CHANNEL) == TIM_CHANNEL_4))) \
Jasper_lee	0:b16d94660a33	3076	\|\| \
Jasper_lee	0:b16d94660a33	3077	(((INSTANCE) == TIM3) && \
Jasper_lee	0:b16d94660a33	3078	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Jasper_lee	0:b16d94660a33	3079	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Jasper_lee	0:b16d94660a33	3080	((CHANNEL) == TIM_CHANNEL_3) \|\| \
Jasper_lee	0:b16d94660a33	3081	((CHANNEL) == TIM_CHANNEL_4))) \
Jasper_lee	0:b16d94660a33	3082	\|\| \
Jasper_lee	0:b16d94660a33	3083	(((INSTANCE) == TIM14) && \
Jasper_lee	0:b16d94660a33	3084	(((CHANNEL) == TIM_CHANNEL_1))) \
Jasper_lee	0:b16d94660a33	3085	\|\| \
Jasper_lee	0:b16d94660a33	3086	(((INSTANCE) == TIM15) && \
Jasper_lee	0:b16d94660a33	3087	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Jasper_lee	0:b16d94660a33	3088	((CHANNEL) == TIM_CHANNEL_2))) \
Jasper_lee	0:b16d94660a33	3089	\|\| \
Jasper_lee	0:b16d94660a33	3090	(((INSTANCE) == TIM16) && \
Jasper_lee	0:b16d94660a33	3091	(((CHANNEL) == TIM_CHANNEL_1))) \
Jasper_lee	0:b16d94660a33	3092	\|\| \
Jasper_lee	0:b16d94660a33	3093	(((INSTANCE) == TIM17) && \
Jasper_lee	0:b16d94660a33	3094	(((CHANNEL) == TIM_CHANNEL_1))))
Jasper_lee	0:b16d94660a33	3095
Jasper_lee	0:b16d94660a33	3096	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Jasper_lee	0:b16d94660a33	3097	((((INSTANCE) == TIM1) && \
Jasper_lee	0:b16d94660a33	3098	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
Jasper_lee	0:b16d94660a33	3099	((CHANNEL) == TIM_CHANNEL_2) \|\| \
Jasper_lee	0:b16d94660a33	3100	((CHANNEL) == TIM_CHANNEL_3))) \
Jasper_lee	0:b16d94660a33	3101	\|\| \
Jasper_lee	0:b16d94660a33	3102	(((INSTANCE) == TIM15) && \
Jasper_lee	0:b16d94660a33	3103	((CHANNEL) == TIM_CHANNEL_1)) \
Jasper_lee	0:b16d94660a33	3104	\|\| \
Jasper_lee	0:b16d94660a33	3105	(((INSTANCE) == TIM16) && \
Jasper_lee	0:b16d94660a33	3106	((CHANNEL) == TIM_CHANNEL_1)) \
Jasper_lee	0:b16d94660a33	3107	\|\| \
Jasper_lee	0:b16d94660a33	3108	(((INSTANCE) == TIM17) && \
Jasper_lee	0:b16d94660a33	3109	((CHANNEL) == TIM_CHANNEL_1)))
Jasper_lee	0:b16d94660a33	3110
Jasper_lee	0:b16d94660a33	3111	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3112	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3113	((INSTANCE) == TIM3))
Jasper_lee	0:b16d94660a33	3114
Jasper_lee	0:b16d94660a33	3115	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3116	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3117	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3118	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3119	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3120
Jasper_lee	0:b16d94660a33	3121	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3122	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3123	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3124	((INSTANCE) == TIM14) \|\| \
Jasper_lee	0:b16d94660a33	3125	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3126	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3127	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3128
Jasper_lee	0:b16d94660a33	3129	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3130	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3131	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3132	((INSTANCE) == TIM6) \|\| \
Jasper_lee	0:b16d94660a33	3133	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3134	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3135	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3136
Jasper_lee	0:b16d94660a33	3137	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3138	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3139	((INSTANCE) == TIM3) \|\| \
Jasper_lee	0:b16d94660a33	3140	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3141	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3142	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3143
Jasper_lee	0:b16d94660a33	3144	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3145	(((INSTANCE) == TIM1) \|\| \
Jasper_lee	0:b16d94660a33	3146	((INSTANCE) == TIM15) \|\| \
Jasper_lee	0:b16d94660a33	3147	((INSTANCE) == TIM16) \|\| \
Jasper_lee	0:b16d94660a33	3148	((INSTANCE) == TIM17))
Jasper_lee	0:b16d94660a33	3149
Jasper_lee	0:b16d94660a33	3150	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Jasper_lee	0:b16d94660a33	3151	((INSTANCE) == TIM14)
Jasper_lee	0:b16d94660a33	3152
Jasper_lee	0:b16d94660a33	3153	/****************** USART Instances : Synchronous mode ********************/
Jasper_lee	0:b16d94660a33	3154	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Jasper_lee	0:b16d94660a33	3155	((INSTANCE) == USART2))
Jasper_lee	0:b16d94660a33	3156
Jasper_lee	0:b16d94660a33	3157	/****************** USART Instances : auto Baud rate detection ************/
Jasper_lee	0:b16d94660a33	3158	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Jasper_lee	0:b16d94660a33	3159
Jasper_lee	0:b16d94660a33	3160	/****************** UART Instances : Asynchronous mode ********************/
Jasper_lee	0:b16d94660a33	3161	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Jasper_lee	0:b16d94660a33	3162	((INSTANCE) == USART2))
Jasper_lee	0:b16d94660a33	3163
Jasper_lee	0:b16d94660a33	3164	/****************** UART Instances : Half-Duplex mode ********************/
Jasper_lee	0:b16d94660a33	3165	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Jasper_lee	0:b16d94660a33	3166	((INSTANCE) == USART2))
Jasper_lee	0:b16d94660a33	3167
Jasper_lee	0:b16d94660a33	3168	/**************** UART Instances : Hardware Flow control ******************/
Jasper_lee	0:b16d94660a33	3169	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Jasper_lee	0:b16d94660a33	3170	((INSTANCE) == USART2))
Jasper_lee	0:b16d94660a33	3171
Jasper_lee	0:b16d94660a33	3172	/**************** UART Instances : Auto Baud Rate detection ******************/
Jasper_lee	0:b16d94660a33	3173	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Jasper_lee	0:b16d94660a33	3174
Jasper_lee	0:b16d94660a33	3175	/**************** UART Instances : Driver enable detection ******************/
Jasper_lee	0:b16d94660a33	3176	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
Jasper_lee	0:b16d94660a33	3177	((INSTANCE) == USART2))
Jasper_lee	0:b16d94660a33	3178
Jasper_lee	0:b16d94660a33	3179	/**************************** WWDG Instances ******************************/
Jasper_lee	0:b16d94660a33	3180	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Jasper_lee	0:b16d94660a33	3181
Jasper_lee	0:b16d94660a33	3182	/**
Jasper_lee	0:b16d94660a33	3183	* @}
Jasper_lee	0:b16d94660a33	3184	*/
Jasper_lee	0:b16d94660a33	3185
Jasper_lee	0:b16d94660a33	3186
Jasper_lee	0:b16d94660a33	3187	/******************************************************************************/
Jasper_lee	0:b16d94660a33	3188	/* For a painless codes migration between the STM32F0xx device product */
Jasper_lee	0:b16d94660a33	3189	/* lines, the aliases defined below are put in place to overcome the */
Jasper_lee	0:b16d94660a33	3190	/* differences in the interrupt handlers and IRQn definitions. */
Jasper_lee	0:b16d94660a33	3191	/* No need to update developed interrupt code when moving across */
Jasper_lee	0:b16d94660a33	3192	/* product lines within the same STM32F0 Family */
Jasper_lee	0:b16d94660a33	3193	/******************************************************************************/
Jasper_lee	0:b16d94660a33	3194
Jasper_lee	0:b16d94660a33	3195	/* Aliases for __IRQn */
Jasper_lee	0:b16d94660a33	3196	#define RCC_CRS_IRQn RCC_IRQn
Jasper_lee	0:b16d94660a33	3197	#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Jasper_lee	0:b16d94660a33	3198	#define ADC1_COMP_IRQn ADC1_IRQn
Jasper_lee	0:b16d94660a33	3199	#define TIM6_DAC_IRQn TIM6_IRQn
Jasper_lee	0:b16d94660a33	3200
Jasper_lee	0:b16d94660a33	3201	/* Aliases for __IRQHandler */
Jasper_lee	0:b16d94660a33	3202	#define RCC_CRS_IRQHandler RCC_IRQHandler
Jasper_lee	0:b16d94660a33	3203	#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Jasper_lee	0:b16d94660a33	3204	#define ADC1_COMP_IRQHandler ADC1_IRQHandler
Jasper_lee	0:b16d94660a33	3205	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
Jasper_lee	0:b16d94660a33	3206
Jasper_lee	0:b16d94660a33	3207	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	3208	}
Jasper_lee	0:b16d94660a33	3209	#endif /* __cplusplus */
Jasper_lee	0:b16d94660a33	3210
Jasper_lee	0:b16d94660a33	3211	#endif /* __STM32F030x8_H */
Jasper_lee	0:b16d94660a33	3212
Jasper_lee	0:b16d94660a33	3213	/**
Jasper_lee	0:b16d94660a33	3214	* @}
Jasper_lee	0:b16d94660a33	3215	*/
Jasper_lee	0:b16d94660a33	3216
Jasper_lee	0:b16d94660a33	3217	/**
Jasper_lee	0:b16d94660a33	3218	* @}
Jasper_lee	0:b16d94660a33	3219	*/
Jasper_lee	0:b16d94660a33	3220
Jasper_lee	0:b16d94660a33	3221	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	23 Dec 2014
Imports:	459
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	12

The code in this repository is Apache licensed.

TARGET_NUCLEO_F030R8/stm32f030x8.h@0:b16d94660a33, 2014-12-23 (annotated)

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