mbed_helloworld - change some io settings for TWR-K22F-120M

Users » Jasper_lee » Code » mbed_helloworld

change some io settings for TWR-K22F-120M

TARGET_LPC4337/LPC43xx.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:: Jasper_lee
Date:: Tue Dec 23 03:35:08 2014 +0000
Revision:: 0:b16d94660a33

change some io setting used in TWR-K22F120M

Who changed what in which revision?

User	Revision	Line number	New contents of line
Jasper_lee	0:b16d94660a33	1	/*
Jasper_lee	0:b16d94660a33	2	* LPC43xx/LPC18xx MCU header
Jasper_lee	0:b16d94660a33	3	*
Jasper_lee	0:b16d94660a33	4	* Copyright(C) NXP Semiconductors, 2012
Jasper_lee	0:b16d94660a33	5	* All rights reserved.
Jasper_lee	0:b16d94660a33	6	*
Jasper_lee	0:b16d94660a33	7	* Software that is described herein is for illustrative purposes only
Jasper_lee	0:b16d94660a33	8	* which provides customers with programming information regarding the
Jasper_lee	0:b16d94660a33	9	* LPC products. This software is supplied "AS IS" without any warranties of
Jasper_lee	0:b16d94660a33	10	* any kind, and NXP Semiconductors and its licensor disclaim any and
Jasper_lee	0:b16d94660a33	11	* all warranties, express or implied, including all implied warranties of
Jasper_lee	0:b16d94660a33	12	* merchantability, fitness for a particular purpose and non-infringement of
Jasper_lee	0:b16d94660a33	13	* intellectual property rights. NXP Semiconductors assumes no responsibility
Jasper_lee	0:b16d94660a33	14	* or liability for the use of the software, conveys no license or rights under any
Jasper_lee	0:b16d94660a33	15	* patent, copyright, mask work right, or any other intellectual property rights in
Jasper_lee	0:b16d94660a33	16	* or to any products. NXP Semiconductors reserves the right to make changes
Jasper_lee	0:b16d94660a33	17	* in the software without notification. NXP Semiconductors also makes no
Jasper_lee	0:b16d94660a33	18	* representation or warranty that such application will be suitable for the
Jasper_lee	0:b16d94660a33	19	* specified use without further testing or modification.
Jasper_lee	0:b16d94660a33	20	*
Jasper_lee	0:b16d94660a33	21	* Permission to use, copy, modify, and distribute this software and its
Jasper_lee	0:b16d94660a33	22	* documentation is hereby granted, under NXP Semiconductors' and its
Jasper_lee	0:b16d94660a33	23	* licensor's relevant copyrights in the software, without fee, provided that it
Jasper_lee	0:b16d94660a33	24	* is used in conjunction with NXP Semiconductors microcontrollers. This
Jasper_lee	0:b16d94660a33	25	* copyright, permission, and disclaimer notice must appear in all copies of
Jasper_lee	0:b16d94660a33	26	* this code.
Jasper_lee	0:b16d94660a33	27	*
Jasper_lee	0:b16d94660a33	28	* Simplified version of NXP LPCOPEN LPC43XX/LPC18XX headers
Jasper_lee	0:b16d94660a33	29	* 05/15/13 Micromint USA <support@micromint.com>
Jasper_lee	0:b16d94660a33	30	*/
Jasper_lee	0:b16d94660a33	31
Jasper_lee	0:b16d94660a33	32	#ifndef __LPC43XX_H
Jasper_lee	0:b16d94660a33	33	#define __LPC43XX_H
Jasper_lee	0:b16d94660a33	34
Jasper_lee	0:b16d94660a33	35	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	36	extern "C" {
Jasper_lee	0:b16d94660a33	37	#endif
Jasper_lee	0:b16d94660a33	38
Jasper_lee	0:b16d94660a33	39	/* Treat __CORE_Mx as CORE_Mx */
Jasper_lee	0:b16d94660a33	40	#if defined(__CORTEX_M0) && !defined(CORE_M0)
Jasper_lee	0:b16d94660a33	41	#define CORE_M0
Jasper_lee	0:b16d94660a33	42	#endif
Jasper_lee	0:b16d94660a33	43	#if defined(__CORTEX_M3) && !defined(CORE_M3)
Jasper_lee	0:b16d94660a33	44	#define CORE_M3
Jasper_lee	0:b16d94660a33	45	#endif
Jasper_lee	0:b16d94660a33	46	/* Default to M4 core if no core explicitly declared */
Jasper_lee	0:b16d94660a33	47	#if !defined(CORE_M0) && !defined(CORE_M3)
Jasper_lee	0:b16d94660a33	48	#define CORE_M4
Jasper_lee	0:b16d94660a33	49	#endif
Jasper_lee	0:b16d94660a33	50
Jasper_lee	0:b16d94660a33	51	/* Define LPC18XX or LPC43XX according to core type */
Jasper_lee	0:b16d94660a33	52	#if (defined(CORE_M4) \|\| defined(CORE_M0)) && !defined(__LPC43XX__)
Jasper_lee	0:b16d94660a33	53	#define __LPC43XX__
Jasper_lee	0:b16d94660a33	54	#endif
Jasper_lee	0:b16d94660a33	55	#if defined(CORE_M3) && !defined(__LPC18XX__)
Jasper_lee	0:b16d94660a33	56	#define __LPC18XX__
Jasper_lee	0:b16d94660a33	57	#endif
Jasper_lee	0:b16d94660a33	58
Jasper_lee	0:b16d94660a33	59	/* Start of section using anonymous unions */
Jasper_lee	0:b16d94660a33	60	#if defined(__ARMCC_VERSION)
Jasper_lee	0:b16d94660a33	61	// Kill warning "#pragma push with no matching #pragma pop"
Jasper_lee	0:b16d94660a33	62	#pragma diag_suppress 2525
Jasper_lee	0:b16d94660a33	63	#pragma push
Jasper_lee	0:b16d94660a33	64	#pragma anon_unions
Jasper_lee	0:b16d94660a33	65	#elif defined(__CWCC__)
Jasper_lee	0:b16d94660a33	66	#pragma push
Jasper_lee	0:b16d94660a33	67	#pragma cpp_extensions on
Jasper_lee	0:b16d94660a33	68	#elif defined(__IAR_SYSTEMS_ICC__)
Jasper_lee	0:b16d94660a33	69	//#pragma push // FIXME not usable for IAR
Jasper_lee	0:b16d94660a33	70	#pragma language=extended
Jasper_lee	0:b16d94660a33	71	#else /* defined(__GNUC__) and others */
Jasper_lee	0:b16d94660a33	72	/* Assume anonymous unions are enabled by default */
Jasper_lee	0:b16d94660a33	73	#endif
Jasper_lee	0:b16d94660a33	74
Jasper_lee	0:b16d94660a33	75	#if defined(CORE_M4)
Jasper_lee	0:b16d94660a33	76	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	77	* LPC43xx (M4 Core) Cortex CMSIS definitions
Jasper_lee	0:b16d94660a33	78	*/
Jasper_lee	0:b16d94660a33	79
Jasper_lee	0:b16d94660a33	80	#define __CM4_REV 0x0000 /* Cortex-M4 Core Revision */
Jasper_lee	0:b16d94660a33	81	#define __MPU_PRESENT 1 /* MPU present or not */
Jasper_lee	0:b16d94660a33	82	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
Jasper_lee	0:b16d94660a33	83	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
Jasper_lee	0:b16d94660a33	84	#define __FPU_PRESENT 1 /* FPU present or not */
Jasper_lee	0:b16d94660a33	85	#define CHIP_LPC43XX /* LPCOPEN compatibility */
Jasper_lee	0:b16d94660a33	86
Jasper_lee	0:b16d94660a33	87	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	88	* LPC43xx peripheral interrupt numbers
Jasper_lee	0:b16d94660a33	89	*/
Jasper_lee	0:b16d94660a33	90
Jasper_lee	0:b16d94660a33	91	typedef enum {
Jasper_lee	0:b16d94660a33	92	/* --------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
Jasper_lee	0:b16d94660a33	93	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
Jasper_lee	0:b16d94660a33	94	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
Jasper_lee	0:b16d94660a33	95	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
Jasper_lee	0:b16d94660a33	96	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
Jasper_lee	0:b16d94660a33	97	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
Jasper_lee	0:b16d94660a33	98	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
Jasper_lee	0:b16d94660a33	99	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
Jasper_lee	0:b16d94660a33	100	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
Jasper_lee	0:b16d94660a33	101	PendSV_IRQn = -2,/* 14 Pendable request for system service */
Jasper_lee	0:b16d94660a33	102	SysTick_IRQn = -1,/* 15 System Tick Timer */
Jasper_lee	0:b16d94660a33	103
Jasper_lee	0:b16d94660a33	104	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
Jasper_lee	0:b16d94660a33	105	DAC_IRQn = 0,/* 0 DAC */
Jasper_lee	0:b16d94660a33	106	M0CORE_IRQn = 1,/* 1 M0a */
Jasper_lee	0:b16d94660a33	107	DMA_IRQn = 2,/* 2 DMA */
Jasper_lee	0:b16d94660a33	108	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
Jasper_lee	0:b16d94660a33	109	RESERVED2_IRQn = 4,
Jasper_lee	0:b16d94660a33	110	ETHERNET_IRQn = 5,/* 5 ETHERNET */
Jasper_lee	0:b16d94660a33	111	SDIO_IRQn = 6,/* 6 SDIO */
Jasper_lee	0:b16d94660a33	112	LCD_IRQn = 7,/* 7 LCD */
Jasper_lee	0:b16d94660a33	113	USB0_IRQn = 8,/* 8 USB0 */
Jasper_lee	0:b16d94660a33	114	USB1_IRQn = 9,/* 9 USB1 */
Jasper_lee	0:b16d94660a33	115	SCT_IRQn = 10,/* 10 SCT */
Jasper_lee	0:b16d94660a33	116	RITIMER_IRQn = 11,/* 11 RITIMER */
Jasper_lee	0:b16d94660a33	117	TIMER0_IRQn = 12,/* 12 TIMER0 */
Jasper_lee	0:b16d94660a33	118	TIMER1_IRQn = 13,/* 13 TIMER1 */
Jasper_lee	0:b16d94660a33	119	TIMER2_IRQn = 14,/* 14 TIMER2 */
Jasper_lee	0:b16d94660a33	120	TIMER3_IRQn = 15,/* 15 TIMER3 */
Jasper_lee	0:b16d94660a33	121	MCPWM_IRQn = 16,/* 16 MCPWM */
Jasper_lee	0:b16d94660a33	122	ADC0_IRQn = 17,/* 17 ADC0 */
Jasper_lee	0:b16d94660a33	123	I2C0_IRQn = 18,/* 18 I2C0 */
Jasper_lee	0:b16d94660a33	124	I2C1_IRQn = 19,/* 19 I2C1 */
Jasper_lee	0:b16d94660a33	125	SPI_INT_IRQn = 20,/* 20 SPI_INT */
Jasper_lee	0:b16d94660a33	126	ADC1_IRQn = 21,/* 21 ADC1 */
Jasper_lee	0:b16d94660a33	127	SSP0_IRQn = 22,/* 22 SSP0 */
Jasper_lee	0:b16d94660a33	128	SSP1_IRQn = 23,/* 23 SSP1 */
Jasper_lee	0:b16d94660a33	129	USART0_IRQn = 24,/* 24 USART0 */
Jasper_lee	0:b16d94660a33	130	UART1_IRQn = 25,/* 25 UART1 */
Jasper_lee	0:b16d94660a33	131	USART2_IRQn = 26,/* 26 USART2 */
Jasper_lee	0:b16d94660a33	132	USART3_IRQn = 27,/* 27 USART3 */
Jasper_lee	0:b16d94660a33	133	I2S0_IRQn = 28,/* 28 I2S0 */
Jasper_lee	0:b16d94660a33	134	I2S1_IRQn = 29,/* 29 I2S1 */
Jasper_lee	0:b16d94660a33	135	RESERVED4_IRQn = 30,
Jasper_lee	0:b16d94660a33	136	SGPIO_INT_IRQn = 31,/* 31 SGPIO_IINT */
Jasper_lee	0:b16d94660a33	137	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
Jasper_lee	0:b16d94660a33	138	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
Jasper_lee	0:b16d94660a33	139	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
Jasper_lee	0:b16d94660a33	140	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
Jasper_lee	0:b16d94660a33	141	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
Jasper_lee	0:b16d94660a33	142	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
Jasper_lee	0:b16d94660a33	143	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
Jasper_lee	0:b16d94660a33	144	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
Jasper_lee	0:b16d94660a33	145	GINT0_IRQn = 40,/* 40 GINT0 */
Jasper_lee	0:b16d94660a33	146	GINT1_IRQn = 41,/* 41 GINT1 */
Jasper_lee	0:b16d94660a33	147	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
Jasper_lee	0:b16d94660a33	148	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
Jasper_lee	0:b16d94660a33	149	RESERVED6_IRQn = 44,
Jasper_lee	0:b16d94660a33	150	RESERVED7_IRQn = 45,/* 45 VADC */
Jasper_lee	0:b16d94660a33	151	ATIMER_IRQn = 46,/* 46 ATIMER */
Jasper_lee	0:b16d94660a33	152	RTC_IRQn = 47,/* 47 RTC */
Jasper_lee	0:b16d94660a33	153	RESERVED8_IRQn = 48,
Jasper_lee	0:b16d94660a33	154	WWDT_IRQn = 49,/* 49 WWDT */
Jasper_lee	0:b16d94660a33	155	RESERVED9_IRQn = 50,
Jasper_lee	0:b16d94660a33	156	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
Jasper_lee	0:b16d94660a33	157	QEI_IRQn = 52,/* 52 QEI */
Jasper_lee	0:b16d94660a33	158	} IRQn_Type;
Jasper_lee	0:b16d94660a33	159
Jasper_lee	0:b16d94660a33	160	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
Jasper_lee	0:b16d94660a33	161
Jasper_lee	0:b16d94660a33	162	#elif defined(CORE_M3)
Jasper_lee	0:b16d94660a33	163	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	164	* LPC18xx (M3 Core) Cortex CMSIS definitions
Jasper_lee	0:b16d94660a33	165	*/
Jasper_lee	0:b16d94660a33	166	#define __MPU_PRESENT 1 /* MPU present or not */
Jasper_lee	0:b16d94660a33	167	#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
Jasper_lee	0:b16d94660a33	168	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
Jasper_lee	0:b16d94660a33	169	#define __FPU_PRESENT 0 /* FPU present or not */
Jasper_lee	0:b16d94660a33	170	#define CHIP_LPC18XX /* LPCOPEN compatibility */
Jasper_lee	0:b16d94660a33	171
Jasper_lee	0:b16d94660a33	172	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	173	* LPC18xx peripheral interrupt numbers
Jasper_lee	0:b16d94660a33	174	*/
Jasper_lee	0:b16d94660a33	175
Jasper_lee	0:b16d94660a33	176	typedef enum {
Jasper_lee	0:b16d94660a33	177	/* --------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
Jasper_lee	0:b16d94660a33	178	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
Jasper_lee	0:b16d94660a33	179	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
Jasper_lee	0:b16d94660a33	180	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
Jasper_lee	0:b16d94660a33	181	MemoryManagement_IRQn = -12,/* 4 Memory Management, MPU mismatch, including Access Violation and No Match */
Jasper_lee	0:b16d94660a33	182	BusFault_IRQn = -11,/* 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
Jasper_lee	0:b16d94660a33	183	UsageFault_IRQn = -10,/* 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
Jasper_lee	0:b16d94660a33	184	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
Jasper_lee	0:b16d94660a33	185	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
Jasper_lee	0:b16d94660a33	186	PendSV_IRQn = -2,/* 14 Pendable request for system service */
Jasper_lee	0:b16d94660a33	187	SysTick_IRQn = -1,/* 15 System Tick Timer */
Jasper_lee	0:b16d94660a33	188
Jasper_lee	0:b16d94660a33	189	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
Jasper_lee	0:b16d94660a33	190	DAC_IRQn = 0,/* 0 DAC */
Jasper_lee	0:b16d94660a33	191	RESERVED0_IRQn = 1,
Jasper_lee	0:b16d94660a33	192	DMA_IRQn = 2,/* 2 DMA */
Jasper_lee	0:b16d94660a33	193	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
Jasper_lee	0:b16d94660a33	194	RESERVED2_IRQn = 4,
Jasper_lee	0:b16d94660a33	195	ETHERNET_IRQn = 5,/* 5 ETHERNET */
Jasper_lee	0:b16d94660a33	196	SDIO_IRQn = 6,/* 6 SDIO */
Jasper_lee	0:b16d94660a33	197	LCD_IRQn = 7,/* 7 LCD */
Jasper_lee	0:b16d94660a33	198	USB0_IRQn = 8,/* 8 USB0 */
Jasper_lee	0:b16d94660a33	199	USB1_IRQn = 9,/* 9 USB1 */
Jasper_lee	0:b16d94660a33	200	SCT_IRQn = 10,/* 10 SCT */
Jasper_lee	0:b16d94660a33	201	RITIMER_IRQn = 11,/* 11 RITIMER */
Jasper_lee	0:b16d94660a33	202	TIMER0_IRQn = 12,/* 12 TIMER0 */
Jasper_lee	0:b16d94660a33	203	TIMER1_IRQn = 13,/* 13 TIMER1 */
Jasper_lee	0:b16d94660a33	204	TIMER2_IRQn = 14,/* 14 TIMER2 */
Jasper_lee	0:b16d94660a33	205	TIMER3_IRQn = 15,/* 15 TIMER3 */
Jasper_lee	0:b16d94660a33	206	MCPWM_IRQn = 16,/* 16 MCPWM */
Jasper_lee	0:b16d94660a33	207	ADC0_IRQn = 17,/* 17 ADC0 */
Jasper_lee	0:b16d94660a33	208	I2C0_IRQn = 18,/* 18 I2C0 */
Jasper_lee	0:b16d94660a33	209	I2C1_IRQn = 19,/* 19 I2C1 */
Jasper_lee	0:b16d94660a33	210	RESERVED3_IRQn = 20,
Jasper_lee	0:b16d94660a33	211	ADC1_IRQn = 21,/* 21 ADC1 */
Jasper_lee	0:b16d94660a33	212	SSP0_IRQn = 22,/* 22 SSP0 */
Jasper_lee	0:b16d94660a33	213	SSP1_IRQn = 23,/* 23 SSP1 */
Jasper_lee	0:b16d94660a33	214	USART0_IRQn = 24,/* 24 USART0 */
Jasper_lee	0:b16d94660a33	215	UART1_IRQn = 25,/* 25 UART1 */
Jasper_lee	0:b16d94660a33	216	USART2_IRQn = 26,/* 26 USART2 */
Jasper_lee	0:b16d94660a33	217	USART3_IRQn = 27,/* 27 USART3 */
Jasper_lee	0:b16d94660a33	218	I2S0_IRQn = 28,/* 28 I2S0 */
Jasper_lee	0:b16d94660a33	219	I2S1_IRQn = 29,/* 29 I2S1 */
Jasper_lee	0:b16d94660a33	220	RESERVED4_IRQn = 30,
Jasper_lee	0:b16d94660a33	221	RESERVED5_IRQn = 31,
Jasper_lee	0:b16d94660a33	222	PIN_INT0_IRQn = 32,/* 32 PIN_INT0 */
Jasper_lee	0:b16d94660a33	223	PIN_INT1_IRQn = 33,/* 33 PIN_INT1 */
Jasper_lee	0:b16d94660a33	224	PIN_INT2_IRQn = 34,/* 34 PIN_INT2 */
Jasper_lee	0:b16d94660a33	225	PIN_INT3_IRQn = 35,/* 35 PIN_INT3 */
Jasper_lee	0:b16d94660a33	226	PIN_INT4_IRQn = 36,/* 36 PIN_INT4 */
Jasper_lee	0:b16d94660a33	227	PIN_INT5_IRQn = 37,/* 37 PIN_INT5 */
Jasper_lee	0:b16d94660a33	228	PIN_INT6_IRQn = 38,/* 38 PIN_INT6 */
Jasper_lee	0:b16d94660a33	229	PIN_INT7_IRQn = 39,/* 39 PIN_INT7 */
Jasper_lee	0:b16d94660a33	230	GINT0_IRQn = 40,/* 40 GINT0 */
Jasper_lee	0:b16d94660a33	231	GINT1_IRQn = 41,/* 41 GINT1 */
Jasper_lee	0:b16d94660a33	232	EVENTROUTER_IRQn = 42,/* 42 EVENTROUTER */
Jasper_lee	0:b16d94660a33	233	C_CAN1_IRQn = 43,/* 43 C_CAN1 */
Jasper_lee	0:b16d94660a33	234	RESERVED6_IRQn = 44,
Jasper_lee	0:b16d94660a33	235	RESERVED7_IRQn = 45,/* 45 VADC */
Jasper_lee	0:b16d94660a33	236	ATIMER_IRQn = 46,/* 46 ATIMER */
Jasper_lee	0:b16d94660a33	237	RTC_IRQn = 47,/* 47 RTC */
Jasper_lee	0:b16d94660a33	238	RESERVED8_IRQn = 48,
Jasper_lee	0:b16d94660a33	239	WWDT_IRQn = 49,/* 49 WWDT */
Jasper_lee	0:b16d94660a33	240	RESERVED9_IRQn = 50,
Jasper_lee	0:b16d94660a33	241	C_CAN0_IRQn = 51,/* 51 C_CAN0 */
Jasper_lee	0:b16d94660a33	242	QEI_IRQn = 52,/* 52 QEI */
Jasper_lee	0:b16d94660a33	243	} IRQn_Type;
Jasper_lee	0:b16d94660a33	244
Jasper_lee	0:b16d94660a33	245	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
Jasper_lee	0:b16d94660a33	246
Jasper_lee	0:b16d94660a33	247	#elif defined(CORE_M0)
Jasper_lee	0:b16d94660a33	248	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	249	* LPC43xx (M0 Core) Cortex CMSIS definitions
Jasper_lee	0:b16d94660a33	250	*/
Jasper_lee	0:b16d94660a33	251
Jasper_lee	0:b16d94660a33	252	#define __MPU_PRESENT 0 /* MPU present or not */
Jasper_lee	0:b16d94660a33	253	#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
Jasper_lee	0:b16d94660a33	254	#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
Jasper_lee	0:b16d94660a33	255	#define __FPU_PRESENT 0 /* FPU present or not */
Jasper_lee	0:b16d94660a33	256	#define CHIP_LPC43XX /* LPCOPEN compatibility */
Jasper_lee	0:b16d94660a33	257
Jasper_lee	0:b16d94660a33	258	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	259	* LPC43xx (M0 Core) peripheral interrupt numbers
Jasper_lee	0:b16d94660a33	260	*/
Jasper_lee	0:b16d94660a33	261
Jasper_lee	0:b16d94660a33	262	typedef enum {
Jasper_lee	0:b16d94660a33	263	/* --------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Jasper_lee	0:b16d94660a33	264	Reset_IRQn = -15,/* 1 Reset Vector, invoked on Power up and warm reset */
Jasper_lee	0:b16d94660a33	265	NonMaskableInt_IRQn = -14,/* 2 Non maskable Interrupt, cannot be stopped or preempted */
Jasper_lee	0:b16d94660a33	266	HardFault_IRQn = -13,/* 3 Hard Fault, all classes of Fault */
Jasper_lee	0:b16d94660a33	267	SVCall_IRQn = -5,/* 11 System Service Call via SVC instruction */
Jasper_lee	0:b16d94660a33	268	DebugMonitor_IRQn = -4,/* 12 Debug Monitor */
Jasper_lee	0:b16d94660a33	269	PendSV_IRQn = -2,/* 14 Pendable request for system service */
Jasper_lee	0:b16d94660a33	270	SysTick_IRQn = -1,/* 15 System Tick Timer */
Jasper_lee	0:b16d94660a33	271
Jasper_lee	0:b16d94660a33	272	/* ----------------- LPC18xx/43xx Specific Interrupt Numbers --------------------- */
Jasper_lee	0:b16d94660a33	273	DAC_IRQn = 0,/* 0 DAC */
Jasper_lee	0:b16d94660a33	274	M0_M4CORE_IRQn = 1,/* 1 M0a */
Jasper_lee	0:b16d94660a33	275	DMA_IRQn = 2,/* 2 DMA r */
Jasper_lee	0:b16d94660a33	276	RESERVED1_IRQn = 3,/* 3 EZH/EDM */
Jasper_lee	0:b16d94660a33	277	FLASHEEPROM_IRQn = 4,/* 4 ORed Flash EEPROM Bank A, B, EEPROM */
Jasper_lee	0:b16d94660a33	278	ETHERNET_IRQn = 5,/* 5 ETHERNET */
Jasper_lee	0:b16d94660a33	279	SDIO_IRQn = 6,/* 6 SDIO */
Jasper_lee	0:b16d94660a33	280	LCD_IRQn = 7,/* 7 LCD */
Jasper_lee	0:b16d94660a33	281	USB0_IRQn = 8,/* 8 USB0 */
Jasper_lee	0:b16d94660a33	282	USB1_IRQn = 9,/* 9 USB1 */
Jasper_lee	0:b16d94660a33	283	SCT_IRQn = 10,/* 10 SCT */
Jasper_lee	0:b16d94660a33	284	RITIMER_IRQn = 11,/* 11 ORed RITIMER, WDT */
Jasper_lee	0:b16d94660a33	285	TIMER0_IRQn = 12,/* 12 TIMER0 */
Jasper_lee	0:b16d94660a33	286	GINT1_IRQn = 13,/* 13 GINT1 */
Jasper_lee	0:b16d94660a33	287	PIN_INT4_IRQn = 14,/* 14 GPIO 4 */
Jasper_lee	0:b16d94660a33	288	TIMER3_IRQn = 15,/* 15 TIMER3 */
Jasper_lee	0:b16d94660a33	289	MCPWM_IRQn = 16,/* 16 MCPWM */
Jasper_lee	0:b16d94660a33	290	ADC0_IRQn = 17,/* 17 ADC0 */
Jasper_lee	0:b16d94660a33	291	I2C0_IRQn = 18,/* 18 ORed I2C0, I2C1 */
Jasper_lee	0:b16d94660a33	292	SGPIO_INT_IRQn = 19,/* 19 SGPIO */
Jasper_lee	0:b16d94660a33	293	SPI_INT_IRQn = 20,/* 20 SPI_INT */
Jasper_lee	0:b16d94660a33	294	ADC1_IRQn = 21,/* 21 ADC1 */
Jasper_lee	0:b16d94660a33	295	SSP0_IRQn = 22,/* 22 ORed SSP0, SSP1 */
Jasper_lee	0:b16d94660a33	296	EVENTROUTER_IRQn = 23,/* 23 EVENTROUTER */
Jasper_lee	0:b16d94660a33	297	USART0_IRQn = 24,/* 24 USART0 */
Jasper_lee	0:b16d94660a33	298	UART1_IRQn = 25,/* 25 UART1 */
Jasper_lee	0:b16d94660a33	299	USART2_IRQn = 26,/* 26 USART2 */
Jasper_lee	0:b16d94660a33	300	USART3_IRQn = 27,/* 27 USART3 */
Jasper_lee	0:b16d94660a33	301	I2S0_IRQn = 28,/* 28 ORed I2S0, I2S1 */
Jasper_lee	0:b16d94660a33	302	C_CAN0_IRQn = 29,/* 29 C_CAN0 */
Jasper_lee	0:b16d94660a33	303	I2S1_IRQn = 29,/* 29 I2S1 */
Jasper_lee	0:b16d94660a33	304	RESERVED2_IRQn = 30,
Jasper_lee	0:b16d94660a33	305	RESERVED3_IRQn = 31,
Jasper_lee	0:b16d94660a33	306	} IRQn_Type;
Jasper_lee	0:b16d94660a33	307
Jasper_lee	0:b16d94660a33	308	#include "core_cm0.h" /* Cortex-M4 processor and core peripherals */
Jasper_lee	0:b16d94660a33	309	#else
Jasper_lee	0:b16d94660a33	310	#error Please #define CORE_M0, CORE_M3 or CORE_M4
Jasper_lee	0:b16d94660a33	311	#endif
Jasper_lee	0:b16d94660a33	312
Jasper_lee	0:b16d94660a33	313	#include "system_LPC43xx.h"
Jasper_lee	0:b16d94660a33	314
Jasper_lee	0:b16d94660a33	315	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	316	* State Configurable Timer register block structure
Jasper_lee	0:b16d94660a33	317	*/
Jasper_lee	0:b16d94660a33	318	#define LPC_SCT_BASE 0x40000000
Jasper_lee	0:b16d94660a33	319	#define CONFIG_SCT_nEV (16) /* Number of events */
Jasper_lee	0:b16d94660a33	320	#define CONFIG_SCT_nRG (16) /* Number of match/compare registers */
Jasper_lee	0:b16d94660a33	321	#define CONFIG_SCT_nOU (16) /* Number of outputs */
Jasper_lee	0:b16d94660a33	322
Jasper_lee	0:b16d94660a33	323	typedef struct {
Jasper_lee	0:b16d94660a33	324	__IO uint32_t CONFIG; /* Configuration Register */
Jasper_lee	0:b16d94660a33	325	union {
Jasper_lee	0:b16d94660a33	326	__IO uint32_t CTRL_U; /* Control Register */
Jasper_lee	0:b16d94660a33	327	struct {
Jasper_lee	0:b16d94660a33	328	__IO uint16_t CTRL_L; /* Low control register */
Jasper_lee	0:b16d94660a33	329	__IO uint16_t CTRL_H; /* High control register */
Jasper_lee	0:b16d94660a33	330	};
Jasper_lee	0:b16d94660a33	331
Jasper_lee	0:b16d94660a33	332	};
Jasper_lee	0:b16d94660a33	333
Jasper_lee	0:b16d94660a33	334	__IO uint16_t LIMIT_L; /* limit register for counter L */
Jasper_lee	0:b16d94660a33	335	__IO uint16_t LIMIT_H; /* limit register for counter H */
Jasper_lee	0:b16d94660a33	336	__IO uint16_t HALT_L; /* halt register for counter L */
Jasper_lee	0:b16d94660a33	337	__IO uint16_t HALT_H; /* halt register for counter H */
Jasper_lee	0:b16d94660a33	338	__IO uint16_t STOP_L; /* stop register for counter L */
Jasper_lee	0:b16d94660a33	339	__IO uint16_t STOP_H; /* stop register for counter H */
Jasper_lee	0:b16d94660a33	340	__IO uint16_t START_L; /* start register for counter L */
Jasper_lee	0:b16d94660a33	341	__IO uint16_t START_H; /* start register for counter H */
Jasper_lee	0:b16d94660a33	342	uint32_t RESERVED1[10]; /* 0x03C reserved */
Jasper_lee	0:b16d94660a33	343	union {
Jasper_lee	0:b16d94660a33	344	__IO uint32_t COUNT_U; /* counter register */
Jasper_lee	0:b16d94660a33	345	struct {
Jasper_lee	0:b16d94660a33	346	__IO uint16_t COUNT_L; /* counter register for counter L */
Jasper_lee	0:b16d94660a33	347	__IO uint16_t COUNT_H; /* counter register for counter H */
Jasper_lee	0:b16d94660a33	348	};
Jasper_lee	0:b16d94660a33	349
Jasper_lee	0:b16d94660a33	350	};
Jasper_lee	0:b16d94660a33	351
Jasper_lee	0:b16d94660a33	352	__IO uint16_t STATE_L; /* state register for counter L */
Jasper_lee	0:b16d94660a33	353	__IO uint16_t STATE_H; /* state register for counter H */
Jasper_lee	0:b16d94660a33	354	__I uint32_t INPUT; /* input register */
Jasper_lee	0:b16d94660a33	355	__IO uint16_t REGMODE_L; /* match - capture registers mode register L */
Jasper_lee	0:b16d94660a33	356	__IO uint16_t REGMODE_H; /* match - capture registers mode register H */
Jasper_lee	0:b16d94660a33	357	__IO uint32_t OUTPUT; /* output register */
Jasper_lee	0:b16d94660a33	358	__IO uint32_t OUTPUTDIRCTRL; /* output counter direction Control Register */
Jasper_lee	0:b16d94660a33	359	__IO uint32_t RES; /* conflict resolution register */
Jasper_lee	0:b16d94660a33	360	__IO uint32_t DMA0REQUEST; /* DMA0 Request Register */
Jasper_lee	0:b16d94660a33	361	__IO uint32_t DMA1REQUEST; /* DMA1 Request Register */
Jasper_lee	0:b16d94660a33	362	uint32_t RESERVED2[35];
Jasper_lee	0:b16d94660a33	363	__IO uint32_t EVEN; /* event enable register */
Jasper_lee	0:b16d94660a33	364	__IO uint32_t EVFLAG; /* event flag register */
Jasper_lee	0:b16d94660a33	365	__IO uint32_t CONEN; /* conflict enable register */
Jasper_lee	0:b16d94660a33	366	__IO uint32_t CONFLAG; /* conflict flag register */
Jasper_lee	0:b16d94660a33	367	union {
Jasper_lee	0:b16d94660a33	368	__IO union { /* ... Match / Capture value */
Jasper_lee	0:b16d94660a33	369	uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
Jasper_lee	0:b16d94660a33	370	struct {
Jasper_lee	0:b16d94660a33	371	uint16_t L; /* SCTMATCH[i].L Access to L value */
Jasper_lee	0:b16d94660a33	372	uint16_t H; /* SCTMATCH[i].H Access to H value */
Jasper_lee	0:b16d94660a33	373	};
Jasper_lee	0:b16d94660a33	374
Jasper_lee	0:b16d94660a33	375	} MATCH[CONFIG_SCT_nRG];
Jasper_lee	0:b16d94660a33	376
Jasper_lee	0:b16d94660a33	377	__I union {
Jasper_lee	0:b16d94660a33	378	uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
Jasper_lee	0:b16d94660a33	379	struct {
Jasper_lee	0:b16d94660a33	380	uint16_t L; /* SCTCAP[i].L Access to L value */
Jasper_lee	0:b16d94660a33	381	uint16_t H; /* SCTCAP[i].H Access to H value */
Jasper_lee	0:b16d94660a33	382	};
Jasper_lee	0:b16d94660a33	383
Jasper_lee	0:b16d94660a33	384	} CAP[CONFIG_SCT_nRG];
Jasper_lee	0:b16d94660a33	385
Jasper_lee	0:b16d94660a33	386	};
Jasper_lee	0:b16d94660a33	387
Jasper_lee	0:b16d94660a33	388	uint32_t RESERVED3[32 - CONFIG_SCT_nRG]; /* ...-0x17C reserved */
Jasper_lee	0:b16d94660a33	389	union {
Jasper_lee	0:b16d94660a33	390	__IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
Jasper_lee	0:b16d94660a33	391	__I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
Jasper_lee	0:b16d94660a33	392	};
Jasper_lee	0:b16d94660a33	393
Jasper_lee	0:b16d94660a33	394	uint16_t RESERVED4[32 - CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
Jasper_lee	0:b16d94660a33	395	union {
Jasper_lee	0:b16d94660a33	396	__IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
Jasper_lee	0:b16d94660a33	397	__I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
Jasper_lee	0:b16d94660a33	398	};
Jasper_lee	0:b16d94660a33	399
Jasper_lee	0:b16d94660a33	400	uint16_t RESERVED5[32 - CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
Jasper_lee	0:b16d94660a33	401	union {
Jasper_lee	0:b16d94660a33	402	__IO union { /* 0x200-... Match Reload / Capture Control value */
Jasper_lee	0:b16d94660a33	403	uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
Jasper_lee	0:b16d94660a33	404	struct {
Jasper_lee	0:b16d94660a33	405	uint16_t L; /* SCTMATCHREL[i].L Access to L value */
Jasper_lee	0:b16d94660a33	406	uint16_t H; /* SCTMATCHREL[i].H Access to H value */
Jasper_lee	0:b16d94660a33	407	};
Jasper_lee	0:b16d94660a33	408
Jasper_lee	0:b16d94660a33	409	} MATCHREL[CONFIG_SCT_nRG];
Jasper_lee	0:b16d94660a33	410
Jasper_lee	0:b16d94660a33	411	__IO union {
Jasper_lee	0:b16d94660a33	412	uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
Jasper_lee	0:b16d94660a33	413	struct {
Jasper_lee	0:b16d94660a33	414	uint16_t L; /* SCTCAPCTRL[i].L Access to L value */
Jasper_lee	0:b16d94660a33	415	uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
Jasper_lee	0:b16d94660a33	416	};
Jasper_lee	0:b16d94660a33	417
Jasper_lee	0:b16d94660a33	418	} CAPCTRL[CONFIG_SCT_nRG];
Jasper_lee	0:b16d94660a33	419
Jasper_lee	0:b16d94660a33	420	};
Jasper_lee	0:b16d94660a33	421
Jasper_lee	0:b16d94660a33	422	uint32_t RESERVED6[32 - CONFIG_SCT_nRG]; /* ...-0x27C reserved */
Jasper_lee	0:b16d94660a33	423	union {
Jasper_lee	0:b16d94660a33	424	__IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
Jasper_lee	0:b16d94660a33	425	__IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
Jasper_lee	0:b16d94660a33	426	};
Jasper_lee	0:b16d94660a33	427
Jasper_lee	0:b16d94660a33	428	uint16_t RESERVED7[32 - CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
Jasper_lee	0:b16d94660a33	429	union {
Jasper_lee	0:b16d94660a33	430	__IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
Jasper_lee	0:b16d94660a33	431	__IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
Jasper_lee	0:b16d94660a33	432	};
Jasper_lee	0:b16d94660a33	433
Jasper_lee	0:b16d94660a33	434	uint16_t RESERVED8[32 - CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
Jasper_lee	0:b16d94660a33	435	__IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
Jasper_lee	0:b16d94660a33	436	uint32_t STATE; /* Event State Register */
Jasper_lee	0:b16d94660a33	437	uint32_t CTRL; /* Event Control Register */
Jasper_lee	0:b16d94660a33	438	} EVENT[CONFIG_SCT_nEV];
Jasper_lee	0:b16d94660a33	439
Jasper_lee	0:b16d94660a33	440	uint32_t RESERVED9[128 - 2 * CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
Jasper_lee	0:b16d94660a33	441	__IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
Jasper_lee	0:b16d94660a33	442	uint32_t SET; /* Output n Set Register */
Jasper_lee	0:b16d94660a33	443	uint32_t CLR; /* Output n Clear Register */
Jasper_lee	0:b16d94660a33	444	} OUT[CONFIG_SCT_nOU];
Jasper_lee	0:b16d94660a33	445
Jasper_lee	0:b16d94660a33	446	uint32_t RESERVED10[191 - 2 * CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
Jasper_lee	0:b16d94660a33	447	__I uint32_t MODULECONTENT; /* 0x7FC Module Content */
Jasper_lee	0:b16d94660a33	448	} LPC_SCT_T;
Jasper_lee	0:b16d94660a33	449
Jasper_lee	0:b16d94660a33	450	/* Macro defines for SCT configuration register */
Jasper_lee	0:b16d94660a33	451	#define SCT_CONFIG_16BIT_COUNTER 0x00000000 /* Operate as 2 16-bit counters */
Jasper_lee	0:b16d94660a33	452	#define SCT_CONFIG_32BIT_COUNTER 0x00000001 /* Operate as 1 32-bit counter */
Jasper_lee	0:b16d94660a33	453
Jasper_lee	0:b16d94660a33	454	#define SCT_CONFIG_CLKMODE_BUSCLK (0x0 << 1) /* Bus clock */
Jasper_lee	0:b16d94660a33	455	#define SCT_CONFIG_CLKMODE_SCTCLK (0x1 << 1) /* SCT clock */
Jasper_lee	0:b16d94660a33	456	#define SCT_CONFIG_CLKMODE_INCLK (0x2 << 1) /* Input clock selected in CLKSEL field */
Jasper_lee	0:b16d94660a33	457	#define SCT_CONFIG_CLKMODE_INEDGECLK (0x3 << 1) /* Input clock edge selected in CLKSEL field */
Jasper_lee	0:b16d94660a33	458
Jasper_lee	0:b16d94660a33	459	#define SCT_CONFIG_NORELOADL_U (0x1 << 7) /* Operate as 1 32-bit counter */
Jasper_lee	0:b16d94660a33	460	#define SCT_CONFIG_NORELOADH (0x1 << 8) /* Operate as 1 32-bit counter */
Jasper_lee	0:b16d94660a33	461
Jasper_lee	0:b16d94660a33	462	/* Macro defines for SCT control register */
Jasper_lee	0:b16d94660a33	463	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for low or unified counter */
Jasper_lee	0:b16d94660a33	464	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
Jasper_lee	0:b16d94660a33	465
Jasper_lee	0:b16d94660a33	466	#define SCT_CTRL_STOP_L (1 << 1) /* Stop low counter */
Jasper_lee	0:b16d94660a33	467	#define SCT_CTRL_HALT_L (1 << 2) /* Halt low counter */
Jasper_lee	0:b16d94660a33	468	#define SCT_CTRL_CLRCTR_L (1 << 3) /* Clear low or unified counter */
Jasper_lee	0:b16d94660a33	469	#define SCT_CTRL_BIDIR_L(x) (((x) & 0x01) << 4) /* Bidirectional bit */
Jasper_lee	0:b16d94660a33	470	#define SCT_CTRL_PRE_L(x) (((x) & 0xFF) << 5) /* Prescale clock for low or unified counter */
Jasper_lee	0:b16d94660a33	471
Jasper_lee	0:b16d94660a33	472	#define COUNTUP_TO_LIMIT_THEN_CLEAR_TO_ZERO 0 /* Direction for high counter */
Jasper_lee	0:b16d94660a33	473	#define COUNTUP_TO LIMIT_THEN_COUNTDOWN_TO_ZERO 1
Jasper_lee	0:b16d94660a33	474	#define SCT_CTRL_STOP_H (1 << 17) /* Stop high counter */
Jasper_lee	0:b16d94660a33	475	#define SCT_CTRL_HALT_H (1 << 18) /* Halt high counter */
Jasper_lee	0:b16d94660a33	476	#define SCT_CTRL_CLRCTR_H (1 << 19) /* Clear high counter */
Jasper_lee	0:b16d94660a33	477	#define SCT_CTRL_BIDIR_H(x) (((x) & 0x01) << 20)
Jasper_lee	0:b16d94660a33	478	#define SCT_CTRL_PRE_H(x) (((x) & 0xFF) << 21) /* Prescale clock for high counter */
Jasper_lee	0:b16d94660a33	479
Jasper_lee	0:b16d94660a33	480	/* Macro defines for SCT Conflict resolution register */
Jasper_lee	0:b16d94660a33	481	#define SCT_RES_NOCHANGE (0)
Jasper_lee	0:b16d94660a33	482	#define SCT_RES_SET_OUTPUT (1)
Jasper_lee	0:b16d94660a33	483	#define SCT_RES_CLEAR_OUTPUT (2)
Jasper_lee	0:b16d94660a33	484	#define SCT_RES_TOGGLE_OUTPUT (3)
Jasper_lee	0:b16d94660a33	485
Jasper_lee	0:b16d94660a33	486	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	487	* GPDMA Channel register block structure
Jasper_lee	0:b16d94660a33	488	*/
Jasper_lee	0:b16d94660a33	489	#define LPC_GPDMA_BASE 0x40002000
Jasper_lee	0:b16d94660a33	490
Jasper_lee	0:b16d94660a33	491	typedef struct {
Jasper_lee	0:b16d94660a33	492	__IO uint32_t SRCADDR; /* DMA Channel Source Address Register */
Jasper_lee	0:b16d94660a33	493	__IO uint32_t DESTADDR; /* DMA Channel Destination Address Register */
Jasper_lee	0:b16d94660a33	494	__IO uint32_t LLI; /* DMA Channel Linked List Item Register */
Jasper_lee	0:b16d94660a33	495	__IO uint32_t CONTROL; /* DMA Channel Control Register */
Jasper_lee	0:b16d94660a33	496	__IO uint32_t CONFIG; /* DMA Channel Configuration Register */
Jasper_lee	0:b16d94660a33	497	__I uint32_t RESERVED1[3];
Jasper_lee	0:b16d94660a33	498	} LPC_GPDMA_CH_T;
Jasper_lee	0:b16d94660a33	499
Jasper_lee	0:b16d94660a33	500	#define GPDMA_CHANNELS 8
Jasper_lee	0:b16d94660a33	501
Jasper_lee	0:b16d94660a33	502	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	503	* GPDMA register block
Jasper_lee	0:b16d94660a33	504	*/
Jasper_lee	0:b16d94660a33	505	typedef struct { /* GPDMA Structure */
Jasper_lee	0:b16d94660a33	506	__I uint32_t INTSTAT; /* DMA Interrupt Status Register */
Jasper_lee	0:b16d94660a33	507	__I uint32_t INTTCSTAT; /* DMA Interrupt Terminal Count Request Status Register */
Jasper_lee	0:b16d94660a33	508	__O uint32_t INTTCCLEAR; /* DMA Interrupt Terminal Count Request Clear Register */
Jasper_lee	0:b16d94660a33	509	__I uint32_t INTERRSTAT; /* DMA Interrupt Error Status Register */
Jasper_lee	0:b16d94660a33	510	__O uint32_t INTERRCLR; /* DMA Interrupt Error Clear Register */
Jasper_lee	0:b16d94660a33	511	__I uint32_t RAWINTTCSTAT; /* DMA Raw Interrupt Terminal Count Status Register */
Jasper_lee	0:b16d94660a33	512	__I uint32_t RAWINTERRSTAT; /* DMA Raw Error Interrupt Status Register */
Jasper_lee	0:b16d94660a33	513	__I uint32_t ENBLDCHNS; /* DMA Enabled Channel Register */
Jasper_lee	0:b16d94660a33	514	__IO uint32_t SOFTBREQ; /* DMA Software Burst Request Register */
Jasper_lee	0:b16d94660a33	515	__IO uint32_t SOFTSREQ; /* DMA Software Single Request Register */
Jasper_lee	0:b16d94660a33	516	__IO uint32_t SOFTLBREQ; /* DMA Software Last Burst Request Register */
Jasper_lee	0:b16d94660a33	517	__IO uint32_t SOFTLSREQ; /* DMA Software Last Single Request Register */
Jasper_lee	0:b16d94660a33	518	__IO uint32_t CONFIG; /* DMA Configuration Register */
Jasper_lee	0:b16d94660a33	519	__IO uint32_t SYNC; /* DMA Synchronization Register */
Jasper_lee	0:b16d94660a33	520	__I uint32_t RESERVED0[50];
Jasper_lee	0:b16d94660a33	521	LPC_GPDMA_CH_T CH[GPDMA_CHANNELS];
Jasper_lee	0:b16d94660a33	522	} LPC_GPDMA_T;
Jasper_lee	0:b16d94660a33	523
Jasper_lee	0:b16d94660a33	524	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	525	* SPIFI register block structure
Jasper_lee	0:b16d94660a33	526	*/
Jasper_lee	0:b16d94660a33	527	#define LPC_SPIFI_BASE 0x40003000
Jasper_lee	0:b16d94660a33	528
Jasper_lee	0:b16d94660a33	529	typedef struct { /* SPIFI Structure */
Jasper_lee	0:b16d94660a33	530	__IO uint32_t CTRL; /* Control register */
Jasper_lee	0:b16d94660a33	531	__IO uint32_t CMD; /* Command register */
Jasper_lee	0:b16d94660a33	532	__IO uint32_t ADDR; /* Address register */
Jasper_lee	0:b16d94660a33	533	__IO uint32_t IDATA; /* Intermediate data register */
Jasper_lee	0:b16d94660a33	534	__IO uint32_t CLIMIT; /* Cache limit register */
Jasper_lee	0:b16d94660a33	535	union {
Jasper_lee	0:b16d94660a33	536	__IO uint32_t DATA;
Jasper_lee	0:b16d94660a33	537	__IO uint16_t DATA_HWORD;
Jasper_lee	0:b16d94660a33	538	__IO uint8_t DATA_BYTE;
Jasper_lee	0:b16d94660a33	539	}; /* Data register */
Jasper_lee	0:b16d94660a33	540	__IO uint32_t MCMD; /* Memory command register */
Jasper_lee	0:b16d94660a33	541	__IO uint32_t STAT; /* Status register */
Jasper_lee	0:b16d94660a33	542	} LPC_SPIFI_T;
Jasper_lee	0:b16d94660a33	543
Jasper_lee	0:b16d94660a33	544	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	545	* SD/MMC & SDIO register block structure
Jasper_lee	0:b16d94660a33	546	*/
Jasper_lee	0:b16d94660a33	547	#define LPC_SDMMC_BASE 0x40004000
Jasper_lee	0:b16d94660a33	548
Jasper_lee	0:b16d94660a33	549	typedef struct { /* SDMMC Structure */
Jasper_lee	0:b16d94660a33	550	__IO uint32_t CTRL; /* Control Register */
Jasper_lee	0:b16d94660a33	551	__IO uint32_t PWREN; /* Power Enable Register */
Jasper_lee	0:b16d94660a33	552	__IO uint32_t CLKDIV; /* Clock Divider Register */
Jasper_lee	0:b16d94660a33	553	__IO uint32_t CLKSRC; /* SD Clock Source Register */
Jasper_lee	0:b16d94660a33	554	__IO uint32_t CLKENA; /* Clock Enable Register */
Jasper_lee	0:b16d94660a33	555	__IO uint32_t TMOUT; /* Timeout Register */
Jasper_lee	0:b16d94660a33	556	__IO uint32_t CTYPE; /* Card Type Register */
Jasper_lee	0:b16d94660a33	557	__IO uint32_t BLKSIZ; /* Block Size Register */
Jasper_lee	0:b16d94660a33	558	__IO uint32_t BYTCNT; /* Byte Count Register */
Jasper_lee	0:b16d94660a33	559	__IO uint32_t INTMASK; /* Interrupt Mask Register */
Jasper_lee	0:b16d94660a33	560	__IO uint32_t CMDARG; /* Command Argument Register */
Jasper_lee	0:b16d94660a33	561	__IO uint32_t CMD; /* Command Register */
Jasper_lee	0:b16d94660a33	562	__I uint32_t RESP0; /* Response Register 0 */
Jasper_lee	0:b16d94660a33	563	__I uint32_t RESP1; /* Response Register 1 */
Jasper_lee	0:b16d94660a33	564	__I uint32_t RESP2; /* Response Register 2 */
Jasper_lee	0:b16d94660a33	565	__I uint32_t RESP3; /* Response Register 3 */
Jasper_lee	0:b16d94660a33	566	__I uint32_t MINTSTS; /* Masked Interrupt Status Register */
Jasper_lee	0:b16d94660a33	567	__IO uint32_t RINTSTS; /* Raw Interrupt Status Register */
Jasper_lee	0:b16d94660a33	568	__I uint32_t STATUS; /* Status Register */
Jasper_lee	0:b16d94660a33	569	__IO uint32_t FIFOTH; /* FIFO Threshold Watermark Register */
Jasper_lee	0:b16d94660a33	570	__I uint32_t CDETECT; /* Card Detect Register */
Jasper_lee	0:b16d94660a33	571	__I uint32_t WRTPRT; /* Write Protect Register */
Jasper_lee	0:b16d94660a33	572	__IO uint32_t GPIO; /* General Purpose Input/Output Register */
Jasper_lee	0:b16d94660a33	573	__I uint32_t TCBCNT; /* Transferred CIU Card Byte Count Register */
Jasper_lee	0:b16d94660a33	574	__I uint32_t TBBCNT; /* Transferred Host to BIU-FIFO Byte Count Register */
Jasper_lee	0:b16d94660a33	575	__IO uint32_t DEBNCE; /* Debounce Count Register */
Jasper_lee	0:b16d94660a33	576	__IO uint32_t USRID; /* User ID Register */
Jasper_lee	0:b16d94660a33	577	__I uint32_t VERID; /* Version ID Register */
Jasper_lee	0:b16d94660a33	578	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	579	__IO uint32_t UHS_REG; /* UHS-1 Register */
Jasper_lee	0:b16d94660a33	580	__IO uint32_t RST_N; /* Hardware Reset */
Jasper_lee	0:b16d94660a33	581	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	582	__IO uint32_t BMOD; /* Bus Mode Register */
Jasper_lee	0:b16d94660a33	583	__O uint32_t PLDMND; /* Poll Demand Register */
Jasper_lee	0:b16d94660a33	584	__IO uint32_t DBADDR; /* Descriptor List Base Address Register */
Jasper_lee	0:b16d94660a33	585	__IO uint32_t IDSTS; /* Internal DMAC Status Register */
Jasper_lee	0:b16d94660a33	586	__IO uint32_t IDINTEN; /* Internal DMAC Interrupt Enable Register */
Jasper_lee	0:b16d94660a33	587	__I uint32_t DSCADDR; /* Current Host Descriptor Address Register */
Jasper_lee	0:b16d94660a33	588	__I uint32_t BUFADDR; /* Current Buffer Descriptor Address Register */
Jasper_lee	0:b16d94660a33	589	} LPC_SDMMC_T;
Jasper_lee	0:b16d94660a33	590
Jasper_lee	0:b16d94660a33	591	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	592	* External Memory Controller (EMC) register block structure
Jasper_lee	0:b16d94660a33	593	*/
Jasper_lee	0:b16d94660a33	594	#define LPC_EMC_BASE 0x40005000
Jasper_lee	0:b16d94660a33	595
Jasper_lee	0:b16d94660a33	596	typedef struct { /* EMC Structure */
Jasper_lee	0:b16d94660a33	597	__IO uint32_t CONTROL; /* Controls operation of the memory controller. */
Jasper_lee	0:b16d94660a33	598	__I uint32_t STATUS; /* Provides EMC status information. */
Jasper_lee	0:b16d94660a33	599	__IO uint32_t CONFIG; /* Configures operation of the memory controller. */
Jasper_lee	0:b16d94660a33	600	__I uint32_t RESERVED0[5];
Jasper_lee	0:b16d94660a33	601	__IO uint32_t DYNAMICCONTROL; /* Controls dynamic memory operation. */
Jasper_lee	0:b16d94660a33	602	__IO uint32_t DYNAMICREFRESH; /* Configures dynamic memory refresh operation. */
Jasper_lee	0:b16d94660a33	603	__IO uint32_t DYNAMICREADCONFIG; /* Configures the dynamic memory read strategy. */
Jasper_lee	0:b16d94660a33	604	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	605	__IO uint32_t DYNAMICRP; /* Selects the precharge command period. */
Jasper_lee	0:b16d94660a33	606	__IO uint32_t DYNAMICRAS; /* Selects the active to precharge command period. */
Jasper_lee	0:b16d94660a33	607	__IO uint32_t DYNAMICSREX; /* Selects the self-refresh exit time. */
Jasper_lee	0:b16d94660a33	608	__IO uint32_t DYNAMICAPR; /* Selects the last-data-out to active command time. */
Jasper_lee	0:b16d94660a33	609	__IO uint32_t DYNAMICDAL; /* Selects the data-in to active command time. */
Jasper_lee	0:b16d94660a33	610	__IO uint32_t DYNAMICWR; /* Selects the write recovery time. */
Jasper_lee	0:b16d94660a33	611	__IO uint32_t DYNAMICRC; /* Selects the active to active command period. */
Jasper_lee	0:b16d94660a33	612	__IO uint32_t DYNAMICRFC; /* Selects the auto-refresh period. */
Jasper_lee	0:b16d94660a33	613	__IO uint32_t DYNAMICXSR; /* Selects the exit self-refresh to active command time. */
Jasper_lee	0:b16d94660a33	614	__IO uint32_t DYNAMICRRD; /* Selects the active bank A to active bank B latency. */
Jasper_lee	0:b16d94660a33	615	__IO uint32_t DYNAMICMRD; /* Selects the load mode register to active command time. */
Jasper_lee	0:b16d94660a33	616	__I uint32_t RESERVED2[9];
Jasper_lee	0:b16d94660a33	617	__IO uint32_t STATICEXTENDEDWAIT; /* Selects time for long static memory read and write transfers. */
Jasper_lee	0:b16d94660a33	618	__I uint32_t RESERVED3[31];
Jasper_lee	0:b16d94660a33	619	__IO uint32_t DYNAMICCONFIG0; /* Selects the configuration information for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	620	__IO uint32_t DYNAMICRASCAS0; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	621	__I uint32_t RESERVED4[6];
Jasper_lee	0:b16d94660a33	622	__IO uint32_t DYNAMICCONFIG1; /* Selects the configuration information for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	623	__IO uint32_t DYNAMICRASCAS1; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	624	__I uint32_t RESERVED5[6];
Jasper_lee	0:b16d94660a33	625	__IO uint32_t DYNAMICCONFIG2; /* Selects the configuration information for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	626	__IO uint32_t DYNAMICRASCAS2; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	627	__I uint32_t RESERVED6[6];
Jasper_lee	0:b16d94660a33	628	__IO uint32_t DYNAMICCONFIG3; /* Selects the configuration information for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	629	__IO uint32_t DYNAMICRASCAS3; /* Selects the RAS and CAS latencies for dynamic memory chip select n. */
Jasper_lee	0:b16d94660a33	630	__I uint32_t RESERVED7[38];
Jasper_lee	0:b16d94660a33	631	__IO uint32_t STATICCONFIG0; /* Selects the memory configuration for static chip select n. */
Jasper_lee	0:b16d94660a33	632	__IO uint32_t STATICWAITWEN0; /* Selects the delay from chip select n to write enable. */
Jasper_lee	0:b16d94660a33	633	__IO uint32_t STATICWAITOEN0; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
Jasper_lee	0:b16d94660a33	634	__IO uint32_t STATICWAITRD0; /* Selects the delay from chip select n to a read access. */
Jasper_lee	0:b16d94660a33	635	__IO uint32_t STATICWAITPAG0; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
Jasper_lee	0:b16d94660a33	636	__IO uint32_t STATICWAITWR0; /* Selects the delay from chip select n to a write access. */
Jasper_lee	0:b16d94660a33	637	__IO uint32_t STATICWAITTURN0; /* Selects bus turnaround cycles */
Jasper_lee	0:b16d94660a33	638	__I uint32_t RESERVED8;
Jasper_lee	0:b16d94660a33	639	__IO uint32_t STATICCONFIG1; /* Selects the memory configuration for static chip select n. */
Jasper_lee	0:b16d94660a33	640	__IO uint32_t STATICWAITWEN1; /* Selects the delay from chip select n to write enable. */
Jasper_lee	0:b16d94660a33	641	__IO uint32_t STATICWAITOEN1; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
Jasper_lee	0:b16d94660a33	642	__IO uint32_t STATICWAITRD1; /* Selects the delay from chip select n to a read access. */
Jasper_lee	0:b16d94660a33	643	__IO uint32_t STATICWAITPAG1; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
Jasper_lee	0:b16d94660a33	644	__IO uint32_t STATICWAITWR1; /* Selects the delay from chip select n to a write access. */
Jasper_lee	0:b16d94660a33	645	__IO uint32_t STATICWAITTURN1; /* Selects bus turnaround cycles */
Jasper_lee	0:b16d94660a33	646	__I uint32_t RESERVED9;
Jasper_lee	0:b16d94660a33	647	__IO uint32_t STATICCONFIG2; /* Selects the memory configuration for static chip select n. */
Jasper_lee	0:b16d94660a33	648	__IO uint32_t STATICWAITWEN2; /* Selects the delay from chip select n to write enable. */
Jasper_lee	0:b16d94660a33	649	__IO uint32_t STATICWAITOEN2; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
Jasper_lee	0:b16d94660a33	650	__IO uint32_t STATICWAITRD2; /* Selects the delay from chip select n to a read access. */
Jasper_lee	0:b16d94660a33	651	__IO uint32_t STATICWAITPAG2; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
Jasper_lee	0:b16d94660a33	652	__IO uint32_t STATICWAITWR2; /* Selects the delay from chip select n to a write access. */
Jasper_lee	0:b16d94660a33	653	__IO uint32_t STATICWAITTURN2; /* Selects bus turnaround cycles */
Jasper_lee	0:b16d94660a33	654	__I uint32_t RESERVED10;
Jasper_lee	0:b16d94660a33	655	__IO uint32_t STATICCONFIG3; /* Selects the memory configuration for static chip select n. */
Jasper_lee	0:b16d94660a33	656	__IO uint32_t STATICWAITWEN3; /* Selects the delay from chip select n to write enable. */
Jasper_lee	0:b16d94660a33	657	__IO uint32_t STATICWAITOEN3; /* Selects the delay from chip select n or address change, whichever is later, to output enable. */
Jasper_lee	0:b16d94660a33	658	__IO uint32_t STATICWAITRD3; /* Selects the delay from chip select n to a read access. */
Jasper_lee	0:b16d94660a33	659	__IO uint32_t STATICWAITPAG3; /* Selects the delay for asynchronous page mode sequential accesses for chip select n. */
Jasper_lee	0:b16d94660a33	660	__IO uint32_t STATICWAITWR3; /* Selects the delay from chip select n to a write access. */
Jasper_lee	0:b16d94660a33	661	__IO uint32_t STATICWAITTURN3; /* Selects bus turnaround cycles */
Jasper_lee	0:b16d94660a33	662	} LPC_EMC_T;
Jasper_lee	0:b16d94660a33	663
Jasper_lee	0:b16d94660a33	664	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	665	* USB High-Speed register block structure
Jasper_lee	0:b16d94660a33	666	*/
Jasper_lee	0:b16d94660a33	667	#define LPC_USB0_BASE 0x40006000
Jasper_lee	0:b16d94660a33	668	#define LPC_USB1_BASE 0x40007000
Jasper_lee	0:b16d94660a33	669
Jasper_lee	0:b16d94660a33	670	typedef struct { /* USB Structure */
Jasper_lee	0:b16d94660a33	671	__I uint32_t RESERVED0[64];
Jasper_lee	0:b16d94660a33	672	__I uint32_t CAPLENGTH; /* Capability register length */
Jasper_lee	0:b16d94660a33	673	__I uint32_t HCSPARAMS; /* Host controller structural parameters */
Jasper_lee	0:b16d94660a33	674	__I uint32_t HCCPARAMS; /* Host controller capability parameters */
Jasper_lee	0:b16d94660a33	675	__I uint32_t RESERVED1[5];
Jasper_lee	0:b16d94660a33	676	__I uint32_t DCIVERSION; /* Device interface version number */
Jasper_lee	0:b16d94660a33	677	__I uint32_t RESERVED2[7];
Jasper_lee	0:b16d94660a33	678	union {
Jasper_lee	0:b16d94660a33	679	__IO uint32_t USBCMD_H; /* USB command (host mode) */
Jasper_lee	0:b16d94660a33	680	__IO uint32_t USBCMD_D; /* USB command (device mode) */
Jasper_lee	0:b16d94660a33	681	};
Jasper_lee	0:b16d94660a33	682
Jasper_lee	0:b16d94660a33	683	union {
Jasper_lee	0:b16d94660a33	684	__IO uint32_t USBSTS_H; /* USB status (host mode) */
Jasper_lee	0:b16d94660a33	685	__IO uint32_t USBSTS_D; /* USB status (device mode) */
Jasper_lee	0:b16d94660a33	686	};
Jasper_lee	0:b16d94660a33	687
Jasper_lee	0:b16d94660a33	688	union {
Jasper_lee	0:b16d94660a33	689	__IO uint32_t USBINTR_H; /* USB interrupt enable (host mode) */
Jasper_lee	0:b16d94660a33	690	__IO uint32_t USBINTR_D; /* USB interrupt enable (device mode) */
Jasper_lee	0:b16d94660a33	691	};
Jasper_lee	0:b16d94660a33	692
Jasper_lee	0:b16d94660a33	693	union {
Jasper_lee	0:b16d94660a33	694	__IO uint32_t FRINDEX_H; /* USB frame index (host mode) */
Jasper_lee	0:b16d94660a33	695	__I uint32_t FRINDEX_D; /* USB frame index (device mode) */
Jasper_lee	0:b16d94660a33	696	};
Jasper_lee	0:b16d94660a33	697
Jasper_lee	0:b16d94660a33	698	__I uint32_t RESERVED3;
Jasper_lee	0:b16d94660a33	699	union {
Jasper_lee	0:b16d94660a33	700	__IO uint32_t PERIODICLISTBASE; /* Frame list base address */
Jasper_lee	0:b16d94660a33	701	__IO uint32_t DEVICEADDR; /* USB device address */
Jasper_lee	0:b16d94660a33	702	};
Jasper_lee	0:b16d94660a33	703
Jasper_lee	0:b16d94660a33	704	union {
Jasper_lee	0:b16d94660a33	705	__IO uint32_t ASYNCLISTADDR; /* Address of endpoint list in memory (host mode) */
Jasper_lee	0:b16d94660a33	706	__IO uint32_t ENDPOINTLISTADDR; /* Address of endpoint list in memory (device mode) */
Jasper_lee	0:b16d94660a33	707	};
Jasper_lee	0:b16d94660a33	708
Jasper_lee	0:b16d94660a33	709	__IO uint32_t TTCTRL; /* Asynchronous buffer status for embedded TT (host mode) */
Jasper_lee	0:b16d94660a33	710	__IO uint32_t BURSTSIZE; /* Programmable burst size */
Jasper_lee	0:b16d94660a33	711	__IO uint32_t TXFILLTUNING; /* Host transmit pre-buffer packet tuning (host mode) */
Jasper_lee	0:b16d94660a33	712	__I uint32_t RESERVED4[2];
Jasper_lee	0:b16d94660a33	713	__IO uint32_t ULPIVIEWPORT; /* ULPI viewport */
Jasper_lee	0:b16d94660a33	714	__IO uint32_t BINTERVAL; /* Length of virtual frame */
Jasper_lee	0:b16d94660a33	715	__IO uint32_t ENDPTNAK; /* Endpoint NAK (device mode) */
Jasper_lee	0:b16d94660a33	716	__IO uint32_t ENDPTNAKEN; /* Endpoint NAK Enable (device mode) */
Jasper_lee	0:b16d94660a33	717	__I uint32_t RESERVED5;
Jasper_lee	0:b16d94660a33	718	union {
Jasper_lee	0:b16d94660a33	719	__IO uint32_t PORTSC1_H; /* Port 1 status/control (host mode) */
Jasper_lee	0:b16d94660a33	720	__IO uint32_t PORTSC1_D; /* Port 1 status/control (device mode) */
Jasper_lee	0:b16d94660a33	721	};
Jasper_lee	0:b16d94660a33	722
Jasper_lee	0:b16d94660a33	723	__I uint32_t RESERVED6[7];
Jasper_lee	0:b16d94660a33	724	__IO uint32_t OTGSC; /* OTG status and control */
Jasper_lee	0:b16d94660a33	725	union {
Jasper_lee	0:b16d94660a33	726	__IO uint32_t USBMODE_H; /* USB mode (host mode) */
Jasper_lee	0:b16d94660a33	727	__IO uint32_t USBMODE_D; /* USB mode (device mode) */
Jasper_lee	0:b16d94660a33	728	};
Jasper_lee	0:b16d94660a33	729
Jasper_lee	0:b16d94660a33	730	__IO uint32_t ENDPTSETUPSTAT; /* Endpoint setup status */
Jasper_lee	0:b16d94660a33	731	__IO uint32_t ENDPTPRIME; /* Endpoint initialization */
Jasper_lee	0:b16d94660a33	732	__IO uint32_t ENDPTFLUSH; /* Endpoint de-initialization */
Jasper_lee	0:b16d94660a33	733	__I uint32_t ENDPTSTAT; /* Endpoint status */
Jasper_lee	0:b16d94660a33	734	__IO uint32_t ENDPTCOMPLETE; /* Endpoint complete */
Jasper_lee	0:b16d94660a33	735	__IO uint32_t ENDPTCTRL[6]; /* Endpoint control 0 */
Jasper_lee	0:b16d94660a33	736	} LPC_USBHS_T;
Jasper_lee	0:b16d94660a33	737
Jasper_lee	0:b16d94660a33	738	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	739	* LCD Controller register block structure
Jasper_lee	0:b16d94660a33	740	*/
Jasper_lee	0:b16d94660a33	741	#define LPC_LCD_BASE 0x40008000
Jasper_lee	0:b16d94660a33	742
Jasper_lee	0:b16d94660a33	743	typedef struct { /* LCD Structure */
Jasper_lee	0:b16d94660a33	744	__IO uint32_t TIMH; /* Horizontal Timing Control register */
Jasper_lee	0:b16d94660a33	745	__IO uint32_t TIMV; /* Vertical Timing Control register */
Jasper_lee	0:b16d94660a33	746	__IO uint32_t POL; /* Clock and Signal Polarity Control register */
Jasper_lee	0:b16d94660a33	747	__IO uint32_t LE; /* Line End Control register */
Jasper_lee	0:b16d94660a33	748	__IO uint32_t UPBASE; /* Upper Panel Frame Base Address register */
Jasper_lee	0:b16d94660a33	749	__IO uint32_t LPBASE; /* Lower Panel Frame Base Address register */
Jasper_lee	0:b16d94660a33	750	__IO uint32_t CTRL; /* LCD Control register */
Jasper_lee	0:b16d94660a33	751	__IO uint32_t INTMSK; /* Interrupt Mask register */
Jasper_lee	0:b16d94660a33	752	__I uint32_t INTRAW; /* Raw Interrupt Status register */
Jasper_lee	0:b16d94660a33	753	__I uint32_t INTSTAT; /* Masked Interrupt Status register */
Jasper_lee	0:b16d94660a33	754	__O uint32_t INTCLR; /* Interrupt Clear register */
Jasper_lee	0:b16d94660a33	755	__I uint32_t UPCURR; /* Upper Panel Current Address Value register */
Jasper_lee	0:b16d94660a33	756	__I uint32_t LPCURR; /* Lower Panel Current Address Value register */
Jasper_lee	0:b16d94660a33	757	__I uint32_t RESERVED0[115];
Jasper_lee	0:b16d94660a33	758	__IO uint16_t PAL[256]; /* 256x16-bit Color Palette registers */
Jasper_lee	0:b16d94660a33	759	__I uint32_t RESERVED1[256];
Jasper_lee	0:b16d94660a33	760	__IO uint32_t CRSR_IMG[256];/* Cursor Image registers */
Jasper_lee	0:b16d94660a33	761	__IO uint32_t CRSR_CTRL; /* Cursor Control register */
Jasper_lee	0:b16d94660a33	762	__IO uint32_t CRSR_CFG; /* Cursor Configuration register */
Jasper_lee	0:b16d94660a33	763	__IO uint32_t CRSR_PAL0; /* Cursor Palette register 0 */
Jasper_lee	0:b16d94660a33	764	__IO uint32_t CRSR_PAL1; /* Cursor Palette register 1 */
Jasper_lee	0:b16d94660a33	765	__IO uint32_t CRSR_XY; /* Cursor XY Position register */
Jasper_lee	0:b16d94660a33	766	__IO uint32_t CRSR_CLIP; /* Cursor Clip Position register */
Jasper_lee	0:b16d94660a33	767	__I uint32_t RESERVED2[2];
Jasper_lee	0:b16d94660a33	768	__IO uint32_t CRSR_INTMSK; /* Cursor Interrupt Mask register */
Jasper_lee	0:b16d94660a33	769	__O uint32_t CRSR_INTCLR; /* Cursor Interrupt Clear register */
Jasper_lee	0:b16d94660a33	770	__I uint32_t CRSR_INTRAW; /* Cursor Raw Interrupt Status register */
Jasper_lee	0:b16d94660a33	771	__I uint32_t CRSR_INTSTAT;/* Cursor Masked Interrupt Status register */
Jasper_lee	0:b16d94660a33	772	} LPC_LCD_T;
Jasper_lee	0:b16d94660a33	773
Jasper_lee	0:b16d94660a33	774	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	775	* EEPROM register block structure
Jasper_lee	0:b16d94660a33	776	*/
Jasper_lee	0:b16d94660a33	777	#define LPC_EEPROM_BASE 0x4000E000
Jasper_lee	0:b16d94660a33	778
Jasper_lee	0:b16d94660a33	779	typedef struct { /* EEPROM Structure */
Jasper_lee	0:b16d94660a33	780	__IO uint32_t CMD; /* EEPROM command register */
Jasper_lee	0:b16d94660a33	781	uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	782	__IO uint32_t RWSTATE; /* EEPROM read wait state register */
Jasper_lee	0:b16d94660a33	783	__IO uint32_t AUTOPROG; /* EEPROM auto programming register */
Jasper_lee	0:b16d94660a33	784	__IO uint32_t WSTATE; /* EEPROM wait state register */
Jasper_lee	0:b16d94660a33	785	__IO uint32_t CLKDIV; /* EEPROM clock divider register */
Jasper_lee	0:b16d94660a33	786	__IO uint32_t PWRDWN; /* EEPROM power-down register */
Jasper_lee	0:b16d94660a33	787	uint32_t RESERVED2[1007];
Jasper_lee	0:b16d94660a33	788	__O uint32_t INTENCLR; /* EEPROM interrupt enable clear */
Jasper_lee	0:b16d94660a33	789	__O uint32_t INTENSET; /* EEPROM interrupt enable set */
Jasper_lee	0:b16d94660a33	790	__I uint32_t INTSTAT; /* EEPROM interrupt status */
Jasper_lee	0:b16d94660a33	791	__I uint32_t INTEN; /* EEPROM interrupt enable */
Jasper_lee	0:b16d94660a33	792	__O uint32_t INTSTATCLR; /* EEPROM interrupt status clear */
Jasper_lee	0:b16d94660a33	793	__O uint32_t INTSTATSET; /* EEPROM interrupt status set */
Jasper_lee	0:b16d94660a33	794	} LPC_EEPROM_T;
Jasper_lee	0:b16d94660a33	795
Jasper_lee	0:b16d94660a33	796	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	797	* 10/100 MII & RMII Ethernet with timestamping register block structure
Jasper_lee	0:b16d94660a33	798	*/
Jasper_lee	0:b16d94660a33	799	#define LPC_ETHERNET_BASE 0x40010000
Jasper_lee	0:b16d94660a33	800
Jasper_lee	0:b16d94660a33	801	typedef struct { /* ETHERNET Structure */
Jasper_lee	0:b16d94660a33	802	__IO uint32_t MAC_CONFIG; /* MAC configuration register */
Jasper_lee	0:b16d94660a33	803	__IO uint32_t MAC_FRAME_FILTER; /* MAC frame filter */
Jasper_lee	0:b16d94660a33	804	__IO uint32_t MAC_HASHTABLE_HIGH; /* Hash table high register */
Jasper_lee	0:b16d94660a33	805	__IO uint32_t MAC_HASHTABLE_LOW; /* Hash table low register */
Jasper_lee	0:b16d94660a33	806	__IO uint32_t MAC_MII_ADDR; /* MII address register */
Jasper_lee	0:b16d94660a33	807	__IO uint32_t MAC_MII_DATA; /* MII data register */
Jasper_lee	0:b16d94660a33	808	__IO uint32_t MAC_FLOW_CTRL; /* Flow control register */
Jasper_lee	0:b16d94660a33	809	__IO uint32_t MAC_VLAN_TAG; /* VLAN tag register */
Jasper_lee	0:b16d94660a33	810	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	811	__I uint32_t MAC_DEBUG; /* Debug register */
Jasper_lee	0:b16d94660a33	812	__IO uint32_t MAC_RWAKE_FRFLT; /* Remote wake-up frame filter */
Jasper_lee	0:b16d94660a33	813	__IO uint32_t MAC_PMT_CTRL_STAT; /* PMT control and status */
Jasper_lee	0:b16d94660a33	814	__I uint32_t RESERVED1[2];
Jasper_lee	0:b16d94660a33	815	__I uint32_t MAC_INTR; /* Interrupt status register */
Jasper_lee	0:b16d94660a33	816	__IO uint32_t MAC_INTR_MASK; /* Interrupt mask register */
Jasper_lee	0:b16d94660a33	817	__IO uint32_t MAC_ADDR0_HIGH; /* MAC address 0 high register */
Jasper_lee	0:b16d94660a33	818	__IO uint32_t MAC_ADDR0_LOW; /* MAC address 0 low register */
Jasper_lee	0:b16d94660a33	819	__I uint32_t RESERVED2[430];
Jasper_lee	0:b16d94660a33	820	__IO uint32_t MAC_TIMESTP_CTRL; /* Time stamp control register */
Jasper_lee	0:b16d94660a33	821	__IO uint32_t SUBSECOND_INCR; /* Sub-second increment register */
Jasper_lee	0:b16d94660a33	822	__I uint32_t SECONDS; /* System time seconds register */
Jasper_lee	0:b16d94660a33	823	__I uint32_t NANOSECONDS; /* System time nanoseconds register */
Jasper_lee	0:b16d94660a33	824	__IO uint32_t SECONDSUPDATE; /* System time seconds update register */
Jasper_lee	0:b16d94660a33	825	__IO uint32_t NANOSECONDSUPDATE; /* System time nanoseconds update register */
Jasper_lee	0:b16d94660a33	826	__IO uint32_t ADDEND; /* Time stamp addend register */
Jasper_lee	0:b16d94660a33	827	__IO uint32_t TARGETSECONDS; /* Target time seconds register */
Jasper_lee	0:b16d94660a33	828	__IO uint32_t TARGETNANOSECONDS; /* Target time nanoseconds register */
Jasper_lee	0:b16d94660a33	829	__IO uint32_t HIGHWORD; /* System time higher word seconds register */
Jasper_lee	0:b16d94660a33	830	__I uint32_t TIMESTAMPSTAT; /* Time stamp status register */
Jasper_lee	0:b16d94660a33	831	__IO uint32_t PPSCTRL; /* PPS control register */
Jasper_lee	0:b16d94660a33	832	__I uint32_t AUXNANOSECONDS; /* Auxiliary time stamp nanoseconds register */
Jasper_lee	0:b16d94660a33	833	__I uint32_t AUXSECONDS; /* Auxiliary time stamp seconds register */
Jasper_lee	0:b16d94660a33	834	__I uint32_t RESERVED3[562];
Jasper_lee	0:b16d94660a33	835	__IO uint32_t DMA_BUS_MODE; /* Bus Mode Register */
Jasper_lee	0:b16d94660a33	836	__IO uint32_t DMA_TRANS_POLL_DEMAND; /* Transmit poll demand register */
Jasper_lee	0:b16d94660a33	837	__IO uint32_t DMA_REC_POLL_DEMAND; /* Receive poll demand register */
Jasper_lee	0:b16d94660a33	838	__IO uint32_t DMA_REC_DES_ADDR; /* Receive descriptor list address register */
Jasper_lee	0:b16d94660a33	839	__IO uint32_t DMA_TRANS_DES_ADDR; /* Transmit descriptor list address register */
Jasper_lee	0:b16d94660a33	840	__IO uint32_t DMA_STAT; /* Status register */
Jasper_lee	0:b16d94660a33	841	__IO uint32_t DMA_OP_MODE; /* Operation mode register */
Jasper_lee	0:b16d94660a33	842	__IO uint32_t DMA_INT_EN; /* Interrupt enable register */
Jasper_lee	0:b16d94660a33	843	__I uint32_t DMA_MFRM_BUFOF; /* Missed frame and buffer overflow register */
Jasper_lee	0:b16d94660a33	844	__IO uint32_t DMA_REC_INT_WDT; /* Receive interrupt watchdog timer register */
Jasper_lee	0:b16d94660a33	845	__I uint32_t RESERVED4[8];
Jasper_lee	0:b16d94660a33	846	__I uint32_t DMA_CURHOST_TRANS_DES; /* Current host transmit descriptor register */
Jasper_lee	0:b16d94660a33	847	__I uint32_t DMA_CURHOST_REC_DES; /* Current host receive descriptor register */
Jasper_lee	0:b16d94660a33	848	__I uint32_t DMA_CURHOST_TRANS_BUF; /* Current host transmit buffer address register */
Jasper_lee	0:b16d94660a33	849	__I uint32_t DMA_CURHOST_REC_BUF; /* Current host receive buffer address register */
Jasper_lee	0:b16d94660a33	850	} LPC_ENET_T;
Jasper_lee	0:b16d94660a33	851
Jasper_lee	0:b16d94660a33	852	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	853	* Alarm Timer register block structure
Jasper_lee	0:b16d94660a33	854	*/
Jasper_lee	0:b16d94660a33	855	#define LPC_ATIMER_BASE 0x40040000
Jasper_lee	0:b16d94660a33	856
Jasper_lee	0:b16d94660a33	857	typedef struct { /* ATIMER Structure */
Jasper_lee	0:b16d94660a33	858	__IO uint32_t DOWNCOUNTER; /* Downcounter register */
Jasper_lee	0:b16d94660a33	859	__IO uint32_t PRESET; /* Preset value register */
Jasper_lee	0:b16d94660a33	860	__I uint32_t RESERVED0[1012];
Jasper_lee	0:b16d94660a33	861	__O uint32_t CLR_EN; /* Interrupt clear enable register */
Jasper_lee	0:b16d94660a33	862	__O uint32_t SET_EN; /* Interrupt set enable register */
Jasper_lee	0:b16d94660a33	863	__I uint32_t STATUS; /* Status register */
Jasper_lee	0:b16d94660a33	864	__I uint32_t ENABLE; /* Enable register */
Jasper_lee	0:b16d94660a33	865	__O uint32_t CLR_STAT; /* Clear register */
Jasper_lee	0:b16d94660a33	866	__O uint32_t SET_STAT; /* Set register */
Jasper_lee	0:b16d94660a33	867	} LPC_ATIMER_T;
Jasper_lee	0:b16d94660a33	868
Jasper_lee	0:b16d94660a33	869	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	870	* Register File register block structure
Jasper_lee	0:b16d94660a33	871	*/
Jasper_lee	0:b16d94660a33	872	#define LPC_REGFILE_BASE 0x40041000
Jasper_lee	0:b16d94660a33	873
Jasper_lee	0:b16d94660a33	874	typedef struct {
Jasper_lee	0:b16d94660a33	875	__IO uint32_t REGFILE[64]; /* General purpose storage register */
Jasper_lee	0:b16d94660a33	876	} LPC_REGFILE_T;
Jasper_lee	0:b16d94660a33	877
Jasper_lee	0:b16d94660a33	878	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	879	* Power Management Controller register block structure
Jasper_lee	0:b16d94660a33	880	*/
Jasper_lee	0:b16d94660a33	881	#define LPC_PMC_BASE 0x40042000
Jasper_lee	0:b16d94660a33	882
Jasper_lee	0:b16d94660a33	883	typedef struct { /* PMC Structure */
Jasper_lee	0:b16d94660a33	884	__IO uint32_t PD0_SLEEP0_HW_ENA; /* Hardware sleep event enable register */
Jasper_lee	0:b16d94660a33	885	__I uint32_t RESERVED0[6];
Jasper_lee	0:b16d94660a33	886	__IO uint32_t PD0_SLEEP0_MODE; /* Sleep power mode register */
Jasper_lee	0:b16d94660a33	887	} LPC_PMC_T;
Jasper_lee	0:b16d94660a33	888
Jasper_lee	0:b16d94660a33	889	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	890	* CREG Register Block
Jasper_lee	0:b16d94660a33	891	*/
Jasper_lee	0:b16d94660a33	892	#define LPC_CREG_BASE 0x40043000
Jasper_lee	0:b16d94660a33	893
Jasper_lee	0:b16d94660a33	894	typedef struct { /* CREG Structure */
Jasper_lee	0:b16d94660a33	895	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	896	__IO uint32_t CREG0; /* Chip configuration register 32 kHz oscillator output and BOD control register. */
Jasper_lee	0:b16d94660a33	897	__I uint32_t RESERVED1[62];
Jasper_lee	0:b16d94660a33	898	__IO uint32_t MXMEMMAP; /* ARM Cortex-M3/M4 memory mapping */
Jasper_lee	0:b16d94660a33	899	#if defined(CHIP_LPC18XX)
Jasper_lee	0:b16d94660a33	900	__I uint32_t RESERVED2[5];
Jasper_lee	0:b16d94660a33	901	#else
Jasper_lee	0:b16d94660a33	902	__I uint32_t RESERVED2;
Jasper_lee	0:b16d94660a33	903	__I uint32_t CREG1; /* Configuration Register 1 */
Jasper_lee	0:b16d94660a33	904	__I uint32_t CREG2; /* Configuration Register 2 */
Jasper_lee	0:b16d94660a33	905	__I uint32_t CREG3; /* Configuration Register 3 */
Jasper_lee	0:b16d94660a33	906	__I uint32_t CREG4; /* Configuration Register 4 */
Jasper_lee	0:b16d94660a33	907	#endif
Jasper_lee	0:b16d94660a33	908	__IO uint32_t CREG5; /* Chip configuration register 5. Controls JTAG access. */
Jasper_lee	0:b16d94660a33	909	__IO uint32_t DMAMUX; /* DMA muxing control */
Jasper_lee	0:b16d94660a33	910	__IO uint32_t FLASHCFGA; /* Flash accelerator configuration register for flash bank A */
Jasper_lee	0:b16d94660a33	911	__IO uint32_t FLASHCFGB; /* Flash accelerator configuration register for flash bank B */
Jasper_lee	0:b16d94660a33	912	__IO uint32_t ETBCFG; /* ETB RAM configuration */
Jasper_lee	0:b16d94660a33	913	__IO uint32_t CREG6; /* Chip configuration register 6. */
Jasper_lee	0:b16d94660a33	914	#if defined(CHIP_LPC18XX)
Jasper_lee	0:b16d94660a33	915	__I uint32_t RESERVED4[52];
Jasper_lee	0:b16d94660a33	916	#else
Jasper_lee	0:b16d94660a33	917	__IO uint32_t M4TXEVENT; /* M4 IPC event register */
Jasper_lee	0:b16d94660a33	918	__I uint32_t RESERVED4[51];
Jasper_lee	0:b16d94660a33	919	#endif
Jasper_lee	0:b16d94660a33	920	__I uint32_t CHIPID; /* Part ID */
Jasper_lee	0:b16d94660a33	921	#if defined(CHIP_LPC18XX)
Jasper_lee	0:b16d94660a33	922	__I uint32_t RESERVED5[191];
Jasper_lee	0:b16d94660a33	923	#else
Jasper_lee	0:b16d94660a33	924	__I uint32_t RESERVED5[127];
Jasper_lee	0:b16d94660a33	925	__IO uint32_t M0TXEVENT; /* M0 IPC Event register */
Jasper_lee	0:b16d94660a33	926	__IO uint32_t M0APPMEMMAP; /* ARM Cortex M0 memory mapping */
Jasper_lee	0:b16d94660a33	927	__I uint32_t RESERVED6[62];
Jasper_lee	0:b16d94660a33	928	#endif
Jasper_lee	0:b16d94660a33	929	__IO uint32_t USB0FLADJ; /* USB0 frame length adjust register */
Jasper_lee	0:b16d94660a33	930	__I uint32_t RESERVED7[63];
Jasper_lee	0:b16d94660a33	931	__IO uint32_t USB1FLADJ; /* USB1 frame length adjust register */
Jasper_lee	0:b16d94660a33	932	} LPC_CREG_T;
Jasper_lee	0:b16d94660a33	933
Jasper_lee	0:b16d94660a33	934	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	935	* Event Router register structure
Jasper_lee	0:b16d94660a33	936	*/
Jasper_lee	0:b16d94660a33	937	#define LPC_EVRT_BASE 0x40044000
Jasper_lee	0:b16d94660a33	938
Jasper_lee	0:b16d94660a33	939	typedef struct { /* EVENTROUTER Structure */
Jasper_lee	0:b16d94660a33	940	__IO uint32_t HILO; /* Level configuration register */
Jasper_lee	0:b16d94660a33	941	__IO uint32_t EDGE; /* Edge configuration */
Jasper_lee	0:b16d94660a33	942	__I uint32_t RESERVED0[1012];
Jasper_lee	0:b16d94660a33	943	__O uint32_t CLR_EN; /* Event clear enable register */
Jasper_lee	0:b16d94660a33	944	__O uint32_t SET_EN; /* Event set enable register */
Jasper_lee	0:b16d94660a33	945	__I uint32_t STATUS; /* Status register */
Jasper_lee	0:b16d94660a33	946	__I uint32_t ENABLE; /* Enable register */
Jasper_lee	0:b16d94660a33	947	__O uint32_t CLR_STAT; /* Clear register */
Jasper_lee	0:b16d94660a33	948	__O uint32_t SET_STAT; /* Set register */
Jasper_lee	0:b16d94660a33	949	} LPC_EVRT_T;
Jasper_lee	0:b16d94660a33	950
Jasper_lee	0:b16d94660a33	951	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	952	* Real Time Clock register block structure
Jasper_lee	0:b16d94660a33	953	*/
Jasper_lee	0:b16d94660a33	954	#define LPC_RTC_BASE 0x40046000
Jasper_lee	0:b16d94660a33	955	#define RTC_EV_SUPPORT 1 /* Event Monitor/Recorder support */
Jasper_lee	0:b16d94660a33	956
Jasper_lee	0:b16d94660a33	957	typedef enum RTC_TIMEINDEX {
Jasper_lee	0:b16d94660a33	958	RTC_TIMETYPE_SECOND, /* Second */
Jasper_lee	0:b16d94660a33	959	RTC_TIMETYPE_MINUTE, /* Month */
Jasper_lee	0:b16d94660a33	960	RTC_TIMETYPE_HOUR, /* Hour */
Jasper_lee	0:b16d94660a33	961	RTC_TIMETYPE_DAYOFMONTH, /* Day of month */
Jasper_lee	0:b16d94660a33	962	RTC_TIMETYPE_DAYOFWEEK, /* Day of week */
Jasper_lee	0:b16d94660a33	963	RTC_TIMETYPE_DAYOFYEAR, /* Day of year */
Jasper_lee	0:b16d94660a33	964	RTC_TIMETYPE_MONTH, /* Month */
Jasper_lee	0:b16d94660a33	965	RTC_TIMETYPE_YEAR, /* Year */
Jasper_lee	0:b16d94660a33	966	RTC_TIMETYPE_LAST
Jasper_lee	0:b16d94660a33	967	} RTC_TIMEINDEX_T;
Jasper_lee	0:b16d94660a33	968
Jasper_lee	0:b16d94660a33	969	#if RTC_EV_SUPPORT
Jasper_lee	0:b16d94660a33	970	typedef enum LPC_RTC_EV_CHANNEL {
Jasper_lee	0:b16d94660a33	971	RTC_EV_CHANNEL_1 = 0,
Jasper_lee	0:b16d94660a33	972	RTC_EV_CHANNEL_2,
Jasper_lee	0:b16d94660a33	973	RTC_EV_CHANNEL_3,
Jasper_lee	0:b16d94660a33	974	RTC_EV_CHANNEL_NUM,
Jasper_lee	0:b16d94660a33	975	} LPC_RTC_EV_CHANNEL_T;
Jasper_lee	0:b16d94660a33	976	#endif /RTC_EV_SUPPORT/
Jasper_lee	0:b16d94660a33	977
Jasper_lee	0:b16d94660a33	978	typedef struct { /* RTC Structure */
Jasper_lee	0:b16d94660a33	979	__IO uint32_t ILR; /* Interrupt Location Register */
Jasper_lee	0:b16d94660a33	980	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	981	__IO uint32_t CCR; /* Clock Control Register */
Jasper_lee	0:b16d94660a33	982	__IO uint32_t CIIR; /* Counter Increment Interrupt Register */
Jasper_lee	0:b16d94660a33	983	__IO uint32_t AMR; /* Alarm Mask Register */
Jasper_lee	0:b16d94660a33	984	__I uint32_t CTIME[3]; /* Consolidated Time Register 0,1,2 */
Jasper_lee	0:b16d94660a33	985	__IO uint32_t TIME[RTC_TIMETYPE_LAST]; /* Timer field registers */
Jasper_lee	0:b16d94660a33	986	__IO uint32_t CALIBRATION; /* Calibration Value Register */
Jasper_lee	0:b16d94660a33	987	__I uint32_t RESERVED1[7];
Jasper_lee	0:b16d94660a33	988	__IO uint32_t ALRM[RTC_TIMETYPE_LAST]; /* Alarm field registers */
Jasper_lee	0:b16d94660a33	989	#if RTC_EV_SUPPORT
Jasper_lee	0:b16d94660a33	990	__IO uint32_t ERSTATUS; /* Event Monitor/Recorder Status register*/
Jasper_lee	0:b16d94660a33	991	__IO uint32_t ERCONTROL; /* Event Monitor/Recorder Control register*/
Jasper_lee	0:b16d94660a33	992	__I uint32_t ERCOUNTERS; /* Event Monitor/Recorder Counters register*/
Jasper_lee	0:b16d94660a33	993	__I uint32_t RESERVED2;
Jasper_lee	0:b16d94660a33	994	__I uint32_t ERFIRSTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder First Stamp registers*/
Jasper_lee	0:b16d94660a33	995	__I uint32_t RESERVED3;
Jasper_lee	0:b16d94660a33	996	__I uint32_t ERLASTSTAMP[RTC_EV_CHANNEL_NUM]; /* Event Monitor/Recorder Last Stamp registers*/
Jasper_lee	0:b16d94660a33	997	#endif /RTC_EV_SUPPORT/
Jasper_lee	0:b16d94660a33	998	} LPC_RTC_T;
Jasper_lee	0:b16d94660a33	999
Jasper_lee	0:b16d94660a33	1000	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1001	* LPC18XX/43XX CGU register block structure
Jasper_lee	0:b16d94660a33	1002	*/
Jasper_lee	0:b16d94660a33	1003	#define LPC_CGU_BASE 0x40050000
Jasper_lee	0:b16d94660a33	1004	#define LPC_CCU1_BASE 0x40051000
Jasper_lee	0:b16d94660a33	1005	#define LPC_CCU2_BASE 0x40052000
Jasper_lee	0:b16d94660a33	1006	/*
Jasper_lee	0:b16d94660a33	1007	* Input clocks for the CGU and can come from both external (crystal) and
Jasper_lee	0:b16d94660a33	1008	* internal (PLL) sources. Can be routed to the base clocks.
Jasper_lee	0:b16d94660a33	1009	*/
Jasper_lee	0:b16d94660a33	1010	typedef enum CGU_CLKIN {
Jasper_lee	0:b16d94660a33	1011	CLKIN_32K, /* External 32KHz input */
Jasper_lee	0:b16d94660a33	1012	CLKIN_IRC, /* Internal IRC (12MHz) input */
Jasper_lee	0:b16d94660a33	1013	CLKIN_ENET_RX, /* External ENET_RX pin input */
Jasper_lee	0:b16d94660a33	1014	CLKIN_ENET_TX, /* External ENET_TX pin input */
Jasper_lee	0:b16d94660a33	1015	CLKIN_CLKIN, /* External GPCLKIN pin input */
Jasper_lee	0:b16d94660a33	1016	CLKIN_RESERVED1,
Jasper_lee	0:b16d94660a33	1017	CLKIN_CRYSTAL, /* External (main) crystal pin input */
Jasper_lee	0:b16d94660a33	1018	CLKIN_USBPLL, /* Internal USB PLL input */
Jasper_lee	0:b16d94660a33	1019	CLKIN_AUDIOPLL, /* Internal Audio PLL input */
Jasper_lee	0:b16d94660a33	1020	CLKIN_MAINPLL, /* Internal Main PLL input */
Jasper_lee	0:b16d94660a33	1021	CLKIN_RESERVED2,
Jasper_lee	0:b16d94660a33	1022	CLKIN_RESERVED3,
Jasper_lee	0:b16d94660a33	1023	CLKIN_IDIVA, /* Internal divider A input */
Jasper_lee	0:b16d94660a33	1024	CLKIN_IDIVB, /* Internal divider B input */
Jasper_lee	0:b16d94660a33	1025	CLKIN_IDIVC, /* Internal divider C input */
Jasper_lee	0:b16d94660a33	1026	CLKIN_IDIVD, /* Internal divider D input */
Jasper_lee	0:b16d94660a33	1027	CLKIN_IDIVE, /* Internal divider E input */
Jasper_lee	0:b16d94660a33	1028	CLKINPUT_PD /* External 32KHz input */
Jasper_lee	0:b16d94660a33	1029	} CGU_CLKIN_T;
Jasper_lee	0:b16d94660a33	1030
Jasper_lee	0:b16d94660a33	1031	#define CLKIN_PLL0USB CLKIN_USBPLL
Jasper_lee	0:b16d94660a33	1032	#define CLKIN_PLL0AUDIO CLKIN_AUDIOPLL
Jasper_lee	0:b16d94660a33	1033	#define CLKIN_PLL1 CLKIN_MAINPLL
Jasper_lee	0:b16d94660a33	1034
Jasper_lee	0:b16d94660a33	1035	/*
Jasper_lee	0:b16d94660a33	1036	* CGU base clocks are clocks that are associated with a single input clock
Jasper_lee	0:b16d94660a33	1037	* and are routed out to 1 or more peripherals. For example, the CLK_BASE_PERIPH
Jasper_lee	0:b16d94660a33	1038	* clock can be configured to use the CLKIN_MAINPLL input clock, which will in
Jasper_lee	0:b16d94660a33	1039	* turn route that clock to the CLK_PERIPH_BUS, CLK_PERIPH_CORE, and
Jasper_lee	0:b16d94660a33	1040	* CLK_PERIPH_SGPIO periphral clocks.
Jasper_lee	0:b16d94660a33	1041	*/
Jasper_lee	0:b16d94660a33	1042	typedef enum CGU_BASE_CLK {
Jasper_lee	0:b16d94660a33	1043	CLK_BASE_SAFE, /* Base clock for WDT oscillator, IRC input only */
Jasper_lee	0:b16d94660a33	1044	CLK_BASE_USB0, /* Base USB clock for USB0, USB PLL input only */
Jasper_lee	0:b16d94660a33	1045	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1046	CLK_BASE_PERIPH, /* Base clock for SGPIO */
Jasper_lee	0:b16d94660a33	1047	#else
Jasper_lee	0:b16d94660a33	1048	CLK_BASE_RESERVED1,
Jasper_lee	0:b16d94660a33	1049	#endif
Jasper_lee	0:b16d94660a33	1050	CLK_BASE_USB1, /* Base USB clock for USB1 */
Jasper_lee	0:b16d94660a33	1051	CLK_BASE_MX, /* Base clock for CPU core */
Jasper_lee	0:b16d94660a33	1052	CLK_BASE_SPIFI, /* Base clock for SPIFI */
Jasper_lee	0:b16d94660a33	1053	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1054	CLK_BASE_SPI, /* Base clock for SPI */
Jasper_lee	0:b16d94660a33	1055	#else
Jasper_lee	0:b16d94660a33	1056	CLK_BASE_RESERVED2,
Jasper_lee	0:b16d94660a33	1057	#endif
Jasper_lee	0:b16d94660a33	1058	CLK_BASE_PHY_RX, /* Base clock for PHY RX */
Jasper_lee	0:b16d94660a33	1059	CLK_BASE_PHY_TX, /* Base clock for PHY TX */
Jasper_lee	0:b16d94660a33	1060	CLK_BASE_APB1, /* Base clock for APB1 group */
Jasper_lee	0:b16d94660a33	1061	CLK_BASE_APB3, /* Base clock for APB3 group */
Jasper_lee	0:b16d94660a33	1062	CLK_BASE_LCD, /* Base clock for LCD pixel clock */
Jasper_lee	0:b16d94660a33	1063	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1064	CLK_BASE_VADC, /* Base clock for VADC */
Jasper_lee	0:b16d94660a33	1065	#else
Jasper_lee	0:b16d94660a33	1066	CLK_BASE_RESERVED3,
Jasper_lee	0:b16d94660a33	1067	#endif
Jasper_lee	0:b16d94660a33	1068	CLK_BASE_SDIO, /* Base clock for SDIO */
Jasper_lee	0:b16d94660a33	1069	CLK_BASE_SSP0, /* Base clock for SSP0 */
Jasper_lee	0:b16d94660a33	1070	CLK_BASE_SSP1, /* Base clock for SSP1 */
Jasper_lee	0:b16d94660a33	1071	CLK_BASE_UART0, /* Base clock for UART0 */
Jasper_lee	0:b16d94660a33	1072	CLK_BASE_UART1, /* Base clock for UART1 */
Jasper_lee	0:b16d94660a33	1073	CLK_BASE_UART2, /* Base clock for UART2 */
Jasper_lee	0:b16d94660a33	1074	CLK_BASE_UART3, /* Base clock for UART3 */
Jasper_lee	0:b16d94660a33	1075	CLK_BASE_OUT, /* Base clock for CLKOUT pin */
Jasper_lee	0:b16d94660a33	1076	CLK_BASE_RESERVED4,
Jasper_lee	0:b16d94660a33	1077	CLK_BASE_RESERVED5,
Jasper_lee	0:b16d94660a33	1078	CLK_BASE_RESERVED6,
Jasper_lee	0:b16d94660a33	1079	CLK_BASE_RESERVED7,
Jasper_lee	0:b16d94660a33	1080	CLK_BASE_APLL, /* Base clock for audio PLL */
Jasper_lee	0:b16d94660a33	1081	CLK_BASE_CGU_OUT0, /* Base clock for CGUOUT0 pin */
Jasper_lee	0:b16d94660a33	1082	CLK_BASE_CGU_OUT1, /* Base clock for CGUOUT1 pin */
Jasper_lee	0:b16d94660a33	1083	CLK_BASE_LAST,
Jasper_lee	0:b16d94660a33	1084	CLK_BASE_NONE = CLK_BASE_LAST
Jasper_lee	0:b16d94660a33	1085	} CGU_BASE_CLK_T;
Jasper_lee	0:b16d94660a33	1086
Jasper_lee	0:b16d94660a33	1087	/*
Jasper_lee	0:b16d94660a33	1088	* CGU dividers provide an extra clock state where a specific clock can be
Jasper_lee	0:b16d94660a33	1089	* divided before being routed to a peripheral group. A divider accepts an
Jasper_lee	0:b16d94660a33	1090	* input clock and then divides it. To use the divided clock for a base clock
Jasper_lee	0:b16d94660a33	1091	* group, use the divider as the input clock for the base clock (for example,
Jasper_lee	0:b16d94660a33	1092	* use CLKIN_IDIVB, where CLKIN_MAINPLL might be the input into the divider).
Jasper_lee	0:b16d94660a33	1093	*/
Jasper_lee	0:b16d94660a33	1094	typedef enum CGU_IDIV {
Jasper_lee	0:b16d94660a33	1095	CLK_IDIV_A, /* CGU clock divider A */
Jasper_lee	0:b16d94660a33	1096	CLK_IDIV_B, /* CGU clock divider B */
Jasper_lee	0:b16d94660a33	1097	CLK_IDIV_C, /* CGU clock divider A */
Jasper_lee	0:b16d94660a33	1098	CLK_IDIV_D, /* CGU clock divider D */
Jasper_lee	0:b16d94660a33	1099	CLK_IDIV_E, /* CGU clock divider E */
Jasper_lee	0:b16d94660a33	1100	CLK_IDIV_LAST
Jasper_lee	0:b16d94660a33	1101	} CGU_IDIV_T;
Jasper_lee	0:b16d94660a33	1102
Jasper_lee	0:b16d94660a33	1103	/*
Jasper_lee	0:b16d94660a33	1104	* Peripheral clocks are individual clocks routed to peripherals. Although
Jasper_lee	0:b16d94660a33	1105	* multiple peripherals may share a same base clock, each peripheral's clock
Jasper_lee	0:b16d94660a33	1106	* can be enabled or disabled individually. Some peripheral clocks also have
Jasper_lee	0:b16d94660a33	1107	* additional dividers associated with them.
Jasper_lee	0:b16d94660a33	1108	*/
Jasper_lee	0:b16d94660a33	1109	typedef enum CCU_CLK {
Jasper_lee	0:b16d94660a33	1110	/* CCU1 clocks */
Jasper_lee	0:b16d94660a33	1111	CLK_APB3_BUS, /* APB3 bus clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1112	CLK_APB3_I2C1, /* I2C1 register/perigheral clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1113	CLK_APB3_DAC, /* DAC peripheral clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1114	CLK_APB3_ADC0, /* ADC0 register/perigheral clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1115	CLK_APB3_ADC1, /* ADC1 register/perigheral clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1116	CLK_APB3_CAN0, /* CAN0 register/perigheral clock from base clock CLK_BASE_APB3 */
Jasper_lee	0:b16d94660a33	1117	CLK_APB1_BUS = 32, /* APB1 bus clock clock from base clock CLK_BASE_APB1 */
Jasper_lee	0:b16d94660a33	1118	CLK_APB1_MOTOCON, /* Motor controller register/perigheral clock from base clock CLK_BASE_APB1 */
Jasper_lee	0:b16d94660a33	1119	CLK_APB1_I2C0, /* I2C0 register/perigheral clock from base clock CLK_BASE_APB1 */
Jasper_lee	0:b16d94660a33	1120	CLK_APB1_I2S, /* I2S register/perigheral clock from base clock CLK_BASE_APB1 */
Jasper_lee	0:b16d94660a33	1121	CLK_APB1_CAN1, /* CAN1 register/perigheral clock from base clock CLK_BASE_APB1 */
Jasper_lee	0:b16d94660a33	1122	CLK_SPIFI = 64, /* SPIFI SCKI input clock from base clock CLK_BASE_SPIFI */
Jasper_lee	0:b16d94660a33	1123	CLK_MX_BUS = 96, /* M3/M4 BUS core clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1124	CLK_MX_SPIFI, /* SPIFI register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1125	CLK_MX_GPIO, /* GPIO register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1126	CLK_MX_LCD, /* LCD register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1127	CLK_MX_ETHERNET, /* ETHERNET register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1128	CLK_MX_USB0, /* USB0 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1129	CLK_MX_EMC, /* EMC clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1130	CLK_MX_SDIO, /* SDIO register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1131	CLK_MX_DMA, /* DMA register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1132	CLK_MX_MXCORE, /* M3/M4 CPU core clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1133	RESERVED_ALIGN = CLK_MX_MXCORE + 3,
Jasper_lee	0:b16d94660a33	1134	CLK_MX_SCT, /* SCT register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1135	CLK_MX_USB1, /* USB1 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1136	CLK_MX_EMC_DIV, /* ENC divider clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1137	CLK_MX_FLASHA, /* FLASHA bank clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1138	CLK_MX_FLASHB, /* FLASHB bank clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1139	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1140	CLK_M4_M0APP, /* M0 app CPU core clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1141	CLK_MX_VADC, /* VADC clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1142	#else
Jasper_lee	0:b16d94660a33	1143	CLK_RESERVED1,
Jasper_lee	0:b16d94660a33	1144	CLK_RESERVED2,
Jasper_lee	0:b16d94660a33	1145	#endif
Jasper_lee	0:b16d94660a33	1146	CLK_MX_EEPROM, /* EEPROM clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1147	CLK_MX_WWDT = 128, /* WWDT register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1148	CLK_MX_UART0, /* UART0 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1149	CLK_MX_UART1, /* UART1 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1150	CLK_MX_SSP0, /* SSP0 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1151	CLK_MX_TIMER0, /* TIMER0 register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1152	CLK_MX_TIMER1, /* TIMER1 register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1153	CLK_MX_SCU, /* SCU register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1154	CLK_MX_CREG, /* CREG clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1155	CLK_MX_RITIMER = 160, /* RITIMER register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1156	CLK_MX_UART2, /* UART3 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1157	CLK_MX_UART3, /* UART4 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1158	CLK_MX_TIMER2, /* TIMER2 register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1159	CLK_MX_TIMER3, /* TIMER3 register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1160	CLK_MX_SSP1, /* SSP1 register clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1161	CLK_MX_QEI, /* QEI register/perigheral clock from base clock CLK_BASE_MX */
Jasper_lee	0:b16d94660a33	1162	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1163	CLK_PERIPH_BUS = 192, /* Peripheral bus clock from base clock CLK_BASE_PERIPH */
Jasper_lee	0:b16d94660a33	1164	CLK_RESERVED3,
Jasper_lee	0:b16d94660a33	1165	CLK_PERIPH_CORE, /* Peripheral core clock from base clock CLK_BASE_PERIPH */
Jasper_lee	0:b16d94660a33	1166	CLK_PERIPH_SGPIO, /* SGPIO clock from base clock CLK_BASE_PERIPH */
Jasper_lee	0:b16d94660a33	1167	#else
Jasper_lee	0:b16d94660a33	1168	CLK_RESERVED3 = 192,
Jasper_lee	0:b16d94660a33	1169	CLK_RESERVED3A,
Jasper_lee	0:b16d94660a33	1170	CLK_RESERVED4,
Jasper_lee	0:b16d94660a33	1171	CLK_RESERVED5,
Jasper_lee	0:b16d94660a33	1172	#endif
Jasper_lee	0:b16d94660a33	1173	CLK_USB0 = 224, /* USB0 clock from base clock CLK_BASE_USB0 */
Jasper_lee	0:b16d94660a33	1174	CLK_USB1 = 256, /* USB1 clock from base clock CLK_BASE_USB1 */
Jasper_lee	0:b16d94660a33	1175	#if defined(CHIP_LPC43XX)
Jasper_lee	0:b16d94660a33	1176	CLK_SPI = 288, /* SPI clock from base clock CLK_BASE_SPI */
Jasper_lee	0:b16d94660a33	1177	CLK_VADC, /* VADC clock from base clock CLK_BASE_VADC */
Jasper_lee	0:b16d94660a33	1178	#else
Jasper_lee	0:b16d94660a33	1179	CLK_RESERVED7 = 320,
Jasper_lee	0:b16d94660a33	1180	CLK_RESERVED8,
Jasper_lee	0:b16d94660a33	1181	#endif
Jasper_lee	0:b16d94660a33	1182	CLK_CCU1_LAST,
Jasper_lee	0:b16d94660a33	1183
Jasper_lee	0:b16d94660a33	1184	/* CCU2 clocks */
Jasper_lee	0:b16d94660a33	1185	CLK_CCU2_START,
Jasper_lee	0:b16d94660a33	1186	CLK_APLL = CLK_CCU2_START, /* Audio PLL clock from base clock CLK_BASE_APLL */
Jasper_lee	0:b16d94660a33	1187	RESERVED_ALIGNB = CLK_CCU2_START + 31,
Jasper_lee	0:b16d94660a33	1188	CLK_APB2_UART3, /* UART3 clock from base clock CLK_BASE_UART3 */
Jasper_lee	0:b16d94660a33	1189	RESERVED_ALIGNC = CLK_CCU2_START + 63,
Jasper_lee	0:b16d94660a33	1190	CLK_APB2_UART2, /* UART2 clock from base clock CLK_BASE_UART2 */
Jasper_lee	0:b16d94660a33	1191	RESERVED_ALIGND = CLK_CCU2_START + 95,
Jasper_lee	0:b16d94660a33	1192	CLK_APB0_UART1, /* UART1 clock from base clock CLK_BASE_UART1 */
Jasper_lee	0:b16d94660a33	1193	RESERVED_ALIGNE = CLK_CCU2_START + 127,
Jasper_lee	0:b16d94660a33	1194	CLK_APB0_UART0, /* UART0 clock from base clock CLK_BASE_UART0 */
Jasper_lee	0:b16d94660a33	1195	RESERVED_ALIGNF = CLK_CCU2_START + 159,
Jasper_lee	0:b16d94660a33	1196	CLK_APB2_SSP1, /* SSP1 clock from base clock CLK_BASE_SSP1 */
Jasper_lee	0:b16d94660a33	1197	RESERVED_ALIGNG = CLK_CCU2_START + 191,
Jasper_lee	0:b16d94660a33	1198	CLK_APB0_SSP0, /* SSP0 clock from base clock CLK_BASE_SSP0 */
Jasper_lee	0:b16d94660a33	1199	RESERVED_ALIGNH = CLK_CCU2_START + 223,
Jasper_lee	0:b16d94660a33	1200	CLK_APB2_SDIO, /* SDIO clock from base clock CLK_BASE_SDIO */
Jasper_lee	0:b16d94660a33	1201	CLK_CCU2_LAST
Jasper_lee	0:b16d94660a33	1202	} CCU_CLK_T;
Jasper_lee	0:b16d94660a33	1203
Jasper_lee	0:b16d94660a33	1204	/*
Jasper_lee	0:b16d94660a33	1205	* Audio or USB PLL selection
Jasper_lee	0:b16d94660a33	1206	*/
Jasper_lee	0:b16d94660a33	1207	typedef enum CGU_USB_AUDIO_PLL {
Jasper_lee	0:b16d94660a33	1208	CGU_USB_PLL,
Jasper_lee	0:b16d94660a33	1209	CGU_AUDIO_PLL
Jasper_lee	0:b16d94660a33	1210	} CGU_USB_AUDIO_PLL_T;
Jasper_lee	0:b16d94660a33	1211
Jasper_lee	0:b16d94660a33	1212	/*
Jasper_lee	0:b16d94660a33	1213	* PLL register block
Jasper_lee	0:b16d94660a33	1214	*/
Jasper_lee	0:b16d94660a33	1215	typedef struct {
Jasper_lee	0:b16d94660a33	1216	__I uint32_t PLL_STAT; /* PLL status register */
Jasper_lee	0:b16d94660a33	1217	__IO uint32_t PLL_CTRL; /* PLL control register */
Jasper_lee	0:b16d94660a33	1218	__IO uint32_t PLL_MDIV; /* PLL M-divider register */
Jasper_lee	0:b16d94660a33	1219	__IO uint32_t PLL_NP_DIV; /* PLL N/P-divider register */
Jasper_lee	0:b16d94660a33	1220	} CGU_PLL_REG_T;
Jasper_lee	0:b16d94660a33	1221
Jasper_lee	0:b16d94660a33	1222	typedef struct { /* (@ 0x40050000) CGU Structure */
Jasper_lee	0:b16d94660a33	1223	__I uint32_t RESERVED0[5];
Jasper_lee	0:b16d94660a33	1224	__IO uint32_t FREQ_MON; /* (@ 0x40050014) Frequency monitor register */
Jasper_lee	0:b16d94660a33	1225	__IO uint32_t XTAL_OSC_CTRL; /* (@ 0x40050018) Crystal oscillator control register */
Jasper_lee	0:b16d94660a33	1226	CGU_PLL_REG_T PLL[CGU_AUDIO_PLL + 1]; /* (@ 0x4005001C) USB and audio PLL blocks */
Jasper_lee	0:b16d94660a33	1227	__IO uint32_t PLL0AUDIO_FRAC; /* (@ 0x4005003C) PLL0 (audio) */
Jasper_lee	0:b16d94660a33	1228	__I uint32_t PLL1_STAT; /* (@ 0x40050040) PLL1 status register */
Jasper_lee	0:b16d94660a33	1229	__IO uint32_t PLL1_CTRL; /* (@ 0x40050044) PLL1 control register */
Jasper_lee	0:b16d94660a33	1230	__IO uint32_t IDIV_CTRL[CLK_IDIV_LAST];/* (@ 0x40050048) Integer divider A-E control registers */
Jasper_lee	0:b16d94660a33	1231	__IO uint32_t BASE_CLK[CLK_BASE_LAST]; /* (@ 0x4005005C) Start of base clock registers */
Jasper_lee	0:b16d94660a33	1232	} LPC_CGU_T;
Jasper_lee	0:b16d94660a33	1233
Jasper_lee	0:b16d94660a33	1234	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1235	* CCU clock config/status register pair
Jasper_lee	0:b16d94660a33	1236	*/
Jasper_lee	0:b16d94660a33	1237	typedef struct {
Jasper_lee	0:b16d94660a33	1238	__IO uint32_t CFG; /* CCU clock configuration register */
Jasper_lee	0:b16d94660a33	1239	__I uint32_t STAT; /* CCU clock status register */
Jasper_lee	0:b16d94660a33	1240	} CCU_CFGSTAT_T;
Jasper_lee	0:b16d94660a33	1241
Jasper_lee	0:b16d94660a33	1242	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1243	* CCU1 register block structure
Jasper_lee	0:b16d94660a33	1244	*/
Jasper_lee	0:b16d94660a33	1245	typedef struct { /* (@ 0x40051000) CCU1 Structure */
Jasper_lee	0:b16d94660a33	1246	__IO uint32_t PM; /* (@ 0x40051000) CCU1 power mode register */
Jasper_lee	0:b16d94660a33	1247	__I uint32_t BASE_STAT; /* (@ 0x40051004) CCU1 base clocks status register */
Jasper_lee	0:b16d94660a33	1248	__I uint32_t RESERVED0[62];
Jasper_lee	0:b16d94660a33	1249	CCU_CFGSTAT_T CLKCCU[CLK_CCU1_LAST]; /* (@ 0x40051100) Start of CCU1 clock registers */
Jasper_lee	0:b16d94660a33	1250	} LPC_CCU1_T;
Jasper_lee	0:b16d94660a33	1251
Jasper_lee	0:b16d94660a33	1252	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1253	* CCU2 register block structure
Jasper_lee	0:b16d94660a33	1254	*/
Jasper_lee	0:b16d94660a33	1255	typedef struct { /* (@ 0x40052000) CCU2 Structure */
Jasper_lee	0:b16d94660a33	1256	__IO uint32_t PM; /* (@ 0x40052000) Power mode register */
Jasper_lee	0:b16d94660a33	1257	__I uint32_t BASE_STAT; /* (@ 0x40052004) CCU base clocks status register */
Jasper_lee	0:b16d94660a33	1258	__I uint32_t RESERVED0[62];
Jasper_lee	0:b16d94660a33	1259	CCU_CFGSTAT_T CLKCCU[CLK_CCU2_LAST - CLK_CCU1_LAST]; /* (@ 0x40052100) Start of CCU2 clock registers */
Jasper_lee	0:b16d94660a33	1260	} LPC_CCU2_T;
Jasper_lee	0:b16d94660a33	1261
Jasper_lee	0:b16d94660a33	1262	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1263	* RGU register structure
Jasper_lee	0:b16d94660a33	1264	*/
Jasper_lee	0:b16d94660a33	1265	#define LPC_RGU_BASE 0x40053000
Jasper_lee	0:b16d94660a33	1266
Jasper_lee	0:b16d94660a33	1267	typedef enum RGU_RST {
Jasper_lee	0:b16d94660a33	1268	RGU_CORE_RST,
Jasper_lee	0:b16d94660a33	1269	RGU_PERIPH_RST,
Jasper_lee	0:b16d94660a33	1270	RGU_MASTER_RST,
Jasper_lee	0:b16d94660a33	1271	RGU_WWDT_RST = 4,
Jasper_lee	0:b16d94660a33	1272	RGU_CREG_RST,
Jasper_lee	0:b16d94660a33	1273	RGU_BUS_RST = 8,
Jasper_lee	0:b16d94660a33	1274	RGU_SCU_RST,
Jasper_lee	0:b16d94660a33	1275	RGU_M3_RST = 13,
Jasper_lee	0:b16d94660a33	1276	RGU_LCD_RST = 16,
Jasper_lee	0:b16d94660a33	1277	RGU_USB0_RST,
Jasper_lee	0:b16d94660a33	1278	RGU_USB1_RST,
Jasper_lee	0:b16d94660a33	1279	RGU_DMA_RST,
Jasper_lee	0:b16d94660a33	1280	RGU_SDIO_RST,
Jasper_lee	0:b16d94660a33	1281	RGU_EMC_RST,
Jasper_lee	0:b16d94660a33	1282	RGU_ETHERNET_RST,
Jasper_lee	0:b16d94660a33	1283	RGU_FLASHA_RST = 25,
Jasper_lee	0:b16d94660a33	1284	RGU_EEPROM_RST = 27,
Jasper_lee	0:b16d94660a33	1285	RGU_GPIO_RST,
Jasper_lee	0:b16d94660a33	1286	RGU_FLASHB_RST,
Jasper_lee	0:b16d94660a33	1287	RGU_TIMER0_RST = 32,
Jasper_lee	0:b16d94660a33	1288	RGU_TIMER1_RST,
Jasper_lee	0:b16d94660a33	1289	RGU_TIMER2_RST,
Jasper_lee	0:b16d94660a33	1290	RGU_TIMER3_RST,
Jasper_lee	0:b16d94660a33	1291	RGU_RITIMER_RST,
Jasper_lee	0:b16d94660a33	1292	RGU_SCT_RST,
Jasper_lee	0:b16d94660a33	1293	RGU_MOTOCONPWM_RST,
Jasper_lee	0:b16d94660a33	1294	RGU_QEI_RST,
Jasper_lee	0:b16d94660a33	1295	RGU_ADC0_RST,
Jasper_lee	0:b16d94660a33	1296	RGU_ADC1_RST,
Jasper_lee	0:b16d94660a33	1297	RGU_DAC_RST,
Jasper_lee	0:b16d94660a33	1298	RGU_UART0_RST = 44,
Jasper_lee	0:b16d94660a33	1299	RGU_UART1_RST,
Jasper_lee	0:b16d94660a33	1300	RGU_UART2_RST,
Jasper_lee	0:b16d94660a33	1301	RGU_UART3_RST,
Jasper_lee	0:b16d94660a33	1302	RGU_I2C0_RST,
Jasper_lee	0:b16d94660a33	1303	RGU_I2C1_RST,
Jasper_lee	0:b16d94660a33	1304	RGU_SSP0_RST,
Jasper_lee	0:b16d94660a33	1305	RGU_SSP1_RST,
Jasper_lee	0:b16d94660a33	1306	RGU_I2S_RST,
Jasper_lee	0:b16d94660a33	1307	RGU_SPIFI_RST,
Jasper_lee	0:b16d94660a33	1308	RGU_CAN1_RST,
Jasper_lee	0:b16d94660a33	1309	RGU_CAN0_RST,
Jasper_lee	0:b16d94660a33	1310	#ifdef CHIP_LPC43XX
Jasper_lee	0:b16d94660a33	1311	RGU_M0APP_RST,
Jasper_lee	0:b16d94660a33	1312	RGU_SGPIO_RST,
Jasper_lee	0:b16d94660a33	1313	RGU_SPI_RST,
Jasper_lee	0:b16d94660a33	1314	#endif
Jasper_lee	0:b16d94660a33	1315	RGU_LAST_RST = 63,
Jasper_lee	0:b16d94660a33	1316	} RGU_RST_T;
Jasper_lee	0:b16d94660a33	1317
Jasper_lee	0:b16d94660a33	1318	typedef struct { /* RGU Structure */
Jasper_lee	0:b16d94660a33	1319	__I uint32_t RESERVED0[64];
Jasper_lee	0:b16d94660a33	1320	__O uint32_t RESET_CTRL0; /* Reset control register 0 */
Jasper_lee	0:b16d94660a33	1321	__O uint32_t RESET_CTRL1; /* Reset control register 1 */
Jasper_lee	0:b16d94660a33	1322	__I uint32_t RESERVED1[2];
Jasper_lee	0:b16d94660a33	1323	__IO uint32_t RESET_STATUS0; /* Reset status register 0 */
Jasper_lee	0:b16d94660a33	1324	__IO uint32_t RESET_STATUS1; /* Reset status register 1 */
Jasper_lee	0:b16d94660a33	1325	__IO uint32_t RESET_STATUS2; /* Reset status register 2 */
Jasper_lee	0:b16d94660a33	1326	__IO uint32_t RESET_STATUS3; /* Reset status register 3 */
Jasper_lee	0:b16d94660a33	1327	__I uint32_t RESERVED2[12];
Jasper_lee	0:b16d94660a33	1328	__I uint32_t RESET_ACTIVE_STATUS0;/* Reset active status register 0 */
Jasper_lee	0:b16d94660a33	1329	__I uint32_t RESET_ACTIVE_STATUS1;/* Reset active status register 1 */
Jasper_lee	0:b16d94660a33	1330	__I uint32_t RESERVED3[170];
Jasper_lee	0:b16d94660a33	1331	__IO uint32_t RESET_EXT_STAT[RGU_LAST_RST + 1];/* Reset external status registers */
Jasper_lee	0:b16d94660a33	1332	} LPC_RGU_T;
Jasper_lee	0:b16d94660a33	1333
Jasper_lee	0:b16d94660a33	1334	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1335	* Windowed Watchdog register block structure
Jasper_lee	0:b16d94660a33	1336	*/
Jasper_lee	0:b16d94660a33	1337	#define LPC_WWDT_BASE 0x40080000
Jasper_lee	0:b16d94660a33	1338
Jasper_lee	0:b16d94660a33	1339	typedef struct { /* WWDT Structure */
Jasper_lee	0:b16d94660a33	1340	__IO uint32_t MOD; /* Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
Jasper_lee	0:b16d94660a33	1341	__IO uint32_t TC; /* Watchdog timer constant register. This register determines the time-out value. */
Jasper_lee	0:b16d94660a33	1342	__O uint32_t FEED; /* Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
Jasper_lee	0:b16d94660a33	1343	__I uint32_t TV; /* Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
Jasper_lee	0:b16d94660a33	1344	#ifdef WATCHDOG_CLKSEL_SUPPORT
Jasper_lee	0:b16d94660a33	1345	__IO uint32_t CLKSEL; /* Watchdog clock select register. */
Jasper_lee	0:b16d94660a33	1346	#else
Jasper_lee	0:b16d94660a33	1347	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1348	#endif
Jasper_lee	0:b16d94660a33	1349	#ifdef WATCHDOG_WINDOW_SUPPORT
Jasper_lee	0:b16d94660a33	1350	__IO uint32_t WARNINT; /* Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
Jasper_lee	0:b16d94660a33	1351	__IO uint32_t WINDOW; /* Watchdog timer window register. This register contains the Watchdog window value. */
Jasper_lee	0:b16d94660a33	1352	#endif
Jasper_lee	0:b16d94660a33	1353	} LPC_WWDT_T;
Jasper_lee	0:b16d94660a33	1354
Jasper_lee	0:b16d94660a33	1355	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1356	* USART register block structure
Jasper_lee	0:b16d94660a33	1357	*/
Jasper_lee	0:b16d94660a33	1358	#define LPC_USART0_BASE 0x40081000
Jasper_lee	0:b16d94660a33	1359	#define LPC_UART1_BASE 0x40082000
Jasper_lee	0:b16d94660a33	1360	#define LPC_USART2_BASE 0x400C1000
Jasper_lee	0:b16d94660a33	1361	#define LPC_USART3_BASE 0x400C2000
Jasper_lee	0:b16d94660a33	1362
Jasper_lee	0:b16d94660a33	1363	typedef struct { /* USARTn Structure */
Jasper_lee	0:b16d94660a33	1364
Jasper_lee	0:b16d94660a33	1365	union {
Jasper_lee	0:b16d94660a33	1366	__IO uint32_t DLL; /* Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
Jasper_lee	0:b16d94660a33	1367	__O uint32_t THR; /* Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
Jasper_lee	0:b16d94660a33	1368	__I uint32_t RBR; /* Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
Jasper_lee	0:b16d94660a33	1369	};
Jasper_lee	0:b16d94660a33	1370
Jasper_lee	0:b16d94660a33	1371	union {
Jasper_lee	0:b16d94660a33	1372	__IO uint32_t IER; /* Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
Jasper_lee	0:b16d94660a33	1373	__IO uint32_t DLM; /* Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
Jasper_lee	0:b16d94660a33	1374	};
Jasper_lee	0:b16d94660a33	1375
Jasper_lee	0:b16d94660a33	1376	union {
Jasper_lee	0:b16d94660a33	1377	__O uint32_t FCR; /* FIFO Control Register. Controls UART FIFO usage and modes. */
Jasper_lee	0:b16d94660a33	1378	__I uint32_t IIR; /* Interrupt ID Register. Identifies which interrupt(s) are pending. */
Jasper_lee	0:b16d94660a33	1379	};
Jasper_lee	0:b16d94660a33	1380
Jasper_lee	0:b16d94660a33	1381	__IO uint32_t LCR; /* Line Control Register. Contains controls for frame formatting and break generation. */
Jasper_lee	0:b16d94660a33	1382	__IO uint32_t MCR; /* Modem Control Register. Only present on USART ports with full modem support. */
Jasper_lee	0:b16d94660a33	1383	__I uint32_t LSR; /* Line Status Register. Contains flags for transmit and receive status, including line errors. */
Jasper_lee	0:b16d94660a33	1384	__I uint32_t MSR; /* Modem Status Register. Only present on USART ports with full modem support. */
Jasper_lee	0:b16d94660a33	1385	__IO uint32_t SCR; /* Scratch Pad Register. Eight-bit temporary storage for software. */
Jasper_lee	0:b16d94660a33	1386	__IO uint32_t ACR; /* Auto-baud Control Register. Contains controls for the auto-baud feature. */
Jasper_lee	0:b16d94660a33	1387	__IO uint32_t ICR; /* IrDA control register (not all UARTS) */
Jasper_lee	0:b16d94660a33	1388	__IO uint32_t FDR; /* Fractional Divider Register. Generates a clock input for the baud rate divider. */
Jasper_lee	0:b16d94660a33	1389	__IO uint32_t OSR; /* Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
Jasper_lee	0:b16d94660a33	1390	__IO uint32_t TER1; /* Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
Jasper_lee	0:b16d94660a33	1391	uint32_t RESERVED0[3];
Jasper_lee	0:b16d94660a33	1392	__IO uint32_t HDEN; /* Half-duplex enable Register- only on some UARTs */
Jasper_lee	0:b16d94660a33	1393	__I uint32_t RESERVED1[1];
Jasper_lee	0:b16d94660a33	1394	__IO uint32_t SCICTRL; /* Smart card interface control register- only on some UARTs */
Jasper_lee	0:b16d94660a33	1395	__IO uint32_t RS485CTRL; /* RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
Jasper_lee	0:b16d94660a33	1396	__IO uint32_t RS485ADRMATCH; /* RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
Jasper_lee	0:b16d94660a33	1397	__IO uint32_t RS485DLY; /* RS-485/EIA-485 direction control delay. */
Jasper_lee	0:b16d94660a33	1398	union {
Jasper_lee	0:b16d94660a33	1399	__IO uint32_t SYNCCTRL; /* Synchronous mode control register. Only on USARTs. */
Jasper_lee	0:b16d94660a33	1400	__I uint32_t FIFOLVL; /* FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
Jasper_lee	0:b16d94660a33	1401	};
Jasper_lee	0:b16d94660a33	1402
Jasper_lee	0:b16d94660a33	1403	__IO uint32_t TER2; /* Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
Jasper_lee	0:b16d94660a33	1404	} LPC_USART_T;
Jasper_lee	0:b16d94660a33	1405
Jasper_lee	0:b16d94660a33	1406	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1407	* SSP register block structure
Jasper_lee	0:b16d94660a33	1408	*/
Jasper_lee	0:b16d94660a33	1409	#define LPC_SSP0_BASE 0x40083000
Jasper_lee	0:b16d94660a33	1410	#define LPC_SSP1_BASE 0x400C5000
Jasper_lee	0:b16d94660a33	1411
Jasper_lee	0:b16d94660a33	1412	typedef struct { /* SSPn Structure */
Jasper_lee	0:b16d94660a33	1413	__IO uint32_t CR0; /* Control Register 0. Selects the serial clock rate, bus type, and data size. */
Jasper_lee	0:b16d94660a33	1414	__IO uint32_t CR1; /* Control Register 1. Selects master/slave and other modes. */
Jasper_lee	0:b16d94660a33	1415	__IO uint32_t DR; /* Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
Jasper_lee	0:b16d94660a33	1416	__I uint32_t SR; /* Status Register */
Jasper_lee	0:b16d94660a33	1417	__IO uint32_t CPSR; /* Clock Prescale Register */
Jasper_lee	0:b16d94660a33	1418	__IO uint32_t IMSC; /* Interrupt Mask Set and Clear Register */
Jasper_lee	0:b16d94660a33	1419	__I uint32_t RIS; /* Raw Interrupt Status Register */
Jasper_lee	0:b16d94660a33	1420	__I uint32_t MIS; /* Masked Interrupt Status Register */
Jasper_lee	0:b16d94660a33	1421	__O uint32_t ICR; /* SSPICR Interrupt Clear Register */
Jasper_lee	0:b16d94660a33	1422	__IO uint32_t DMACR; /* SSPn DMA control register */
Jasper_lee	0:b16d94660a33	1423	} LPC_SSP_T;
Jasper_lee	0:b16d94660a33	1424
Jasper_lee	0:b16d94660a33	1425	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1426	* 32-bit Standard timer register block structure
Jasper_lee	0:b16d94660a33	1427	*/
Jasper_lee	0:b16d94660a33	1428	#define LPC_TIMER0_BASE 0x40084000
Jasper_lee	0:b16d94660a33	1429	#define LPC_TIMER1_BASE 0x40085000
Jasper_lee	0:b16d94660a33	1430	#define LPC_TIMER2_BASE 0x400C3000
Jasper_lee	0:b16d94660a33	1431	#define LPC_TIMER3_BASE 0x400C4000
Jasper_lee	0:b16d94660a33	1432
Jasper_lee	0:b16d94660a33	1433	typedef struct { /* TIMERn Structure */
Jasper_lee	0:b16d94660a33	1434	__IO uint32_t IR; /* Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
Jasper_lee	0:b16d94660a33	1435	__IO uint32_t TCR; /* Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
Jasper_lee	0:b16d94660a33	1436	__IO uint32_t TC; /* Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
Jasper_lee	0:b16d94660a33	1437	__IO uint32_t PR; /* Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
Jasper_lee	0:b16d94660a33	1438	__IO uint32_t PC; /* Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
Jasper_lee	0:b16d94660a33	1439	__IO uint32_t MCR; /* Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
Jasper_lee	0:b16d94660a33	1440	__IO uint32_t MR[4]; /* Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
Jasper_lee	0:b16d94660a33	1441	__IO uint32_t CCR; /* Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
Jasper_lee	0:b16d94660a33	1442	__IO uint32_t CR[4]; /* Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
Jasper_lee	0:b16d94660a33	1443	__IO uint32_t EMR; /* External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
Jasper_lee	0:b16d94660a33	1444	__I uint32_t RESERVED0[12];
Jasper_lee	0:b16d94660a33	1445	__IO uint32_t CTCR; /* Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
Jasper_lee	0:b16d94660a33	1446	} LPC_TIMER_T;
Jasper_lee	0:b16d94660a33	1447
Jasper_lee	0:b16d94660a33	1448	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1449	* System Control Unit register block
Jasper_lee	0:b16d94660a33	1450	*/
Jasper_lee	0:b16d94660a33	1451	#define LPC_SCU_BASE 0x40086000
Jasper_lee	0:b16d94660a33	1452
Jasper_lee	0:b16d94660a33	1453	typedef struct {
Jasper_lee	0:b16d94660a33	1454	__IO uint32_t SFSP[16][32];
Jasper_lee	0:b16d94660a33	1455	__I uint32_t RESERVED0[256];
Jasper_lee	0:b16d94660a33	1456	__IO uint32_t SFSCLK[4]; /* Pin configuration register for pins CLK0-3 */
Jasper_lee	0:b16d94660a33	1457	__I uint32_t RESERVED16[28];
Jasper_lee	0:b16d94660a33	1458	__IO uint32_t SFSUSB; /* Pin configuration register for USB */
Jasper_lee	0:b16d94660a33	1459	__IO uint32_t SFSI2C0; /* Pin configuration register for I2C0-bus pins */
Jasper_lee	0:b16d94660a33	1460	__IO uint32_t ENAIO[3]; /* Analog function select registers */
Jasper_lee	0:b16d94660a33	1461	__I uint32_t RESERVED17[27];
Jasper_lee	0:b16d94660a33	1462	__IO uint32_t EMCDELAYCLK; /* EMC clock delay register */
Jasper_lee	0:b16d94660a33	1463	__I uint32_t RESERVED18[63];
Jasper_lee	0:b16d94660a33	1464	__IO uint32_t PINTSEL0; /* Pin interrupt select register for pin interrupts 0 to 3. */
Jasper_lee	0:b16d94660a33	1465	__IO uint32_t PINTSEL1; /* Pin interrupt select register for pin interrupts 4 to 7. */
Jasper_lee	0:b16d94660a33	1466	} LPC_SCU_T;
Jasper_lee	0:b16d94660a33	1467
Jasper_lee	0:b16d94660a33	1468	/*
Jasper_lee	0:b16d94660a33	1469	* SCU function and mode selection definitions
Jasper_lee	0:b16d94660a33	1470	* See the User Manual for specific modes and functions supoprted by the
Jasper_lee	0:b16d94660a33	1471	* various LPC18xx/43xx devices. Functionality can vary per device.
Jasper_lee	0:b16d94660a33	1472	*/
Jasper_lee	0:b16d94660a33	1473	#define SCU_MODE_PULLUP (0x0 << 3) /* Enable pull-up resistor at pad */
Jasper_lee	0:b16d94660a33	1474	#define SCU_MODE_REPEATER (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
Jasper_lee	0:b16d94660a33	1475	#define SCU_MODE_INACT (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
Jasper_lee	0:b16d94660a33	1476	#define SCU_MODE_PULLDOWN (0x3 << 3) /* Enable pull-down resistor at pad */
Jasper_lee	0:b16d94660a33	1477	#define SCU_MODE_HIGHSPEEDSLEW_EN (0x1 << 5) /* Enable high-speed slew */
Jasper_lee	0:b16d94660a33	1478	#define SCU_MODE_INBUFF_EN (0x1 << 6) /* Enable Input buffer */
Jasper_lee	0:b16d94660a33	1479	#define SCU_MODE_ZIF_DIS (0x1 << 7) /* Disable input glitch filter */
Jasper_lee	0:b16d94660a33	1480	#define SCU_MODE_4MA_DRIVESTR (0x0 << 8) /* Normal drive: 4mA drive strength */
Jasper_lee	0:b16d94660a33	1481	#define SCU_MODE_8MA_DRIVESTR (0x1 << 8) /* Medium drive: 8mA drive strength */
Jasper_lee	0:b16d94660a33	1482	#define SCU_MODE_14MA_DRIVESTR (0x2 << 8) /* High drive: 14mA drive strength */
Jasper_lee	0:b16d94660a33	1483	#define SCU_MODE_20MA_DRIVESTR (0x3 << 8) /* Ultra high- drive: 20mA drive strength */
Jasper_lee	0:b16d94660a33	1484
Jasper_lee	0:b16d94660a33	1485	#define SCU_MODE_FUNC0 0x0 /* Selects pin function 0 */
Jasper_lee	0:b16d94660a33	1486	#define SCU_MODE_FUNC1 0x1 /* Selects pin function 1 */
Jasper_lee	0:b16d94660a33	1487	#define SCU_MODE_FUNC2 0x2 /* Selects pin function 2 */
Jasper_lee	0:b16d94660a33	1488	#define SCU_MODE_FUNC3 0x3 /* Selects pin function 3 */
Jasper_lee	0:b16d94660a33	1489	#define SCU_MODE_FUNC4 0x4 /* Selects pin function 4 */
Jasper_lee	0:b16d94660a33	1490	#define SCU_MODE_FUNC5 0x5 /* Selects pin function 5 */
Jasper_lee	0:b16d94660a33	1491	#define SCU_MODE_FUNC6 0x6 /* Selects pin function 6 */
Jasper_lee	0:b16d94660a33	1492	#define SCU_MODE_FUNC7 0x7 /* Selects pin function 7 */
Jasper_lee	0:b16d94660a33	1493
Jasper_lee	0:b16d94660a33	1494	/* Common SCU configurations */
Jasper_lee	0:b16d94660a33	1495	#define SCU_PINIO_FAST (SCU_MODE_INACT \| SCU_MODE_HIGHSPEEDSLEW_EN \| SCU_MODE_INBUFF_EN \| SCU_MODE_ZIF_DIS)
Jasper_lee	0:b16d94660a33	1496	#define SCU_PINIO_PULLUP (SCU_MODE_INBUFF_EN)
Jasper_lee	0:b16d94660a33	1497	#define SCU_PINIO_PULLDOWN (SCU_MODE_PULLDOWN \| SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
Jasper_lee	0:b16d94660a33	1498	#define SCU_PINIO_PULLNONE (SCU_MODE_INACT \| SCU_MODE_INBUFF_EN)
Jasper_lee	0:b16d94660a33	1499
Jasper_lee	0:b16d94660a33	1500	/* Calculate SCU offset and register address from group and pin number */
Jasper_lee	0:b16d94660a33	1501	#define SCU_OFF(group, num) ((group << 7) + (num << 2))
Jasper_lee	0:b16d94660a33	1502	#define SCU_REG(group, num) ((__IO uint32_t *)(LPC_SCU_BASE + SCU_OFF(group, num)))
Jasper_lee	0:b16d94660a33	1503
Jasper_lee	0:b16d94660a33	1504	/**
Jasper_lee	0:b16d94660a33	1505	* SCU function and mode selection definitions (old)
Jasper_lee	0:b16d94660a33	1506	* For backwards compatibility.
Jasper_lee	0:b16d94660a33	1507	*/
Jasper_lee	0:b16d94660a33	1508	#define MD_PUP (0x0 << 3) /* Enable pull-up resistor at pad */
Jasper_lee	0:b16d94660a33	1509	#define MD_BUK (0x1 << 3) /* Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
Jasper_lee	0:b16d94660a33	1510	#define MD_PLN (0x2 << 3) /* Disable pull-down and pull-up resistor at resistor at pad */
Jasper_lee	0:b16d94660a33	1511	#define MD_PDN (0x3 << 3) /* Enable pull-down resistor at pad */
Jasper_lee	0:b16d94660a33	1512	#define MD_EHS (0x1 << 5) /* Enable fast slew rate */
Jasper_lee	0:b16d94660a33	1513	#define MD_EZI (0x1 << 6) /* Input buffer enable */
Jasper_lee	0:b16d94660a33	1514	#define MD_ZI (0x1 << 7) /* Disable input glitch filter */
Jasper_lee	0:b16d94660a33	1515	#define MD_EHD0 (0x1 << 8) /* EHD driver strength low bit */
Jasper_lee	0:b16d94660a33	1516	#define MD_EHD1 (0x1 << 8) /* EHD driver strength high bit */
Jasper_lee	0:b16d94660a33	1517	#define MD_PLN_FAST (MD_PLN \| MD_EZI \| MD_ZI \| MD_EHS)
Jasper_lee	0:b16d94660a33	1518	#define I2C0_STANDARD_FAST_MODE (1 << 3 \| 1 << 11) /* Pin configuration for STANDARD/FAST mode I2C */
Jasper_lee	0:b16d94660a33	1519	#define I2C0_FAST_MODE_PLUS (2 << 1 \| 1 << 3 \| 1 << 7 \| 1 << 10 \| 1 << 11) /* Pin configuration for Fast-mode Plus I2C */
Jasper_lee	0:b16d94660a33	1520
Jasper_lee	0:b16d94660a33	1521	#define FUNC0 0x0 /* Pin function 0 */
Jasper_lee	0:b16d94660a33	1522	#define FUNC1 0x1 /* Pin function 1 */
Jasper_lee	0:b16d94660a33	1523	#define FUNC2 0x2 /* Pin function 2 */
Jasper_lee	0:b16d94660a33	1524	#define FUNC3 0x3 /* Pin function 3 */
Jasper_lee	0:b16d94660a33	1525	#define FUNC4 0x4 /* Pin function 4 */
Jasper_lee	0:b16d94660a33	1526	#define FUNC5 0x5 /* Pin function 5 */
Jasper_lee	0:b16d94660a33	1527	#define FUNC6 0x6 /* Pin function 6 */
Jasper_lee	0:b16d94660a33	1528	#define FUNC7 0x7 /* Pin function 7 */
Jasper_lee	0:b16d94660a33	1529
Jasper_lee	0:b16d94660a33	1530	#define PORT_OFFSET 0x80 /* Port offset definition */
Jasper_lee	0:b16d94660a33	1531	#define PIN_OFFSET 0x04 /* Pin offset definition */
Jasper_lee	0:b16d94660a33	1532
Jasper_lee	0:b16d94660a33	1533	/* Returns the SFSP register address in the SCU for a pin and port,
Jasper_lee	0:b16d94660a33	1534	recommend using ((volatile int ) &LPC_SCU->SFSP[po][pi];) */
Jasper_lee	0:b16d94660a33	1535	#define LPC_SCU_PIN(LPC_SCU_BASE, po, pi) \
Jasper_lee	0:b16d94660a33	1536	((volatile int ) ((LPC_SCU_BASE) + ((po) * 0x80) + ((pi) * 0x4))
Jasper_lee	0:b16d94660a33	1537
Jasper_lee	0:b16d94660a33	1538	/* Returns the address in the SCU for a SFSCLK clock register,
Jasper_lee	0:b16d94660a33	1539	recommend using ((volatile int ) &LPC_SCU->SFSCLK[c];) */
Jasper_lee	0:b16d94660a33	1540	#define LPC_SCU_CLK(LPC_SCU_BASE, c) \
Jasper_lee	0:b16d94660a33	1541	((volatile int ) ((LPC_SCU_BASE) +0xC00 + ((c) * 0x4)))
Jasper_lee	0:b16d94660a33	1542
Jasper_lee	0:b16d94660a33	1543	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1544	* GPIO pin interrupt register block structure
Jasper_lee	0:b16d94660a33	1545	*/
Jasper_lee	0:b16d94660a33	1546	#define LPC_GPIO_PIN_INT_BASE 0x40087000
Jasper_lee	0:b16d94660a33	1547
Jasper_lee	0:b16d94660a33	1548	typedef struct { /* GPIO_PIN_INT Structure */
Jasper_lee	0:b16d94660a33	1549	__IO uint32_t ISEL; /* Pin Interrupt Mode register */
Jasper_lee	0:b16d94660a33	1550	__IO uint32_t IENR; /* Pin Interrupt Enable (Rising) register */
Jasper_lee	0:b16d94660a33	1551	__O uint32_t SIENR; /* Set Pin Interrupt Enable (Rising) register */
Jasper_lee	0:b16d94660a33	1552	__O uint32_t CIENR; /* Clear Pin Interrupt Enable (Rising) register */
Jasper_lee	0:b16d94660a33	1553	__IO uint32_t IENF; /* Pin Interrupt Enable Falling Edge / Active Level register */
Jasper_lee	0:b16d94660a33	1554	__O uint32_t SIENF; /* Set Pin Interrupt Enable Falling Edge / Active Level register */
Jasper_lee	0:b16d94660a33	1555	__O uint32_t CIENF; /* Clear Pin Interrupt Enable Falling Edge / Active Level address */
Jasper_lee	0:b16d94660a33	1556	__IO uint32_t RISE; /* Pin Interrupt Rising Edge register */
Jasper_lee	0:b16d94660a33	1557	__IO uint32_t FALL; /* Pin Interrupt Falling Edge register */
Jasper_lee	0:b16d94660a33	1558	__IO uint32_t IST; /* Pin Interrupt Status register */
Jasper_lee	0:b16d94660a33	1559	} LPC_GPIOPININT_T;
Jasper_lee	0:b16d94660a33	1560
Jasper_lee	0:b16d94660a33	1561	typedef enum LPC_GPIOPININT_MODE {
Jasper_lee	0:b16d94660a33	1562	GPIOPININT_RISING_EDGE = 0x01,
Jasper_lee	0:b16d94660a33	1563	GPIOPININT_FALLING_EDGE = 0x02,
Jasper_lee	0:b16d94660a33	1564	GPIOPININT_ACTIVE_HIGH_LEVEL = 0x04,
Jasper_lee	0:b16d94660a33	1565	GPIOPININT_ACTIVE_LOW_LEVEL = 0x08
Jasper_lee	0:b16d94660a33	1566	} LPC_GPIOPININT_MODE_T;
Jasper_lee	0:b16d94660a33	1567
Jasper_lee	0:b16d94660a33	1568	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1569	* GPIO grouped interrupt register block structure
Jasper_lee	0:b16d94660a33	1570	*/
Jasper_lee	0:b16d94660a33	1571	#define LPC_GPIO_GROUP_INT0_BASE 0x40088000
Jasper_lee	0:b16d94660a33	1572	#define LPC_GPIO_GROUP_INT1_BASE 0x40089000
Jasper_lee	0:b16d94660a33	1573
Jasper_lee	0:b16d94660a33	1574	typedef struct { /* GPIO_GROUP_INTn Structure */
Jasper_lee	0:b16d94660a33	1575	__IO uint32_t CTRL; /* GPIO grouped interrupt control register */
Jasper_lee	0:b16d94660a33	1576	__I uint32_t RESERVED0[7];
Jasper_lee	0:b16d94660a33	1577	__IO uint32_t PORT_POL[8]; /* GPIO grouped interrupt port polarity register */
Jasper_lee	0:b16d94660a33	1578	__IO uint32_t PORT_ENA[8]; /* GPIO grouped interrupt port m enable register */
Jasper_lee	0:b16d94660a33	1579	} LPC_GPIOGROUPINT_T;
Jasper_lee	0:b16d94660a33	1580
Jasper_lee	0:b16d94660a33	1581	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1582	* Motor Control PWM register block structure
Jasper_lee	0:b16d94660a33	1583	*/
Jasper_lee	0:b16d94660a33	1584	#define LPC_MCPWM_BASE 0x400A0000
Jasper_lee	0:b16d94660a33	1585
Jasper_lee	0:b16d94660a33	1586	typedef struct { /* MCPWM Structure */
Jasper_lee	0:b16d94660a33	1587	__I uint32_t CON; /* PWM Control read address */
Jasper_lee	0:b16d94660a33	1588	__O uint32_t CON_SET; /* PWM Control set address */
Jasper_lee	0:b16d94660a33	1589	__O uint32_t CON_CLR; /* PWM Control clear address */
Jasper_lee	0:b16d94660a33	1590	__I uint32_t CAPCON; /* Capture Control read address */
Jasper_lee	0:b16d94660a33	1591	__O uint32_t CAPCON_SET; /* Capture Control set address */
Jasper_lee	0:b16d94660a33	1592	__O uint32_t CAPCON_CLR; /* Event Control clear address */
Jasper_lee	0:b16d94660a33	1593	__IO uint32_t TC[3]; /* Timer Counter register */
Jasper_lee	0:b16d94660a33	1594	__IO uint32_t LIM[3]; /* Limit register */
Jasper_lee	0:b16d94660a33	1595	__IO uint32_t MAT[3]; /* Match register */
Jasper_lee	0:b16d94660a33	1596	__IO uint32_t DT; /* Dead time register */
Jasper_lee	0:b16d94660a33	1597	__IO uint32_t CCP; /* Communication Pattern register */
Jasper_lee	0:b16d94660a33	1598	__I uint32_t CAP[3]; /* Capture register */
Jasper_lee	0:b16d94660a33	1599	__I uint32_t INTEN; /* Interrupt Enable read address */
Jasper_lee	0:b16d94660a33	1600	__O uint32_t INTEN_SET; /* Interrupt Enable set address */
Jasper_lee	0:b16d94660a33	1601	__O uint32_t INTEN_CLR; /* Interrupt Enable clear address */
Jasper_lee	0:b16d94660a33	1602	__I uint32_t CNTCON; /* Count Control read address */
Jasper_lee	0:b16d94660a33	1603	__O uint32_t CNTCON_SET; /* Count Control set address */
Jasper_lee	0:b16d94660a33	1604	__O uint32_t CNTCON_CLR; /* Count Control clear address */
Jasper_lee	0:b16d94660a33	1605	__I uint32_t INTF; /* Interrupt flags read address */
Jasper_lee	0:b16d94660a33	1606	__O uint32_t INTF_SET; /* Interrupt flags set address */
Jasper_lee	0:b16d94660a33	1607	__O uint32_t INTF_CLR; /* Interrupt flags clear address */
Jasper_lee	0:b16d94660a33	1608	__O uint32_t CAP_CLR; /* Capture clear address */
Jasper_lee	0:b16d94660a33	1609	} LPC_MCPWM_T;
Jasper_lee	0:b16d94660a33	1610
Jasper_lee	0:b16d94660a33	1611	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1612	* I2C register block structure
Jasper_lee	0:b16d94660a33	1613	*/
Jasper_lee	0:b16d94660a33	1614	#define LPC_I2C0_BASE 0x400A1000
Jasper_lee	0:b16d94660a33	1615	#define LPC_I2C1_BASE 0x400E0000
Jasper_lee	0:b16d94660a33	1616
Jasper_lee	0:b16d94660a33	1617	typedef struct { /* I2C0 Structure */
Jasper_lee	0:b16d94660a33	1618	__IO uint32_t CONSET; /* I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
Jasper_lee	0:b16d94660a33	1619	__I uint32_t STAT; /* I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
Jasper_lee	0:b16d94660a33	1620	__IO uint32_t DAT; /* I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
Jasper_lee	0:b16d94660a33	1621	__IO uint32_t ADR0; /* I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
Jasper_lee	0:b16d94660a33	1622	__IO uint32_t SCLH; /* SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
Jasper_lee	0:b16d94660a33	1623	__IO uint32_t SCLL; /* SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
Jasper_lee	0:b16d94660a33	1624	__O uint32_t CONCLR; /* I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
Jasper_lee	0:b16d94660a33	1625	__IO uint32_t MMCTRL; /* Monitor mode control register. */
Jasper_lee	0:b16d94660a33	1626	__IO uint32_t ADR1; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
Jasper_lee	0:b16d94660a33	1627	__IO uint32_t ADR2; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
Jasper_lee	0:b16d94660a33	1628	__IO uint32_t ADR3; /* I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
Jasper_lee	0:b16d94660a33	1629	__I uint32_t DATA_BUFFER; /* Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
Jasper_lee	0:b16d94660a33	1630	__IO uint32_t MASK[4]; /* I2C Slave address mask register */
Jasper_lee	0:b16d94660a33	1631	} LPC_I2C_T;
Jasper_lee	0:b16d94660a33	1632
Jasper_lee	0:b16d94660a33	1633	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1634	* I2S register block structure
Jasper_lee	0:b16d94660a33	1635	*/
Jasper_lee	0:b16d94660a33	1636	#define LPC_I2S0_BASE 0x400A2000
Jasper_lee	0:b16d94660a33	1637	#define LPC_I2S1_BASE 0x400A3000
Jasper_lee	0:b16d94660a33	1638
Jasper_lee	0:b16d94660a33	1639	typedef struct { /* I2S Structure */
Jasper_lee	0:b16d94660a33	1640	__IO uint32_t DAO; /* I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel */
Jasper_lee	0:b16d94660a33	1641	__IO uint32_t DAI; /* I2S Digital Audio Input Register. Contains control bits for the I2S receive channel */
Jasper_lee	0:b16d94660a33	1642	__O uint32_t TXFIFO; /* I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO */
Jasper_lee	0:b16d94660a33	1643	__I uint32_t RXFIFO; /* I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO */
Jasper_lee	0:b16d94660a33	1644	__I uint32_t STATE; /* I2S Status Feedback Register. Contains status information about the I2S interface */
Jasper_lee	0:b16d94660a33	1645	__IO uint32_t DMA1; /* I2S DMA Configuration Register 1. Contains control information for DMA request 1 */
Jasper_lee	0:b16d94660a33	1646	__IO uint32_t DMA2; /* I2S DMA Configuration Register 2. Contains control information for DMA request 2 */
Jasper_lee	0:b16d94660a33	1647	__IO uint32_t IRQ; /* I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated */
Jasper_lee	0:b16d94660a33	1648	__IO uint32_t TXRATE; /* I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
Jasper_lee	0:b16d94660a33	1649	__IO uint32_t RXRATE; /* I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK */
Jasper_lee	0:b16d94660a33	1650	__IO uint32_t TXBITRATE; /* I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock */
Jasper_lee	0:b16d94660a33	1651	__IO uint32_t RXBITRATE; /* I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock */
Jasper_lee	0:b16d94660a33	1652	__IO uint32_t TXMODE; /* I2S Transmit mode control */
Jasper_lee	0:b16d94660a33	1653	__IO uint32_t RXMODE; /* I2S Receive mode control */
Jasper_lee	0:b16d94660a33	1654	} LPC_I2S_T;
Jasper_lee	0:b16d94660a33	1655
Jasper_lee	0:b16d94660a33	1656	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1657	* CCAN Controller Area Network register block structure
Jasper_lee	0:b16d94660a33	1658	*/
Jasper_lee	0:b16d94660a33	1659	#define LPC_C_CAN1_BASE 0x400A4000
Jasper_lee	0:b16d94660a33	1660	#define LPC_C_CAN0_BASE 0x400E2000
Jasper_lee	0:b16d94660a33	1661
Jasper_lee	0:b16d94660a33	1662	typedef struct { /* C_CAN message interface Structure */
Jasper_lee	0:b16d94660a33	1663	__IO uint32_t IF_CMDREQ; /* Message interface command request */
Jasper_lee	0:b16d94660a33	1664	union {
Jasper_lee	0:b16d94660a33	1665	__IO uint32_t IF_CMDMSK_R; /* Message interface command mask (read direction) */
Jasper_lee	0:b16d94660a33	1666	__IO uint32_t IF_CMDMSK_W; /* Message interface command mask (write direction) */
Jasper_lee	0:b16d94660a33	1667	};
Jasper_lee	0:b16d94660a33	1668
Jasper_lee	0:b16d94660a33	1669	__IO uint32_t IF_MSK1; /* Message interface mask 1 */
Jasper_lee	0:b16d94660a33	1670	__IO uint32_t IF_MSK2; /* Message interface mask 2 */
Jasper_lee	0:b16d94660a33	1671	__IO uint32_t IF_ARB1; /* Message interface arbitration 1 */
Jasper_lee	0:b16d94660a33	1672	__IO uint32_t IF_ARB2; /* Message interface arbitration 2 */
Jasper_lee	0:b16d94660a33	1673	__IO uint32_t IF_MCTRL; /* Message interface message control */
Jasper_lee	0:b16d94660a33	1674	__IO uint32_t IF_DA1; /* Message interface data A1 */
Jasper_lee	0:b16d94660a33	1675	__IO uint32_t IF_DA2; /* Message interface data A2 */
Jasper_lee	0:b16d94660a33	1676	__IO uint32_t IF_DB1; /* Message interface data B1 */
Jasper_lee	0:b16d94660a33	1677	__IO uint32_t IF_DB2; /* Message interface data B2 */
Jasper_lee	0:b16d94660a33	1678	__I uint32_t RESERVED[13];
Jasper_lee	0:b16d94660a33	1679	} LPC_CCAN_IF_T;
Jasper_lee	0:b16d94660a33	1680
Jasper_lee	0:b16d94660a33	1681	typedef struct { /* C_CAN Structure */
Jasper_lee	0:b16d94660a33	1682	__IO uint32_t CNTL; /* CAN control */
Jasper_lee	0:b16d94660a33	1683	__IO uint32_t STAT; /* Status register */
Jasper_lee	0:b16d94660a33	1684	__I uint32_t EC; /* Error counter */
Jasper_lee	0:b16d94660a33	1685	__IO uint32_t BT; /* Bit timing register */
Jasper_lee	0:b16d94660a33	1686	__I uint32_t INT; /* Interrupt register */
Jasper_lee	0:b16d94660a33	1687	__IO uint32_t TEST; /* Test register */
Jasper_lee	0:b16d94660a33	1688	__IO uint32_t BRPE; /* Baud rate prescaler extension register */
Jasper_lee	0:b16d94660a33	1689	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1690	LPC_CCAN_IF_T IF[2];
Jasper_lee	0:b16d94660a33	1691	__I uint32_t RESERVED2[8];
Jasper_lee	0:b16d94660a33	1692	__I uint32_t TXREQ1; /* Transmission request 1 */
Jasper_lee	0:b16d94660a33	1693	__I uint32_t TXREQ2; /* Transmission request 2 */
Jasper_lee	0:b16d94660a33	1694	__I uint32_t RESERVED3[6];
Jasper_lee	0:b16d94660a33	1695	__I uint32_t ND1; /* New data 1 */
Jasper_lee	0:b16d94660a33	1696	__I uint32_t ND2; /* New data 2 */
Jasper_lee	0:b16d94660a33	1697	__I uint32_t RESERVED4[6];
Jasper_lee	0:b16d94660a33	1698	__I uint32_t IR1; /* Interrupt pending 1 */
Jasper_lee	0:b16d94660a33	1699	__I uint32_t IR2; /* Interrupt pending 2 */
Jasper_lee	0:b16d94660a33	1700	__I uint32_t RESERVED5[6];
Jasper_lee	0:b16d94660a33	1701	__I uint32_t MSGV1; /* Message valid 1 */
Jasper_lee	0:b16d94660a33	1702	__I uint32_t MSGV2; /* Message valid 2 */
Jasper_lee	0:b16d94660a33	1703	__I uint32_t RESERVED6[6];
Jasper_lee	0:b16d94660a33	1704	__IO uint32_t CLKDIV; /* CAN clock divider register */
Jasper_lee	0:b16d94660a33	1705	} LPC_CCAN_T;
Jasper_lee	0:b16d94660a33	1706
Jasper_lee	0:b16d94660a33	1707	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1708	* Repetitive Interrupt Timer register block structure
Jasper_lee	0:b16d94660a33	1709	*/
Jasper_lee	0:b16d94660a33	1710	#define LPC_RITIMER_BASE 0x400C0000
Jasper_lee	0:b16d94660a33	1711
Jasper_lee	0:b16d94660a33	1712	typedef struct { /* RITIMER Structure */
Jasper_lee	0:b16d94660a33	1713	__IO uint32_t COMPVAL; /* Compare register */
Jasper_lee	0:b16d94660a33	1714	__IO uint32_t MASK; /* Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register. */
Jasper_lee	0:b16d94660a33	1715	__IO uint32_t CTRL; /* Control register. */
Jasper_lee	0:b16d94660a33	1716	__IO uint32_t COUNTER; /* 32-bit counter */
Jasper_lee	0:b16d94660a33	1717	} LPC_RITIMER_T;
Jasper_lee	0:b16d94660a33	1718
Jasper_lee	0:b16d94660a33	1719	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1720	* Quadrature Encoder Interface register block structure
Jasper_lee	0:b16d94660a33	1721	*/
Jasper_lee	0:b16d94660a33	1722	#define LPC_QEI_BASE 0x400C6000
Jasper_lee	0:b16d94660a33	1723
Jasper_lee	0:b16d94660a33	1724	typedef struct { /* QEI Structure */
Jasper_lee	0:b16d94660a33	1725	__O uint32_t CON; /* Control register */
Jasper_lee	0:b16d94660a33	1726	__I uint32_t STAT; /* Encoder status register */
Jasper_lee	0:b16d94660a33	1727	__IO uint32_t CONF; /* Configuration register */
Jasper_lee	0:b16d94660a33	1728	__I uint32_t POS; /* Position register */
Jasper_lee	0:b16d94660a33	1729	__IO uint32_t MAXPOS; /* Maximum position register */
Jasper_lee	0:b16d94660a33	1730	__IO uint32_t CMPOS0; /* position compare register 0 */
Jasper_lee	0:b16d94660a33	1731	__IO uint32_t CMPOS1; /* position compare register 1 */
Jasper_lee	0:b16d94660a33	1732	__IO uint32_t CMPOS2; /* position compare register 2 */
Jasper_lee	0:b16d94660a33	1733	__I uint32_t INXCNT; /* Index count register */
Jasper_lee	0:b16d94660a33	1734	__IO uint32_t INXCMP0; /* Index compare register 0 */
Jasper_lee	0:b16d94660a33	1735	__IO uint32_t LOAD; /* Velocity timer reload register */
Jasper_lee	0:b16d94660a33	1736	__I uint32_t TIME; /* Velocity timer register */
Jasper_lee	0:b16d94660a33	1737	__I uint32_t VEL; /* Velocity counter register */
Jasper_lee	0:b16d94660a33	1738	__I uint32_t CAP; /* Velocity capture register */
Jasper_lee	0:b16d94660a33	1739	__IO uint32_t VELCOMP; /* Velocity compare register */
Jasper_lee	0:b16d94660a33	1740	__IO uint32_t FILTERPHA; /* Digital filter register on input phase A (QEI_A) */
Jasper_lee	0:b16d94660a33	1741	__IO uint32_t FILTERPHB; /* Digital filter register on input phase B (QEI_B) */
Jasper_lee	0:b16d94660a33	1742	__IO uint32_t FILTERINX; /* Digital filter register on input index (QEI_IDX) */
Jasper_lee	0:b16d94660a33	1743	__IO uint32_t WINDOW; /* Index acceptance window register */
Jasper_lee	0:b16d94660a33	1744	__IO uint32_t INXCMP1; /* Index compare register 1 */
Jasper_lee	0:b16d94660a33	1745	__IO uint32_t INXCMP2; /* Index compare register 2 */
Jasper_lee	0:b16d94660a33	1746	__I uint32_t RESERVED0[993];
Jasper_lee	0:b16d94660a33	1747	__O uint32_t IEC; /* Interrupt enable clear register */
Jasper_lee	0:b16d94660a33	1748	__O uint32_t IES; /* Interrupt enable set register */
Jasper_lee	0:b16d94660a33	1749	__I uint32_t INTSTAT; /* Interrupt status register */
Jasper_lee	0:b16d94660a33	1750	__I uint32_t IE; /* Interrupt enable register */
Jasper_lee	0:b16d94660a33	1751	__O uint32_t CLR; /* Interrupt status clear register */
Jasper_lee	0:b16d94660a33	1752	__O uint32_t SET; /* Interrupt status set register */
Jasper_lee	0:b16d94660a33	1753	} LPC_QEI_T;
Jasper_lee	0:b16d94660a33	1754
Jasper_lee	0:b16d94660a33	1755	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1756	* Global Input Multiplexer Array (GIMA) register block structure
Jasper_lee	0:b16d94660a33	1757	*/
Jasper_lee	0:b16d94660a33	1758	#define LPC_GIMA_BASE 0x400C7000
Jasper_lee	0:b16d94660a33	1759
Jasper_lee	0:b16d94660a33	1760	typedef struct { /* GIMA Structure */
Jasper_lee	0:b16d94660a33	1761	__IO uint32_t CAP0_IN[4][4]; /* Timer x CAP0_y capture input multiplexer (GIMA output ((x4)+y)) /
Jasper_lee	0:b16d94660a33	1762	__IO uint32_t CTIN_IN[8]; /* SCT CTIN_x capture input multiplexer (GIMA output (16+x)) */
Jasper_lee	0:b16d94660a33	1763	__IO uint32_t VADC_TRIGGER_IN; /* VADC trigger input multiplexer (GIMA output 24) */
Jasper_lee	0:b16d94660a33	1764	__IO uint32_t EVENTROUTER_13_IN; /* Event router input 13 multiplexer (GIMA output 25) */
Jasper_lee	0:b16d94660a33	1765	__IO uint32_t EVENTROUTER_14_IN; /* Event router input 14 multiplexer (GIMA output 26) */
Jasper_lee	0:b16d94660a33	1766	__IO uint32_t EVENTROUTER_16_IN; /* Event router input 16 multiplexer (GIMA output 27) */
Jasper_lee	0:b16d94660a33	1767	__IO uint32_t ADCSTART0_IN; /* ADC start0 input multiplexer (GIMA output 28) */
Jasper_lee	0:b16d94660a33	1768	__IO uint32_t ADCSTART1_IN; /* ADC start1 input multiplexer (GIMA output 29) */
Jasper_lee	0:b16d94660a33	1769	} LPC_GIMA_T;
Jasper_lee	0:b16d94660a33	1770
Jasper_lee	0:b16d94660a33	1771	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1772	* DAC register block structure
Jasper_lee	0:b16d94660a33	1773	*/
Jasper_lee	0:b16d94660a33	1774	#define LPC_DAC_BASE 0x400E1000
Jasper_lee	0:b16d94660a33	1775
Jasper_lee	0:b16d94660a33	1776	typedef struct { /* DAC Structure */
Jasper_lee	0:b16d94660a33	1777	__IO uint32_t CR; /* DAC register. Holds the conversion data. */
Jasper_lee	0:b16d94660a33	1778	__IO uint32_t CTRL; /* DAC control register. */
Jasper_lee	0:b16d94660a33	1779	__IO uint32_t CNTVAL; /* DAC counter value register. */
Jasper_lee	0:b16d94660a33	1780	} LPC_DAC_T;
Jasper_lee	0:b16d94660a33	1781
Jasper_lee	0:b16d94660a33	1782	/* After the selected settling time after this field is written with a
Jasper_lee	0:b16d94660a33	1783	* new VALUE, the voltage on the AOUT pin (with respect to VSSA)
Jasper_lee	0:b16d94660a33	1784	* is VALUE/1024 ? VREF
Jasper_lee	0:b16d94660a33	1785	*/
Jasper_lee	0:b16d94660a33	1786	#define DAC_RANGE 0x3FF
Jasper_lee	0:b16d94660a33	1787	#define DAC_SET(n) ((uint32_t) ((n & DAC_RANGE) << 6))
Jasper_lee	0:b16d94660a33	1788	#define DAC_GET(n) ((uint32_t) ((n >> 6) & DAC_RANGE))
Jasper_lee	0:b16d94660a33	1789	#define DAC_VALUE(n) DAC_SET(n)
Jasper_lee	0:b16d94660a33	1790	/* If this bit = 0: The settling time of the DAC is 1 microsecond max,
Jasper_lee	0:b16d94660a33	1791	* and the maximum current is 700 microAmpere
Jasper_lee	0:b16d94660a33	1792	* If this bit = 1: The settling time of the DAC is 2.5 microsecond
Jasper_lee	0:b16d94660a33	1793	* and the maximum current is 350 microAmpere
Jasper_lee	0:b16d94660a33	1794	*/
Jasper_lee	0:b16d94660a33	1795	#define DAC_BIAS_EN ((uint32_t) (1 << 16))
Jasper_lee	0:b16d94660a33	1796	/* Value to reload interrupt DMA counter */
Jasper_lee	0:b16d94660a33	1797	#define DAC_CCNT_VALUE(n) ((uint32_t) (n & 0xffff))
Jasper_lee	0:b16d94660a33	1798
Jasper_lee	0:b16d94660a33	1799	#define DAC_DBLBUF_ENA ((uint32_t) (1 << 1))
Jasper_lee	0:b16d94660a33	1800	#define DAC_CNT_ENA ((uint32_t) (1 << 2))
Jasper_lee	0:b16d94660a33	1801	#define DAC_DMA_ENA ((uint32_t) (1 << 3))
Jasper_lee	0:b16d94660a33	1802	#define DAC_DACCTRL_MASK ((uint32_t) (0x0F))
Jasper_lee	0:b16d94660a33	1803
Jasper_lee	0:b16d94660a33	1804	/* Current option in DAC configuration option */
Jasper_lee	0:b16d94660a33	1805	typedef enum DAC_CURRENT_OPT {
Jasper_lee	0:b16d94660a33	1806	DAC_MAX_UPDATE_RATE_1MHz = 0, /* Shorter settling times and higher power consumption;
Jasper_lee	0:b16d94660a33	1807	allows for a maximum update rate of 1 MHz */
Jasper_lee	0:b16d94660a33	1808	DAC_MAX_UPDATE_RATE_400kHz /* Longer settling times and lower power consumption;
Jasper_lee	0:b16d94660a33	1809	allows for a maximum update rate of 400 kHz */
Jasper_lee	0:b16d94660a33	1810	} DAC_CURRENT_OPT_T;
Jasper_lee	0:b16d94660a33	1811
Jasper_lee	0:b16d94660a33	1812	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1813	* ADC register block structure
Jasper_lee	0:b16d94660a33	1814	*/
Jasper_lee	0:b16d94660a33	1815	#define LPC_ADC0_BASE 0x400E3000
Jasper_lee	0:b16d94660a33	1816	#define LPC_ADC1_BASE 0x400E4000
Jasper_lee	0:b16d94660a33	1817	#define ADC_ACC_10BITS
Jasper_lee	0:b16d94660a33	1818
Jasper_lee	0:b16d94660a33	1819	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1820	* 10 or 12-bit ADC register block structure
Jasper_lee	0:b16d94660a33	1821	*/
Jasper_lee	0:b16d94660a33	1822	typedef struct { /* ADCn Structure */
Jasper_lee	0:b16d94660a33	1823	__IO uint32_t CR; /* A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
Jasper_lee	0:b16d94660a33	1824	__I uint32_t GDR; /* A/D Global Data Register. Contains the result of the most recent A/D conversion. */
Jasper_lee	0:b16d94660a33	1825	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1826	__IO uint32_t INTEN; /* A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
Jasper_lee	0:b16d94660a33	1827	__I uint32_t DR[8]; /* A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
Jasper_lee	0:b16d94660a33	1828	__I uint32_t STAT; /* A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
Jasper_lee	0:b16d94660a33	1829	} LPC_ADC_T;
Jasper_lee	0:b16d94660a33	1830
Jasper_lee	0:b16d94660a33	1831	/* ADC register support bitfields and mask */
Jasper_lee	0:b16d94660a33	1832	#define ADC_RANGE 0x3FF
Jasper_lee	0:b16d94660a33	1833	#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /* Mask for getting the 10 bits ADC data read value */
Jasper_lee	0:b16d94660a33	1834	#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /* Number of ADC accuracy bits */
Jasper_lee	0:b16d94660a33	1835	#define ADC_DR_DONE(n) (((n) >> 31)) /* Mask for reading the ADC done status */
Jasper_lee	0:b16d94660a33	1836	#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /* Mask for reading the ADC overrun status */
Jasper_lee	0:b16d94660a33	1837	#define ADC_CR_CH_SEL(n) ((1UL << (n))) /* Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
Jasper_lee	0:b16d94660a33	1838	#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /* The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
Jasper_lee	0:b16d94660a33	1839	#define ADC_CR_BURST ((1UL << 16)) /* Repeated conversions A/D enable bit */
Jasper_lee	0:b16d94660a33	1840	#define ADC_CR_PDN ((1UL << 21)) /* ADC convert is operational */
Jasper_lee	0:b16d94660a33	1841	#define ADC_CR_START_MASK ((7UL << 24)) /* ADC start mask bits */
Jasper_lee	0:b16d94660a33	1842	#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /* Select Start Mode */
Jasper_lee	0:b16d94660a33	1843	#define ADC_CR_START_NOW ((1UL << 24)) /* Start conversion now */
Jasper_lee	0:b16d94660a33	1844	#define ADC_CR_START_CTOUT15 ((2UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
Jasper_lee	0:b16d94660a33	1845	#define ADC_CR_START_CTOUT8 ((3UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
Jasper_lee	0:b16d94660a33	1846	#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
Jasper_lee	0:b16d94660a33	1847	#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
Jasper_lee	0:b16d94660a33	1848	#define ADC_CR_START_MCOA2 ((6UL << 24)) /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
Jasper_lee	0:b16d94660a33	1849	#define ADC_CR_EDGE ((1UL << 27)) /* Start conversion on a falling edge on the selected CAP/MAT signal */
Jasper_lee	0:b16d94660a33	1850	#define ADC_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) \| ADC_CR_BITACC(0x07) \| ADC_CR_PDN)
Jasper_lee	0:b16d94660a33	1851
Jasper_lee	0:b16d94660a33	1852	/* ADC status register used for IP drivers */
Jasper_lee	0:b16d94660a33	1853	typedef enum ADC_STATUS {
Jasper_lee	0:b16d94660a33	1854	ADC_DR_DONE_STAT, /* ADC data register staus */
Jasper_lee	0:b16d94660a33	1855	ADC_DR_OVERRUN_STAT,/* ADC data overrun staus */
Jasper_lee	0:b16d94660a33	1856	ADC_DR_ADINT_STAT /* ADC interrupt status */
Jasper_lee	0:b16d94660a33	1857	} ADC_STATUS_T;
Jasper_lee	0:b16d94660a33	1858
Jasper_lee	0:b16d94660a33	1859	/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
Jasper_lee	0:b16d94660a33	1860	typedef enum ADC_START_MODE {
Jasper_lee	0:b16d94660a33	1861	ADC_NO_START = 0,
Jasper_lee	0:b16d94660a33	1862	ADC_START_NOW, /* Start conversion now */
Jasper_lee	0:b16d94660a33	1863	ADC_START_ON_CTOUT15, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
Jasper_lee	0:b16d94660a33	1864	ADC_START_ON_CTOUT8, /* Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
Jasper_lee	0:b16d94660a33	1865	ADC_START_ON_ADCTRIG0, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
Jasper_lee	0:b16d94660a33	1866	ADC_START_ON_ADCTRIG1, /* Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
Jasper_lee	0:b16d94660a33	1867	ADC_START_ON_MCOA2 /* Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
Jasper_lee	0:b16d94660a33	1868	} ADC_START_MODE_T;
Jasper_lee	0:b16d94660a33	1869
Jasper_lee	0:b16d94660a33	1870	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1871	* GPIO port register block structure
Jasper_lee	0:b16d94660a33	1872	*/
Jasper_lee	0:b16d94660a33	1873	#define LPC_GPIO_PORT_BASE 0x400F4000
Jasper_lee	0:b16d94660a33	1874	#define LPC_GPIO0_BASE (LPC_GPIO_PORT_BASE)
Jasper_lee	0:b16d94660a33	1875	#define LPC_GPIO1_BASE (LPC_GPIO_PORT_BASE + 0x04)
Jasper_lee	0:b16d94660a33	1876	#define LPC_GPIO2_BASE (LPC_GPIO_PORT_BASE + 0x08)
Jasper_lee	0:b16d94660a33	1877	#define LPC_GPIO3_BASE (LPC_GPIO_PORT_BASE + 0x0C)
Jasper_lee	0:b16d94660a33	1878	#define LPC_GPIO4_BASE (LPC_GPIO_PORT_BASE + 0x10)
Jasper_lee	0:b16d94660a33	1879	#define LPC_GPIO5_BASE (LPC_GPIO_PORT_BASE + 0x14)
Jasper_lee	0:b16d94660a33	1880	#define LPC_GPIO6_BASE (LPC_GPIO_PORT_BASE + 0x18)
Jasper_lee	0:b16d94660a33	1881	#define LPC_GPIO7_BASE (LPC_GPIO_PORT_BASE + 0x1C)
Jasper_lee	0:b16d94660a33	1882
Jasper_lee	0:b16d94660a33	1883	typedef struct { /* GPIO_PORT Structure */
Jasper_lee	0:b16d94660a33	1884	__IO uint8_t B[128][32]; /* Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
Jasper_lee	0:b16d94660a33	1885	__IO uint32_t W[32][32]; /* Offset 0x1000: Word pin registers port 0 to n */
Jasper_lee	0:b16d94660a33	1886	__IO uint32_t DIR[32]; /* Offset 0x2000: Direction registers port n */
Jasper_lee	0:b16d94660a33	1887	__IO uint32_t MASK[32]; /* Offset 0x2080: Mask register port n */
Jasper_lee	0:b16d94660a33	1888	__IO uint32_t PIN[32]; /* Offset 0x2100: Portpin register port n */
Jasper_lee	0:b16d94660a33	1889	__IO uint32_t MPIN[32]; /* Offset 0x2180: Masked port register port n */
Jasper_lee	0:b16d94660a33	1890	__IO uint32_t SET[32]; /* Offset 0x2200: Write: Set register for port n Read: output bits for port n */
Jasper_lee	0:b16d94660a33	1891	__O uint32_t CLR[32]; /* Offset 0x2280: Clear port n */
Jasper_lee	0:b16d94660a33	1892	__O uint32_t NOT[32]; /* Offset 0x2300: Toggle port n */
Jasper_lee	0:b16d94660a33	1893	} LPC_GPIO_T;
Jasper_lee	0:b16d94660a33	1894
Jasper_lee	0:b16d94660a33	1895	/* Calculate GPIO offset and port register address from group and pin number */
Jasper_lee	0:b16d94660a33	1896	#define GPIO_OFF(port, pin) ((port << 5) + pin)
Jasper_lee	0:b16d94660a33	1897	#define GPIO_REG(port, pin) ((__IO uint32_t *)(LPC_GPIO_PORT_BASE + 0x2000 + GPIO_OFF(port, pin)))
Jasper_lee	0:b16d94660a33	1898
Jasper_lee	0:b16d94660a33	1899	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1900	* SPI register block structure
Jasper_lee	0:b16d94660a33	1901	*/
Jasper_lee	0:b16d94660a33	1902	#define LPC_SPI_BASE 0x40100000
Jasper_lee	0:b16d94660a33	1903
Jasper_lee	0:b16d94660a33	1904	typedef struct { /* SPI Structure */
Jasper_lee	0:b16d94660a33	1905	__IO uint32_t CR; /* SPI Control Register. This register controls the operation of the SPI. */
Jasper_lee	0:b16d94660a33	1906	__I uint32_t SR; /* SPI Status Register. This register shows the status of the SPI. */
Jasper_lee	0:b16d94660a33	1907	__IO uint32_t DR; /* SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. */
Jasper_lee	0:b16d94660a33	1908	__IO uint32_t CCR; /* SPI Clock Counter Register. This register controls the frequency of a master's SCK0. */
Jasper_lee	0:b16d94660a33	1909	__I uint32_t RESERVED0[3];
Jasper_lee	0:b16d94660a33	1910	__IO uint32_t INT; /* SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface. */
Jasper_lee	0:b16d94660a33	1911	} LPC_SPI_T;
Jasper_lee	0:b16d94660a33	1912
Jasper_lee	0:b16d94660a33	1913	/* SPI CFG Register BitMask */
Jasper_lee	0:b16d94660a33	1914	#define SPI_CR_BITMASK ((uint32_t) 0xFFC)
Jasper_lee	0:b16d94660a33	1915	/* Enable of controlling the number of bits per transfer */
Jasper_lee	0:b16d94660a33	1916	#define SPI_CR_BIT_EN ((uint32_t) (1 << 2))
Jasper_lee	0:b16d94660a33	1917	/* Mask of field of bit controlling */
Jasper_lee	0:b16d94660a33	1918	#define SPI_CR_BITS_MASK ((uint32_t) 0xF00)
Jasper_lee	0:b16d94660a33	1919	/* Set the number of bits per a transfer */
Jasper_lee	0:b16d94660a33	1920	#define SPI_CR_BITS(n) ((uint32_t) ((n << 8) & 0xF00)) /* n is in range 8-16 */
Jasper_lee	0:b16d94660a33	1921	/* SPI Clock Phase Select*/
Jasper_lee	0:b16d94660a33	1922	#define SPI_CR_CPHA_FIRST ((uint32_t) (0)) /Capture data on the first edge, Change data on the following edge/
Jasper_lee	0:b16d94660a33	1923	#define SPI_CR_CPHA_SECOND ((uint32_t) (1 << 3)) /* Change data on the first edge, Capture data on the following edge*/
Jasper_lee	0:b16d94660a33	1924	/* SPI Clock Polarity Select*/
Jasper_lee	0:b16d94660a33	1925	#define SPI_CR_CPOL_LO ((uint32_t) (0)) /* The rest state of the clock (between frames) is low.*/
Jasper_lee	0:b16d94660a33	1926	#define SPI_CR_CPOL_HI ((uint32_t) (1 << 4)) /* The rest state of the clock (between frames) is high.*/
Jasper_lee	0:b16d94660a33	1927	/* SPI Slave Mode Select */
Jasper_lee	0:b16d94660a33	1928	#define SPI_CR_SLAVE_EN ((uint32_t) 0)
Jasper_lee	0:b16d94660a33	1929	/* SPI Master Mode Select */
Jasper_lee	0:b16d94660a33	1930	#define SPI_CR_MASTER_EN ((uint32_t) (1 << 5))
Jasper_lee	0:b16d94660a33	1931	/* SPI MSB First mode enable */
Jasper_lee	0:b16d94660a33	1932	#define SPI_CR_MSB_FIRST_EN ((uint32_t) 0) /* Data will be transmitted and received in standard order (MSB first).*/
Jasper_lee	0:b16d94660a33	1933	/* SPI LSB First mode enable */
Jasper_lee	0:b16d94660a33	1934	#define SPI_CR_LSB_FIRST_EN ((uint32_t) (1 << 6)) /* Data will be transmitted and received in reverse order (LSB first).*/
Jasper_lee	0:b16d94660a33	1935	/* SPI interrupt enable */
Jasper_lee	0:b16d94660a33	1936	#define SPI_CR_INT_EN ((uint32_t) (1 << 7))
Jasper_lee	0:b16d94660a33	1937	/* SPI STAT Register BitMask */
Jasper_lee	0:b16d94660a33	1938	#define SPI_SR_BITMASK ((uint32_t) 0xF8)
Jasper_lee	0:b16d94660a33	1939	/* Slave abort Flag */
Jasper_lee	0:b16d94660a33	1940	#define SPI_SR_ABRT ((uint32_t) (1 << 3)) /* When 1, this bit indicates that a slave abort has occurred. */
Jasper_lee	0:b16d94660a33	1941	/* Mode fault Flag */
Jasper_lee	0:b16d94660a33	1942	#define SPI_SR_MODF ((uint32_t) (1 << 4)) /* when 1, this bit indicates that a Mode fault error has occurred. */
Jasper_lee	0:b16d94660a33	1943	/* Read overrun flag*/
Jasper_lee	0:b16d94660a33	1944	#define SPI_SR_ROVR ((uint32_t) (1 << 5)) /* When 1, this bit indicates that a read overrun has occurred. */
Jasper_lee	0:b16d94660a33	1945	/* Write collision flag. */
Jasper_lee	0:b16d94660a33	1946	#define SPI_SR_WCOL ((uint32_t) (1 << 6)) /* When 1, this bit indicates that a write collision has occurred.. */
Jasper_lee	0:b16d94660a33	1947	/* SPI transfer complete flag. */
Jasper_lee	0:b16d94660a33	1948	#define SPI_SR_SPIF ((uint32_t) (1 << 7)) /* When 1, this bit indicates when a SPI data transfer is complete.. */
Jasper_lee	0:b16d94660a33	1949	/* SPI error flag */
Jasper_lee	0:b16d94660a33	1950	#define SPI_SR_ERROR (SPI_SR_ABRT \| SPI_SR_MODF \| SPI_SR_ROVR \| SPI_SR_WCOL)
Jasper_lee	0:b16d94660a33	1951	/* Enable SPI Test Mode */
Jasper_lee	0:b16d94660a33	1952	#define SPI_TCR_TEST(n) ((uint32_t) ((n & 0x3F) << 1))
Jasper_lee	0:b16d94660a33	1953	/* SPI interrupt flag */
Jasper_lee	0:b16d94660a33	1954	#define SPI_INT_SPIF ((uint32_t) (1 << 0))
Jasper_lee	0:b16d94660a33	1955	/* Receiver Data */
Jasper_lee	0:b16d94660a33	1956	#define SPI_DR_DATA(n) ((uint32_t) ((n) & 0xFFFF))
Jasper_lee	0:b16d94660a33	1957
Jasper_lee	0:b16d94660a33	1958	/* SPI Mode*/
Jasper_lee	0:b16d94660a33	1959	typedef enum LPC_SPI_MODE {
Jasper_lee	0:b16d94660a33	1960	SPI_MODE_MASTER = SPI_CR_MASTER_EN, /* Master Mode */
Jasper_lee	0:b16d94660a33	1961	SPI_MODE_SLAVE = SPI_CR_SLAVE_EN, /* Slave Mode */
Jasper_lee	0:b16d94660a33	1962	} LPC_SPI_MODE_T;
Jasper_lee	0:b16d94660a33	1963
Jasper_lee	0:b16d94660a33	1964	/* SPI Clock Mode*/
Jasper_lee	0:b16d94660a33	1965	typedef enum LPC_SPI_CLOCK_MODE {
Jasper_lee	0:b16d94660a33	1966	SPI_CLOCK_CPHA0_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 0 */
Jasper_lee	0:b16d94660a33	1967	SPI_CLOCK_CPHA0_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_FIRST, /* CPHA = 0, CPOL = 1 */
Jasper_lee	0:b16d94660a33	1968	SPI_CLOCK_CPHA1_CPOL0 = SPI_CR_CPOL_LO \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 0 */
Jasper_lee	0:b16d94660a33	1969	SPI_CLOCK_CPHA1_CPOL1 = SPI_CR_CPOL_HI \| SPI_CR_CPHA_SECOND, /* CPHA = 1, CPOL = 1 */
Jasper_lee	0:b16d94660a33	1970	SPI_CLOCK_MODE0 = SPI_CLOCK_CPHA0_CPOL0, /* alias */
Jasper_lee	0:b16d94660a33	1971	SPI_CLOCK_MODE1 = SPI_CLOCK_CPHA1_CPOL0, /* alias */
Jasper_lee	0:b16d94660a33	1972	SPI_CLOCK_MODE2 = SPI_CLOCK_CPHA0_CPOL1, /* alias */
Jasper_lee	0:b16d94660a33	1973	SPI_CLOCK_MODE3 = SPI_CLOCK_CPHA1_CPOL1, /* alias */
Jasper_lee	0:b16d94660a33	1974	} LPC_SPI_CLOCK_MODE_T;
Jasper_lee	0:b16d94660a33	1975
Jasper_lee	0:b16d94660a33	1976	/* SPI Data Order Mode*/
Jasper_lee	0:b16d94660a33	1977	typedef enum LPC_SPI_DATA_ORDER {
Jasper_lee	0:b16d94660a33	1978	SPI_DATA_MSB_FIRST = SPI_CR_MSB_FIRST_EN, /* Standard Order */
Jasper_lee	0:b16d94660a33	1979	SPI_DATA_LSB_FIRST = SPI_CR_LSB_FIRST_EN, /* Reverse Order */
Jasper_lee	0:b16d94660a33	1980	} LPC_SPI_DATA_ORDER_T;
Jasper_lee	0:b16d94660a33	1981
Jasper_lee	0:b16d94660a33	1982	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	1983	* Serial GPIO register block structure
Jasper_lee	0:b16d94660a33	1984	*/
Jasper_lee	0:b16d94660a33	1985	#define LPC_SGPIO_BASE 0x40101000
Jasper_lee	0:b16d94660a33	1986
Jasper_lee	0:b16d94660a33	1987	typedef struct { /* SGPIO Structure */
Jasper_lee	0:b16d94660a33	1988	__IO uint32_t OUT_MUX_CFG[16]; /* Pin multiplexer configurationregisters. */
Jasper_lee	0:b16d94660a33	1989	__IO uint32_t SGPIO_MUX_CFG[16]; /* SGPIO multiplexer configuration registers. */
Jasper_lee	0:b16d94660a33	1990	__IO uint32_t SLICE_MUX_CFG[16]; /* Slice multiplexer configuration registers. */
Jasper_lee	0:b16d94660a33	1991	__IO uint32_t REG[16]; /* Slice data registers. Eachtime COUNT0 reaches 0x0 the register shifts loading bit 31 withdata captured from DIN(n). DOUT(n) is set to REG(0) */
Jasper_lee	0:b16d94660a33	1992	__IO uint32_t REG_SS[16]; /* Slice data shadow registers. Each time POSreaches 0x0 the contents of REG_SS is exchanged with the contentof REG */
Jasper_lee	0:b16d94660a33	1993	__IO uint32_t PRESET[16]; /* Reload valueof COUNT0, loaded when COUNT0 reaches 0x0 */
Jasper_lee	0:b16d94660a33	1994	__IO uint32_t COUNT[16]; /* Down counter, counts down each clock cycle. */
Jasper_lee	0:b16d94660a33	1995	__IO uint32_t POS[16]; /* Each time COUNT0 reaches 0x0 */
Jasper_lee	0:b16d94660a33	1996	__IO uint32_t MASK_A; /* Mask for pattern match function of slice A */
Jasper_lee	0:b16d94660a33	1997	__IO uint32_t MASK_H; /* Mask for pattern match function of slice H */
Jasper_lee	0:b16d94660a33	1998	__IO uint32_t MASK_I; /* Mask for pattern match function of slice I */
Jasper_lee	0:b16d94660a33	1999	__IO uint32_t MASK_P; /* Mask for pattern match function of slice P */
Jasper_lee	0:b16d94660a33	2000	__I uint32_t GPIO_INREG; /* GPIO input status register */
Jasper_lee	0:b16d94660a33	2001	__IO uint32_t GPIO_OUTREG; /* GPIO output control register */
Jasper_lee	0:b16d94660a33	2002	__IO uint32_t GPIO_OENREG; /* GPIO OE control register */
Jasper_lee	0:b16d94660a33	2003	__IO uint32_t CTRL_ENABLED; /* Enables the slice COUNT counter */
Jasper_lee	0:b16d94660a33	2004	__IO uint32_t CTRL_DISABLED; /* Disables the slice COUNT counter */
Jasper_lee	0:b16d94660a33	2005	__I uint32_t RESERVED0[823];
Jasper_lee	0:b16d94660a33	2006	__O uint32_t CLR_EN_0; /* Shift clock interrupt clear mask */
Jasper_lee	0:b16d94660a33	2007	__O uint32_t SET_EN_0; /* Shift clock interrupt set mask */
Jasper_lee	0:b16d94660a33	2008	__I uint32_t ENABLE_0; /* Shift clock interrupt enable */
Jasper_lee	0:b16d94660a33	2009	__I uint32_t STATUS_0; /* Shift clock interrupt status */
Jasper_lee	0:b16d94660a33	2010	__O uint32_t CTR_STATUS_0; /* Shift clock interrupt clear status */
Jasper_lee	0:b16d94660a33	2011	__O uint32_t SET_STATUS_0; /* Shift clock interrupt set status */
Jasper_lee	0:b16d94660a33	2012	__I uint32_t RESERVED1[2];
Jasper_lee	0:b16d94660a33	2013	__O uint32_t CLR_EN_1; /* Capture clock interrupt clear mask */
Jasper_lee	0:b16d94660a33	2014	__O uint32_t SET_EN_1; /* Capture clock interrupt set mask */
Jasper_lee	0:b16d94660a33	2015	__I uint32_t ENABLE_1; /* Capture clock interrupt enable */
Jasper_lee	0:b16d94660a33	2016	__I uint32_t STATUS_1; /* Capture clock interrupt status */
Jasper_lee	0:b16d94660a33	2017	__O uint32_t CTR_STATUS_1; /* Capture clock interrupt clear status */
Jasper_lee	0:b16d94660a33	2018	__O uint32_t SET_STATUS_1; /* Capture clock interrupt set status */
Jasper_lee	0:b16d94660a33	2019	__I uint32_t RESERVED2[2];
Jasper_lee	0:b16d94660a33	2020	__O uint32_t CLR_EN_2; /* Pattern match interrupt clear mask */
Jasper_lee	0:b16d94660a33	2021	__O uint32_t SET_EN_2; /* Pattern match interrupt set mask */
Jasper_lee	0:b16d94660a33	2022	__I uint32_t ENABLE_2; /* Pattern match interrupt enable */
Jasper_lee	0:b16d94660a33	2023	__I uint32_t STATUS_2; /* Pattern match interrupt status */
Jasper_lee	0:b16d94660a33	2024	__O uint32_t CTR_STATUS_2; /* Pattern match interrupt clear status */
Jasper_lee	0:b16d94660a33	2025	__O uint32_t SET_STATUS_2; /* Pattern match interrupt set status */
Jasper_lee	0:b16d94660a33	2026	__I uint32_t RESERVED3[2];
Jasper_lee	0:b16d94660a33	2027	__O uint32_t CLR_EN_3; /* Input interrupt clear mask */
Jasper_lee	0:b16d94660a33	2028	__O uint32_t SET_EN_3; /* Input bit match interrupt set mask */
Jasper_lee	0:b16d94660a33	2029	__I uint32_t ENABLE_3; /* Input bit match interrupt enable */
Jasper_lee	0:b16d94660a33	2030	__I uint32_t STATUS_3; /* Input bit match interrupt status */
Jasper_lee	0:b16d94660a33	2031	__O uint32_t CTR_STATUS_3; /* Input bit match interrupt clear status */
Jasper_lee	0:b16d94660a33	2032	__O uint32_t SET_STATUS_3; /* Shift clock interrupt set status */
Jasper_lee	0:b16d94660a33	2033	} LPC_SGPIO_T;
Jasper_lee	0:b16d94660a33	2034
Jasper_lee	0:b16d94660a33	2035	/* End of section using anonymous unions */
Jasper_lee	0:b16d94660a33	2036	#if defined(__ARMCC_VERSION)
Jasper_lee	0:b16d94660a33	2037	#pragma pop
Jasper_lee	0:b16d94660a33	2038	#elif defined(__CWCC__)
Jasper_lee	0:b16d94660a33	2039	#pragma pop
Jasper_lee	0:b16d94660a33	2040	#elif defined(__IAR_SYSTEMS_ICC__)
Jasper_lee	0:b16d94660a33	2041	//#pragma pop // FIXME not usable for IAR
Jasper_lee	0:b16d94660a33	2042	#else /* defined(__GNUC__) and others */
Jasper_lee	0:b16d94660a33	2043	/* Leave anonymous unions enabled */
Jasper_lee	0:b16d94660a33	2044	#endif
Jasper_lee	0:b16d94660a33	2045
Jasper_lee	0:b16d94660a33	2046	/* ---------------------------------------------------------------------------
Jasper_lee	0:b16d94660a33	2047	* LPC43xx Peripheral register set declarations
Jasper_lee	0:b16d94660a33	2048	*/
Jasper_lee	0:b16d94660a33	2049	#define LPC_SCT ((LPC_SCT_T *) LPC_SCT_BASE)
Jasper_lee	0:b16d94660a33	2050	#define LPC_GPDMA ((LPC_GPDMA_T *) LPC_GPDMA_BASE)
Jasper_lee	0:b16d94660a33	2051	#define LPC_SPIFI ((LPC_SPIFI_T *) LPC_SPIFI_BASE)
Jasper_lee	0:b16d94660a33	2052	#define LPC_SDMMC ((LPC_SDMMC_T *) LPC_SDMMC_BASE)
Jasper_lee	0:b16d94660a33	2053	#define LPC_EMC ((LPC_EMC_T *) LPC_EMC_BASE)
Jasper_lee	0:b16d94660a33	2054	#define LPC_USB0 ((LPC_USBHS_T *) LPC_USB0_BASE)
Jasper_lee	0:b16d94660a33	2055	#define LPC_USB1 ((LPC_USBHS_T *) LPC_USB1_BASE)
Jasper_lee	0:b16d94660a33	2056	#define LPC_LCD ((LPC_LCD_T *) LPC_LCD_BASE)
Jasper_lee	0:b16d94660a33	2057	#define LPC_EEPROM ((LPC_EEPROM_T *) LPC_EEPROM_BASE)
Jasper_lee	0:b16d94660a33	2058	#define LPC_ETHERNET ((LPC_ENET_T *) LPC_ETHERNET_BASE)
Jasper_lee	0:b16d94660a33	2059	#define LPC_ATIMER ((LPC_ATIMER_T *) LPC_ATIMER_BASE)
Jasper_lee	0:b16d94660a33	2060	#define LPC_REGFILE ((LPC_REGFILE_T *) LPC_REGFILE_BASE)
Jasper_lee	0:b16d94660a33	2061	#define LPC_PMC ((LPC_PMC_T *) LPC_PMC_BASE)
Jasper_lee	0:b16d94660a33	2062	#define LPC_CREG ((LPC_CREG_T *) LPC_CREG_BASE)
Jasper_lee	0:b16d94660a33	2063	#define LPC_EVRT ((LPC_EVRT_T *) LPC_EVRT_BASE)
Jasper_lee	0:b16d94660a33	2064	#define LPC_RTC ((LPC_RTC_T *) LPC_RTC_BASE)
Jasper_lee	0:b16d94660a33	2065	#define LPC_CGU ((LPC_CGU_T *) LPC_CGU_BASE)
Jasper_lee	0:b16d94660a33	2066	#define LPC_CCU1 ((LPC_CCU1_T *) LPC_CCU1_BASE)
Jasper_lee	0:b16d94660a33	2067	#define LPC_CCU2 ((LPC_CCU2_T *) LPC_CCU2_BASE)
Jasper_lee	0:b16d94660a33	2068	#define LPC_RGU ((LPC_RGU_T *) LPC_RGU_BASE)
Jasper_lee	0:b16d94660a33	2069	#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
Jasper_lee	0:b16d94660a33	2070	#define LPC_USART0 ((LPC_USART_T *) LPC_USART0_BASE)
Jasper_lee	0:b16d94660a33	2071	#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
Jasper_lee	0:b16d94660a33	2072	#define LPC_USART3 ((LPC_USART_T *) LPC_USART3_BASE)
Jasper_lee	0:b16d94660a33	2073	#define LPC_UART1 ((LPC_USART_T *) LPC_UART1_BASE)
Jasper_lee	0:b16d94660a33	2074	#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
Jasper_lee	0:b16d94660a33	2075	#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
Jasper_lee	0:b16d94660a33	2076	#define LPC_TIMER0 ((LPC_TIMER_T *) LPC_TIMER0_BASE)
Jasper_lee	0:b16d94660a33	2077	#define LPC_TIMER1 ((LPC_TIMER_T *) LPC_TIMER1_BASE)
Jasper_lee	0:b16d94660a33	2078	#define LPC_TIMER2 ((LPC_TIMER_T *) LPC_TIMER2_BASE)
Jasper_lee	0:b16d94660a33	2079	#define LPC_TIMER3 ((LPC_TIMER_T *) LPC_TIMER3_BASE)
Jasper_lee	0:b16d94660a33	2080	#define LPC_SCU ((LPC_SCU_T *) LPC_SCU_BASE)
Jasper_lee	0:b16d94660a33	2081	#define LPC_GPIO_PIN_INT ((LPC_GPIOPININT_T *) LPC_GPIO_PIN_INT_BASE)
Jasper_lee	0:b16d94660a33	2082	#define LPC_GPIO_GROUP_INT0 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
Jasper_lee	0:b16d94660a33	2083	#define LPC_GPIO_GROUP_INT1 ((IP_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT1_BASE)
Jasper_lee	0:b16d94660a33	2084	#define LPC_MCPWM ((LPC_MCPWM_T *) LPC_MCPWM_BASE)
Jasper_lee	0:b16d94660a33	2085	#define LPC_I2C0 ((LPC_I2C_T *) LPC_I2C0_BASE)
Jasper_lee	0:b16d94660a33	2086	#define LPC_I2C1 ((LPC_I2C_T *) LPC_I2C1_BASE)
Jasper_lee	0:b16d94660a33	2087	#define LPC_I2S0 ((LPC_I2S_T *) LPC_I2S0_BASE)
Jasper_lee	0:b16d94660a33	2088	#define LPC_I2S1 ((LPC_I2S_T *) LPC_I2S1_BASE)
Jasper_lee	0:b16d94660a33	2089	#define LPC_C_CAN1 ((LPC_CCAN_T *) LPC_C_CAN1_BASE)
Jasper_lee	0:b16d94660a33	2090	#define LPC_RITIMER ((LPC_RITIMER_T *) LPC_RITIMER_BASE)
Jasper_lee	0:b16d94660a33	2091	#define LPC_QEI ((LPC_QEI_T *) LPC_QEI_BASE)
Jasper_lee	0:b16d94660a33	2092	#define LPC_GIMA ((LPC_GIMA_T *) LPC_GIMA_BASE)
Jasper_lee	0:b16d94660a33	2093	#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
Jasper_lee	0:b16d94660a33	2094	#define LPC_C_CAN0 ((LPC_CCAN_T *) LPC_C_CAN0_BASE)
Jasper_lee	0:b16d94660a33	2095	#define LPC_ADC0 ((LPC_ADC_T *) LPC_ADC0_BASE)
Jasper_lee	0:b16d94660a33	2096	#define LPC_ADC1 ((LPC_ADC_T *) LPC_ADC1_BASE)
Jasper_lee	0:b16d94660a33	2097	#define LPC_GPIO_PORT ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
Jasper_lee	0:b16d94660a33	2098	#define LPC_GPIO0 ((LPC_GPIO_T *) LPC_GPIO0_BASE)
Jasper_lee	0:b16d94660a33	2099	#define LPC_GPIO1 ((LPC_GPIO_T *) LPC_GPIO1_BASE)
Jasper_lee	0:b16d94660a33	2100	#define LPC_GPIO2 ((LPC_GPIO_T *) LPC_GPIO2_BASE)
Jasper_lee	0:b16d94660a33	2101	#define LPC_GPIO3 ((LPC_GPIO_T *) LPC_GPIO3_BASE)
Jasper_lee	0:b16d94660a33	2102	#define LPC_GPIO4 ((LPC_GPIO_T *) LPC_GPIO4_BASE)
Jasper_lee	0:b16d94660a33	2103	#define LPC_GPIO5 ((LPC_GPIO_T *) LPC_GPIO5_BASE)
Jasper_lee	0:b16d94660a33	2104	#define LPC_GPIO6 ((LPC_GPIO_T *) LPC_GPIO6_BASE)
Jasper_lee	0:b16d94660a33	2105	#define LPC_GPIO7 ((LPC_GPIO_T *) LPC_GPIO7_BASE)
Jasper_lee	0:b16d94660a33	2106	#define LPC_SPI ((LPC_SPI_T *) LPC_SPI_BASE)
Jasper_lee	0:b16d94660a33	2107	#define LPC_SGPIO ((LPC_SGPIO_T *) LPC_SGPIO_BASE)
Jasper_lee	0:b16d94660a33	2108
Jasper_lee	0:b16d94660a33	2109	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	2110	}
Jasper_lee	0:b16d94660a33	2111	#endif
Jasper_lee	0:b16d94660a33	2112
Jasper_lee	0:b16d94660a33	2113	#endif /* __LPC43XX_H */

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Type:	Library
Created:	23 Dec 2014
Imports:	459
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	12

The code in this repository is Apache licensed.

TARGET_LPC4337/LPC43xx.h@0:b16d94660a33, 2014-12-23 (annotated)

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