Jasper Lee / mbed_helloworld

change some io settings for TWR-K22F-120M

Dependents:   twr_helloworld

TARGET_LPC1768/LPC17xx.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:
Jasper_lee
Date:
Tue Dec 23 03:35:08 2014 +0000
Revision:
0:b16d94660a33
change some io setting used in TWR-K22F120M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jasper_lee 0:b16d94660a33 1 /**************************************************************************//**
Jasper_lee 0:b16d94660a33 2 * @file LPC17xx.h
Jasper_lee 0:b16d94660a33 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
Jasper_lee 0:b16d94660a33 4 * NXP LPC17xx Device Series
Jasper_lee 0:b16d94660a33 5 * @version: V1.09
Jasper_lee 0:b16d94660a33 6 * @date: 17. March 2010
Jasper_lee 0:b16d94660a33 7
Jasper_lee 0:b16d94660a33 8 *
Jasper_lee 0:b16d94660a33 9 * @note
Jasper_lee 0:b16d94660a33 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
Jasper_lee 0:b16d94660a33 11 *
Jasper_lee 0:b16d94660a33 12 * @par
Jasper_lee 0:b16d94660a33 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Jasper_lee 0:b16d94660a33 14 * processor based microcontrollers. This file can be freely distributed
Jasper_lee 0:b16d94660a33 15 * within development tools that are supporting such ARM based processors.
Jasper_lee 0:b16d94660a33 16 *
Jasper_lee 0:b16d94660a33 17 * @par
Jasper_lee 0:b16d94660a33 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Jasper_lee 0:b16d94660a33 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Jasper_lee 0:b16d94660a33 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Jasper_lee 0:b16d94660a33 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Jasper_lee 0:b16d94660a33 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Jasper_lee 0:b16d94660a33 23 *
Jasper_lee 0:b16d94660a33 24 ******************************************************************************/
Jasper_lee 0:b16d94660a33 25
Jasper_lee 0:b16d94660a33 26
Jasper_lee 0:b16d94660a33 27 #ifndef __LPC17xx_H__
Jasper_lee 0:b16d94660a33 28 #define __LPC17xx_H__
Jasper_lee 0:b16d94660a33 29
Jasper_lee 0:b16d94660a33 30 /*
Jasper_lee 0:b16d94660a33 31 * ==========================================================================
Jasper_lee 0:b16d94660a33 32 * ---------- Interrupt Number Definition -----------------------------------
Jasper_lee 0:b16d94660a33 33 * ==========================================================================
Jasper_lee 0:b16d94660a33 34 */
Jasper_lee 0:b16d94660a33 35
Jasper_lee 0:b16d94660a33 36 typedef enum IRQn
Jasper_lee 0:b16d94660a33 37 {
Jasper_lee 0:b16d94660a33 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
Jasper_lee 0:b16d94660a33 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Jasper_lee 0:b16d94660a33 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
Jasper_lee 0:b16d94660a33 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
Jasper_lee 0:b16d94660a33 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
Jasper_lee 0:b16d94660a33 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
Jasper_lee 0:b16d94660a33 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
Jasper_lee 0:b16d94660a33 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
Jasper_lee 0:b16d94660a33 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
Jasper_lee 0:b16d94660a33 47
Jasper_lee 0:b16d94660a33 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
Jasper_lee 0:b16d94660a33 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
Jasper_lee 0:b16d94660a33 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
Jasper_lee 0:b16d94660a33 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
Jasper_lee 0:b16d94660a33 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
Jasper_lee 0:b16d94660a33 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
Jasper_lee 0:b16d94660a33 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
Jasper_lee 0:b16d94660a33 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
Jasper_lee 0:b16d94660a33 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
Jasper_lee 0:b16d94660a33 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
Jasper_lee 0:b16d94660a33 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
Jasper_lee 0:b16d94660a33 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
Jasper_lee 0:b16d94660a33 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
Jasper_lee 0:b16d94660a33 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
Jasper_lee 0:b16d94660a33 62 SPI_IRQn = 13, /*!< SPI Interrupt */
Jasper_lee 0:b16d94660a33 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
Jasper_lee 0:b16d94660a33 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
Jasper_lee 0:b16d94660a33 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
Jasper_lee 0:b16d94660a33 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
Jasper_lee 0:b16d94660a33 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
Jasper_lee 0:b16d94660a33 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
Jasper_lee 0:b16d94660a33 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
Jasper_lee 0:b16d94660a33 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
Jasper_lee 0:b16d94660a33 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
Jasper_lee 0:b16d94660a33 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
Jasper_lee 0:b16d94660a33 73 USB_IRQn = 24, /*!< USB Interrupt */
Jasper_lee 0:b16d94660a33 74 CAN_IRQn = 25, /*!< CAN Interrupt */
Jasper_lee 0:b16d94660a33 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
Jasper_lee 0:b16d94660a33 76 I2S_IRQn = 27, /*!< I2S Interrupt */
Jasper_lee 0:b16d94660a33 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
Jasper_lee 0:b16d94660a33 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
Jasper_lee 0:b16d94660a33 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
Jasper_lee 0:b16d94660a33 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
Jasper_lee 0:b16d94660a33 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
Jasper_lee 0:b16d94660a33 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
Jasper_lee 0:b16d94660a33 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
Jasper_lee 0:b16d94660a33 84 } IRQn_Type;
Jasper_lee 0:b16d94660a33 85
Jasper_lee 0:b16d94660a33 86
Jasper_lee 0:b16d94660a33 87 /*
Jasper_lee 0:b16d94660a33 88 * ==========================================================================
Jasper_lee 0:b16d94660a33 89 * ----------- Processor and Core Peripheral Section ------------------------
Jasper_lee 0:b16d94660a33 90 * ==========================================================================
Jasper_lee 0:b16d94660a33 91 */
Jasper_lee 0:b16d94660a33 92
Jasper_lee 0:b16d94660a33 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
Jasper_lee 0:b16d94660a33 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
Jasper_lee 0:b16d94660a33 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
Jasper_lee 0:b16d94660a33 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Jasper_lee 0:b16d94660a33 97
Jasper_lee 0:b16d94660a33 98
Jasper_lee 0:b16d94660a33 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
Jasper_lee 0:b16d94660a33 100 #include "system_LPC17xx.h" /* System Header */
Jasper_lee 0:b16d94660a33 101
Jasper_lee 0:b16d94660a33 102
Jasper_lee 0:b16d94660a33 103 /******************************************************************************/
Jasper_lee 0:b16d94660a33 104 /* Device Specific Peripheral registers structures */
Jasper_lee 0:b16d94660a33 105 /******************************************************************************/
Jasper_lee 0:b16d94660a33 106
Jasper_lee 0:b16d94660a33 107 #if defined ( __CC_ARM )
Jasper_lee 0:b16d94660a33 108 #pragma anon_unions
Jasper_lee 0:b16d94660a33 109 #endif
Jasper_lee 0:b16d94660a33 110
Jasper_lee 0:b16d94660a33 111 /*------------- System Control (SC) ------------------------------------------*/
Jasper_lee 0:b16d94660a33 112 typedef struct
Jasper_lee 0:b16d94660a33 113 {
Jasper_lee 0:b16d94660a33 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
Jasper_lee 0:b16d94660a33 115 uint32_t RESERVED0[31];
Jasper_lee 0:b16d94660a33 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
Jasper_lee 0:b16d94660a33 117 __IO uint32_t PLL0CFG;
Jasper_lee 0:b16d94660a33 118 __I uint32_t PLL0STAT;
Jasper_lee 0:b16d94660a33 119 __O uint32_t PLL0FEED;
Jasper_lee 0:b16d94660a33 120 uint32_t RESERVED1[4];
Jasper_lee 0:b16d94660a33 121 __IO uint32_t PLL1CON;
Jasper_lee 0:b16d94660a33 122 __IO uint32_t PLL1CFG;
Jasper_lee 0:b16d94660a33 123 __I uint32_t PLL1STAT;
Jasper_lee 0:b16d94660a33 124 __O uint32_t PLL1FEED;
Jasper_lee 0:b16d94660a33 125 uint32_t RESERVED2[4];
Jasper_lee 0:b16d94660a33 126 __IO uint32_t PCON;
Jasper_lee 0:b16d94660a33 127 __IO uint32_t PCONP;
Jasper_lee 0:b16d94660a33 128 uint32_t RESERVED3[15];
Jasper_lee 0:b16d94660a33 129 __IO uint32_t CCLKCFG;
Jasper_lee 0:b16d94660a33 130 __IO uint32_t USBCLKCFG;
Jasper_lee 0:b16d94660a33 131 __IO uint32_t CLKSRCSEL;
Jasper_lee 0:b16d94660a33 132 __IO uint32_t CANSLEEPCLR;
Jasper_lee 0:b16d94660a33 133 __IO uint32_t CANWAKEFLAGS;
Jasper_lee 0:b16d94660a33 134 uint32_t RESERVED4[10];
Jasper_lee 0:b16d94660a33 135 __IO uint32_t EXTINT; /* External Interrupts */
Jasper_lee 0:b16d94660a33 136 uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 137 __IO uint32_t EXTMODE;
Jasper_lee 0:b16d94660a33 138 __IO uint32_t EXTPOLAR;
Jasper_lee 0:b16d94660a33 139 uint32_t RESERVED6[12];
Jasper_lee 0:b16d94660a33 140 __IO uint32_t RSID; /* Reset */
Jasper_lee 0:b16d94660a33 141 uint32_t RESERVED7[7];
Jasper_lee 0:b16d94660a33 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
Jasper_lee 0:b16d94660a33 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
Jasper_lee 0:b16d94660a33 144 __IO uint32_t PCLKSEL0;
Jasper_lee 0:b16d94660a33 145 __IO uint32_t PCLKSEL1;
Jasper_lee 0:b16d94660a33 146 uint32_t RESERVED8[4];
Jasper_lee 0:b16d94660a33 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
Jasper_lee 0:b16d94660a33 148 __IO uint32_t DMAREQSEL;
Jasper_lee 0:b16d94660a33 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
Jasper_lee 0:b16d94660a33 150 } LPC_SC_TypeDef;
Jasper_lee 0:b16d94660a33 151
Jasper_lee 0:b16d94660a33 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
Jasper_lee 0:b16d94660a33 153 typedef struct
Jasper_lee 0:b16d94660a33 154 {
Jasper_lee 0:b16d94660a33 155 __IO uint32_t PINSEL0;
Jasper_lee 0:b16d94660a33 156 __IO uint32_t PINSEL1;
Jasper_lee 0:b16d94660a33 157 __IO uint32_t PINSEL2;
Jasper_lee 0:b16d94660a33 158 __IO uint32_t PINSEL3;
Jasper_lee 0:b16d94660a33 159 __IO uint32_t PINSEL4;
Jasper_lee 0:b16d94660a33 160 __IO uint32_t PINSEL5;
Jasper_lee 0:b16d94660a33 161 __IO uint32_t PINSEL6;
Jasper_lee 0:b16d94660a33 162 __IO uint32_t PINSEL7;
Jasper_lee 0:b16d94660a33 163 __IO uint32_t PINSEL8;
Jasper_lee 0:b16d94660a33 164 __IO uint32_t PINSEL9;
Jasper_lee 0:b16d94660a33 165 __IO uint32_t PINSEL10;
Jasper_lee 0:b16d94660a33 166 uint32_t RESERVED0[5];
Jasper_lee 0:b16d94660a33 167 __IO uint32_t PINMODE0;
Jasper_lee 0:b16d94660a33 168 __IO uint32_t PINMODE1;
Jasper_lee 0:b16d94660a33 169 __IO uint32_t PINMODE2;
Jasper_lee 0:b16d94660a33 170 __IO uint32_t PINMODE3;
Jasper_lee 0:b16d94660a33 171 __IO uint32_t PINMODE4;
Jasper_lee 0:b16d94660a33 172 __IO uint32_t PINMODE5;
Jasper_lee 0:b16d94660a33 173 __IO uint32_t PINMODE6;
Jasper_lee 0:b16d94660a33 174 __IO uint32_t PINMODE7;
Jasper_lee 0:b16d94660a33 175 __IO uint32_t PINMODE8;
Jasper_lee 0:b16d94660a33 176 __IO uint32_t PINMODE9;
Jasper_lee 0:b16d94660a33 177 __IO uint32_t PINMODE_OD0;
Jasper_lee 0:b16d94660a33 178 __IO uint32_t PINMODE_OD1;
Jasper_lee 0:b16d94660a33 179 __IO uint32_t PINMODE_OD2;
Jasper_lee 0:b16d94660a33 180 __IO uint32_t PINMODE_OD3;
Jasper_lee 0:b16d94660a33 181 __IO uint32_t PINMODE_OD4;
Jasper_lee 0:b16d94660a33 182 __IO uint32_t I2CPADCFG;
Jasper_lee 0:b16d94660a33 183 } LPC_PINCON_TypeDef;
Jasper_lee 0:b16d94660a33 184
Jasper_lee 0:b16d94660a33 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
Jasper_lee 0:b16d94660a33 186 typedef struct
Jasper_lee 0:b16d94660a33 187 {
Jasper_lee 0:b16d94660a33 188 union {
Jasper_lee 0:b16d94660a33 189 __IO uint32_t FIODIR;
Jasper_lee 0:b16d94660a33 190 struct {
Jasper_lee 0:b16d94660a33 191 __IO uint16_t FIODIRL;
Jasper_lee 0:b16d94660a33 192 __IO uint16_t FIODIRH;
Jasper_lee 0:b16d94660a33 193 };
Jasper_lee 0:b16d94660a33 194 struct {
Jasper_lee 0:b16d94660a33 195 __IO uint8_t FIODIR0;
Jasper_lee 0:b16d94660a33 196 __IO uint8_t FIODIR1;
Jasper_lee 0:b16d94660a33 197 __IO uint8_t FIODIR2;
Jasper_lee 0:b16d94660a33 198 __IO uint8_t FIODIR3;
Jasper_lee 0:b16d94660a33 199 };
Jasper_lee 0:b16d94660a33 200 };
Jasper_lee 0:b16d94660a33 201 uint32_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 202 union {
Jasper_lee 0:b16d94660a33 203 __IO uint32_t FIOMASK;
Jasper_lee 0:b16d94660a33 204 struct {
Jasper_lee 0:b16d94660a33 205 __IO uint16_t FIOMASKL;
Jasper_lee 0:b16d94660a33 206 __IO uint16_t FIOMASKH;
Jasper_lee 0:b16d94660a33 207 };
Jasper_lee 0:b16d94660a33 208 struct {
Jasper_lee 0:b16d94660a33 209 __IO uint8_t FIOMASK0;
Jasper_lee 0:b16d94660a33 210 __IO uint8_t FIOMASK1;
Jasper_lee 0:b16d94660a33 211 __IO uint8_t FIOMASK2;
Jasper_lee 0:b16d94660a33 212 __IO uint8_t FIOMASK3;
Jasper_lee 0:b16d94660a33 213 };
Jasper_lee 0:b16d94660a33 214 };
Jasper_lee 0:b16d94660a33 215 union {
Jasper_lee 0:b16d94660a33 216 __IO uint32_t FIOPIN;
Jasper_lee 0:b16d94660a33 217 struct {
Jasper_lee 0:b16d94660a33 218 __IO uint16_t FIOPINL;
Jasper_lee 0:b16d94660a33 219 __IO uint16_t FIOPINH;
Jasper_lee 0:b16d94660a33 220 };
Jasper_lee 0:b16d94660a33 221 struct {
Jasper_lee 0:b16d94660a33 222 __IO uint8_t FIOPIN0;
Jasper_lee 0:b16d94660a33 223 __IO uint8_t FIOPIN1;
Jasper_lee 0:b16d94660a33 224 __IO uint8_t FIOPIN2;
Jasper_lee 0:b16d94660a33 225 __IO uint8_t FIOPIN3;
Jasper_lee 0:b16d94660a33 226 };
Jasper_lee 0:b16d94660a33 227 };
Jasper_lee 0:b16d94660a33 228 union {
Jasper_lee 0:b16d94660a33 229 __IO uint32_t FIOSET;
Jasper_lee 0:b16d94660a33 230 struct {
Jasper_lee 0:b16d94660a33 231 __IO uint16_t FIOSETL;
Jasper_lee 0:b16d94660a33 232 __IO uint16_t FIOSETH;
Jasper_lee 0:b16d94660a33 233 };
Jasper_lee 0:b16d94660a33 234 struct {
Jasper_lee 0:b16d94660a33 235 __IO uint8_t FIOSET0;
Jasper_lee 0:b16d94660a33 236 __IO uint8_t FIOSET1;
Jasper_lee 0:b16d94660a33 237 __IO uint8_t FIOSET2;
Jasper_lee 0:b16d94660a33 238 __IO uint8_t FIOSET3;
Jasper_lee 0:b16d94660a33 239 };
Jasper_lee 0:b16d94660a33 240 };
Jasper_lee 0:b16d94660a33 241 union {
Jasper_lee 0:b16d94660a33 242 __O uint32_t FIOCLR;
Jasper_lee 0:b16d94660a33 243 struct {
Jasper_lee 0:b16d94660a33 244 __O uint16_t FIOCLRL;
Jasper_lee 0:b16d94660a33 245 __O uint16_t FIOCLRH;
Jasper_lee 0:b16d94660a33 246 };
Jasper_lee 0:b16d94660a33 247 struct {
Jasper_lee 0:b16d94660a33 248 __O uint8_t FIOCLR0;
Jasper_lee 0:b16d94660a33 249 __O uint8_t FIOCLR1;
Jasper_lee 0:b16d94660a33 250 __O uint8_t FIOCLR2;
Jasper_lee 0:b16d94660a33 251 __O uint8_t FIOCLR3;
Jasper_lee 0:b16d94660a33 252 };
Jasper_lee 0:b16d94660a33 253 };
Jasper_lee 0:b16d94660a33 254 } LPC_GPIO_TypeDef;
Jasper_lee 0:b16d94660a33 255
Jasper_lee 0:b16d94660a33 256 typedef struct
Jasper_lee 0:b16d94660a33 257 {
Jasper_lee 0:b16d94660a33 258 __I uint32_t IntStatus;
Jasper_lee 0:b16d94660a33 259 __I uint32_t IO0IntStatR;
Jasper_lee 0:b16d94660a33 260 __I uint32_t IO0IntStatF;
Jasper_lee 0:b16d94660a33 261 __O uint32_t IO0IntClr;
Jasper_lee 0:b16d94660a33 262 __IO uint32_t IO0IntEnR;
Jasper_lee 0:b16d94660a33 263 __IO uint32_t IO0IntEnF;
Jasper_lee 0:b16d94660a33 264 uint32_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 265 __I uint32_t IO2IntStatR;
Jasper_lee 0:b16d94660a33 266 __I uint32_t IO2IntStatF;
Jasper_lee 0:b16d94660a33 267 __O uint32_t IO2IntClr;
Jasper_lee 0:b16d94660a33 268 __IO uint32_t IO2IntEnR;
Jasper_lee 0:b16d94660a33 269 __IO uint32_t IO2IntEnF;
Jasper_lee 0:b16d94660a33 270 } LPC_GPIOINT_TypeDef;
Jasper_lee 0:b16d94660a33 271
Jasper_lee 0:b16d94660a33 272 /*------------- Timer (TIM) --------------------------------------------------*/
Jasper_lee 0:b16d94660a33 273 typedef struct
Jasper_lee 0:b16d94660a33 274 {
Jasper_lee 0:b16d94660a33 275 __IO uint32_t IR;
Jasper_lee 0:b16d94660a33 276 __IO uint32_t TCR;
Jasper_lee 0:b16d94660a33 277 __IO uint32_t TC;
Jasper_lee 0:b16d94660a33 278 __IO uint32_t PR;
Jasper_lee 0:b16d94660a33 279 __IO uint32_t PC;
Jasper_lee 0:b16d94660a33 280 __IO uint32_t MCR;
Jasper_lee 0:b16d94660a33 281 __IO uint32_t MR0;
Jasper_lee 0:b16d94660a33 282 __IO uint32_t MR1;
Jasper_lee 0:b16d94660a33 283 __IO uint32_t MR2;
Jasper_lee 0:b16d94660a33 284 __IO uint32_t MR3;
Jasper_lee 0:b16d94660a33 285 __IO uint32_t CCR;
Jasper_lee 0:b16d94660a33 286 __I uint32_t CR0;
Jasper_lee 0:b16d94660a33 287 __I uint32_t CR1;
Jasper_lee 0:b16d94660a33 288 uint32_t RESERVED0[2];
Jasper_lee 0:b16d94660a33 289 __IO uint32_t EMR;
Jasper_lee 0:b16d94660a33 290 uint32_t RESERVED1[12];
Jasper_lee 0:b16d94660a33 291 __IO uint32_t CTCR;
Jasper_lee 0:b16d94660a33 292 } LPC_TIM_TypeDef;
Jasper_lee 0:b16d94660a33 293
Jasper_lee 0:b16d94660a33 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
Jasper_lee 0:b16d94660a33 295 typedef struct
Jasper_lee 0:b16d94660a33 296 {
Jasper_lee 0:b16d94660a33 297 __IO uint32_t IR;
Jasper_lee 0:b16d94660a33 298 __IO uint32_t TCR;
Jasper_lee 0:b16d94660a33 299 __IO uint32_t TC;
Jasper_lee 0:b16d94660a33 300 __IO uint32_t PR;
Jasper_lee 0:b16d94660a33 301 __IO uint32_t PC;
Jasper_lee 0:b16d94660a33 302 __IO uint32_t MCR;
Jasper_lee 0:b16d94660a33 303 __IO uint32_t MR0;
Jasper_lee 0:b16d94660a33 304 __IO uint32_t MR1;
Jasper_lee 0:b16d94660a33 305 __IO uint32_t MR2;
Jasper_lee 0:b16d94660a33 306 __IO uint32_t MR3;
Jasper_lee 0:b16d94660a33 307 __IO uint32_t CCR;
Jasper_lee 0:b16d94660a33 308 __I uint32_t CR0;
Jasper_lee 0:b16d94660a33 309 __I uint32_t CR1;
Jasper_lee 0:b16d94660a33 310 __I uint32_t CR2;
Jasper_lee 0:b16d94660a33 311 __I uint32_t CR3;
Jasper_lee 0:b16d94660a33 312 uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 313 __IO uint32_t MR4;
Jasper_lee 0:b16d94660a33 314 __IO uint32_t MR5;
Jasper_lee 0:b16d94660a33 315 __IO uint32_t MR6;
Jasper_lee 0:b16d94660a33 316 __IO uint32_t PCR;
Jasper_lee 0:b16d94660a33 317 __IO uint32_t LER;
Jasper_lee 0:b16d94660a33 318 uint32_t RESERVED1[7];
Jasper_lee 0:b16d94660a33 319 __IO uint32_t CTCR;
Jasper_lee 0:b16d94660a33 320 } LPC_PWM_TypeDef;
Jasper_lee 0:b16d94660a33 321
Jasper_lee 0:b16d94660a33 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
Jasper_lee 0:b16d94660a33 323 typedef struct
Jasper_lee 0:b16d94660a33 324 {
Jasper_lee 0:b16d94660a33 325 union {
Jasper_lee 0:b16d94660a33 326 __I uint8_t RBR;
Jasper_lee 0:b16d94660a33 327 __O uint8_t THR;
Jasper_lee 0:b16d94660a33 328 __IO uint8_t DLL;
Jasper_lee 0:b16d94660a33 329 uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 330 };
Jasper_lee 0:b16d94660a33 331 union {
Jasper_lee 0:b16d94660a33 332 __IO uint8_t DLM;
Jasper_lee 0:b16d94660a33 333 __IO uint32_t IER;
Jasper_lee 0:b16d94660a33 334 };
Jasper_lee 0:b16d94660a33 335 union {
Jasper_lee 0:b16d94660a33 336 __I uint32_t IIR;
Jasper_lee 0:b16d94660a33 337 __O uint8_t FCR;
Jasper_lee 0:b16d94660a33 338 };
Jasper_lee 0:b16d94660a33 339 __IO uint8_t LCR;
Jasper_lee 0:b16d94660a33 340 uint8_t RESERVED1[7];
Jasper_lee 0:b16d94660a33 341 __I uint8_t LSR;
Jasper_lee 0:b16d94660a33 342 uint8_t RESERVED2[7];
Jasper_lee 0:b16d94660a33 343 __IO uint8_t SCR;
Jasper_lee 0:b16d94660a33 344 uint8_t RESERVED3[3];
Jasper_lee 0:b16d94660a33 345 __IO uint32_t ACR;
Jasper_lee 0:b16d94660a33 346 __IO uint8_t ICR;
Jasper_lee 0:b16d94660a33 347 uint8_t RESERVED4[3];
Jasper_lee 0:b16d94660a33 348 __IO uint8_t FDR;
Jasper_lee 0:b16d94660a33 349 uint8_t RESERVED5[7];
Jasper_lee 0:b16d94660a33 350 __IO uint8_t TER;
Jasper_lee 0:b16d94660a33 351 uint8_t RESERVED6[39];
Jasper_lee 0:b16d94660a33 352 __IO uint32_t FIFOLVL;
Jasper_lee 0:b16d94660a33 353 } LPC_UART_TypeDef;
Jasper_lee 0:b16d94660a33 354
Jasper_lee 0:b16d94660a33 355 typedef struct
Jasper_lee 0:b16d94660a33 356 {
Jasper_lee 0:b16d94660a33 357 union {
Jasper_lee 0:b16d94660a33 358 __I uint8_t RBR;
Jasper_lee 0:b16d94660a33 359 __O uint8_t THR;
Jasper_lee 0:b16d94660a33 360 __IO uint8_t DLL;
Jasper_lee 0:b16d94660a33 361 uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 362 };
Jasper_lee 0:b16d94660a33 363 union {
Jasper_lee 0:b16d94660a33 364 __IO uint8_t DLM;
Jasper_lee 0:b16d94660a33 365 __IO uint32_t IER;
Jasper_lee 0:b16d94660a33 366 };
Jasper_lee 0:b16d94660a33 367 union {
Jasper_lee 0:b16d94660a33 368 __I uint32_t IIR;
Jasper_lee 0:b16d94660a33 369 __O uint8_t FCR;
Jasper_lee 0:b16d94660a33 370 };
Jasper_lee 0:b16d94660a33 371 __IO uint8_t LCR;
Jasper_lee 0:b16d94660a33 372 uint8_t RESERVED1[7];
Jasper_lee 0:b16d94660a33 373 __I uint8_t LSR;
Jasper_lee 0:b16d94660a33 374 uint8_t RESERVED2[7];
Jasper_lee 0:b16d94660a33 375 __IO uint8_t SCR;
Jasper_lee 0:b16d94660a33 376 uint8_t RESERVED3[3];
Jasper_lee 0:b16d94660a33 377 __IO uint32_t ACR;
Jasper_lee 0:b16d94660a33 378 __IO uint8_t ICR;
Jasper_lee 0:b16d94660a33 379 uint8_t RESERVED4[3];
Jasper_lee 0:b16d94660a33 380 __IO uint8_t FDR;
Jasper_lee 0:b16d94660a33 381 uint8_t RESERVED5[7];
Jasper_lee 0:b16d94660a33 382 __IO uint8_t TER;
Jasper_lee 0:b16d94660a33 383 uint8_t RESERVED6[39];
Jasper_lee 0:b16d94660a33 384 __IO uint32_t FIFOLVL;
Jasper_lee 0:b16d94660a33 385 } LPC_UART0_TypeDef;
Jasper_lee 0:b16d94660a33 386
Jasper_lee 0:b16d94660a33 387 typedef struct
Jasper_lee 0:b16d94660a33 388 {
Jasper_lee 0:b16d94660a33 389 union {
Jasper_lee 0:b16d94660a33 390 __I uint8_t RBR;
Jasper_lee 0:b16d94660a33 391 __O uint8_t THR;
Jasper_lee 0:b16d94660a33 392 __IO uint8_t DLL;
Jasper_lee 0:b16d94660a33 393 uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 394 };
Jasper_lee 0:b16d94660a33 395 union {
Jasper_lee 0:b16d94660a33 396 __IO uint8_t DLM;
Jasper_lee 0:b16d94660a33 397 __IO uint32_t IER;
Jasper_lee 0:b16d94660a33 398 };
Jasper_lee 0:b16d94660a33 399 union {
Jasper_lee 0:b16d94660a33 400 __I uint32_t IIR;
Jasper_lee 0:b16d94660a33 401 __O uint8_t FCR;
Jasper_lee 0:b16d94660a33 402 };
Jasper_lee 0:b16d94660a33 403 __IO uint8_t LCR;
Jasper_lee 0:b16d94660a33 404 uint8_t RESERVED1[3];
Jasper_lee 0:b16d94660a33 405 __IO uint8_t MCR;
Jasper_lee 0:b16d94660a33 406 uint8_t RESERVED2[3];
Jasper_lee 0:b16d94660a33 407 __I uint8_t LSR;
Jasper_lee 0:b16d94660a33 408 uint8_t RESERVED3[3];
Jasper_lee 0:b16d94660a33 409 __I uint8_t MSR;
Jasper_lee 0:b16d94660a33 410 uint8_t RESERVED4[3];
Jasper_lee 0:b16d94660a33 411 __IO uint8_t SCR;
Jasper_lee 0:b16d94660a33 412 uint8_t RESERVED5[3];
Jasper_lee 0:b16d94660a33 413 __IO uint32_t ACR;
Jasper_lee 0:b16d94660a33 414 uint32_t RESERVED6;
Jasper_lee 0:b16d94660a33 415 __IO uint32_t FDR;
Jasper_lee 0:b16d94660a33 416 uint32_t RESERVED7;
Jasper_lee 0:b16d94660a33 417 __IO uint8_t TER;
Jasper_lee 0:b16d94660a33 418 uint8_t RESERVED8[27];
Jasper_lee 0:b16d94660a33 419 __IO uint8_t RS485CTRL;
Jasper_lee 0:b16d94660a33 420 uint8_t RESERVED9[3];
Jasper_lee 0:b16d94660a33 421 __IO uint8_t ADRMATCH;
Jasper_lee 0:b16d94660a33 422 uint8_t RESERVED10[3];
Jasper_lee 0:b16d94660a33 423 __IO uint8_t RS485DLY;
Jasper_lee 0:b16d94660a33 424 uint8_t RESERVED11[3];
Jasper_lee 0:b16d94660a33 425 __IO uint32_t FIFOLVL;
Jasper_lee 0:b16d94660a33 426 } LPC_UART1_TypeDef;
Jasper_lee 0:b16d94660a33 427
Jasper_lee 0:b16d94660a33 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
Jasper_lee 0:b16d94660a33 429 typedef struct
Jasper_lee 0:b16d94660a33 430 {
Jasper_lee 0:b16d94660a33 431 __IO uint32_t SPCR;
Jasper_lee 0:b16d94660a33 432 __I uint32_t SPSR;
Jasper_lee 0:b16d94660a33 433 __IO uint32_t SPDR;
Jasper_lee 0:b16d94660a33 434 __IO uint32_t SPCCR;
Jasper_lee 0:b16d94660a33 435 uint32_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 436 __IO uint32_t SPINT;
Jasper_lee 0:b16d94660a33 437 } LPC_SPI_TypeDef;
Jasper_lee 0:b16d94660a33 438
Jasper_lee 0:b16d94660a33 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
Jasper_lee 0:b16d94660a33 440 typedef struct
Jasper_lee 0:b16d94660a33 441 {
Jasper_lee 0:b16d94660a33 442 __IO uint32_t CR0;
Jasper_lee 0:b16d94660a33 443 __IO uint32_t CR1;
Jasper_lee 0:b16d94660a33 444 __IO uint32_t DR;
Jasper_lee 0:b16d94660a33 445 __I uint32_t SR;
Jasper_lee 0:b16d94660a33 446 __IO uint32_t CPSR;
Jasper_lee 0:b16d94660a33 447 __IO uint32_t IMSC;
Jasper_lee 0:b16d94660a33 448 __IO uint32_t RIS;
Jasper_lee 0:b16d94660a33 449 __IO uint32_t MIS;
Jasper_lee 0:b16d94660a33 450 __IO uint32_t ICR;
Jasper_lee 0:b16d94660a33 451 __IO uint32_t DMACR;
Jasper_lee 0:b16d94660a33 452 } LPC_SSP_TypeDef;
Jasper_lee 0:b16d94660a33 453
Jasper_lee 0:b16d94660a33 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
Jasper_lee 0:b16d94660a33 455 typedef struct
Jasper_lee 0:b16d94660a33 456 {
Jasper_lee 0:b16d94660a33 457 __IO uint32_t I2CONSET;
Jasper_lee 0:b16d94660a33 458 __I uint32_t I2STAT;
Jasper_lee 0:b16d94660a33 459 __IO uint32_t I2DAT;
Jasper_lee 0:b16d94660a33 460 __IO uint32_t I2ADR0;
Jasper_lee 0:b16d94660a33 461 __IO uint32_t I2SCLH;
Jasper_lee 0:b16d94660a33 462 __IO uint32_t I2SCLL;
Jasper_lee 0:b16d94660a33 463 __O uint32_t I2CONCLR;
Jasper_lee 0:b16d94660a33 464 __IO uint32_t MMCTRL;
Jasper_lee 0:b16d94660a33 465 __IO uint32_t I2ADR1;
Jasper_lee 0:b16d94660a33 466 __IO uint32_t I2ADR2;
Jasper_lee 0:b16d94660a33 467 __IO uint32_t I2ADR3;
Jasper_lee 0:b16d94660a33 468 __I uint32_t I2DATA_BUFFER;
Jasper_lee 0:b16d94660a33 469 __IO uint32_t I2MASK0;
Jasper_lee 0:b16d94660a33 470 __IO uint32_t I2MASK1;
Jasper_lee 0:b16d94660a33 471 __IO uint32_t I2MASK2;
Jasper_lee 0:b16d94660a33 472 __IO uint32_t I2MASK3;
Jasper_lee 0:b16d94660a33 473 } LPC_I2C_TypeDef;
Jasper_lee 0:b16d94660a33 474
Jasper_lee 0:b16d94660a33 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
Jasper_lee 0:b16d94660a33 476 typedef struct
Jasper_lee 0:b16d94660a33 477 {
Jasper_lee 0:b16d94660a33 478 __IO uint32_t I2SDAO;
Jasper_lee 0:b16d94660a33 479 __IO uint32_t I2SDAI;
Jasper_lee 0:b16d94660a33 480 __O uint32_t I2STXFIFO;
Jasper_lee 0:b16d94660a33 481 __I uint32_t I2SRXFIFO;
Jasper_lee 0:b16d94660a33 482 __I uint32_t I2SSTATE;
Jasper_lee 0:b16d94660a33 483 __IO uint32_t I2SDMA1;
Jasper_lee 0:b16d94660a33 484 __IO uint32_t I2SDMA2;
Jasper_lee 0:b16d94660a33 485 __IO uint32_t I2SIRQ;
Jasper_lee 0:b16d94660a33 486 __IO uint32_t I2STXRATE;
Jasper_lee 0:b16d94660a33 487 __IO uint32_t I2SRXRATE;
Jasper_lee 0:b16d94660a33 488 __IO uint32_t I2STXBITRATE;
Jasper_lee 0:b16d94660a33 489 __IO uint32_t I2SRXBITRATE;
Jasper_lee 0:b16d94660a33 490 __IO uint32_t I2STXMODE;
Jasper_lee 0:b16d94660a33 491 __IO uint32_t I2SRXMODE;
Jasper_lee 0:b16d94660a33 492 } LPC_I2S_TypeDef;
Jasper_lee 0:b16d94660a33 493
Jasper_lee 0:b16d94660a33 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
Jasper_lee 0:b16d94660a33 495 typedef struct
Jasper_lee 0:b16d94660a33 496 {
Jasper_lee 0:b16d94660a33 497 __IO uint32_t RICOMPVAL;
Jasper_lee 0:b16d94660a33 498 __IO uint32_t RIMASK;
Jasper_lee 0:b16d94660a33 499 __IO uint8_t RICTRL;
Jasper_lee 0:b16d94660a33 500 uint8_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 501 __IO uint32_t RICOUNTER;
Jasper_lee 0:b16d94660a33 502 } LPC_RIT_TypeDef;
Jasper_lee 0:b16d94660a33 503
Jasper_lee 0:b16d94660a33 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
Jasper_lee 0:b16d94660a33 505 typedef struct
Jasper_lee 0:b16d94660a33 506 {
Jasper_lee 0:b16d94660a33 507 __IO uint8_t ILR;
Jasper_lee 0:b16d94660a33 508 uint8_t RESERVED0[7];
Jasper_lee 0:b16d94660a33 509 __IO uint8_t CCR;
Jasper_lee 0:b16d94660a33 510 uint8_t RESERVED1[3];
Jasper_lee 0:b16d94660a33 511 __IO uint8_t CIIR;
Jasper_lee 0:b16d94660a33 512 uint8_t RESERVED2[3];
Jasper_lee 0:b16d94660a33 513 __IO uint8_t AMR;
Jasper_lee 0:b16d94660a33 514 uint8_t RESERVED3[3];
Jasper_lee 0:b16d94660a33 515 __I uint32_t CTIME0;
Jasper_lee 0:b16d94660a33 516 __I uint32_t CTIME1;
Jasper_lee 0:b16d94660a33 517 __I uint32_t CTIME2;
Jasper_lee 0:b16d94660a33 518 __IO uint8_t SEC;
Jasper_lee 0:b16d94660a33 519 uint8_t RESERVED4[3];
Jasper_lee 0:b16d94660a33 520 __IO uint8_t MIN;
Jasper_lee 0:b16d94660a33 521 uint8_t RESERVED5[3];
Jasper_lee 0:b16d94660a33 522 __IO uint8_t HOUR;
Jasper_lee 0:b16d94660a33 523 uint8_t RESERVED6[3];
Jasper_lee 0:b16d94660a33 524 __IO uint8_t DOM;
Jasper_lee 0:b16d94660a33 525 uint8_t RESERVED7[3];
Jasper_lee 0:b16d94660a33 526 __IO uint8_t DOW;
Jasper_lee 0:b16d94660a33 527 uint8_t RESERVED8[3];
Jasper_lee 0:b16d94660a33 528 __IO uint16_t DOY;
Jasper_lee 0:b16d94660a33 529 uint16_t RESERVED9;
Jasper_lee 0:b16d94660a33 530 __IO uint8_t MONTH;
Jasper_lee 0:b16d94660a33 531 uint8_t RESERVED10[3];
Jasper_lee 0:b16d94660a33 532 __IO uint16_t YEAR;
Jasper_lee 0:b16d94660a33 533 uint16_t RESERVED11;
Jasper_lee 0:b16d94660a33 534 __IO uint32_t CALIBRATION;
Jasper_lee 0:b16d94660a33 535 __IO uint32_t GPREG0;
Jasper_lee 0:b16d94660a33 536 __IO uint32_t GPREG1;
Jasper_lee 0:b16d94660a33 537 __IO uint32_t GPREG2;
Jasper_lee 0:b16d94660a33 538 __IO uint32_t GPREG3;
Jasper_lee 0:b16d94660a33 539 __IO uint32_t GPREG4;
Jasper_lee 0:b16d94660a33 540 __IO uint8_t RTC_AUXEN;
Jasper_lee 0:b16d94660a33 541 uint8_t RESERVED12[3];
Jasper_lee 0:b16d94660a33 542 __IO uint8_t RTC_AUX;
Jasper_lee 0:b16d94660a33 543 uint8_t RESERVED13[3];
Jasper_lee 0:b16d94660a33 544 __IO uint8_t ALSEC;
Jasper_lee 0:b16d94660a33 545 uint8_t RESERVED14[3];
Jasper_lee 0:b16d94660a33 546 __IO uint8_t ALMIN;
Jasper_lee 0:b16d94660a33 547 uint8_t RESERVED15[3];
Jasper_lee 0:b16d94660a33 548 __IO uint8_t ALHOUR;
Jasper_lee 0:b16d94660a33 549 uint8_t RESERVED16[3];
Jasper_lee 0:b16d94660a33 550 __IO uint8_t ALDOM;
Jasper_lee 0:b16d94660a33 551 uint8_t RESERVED17[3];
Jasper_lee 0:b16d94660a33 552 __IO uint8_t ALDOW;
Jasper_lee 0:b16d94660a33 553 uint8_t RESERVED18[3];
Jasper_lee 0:b16d94660a33 554 __IO uint16_t ALDOY;
Jasper_lee 0:b16d94660a33 555 uint16_t RESERVED19;
Jasper_lee 0:b16d94660a33 556 __IO uint8_t ALMON;
Jasper_lee 0:b16d94660a33 557 uint8_t RESERVED20[3];
Jasper_lee 0:b16d94660a33 558 __IO uint16_t ALYEAR;
Jasper_lee 0:b16d94660a33 559 uint16_t RESERVED21;
Jasper_lee 0:b16d94660a33 560 } LPC_RTC_TypeDef;
Jasper_lee 0:b16d94660a33 561
Jasper_lee 0:b16d94660a33 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
Jasper_lee 0:b16d94660a33 563 typedef struct
Jasper_lee 0:b16d94660a33 564 {
Jasper_lee 0:b16d94660a33 565 __IO uint8_t WDMOD;
Jasper_lee 0:b16d94660a33 566 uint8_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 567 __IO uint32_t WDTC;
Jasper_lee 0:b16d94660a33 568 __O uint8_t WDFEED;
Jasper_lee 0:b16d94660a33 569 uint8_t RESERVED1[3];
Jasper_lee 0:b16d94660a33 570 __I uint32_t WDTV;
Jasper_lee 0:b16d94660a33 571 __IO uint32_t WDCLKSEL;
Jasper_lee 0:b16d94660a33 572 } LPC_WDT_TypeDef;
Jasper_lee 0:b16d94660a33 573
Jasper_lee 0:b16d94660a33 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
Jasper_lee 0:b16d94660a33 575 typedef struct
Jasper_lee 0:b16d94660a33 576 {
Jasper_lee 0:b16d94660a33 577 __IO uint32_t ADCR;
Jasper_lee 0:b16d94660a33 578 __IO uint32_t ADGDR;
Jasper_lee 0:b16d94660a33 579 uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 580 __IO uint32_t ADINTEN;
Jasper_lee 0:b16d94660a33 581 __I uint32_t ADDR0;
Jasper_lee 0:b16d94660a33 582 __I uint32_t ADDR1;
Jasper_lee 0:b16d94660a33 583 __I uint32_t ADDR2;
Jasper_lee 0:b16d94660a33 584 __I uint32_t ADDR3;
Jasper_lee 0:b16d94660a33 585 __I uint32_t ADDR4;
Jasper_lee 0:b16d94660a33 586 __I uint32_t ADDR5;
Jasper_lee 0:b16d94660a33 587 __I uint32_t ADDR6;
Jasper_lee 0:b16d94660a33 588 __I uint32_t ADDR7;
Jasper_lee 0:b16d94660a33 589 __I uint32_t ADSTAT;
Jasper_lee 0:b16d94660a33 590 __IO uint32_t ADTRM;
Jasper_lee 0:b16d94660a33 591 } LPC_ADC_TypeDef;
Jasper_lee 0:b16d94660a33 592
Jasper_lee 0:b16d94660a33 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
Jasper_lee 0:b16d94660a33 594 typedef struct
Jasper_lee 0:b16d94660a33 595 {
Jasper_lee 0:b16d94660a33 596 __IO uint32_t DACR;
Jasper_lee 0:b16d94660a33 597 __IO uint32_t DACCTRL;
Jasper_lee 0:b16d94660a33 598 __IO uint16_t DACCNTVAL;
Jasper_lee 0:b16d94660a33 599 } LPC_DAC_TypeDef;
Jasper_lee 0:b16d94660a33 600
Jasper_lee 0:b16d94660a33 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
Jasper_lee 0:b16d94660a33 602 typedef struct
Jasper_lee 0:b16d94660a33 603 {
Jasper_lee 0:b16d94660a33 604 __I uint32_t MCCON;
Jasper_lee 0:b16d94660a33 605 __O uint32_t MCCON_SET;
Jasper_lee 0:b16d94660a33 606 __O uint32_t MCCON_CLR;
Jasper_lee 0:b16d94660a33 607 __I uint32_t MCCAPCON;
Jasper_lee 0:b16d94660a33 608 __O uint32_t MCCAPCON_SET;
Jasper_lee 0:b16d94660a33 609 __O uint32_t MCCAPCON_CLR;
Jasper_lee 0:b16d94660a33 610 __IO uint32_t MCTIM0;
Jasper_lee 0:b16d94660a33 611 __IO uint32_t MCTIM1;
Jasper_lee 0:b16d94660a33 612 __IO uint32_t MCTIM2;
Jasper_lee 0:b16d94660a33 613 __IO uint32_t MCPER0;
Jasper_lee 0:b16d94660a33 614 __IO uint32_t MCPER1;
Jasper_lee 0:b16d94660a33 615 __IO uint32_t MCPER2;
Jasper_lee 0:b16d94660a33 616 __IO uint32_t MCPW0;
Jasper_lee 0:b16d94660a33 617 __IO uint32_t MCPW1;
Jasper_lee 0:b16d94660a33 618 __IO uint32_t MCPW2;
Jasper_lee 0:b16d94660a33 619 __IO uint32_t MCDEADTIME;
Jasper_lee 0:b16d94660a33 620 __IO uint32_t MCCCP;
Jasper_lee 0:b16d94660a33 621 __IO uint32_t MCCR0;
Jasper_lee 0:b16d94660a33 622 __IO uint32_t MCCR1;
Jasper_lee 0:b16d94660a33 623 __IO uint32_t MCCR2;
Jasper_lee 0:b16d94660a33 624 __I uint32_t MCINTEN;
Jasper_lee 0:b16d94660a33 625 __O uint32_t MCINTEN_SET;
Jasper_lee 0:b16d94660a33 626 __O uint32_t MCINTEN_CLR;
Jasper_lee 0:b16d94660a33 627 __I uint32_t MCCNTCON;
Jasper_lee 0:b16d94660a33 628 __O uint32_t MCCNTCON_SET;
Jasper_lee 0:b16d94660a33 629 __O uint32_t MCCNTCON_CLR;
Jasper_lee 0:b16d94660a33 630 __I uint32_t MCINTFLAG;
Jasper_lee 0:b16d94660a33 631 __O uint32_t MCINTFLAG_SET;
Jasper_lee 0:b16d94660a33 632 __O uint32_t MCINTFLAG_CLR;
Jasper_lee 0:b16d94660a33 633 __O uint32_t MCCAP_CLR;
Jasper_lee 0:b16d94660a33 634 } LPC_MCPWM_TypeDef;
Jasper_lee 0:b16d94660a33 635
Jasper_lee 0:b16d94660a33 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
Jasper_lee 0:b16d94660a33 637 typedef struct
Jasper_lee 0:b16d94660a33 638 {
Jasper_lee 0:b16d94660a33 639 __O uint32_t QEICON;
Jasper_lee 0:b16d94660a33 640 __I uint32_t QEISTAT;
Jasper_lee 0:b16d94660a33 641 __IO uint32_t QEICONF;
Jasper_lee 0:b16d94660a33 642 __I uint32_t QEIPOS;
Jasper_lee 0:b16d94660a33 643 __IO uint32_t QEIMAXPOS;
Jasper_lee 0:b16d94660a33 644 __IO uint32_t CMPOS0;
Jasper_lee 0:b16d94660a33 645 __IO uint32_t CMPOS1;
Jasper_lee 0:b16d94660a33 646 __IO uint32_t CMPOS2;
Jasper_lee 0:b16d94660a33 647 __I uint32_t INXCNT;
Jasper_lee 0:b16d94660a33 648 __IO uint32_t INXCMP;
Jasper_lee 0:b16d94660a33 649 __IO uint32_t QEILOAD;
Jasper_lee 0:b16d94660a33 650 __I uint32_t QEITIME;
Jasper_lee 0:b16d94660a33 651 __I uint32_t QEIVEL;
Jasper_lee 0:b16d94660a33 652 __I uint32_t QEICAP;
Jasper_lee 0:b16d94660a33 653 __IO uint32_t VELCOMP;
Jasper_lee 0:b16d94660a33 654 __IO uint32_t FILTER;
Jasper_lee 0:b16d94660a33 655 uint32_t RESERVED0[998];
Jasper_lee 0:b16d94660a33 656 __O uint32_t QEIIEC;
Jasper_lee 0:b16d94660a33 657 __O uint32_t QEIIES;
Jasper_lee 0:b16d94660a33 658 __I uint32_t QEIINTSTAT;
Jasper_lee 0:b16d94660a33 659 __I uint32_t QEIIE;
Jasper_lee 0:b16d94660a33 660 __O uint32_t QEICLR;
Jasper_lee 0:b16d94660a33 661 __O uint32_t QEISET;
Jasper_lee 0:b16d94660a33 662 } LPC_QEI_TypeDef;
Jasper_lee 0:b16d94660a33 663
Jasper_lee 0:b16d94660a33 664 /*------------- Controller Area Network (CAN) --------------------------------*/
Jasper_lee 0:b16d94660a33 665 typedef struct
Jasper_lee 0:b16d94660a33 666 {
Jasper_lee 0:b16d94660a33 667 __IO uint32_t mask[512]; /* ID Masks */
Jasper_lee 0:b16d94660a33 668 } LPC_CANAF_RAM_TypeDef;
Jasper_lee 0:b16d94660a33 669
Jasper_lee 0:b16d94660a33 670 typedef struct /* Acceptance Filter Registers */
Jasper_lee 0:b16d94660a33 671 {
Jasper_lee 0:b16d94660a33 672 __IO uint32_t AFMR;
Jasper_lee 0:b16d94660a33 673 __IO uint32_t SFF_sa;
Jasper_lee 0:b16d94660a33 674 __IO uint32_t SFF_GRP_sa;
Jasper_lee 0:b16d94660a33 675 __IO uint32_t EFF_sa;
Jasper_lee 0:b16d94660a33 676 __IO uint32_t EFF_GRP_sa;
Jasper_lee 0:b16d94660a33 677 __IO uint32_t ENDofTable;
Jasper_lee 0:b16d94660a33 678 __I uint32_t LUTerrAd;
Jasper_lee 0:b16d94660a33 679 __I uint32_t LUTerr;
Jasper_lee 0:b16d94660a33 680 __IO uint32_t FCANIE;
Jasper_lee 0:b16d94660a33 681 __IO uint32_t FCANIC0;
Jasper_lee 0:b16d94660a33 682 __IO uint32_t FCANIC1;
Jasper_lee 0:b16d94660a33 683 } LPC_CANAF_TypeDef;
Jasper_lee 0:b16d94660a33 684
Jasper_lee 0:b16d94660a33 685 typedef struct /* Central Registers */
Jasper_lee 0:b16d94660a33 686 {
Jasper_lee 0:b16d94660a33 687 __I uint32_t CANTxSR;
Jasper_lee 0:b16d94660a33 688 __I uint32_t CANRxSR;
Jasper_lee 0:b16d94660a33 689 __I uint32_t CANMSR;
Jasper_lee 0:b16d94660a33 690 } LPC_CANCR_TypeDef;
Jasper_lee 0:b16d94660a33 691
Jasper_lee 0:b16d94660a33 692 typedef struct /* Controller Registers */
Jasper_lee 0:b16d94660a33 693 {
Jasper_lee 0:b16d94660a33 694 __IO uint32_t MOD;
Jasper_lee 0:b16d94660a33 695 __O uint32_t CMR;
Jasper_lee 0:b16d94660a33 696 __IO uint32_t GSR;
Jasper_lee 0:b16d94660a33 697 __I uint32_t ICR;
Jasper_lee 0:b16d94660a33 698 __IO uint32_t IER;
Jasper_lee 0:b16d94660a33 699 __IO uint32_t BTR;
Jasper_lee 0:b16d94660a33 700 __IO uint32_t EWL;
Jasper_lee 0:b16d94660a33 701 __I uint32_t SR;
Jasper_lee 0:b16d94660a33 702 __IO uint32_t RFS;
Jasper_lee 0:b16d94660a33 703 __IO uint32_t RID;
Jasper_lee 0:b16d94660a33 704 __IO uint32_t RDA;
Jasper_lee 0:b16d94660a33 705 __IO uint32_t RDB;
Jasper_lee 0:b16d94660a33 706 __IO uint32_t TFI1;
Jasper_lee 0:b16d94660a33 707 __IO uint32_t TID1;
Jasper_lee 0:b16d94660a33 708 __IO uint32_t TDA1;
Jasper_lee 0:b16d94660a33 709 __IO uint32_t TDB1;
Jasper_lee 0:b16d94660a33 710 __IO uint32_t TFI2;
Jasper_lee 0:b16d94660a33 711 __IO uint32_t TID2;
Jasper_lee 0:b16d94660a33 712 __IO uint32_t TDA2;
Jasper_lee 0:b16d94660a33 713 __IO uint32_t TDB2;
Jasper_lee 0:b16d94660a33 714 __IO uint32_t TFI3;
Jasper_lee 0:b16d94660a33 715 __IO uint32_t TID3;
Jasper_lee 0:b16d94660a33 716 __IO uint32_t TDA3;
Jasper_lee 0:b16d94660a33 717 __IO uint32_t TDB3;
Jasper_lee 0:b16d94660a33 718 } LPC_CAN_TypeDef;
Jasper_lee 0:b16d94660a33 719
Jasper_lee 0:b16d94660a33 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
Jasper_lee 0:b16d94660a33 721 typedef struct /* Common Registers */
Jasper_lee 0:b16d94660a33 722 {
Jasper_lee 0:b16d94660a33 723 __I uint32_t DMACIntStat;
Jasper_lee 0:b16d94660a33 724 __I uint32_t DMACIntTCStat;
Jasper_lee 0:b16d94660a33 725 __O uint32_t DMACIntTCClear;
Jasper_lee 0:b16d94660a33 726 __I uint32_t DMACIntErrStat;
Jasper_lee 0:b16d94660a33 727 __O uint32_t DMACIntErrClr;
Jasper_lee 0:b16d94660a33 728 __I uint32_t DMACRawIntTCStat;
Jasper_lee 0:b16d94660a33 729 __I uint32_t DMACRawIntErrStat;
Jasper_lee 0:b16d94660a33 730 __I uint32_t DMACEnbldChns;
Jasper_lee 0:b16d94660a33 731 __IO uint32_t DMACSoftBReq;
Jasper_lee 0:b16d94660a33 732 __IO uint32_t DMACSoftSReq;
Jasper_lee 0:b16d94660a33 733 __IO uint32_t DMACSoftLBReq;
Jasper_lee 0:b16d94660a33 734 __IO uint32_t DMACSoftLSReq;
Jasper_lee 0:b16d94660a33 735 __IO uint32_t DMACConfig;
Jasper_lee 0:b16d94660a33 736 __IO uint32_t DMACSync;
Jasper_lee 0:b16d94660a33 737 } LPC_GPDMA_TypeDef;
Jasper_lee 0:b16d94660a33 738
Jasper_lee 0:b16d94660a33 739 typedef struct /* Channel Registers */
Jasper_lee 0:b16d94660a33 740 {
Jasper_lee 0:b16d94660a33 741 __IO uint32_t DMACCSrcAddr;
Jasper_lee 0:b16d94660a33 742 __IO uint32_t DMACCDestAddr;
Jasper_lee 0:b16d94660a33 743 __IO uint32_t DMACCLLI;
Jasper_lee 0:b16d94660a33 744 __IO uint32_t DMACCControl;
Jasper_lee 0:b16d94660a33 745 __IO uint32_t DMACCConfig;
Jasper_lee 0:b16d94660a33 746 } LPC_GPDMACH_TypeDef;
Jasper_lee 0:b16d94660a33 747
Jasper_lee 0:b16d94660a33 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
Jasper_lee 0:b16d94660a33 749 typedef struct
Jasper_lee 0:b16d94660a33 750 {
Jasper_lee 0:b16d94660a33 751 __I uint32_t HcRevision; /* USB Host Registers */
Jasper_lee 0:b16d94660a33 752 __IO uint32_t HcControl;
Jasper_lee 0:b16d94660a33 753 __IO uint32_t HcCommandStatus;
Jasper_lee 0:b16d94660a33 754 __IO uint32_t HcInterruptStatus;
Jasper_lee 0:b16d94660a33 755 __IO uint32_t HcInterruptEnable;
Jasper_lee 0:b16d94660a33 756 __IO uint32_t HcInterruptDisable;
Jasper_lee 0:b16d94660a33 757 __IO uint32_t HcHCCA;
Jasper_lee 0:b16d94660a33 758 __I uint32_t HcPeriodCurrentED;
Jasper_lee 0:b16d94660a33 759 __IO uint32_t HcControlHeadED;
Jasper_lee 0:b16d94660a33 760 __IO uint32_t HcControlCurrentED;
Jasper_lee 0:b16d94660a33 761 __IO uint32_t HcBulkHeadED;
Jasper_lee 0:b16d94660a33 762 __IO uint32_t HcBulkCurrentED;
Jasper_lee 0:b16d94660a33 763 __I uint32_t HcDoneHead;
Jasper_lee 0:b16d94660a33 764 __IO uint32_t HcFmInterval;
Jasper_lee 0:b16d94660a33 765 __I uint32_t HcFmRemaining;
Jasper_lee 0:b16d94660a33 766 __I uint32_t HcFmNumber;
Jasper_lee 0:b16d94660a33 767 __IO uint32_t HcPeriodicStart;
Jasper_lee 0:b16d94660a33 768 __IO uint32_t HcLSTreshold;
Jasper_lee 0:b16d94660a33 769 __IO uint32_t HcRhDescriptorA;
Jasper_lee 0:b16d94660a33 770 __IO uint32_t HcRhDescriptorB;
Jasper_lee 0:b16d94660a33 771 __IO uint32_t HcRhStatus;
Jasper_lee 0:b16d94660a33 772 __IO uint32_t HcRhPortStatus1;
Jasper_lee 0:b16d94660a33 773 __IO uint32_t HcRhPortStatus2;
Jasper_lee 0:b16d94660a33 774 uint32_t RESERVED0[40];
Jasper_lee 0:b16d94660a33 775 __I uint32_t Module_ID;
Jasper_lee 0:b16d94660a33 776
Jasper_lee 0:b16d94660a33 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
Jasper_lee 0:b16d94660a33 778 __IO uint32_t OTGIntEn;
Jasper_lee 0:b16d94660a33 779 __O uint32_t OTGIntSet;
Jasper_lee 0:b16d94660a33 780 __O uint32_t OTGIntClr;
Jasper_lee 0:b16d94660a33 781 __IO uint32_t OTGStCtrl;
Jasper_lee 0:b16d94660a33 782 __IO uint32_t OTGTmr;
Jasper_lee 0:b16d94660a33 783 uint32_t RESERVED1[58];
Jasper_lee 0:b16d94660a33 784
Jasper_lee 0:b16d94660a33 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
Jasper_lee 0:b16d94660a33 786 __IO uint32_t USBDevIntEn;
Jasper_lee 0:b16d94660a33 787 __O uint32_t USBDevIntClr;
Jasper_lee 0:b16d94660a33 788 __O uint32_t USBDevIntSet;
Jasper_lee 0:b16d94660a33 789
Jasper_lee 0:b16d94660a33 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
Jasper_lee 0:b16d94660a33 791 __I uint32_t USBCmdData;
Jasper_lee 0:b16d94660a33 792
Jasper_lee 0:b16d94660a33 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
Jasper_lee 0:b16d94660a33 794 __O uint32_t USBTxData;
Jasper_lee 0:b16d94660a33 795 __I uint32_t USBRxPLen;
Jasper_lee 0:b16d94660a33 796 __O uint32_t USBTxPLen;
Jasper_lee 0:b16d94660a33 797 __IO uint32_t USBCtrl;
Jasper_lee 0:b16d94660a33 798 __O uint32_t USBDevIntPri;
Jasper_lee 0:b16d94660a33 799
Jasper_lee 0:b16d94660a33 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
Jasper_lee 0:b16d94660a33 801 __IO uint32_t USBEpIntEn;
Jasper_lee 0:b16d94660a33 802 __O uint32_t USBEpIntClr;
Jasper_lee 0:b16d94660a33 803 __O uint32_t USBEpIntSet;
Jasper_lee 0:b16d94660a33 804 __O uint32_t USBEpIntPri;
Jasper_lee 0:b16d94660a33 805
Jasper_lee 0:b16d94660a33 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
Jasper_lee 0:b16d94660a33 807 __O uint32_t USBEpInd;
Jasper_lee 0:b16d94660a33 808 __IO uint32_t USBMaxPSize;
Jasper_lee 0:b16d94660a33 809
Jasper_lee 0:b16d94660a33 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
Jasper_lee 0:b16d94660a33 811 __O uint32_t USBDMARClr;
Jasper_lee 0:b16d94660a33 812 __O uint32_t USBDMARSet;
Jasper_lee 0:b16d94660a33 813 uint32_t RESERVED2[9];
Jasper_lee 0:b16d94660a33 814 __IO uint32_t USBUDCAH;
Jasper_lee 0:b16d94660a33 815 __I uint32_t USBEpDMASt;
Jasper_lee 0:b16d94660a33 816 __O uint32_t USBEpDMAEn;
Jasper_lee 0:b16d94660a33 817 __O uint32_t USBEpDMADis;
Jasper_lee 0:b16d94660a33 818 __I uint32_t USBDMAIntSt;
Jasper_lee 0:b16d94660a33 819 __IO uint32_t USBDMAIntEn;
Jasper_lee 0:b16d94660a33 820 uint32_t RESERVED3[2];
Jasper_lee 0:b16d94660a33 821 __I uint32_t USBEoTIntSt;
Jasper_lee 0:b16d94660a33 822 __O uint32_t USBEoTIntClr;
Jasper_lee 0:b16d94660a33 823 __O uint32_t USBEoTIntSet;
Jasper_lee 0:b16d94660a33 824 __I uint32_t USBNDDRIntSt;
Jasper_lee 0:b16d94660a33 825 __O uint32_t USBNDDRIntClr;
Jasper_lee 0:b16d94660a33 826 __O uint32_t USBNDDRIntSet;
Jasper_lee 0:b16d94660a33 827 __I uint32_t USBSysErrIntSt;
Jasper_lee 0:b16d94660a33 828 __O uint32_t USBSysErrIntClr;
Jasper_lee 0:b16d94660a33 829 __O uint32_t USBSysErrIntSet;
Jasper_lee 0:b16d94660a33 830 uint32_t RESERVED4[15];
Jasper_lee 0:b16d94660a33 831
Jasper_lee 0:b16d94660a33 832 union {
Jasper_lee 0:b16d94660a33 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
Jasper_lee 0:b16d94660a33 834 __O uint32_t I2C_TX;
Jasper_lee 0:b16d94660a33 835 };
Jasper_lee 0:b16d94660a33 836 __I uint32_t I2C_STS;
Jasper_lee 0:b16d94660a33 837 __IO uint32_t I2C_CTL;
Jasper_lee 0:b16d94660a33 838 __IO uint32_t I2C_CLKHI;
Jasper_lee 0:b16d94660a33 839 __O uint32_t I2C_CLKLO;
Jasper_lee 0:b16d94660a33 840 uint32_t RESERVED5[824];
Jasper_lee 0:b16d94660a33 841
Jasper_lee 0:b16d94660a33 842 union {
Jasper_lee 0:b16d94660a33 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
Jasper_lee 0:b16d94660a33 844 __IO uint32_t OTGClkCtrl;
Jasper_lee 0:b16d94660a33 845 };
Jasper_lee 0:b16d94660a33 846 union {
Jasper_lee 0:b16d94660a33 847 __I uint32_t USBClkSt;
Jasper_lee 0:b16d94660a33 848 __I uint32_t OTGClkSt;
Jasper_lee 0:b16d94660a33 849 };
Jasper_lee 0:b16d94660a33 850 } LPC_USB_TypeDef;
Jasper_lee 0:b16d94660a33 851
Jasper_lee 0:b16d94660a33 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
Jasper_lee 0:b16d94660a33 853 typedef struct
Jasper_lee 0:b16d94660a33 854 {
Jasper_lee 0:b16d94660a33 855 __IO uint32_t MAC1; /* MAC Registers */
Jasper_lee 0:b16d94660a33 856 __IO uint32_t MAC2;
Jasper_lee 0:b16d94660a33 857 __IO uint32_t IPGT;
Jasper_lee 0:b16d94660a33 858 __IO uint32_t IPGR;
Jasper_lee 0:b16d94660a33 859 __IO uint32_t CLRT;
Jasper_lee 0:b16d94660a33 860 __IO uint32_t MAXF;
Jasper_lee 0:b16d94660a33 861 __IO uint32_t SUPP;
Jasper_lee 0:b16d94660a33 862 __IO uint32_t TEST;
Jasper_lee 0:b16d94660a33 863 __IO uint32_t MCFG;
Jasper_lee 0:b16d94660a33 864 __IO uint32_t MCMD;
Jasper_lee 0:b16d94660a33 865 __IO uint32_t MADR;
Jasper_lee 0:b16d94660a33 866 __O uint32_t MWTD;
Jasper_lee 0:b16d94660a33 867 __I uint32_t MRDD;
Jasper_lee 0:b16d94660a33 868 __I uint32_t MIND;
Jasper_lee 0:b16d94660a33 869 uint32_t RESERVED0[2];
Jasper_lee 0:b16d94660a33 870 __IO uint32_t SA0;
Jasper_lee 0:b16d94660a33 871 __IO uint32_t SA1;
Jasper_lee 0:b16d94660a33 872 __IO uint32_t SA2;
Jasper_lee 0:b16d94660a33 873 uint32_t RESERVED1[45];
Jasper_lee 0:b16d94660a33 874 __IO uint32_t Command; /* Control Registers */
Jasper_lee 0:b16d94660a33 875 __I uint32_t Status;
Jasper_lee 0:b16d94660a33 876 __IO uint32_t RxDescriptor;
Jasper_lee 0:b16d94660a33 877 __IO uint32_t RxStatus;
Jasper_lee 0:b16d94660a33 878 __IO uint32_t RxDescriptorNumber;
Jasper_lee 0:b16d94660a33 879 __I uint32_t RxProduceIndex;
Jasper_lee 0:b16d94660a33 880 __IO uint32_t RxConsumeIndex;
Jasper_lee 0:b16d94660a33 881 __IO uint32_t TxDescriptor;
Jasper_lee 0:b16d94660a33 882 __IO uint32_t TxStatus;
Jasper_lee 0:b16d94660a33 883 __IO uint32_t TxDescriptorNumber;
Jasper_lee 0:b16d94660a33 884 __IO uint32_t TxProduceIndex;
Jasper_lee 0:b16d94660a33 885 __I uint32_t TxConsumeIndex;
Jasper_lee 0:b16d94660a33 886 uint32_t RESERVED2[10];
Jasper_lee 0:b16d94660a33 887 __I uint32_t TSV0;
Jasper_lee 0:b16d94660a33 888 __I uint32_t TSV1;
Jasper_lee 0:b16d94660a33 889 __I uint32_t RSV;
Jasper_lee 0:b16d94660a33 890 uint32_t RESERVED3[3];
Jasper_lee 0:b16d94660a33 891 __IO uint32_t FlowControlCounter;
Jasper_lee 0:b16d94660a33 892 __I uint32_t FlowControlStatus;
Jasper_lee 0:b16d94660a33 893 uint32_t RESERVED4[34];
Jasper_lee 0:b16d94660a33 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
Jasper_lee 0:b16d94660a33 895 __IO uint32_t RxFilterWoLStatus;
Jasper_lee 0:b16d94660a33 896 __IO uint32_t RxFilterWoLClear;
Jasper_lee 0:b16d94660a33 897 uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 898 __IO uint32_t HashFilterL;
Jasper_lee 0:b16d94660a33 899 __IO uint32_t HashFilterH;
Jasper_lee 0:b16d94660a33 900 uint32_t RESERVED6[882];
Jasper_lee 0:b16d94660a33 901 __I uint32_t IntStatus; /* Module Control Registers */
Jasper_lee 0:b16d94660a33 902 __IO uint32_t IntEnable;
Jasper_lee 0:b16d94660a33 903 __O uint32_t IntClear;
Jasper_lee 0:b16d94660a33 904 __O uint32_t IntSet;
Jasper_lee 0:b16d94660a33 905 uint32_t RESERVED7;
Jasper_lee 0:b16d94660a33 906 __IO uint32_t PowerDown;
Jasper_lee 0:b16d94660a33 907 uint32_t RESERVED8;
Jasper_lee 0:b16d94660a33 908 __IO uint32_t Module_ID;
Jasper_lee 0:b16d94660a33 909 } LPC_EMAC_TypeDef;
Jasper_lee 0:b16d94660a33 910
Jasper_lee 0:b16d94660a33 911 #if defined ( __CC_ARM )
Jasper_lee 0:b16d94660a33 912 #pragma no_anon_unions
Jasper_lee 0:b16d94660a33 913 #endif
Jasper_lee 0:b16d94660a33 914
Jasper_lee 0:b16d94660a33 915
Jasper_lee 0:b16d94660a33 916 /******************************************************************************/
Jasper_lee 0:b16d94660a33 917 /* Peripheral memory map */
Jasper_lee 0:b16d94660a33 918 /******************************************************************************/
Jasper_lee 0:b16d94660a33 919 /* Base addresses */
Jasper_lee 0:b16d94660a33 920 #define LPC_FLASH_BASE (0x00000000UL)
Jasper_lee 0:b16d94660a33 921 #define LPC_RAM_BASE (0x10000000UL)
Jasper_lee 0:b16d94660a33 922 #define LPC_GPIO_BASE (0x2009C000UL)
Jasper_lee 0:b16d94660a33 923 #define LPC_APB0_BASE (0x40000000UL)
Jasper_lee 0:b16d94660a33 924 #define LPC_APB1_BASE (0x40080000UL)
Jasper_lee 0:b16d94660a33 925 #define LPC_AHB_BASE (0x50000000UL)
Jasper_lee 0:b16d94660a33 926 #define LPC_CM3_BASE (0xE0000000UL)
Jasper_lee 0:b16d94660a33 927
Jasper_lee 0:b16d94660a33 928 /* APB0 peripherals */
Jasper_lee 0:b16d94660a33 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
Jasper_lee 0:b16d94660a33 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
Jasper_lee 0:b16d94660a33 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
Jasper_lee 0:b16d94660a33 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
Jasper_lee 0:b16d94660a33 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
Jasper_lee 0:b16d94660a33 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
Jasper_lee 0:b16d94660a33 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
Jasper_lee 0:b16d94660a33 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
Jasper_lee 0:b16d94660a33 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
Jasper_lee 0:b16d94660a33 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
Jasper_lee 0:b16d94660a33 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
Jasper_lee 0:b16d94660a33 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
Jasper_lee 0:b16d94660a33 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
Jasper_lee 0:b16d94660a33 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
Jasper_lee 0:b16d94660a33 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
Jasper_lee 0:b16d94660a33 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
Jasper_lee 0:b16d94660a33 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
Jasper_lee 0:b16d94660a33 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
Jasper_lee 0:b16d94660a33 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
Jasper_lee 0:b16d94660a33 948
Jasper_lee 0:b16d94660a33 949 /* APB1 peripherals */
Jasper_lee 0:b16d94660a33 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
Jasper_lee 0:b16d94660a33 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
Jasper_lee 0:b16d94660a33 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
Jasper_lee 0:b16d94660a33 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
Jasper_lee 0:b16d94660a33 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
Jasper_lee 0:b16d94660a33 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
Jasper_lee 0:b16d94660a33 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
Jasper_lee 0:b16d94660a33 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
Jasper_lee 0:b16d94660a33 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
Jasper_lee 0:b16d94660a33 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
Jasper_lee 0:b16d94660a33 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
Jasper_lee 0:b16d94660a33 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
Jasper_lee 0:b16d94660a33 962
Jasper_lee 0:b16d94660a33 963 /* AHB peripherals */
Jasper_lee 0:b16d94660a33 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
Jasper_lee 0:b16d94660a33 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
Jasper_lee 0:b16d94660a33 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
Jasper_lee 0:b16d94660a33 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
Jasper_lee 0:b16d94660a33 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
Jasper_lee 0:b16d94660a33 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
Jasper_lee 0:b16d94660a33 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
Jasper_lee 0:b16d94660a33 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
Jasper_lee 0:b16d94660a33 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
Jasper_lee 0:b16d94660a33 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
Jasper_lee 0:b16d94660a33 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
Jasper_lee 0:b16d94660a33 975
Jasper_lee 0:b16d94660a33 976 /* GPIOs */
Jasper_lee 0:b16d94660a33 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
Jasper_lee 0:b16d94660a33 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
Jasper_lee 0:b16d94660a33 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
Jasper_lee 0:b16d94660a33 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
Jasper_lee 0:b16d94660a33 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
Jasper_lee 0:b16d94660a33 982
Jasper_lee 0:b16d94660a33 983
Jasper_lee 0:b16d94660a33 984 /******************************************************************************/
Jasper_lee 0:b16d94660a33 985 /* Peripheral declaration */
Jasper_lee 0:b16d94660a33 986 /******************************************************************************/
Jasper_lee 0:b16d94660a33 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
Jasper_lee 0:b16d94660a33 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
Jasper_lee 0:b16d94660a33 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
Jasper_lee 0:b16d94660a33 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
Jasper_lee 0:b16d94660a33 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
Jasper_lee 0:b16d94660a33 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
Jasper_lee 0:b16d94660a33 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
Jasper_lee 0:b16d94660a33 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
Jasper_lee 0:b16d94660a33 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
Jasper_lee 0:b16d94660a33 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
Jasper_lee 0:b16d94660a33 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
Jasper_lee 0:b16d94660a33 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
Jasper_lee 0:b16d94660a33 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
Jasper_lee 0:b16d94660a33 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
Jasper_lee 0:b16d94660a33 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
Jasper_lee 0:b16d94660a33 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
Jasper_lee 0:b16d94660a33 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
Jasper_lee 0:b16d94660a33 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
Jasper_lee 0:b16d94660a33 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
Jasper_lee 0:b16d94660a33 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
Jasper_lee 0:b16d94660a33 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
Jasper_lee 0:b16d94660a33 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
Jasper_lee 0:b16d94660a33 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
Jasper_lee 0:b16d94660a33 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
Jasper_lee 0:b16d94660a33 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
Jasper_lee 0:b16d94660a33 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
Jasper_lee 0:b16d94660a33 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
Jasper_lee 0:b16d94660a33 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
Jasper_lee 0:b16d94660a33 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
Jasper_lee 0:b16d94660a33 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
Jasper_lee 0:b16d94660a33 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
Jasper_lee 0:b16d94660a33 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
Jasper_lee 0:b16d94660a33 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
Jasper_lee 0:b16d94660a33 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
Jasper_lee 0:b16d94660a33 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
Jasper_lee 0:b16d94660a33 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
Jasper_lee 0:b16d94660a33 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
Jasper_lee 0:b16d94660a33 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
Jasper_lee 0:b16d94660a33 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
Jasper_lee 0:b16d94660a33 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
Jasper_lee 0:b16d94660a33 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
Jasper_lee 0:b16d94660a33 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
Jasper_lee 0:b16d94660a33 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
Jasper_lee 0:b16d94660a33 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
Jasper_lee 0:b16d94660a33 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
Jasper_lee 0:b16d94660a33 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
Jasper_lee 0:b16d94660a33 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
Jasper_lee 0:b16d94660a33 1034
Jasper_lee 0:b16d94660a33 1035 #endif // __LPC17xx_H__