mbed_helloworld - change some io settings for TWR-K22F-120M

Users » Jasper_lee » Code » mbed_helloworld

change some io settings for TWR-K22F-120M

TARGET_LPC1549/LPC15xx.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:: Jasper_lee
Date:: Tue Dec 23 03:35:08 2014 +0000
Revision:: 0:b16d94660a33

change some io setting used in TWR-K22F120M

Who changed what in which revision?

User	Revision	Line number	New contents of line
Jasper_lee	0:b16d94660a33	1
Jasper_lee	0:b16d94660a33	2	/**************************************************************************************************//
Jasper_lee	0:b16d94660a33	3	* @file LPC15xx.h
Jasper_lee	0:b16d94660a33	4	*
Jasper_lee	0:b16d94660a33	5	* @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
Jasper_lee	0:b16d94660a33	6	* LPC15xx from .
Jasper_lee	0:b16d94660a33	7	*
Jasper_lee	0:b16d94660a33	8	* @version V0.3
Jasper_lee	0:b16d94660a33	9	* @date 17. July 2013
Jasper_lee	0:b16d94660a33	10	*
Jasper_lee	0:b16d94660a33	11	* @note Generated with SVDConv V2.80
Jasper_lee	0:b16d94660a33	12	* from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
Jasper_lee	0:b16d94660a33	13	*
Jasper_lee	0:b16d94660a33	14	* modified by Keil
Jasper_lee	0:b16d94660a33	15	* modified by ytsuboi
Jasper_lee	0:b16d94660a33	16	*******************************************************************************************************/
Jasper_lee	0:b16d94660a33	17
Jasper_lee	0:b16d94660a33	18
Jasper_lee	0:b16d94660a33	19
Jasper_lee	0:b16d94660a33	20	/** @addtogroup (null)
Jasper_lee	0:b16d94660a33	21	* @{
Jasper_lee	0:b16d94660a33	22	*/
Jasper_lee	0:b16d94660a33	23
Jasper_lee	0:b16d94660a33	24	/** @addtogroup LPC15xx
Jasper_lee	0:b16d94660a33	25	* @{
Jasper_lee	0:b16d94660a33	26	*/
Jasper_lee	0:b16d94660a33	27
Jasper_lee	0:b16d94660a33	28	#ifndef LPC15XX_H
Jasper_lee	0:b16d94660a33	29	#define LPC15XX_H
Jasper_lee	0:b16d94660a33	30
Jasper_lee	0:b16d94660a33	31	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	32	extern "C" {
Jasper_lee	0:b16d94660a33	33	#endif
Jasper_lee	0:b16d94660a33	34
Jasper_lee	0:b16d94660a33	35
Jasper_lee	0:b16d94660a33	36	/* ------------------------- Interrupt Number Definition ------------------------ */
Jasper_lee	0:b16d94660a33	37
Jasper_lee	0:b16d94660a33	38	typedef enum {
Jasper_lee	0:b16d94660a33	39	/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
Jasper_lee	0:b16d94660a33	40	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
Jasper_lee	0:b16d94660a33	41	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
Jasper_lee	0:b16d94660a33	42	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
Jasper_lee	0:b16d94660a33	43	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
Jasper_lee	0:b16d94660a33	44	and No Match */
Jasper_lee	0:b16d94660a33	45	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
Jasper_lee	0:b16d94660a33	46	related Fault */
Jasper_lee	0:b16d94660a33	47	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
Jasper_lee	0:b16d94660a33	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
Jasper_lee	0:b16d94660a33	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
Jasper_lee	0:b16d94660a33	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
Jasper_lee	0:b16d94660a33	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
Jasper_lee	0:b16d94660a33	52	/* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
Jasper_lee	0:b16d94660a33	53	WDT_IRQn = 0, /!< 0 WDT /
Jasper_lee	0:b16d94660a33	54	BOD_IRQn = 1, /!< 1 BOD /
Jasper_lee	0:b16d94660a33	55	FLASH_IRQn = 2, /!< 2 FLASH /
Jasper_lee	0:b16d94660a33	56	EE_IRQn = 3, /!< 3 EE /
Jasper_lee	0:b16d94660a33	57	DMA_IRQn = 4, /!< 4 DMA /
Jasper_lee	0:b16d94660a33	58	GINT0_IRQn = 5, /!< 5 GINT0 /
Jasper_lee	0:b16d94660a33	59	GINT1_IRQn = 6, /!< 6 GINT1 /
Jasper_lee	0:b16d94660a33	60	PIN_INT0_IRQn = 7, /!< 7 PIN_INT0 /
Jasper_lee	0:b16d94660a33	61	PIN_INT1_IRQn = 8, /!< 8 PIN_INT1 /
Jasper_lee	0:b16d94660a33	62	PIN_INT2_IRQn = 9, /!< 9 PIN_INT2 /
Jasper_lee	0:b16d94660a33	63	PIN_INT3_IRQn = 10, /!< 10 PIN_INT3 /
Jasper_lee	0:b16d94660a33	64	PIN_INT4_IRQn = 11, /!< 11 PIN_INT4 /
Jasper_lee	0:b16d94660a33	65	PIN_INT5_IRQn = 12, /!< 12 PIN_INT5 /
Jasper_lee	0:b16d94660a33	66	PIN_INT6_IRQn = 13, /!< 13 PIN_INT6 /
Jasper_lee	0:b16d94660a33	67	PIN_INT7_IRQn = 14, /!< 14 PIN_INT7 /
Jasper_lee	0:b16d94660a33	68	RIT_IRQn = 15, /!< 15 RIT /
Jasper_lee	0:b16d94660a33	69	SCT0_IRQn = 16, /!< 16 SCT0 /
Jasper_lee	0:b16d94660a33	70	SCT1_IRQn = 17, /!< 17 SCT1 /
Jasper_lee	0:b16d94660a33	71	SCT2_IRQn = 18, /!< 18 SCT2 /
Jasper_lee	0:b16d94660a33	72	SCT3_IRQn = 19, /!< 19 SCT3 /
Jasper_lee	0:b16d94660a33	73	MRT_IRQn = 20, /!< 20 MRT /
Jasper_lee	0:b16d94660a33	74	UART0_IRQn = 21, /!< 21 UART0 /
Jasper_lee	0:b16d94660a33	75	UART1_IRQn = 22, /!< 22 UART1 /
Jasper_lee	0:b16d94660a33	76	UART2_IRQn = 23, /!< 23 UART2 /
Jasper_lee	0:b16d94660a33	77	I2C0_IRQn = 24, /!< 24 I2C0 /
Jasper_lee	0:b16d94660a33	78	SPI0_IRQn = 25, /!< 25 SPI0 /
Jasper_lee	0:b16d94660a33	79	SPI1_IRQn = 26, /!< 26 SPI1 /
Jasper_lee	0:b16d94660a33	80	C_CAN0_IRQn = 27, /!< 27 C_CAN0 /
Jasper_lee	0:b16d94660a33	81	USB_IRQ_IRQn = 28, /!< 28 USB_IRQ /
Jasper_lee	0:b16d94660a33	82	USB_FIQ_IRQn = 29, /!< 29 USB_FIQ /
Jasper_lee	0:b16d94660a33	83	USBWAKEUP_IRQn = 30, /!< 30 USBWAKEUP /
Jasper_lee	0:b16d94660a33	84	ADC0_SEQA_IRQn = 31, /!< 31 ADC0_SEQA /
Jasper_lee	0:b16d94660a33	85	ADC0_SEQB_IRQn = 32, /!< 32 ADC0_SEQB /
Jasper_lee	0:b16d94660a33	86	ADC0_THCMP_IRQn = 33, /!< 33 ADC0_THCMP /
Jasper_lee	0:b16d94660a33	87	ADC0_OVR_IRQn = 34, /!< 34 ADC0_OVR /
Jasper_lee	0:b16d94660a33	88	ADC1_SEQA_IRQn = 35, /!< 35 ADC1_SEQA /
Jasper_lee	0:b16d94660a33	89	ADC1_SEQB_IRQn = 36, /!< 36 ADC1_SEQB /
Jasper_lee	0:b16d94660a33	90	ADC1_THCMP_IRQn = 37, /!< 37 ADC1_THCMP /
Jasper_lee	0:b16d94660a33	91	ADC1_OVR_IRQn = 38, /!< 38 ADC1_OVR /
Jasper_lee	0:b16d94660a33	92	DAC_IRQn = 39, /!< 39 DAC /
Jasper_lee	0:b16d94660a33	93	CMP0_IRQn = 40, /!< 40 CMP0 /
Jasper_lee	0:b16d94660a33	94	CMP1_IRQn = 41, /!< 41 CMP1 /
Jasper_lee	0:b16d94660a33	95	CMP2_IRQn = 42, /!< 42 CMP2 /
Jasper_lee	0:b16d94660a33	96	CMP3_IRQn = 43, /!< 43 CMP3 /
Jasper_lee	0:b16d94660a33	97	QEI_IRQn = 44, /!< 44 QEI /
Jasper_lee	0:b16d94660a33	98	RTC_ALARM_IRQn = 45, /!< 45 RTC_ALARM /
Jasper_lee	0:b16d94660a33	99	RTC_WAKE_IRQn = 46 /!< 46 RTC_WAKE /
Jasper_lee	0:b16d94660a33	100	} IRQn_Type;
Jasper_lee	0:b16d94660a33	101
Jasper_lee	0:b16d94660a33	102
Jasper_lee	0:b16d94660a33	103	/** @addtogroup Configuration_of_CMSIS
Jasper_lee	0:b16d94660a33	104	* @{
Jasper_lee	0:b16d94660a33	105	*/
Jasper_lee	0:b16d94660a33	106
Jasper_lee	0:b16d94660a33	107
Jasper_lee	0:b16d94660a33	108	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	109	/* ================ Processor and Core Peripheral Section ================ */
Jasper_lee	0:b16d94660a33	110	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	111
Jasper_lee	0:b16d94660a33	112	/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
Jasper_lee	0:b16d94660a33	113	#define __CM3_REV 0x0201 /!< Cortex-M3 Core Revision /
Jasper_lee	0:b16d94660a33	114	#define __MPU_PRESENT 0 /!< MPU present or not /
Jasper_lee	0:b16d94660a33	115	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
Jasper_lee	0:b16d94660a33	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Jasper_lee	0:b16d94660a33	117	/** @} / / End of group Configuration_of_CMSIS */
Jasper_lee	0:b16d94660a33	118
Jasper_lee	0:b16d94660a33	119	#include "core_cm3.h" /!< Cortex-M3 processor and core peripherals /
Jasper_lee	0:b16d94660a33	120	#include "system_LPC15xx.h" /!< LPC15xx System /
Jasper_lee	0:b16d94660a33	121
Jasper_lee	0:b16d94660a33	122
Jasper_lee	0:b16d94660a33	123	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	124	/* ================ Device Specific Peripheral Section ================ */
Jasper_lee	0:b16d94660a33	125	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	126
Jasper_lee	0:b16d94660a33	127
Jasper_lee	0:b16d94660a33	128	/** @addtogroup Device_Peripheral_Registers
Jasper_lee	0:b16d94660a33	129	* @{
Jasper_lee	0:b16d94660a33	130	*/
Jasper_lee	0:b16d94660a33	131
Jasper_lee	0:b16d94660a33	132
Jasper_lee	0:b16d94660a33	133	/* ------------------- Start of section using anonymous unions ------------------ */
Jasper_lee	0:b16d94660a33	134	#if defined(__CC_ARM)
Jasper_lee	0:b16d94660a33	135	#pragma push
Jasper_lee	0:b16d94660a33	136	#pragma anon_unions
Jasper_lee	0:b16d94660a33	137	#elif defined(__ICCARM__)
Jasper_lee	0:b16d94660a33	138	#pragma language=extended
Jasper_lee	0:b16d94660a33	139	#elif defined(__GNUC__)
Jasper_lee	0:b16d94660a33	140	/* anonymous unions are enabled by default */
Jasper_lee	0:b16d94660a33	141	#elif defined(__TMS470__)
Jasper_lee	0:b16d94660a33	142	/* anonymous unions are enabled by default */
Jasper_lee	0:b16d94660a33	143	#elif defined(__TASKING__)
Jasper_lee	0:b16d94660a33	144	#pragma warning 586
Jasper_lee	0:b16d94660a33	145	#else
Jasper_lee	0:b16d94660a33	146	#warning Not supported compiler type
Jasper_lee	0:b16d94660a33	147	#endif
Jasper_lee	0:b16d94660a33	148
Jasper_lee	0:b16d94660a33	149
Jasper_lee	0:b16d94660a33	150
Jasper_lee	0:b16d94660a33	151	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	152	/* ================ GPIO_PORT ================ */
Jasper_lee	0:b16d94660a33	153	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	154
Jasper_lee	0:b16d94660a33	155
Jasper_lee	0:b16d94660a33	156	/**
Jasper_lee	0:b16d94660a33	157	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
Jasper_lee	0:b16d94660a33	158	*/
Jasper_lee	0:b16d94660a33	159
Jasper_lee	0:b16d94660a33	160	typedef struct { /!< GPIO_PORT Structure /
Jasper_lee	0:b16d94660a33	161	__IO uint8_t B[76]; /!< Byte pin registers /
Jasper_lee	0:b16d94660a33	162	__I uint32_t RESERVED0[45];
Jasper_lee	0:b16d94660a33	163	__IO uint32_t W[76]; /!< Word pin registers /
Jasper_lee	0:b16d94660a33	164	__I uint32_t RESERVED1[1908];
Jasper_lee	0:b16d94660a33	165	__IO uint32_t DIR[3]; /!< Port Direction registers /
Jasper_lee	0:b16d94660a33	166	__I uint32_t RESERVED2[29];
Jasper_lee	0:b16d94660a33	167	__IO uint32_t MASK[3]; /!< Port Mask register /
Jasper_lee	0:b16d94660a33	168	__I uint32_t RESERVED3[29];
Jasper_lee	0:b16d94660a33	169	__IO uint32_t PIN[3]; /!< Port pin register /
Jasper_lee	0:b16d94660a33	170	__I uint32_t RESERVED4[29];
Jasper_lee	0:b16d94660a33	171	__IO uint32_t MPIN[3]; /!< Masked port register /
Jasper_lee	0:b16d94660a33	172	__I uint32_t RESERVED5[29];
Jasper_lee	0:b16d94660a33	173	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
Jasper_lee	0:b16d94660a33	174	__I uint32_t RESERVED6[29];
Jasper_lee	0:b16d94660a33	175	__O uint32_t CLR[3]; /!< Clear port /
Jasper_lee	0:b16d94660a33	176	__I uint32_t RESERVED7[29];
Jasper_lee	0:b16d94660a33	177	__O uint32_t NOT[3]; /!< Toggle port /
Jasper_lee	0:b16d94660a33	178	} LPC_GPIO_PORT_Type;
Jasper_lee	0:b16d94660a33	179
Jasper_lee	0:b16d94660a33	180
Jasper_lee	0:b16d94660a33	181	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	182	/* ================ DMA ================ */
Jasper_lee	0:b16d94660a33	183	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	184
Jasper_lee	0:b16d94660a33	185
Jasper_lee	0:b16d94660a33	186	/**
Jasper_lee	0:b16d94660a33	187	* @brief DMA controller (DMA)
Jasper_lee	0:b16d94660a33	188	*/
Jasper_lee	0:b16d94660a33	189
Jasper_lee	0:b16d94660a33	190	typedef struct { /!< DMA Structure /
Jasper_lee	0:b16d94660a33	191	__IO uint32_t CTRL; /!< DMA control. /
Jasper_lee	0:b16d94660a33	192	__I uint32_t INTSTAT; /!< Interrupt status. /
Jasper_lee	0:b16d94660a33	193	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
Jasper_lee	0:b16d94660a33	194	__I uint32_t RESERVED0[5];
Jasper_lee	0:b16d94660a33	195	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
Jasper_lee	0:b16d94660a33	196	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	197	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
Jasper_lee	0:b16d94660a33	198	__I uint32_t RESERVED2;
Jasper_lee	0:b16d94660a33	199	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
Jasper_lee	0:b16d94660a33	200	__I uint32_t RESERVED3;
Jasper_lee	0:b16d94660a33	201	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
Jasper_lee	0:b16d94660a33	202	__I uint32_t RESERVED4;
Jasper_lee	0:b16d94660a33	203	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
Jasper_lee	0:b16d94660a33	204	__I uint32_t RESERVED5;
Jasper_lee	0:b16d94660a33	205	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
Jasper_lee	0:b16d94660a33	206	__I uint32_t RESERVED6;
Jasper_lee	0:b16d94660a33	207	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
Jasper_lee	0:b16d94660a33	208	__I uint32_t RESERVED7;
Jasper_lee	0:b16d94660a33	209	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
Jasper_lee	0:b16d94660a33	210	__I uint32_t RESERVED8;
Jasper_lee	0:b16d94660a33	211	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
Jasper_lee	0:b16d94660a33	212	__I uint32_t RESERVED9;
Jasper_lee	0:b16d94660a33	213	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
Jasper_lee	0:b16d94660a33	214	__I uint32_t RESERVED10;
Jasper_lee	0:b16d94660a33	215	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
Jasper_lee	0:b16d94660a33	216	__I uint32_t RESERVED11;
Jasper_lee	0:b16d94660a33	217	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
Jasper_lee	0:b16d94660a33	218	__I uint32_t RESERVED12[225];
Jasper_lee	0:b16d94660a33	219	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	220	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	221	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	222	__I uint32_t RESERVED13;
Jasper_lee	0:b16d94660a33	223	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	224	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	225	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	226	__I uint32_t RESERVED14;
Jasper_lee	0:b16d94660a33	227	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	228	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	229	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	230	__I uint32_t RESERVED15;
Jasper_lee	0:b16d94660a33	231	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	232	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	233	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	234	__I uint32_t RESERVED16;
Jasper_lee	0:b16d94660a33	235	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	236	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	237	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	238	__I uint32_t RESERVED17;
Jasper_lee	0:b16d94660a33	239	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	240	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	241	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	242	__I uint32_t RESERVED18;
Jasper_lee	0:b16d94660a33	243	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	244	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	245	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	246	__I uint32_t RESERVED19;
Jasper_lee	0:b16d94660a33	247	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	248	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	249	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	250	__I uint32_t RESERVED20;
Jasper_lee	0:b16d94660a33	251	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	252	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	253	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	254	__I uint32_t RESERVED21;
Jasper_lee	0:b16d94660a33	255	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	256	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	257	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	258	__I uint32_t RESERVED22;
Jasper_lee	0:b16d94660a33	259	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	260	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	261	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	262	__I uint32_t RESERVED23;
Jasper_lee	0:b16d94660a33	263	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	264	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	265	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	266	__I uint32_t RESERVED24;
Jasper_lee	0:b16d94660a33	267	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	268	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	269	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	270	__I uint32_t RESERVED25;
Jasper_lee	0:b16d94660a33	271	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	272	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	273	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	274	__I uint32_t RESERVED26;
Jasper_lee	0:b16d94660a33	275	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	276	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	277	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	278	__I uint32_t RESERVED27;
Jasper_lee	0:b16d94660a33	279	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	280	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	281	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	282	__I uint32_t RESERVED28;
Jasper_lee	0:b16d94660a33	283	__IO uint32_t CFG16; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	284	__I uint32_t CTLSTAT16; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	285	__IO uint32_t XFERCFG16; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	286	__I uint32_t RESERVED29;
Jasper_lee	0:b16d94660a33	287	__IO uint32_t CFG17; /!< Configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	288	__I uint32_t CTLSTAT17; /!< Control and status register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	289	__IO uint32_t XFERCFG17; /!< Transfer configuration register for DMA channel 0. /
Jasper_lee	0:b16d94660a33	290	} LPC_DMA_Type;
Jasper_lee	0:b16d94660a33	291
Jasper_lee	0:b16d94660a33	292
Jasper_lee	0:b16d94660a33	293	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	294	/* ================ USB ================ */
Jasper_lee	0:b16d94660a33	295	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	296
Jasper_lee	0:b16d94660a33	297
Jasper_lee	0:b16d94660a33	298	/**
Jasper_lee	0:b16d94660a33	299	* @brief USB device controller (USB)
Jasper_lee	0:b16d94660a33	300	*/
Jasper_lee	0:b16d94660a33	301
Jasper_lee	0:b16d94660a33	302	typedef struct { /!< USB Structure /
Jasper_lee	0:b16d94660a33	303	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
Jasper_lee	0:b16d94660a33	304	__IO uint32_t INFO; /!< USB Info register /
Jasper_lee	0:b16d94660a33	305	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
Jasper_lee	0:b16d94660a33	306	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
Jasper_lee	0:b16d94660a33	307	__IO uint32_t LPM; /!< Link Power Management register /
Jasper_lee	0:b16d94660a33	308	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
Jasper_lee	0:b16d94660a33	309	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
Jasper_lee	0:b16d94660a33	310	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
Jasper_lee	0:b16d94660a33	311	__IO uint32_t INTSTAT; /!< USB interrupt status register /
Jasper_lee	0:b16d94660a33	312	__IO uint32_t INTEN; /!< USB interrupt enable register /
Jasper_lee	0:b16d94660a33	313	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
Jasper_lee	0:b16d94660a33	314	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
Jasper_lee	0:b16d94660a33	315	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	316	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
Jasper_lee	0:b16d94660a33	317	} LPC_USB_Type;
Jasper_lee	0:b16d94660a33	318
Jasper_lee	0:b16d94660a33	319
Jasper_lee	0:b16d94660a33	320	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	321	/* ================ CRC ================ */
Jasper_lee	0:b16d94660a33	322	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	323
Jasper_lee	0:b16d94660a33	324
Jasper_lee	0:b16d94660a33	325	/**
Jasper_lee	0:b16d94660a33	326	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
Jasper_lee	0:b16d94660a33	327	*/
Jasper_lee	0:b16d94660a33	328
Jasper_lee	0:b16d94660a33	329	typedef struct { /!< CRC Structure /
Jasper_lee	0:b16d94660a33	330	__IO uint32_t MODE; /!< CRC mode register /
Jasper_lee	0:b16d94660a33	331	__IO uint32_t SEED; /!< CRC seed register /
Jasper_lee	0:b16d94660a33	332
Jasper_lee	0:b16d94660a33	333	union {
Jasper_lee	0:b16d94660a33	334	__O uint32_t WR_DATA; /!< CRC data register /
Jasper_lee	0:b16d94660a33	335	__I uint32_t SUM; /!< CRC checksum register /
Jasper_lee	0:b16d94660a33	336	};
Jasper_lee	0:b16d94660a33	337	} LPC_CRC_Type;
Jasper_lee	0:b16d94660a33	338
Jasper_lee	0:b16d94660a33	339
Jasper_lee	0:b16d94660a33	340	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	341	/* ================ SCT0 ================ */
Jasper_lee	0:b16d94660a33	342	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	343
Jasper_lee	0:b16d94660a33	344
Jasper_lee	0:b16d94660a33	345	/**
Jasper_lee	0:b16d94660a33	346	* @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
Jasper_lee	0:b16d94660a33	347	*/
Jasper_lee	0:b16d94660a33	348
Jasper_lee	0:b16d94660a33	349	typedef struct { /!< SCT0 Structure /
Jasper_lee	0:b16d94660a33	350	__IO uint32_t CONFIG; /!< SCT configuration register /
Jasper_lee	0:b16d94660a33	351	__IO uint32_t CTRL; /!< SCT control register /
Jasper_lee	0:b16d94660a33	352	__IO uint32_t LIMIT; /!< SCT limit register /
Jasper_lee	0:b16d94660a33	353	__IO uint32_t HALT; /!< SCT halt condition register /
Jasper_lee	0:b16d94660a33	354	__IO uint32_t STOP; /!< SCT stop condition register /
Jasper_lee	0:b16d94660a33	355	__IO uint32_t START; /!< SCT start condition register /
Jasper_lee	0:b16d94660a33	356	__IO uint32_t DITHER; /!< SCT dither condition register /
Jasper_lee	0:b16d94660a33	357	__I uint32_t RESERVED0[9];
Jasper_lee	0:b16d94660a33	358	__IO uint32_t COUNT; /!< SCT counter register /
Jasper_lee	0:b16d94660a33	359	__IO uint32_t STATE; /!< SCT state register /
Jasper_lee	0:b16d94660a33	360	__I uint32_t INPUT; /!< SCT input register /
Jasper_lee	0:b16d94660a33	361	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
Jasper_lee	0:b16d94660a33	362	__IO uint32_t OUTPUT; /!< SCT output register /
Jasper_lee	0:b16d94660a33	363	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
Jasper_lee	0:b16d94660a33	364	__IO uint32_t RES; /!< SCT conflict resolution register /
Jasper_lee	0:b16d94660a33	365	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
Jasper_lee	0:b16d94660a33	366	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
Jasper_lee	0:b16d94660a33	367	__I uint32_t RESERVED1[35];
Jasper_lee	0:b16d94660a33	368	__IO uint32_t EVEN; /!< SCT event enable register /
Jasper_lee	0:b16d94660a33	369	__IO uint32_t EVFLAG; /!< SCT event flag register /
Jasper_lee	0:b16d94660a33	370	__IO uint32_t CONEN; /!< SCT conflict enable register /
Jasper_lee	0:b16d94660a33	371	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
Jasper_lee	0:b16d94660a33	372
Jasper_lee	0:b16d94660a33	373	union {
Jasper_lee	0:b16d94660a33	374	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	375	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	376	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	377	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	378	};
Jasper_lee	0:b16d94660a33	379
Jasper_lee	0:b16d94660a33	380	union {
Jasper_lee	0:b16d94660a33	381	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	382	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	383	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	384	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	385	};
Jasper_lee	0:b16d94660a33	386
Jasper_lee	0:b16d94660a33	387	union {
Jasper_lee	0:b16d94660a33	388	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	389	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	390	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	391	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	392	};
Jasper_lee	0:b16d94660a33	393
Jasper_lee	0:b16d94660a33	394	union {
Jasper_lee	0:b16d94660a33	395	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	396	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	397	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	398	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	399	};
Jasper_lee	0:b16d94660a33	400
Jasper_lee	0:b16d94660a33	401	union {
Jasper_lee	0:b16d94660a33	402	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	403	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	404	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	405	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	406	};
Jasper_lee	0:b16d94660a33	407
Jasper_lee	0:b16d94660a33	408	union {
Jasper_lee	0:b16d94660a33	409	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	410	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	411	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	412	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	413	};
Jasper_lee	0:b16d94660a33	414
Jasper_lee	0:b16d94660a33	415	union {
Jasper_lee	0:b16d94660a33	416	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	417	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	418	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	419	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	420	};
Jasper_lee	0:b16d94660a33	421
Jasper_lee	0:b16d94660a33	422	union {
Jasper_lee	0:b16d94660a33	423	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	424	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	425	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	426	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	427	};
Jasper_lee	0:b16d94660a33	428
Jasper_lee	0:b16d94660a33	429	union {
Jasper_lee	0:b16d94660a33	430	__I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	431	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	432	__IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	433	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	434	};
Jasper_lee	0:b16d94660a33	435
Jasper_lee	0:b16d94660a33	436	union {
Jasper_lee	0:b16d94660a33	437	__IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	438	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	439	__I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	440	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	441	};
Jasper_lee	0:b16d94660a33	442
Jasper_lee	0:b16d94660a33	443	union {
Jasper_lee	0:b16d94660a33	444	__IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	445	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	446	__I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	447	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	448	};
Jasper_lee	0:b16d94660a33	449
Jasper_lee	0:b16d94660a33	450	union {
Jasper_lee	0:b16d94660a33	451	__IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	452	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	453	__I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	454	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	455	};
Jasper_lee	0:b16d94660a33	456
Jasper_lee	0:b16d94660a33	457	union {
Jasper_lee	0:b16d94660a33	458	__IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	459	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	460	__I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	461	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	462	};
Jasper_lee	0:b16d94660a33	463
Jasper_lee	0:b16d94660a33	464	union {
Jasper_lee	0:b16d94660a33	465	__IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	466	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	467	__I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	468	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	469	};
Jasper_lee	0:b16d94660a33	470
Jasper_lee	0:b16d94660a33	471	union {
Jasper_lee	0:b16d94660a33	472	__I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	473	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	474	__IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	475	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	476	};
Jasper_lee	0:b16d94660a33	477
Jasper_lee	0:b16d94660a33	478	union {
Jasper_lee	0:b16d94660a33	479	__IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
Jasper_lee	0:b16d94660a33	480	to REGMODE15 = 0 */
Jasper_lee	0:b16d94660a33	481	__I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
Jasper_lee	0:b16d94660a33	482	REGMODE15 = 1 */
Jasper_lee	0:b16d94660a33	483	};
Jasper_lee	0:b16d94660a33	484	__IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	485	0 to 5. */
Jasper_lee	0:b16d94660a33	486	__IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	487	0 to 5. */
Jasper_lee	0:b16d94660a33	488	__IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	489	0 to 5. */
Jasper_lee	0:b16d94660a33	490	__IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	491	0 to 5. */
Jasper_lee	0:b16d94660a33	492	__IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	493	0 to 5. */
Jasper_lee	0:b16d94660a33	494	__IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
Jasper_lee	0:b16d94660a33	495	0 to 5. */
Jasper_lee	0:b16d94660a33	496	__I uint32_t RESERVED2[42];
Jasper_lee	0:b16d94660a33	497
Jasper_lee	0:b16d94660a33	498	union {
Jasper_lee	0:b16d94660a33	499	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	500	= 1 */
Jasper_lee	0:b16d94660a33	501	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	502	= 0 */
Jasper_lee	0:b16d94660a33	503	};
Jasper_lee	0:b16d94660a33	504
Jasper_lee	0:b16d94660a33	505	union {
Jasper_lee	0:b16d94660a33	506	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	507	= 0 */
Jasper_lee	0:b16d94660a33	508	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	509	= 1 */
Jasper_lee	0:b16d94660a33	510	};
Jasper_lee	0:b16d94660a33	511
Jasper_lee	0:b16d94660a33	512	union {
Jasper_lee	0:b16d94660a33	513	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	514	= 0 */
Jasper_lee	0:b16d94660a33	515	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	516	= 1 */
Jasper_lee	0:b16d94660a33	517	};
Jasper_lee	0:b16d94660a33	518
Jasper_lee	0:b16d94660a33	519	union {
Jasper_lee	0:b16d94660a33	520	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	521	= 1 */
Jasper_lee	0:b16d94660a33	522	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	523	= 0 */
Jasper_lee	0:b16d94660a33	524	};
Jasper_lee	0:b16d94660a33	525
Jasper_lee	0:b16d94660a33	526	union {
Jasper_lee	0:b16d94660a33	527	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	528	= 1 */
Jasper_lee	0:b16d94660a33	529	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	530	= 0 */
Jasper_lee	0:b16d94660a33	531	};
Jasper_lee	0:b16d94660a33	532
Jasper_lee	0:b16d94660a33	533	union {
Jasper_lee	0:b16d94660a33	534	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	535	= 1 */
Jasper_lee	0:b16d94660a33	536	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	537	= 0 */
Jasper_lee	0:b16d94660a33	538	};
Jasper_lee	0:b16d94660a33	539
Jasper_lee	0:b16d94660a33	540	union {
Jasper_lee	0:b16d94660a33	541	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	542	= 0 */
Jasper_lee	0:b16d94660a33	543	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	544	= 1 */
Jasper_lee	0:b16d94660a33	545	};
Jasper_lee	0:b16d94660a33	546
Jasper_lee	0:b16d94660a33	547	union {
Jasper_lee	0:b16d94660a33	548	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	549	= 0 */
Jasper_lee	0:b16d94660a33	550	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	551	= 1 */
Jasper_lee	0:b16d94660a33	552	};
Jasper_lee	0:b16d94660a33	553
Jasper_lee	0:b16d94660a33	554	union {
Jasper_lee	0:b16d94660a33	555	__IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	556	= 1 */
Jasper_lee	0:b16d94660a33	557	__IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	558	= 0 */
Jasper_lee	0:b16d94660a33	559	};
Jasper_lee	0:b16d94660a33	560
Jasper_lee	0:b16d94660a33	561	union {
Jasper_lee	0:b16d94660a33	562	__IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	563	= 1 */
Jasper_lee	0:b16d94660a33	564	__IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	565	= 0 */
Jasper_lee	0:b16d94660a33	566	};
Jasper_lee	0:b16d94660a33	567
Jasper_lee	0:b16d94660a33	568	union {
Jasper_lee	0:b16d94660a33	569	__IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	570	= 1 */
Jasper_lee	0:b16d94660a33	571	__IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	572	= 0 */
Jasper_lee	0:b16d94660a33	573	};
Jasper_lee	0:b16d94660a33	574
Jasper_lee	0:b16d94660a33	575	union {
Jasper_lee	0:b16d94660a33	576	__IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	577	= 1 */
Jasper_lee	0:b16d94660a33	578	__IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	579	= 0 */
Jasper_lee	0:b16d94660a33	580	};
Jasper_lee	0:b16d94660a33	581
Jasper_lee	0:b16d94660a33	582	union {
Jasper_lee	0:b16d94660a33	583	__IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	584	= 0 */
Jasper_lee	0:b16d94660a33	585	__IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	586	= 1 */
Jasper_lee	0:b16d94660a33	587	};
Jasper_lee	0:b16d94660a33	588
Jasper_lee	0:b16d94660a33	589	union {
Jasper_lee	0:b16d94660a33	590	__IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	591	= 0 */
Jasper_lee	0:b16d94660a33	592	__IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	593	= 1 */
Jasper_lee	0:b16d94660a33	594	};
Jasper_lee	0:b16d94660a33	595
Jasper_lee	0:b16d94660a33	596	union {
Jasper_lee	0:b16d94660a33	597	__IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	598	= 1 */
Jasper_lee	0:b16d94660a33	599	__IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	600	= 0 */
Jasper_lee	0:b16d94660a33	601	};
Jasper_lee	0:b16d94660a33	602
Jasper_lee	0:b16d94660a33	603	union {
Jasper_lee	0:b16d94660a33	604	__IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
Jasper_lee	0:b16d94660a33	605	= 1 */
Jasper_lee	0:b16d94660a33	606	__IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
Jasper_lee	0:b16d94660a33	607	= 0 */
Jasper_lee	0:b16d94660a33	608	};
Jasper_lee	0:b16d94660a33	609	__IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	610	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	611	__IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	612	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	613	__IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	614	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	615	__IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	616	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	617	__IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	618	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	619	__IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
Jasper_lee	0:b16d94660a33	620	registers 0 to 5. */
Jasper_lee	0:b16d94660a33	621	__I uint32_t RESERVED3[42];
Jasper_lee	0:b16d94660a33	622	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	623	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	624	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	625	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	626	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	627	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	628	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	629	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	630	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	631	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	632	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	633	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	634	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	635	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	636	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	637	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	638	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	639	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	640	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	641	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	642	__IO uint32_t EV10_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	643	__IO uint32_t EV10_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	644	__IO uint32_t EV11_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	645	__IO uint32_t EV11_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	646	__IO uint32_t EV12_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	647	__IO uint32_t EV12_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	648	__IO uint32_t EV13_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	649	__IO uint32_t EV13_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	650	__IO uint32_t EV14_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	651	__IO uint32_t EV14_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	652	__IO uint32_t EV15_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	653	__IO uint32_t EV15_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	654	__I uint32_t RESERVED4[96];
Jasper_lee	0:b16d94660a33	655	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	656	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	657	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	658	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	659	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	660	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	661	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	662	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	663	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	664	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	665	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	666	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	667	__IO uint32_t OUT6_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	668	__IO uint32_t OUT6_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	669	__IO uint32_t OUT7_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	670	__IO uint32_t OUT7_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	671	__IO uint32_t OUT8_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	672	__IO uint32_t OUT8_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	673	__IO uint32_t OUT9_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	674	__IO uint32_t OUT9_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	675	} LPC_SCT0_Type;
Jasper_lee	0:b16d94660a33	676
Jasper_lee	0:b16d94660a33	677
Jasper_lee	0:b16d94660a33	678	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	679	/* ================ SCT2 ================ */
Jasper_lee	0:b16d94660a33	680	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	681
Jasper_lee	0:b16d94660a33	682
Jasper_lee	0:b16d94660a33	683	/**
Jasper_lee	0:b16d94660a33	684	* @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
Jasper_lee	0:b16d94660a33	685	*/
Jasper_lee	0:b16d94660a33	686
Jasper_lee	0:b16d94660a33	687	typedef struct { /!< SCT2 Structure /
Jasper_lee	0:b16d94660a33	688	__IO uint32_t CONFIG; /!< SCT configuration register /
Jasper_lee	0:b16d94660a33	689	__IO uint32_t CTRL; /!< SCT control register /
Jasper_lee	0:b16d94660a33	690	__IO uint32_t LIMIT; /!< SCT limit register /
Jasper_lee	0:b16d94660a33	691	__IO uint32_t HALT; /!< SCT halt condition register /
Jasper_lee	0:b16d94660a33	692	__IO uint32_t STOP; /!< SCT stop condition register /
Jasper_lee	0:b16d94660a33	693	__IO uint32_t START; /!< SCT start condition register /
Jasper_lee	0:b16d94660a33	694	__I uint32_t RESERVED0[10];
Jasper_lee	0:b16d94660a33	695	__IO uint32_t COUNT; /!< SCT counter register /
Jasper_lee	0:b16d94660a33	696	__IO uint32_t STATE; /!< SCT state register /
Jasper_lee	0:b16d94660a33	697	__I uint32_t INPUT; /!< SCT input register /
Jasper_lee	0:b16d94660a33	698	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
Jasper_lee	0:b16d94660a33	699	__IO uint32_t OUTPUT; /!< SCT output register /
Jasper_lee	0:b16d94660a33	700	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
Jasper_lee	0:b16d94660a33	701	__IO uint32_t RES; /!< SCT conflict resolution register /
Jasper_lee	0:b16d94660a33	702	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
Jasper_lee	0:b16d94660a33	703	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
Jasper_lee	0:b16d94660a33	704	__I uint32_t RESERVED1[35];
Jasper_lee	0:b16d94660a33	705	__IO uint32_t EVEN; /!< SCT event enable register /
Jasper_lee	0:b16d94660a33	706	__IO uint32_t EVFLAG; /!< SCT event flag register /
Jasper_lee	0:b16d94660a33	707	__IO uint32_t CONEN; /!< SCT conflict enable register /
Jasper_lee	0:b16d94660a33	708	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
Jasper_lee	0:b16d94660a33	709
Jasper_lee	0:b16d94660a33	710	union {
Jasper_lee	0:b16d94660a33	711	__I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	712	= 1 */
Jasper_lee	0:b16d94660a33	713	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	714	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	715	};
Jasper_lee	0:b16d94660a33	716
Jasper_lee	0:b16d94660a33	717	union {
Jasper_lee	0:b16d94660a33	718	__I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	719	= 1 */
Jasper_lee	0:b16d94660a33	720	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	721	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	722	};
Jasper_lee	0:b16d94660a33	723
Jasper_lee	0:b16d94660a33	724	union {
Jasper_lee	0:b16d94660a33	725	__I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	726	= 1 */
Jasper_lee	0:b16d94660a33	727	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	728	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	729	};
Jasper_lee	0:b16d94660a33	730
Jasper_lee	0:b16d94660a33	731	union {
Jasper_lee	0:b16d94660a33	732	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	733	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	734	__I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	735	= 1 */
Jasper_lee	0:b16d94660a33	736	};
Jasper_lee	0:b16d94660a33	737
Jasper_lee	0:b16d94660a33	738	union {
Jasper_lee	0:b16d94660a33	739	__I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	740	= 1 */
Jasper_lee	0:b16d94660a33	741	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	742	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	743	};
Jasper_lee	0:b16d94660a33	744
Jasper_lee	0:b16d94660a33	745	union {
Jasper_lee	0:b16d94660a33	746	__IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	747	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	748	__I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	749	= 1 */
Jasper_lee	0:b16d94660a33	750	};
Jasper_lee	0:b16d94660a33	751
Jasper_lee	0:b16d94660a33	752	union {
Jasper_lee	0:b16d94660a33	753	__I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	754	= 1 */
Jasper_lee	0:b16d94660a33	755	__IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	756	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	757	};
Jasper_lee	0:b16d94660a33	758
Jasper_lee	0:b16d94660a33	759	union {
Jasper_lee	0:b16d94660a33	760	__I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
Jasper_lee	0:b16d94660a33	761	= 1 */
Jasper_lee	0:b16d94660a33	762	__IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
Jasper_lee	0:b16d94660a33	763	REGMODE7 = 0 */
Jasper_lee	0:b16d94660a33	764	};
Jasper_lee	0:b16d94660a33	765	__I uint32_t RESERVED2[56];
Jasper_lee	0:b16d94660a33	766
Jasper_lee	0:b16d94660a33	767	union {
Jasper_lee	0:b16d94660a33	768	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	769	= 1 */
Jasper_lee	0:b16d94660a33	770	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	771	= 0 */
Jasper_lee	0:b16d94660a33	772	};
Jasper_lee	0:b16d94660a33	773
Jasper_lee	0:b16d94660a33	774	union {
Jasper_lee	0:b16d94660a33	775	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	776	= 1 */
Jasper_lee	0:b16d94660a33	777	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	778	= 0 */
Jasper_lee	0:b16d94660a33	779	};
Jasper_lee	0:b16d94660a33	780
Jasper_lee	0:b16d94660a33	781	union {
Jasper_lee	0:b16d94660a33	782	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	783	= 1 */
Jasper_lee	0:b16d94660a33	784	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	785	= 0 */
Jasper_lee	0:b16d94660a33	786	};
Jasper_lee	0:b16d94660a33	787
Jasper_lee	0:b16d94660a33	788	union {
Jasper_lee	0:b16d94660a33	789	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	790	= 0 */
Jasper_lee	0:b16d94660a33	791	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	792	= 1 */
Jasper_lee	0:b16d94660a33	793	};
Jasper_lee	0:b16d94660a33	794
Jasper_lee	0:b16d94660a33	795	union {
Jasper_lee	0:b16d94660a33	796	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	797	= 1 */
Jasper_lee	0:b16d94660a33	798	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	799	= 0 */
Jasper_lee	0:b16d94660a33	800	};
Jasper_lee	0:b16d94660a33	801
Jasper_lee	0:b16d94660a33	802	union {
Jasper_lee	0:b16d94660a33	803	__IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	804	= 0 */
Jasper_lee	0:b16d94660a33	805	__IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	806	= 1 */
Jasper_lee	0:b16d94660a33	807	};
Jasper_lee	0:b16d94660a33	808
Jasper_lee	0:b16d94660a33	809	union {
Jasper_lee	0:b16d94660a33	810	__IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	811	= 1 */
Jasper_lee	0:b16d94660a33	812	__IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	813	= 0 */
Jasper_lee	0:b16d94660a33	814	};
Jasper_lee	0:b16d94660a33	815
Jasper_lee	0:b16d94660a33	816	union {
Jasper_lee	0:b16d94660a33	817	__IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
Jasper_lee	0:b16d94660a33	818	= 1 */
Jasper_lee	0:b16d94660a33	819	__IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
Jasper_lee	0:b16d94660a33	820	= 0 */
Jasper_lee	0:b16d94660a33	821	};
Jasper_lee	0:b16d94660a33	822	__I uint32_t RESERVED3[56];
Jasper_lee	0:b16d94660a33	823	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	824	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	825	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	826	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	827	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	828	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	829	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	830	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	831	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	832	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	833	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	834	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	835	__IO uint32_t EV6_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	836	__IO uint32_t EV6_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	837	__IO uint32_t EV7_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	838	__IO uint32_t EV7_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	839	__IO uint32_t EV8_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	840	__IO uint32_t EV8_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	841	__IO uint32_t EV9_STATE; /!< SCT event state register 0 /
Jasper_lee	0:b16d94660a33	842	__IO uint32_t EV9_CTRL; /!< SCT event control register 0 /
Jasper_lee	0:b16d94660a33	843	__I uint32_t RESERVED4[108];
Jasper_lee	0:b16d94660a33	844	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	845	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	846	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	847	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	848	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	849	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	850	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	851	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	852	__IO uint32_t OUT4_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	853	__IO uint32_t OUT4_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	854	__IO uint32_t OUT5_SET; /!< SCT output 0 set register /
Jasper_lee	0:b16d94660a33	855	__IO uint32_t OUT5_CLR; /!< SCT output 0 clear register /
Jasper_lee	0:b16d94660a33	856	} LPC_SCT2_Type;
Jasper_lee	0:b16d94660a33	857
Jasper_lee	0:b16d94660a33	858
Jasper_lee	0:b16d94660a33	859	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	860	/* ================ ADC0 ================ */
Jasper_lee	0:b16d94660a33	861	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	862
Jasper_lee	0:b16d94660a33	863
Jasper_lee	0:b16d94660a33	864	/**
Jasper_lee	0:b16d94660a33	865	* @brief 12-bit ADC controller ADC0/1 (ADC0)
Jasper_lee	0:b16d94660a33	866	*/
Jasper_lee	0:b16d94660a33	867
Jasper_lee	0:b16d94660a33	868	typedef struct { /!< ADC0 Structure /
Jasper_lee	0:b16d94660a33	869	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
Jasper_lee	0:b16d94660a33	870	bits for each sequence and the A/D power-down bit. */
Jasper_lee	0:b16d94660a33	871	__IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
Jasper_lee	0:b16d94660a33	872	internal source for various channels */
Jasper_lee	0:b16d94660a33	873	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
Jasper_lee	0:b16d94660a33	874	and channel selection for conversion sequence-A. Also specifies
Jasper_lee	0:b16d94660a33	875	interrupt mode for sequence-A. */
Jasper_lee	0:b16d94660a33	876	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
Jasper_lee	0:b16d94660a33	877	and channel selection for conversion sequence-B. Also specifies
Jasper_lee	0:b16d94660a33	878	interrupt mode for sequence-B. */
Jasper_lee	0:b16d94660a33	879	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
Jasper_lee	0:b16d94660a33	880	the result of the most recent A/D conversion performed under
Jasper_lee	0:b16d94660a33	881	sequence-A */
Jasper_lee	0:b16d94660a33	882	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
Jasper_lee	0:b16d94660a33	883	the result of the most recent A/D conversion performed under
Jasper_lee	0:b16d94660a33	884	sequence-B */
Jasper_lee	0:b16d94660a33	885	__I uint32_t RESERVED0[2];
Jasper_lee	0:b16d94660a33	886	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
Jasper_lee	0:b16d94660a33	887	of the most recent conversion completed on channel 0. */
Jasper_lee	0:b16d94660a33	888	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
Jasper_lee	0:b16d94660a33	889	level for automatic threshold comparison for any channels linked
Jasper_lee	0:b16d94660a33	890	to threshold pair 0. */
Jasper_lee	0:b16d94660a33	891	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
Jasper_lee	0:b16d94660a33	892	level for automatic threshold comparison for any channels linked
Jasper_lee	0:b16d94660a33	893	to threshold pair 1. */
Jasper_lee	0:b16d94660a33	894	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
Jasper_lee	0:b16d94660a33	895	level for automatic threshold comparison for any channels linked
Jasper_lee	0:b16d94660a33	896	to threshold pair 0. */
Jasper_lee	0:b16d94660a33	897	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
Jasper_lee	0:b16d94660a33	898	level for automatic threshold comparison for any channels linked
Jasper_lee	0:b16d94660a33	899	to threshold pair 1. */
Jasper_lee	0:b16d94660a33	900	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
Jasper_lee	0:b16d94660a33	901	threshold compare registers are to be used for each channel */
Jasper_lee	0:b16d94660a33	902	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
Jasper_lee	0:b16d94660a33	903	bits that enable the sequence-A, sequence-B, threshold compare
Jasper_lee	0:b16d94660a33	904	and data overrun interrupts to be generated. */
Jasper_lee	0:b16d94660a33	905	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
Jasper_lee	0:b16d94660a33	906	and the individual component overrun and threshold-compare flags.
Jasper_lee	0:b16d94660a33	907	(The overrun bits replicate information stored in the result
Jasper_lee	0:b16d94660a33	908	registers). */
Jasper_lee	0:b16d94660a33	909	__IO uint32_t TRM; /!< ADC trim register. /
Jasper_lee	0:b16d94660a33	910	} LPC_ADC0_Type;
Jasper_lee	0:b16d94660a33	911
Jasper_lee	0:b16d94660a33	912
Jasper_lee	0:b16d94660a33	913	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	914	/* ================ DAC ================ */
Jasper_lee	0:b16d94660a33	915	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	916
Jasper_lee	0:b16d94660a33	917
Jasper_lee	0:b16d94660a33	918	/**
Jasper_lee	0:b16d94660a33	919	* @brief 12-bit DAC Modification (DAC)
Jasper_lee	0:b16d94660a33	920	*/
Jasper_lee	0:b16d94660a33	921
Jasper_lee	0:b16d94660a33	922	typedef struct { /!< DAC Structure /
Jasper_lee	0:b16d94660a33	923	__IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
Jasper_lee	0:b16d94660a33	924	value to be converted to analog. */
Jasper_lee	0:b16d94660a33	925	__IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
Jasper_lee	0:b16d94660a33	926	DAC operation and the interrupt/dma request flag. */
Jasper_lee	0:b16d94660a33	927	__IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
Jasper_lee	0:b16d94660a33	928	value for the internal DAC DMA/Interrupt timer. */
Jasper_lee	0:b16d94660a33	929	} LPC_DAC_Type;
Jasper_lee	0:b16d94660a33	930
Jasper_lee	0:b16d94660a33	931
Jasper_lee	0:b16d94660a33	932	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	933	/* ================ ACMP ================ */
Jasper_lee	0:b16d94660a33	934	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	935
Jasper_lee	0:b16d94660a33	936
Jasper_lee	0:b16d94660a33	937	/**
Jasper_lee	0:b16d94660a33	938	* @brief Analog comparators ACMP0/1/2/3 (ACMP)
Jasper_lee	0:b16d94660a33	939	*/
Jasper_lee	0:b16d94660a33	940
Jasper_lee	0:b16d94660a33	941	typedef struct { /!< ACMP Structure /
Jasper_lee	0:b16d94660a33	942	__IO uint32_t CTRL; /!< Comparator block control register /
Jasper_lee	0:b16d94660a33	943	__IO uint32_t CMP0; /!< Comparator 0 source control /
Jasper_lee	0:b16d94660a33	944	__IO uint32_t CMPFILTR0; /!< Comparator 0 pin filter set-up /
Jasper_lee	0:b16d94660a33	945	__IO uint32_t CMP1; /!< Comparator 1 source control /
Jasper_lee	0:b16d94660a33	946	__IO uint32_t CMPFILTR1; /!< Comparator 0 pin filter set-up /
Jasper_lee	0:b16d94660a33	947	__IO uint32_t CMP2; /!< Comparator 2 source control /
Jasper_lee	0:b16d94660a33	948	__IO uint32_t CMPFILTR2; /!< Comparator 0 pin filter set-up /
Jasper_lee	0:b16d94660a33	949	__IO uint32_t CMP3; /!< Comparator 3 source control /
Jasper_lee	0:b16d94660a33	950	__IO uint32_t CMPFILTR3; /!< Comparator 0 pin filter set-up /
Jasper_lee	0:b16d94660a33	951	} LPC_ACMP_Type;
Jasper_lee	0:b16d94660a33	952
Jasper_lee	0:b16d94660a33	953
Jasper_lee	0:b16d94660a33	954	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	955	/* ================ INMUX ================ */
Jasper_lee	0:b16d94660a33	956	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	957
Jasper_lee	0:b16d94660a33	958
Jasper_lee	0:b16d94660a33	959	/**
Jasper_lee	0:b16d94660a33	960	* @brief Input multiplexing (INMUX) (INMUX)
Jasper_lee	0:b16d94660a33	961	*/
Jasper_lee	0:b16d94660a33	962
Jasper_lee	0:b16d94660a33	963	typedef struct { /!< INMUX Structure /
Jasper_lee	0:b16d94660a33	964	__IO uint32_t SCT0_INMUX[7]; /!< Pinmux register for SCT0 input 0 /
Jasper_lee	0:b16d94660a33	965	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	966	__IO uint32_t SCT1_INMUX[7]; /!< Pinmux register for SCT1 input 0 /
Jasper_lee	0:b16d94660a33	967	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	968	__IO uint32_t SCT2_INMUX[3]; /!< Pinmux register for SCT2 input 0 /
Jasper_lee	0:b16d94660a33	969	__I uint32_t RESERVED2[5];
Jasper_lee	0:b16d94660a33	970	__IO uint32_t SCT3_INMUX[3]; /!< Pinmux register for SCT3 input 0 /
Jasper_lee	0:b16d94660a33	971	__I uint32_t RESERVED3[21];
Jasper_lee	0:b16d94660a33	972	__IO uint32_t PINTSEL[8]; /!< Pin interrupt select register 0 /
Jasper_lee	0:b16d94660a33	973	__IO uint32_t DMA_ITRIG_INMUX[18]; /!< Trigger input for DMA channel 0 select register. /
Jasper_lee	0:b16d94660a33	974	__I uint32_t RESERVED4[14];
Jasper_lee	0:b16d94660a33	975	__IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
Jasper_lee	0:b16d94660a33	976	clock */
Jasper_lee	0:b16d94660a33	977	__IO uint32_t FREQMEAS_TARGET; /!< Clock selection for frequency measurement function target clock /
Jasper_lee	0:b16d94660a33	978	} LPC_INMUX_Type;
Jasper_lee	0:b16d94660a33	979
Jasper_lee	0:b16d94660a33	980
Jasper_lee	0:b16d94660a33	981	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	982	/* ================ RTC ================ */
Jasper_lee	0:b16d94660a33	983	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	984
Jasper_lee	0:b16d94660a33	985
Jasper_lee	0:b16d94660a33	986	/**
Jasper_lee	0:b16d94660a33	987	* @brief Real-Time Clock (RTC) (RTC)
Jasper_lee	0:b16d94660a33	988	*/
Jasper_lee	0:b16d94660a33	989
Jasper_lee	0:b16d94660a33	990	typedef struct { /!< RTC Structure /
Jasper_lee	0:b16d94660a33	991	__IO uint32_t CTRL; /!< RTC control register /
Jasper_lee	0:b16d94660a33	992	__IO uint32_t MATCH; /!< RTC match register /
Jasper_lee	0:b16d94660a33	993	__IO uint32_t COUNT; /!< RTC counter register /
Jasper_lee	0:b16d94660a33	994	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
Jasper_lee	0:b16d94660a33	995	} LPC_RTC_Type;
Jasper_lee	0:b16d94660a33	996
Jasper_lee	0:b16d94660a33	997
Jasper_lee	0:b16d94660a33	998	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	999	/* ================ WWDT ================ */
Jasper_lee	0:b16d94660a33	1000	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1001
Jasper_lee	0:b16d94660a33	1002
Jasper_lee	0:b16d94660a33	1003	/**
Jasper_lee	0:b16d94660a33	1004	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
Jasper_lee	0:b16d94660a33	1005	*/
Jasper_lee	0:b16d94660a33	1006
Jasper_lee	0:b16d94660a33	1007	typedef struct { /!< WWDT Structure /
Jasper_lee	0:b16d94660a33	1008	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
Jasper_lee	0:b16d94660a33	1009	and status of the Watchdog Timer. */
Jasper_lee	0:b16d94660a33	1010	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
Jasper_lee	0:b16d94660a33	1011	the time-out value. */
Jasper_lee	0:b16d94660a33	1012	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
Jasper_lee	0:b16d94660a33	1013	to this register reloads the Watchdog timer with the value contained
Jasper_lee	0:b16d94660a33	1014	in WDTC. */
Jasper_lee	0:b16d94660a33	1015	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
Jasper_lee	0:b16d94660a33	1016	the current value of the Watchdog timer. */
Jasper_lee	0:b16d94660a33	1017	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1018	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
Jasper_lee	0:b16d94660a33	1019	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
Jasper_lee	0:b16d94660a33	1020	} LPC_WWDT_Type;
Jasper_lee	0:b16d94660a33	1021
Jasper_lee	0:b16d94660a33	1022
Jasper_lee	0:b16d94660a33	1023	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1024	/* ================ SWM ================ */
Jasper_lee	0:b16d94660a33	1025	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1026
Jasper_lee	0:b16d94660a33	1027
Jasper_lee	0:b16d94660a33	1028	/**
Jasper_lee	0:b16d94660a33	1029	* @brief Switch Matrix (SWM) (SWM)
Jasper_lee	0:b16d94660a33	1030	*/
Jasper_lee	0:b16d94660a33	1031
Jasper_lee	0:b16d94660a33	1032	typedef struct { /!< SWM Structure /
Jasper_lee	0:b16d94660a33	1033	union {
Jasper_lee	0:b16d94660a33	1034	__IO uint32_t PINASSIGN[16];
Jasper_lee	0:b16d94660a33	1035	struct {
Jasper_lee	0:b16d94660a33	1036	__IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
Jasper_lee	0:b16d94660a33	1037	U0_RTS, U0_CTS. */
Jasper_lee	0:b16d94660a33	1038	__IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
Jasper_lee	0:b16d94660a33	1039	U1_RXD, U1_RTS. */
Jasper_lee	0:b16d94660a33	1040	__IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
Jasper_lee	0:b16d94660a33	1041	U2_TXD, U2_RXD. */
Jasper_lee	0:b16d94660a33	1042	__IO uint32_t PINASSIGN3; /!< Pin assign register 3. Assign movable function . /
Jasper_lee	0:b16d94660a33	1043	__IO uint32_t PINASSIGN4; /!< Pin assign register 4. Assign movable functions /
Jasper_lee	0:b16d94660a33	1044	__IO uint32_t PINASSIGN5; /!< Pin assign register 5. Assign movable functions /
Jasper_lee	0:b16d94660a33	1045	__IO uint32_t PINASSIGN6; /!< Pin assign register 6. Assign movable functions /
Jasper_lee	0:b16d94660a33	1046	__IO uint32_t PINASSIGN7; /!< Pin assign register 7. Assign movable functions /
Jasper_lee	0:b16d94660a33	1047	__IO uint32_t PINASSIGN8; /!< Pin assign register 8. Assign movable functions /
Jasper_lee	0:b16d94660a33	1048	__IO uint32_t PINASSIGN9; /!< Pin assign register 9. Assign movable functions /
Jasper_lee	0:b16d94660a33	1049	__IO uint32_t PINASSIGN10; /!< Pin assign register 10. Assign movable functions /
Jasper_lee	0:b16d94660a33	1050	__IO uint32_t PINASSIGN11; /!< Pin assign register 11. Assign movable functions /
Jasper_lee	0:b16d94660a33	1051	__IO uint32_t PINASSIGN12; /!< Pin assign register 12. Assign movable functions /
Jasper_lee	0:b16d94660a33	1052	__IO uint32_t PINASSIGN13; /!< Pin assign register 13. Assign movable functions /
Jasper_lee	0:b16d94660a33	1053	__IO uint32_t PINASSIGN14; /!< Pin assign register 14. Assign movable functions /
Jasper_lee	0:b16d94660a33	1054	__IO uint32_t PINASSIGN15; /!< Pin assign register 15. Assign movable functions /
Jasper_lee	0:b16d94660a33	1055	};
Jasper_lee	0:b16d94660a33	1056	};
Jasper_lee	0:b16d94660a33	1057	__I uint32_t RESERVED0[96];
Jasper_lee	0:b16d94660a33	1058	__IO uint32_t PINENABLE0; /!< Pin enable register 0. Enables fixed-pin functions /
Jasper_lee	0:b16d94660a33	1059	__IO uint32_t PINENABLE1; /!< Pin enable register 0. Enables fixed-pin functions /
Jasper_lee	0:b16d94660a33	1060	} LPC_SWM_Type;
Jasper_lee	0:b16d94660a33	1061
Jasper_lee	0:b16d94660a33	1062
Jasper_lee	0:b16d94660a33	1063	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1064	/* ================ PMU ================ */
Jasper_lee	0:b16d94660a33	1065	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1066
Jasper_lee	0:b16d94660a33	1067
Jasper_lee	0:b16d94660a33	1068	/**
Jasper_lee	0:b16d94660a33	1069	* @brief Power Management Unit (PMU) (PMU)
Jasper_lee	0:b16d94660a33	1070	*/
Jasper_lee	0:b16d94660a33	1071
Jasper_lee	0:b16d94660a33	1072	typedef struct { /!< PMU Structure /
Jasper_lee	0:b16d94660a33	1073	__IO uint32_t PCON; /!< Power control register /
Jasper_lee	0:b16d94660a33	1074	__IO uint32_t GPREG0; /!< General purpose register 0 /
Jasper_lee	0:b16d94660a33	1075	__IO uint32_t GPREG1; /!< General purpose register 0 /
Jasper_lee	0:b16d94660a33	1076	__IO uint32_t GPREG2; /!< General purpose register 0 /
Jasper_lee	0:b16d94660a33	1077	__IO uint32_t GPREG3; /!< General purpose register 0 /
Jasper_lee	0:b16d94660a33	1078	__IO uint32_t DPDCTRL; /!< Deep power-down control register /
Jasper_lee	0:b16d94660a33	1079	} LPC_PMU_Type;
Jasper_lee	0:b16d94660a33	1080
Jasper_lee	0:b16d94660a33	1081
Jasper_lee	0:b16d94660a33	1082	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1083	/* ================ USART0 ================ */
Jasper_lee	0:b16d94660a33	1084	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1085
Jasper_lee	0:b16d94660a33	1086
Jasper_lee	0:b16d94660a33	1087	/**
Jasper_lee	0:b16d94660a33	1088	* @brief USART0 (USART0)
Jasper_lee	0:b16d94660a33	1089	*/
Jasper_lee	0:b16d94660a33	1090
Jasper_lee	0:b16d94660a33	1091	typedef struct { /!< USART0 Structure /
Jasper_lee	0:b16d94660a33	1092	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
Jasper_lee	0:b16d94660a33	1093	that typically are not changed during operation. */
Jasper_lee	0:b16d94660a33	1094	__IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
Jasper_lee	0:b16d94660a33	1095	likely to change during operation. */
Jasper_lee	0:b16d94660a33	1096	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
Jasper_lee	0:b16d94660a33	1097	here. Writing ones clears some bits in the register. Some bits
Jasper_lee	0:b16d94660a33	1098	can be cleared by writing a 1 to them. */
Jasper_lee	0:b16d94660a33	1099	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
Jasper_lee	0:b16d94660a33	1100	interrupt enable bit for each potential USART interrupt. A complete
Jasper_lee	0:b16d94660a33	1101	value may be read from this register. Writing a 1 to any implemented
Jasper_lee	0:b16d94660a33	1102	bit position causes that bit to be set. */
Jasper_lee	0:b16d94660a33	1103	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
Jasper_lee	0:b16d94660a33	1104	of bits in the INTENSET register. Writing a 1 to any implemented
Jasper_lee	0:b16d94660a33	1105	bit position causes the corresponding bit to be cleared. */
Jasper_lee	0:b16d94660a33	1106	__I uint32_t RXDATA; /!< Receiver Data register. Contains the last character received. /
Jasper_lee	0:b16d94660a33	1107	__I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
Jasper_lee	0:b16d94660a33	1108	received with the current USART receive status. Allows DMA or
Jasper_lee	0:b16d94660a33	1109	software to recover incoming data and status together. */
Jasper_lee	0:b16d94660a33	1110	__IO uint32_t TXDATA; /!< Transmit Data register. Data to be transmitted is written here. /
Jasper_lee	0:b16d94660a33	1111	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
Jasper_lee	0:b16d94660a33	1112	value. */
Jasper_lee	0:b16d94660a33	1113	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
Jasper_lee	0:b16d94660a33	1114	enabled. */
Jasper_lee	0:b16d94660a33	1115	} LPC_USART0_Type;
Jasper_lee	0:b16d94660a33	1116
Jasper_lee	0:b16d94660a33	1117
Jasper_lee	0:b16d94660a33	1118	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1119	/* ================ SPI0 ================ */
Jasper_lee	0:b16d94660a33	1120	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1121
Jasper_lee	0:b16d94660a33	1122
Jasper_lee	0:b16d94660a33	1123	/**
Jasper_lee	0:b16d94660a33	1124	* @brief SPI0 (SPI0)
Jasper_lee	0:b16d94660a33	1125	*/
Jasper_lee	0:b16d94660a33	1126
Jasper_lee	0:b16d94660a33	1127	typedef struct { /!< SPI0 Structure /
Jasper_lee	0:b16d94660a33	1128	__IO uint32_t CFG; /!< SPI Configuration register /
Jasper_lee	0:b16d94660a33	1129	__IO uint32_t DLY; /!< SPI Delay register /
Jasper_lee	0:b16d94660a33	1130	__IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
Jasper_lee	0:b16d94660a33	1131	to that bit position */
Jasper_lee	0:b16d94660a33	1132	__IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
Jasper_lee	0:b16d94660a33	1133	from this register. Writing a 1 to any implemented bit position
Jasper_lee	0:b16d94660a33	1134	causes that bit to be set. */
Jasper_lee	0:b16d94660a33	1135	__O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
Jasper_lee	0:b16d94660a33	1136	position causes the corresponding bit in INTENSET to be cleared. */
Jasper_lee	0:b16d94660a33	1137	__I uint32_t RXDAT; /!< SPI Receive Data /
Jasper_lee	0:b16d94660a33	1138	__IO uint32_t TXDATCTL; /!< SPI Transmit Data with Control /
Jasper_lee	0:b16d94660a33	1139	__IO uint32_t TXDAT; /!< SPI Transmit Data with Control /
Jasper_lee	0:b16d94660a33	1140	__IO uint32_t TXCTL; /!< SPI Transmit Control /
Jasper_lee	0:b16d94660a33	1141	__IO uint32_t DIV; /!< SPI clock Divider /
Jasper_lee	0:b16d94660a33	1142	__I uint32_t INTSTAT; /!< SPI Interrupt Status /
Jasper_lee	0:b16d94660a33	1143	} LPC_SPI0_Type;
Jasper_lee	0:b16d94660a33	1144
Jasper_lee	0:b16d94660a33	1145
Jasper_lee	0:b16d94660a33	1146	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1147	/* ================ I2C0 ================ */
Jasper_lee	0:b16d94660a33	1148	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1149
Jasper_lee	0:b16d94660a33	1150
Jasper_lee	0:b16d94660a33	1151	/**
Jasper_lee	0:b16d94660a33	1152	* @brief I2C-bus interface (I2C0)
Jasper_lee	0:b16d94660a33	1153	*/
Jasper_lee	0:b16d94660a33	1154
Jasper_lee	0:b16d94660a33	1155	typedef struct { /!< I2C0 Structure /
Jasper_lee	0:b16d94660a33	1156	__IO uint32_t CFG; /!< Configuration for shared functions. /
Jasper_lee	0:b16d94660a33	1157	__IO uint32_t STAT; /!< Status register for Master, Slave, and Monitor functions. /
Jasper_lee	0:b16d94660a33	1158	__IO uint32_t INTENSET; /!< Interrupt Enable Set and read register. /
Jasper_lee	0:b16d94660a33	1159	__O uint32_t INTENCLR; /!< Interrupt Enable Clear register. /
Jasper_lee	0:b16d94660a33	1160	__IO uint32_t TIMEOUT; /!< Time-out value register. /
Jasper_lee	0:b16d94660a33	1161	__IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
Jasper_lee	0:b16d94660a33	1162	what time increments are used for the MSTTIME and SLVTIME registers. */
Jasper_lee	0:b16d94660a33	1163	__I uint32_t INTSTAT; /!< Interrupt Status register for Master, Slave, and Monitor functions. /
Jasper_lee	0:b16d94660a33	1164	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1165	__IO uint32_t MSTCTL; /!< Master control register. /
Jasper_lee	0:b16d94660a33	1166	__IO uint32_t MSTTIME; /!< Master timing configuration. /
Jasper_lee	0:b16d94660a33	1167	__IO uint32_t MSTDAT; /!< Combined Master receiver and transmitter data register. /
Jasper_lee	0:b16d94660a33	1168	__I uint32_t RESERVED1[5];
Jasper_lee	0:b16d94660a33	1169	__IO uint32_t SLVCTL; /!< Slave control register. /
Jasper_lee	0:b16d94660a33	1170	__IO uint32_t SLVDAT; /!< Combined Slave receiver and transmitter data register. /
Jasper_lee	0:b16d94660a33	1171	__IO uint32_t SLVADR0; /!< Slave address 0. /
Jasper_lee	0:b16d94660a33	1172	__IO uint32_t SLVADR1; /!< Slave address 0. /
Jasper_lee	0:b16d94660a33	1173	__IO uint32_t SLVADR2; /!< Slave address 0. /
Jasper_lee	0:b16d94660a33	1174	__IO uint32_t SLVADR3; /!< Slave address 0. /
Jasper_lee	0:b16d94660a33	1175	__IO uint32_t SLVQUAL0; /!< Slave Qualification for address 0. /
Jasper_lee	0:b16d94660a33	1176	__I uint32_t RESERVED2[9];
Jasper_lee	0:b16d94660a33	1177	__I uint32_t MONRXDAT; /!< Monitor receiver data register. /
Jasper_lee	0:b16d94660a33	1178	} LPC_I2C0_Type;
Jasper_lee	0:b16d94660a33	1179
Jasper_lee	0:b16d94660a33	1180
Jasper_lee	0:b16d94660a33	1181	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1182	/* ================ QEI ================ */
Jasper_lee	0:b16d94660a33	1183	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1184
Jasper_lee	0:b16d94660a33	1185
Jasper_lee	0:b16d94660a33	1186	/**
Jasper_lee	0:b16d94660a33	1187	* @brief Quadrature Encoder Interface (QEI) (QEI)
Jasper_lee	0:b16d94660a33	1188	*/
Jasper_lee	0:b16d94660a33	1189
Jasper_lee	0:b16d94660a33	1190	typedef struct { /!< QEI Structure /
Jasper_lee	0:b16d94660a33	1191	__O uint32_t CON; /!< Control register /
Jasper_lee	0:b16d94660a33	1192	__I uint32_t STAT; /!< Encoder status register /
Jasper_lee	0:b16d94660a33	1193	__IO uint32_t CONF; /!< Configuration register /
Jasper_lee	0:b16d94660a33	1194	__I uint32_t POS; /!< Position register /
Jasper_lee	0:b16d94660a33	1195	__IO uint32_t MAXPOS; /!< Maximum position register /
Jasper_lee	0:b16d94660a33	1196	__IO uint32_t CMPOS0; /!< position compare register 0 /
Jasper_lee	0:b16d94660a33	1197	__IO uint32_t CMPOS1; /!< position compare register 1 /
Jasper_lee	0:b16d94660a33	1198	__IO uint32_t CMPOS2; /!< position compare register 2 /
Jasper_lee	0:b16d94660a33	1199	__I uint32_t INXCNT; /!< Index count register /
Jasper_lee	0:b16d94660a33	1200	__IO uint32_t INXCMP0; /!< Index compare register 0 /
Jasper_lee	0:b16d94660a33	1201	__IO uint32_t LOAD; /!< Velocity timer reload register /
Jasper_lee	0:b16d94660a33	1202	__I uint32_t TIME; /!< Velocity timer register /
Jasper_lee	0:b16d94660a33	1203	__I uint32_t VEL; /!< Velocity counter register /
Jasper_lee	0:b16d94660a33	1204	__I uint32_t CAP; /!< Velocity capture register /
Jasper_lee	0:b16d94660a33	1205	__IO uint32_t VELCOMP; /!< Velocity compare register /
Jasper_lee	0:b16d94660a33	1206	__IO uint32_t FILTERPHA; /!< Digital filter register on input phase A (QEI_A) /
Jasper_lee	0:b16d94660a33	1207	__IO uint32_t FILTERPHB; /!< Digital filter register on input phase B (QEI_B) /
Jasper_lee	0:b16d94660a33	1208	__IO uint32_t FILTERINX; /!< Digital filter register on input index (QEI_IDX) /
Jasper_lee	0:b16d94660a33	1209	__IO uint32_t WINDOW; /!< Index acceptance window register /
Jasper_lee	0:b16d94660a33	1210	__IO uint32_t INXCMP1; /!< Index compare register 1 /
Jasper_lee	0:b16d94660a33	1211	__IO uint32_t INXCMP2; /!< Index compare register 2 /
Jasper_lee	0:b16d94660a33	1212	__I uint32_t RESERVED0[993];
Jasper_lee	0:b16d94660a33	1213	__O uint32_t IEC; /!< Interrupt enable clear register /
Jasper_lee	0:b16d94660a33	1214	__O uint32_t IES; /!< Interrupt enable set register /
Jasper_lee	0:b16d94660a33	1215	__I uint32_t INTSTAT; /!< Interrupt status register /
Jasper_lee	0:b16d94660a33	1216	__O uint32_t IE; /!< Interrupt enable clear register /
Jasper_lee	0:b16d94660a33	1217	__O uint32_t CLR; /!< Interrupt status clear register /
Jasper_lee	0:b16d94660a33	1218	__O uint32_t SET; /!< Interrupt status set register /
Jasper_lee	0:b16d94660a33	1219	} LPC_QEI_Type;
Jasper_lee	0:b16d94660a33	1220
Jasper_lee	0:b16d94660a33	1221
Jasper_lee	0:b16d94660a33	1222	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1223	/* ================ SYSCON ================ */
Jasper_lee	0:b16d94660a33	1224	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1225
Jasper_lee	0:b16d94660a33	1226
Jasper_lee	0:b16d94660a33	1227	/**
Jasper_lee	0:b16d94660a33	1228	* @brief System configuration (SYSCON) (SYSCON)
Jasper_lee	0:b16d94660a33	1229	*/
Jasper_lee	0:b16d94660a33	1230
Jasper_lee	0:b16d94660a33	1231	typedef struct { /!< SYSCON Structure /
Jasper_lee	0:b16d94660a33	1232	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
Jasper_lee	0:b16d94660a33	1233	__I uint32_t RESERVED0[4];
Jasper_lee	0:b16d94660a33	1234	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
Jasper_lee	0:b16d94660a33	1235	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	1236	__IO uint32_t NMISRC; /!< NMI Source Control /
Jasper_lee	0:b16d94660a33	1237	__I uint32_t RESERVED2[8];
Jasper_lee	0:b16d94660a33	1238	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
Jasper_lee	0:b16d94660a33	1239	__IO uint32_t PRESETCTRL0; /!< Peripheral reset control 0 /
Jasper_lee	0:b16d94660a33	1240	__IO uint32_t PRESETCTRL1; /!< Peripheral reset control 1 /
Jasper_lee	0:b16d94660a33	1241	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
Jasper_lee	0:b16d94660a33	1242	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
Jasper_lee	0:b16d94660a33	1243	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 2 /
Jasper_lee	0:b16d94660a33	1244	__I uint32_t RESERVED3[10];
Jasper_lee	0:b16d94660a33	1245	__IO uint32_t MAINCLKSELA; /!< Main clock source select A /
Jasper_lee	0:b16d94660a33	1246	__IO uint32_t MAINCLKSELB; /!< Main clock source select B /
Jasper_lee	0:b16d94660a33	1247	__IO uint32_t USBCLKSEL; /!< USB clock source select /
Jasper_lee	0:b16d94660a33	1248	__IO uint32_t ADCASYNCCLKSEL; /!< ADC asynchronous clock source select /
Jasper_lee	0:b16d94660a33	1249	__I uint32_t RESERVED4;
Jasper_lee	0:b16d94660a33	1250	__IO uint32_t CLKOUTSELA; /!< CLKOUT clock source select A /
Jasper_lee	0:b16d94660a33	1251	__IO uint32_t CLKOUTSELB; /!< CLKOUT clock source select B /
Jasper_lee	0:b16d94660a33	1252	__I uint32_t RESERVED5;
Jasper_lee	0:b16d94660a33	1253	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
Jasper_lee	0:b16d94660a33	1254	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
Jasper_lee	0:b16d94660a33	1255	__IO uint32_t SCTPLLCLKSEL; /!< SCT PLL clock source select /
Jasper_lee	0:b16d94660a33	1256	__I uint32_t RESERVED6[5];
Jasper_lee	0:b16d94660a33	1257	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
Jasper_lee	0:b16d94660a33	1258	__IO uint32_t SYSAHBCLKCTRL0; /!< System clock control 0 /
Jasper_lee	0:b16d94660a33	1259	__IO uint32_t SYSAHBCLKCTRL1; /!< System clock control 1 /
Jasper_lee	0:b16d94660a33	1260	__IO uint32_t SYSTICKCLKDIV; /!< SYSTICK clock divider /
Jasper_lee	0:b16d94660a33	1261	__IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
Jasper_lee	0:b16d94660a33	1262	baud rate generator. */
Jasper_lee	0:b16d94660a33	1263	__IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
Jasper_lee	0:b16d94660a33	1264	filter */
Jasper_lee	0:b16d94660a33	1265	__IO uint32_t TRACECLKDIV; /!< ARM trace clock divider /
Jasper_lee	0:b16d94660a33	1266	__I uint32_t RESERVED7[4];
Jasper_lee	0:b16d94660a33	1267	__IO uint32_t USBCLKDIV; /!< USB clock divider /
Jasper_lee	0:b16d94660a33	1268	__IO uint32_t ADCASYNCCLKDIV; /!< Asynchronous ADC clock divider /
Jasper_lee	0:b16d94660a33	1269	__I uint32_t RESERVED8;
Jasper_lee	0:b16d94660a33	1270	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
Jasper_lee	0:b16d94660a33	1271	__I uint32_t RESERVED9[11];
Jasper_lee	0:b16d94660a33	1272	__IO uint32_t FRGCTRL; /!< USART fractional baud rate generator control /
Jasper_lee	0:b16d94660a33	1273	__IO uint32_t USBCLKCTRL; /!< USB clock control /
Jasper_lee	0:b16d94660a33	1274	__IO uint32_t USBCLKST; /!< USB clock status /
Jasper_lee	0:b16d94660a33	1275	__I uint32_t RESERVED10[19];
Jasper_lee	0:b16d94660a33	1276	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
Jasper_lee	0:b16d94660a33	1277	__I uint32_t RESERVED11;
Jasper_lee	0:b16d94660a33	1278	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
Jasper_lee	0:b16d94660a33	1279	__I uint32_t RESERVED12;
Jasper_lee	0:b16d94660a33	1280	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator control /
Jasper_lee	0:b16d94660a33	1281	__I uint32_t RESERVED13;
Jasper_lee	0:b16d94660a33	1282	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
Jasper_lee	0:b16d94660a33	1283	__I uint32_t SYSPLLSTAT; /!< System PLL status /
Jasper_lee	0:b16d94660a33	1284	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
Jasper_lee	0:b16d94660a33	1285	__I uint32_t USBPLLSTAT; /!< USB PLL status /
Jasper_lee	0:b16d94660a33	1286	__IO uint32_t SCTPLLCTRL; /!< SCT PLL control /
Jasper_lee	0:b16d94660a33	1287	__I uint32_t SCTPLLSTAT; /!< SCT PLL status /
Jasper_lee	0:b16d94660a33	1288	__I uint32_t RESERVED14[21];
Jasper_lee	0:b16d94660a33	1289	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
Jasper_lee	0:b16d94660a33	1290	__IO uint32_t PDRUNCFG; /!< Power configuration register /
Jasper_lee	0:b16d94660a33	1291	__I uint32_t RESERVED15[3];
Jasper_lee	0:b16d94660a33	1292	__IO uint32_t STARTERP0; /!< Start logic 0 wake-up enable register /
Jasper_lee	0:b16d94660a33	1293	__IO uint32_t STARTERP1; /!< Start logic 1 wake-up enable register /
Jasper_lee	0:b16d94660a33	1294	} LPC_SYSCON_Type;
Jasper_lee	0:b16d94660a33	1295
Jasper_lee	0:b16d94660a33	1296
Jasper_lee	0:b16d94660a33	1297	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1298	/* ================ MRT ================ */
Jasper_lee	0:b16d94660a33	1299	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1300
Jasper_lee	0:b16d94660a33	1301
Jasper_lee	0:b16d94660a33	1302	/**
Jasper_lee	0:b16d94660a33	1303	* @brief Multi-Rate Timer (MRT) (MRT)
Jasper_lee	0:b16d94660a33	1304	*/
Jasper_lee	0:b16d94660a33	1305
Jasper_lee	0:b16d94660a33	1306	typedef struct { /!< MRT Structure /
Jasper_lee	0:b16d94660a33	1307	__IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
Jasper_lee	0:b16d94660a33	1308	the TIMER0 register. */
Jasper_lee	0:b16d94660a33	1309	__I uint32_t TIMER0; /!< MRT0 Timer register. This register reads the value of the down-counter. /
Jasper_lee	0:b16d94660a33	1310	__IO uint32_t CTRL0; /!< MRT0 Control register. This register controls the MRT0 modes. /
Jasper_lee	0:b16d94660a33	1311	__IO uint32_t STAT0; /!< MRT0 Status register. /
Jasper_lee	0:b16d94660a33	1312	__IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
Jasper_lee	0:b16d94660a33	1313	the TIMER0 register. */
Jasper_lee	0:b16d94660a33	1314	__I uint32_t TIMER1; /!< MRT0 Timer register. This register reads the value of the down-counter. /
Jasper_lee	0:b16d94660a33	1315	__IO uint32_t CTRL1; /!< MRT0 Control register. This register controls the MRT0 modes. /
Jasper_lee	0:b16d94660a33	1316	__IO uint32_t STAT1; /!< MRT0 Status register. /
Jasper_lee	0:b16d94660a33	1317	__IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
Jasper_lee	0:b16d94660a33	1318	the TIMER0 register. */
Jasper_lee	0:b16d94660a33	1319	__I uint32_t TIMER2; /!< MRT0 Timer register. This register reads the value of the down-counter. /
Jasper_lee	0:b16d94660a33	1320	__IO uint32_t CTRL2; /!< MRT0 Control register. This register controls the MRT0 modes. /
Jasper_lee	0:b16d94660a33	1321	__IO uint32_t STAT2; /!< MRT0 Status register. /
Jasper_lee	0:b16d94660a33	1322	__IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
Jasper_lee	0:b16d94660a33	1323	the TIMER0 register. */
Jasper_lee	0:b16d94660a33	1324	__I uint32_t TIMER3; /!< MRT0 Timer register. This register reads the value of the down-counter. /
Jasper_lee	0:b16d94660a33	1325	__IO uint32_t CTRL3; /!< MRT0 Control register. This register controls the MRT0 modes. /
Jasper_lee	0:b16d94660a33	1326	__IO uint32_t STAT3; /!< MRT0 Status register. /
Jasper_lee	0:b16d94660a33	1327	__I uint32_t RESERVED0[45];
Jasper_lee	0:b16d94660a33	1328	__I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
Jasper_lee	0:b16d94660a33	1329	first idle channel. */
Jasper_lee	0:b16d94660a33	1330	__IO uint32_t IRQ_FLAG; /!< Global interrupt flag register /
Jasper_lee	0:b16d94660a33	1331	} LPC_MRT_Type;
Jasper_lee	0:b16d94660a33	1332
Jasper_lee	0:b16d94660a33	1333
Jasper_lee	0:b16d94660a33	1334	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1335	/* ================ PINT ================ */
Jasper_lee	0:b16d94660a33	1336	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1337
Jasper_lee	0:b16d94660a33	1338
Jasper_lee	0:b16d94660a33	1339	/**
Jasper_lee	0:b16d94660a33	1340	* @brief Pin interruptand pattern match (PINT) (PINT)
Jasper_lee	0:b16d94660a33	1341	*/
Jasper_lee	0:b16d94660a33	1342
Jasper_lee	0:b16d94660a33	1343	typedef struct { /!< PINT Structure /
Jasper_lee	0:b16d94660a33	1344	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
Jasper_lee	0:b16d94660a33	1345	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
Jasper_lee	0:b16d94660a33	1346	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
Jasper_lee	0:b16d94660a33	1347	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
Jasper_lee	0:b16d94660a33	1348	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
Jasper_lee	0:b16d94660a33	1349	register */
Jasper_lee	0:b16d94660a33	1350	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
Jasper_lee	0:b16d94660a33	1351	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
Jasper_lee	0:b16d94660a33	1352	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
Jasper_lee	0:b16d94660a33	1353	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
Jasper_lee	0:b16d94660a33	1354	__IO uint32_t IST; /!< Pin interrupt status register /
Jasper_lee	0:b16d94660a33	1355	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
Jasper_lee	0:b16d94660a33	1356	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
Jasper_lee	0:b16d94660a33	1357	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
Jasper_lee	0:b16d94660a33	1358	} LPC_PINT_Type;
Jasper_lee	0:b16d94660a33	1359
Jasper_lee	0:b16d94660a33	1360
Jasper_lee	0:b16d94660a33	1361	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1362	/* ================ GINT0 ================ */
Jasper_lee	0:b16d94660a33	1363	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1364
Jasper_lee	0:b16d94660a33	1365
Jasper_lee	0:b16d94660a33	1366	/**
Jasper_lee	0:b16d94660a33	1367	* @brief Group interrupt 0/1 (GINT0/1) (GINT0)
Jasper_lee	0:b16d94660a33	1368	*/
Jasper_lee	0:b16d94660a33	1369
Jasper_lee	0:b16d94660a33	1370	typedef struct { /!< GINT0 Structure /
Jasper_lee	0:b16d94660a33	1371	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
Jasper_lee	0:b16d94660a33	1372	__I uint32_t RESERVED0[7];
Jasper_lee	0:b16d94660a33	1373	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
Jasper_lee	0:b16d94660a33	1374	__I uint32_t RESERVED1[5];
Jasper_lee	0:b16d94660a33	1375	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port 0 enable register /
Jasper_lee	0:b16d94660a33	1376	} LPC_GINT0_Type;
Jasper_lee	0:b16d94660a33	1377
Jasper_lee	0:b16d94660a33	1378
Jasper_lee	0:b16d94660a33	1379	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1380	/* ================ RIT ================ */
Jasper_lee	0:b16d94660a33	1381	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1382
Jasper_lee	0:b16d94660a33	1383
Jasper_lee	0:b16d94660a33	1384	/**
Jasper_lee	0:b16d94660a33	1385	* @brief Repetitive Interrupt Timer (RIT) (RIT)
Jasper_lee	0:b16d94660a33	1386	*/
Jasper_lee	0:b16d94660a33	1387
Jasper_lee	0:b16d94660a33	1388	typedef struct { /!< RIT Structure /
Jasper_lee	0:b16d94660a33	1389	__IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
Jasper_lee	0:b16d94660a33	1390	value. */
Jasper_lee	0:b16d94660a33	1391	__IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
Jasper_lee	0:b16d94660a33	1392	value. A 1 written to any bit will force a compare on the corresponding
Jasper_lee	0:b16d94660a33	1393	bit of the counter and compare register. */
Jasper_lee	0:b16d94660a33	1394	__IO uint32_t CTRL; /!< Control register. /
Jasper_lee	0:b16d94660a33	1395	__IO uint32_t COUNTER; /!< Counter LSB register. 32 LSBs of the counter. /
Jasper_lee	0:b16d94660a33	1396	__IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
Jasper_lee	0:b16d94660a33	1397	value. */
Jasper_lee	0:b16d94660a33	1398	__IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
Jasper_lee	0:b16d94660a33	1399	value. A 1 written to any bit will force a compare on the corresponding
Jasper_lee	0:b16d94660a33	1400	bit of the counter and compare register. */
Jasper_lee	0:b16d94660a33	1401	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1402	__IO uint32_t COUNTER_H; /!< Counter MSB register. 16 MSBs of the counter. /
Jasper_lee	0:b16d94660a33	1403	} LPC_RIT_Type;
Jasper_lee	0:b16d94660a33	1404
Jasper_lee	0:b16d94660a33	1405
Jasper_lee	0:b16d94660a33	1406	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1407	/* ================ SCTIPU ================ */
Jasper_lee	0:b16d94660a33	1408	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1409
Jasper_lee	0:b16d94660a33	1410
Jasper_lee	0:b16d94660a33	1411	/**
Jasper_lee	0:b16d94660a33	1412	* @brief SCT Input Processing Unit (IPU) (SCTIPU)
Jasper_lee	0:b16d94660a33	1413	*/
Jasper_lee	0:b16d94660a33	1414
Jasper_lee	0:b16d94660a33	1415	typedef struct { /!< SCTIPU Structure /
Jasper_lee	0:b16d94660a33	1416	__IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
Jasper_lee	0:b16d94660a33	1417	latch/sample-enable mux selects, and sample overrride bits for
Jasper_lee	0:b16d94660a33	1418	the SAMPLE module. */
Jasper_lee	0:b16d94660a33	1419	__I uint32_t RESERVED0[7];
Jasper_lee	0:b16d94660a33	1420	__IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
Jasper_lee	0:b16d94660a33	1421	to ORed Abort Output 0. */
Jasper_lee	0:b16d94660a33	1422	__IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
Jasper_lee	0:b16d94660a33	1423	input source caused abort output 0. */
Jasper_lee	0:b16d94660a33	1424	__I uint32_t RESERVED1[6];
Jasper_lee	0:b16d94660a33	1425	__IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
Jasper_lee	0:b16d94660a33	1426	to ORed Abort Output 0. */
Jasper_lee	0:b16d94660a33	1427	__IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
Jasper_lee	0:b16d94660a33	1428	input source caused abort output 0. */
Jasper_lee	0:b16d94660a33	1429	__I uint32_t RESERVED2[6];
Jasper_lee	0:b16d94660a33	1430	__IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
Jasper_lee	0:b16d94660a33	1431	to ORed Abort Output 0. */
Jasper_lee	0:b16d94660a33	1432	__IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
Jasper_lee	0:b16d94660a33	1433	input source caused abort output 0. */
Jasper_lee	0:b16d94660a33	1434	__I uint32_t RESERVED3[6];
Jasper_lee	0:b16d94660a33	1435	__IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
Jasper_lee	0:b16d94660a33	1436	to ORed Abort Output 0. */
Jasper_lee	0:b16d94660a33	1437	__IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
Jasper_lee	0:b16d94660a33	1438	input source caused abort output 0. */
Jasper_lee	0:b16d94660a33	1439	} LPC_SCTIPU_Type;
Jasper_lee	0:b16d94660a33	1440
Jasper_lee	0:b16d94660a33	1441
Jasper_lee	0:b16d94660a33	1442	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1443	/* ================ FLASHCTRL ================ */
Jasper_lee	0:b16d94660a33	1444	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1445
Jasper_lee	0:b16d94660a33	1446
Jasper_lee	0:b16d94660a33	1447	/**
Jasper_lee	0:b16d94660a33	1448	* @brief Flash controller (FLASHCTRL)
Jasper_lee	0:b16d94660a33	1449	*/
Jasper_lee	0:b16d94660a33	1450
Jasper_lee	0:b16d94660a33	1451	typedef struct { /!< FLASHCTRL Structure /
Jasper_lee	0:b16d94660a33	1452	__I uint32_t RESERVED0[8];
Jasper_lee	0:b16d94660a33	1453	__IO uint32_t FMSSTART; /!< Signature start address register /
Jasper_lee	0:b16d94660a33	1454	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
Jasper_lee	0:b16d94660a33	1455	__I uint32_t RESERVED1;
Jasper_lee	0:b16d94660a33	1456	__I uint32_t FMSW0; /!< Signature word /
Jasper_lee	0:b16d94660a33	1457	} LPC_FLASHCTRL_Type;
Jasper_lee	0:b16d94660a33	1458
Jasper_lee	0:b16d94660a33	1459
Jasper_lee	0:b16d94660a33	1460	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1461	/* ================ C_CAN0 ================ */
Jasper_lee	0:b16d94660a33	1462	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1463
Jasper_lee	0:b16d94660a33	1464
Jasper_lee	0:b16d94660a33	1465	/**
Jasper_lee	0:b16d94660a33	1466	* @brief Controller Area Network C_CAN0 (C_CAN0)
Jasper_lee	0:b16d94660a33	1467	*/
Jasper_lee	0:b16d94660a33	1468
Jasper_lee	0:b16d94660a33	1469	typedef struct { /!< C_CAN0 Structure /
Jasper_lee	0:b16d94660a33	1470	__IO uint32_t CANCNTL; /!< CAN control /
Jasper_lee	0:b16d94660a33	1471	__IO uint32_t CANSTAT; /!< Status register /
Jasper_lee	0:b16d94660a33	1472	__I uint32_t CANEC; /!< Error counter /
Jasper_lee	0:b16d94660a33	1473	__IO uint32_t CANBT; /!< Bit timing register /
Jasper_lee	0:b16d94660a33	1474	__I uint32_t CANINT; /!< Interrupt register /
Jasper_lee	0:b16d94660a33	1475	__IO uint32_t CANTEST; /!< Test register /
Jasper_lee	0:b16d94660a33	1476	__IO uint32_t CANBRPE; /!< Baud rate prescaler extension register /
Jasper_lee	0:b16d94660a33	1477	__I uint32_t RESERVED0;
Jasper_lee	0:b16d94660a33	1478	__IO uint32_t CANIF1_CMDREQ; /!< Message interface 1 command request /
Jasper_lee	0:b16d94660a33	1479
Jasper_lee	0:b16d94660a33	1480	union {
Jasper_lee	0:b16d94660a33	1481	__IO uint32_t CANIF1_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
Jasper_lee	0:b16d94660a33	1482	__IO uint32_t CANIF1_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
Jasper_lee	0:b16d94660a33	1483	};
Jasper_lee	0:b16d94660a33	1484	__IO uint32_t CANIF1_MSK1; /!< Message interface 1 mask 1 /
Jasper_lee	0:b16d94660a33	1485	__IO uint32_t CANIF1_MSK2; /!< Message interface 1 mask 2 /
Jasper_lee	0:b16d94660a33	1486	__IO uint32_t CANIF1_ARB1; /!< Message interface 1 arbitration 1 /
Jasper_lee	0:b16d94660a33	1487	__IO uint32_t CANIF1_ARB2; /!< Message interface 1 arbitration 2 /
Jasper_lee	0:b16d94660a33	1488	__IO uint32_t CANIF1_MCTRL; /!< Message interface 1 message control /
Jasper_lee	0:b16d94660a33	1489	__IO uint32_t CANIF1_DA1; /!< Message interface 1 data A1 /
Jasper_lee	0:b16d94660a33	1490	__IO uint32_t CANIF1_DA2; /!< Message interface 1 data A2 /
Jasper_lee	0:b16d94660a33	1491	__IO uint32_t CANIF1_DB1; /!< Message interface 1 data B1 /
Jasper_lee	0:b16d94660a33	1492	__IO uint32_t CANIF1_DB2; /!< Message interface 1 data B2 /
Jasper_lee	0:b16d94660a33	1493	__I uint32_t RESERVED1[13];
Jasper_lee	0:b16d94660a33	1494	__IO uint32_t CANIF2_CMDREQ; /!< Message interface 1 command request /
Jasper_lee	0:b16d94660a33	1495
Jasper_lee	0:b16d94660a33	1496	union {
Jasper_lee	0:b16d94660a33	1497	__IO uint32_t CANIF2_CMDMSK_W; /!< Message interface 1 command mask (write direction) /
Jasper_lee	0:b16d94660a33	1498	__IO uint32_t CANIF2_CMDMSK_R; /!< Message interface 1 command mask (read direction) /
Jasper_lee	0:b16d94660a33	1499	};
Jasper_lee	0:b16d94660a33	1500	__IO uint32_t CANIF2_MSK1; /!< Message interface 1 mask 1 /
Jasper_lee	0:b16d94660a33	1501	__IO uint32_t CANIF2_MSK2; /!< Message interface 1 mask 2 /
Jasper_lee	0:b16d94660a33	1502	__IO uint32_t CANIF2_ARB1; /!< Message interface 1 arbitration 1 /
Jasper_lee	0:b16d94660a33	1503	__IO uint32_t CANIF2_ARB2; /!< Message interface 1 arbitration 2 /
Jasper_lee	0:b16d94660a33	1504	__IO uint32_t CANIF2_MCTRL; /!< Message interface 1 message control /
Jasper_lee	0:b16d94660a33	1505	__IO uint32_t CANIF2_DA1; /!< Message interface 2 data A1 /
Jasper_lee	0:b16d94660a33	1506	__IO uint32_t CANIF2_DA2; /!< Message interface 2 data A2 /
Jasper_lee	0:b16d94660a33	1507	__IO uint32_t CANIF2_DB1; /!< Message interface 2 data B1 /
Jasper_lee	0:b16d94660a33	1508	__IO uint32_t CANIF2_DB2; /!< Message interface 2 data B2 /
Jasper_lee	0:b16d94660a33	1509	__I uint32_t RESERVED2[21];
Jasper_lee	0:b16d94660a33	1510	__I uint32_t CANTXREQ1; /!< Transmission request 1 /
Jasper_lee	0:b16d94660a33	1511	__I uint32_t CANTXREQ2; /!< Transmission request 2 /
Jasper_lee	0:b16d94660a33	1512	__I uint32_t RESERVED3[6];
Jasper_lee	0:b16d94660a33	1513	__I uint32_t CANND1; /!< New data 1 /
Jasper_lee	0:b16d94660a33	1514	__I uint32_t CANND2; /!< New data 2 /
Jasper_lee	0:b16d94660a33	1515	__I uint32_t RESERVED4[6];
Jasper_lee	0:b16d94660a33	1516	__I uint32_t CANIR1; /!< Interrupt pending 1 /
Jasper_lee	0:b16d94660a33	1517	__I uint32_t CANIR2; /!< Interrupt pending 2 /
Jasper_lee	0:b16d94660a33	1518	__I uint32_t RESERVED5[6];
Jasper_lee	0:b16d94660a33	1519	__I uint32_t CANMSGV1; /!< Message valid 1 /
Jasper_lee	0:b16d94660a33	1520	__I uint32_t CANMSGV2; /!< Message valid 2 /
Jasper_lee	0:b16d94660a33	1521	__I uint32_t RESERVED6[6];
Jasper_lee	0:b16d94660a33	1522	__IO uint32_t CANCLKDIV; /!< Can clock divider register /
Jasper_lee	0:b16d94660a33	1523	} LPC_C_CAN0_Type;
Jasper_lee	0:b16d94660a33	1524
Jasper_lee	0:b16d94660a33	1525
Jasper_lee	0:b16d94660a33	1526	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1527	/* ================ IOCON ================ */
Jasper_lee	0:b16d94660a33	1528	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1529
Jasper_lee	0:b16d94660a33	1530
Jasper_lee	0:b16d94660a33	1531	/**
Jasper_lee	0:b16d94660a33	1532	* @brief I/O pin configuration (IOCON) (IOCON)
Jasper_lee	0:b16d94660a33	1533	*/
Jasper_lee	0:b16d94660a33	1534
Jasper_lee	0:b16d94660a33	1535	typedef struct { /!< IOCON Structure /
Jasper_lee	0:b16d94660a33	1536	__IO uint32_t PIO0_0; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1537	__IO uint32_t PIO0_1; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1538	__IO uint32_t PIO0_2; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1539	__IO uint32_t PIO0_3; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1540	__IO uint32_t PIO0_4; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1541	__IO uint32_t PIO0_5; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1542	__IO uint32_t PIO0_6; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1543	__IO uint32_t PIO0_7; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1544	__IO uint32_t PIO0_8; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1545	__IO uint32_t PIO0_9; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1546	__IO uint32_t PIO0_10; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1547	__IO uint32_t PIO0_11; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1548	__IO uint32_t PIO0_12; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1549	__IO uint32_t PIO0_13; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1550	__IO uint32_t PIO0_14; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1551	__IO uint32_t PIO0_15; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1552	__IO uint32_t PIO0_16; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1553	__IO uint32_t PIO0_17; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1554	__IO uint32_t PIO0_18; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1555	__IO uint32_t PIO0_19; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1556	__IO uint32_t PIO0_20; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1557	__IO uint32_t PIO0_21; /!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. /
Jasper_lee	0:b16d94660a33	1558	__IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
Jasper_lee	0:b16d94660a33	1559	the I2C-bus SCL function. */
Jasper_lee	0:b16d94660a33	1560	__IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
Jasper_lee	0:b16d94660a33	1561	the I2C-bus SCL function. */
Jasper_lee	0:b16d94660a33	1562	__IO uint32_t PIO0_24; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1563	__IO uint32_t PIO0_25; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1564	__IO uint32_t PIO0_26; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1565	__IO uint32_t PIO0_27; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1566	__IO uint32_t PIO0_28; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1567	__IO uint32_t PIO0_29; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1568	__IO uint32_t PIO0_30; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1569	__IO uint32_t PIO0_31; /!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. /
Jasper_lee	0:b16d94660a33	1570	__IO uint32_t PIO1_0; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1571	__IO uint32_t PIO1_1; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1572	__IO uint32_t PIO1_2; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1573	__IO uint32_t PIO1_3; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1574	__IO uint32_t PIO1_4; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1575	__IO uint32_t PIO1_5; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1576	__IO uint32_t PIO1_6; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1577	__IO uint32_t PIO1_7; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1578	__IO uint32_t PIO1_8; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1579	__IO uint32_t PIO1_9; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1580	__IO uint32_t PIO1_10; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1581	__IO uint32_t PIO1_11; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1582	__IO uint32_t PIO1_12; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1583	__IO uint32_t PIO1_13; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1584	__IO uint32_t PIO1_14; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1585	__IO uint32_t PIO1_15; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1586	__IO uint32_t PIO1_16; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1587	__IO uint32_t PIO1_17; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1588	__IO uint32_t PIO1_18; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1589	__IO uint32_t PIO1_19; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1590	__IO uint32_t PIO1_20; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1591	__IO uint32_t PIO1_21; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1592	__IO uint32_t PIO1_22; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1593	__IO uint32_t PIO1_23; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1594	__IO uint32_t PIO1_24; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1595	__IO uint32_t PIO1_25; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1596	__IO uint32_t PIO1_26; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1597	__IO uint32_t PIO1_27; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1598	__IO uint32_t PIO1_28; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1599	__IO uint32_t PIO1_29; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1600	__IO uint32_t PIO1_30; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1601	__IO uint32_t PIO1_31; /!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. /
Jasper_lee	0:b16d94660a33	1602	__IO uint32_t PIO2_0; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1603	__IO uint32_t PIO2_1; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1604	__IO uint32_t PIO2_2; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1605	__IO uint32_t PIO2_3; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1606	__IO uint32_t PIO2_4; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1607	__IO uint32_t PIO2_5; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1608	__IO uint32_t PIO2_6; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1609	__IO uint32_t PIO2_7; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1610	__IO uint32_t PIO2_8; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1611	__IO uint32_t PIO2_9; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1612	__IO uint32_t PIO2_10; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1613	__IO uint32_t PIO2_11; /!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. /
Jasper_lee	0:b16d94660a33	1614	} LPC_IOCON_Type;
Jasper_lee	0:b16d94660a33	1615
Jasper_lee	0:b16d94660a33	1616
Jasper_lee	0:b16d94660a33	1617	/* -------------------- End of section using anonymous unions ------------------- */
Jasper_lee	0:b16d94660a33	1618	#if defined(__CC_ARM)
Jasper_lee	0:b16d94660a33	1619	#pragma pop
Jasper_lee	0:b16d94660a33	1620	#elif defined(__ICCARM__)
Jasper_lee	0:b16d94660a33	1621	/* leave anonymous unions enabled */
Jasper_lee	0:b16d94660a33	1622	#elif defined(__GNUC__)
Jasper_lee	0:b16d94660a33	1623	/* anonymous unions are enabled by default */
Jasper_lee	0:b16d94660a33	1624	#elif defined(__TMS470__)
Jasper_lee	0:b16d94660a33	1625	/* anonymous unions are enabled by default */
Jasper_lee	0:b16d94660a33	1626	#elif defined(__TASKING__)
Jasper_lee	0:b16d94660a33	1627	#pragma warning restore
Jasper_lee	0:b16d94660a33	1628	#else
Jasper_lee	0:b16d94660a33	1629	#warning Not supported compiler type
Jasper_lee	0:b16d94660a33	1630	#endif
Jasper_lee	0:b16d94660a33	1631
Jasper_lee	0:b16d94660a33	1632
Jasper_lee	0:b16d94660a33	1633
Jasper_lee	0:b16d94660a33	1634
Jasper_lee	0:b16d94660a33	1635	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1636	/* ================ Peripheral memory map ================ */
Jasper_lee	0:b16d94660a33	1637	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1638
Jasper_lee	0:b16d94660a33	1639	#define LPC_GPIO_PORT_BASE 0x1C000000UL
Jasper_lee	0:b16d94660a33	1640	#define LPC_DMA_BASE 0x1C004000UL
Jasper_lee	0:b16d94660a33	1641	#define LPC_USB_BASE 0x1C00C000UL
Jasper_lee	0:b16d94660a33	1642	#define LPC_CRC_BASE 0x1C010000UL
Jasper_lee	0:b16d94660a33	1643	#define LPC_SCT0_BASE 0x1C018000UL
Jasper_lee	0:b16d94660a33	1644	#define LPC_SCT1_BASE 0x1C01C000UL
Jasper_lee	0:b16d94660a33	1645	#define LPC_SCT2_BASE 0x1C020000UL
Jasper_lee	0:b16d94660a33	1646	#define LPC_SCT3_BASE 0x1C024000UL
Jasper_lee	0:b16d94660a33	1647	#define LPC_ADC0_BASE 0x40000000UL
Jasper_lee	0:b16d94660a33	1648	#define LPC_DAC_BASE 0x40004000UL
Jasper_lee	0:b16d94660a33	1649	#define LPC_ACMP_BASE 0x40008000UL
Jasper_lee	0:b16d94660a33	1650	#define LPC_INMUX_BASE 0x40014000UL
Jasper_lee	0:b16d94660a33	1651	#define LPC_RTC_BASE 0x40028000UL
Jasper_lee	0:b16d94660a33	1652	#define LPC_WWDT_BASE 0x4002C000UL
Jasper_lee	0:b16d94660a33	1653	#define LPC_SWM_BASE 0x40038000UL
Jasper_lee	0:b16d94660a33	1654	#define LPC_PMU_BASE 0x4003C000UL
Jasper_lee	0:b16d94660a33	1655	#define LPC_USART0_BASE 0x40040000UL
Jasper_lee	0:b16d94660a33	1656	#define LPC_USART1_BASE 0x40044000UL
Jasper_lee	0:b16d94660a33	1657	#define LPC_SPI0_BASE 0x40048000UL
Jasper_lee	0:b16d94660a33	1658	#define LPC_SPI1_BASE 0x4004C000UL
Jasper_lee	0:b16d94660a33	1659	#define LPC_I2C0_BASE 0x40050000UL
Jasper_lee	0:b16d94660a33	1660	#define LPC_QEI_BASE 0x40058000UL
Jasper_lee	0:b16d94660a33	1661	#define LPC_SYSCON_BASE 0x40074000UL
Jasper_lee	0:b16d94660a33	1662	#define LPC_ADC1_BASE 0x40080000UL
Jasper_lee	0:b16d94660a33	1663	#define LPC_MRT_BASE 0x400A0000UL
Jasper_lee	0:b16d94660a33	1664	#define LPC_PINT_BASE 0x400A4000UL
Jasper_lee	0:b16d94660a33	1665	#define LPC_GINT0_BASE 0x400A8000UL
Jasper_lee	0:b16d94660a33	1666	#define LPC_GINT1_BASE 0x400AC000UL
Jasper_lee	0:b16d94660a33	1667	#define LPC_RIT_BASE 0x400B4000UL
Jasper_lee	0:b16d94660a33	1668	#define LPC_SCTIPU_BASE 0x400B8000UL
Jasper_lee	0:b16d94660a33	1669	#define LPC_FLASHCTRL_BASE 0x400BC000UL
Jasper_lee	0:b16d94660a33	1670	#define LPC_USART2_BASE 0x400C0000UL
Jasper_lee	0:b16d94660a33	1671	#define LPC_C_CAN0_BASE 0x400F0000UL
Jasper_lee	0:b16d94660a33	1672	#define LPC_IOCON_BASE 0x400F8000UL
Jasper_lee	0:b16d94660a33	1673
Jasper_lee	0:b16d94660a33	1674
Jasper_lee	0:b16d94660a33	1675	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1676	/* ================ Peripheral declaration ================ */
Jasper_lee	0:b16d94660a33	1677	/* ================================================================================ */
Jasper_lee	0:b16d94660a33	1678
Jasper_lee	0:b16d94660a33	1679	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
Jasper_lee	0:b16d94660a33	1680	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
Jasper_lee	0:b16d94660a33	1681	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
Jasper_lee	0:b16d94660a33	1682	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
Jasper_lee	0:b16d94660a33	1683	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
Jasper_lee	0:b16d94660a33	1684	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
Jasper_lee	0:b16d94660a33	1685	#define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
Jasper_lee	0:b16d94660a33	1686	#define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
Jasper_lee	0:b16d94660a33	1687	#define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
Jasper_lee	0:b16d94660a33	1688	#define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
Jasper_lee	0:b16d94660a33	1689	#define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
Jasper_lee	0:b16d94660a33	1690	#define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
Jasper_lee	0:b16d94660a33	1691	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
Jasper_lee	0:b16d94660a33	1692	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
Jasper_lee	0:b16d94660a33	1693	#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
Jasper_lee	0:b16d94660a33	1694	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
Jasper_lee	0:b16d94660a33	1695	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
Jasper_lee	0:b16d94660a33	1696	#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
Jasper_lee	0:b16d94660a33	1697	#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
Jasper_lee	0:b16d94660a33	1698	#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
Jasper_lee	0:b16d94660a33	1699	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
Jasper_lee	0:b16d94660a33	1700	#define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
Jasper_lee	0:b16d94660a33	1701	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
Jasper_lee	0:b16d94660a33	1702	#define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
Jasper_lee	0:b16d94660a33	1703	#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
Jasper_lee	0:b16d94660a33	1704	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
Jasper_lee	0:b16d94660a33	1705	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
Jasper_lee	0:b16d94660a33	1706	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
Jasper_lee	0:b16d94660a33	1707	#define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
Jasper_lee	0:b16d94660a33	1708	#define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
Jasper_lee	0:b16d94660a33	1709	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
Jasper_lee	0:b16d94660a33	1710	#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
Jasper_lee	0:b16d94660a33	1711	#define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
Jasper_lee	0:b16d94660a33	1712	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
Jasper_lee	0:b16d94660a33	1713
Jasper_lee	0:b16d94660a33	1714
Jasper_lee	0:b16d94660a33	1715	/** @} / / End of group Device_Peripheral_Registers */
Jasper_lee	0:b16d94660a33	1716	/** @} / / End of group LPC15xx */
Jasper_lee	0:b16d94660a33	1717	/** @} / / End of group (null) */
Jasper_lee	0:b16d94660a33	1718
Jasper_lee	0:b16d94660a33	1719	#ifdef __cplusplus
Jasper_lee	0:b16d94660a33	1720	}
Jasper_lee	0:b16d94660a33	1721	#endif
Jasper_lee	0:b16d94660a33	1722
Jasper_lee	0:b16d94660a33	1723
Jasper_lee	0:b16d94660a33	1724	#endif /* LPC15XX_H */
Jasper_lee	0:b16d94660a33	1725

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Type:	Library
Created:	23 Dec 2014
Imports:	459
Forks:	0
Commits:	1
Dependents:	1
Dependencies:	0
Followers:	12

The code in this repository is Apache licensed.

TARGET_LPC1549/LPC15xx.h@0:b16d94660a33, 2014-12-23 (annotated)

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