Jasper Lee / mbed_helloworld

change some io settings for TWR-K22F-120M

Dependents:   twr_helloworld

TARGET_K64F/MK64F12.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:
Jasper_lee
Date:
Tue Dec 23 03:35:08 2014 +0000
Revision:
0:b16d94660a33
change some io setting used in TWR-K22F120M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jasper_lee 0:b16d94660a33 1 /*
Jasper_lee 0:b16d94660a33 2 ** ###################################################################
Jasper_lee 0:b16d94660a33 3 ** Processors: MK64FN1M0VDC12
Jasper_lee 0:b16d94660a33 4 ** MK64FN1M0VLL12
Jasper_lee 0:b16d94660a33 5 ** MK64FN1M0VLQ12
Jasper_lee 0:b16d94660a33 6 ** MK64FN1M0VMD12
Jasper_lee 0:b16d94660a33 7 **
Jasper_lee 0:b16d94660a33 8 ** Compilers: Keil ARM C/C++ Compiler
Jasper_lee 0:b16d94660a33 9 ** Freescale C/C++ for Embedded ARM
Jasper_lee 0:b16d94660a33 10 ** GNU C Compiler
Jasper_lee 0:b16d94660a33 11 ** GNU C Compiler - CodeSourcery Sourcery G++
Jasper_lee 0:b16d94660a33 12 ** IAR ANSI C/C++ Compiler for ARM
Jasper_lee 0:b16d94660a33 13 **
Jasper_lee 0:b16d94660a33 14 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
Jasper_lee 0:b16d94660a33 15 ** Version: rev. 2.5, 2014-02-10
Jasper_lee 0:b16d94660a33 16 ** Build: b140604
Jasper_lee 0:b16d94660a33 17 **
Jasper_lee 0:b16d94660a33 18 ** Abstract:
Jasper_lee 0:b16d94660a33 19 ** CMSIS Peripheral Access Layer for MK64F12
Jasper_lee 0:b16d94660a33 20 **
Jasper_lee 0:b16d94660a33 21 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
Jasper_lee 0:b16d94660a33 22 ** All rights reserved.
Jasper_lee 0:b16d94660a33 23 **
Jasper_lee 0:b16d94660a33 24 ** Redistribution and use in source and binary forms, with or without modification,
Jasper_lee 0:b16d94660a33 25 ** are permitted provided that the following conditions are met:
Jasper_lee 0:b16d94660a33 26 **
Jasper_lee 0:b16d94660a33 27 ** o Redistributions of source code must retain the above copyright notice, this list
Jasper_lee 0:b16d94660a33 28 ** of conditions and the following disclaimer.
Jasper_lee 0:b16d94660a33 29 **
Jasper_lee 0:b16d94660a33 30 ** o Redistributions in binary form must reproduce the above copyright notice, this
Jasper_lee 0:b16d94660a33 31 ** list of conditions and the following disclaimer in the documentation and/or
Jasper_lee 0:b16d94660a33 32 ** other materials provided with the distribution.
Jasper_lee 0:b16d94660a33 33 **
Jasper_lee 0:b16d94660a33 34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Jasper_lee 0:b16d94660a33 35 ** contributors may be used to endorse or promote products derived from this
Jasper_lee 0:b16d94660a33 36 ** software without specific prior written permission.
Jasper_lee 0:b16d94660a33 37 **
Jasper_lee 0:b16d94660a33 38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Jasper_lee 0:b16d94660a33 39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Jasper_lee 0:b16d94660a33 40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jasper_lee 0:b16d94660a33 41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Jasper_lee 0:b16d94660a33 42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Jasper_lee 0:b16d94660a33 43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Jasper_lee 0:b16d94660a33 44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Jasper_lee 0:b16d94660a33 45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Jasper_lee 0:b16d94660a33 46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Jasper_lee 0:b16d94660a33 47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jasper_lee 0:b16d94660a33 48 **
Jasper_lee 0:b16d94660a33 49 ** http: www.freescale.com
Jasper_lee 0:b16d94660a33 50 ** mail: support@freescale.com
Jasper_lee 0:b16d94660a33 51 **
Jasper_lee 0:b16d94660a33 52 ** Revisions:
Jasper_lee 0:b16d94660a33 53 ** - rev. 1.0 (2013-08-12)
Jasper_lee 0:b16d94660a33 54 ** Initial version.
Jasper_lee 0:b16d94660a33 55 ** - rev. 2.0 (2013-10-29)
Jasper_lee 0:b16d94660a33 56 ** Register accessor macros added to the memory map.
Jasper_lee 0:b16d94660a33 57 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Jasper_lee 0:b16d94660a33 58 ** Startup file for gcc has been updated according to CMSIS 3.2.
Jasper_lee 0:b16d94660a33 59 ** System initialization updated.
Jasper_lee 0:b16d94660a33 60 ** MCG - registers updated.
Jasper_lee 0:b16d94660a33 61 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
Jasper_lee 0:b16d94660a33 62 ** - rev. 2.1 (2013-10-30)
Jasper_lee 0:b16d94660a33 63 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Jasper_lee 0:b16d94660a33 64 ** - rev. 2.2 (2013-12-09)
Jasper_lee 0:b16d94660a33 65 ** DMA - EARS register removed.
Jasper_lee 0:b16d94660a33 66 ** AIPS0, AIPS1 - MPRA register updated.
Jasper_lee 0:b16d94660a33 67 ** - rev. 2.3 (2014-01-24)
Jasper_lee 0:b16d94660a33 68 ** Update according to reference manual rev. 2
Jasper_lee 0:b16d94660a33 69 ** ENET, MCG, MCM, SIM, USB - registers updated
Jasper_lee 0:b16d94660a33 70 ** - rev. 2.4 (2014-02-10)
Jasper_lee 0:b16d94660a33 71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Jasper_lee 0:b16d94660a33 72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Jasper_lee 0:b16d94660a33 73 ** - rev. 2.5 (2014-02-10)
Jasper_lee 0:b16d94660a33 74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
Jasper_lee 0:b16d94660a33 75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
Jasper_lee 0:b16d94660a33 76 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Jasper_lee 0:b16d94660a33 77 **
Jasper_lee 0:b16d94660a33 78 ** ###################################################################
Jasper_lee 0:b16d94660a33 79 */
Jasper_lee 0:b16d94660a33 80
Jasper_lee 0:b16d94660a33 81 /*!
Jasper_lee 0:b16d94660a33 82 * @file MK64F12.h
Jasper_lee 0:b16d94660a33 83 * @version 2.5
Jasper_lee 0:b16d94660a33 84 * @date 2014-02-10
Jasper_lee 0:b16d94660a33 85 * @brief CMSIS Peripheral Access Layer for MK64F12
Jasper_lee 0:b16d94660a33 86 *
Jasper_lee 0:b16d94660a33 87 * CMSIS Peripheral Access Layer for MK64F12
Jasper_lee 0:b16d94660a33 88 */
Jasper_lee 0:b16d94660a33 89
Jasper_lee 0:b16d94660a33 90
Jasper_lee 0:b16d94660a33 91 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 92 -- MCU activation
Jasper_lee 0:b16d94660a33 93 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 94
Jasper_lee 0:b16d94660a33 95 /* Prevention from multiple including the same memory map */
Jasper_lee 0:b16d94660a33 96 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */
Jasper_lee 0:b16d94660a33 97 #define MK64F12_H_
Jasper_lee 0:b16d94660a33 98 #define MCU_MK64F12
Jasper_lee 0:b16d94660a33 99
Jasper_lee 0:b16d94660a33 100 /* Check if another memory map has not been also included */
Jasper_lee 0:b16d94660a33 101 #if (defined(MCU_ACTIVE))
Jasper_lee 0:b16d94660a33 102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
Jasper_lee 0:b16d94660a33 103 #endif /* (defined(MCU_ACTIVE)) */
Jasper_lee 0:b16d94660a33 104 #define MCU_ACTIVE
Jasper_lee 0:b16d94660a33 105
Jasper_lee 0:b16d94660a33 106 #include <stdint.h>
Jasper_lee 0:b16d94660a33 107
Jasper_lee 0:b16d94660a33 108 /** Memory map major version (memory maps with equal major version number are
Jasper_lee 0:b16d94660a33 109 * compatible) */
Jasper_lee 0:b16d94660a33 110 #define MCU_MEM_MAP_VERSION 0x0200u
Jasper_lee 0:b16d94660a33 111 /** Memory map minor version */
Jasper_lee 0:b16d94660a33 112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
Jasper_lee 0:b16d94660a33 113
Jasper_lee 0:b16d94660a33 114 /**
Jasper_lee 0:b16d94660a33 115 * @brief Macro to calculate address of an aliased word in the peripheral
Jasper_lee 0:b16d94660a33 116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
Jasper_lee 0:b16d94660a33 117 * 0x400FFFFF).
Jasper_lee 0:b16d94660a33 118 * @param Reg Register to access.
Jasper_lee 0:b16d94660a33 119 * @param Bit Bit number to access.
Jasper_lee 0:b16d94660a33 120 * @return Address of the aliased word in the peripheral bitband area.
Jasper_lee 0:b16d94660a33 121 */
Jasper_lee 0:b16d94660a33 122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
Jasper_lee 0:b16d94660a33 123 /**
Jasper_lee 0:b16d94660a33 124 * @brief Macro to access a single bit of a peripheral register (bit band region
Jasper_lee 0:b16d94660a33 125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Jasper_lee 0:b16d94660a33 126 * be used for peripherals with 32bit access allowed.
Jasper_lee 0:b16d94660a33 127 * @param Reg Register to access.
Jasper_lee 0:b16d94660a33 128 * @param Bit Bit number to access.
Jasper_lee 0:b16d94660a33 129 * @return Value of the targeted bit in the bit band region.
Jasper_lee 0:b16d94660a33 130 */
Jasper_lee 0:b16d94660a33 131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Jasper_lee 0:b16d94660a33 132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
Jasper_lee 0:b16d94660a33 133 /**
Jasper_lee 0:b16d94660a33 134 * @brief Macro to access a single bit of a peripheral register (bit band region
Jasper_lee 0:b16d94660a33 135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Jasper_lee 0:b16d94660a33 136 * be used for peripherals with 16bit access allowed.
Jasper_lee 0:b16d94660a33 137 * @param Reg Register to access.
Jasper_lee 0:b16d94660a33 138 * @param Bit Bit number to access.
Jasper_lee 0:b16d94660a33 139 * @return Value of the targeted bit in the bit band region.
Jasper_lee 0:b16d94660a33 140 */
Jasper_lee 0:b16d94660a33 141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Jasper_lee 0:b16d94660a33 142 /**
Jasper_lee 0:b16d94660a33 143 * @brief Macro to access a single bit of a peripheral register (bit band region
Jasper_lee 0:b16d94660a33 144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
Jasper_lee 0:b16d94660a33 145 * be used for peripherals with 8bit access allowed.
Jasper_lee 0:b16d94660a33 146 * @param Reg Register to access.
Jasper_lee 0:b16d94660a33 147 * @param Bit Bit number to access.
Jasper_lee 0:b16d94660a33 148 * @return Value of the targeted bit in the bit band region.
Jasper_lee 0:b16d94660a33 149 */
Jasper_lee 0:b16d94660a33 150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
Jasper_lee 0:b16d94660a33 151
Jasper_lee 0:b16d94660a33 152 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 153 -- Interrupt vector numbers
Jasper_lee 0:b16d94660a33 154 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 155
Jasper_lee 0:b16d94660a33 156 /*!
Jasper_lee 0:b16d94660a33 157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Jasper_lee 0:b16d94660a33 158 * @{
Jasper_lee 0:b16d94660a33 159 */
Jasper_lee 0:b16d94660a33 160
Jasper_lee 0:b16d94660a33 161 /** Interrupt Number Definitions */
Jasper_lee 0:b16d94660a33 162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
Jasper_lee 0:b16d94660a33 163
Jasper_lee 0:b16d94660a33 164 typedef enum IRQn {
Jasper_lee 0:b16d94660a33 165 /* Core interrupts */
Jasper_lee 0:b16d94660a33 166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
Jasper_lee 0:b16d94660a33 167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
Jasper_lee 0:b16d94660a33 168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
Jasper_lee 0:b16d94660a33 169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
Jasper_lee 0:b16d94660a33 170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
Jasper_lee 0:b16d94660a33 171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
Jasper_lee 0:b16d94660a33 172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
Jasper_lee 0:b16d94660a33 173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
Jasper_lee 0:b16d94660a33 174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
Jasper_lee 0:b16d94660a33 175
Jasper_lee 0:b16d94660a33 176 /* Device specific interrupts */
Jasper_lee 0:b16d94660a33 177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
Jasper_lee 0:b16d94660a33 178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
Jasper_lee 0:b16d94660a33 179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
Jasper_lee 0:b16d94660a33 180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
Jasper_lee 0:b16d94660a33 181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
Jasper_lee 0:b16d94660a33 182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
Jasper_lee 0:b16d94660a33 183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
Jasper_lee 0:b16d94660a33 184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
Jasper_lee 0:b16d94660a33 185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
Jasper_lee 0:b16d94660a33 186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
Jasper_lee 0:b16d94660a33 187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
Jasper_lee 0:b16d94660a33 188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
Jasper_lee 0:b16d94660a33 189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
Jasper_lee 0:b16d94660a33 190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
Jasper_lee 0:b16d94660a33 191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
Jasper_lee 0:b16d94660a33 192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
Jasper_lee 0:b16d94660a33 193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
Jasper_lee 0:b16d94660a33 194 MCM_IRQn = 17, /**< Normal Interrupt */
Jasper_lee 0:b16d94660a33 195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
Jasper_lee 0:b16d94660a33 196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
Jasper_lee 0:b16d94660a33 197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
Jasper_lee 0:b16d94660a33 198 LLW_IRQn = 21, /**< Low Leakage Wakeup */
Jasper_lee 0:b16d94660a33 199 Watchdog_IRQn = 22, /**< WDOG Interrupt */
Jasper_lee 0:b16d94660a33 200 RNG_IRQn = 23, /**< RNG Interrupt */
Jasper_lee 0:b16d94660a33 201 I2C0_IRQn = 24, /**< I2C0 interrupt */
Jasper_lee 0:b16d94660a33 202 I2C1_IRQn = 25, /**< I2C1 interrupt */
Jasper_lee 0:b16d94660a33 203 SPI0_IRQn = 26, /**< SPI0 Interrupt */
Jasper_lee 0:b16d94660a33 204 SPI1_IRQn = 27, /**< SPI1 Interrupt */
Jasper_lee 0:b16d94660a33 205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
Jasper_lee 0:b16d94660a33 206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
Jasper_lee 0:b16d94660a33 207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
Jasper_lee 0:b16d94660a33 208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
Jasper_lee 0:b16d94660a33 210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
Jasper_lee 0:b16d94660a33 212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
Jasper_lee 0:b16d94660a33 214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
Jasper_lee 0:b16d94660a33 216 ADC0_IRQn = 39, /**< ADC0 interrupt */
Jasper_lee 0:b16d94660a33 217 CMP0_IRQn = 40, /**< CMP0 interrupt */
Jasper_lee 0:b16d94660a33 218 CMP1_IRQn = 41, /**< CMP1 interrupt */
Jasper_lee 0:b16d94660a33 219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
Jasper_lee 0:b16d94660a33 220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
Jasper_lee 0:b16d94660a33 221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
Jasper_lee 0:b16d94660a33 222 CMT_IRQn = 45, /**< CMT interrupt */
Jasper_lee 0:b16d94660a33 223 RTC_IRQn = 46, /**< RTC interrupt */
Jasper_lee 0:b16d94660a33 224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
Jasper_lee 0:b16d94660a33 225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
Jasper_lee 0:b16d94660a33 226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
Jasper_lee 0:b16d94660a33 227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
Jasper_lee 0:b16d94660a33 228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
Jasper_lee 0:b16d94660a33 229 PDB0_IRQn = 52, /**< PDB0 Interrupt */
Jasper_lee 0:b16d94660a33 230 USB0_IRQn = 53, /**< USB0 interrupt */
Jasper_lee 0:b16d94660a33 231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
Jasper_lee 0:b16d94660a33 232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
Jasper_lee 0:b16d94660a33 233 DAC0_IRQn = 56, /**< DAC0 interrupt */
Jasper_lee 0:b16d94660a33 234 MCG_IRQn = 57, /**< MCG Interrupt */
Jasper_lee 0:b16d94660a33 235 LPTimer_IRQn = 58, /**< LPTimer interrupt */
Jasper_lee 0:b16d94660a33 236 PORTA_IRQn = 59, /**< Port A interrupt */
Jasper_lee 0:b16d94660a33 237 PORTB_IRQn = 60, /**< Port B interrupt */
Jasper_lee 0:b16d94660a33 238 PORTC_IRQn = 61, /**< Port C interrupt */
Jasper_lee 0:b16d94660a33 239 PORTD_IRQn = 62, /**< Port D interrupt */
Jasper_lee 0:b16d94660a33 240 PORTE_IRQn = 63, /**< Port E interrupt */
Jasper_lee 0:b16d94660a33 241 SWI_IRQn = 64, /**< Software interrupt */
Jasper_lee 0:b16d94660a33 242 SPI2_IRQn = 65, /**< SPI2 Interrupt */
Jasper_lee 0:b16d94660a33 243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
Jasper_lee 0:b16d94660a33 245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
Jasper_lee 0:b16d94660a33 246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
Jasper_lee 0:b16d94660a33 247 CMP2_IRQn = 70, /**< CMP2 interrupt */
Jasper_lee 0:b16d94660a33 248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
Jasper_lee 0:b16d94660a33 249 DAC1_IRQn = 72, /**< DAC1 interrupt */
Jasper_lee 0:b16d94660a33 250 ADC1_IRQn = 73, /**< ADC1 interrupt */
Jasper_lee 0:b16d94660a33 251 I2C2_IRQn = 74, /**< I2C2 interrupt */
Jasper_lee 0:b16d94660a33 252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
Jasper_lee 0:b16d94660a33 253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
Jasper_lee 0:b16d94660a33 254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
Jasper_lee 0:b16d94660a33 255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
Jasper_lee 0:b16d94660a33 256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
Jasper_lee 0:b16d94660a33 257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
Jasper_lee 0:b16d94660a33 258 SDHC_IRQn = 81, /**< SDHC interrupt */
Jasper_lee 0:b16d94660a33 259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
Jasper_lee 0:b16d94660a33 260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
Jasper_lee 0:b16d94660a33 261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
Jasper_lee 0:b16d94660a33 262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
Jasper_lee 0:b16d94660a33 263 } IRQn_Type;
Jasper_lee 0:b16d94660a33 264
Jasper_lee 0:b16d94660a33 265 /*!
Jasper_lee 0:b16d94660a33 266 * @}
Jasper_lee 0:b16d94660a33 267 */ /* end of group Interrupt_vector_numbers */
Jasper_lee 0:b16d94660a33 268
Jasper_lee 0:b16d94660a33 269
Jasper_lee 0:b16d94660a33 270 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 271 -- Cortex M4 Core Configuration
Jasper_lee 0:b16d94660a33 272 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 273
Jasper_lee 0:b16d94660a33 274 /*!
Jasper_lee 0:b16d94660a33 275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
Jasper_lee 0:b16d94660a33 276 * @{
Jasper_lee 0:b16d94660a33 277 */
Jasper_lee 0:b16d94660a33 278
Jasper_lee 0:b16d94660a33 279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
Jasper_lee 0:b16d94660a33 280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
Jasper_lee 0:b16d94660a33 281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
Jasper_lee 0:b16d94660a33 282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
Jasper_lee 0:b16d94660a33 283
Jasper_lee 0:b16d94660a33 284 #include "core_cm4.h" /* Core Peripheral Access Layer */
Jasper_lee 0:b16d94660a33 285 #include "system_MK64F12.h" /* Device specific configuration file */
Jasper_lee 0:b16d94660a33 286
Jasper_lee 0:b16d94660a33 287 /*!
Jasper_lee 0:b16d94660a33 288 * @}
Jasper_lee 0:b16d94660a33 289 */ /* end of group Cortex_Core_Configuration */
Jasper_lee 0:b16d94660a33 290
Jasper_lee 0:b16d94660a33 291
Jasper_lee 0:b16d94660a33 292 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 293 -- Device Peripheral Access Layer
Jasper_lee 0:b16d94660a33 294 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 295
Jasper_lee 0:b16d94660a33 296 /*!
Jasper_lee 0:b16d94660a33 297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Jasper_lee 0:b16d94660a33 298 * @{
Jasper_lee 0:b16d94660a33 299 */
Jasper_lee 0:b16d94660a33 300
Jasper_lee 0:b16d94660a33 301
Jasper_lee 0:b16d94660a33 302 /*
Jasper_lee 0:b16d94660a33 303 ** Start of section using anonymous unions
Jasper_lee 0:b16d94660a33 304 */
Jasper_lee 0:b16d94660a33 305
Jasper_lee 0:b16d94660a33 306 #if defined(__ARMCC_VERSION)
Jasper_lee 0:b16d94660a33 307 #pragma push
Jasper_lee 0:b16d94660a33 308 #pragma anon_unions
Jasper_lee 0:b16d94660a33 309 #elif defined(__CWCC__)
Jasper_lee 0:b16d94660a33 310 #pragma push
Jasper_lee 0:b16d94660a33 311 #pragma cpp_extensions on
Jasper_lee 0:b16d94660a33 312 #elif defined(__GNUC__)
Jasper_lee 0:b16d94660a33 313 /* anonymous unions are enabled by default */
Jasper_lee 0:b16d94660a33 314 #elif defined(__IAR_SYSTEMS_ICC__)
Jasper_lee 0:b16d94660a33 315 #pragma language=extended
Jasper_lee 0:b16d94660a33 316 #else
Jasper_lee 0:b16d94660a33 317 #error Not supported compiler type
Jasper_lee 0:b16d94660a33 318 #endif
Jasper_lee 0:b16d94660a33 319
Jasper_lee 0:b16d94660a33 320 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 321 -- ADC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 322 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 323
Jasper_lee 0:b16d94660a33 324 /*!
Jasper_lee 0:b16d94660a33 325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 326 * @{
Jasper_lee 0:b16d94660a33 327 */
Jasper_lee 0:b16d94660a33 328
Jasper_lee 0:b16d94660a33 329 /** ADC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 330 typedef struct {
Jasper_lee 0:b16d94660a33 331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
Jasper_lee 0:b16d94660a33 333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
Jasper_lee 0:b16d94660a33 334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
Jasper_lee 0:b16d94660a33 335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
Jasper_lee 0:b16d94660a33 336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
Jasper_lee 0:b16d94660a33 337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
Jasper_lee 0:b16d94660a33 338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
Jasper_lee 0:b16d94660a33 339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
Jasper_lee 0:b16d94660a33 340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
Jasper_lee 0:b16d94660a33 341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
Jasper_lee 0:b16d94660a33 342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
Jasper_lee 0:b16d94660a33 343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
Jasper_lee 0:b16d94660a33 344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
Jasper_lee 0:b16d94660a33 345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
Jasper_lee 0:b16d94660a33 346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
Jasper_lee 0:b16d94660a33 347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
Jasper_lee 0:b16d94660a33 348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
Jasper_lee 0:b16d94660a33 349 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
Jasper_lee 0:b16d94660a33 351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
Jasper_lee 0:b16d94660a33 352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
Jasper_lee 0:b16d94660a33 353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
Jasper_lee 0:b16d94660a33 354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
Jasper_lee 0:b16d94660a33 355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
Jasper_lee 0:b16d94660a33 356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
Jasper_lee 0:b16d94660a33 357 } ADC_Type, *ADC_MemMapPtr;
Jasper_lee 0:b16d94660a33 358
Jasper_lee 0:b16d94660a33 359 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 360 -- ADC - Register accessor macros
Jasper_lee 0:b16d94660a33 361 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 362
Jasper_lee 0:b16d94660a33 363 /*!
Jasper_lee 0:b16d94660a33 364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Jasper_lee 0:b16d94660a33 365 * @{
Jasper_lee 0:b16d94660a33 366 */
Jasper_lee 0:b16d94660a33 367
Jasper_lee 0:b16d94660a33 368
Jasper_lee 0:b16d94660a33 369 /* ADC - Register accessors */
Jasper_lee 0:b16d94660a33 370 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
Jasper_lee 0:b16d94660a33 371 #define ADC_CFG1_REG(base) ((base)->CFG1)
Jasper_lee 0:b16d94660a33 372 #define ADC_CFG2_REG(base) ((base)->CFG2)
Jasper_lee 0:b16d94660a33 373 #define ADC_R_REG(base,index) ((base)->R[index])
Jasper_lee 0:b16d94660a33 374 #define ADC_CV1_REG(base) ((base)->CV1)
Jasper_lee 0:b16d94660a33 375 #define ADC_CV2_REG(base) ((base)->CV2)
Jasper_lee 0:b16d94660a33 376 #define ADC_SC2_REG(base) ((base)->SC2)
Jasper_lee 0:b16d94660a33 377 #define ADC_SC3_REG(base) ((base)->SC3)
Jasper_lee 0:b16d94660a33 378 #define ADC_OFS_REG(base) ((base)->OFS)
Jasper_lee 0:b16d94660a33 379 #define ADC_PG_REG(base) ((base)->PG)
Jasper_lee 0:b16d94660a33 380 #define ADC_MG_REG(base) ((base)->MG)
Jasper_lee 0:b16d94660a33 381 #define ADC_CLPD_REG(base) ((base)->CLPD)
Jasper_lee 0:b16d94660a33 382 #define ADC_CLPS_REG(base) ((base)->CLPS)
Jasper_lee 0:b16d94660a33 383 #define ADC_CLP4_REG(base) ((base)->CLP4)
Jasper_lee 0:b16d94660a33 384 #define ADC_CLP3_REG(base) ((base)->CLP3)
Jasper_lee 0:b16d94660a33 385 #define ADC_CLP2_REG(base) ((base)->CLP2)
Jasper_lee 0:b16d94660a33 386 #define ADC_CLP1_REG(base) ((base)->CLP1)
Jasper_lee 0:b16d94660a33 387 #define ADC_CLP0_REG(base) ((base)->CLP0)
Jasper_lee 0:b16d94660a33 388 #define ADC_CLMD_REG(base) ((base)->CLMD)
Jasper_lee 0:b16d94660a33 389 #define ADC_CLMS_REG(base) ((base)->CLMS)
Jasper_lee 0:b16d94660a33 390 #define ADC_CLM4_REG(base) ((base)->CLM4)
Jasper_lee 0:b16d94660a33 391 #define ADC_CLM3_REG(base) ((base)->CLM3)
Jasper_lee 0:b16d94660a33 392 #define ADC_CLM2_REG(base) ((base)->CLM2)
Jasper_lee 0:b16d94660a33 393 #define ADC_CLM1_REG(base) ((base)->CLM1)
Jasper_lee 0:b16d94660a33 394 #define ADC_CLM0_REG(base) ((base)->CLM0)
Jasper_lee 0:b16d94660a33 395
Jasper_lee 0:b16d94660a33 396 /*!
Jasper_lee 0:b16d94660a33 397 * @}
Jasper_lee 0:b16d94660a33 398 */ /* end of group ADC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 399
Jasper_lee 0:b16d94660a33 400
Jasper_lee 0:b16d94660a33 401 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 402 -- ADC Register Masks
Jasper_lee 0:b16d94660a33 403 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 404
Jasper_lee 0:b16d94660a33 405 /*!
Jasper_lee 0:b16d94660a33 406 * @addtogroup ADC_Register_Masks ADC Register Masks
Jasper_lee 0:b16d94660a33 407 * @{
Jasper_lee 0:b16d94660a33 408 */
Jasper_lee 0:b16d94660a33 409
Jasper_lee 0:b16d94660a33 410 /* SC1 Bit Fields */
Jasper_lee 0:b16d94660a33 411 #define ADC_SC1_ADCH_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 412 #define ADC_SC1_ADCH_SHIFT 0
Jasper_lee 0:b16d94660a33 413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
Jasper_lee 0:b16d94660a33 414 #define ADC_SC1_DIFF_MASK 0x20u
Jasper_lee 0:b16d94660a33 415 #define ADC_SC1_DIFF_SHIFT 5
Jasper_lee 0:b16d94660a33 416 #define ADC_SC1_AIEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 417 #define ADC_SC1_AIEN_SHIFT 6
Jasper_lee 0:b16d94660a33 418 #define ADC_SC1_COCO_MASK 0x80u
Jasper_lee 0:b16d94660a33 419 #define ADC_SC1_COCO_SHIFT 7
Jasper_lee 0:b16d94660a33 420 /* CFG1 Bit Fields */
Jasper_lee 0:b16d94660a33 421 #define ADC_CFG1_ADICLK_MASK 0x3u
Jasper_lee 0:b16d94660a33 422 #define ADC_CFG1_ADICLK_SHIFT 0
Jasper_lee 0:b16d94660a33 423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
Jasper_lee 0:b16d94660a33 424 #define ADC_CFG1_MODE_MASK 0xCu
Jasper_lee 0:b16d94660a33 425 #define ADC_CFG1_MODE_SHIFT 2
Jasper_lee 0:b16d94660a33 426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
Jasper_lee 0:b16d94660a33 427 #define ADC_CFG1_ADLSMP_MASK 0x10u
Jasper_lee 0:b16d94660a33 428 #define ADC_CFG1_ADLSMP_SHIFT 4
Jasper_lee 0:b16d94660a33 429 #define ADC_CFG1_ADIV_MASK 0x60u
Jasper_lee 0:b16d94660a33 430 #define ADC_CFG1_ADIV_SHIFT 5
Jasper_lee 0:b16d94660a33 431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
Jasper_lee 0:b16d94660a33 432 #define ADC_CFG1_ADLPC_MASK 0x80u
Jasper_lee 0:b16d94660a33 433 #define ADC_CFG1_ADLPC_SHIFT 7
Jasper_lee 0:b16d94660a33 434 /* CFG2 Bit Fields */
Jasper_lee 0:b16d94660a33 435 #define ADC_CFG2_ADLSTS_MASK 0x3u
Jasper_lee 0:b16d94660a33 436 #define ADC_CFG2_ADLSTS_SHIFT 0
Jasper_lee 0:b16d94660a33 437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
Jasper_lee 0:b16d94660a33 438 #define ADC_CFG2_ADHSC_MASK 0x4u
Jasper_lee 0:b16d94660a33 439 #define ADC_CFG2_ADHSC_SHIFT 2
Jasper_lee 0:b16d94660a33 440 #define ADC_CFG2_ADACKEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 441 #define ADC_CFG2_ADACKEN_SHIFT 3
Jasper_lee 0:b16d94660a33 442 #define ADC_CFG2_MUXSEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 443 #define ADC_CFG2_MUXSEL_SHIFT 4
Jasper_lee 0:b16d94660a33 444 /* R Bit Fields */
Jasper_lee 0:b16d94660a33 445 #define ADC_R_D_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 446 #define ADC_R_D_SHIFT 0
Jasper_lee 0:b16d94660a33 447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
Jasper_lee 0:b16d94660a33 448 /* CV1 Bit Fields */
Jasper_lee 0:b16d94660a33 449 #define ADC_CV1_CV_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 450 #define ADC_CV1_CV_SHIFT 0
Jasper_lee 0:b16d94660a33 451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
Jasper_lee 0:b16d94660a33 452 /* CV2 Bit Fields */
Jasper_lee 0:b16d94660a33 453 #define ADC_CV2_CV_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 454 #define ADC_CV2_CV_SHIFT 0
Jasper_lee 0:b16d94660a33 455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
Jasper_lee 0:b16d94660a33 456 /* SC2 Bit Fields */
Jasper_lee 0:b16d94660a33 457 #define ADC_SC2_REFSEL_MASK 0x3u
Jasper_lee 0:b16d94660a33 458 #define ADC_SC2_REFSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
Jasper_lee 0:b16d94660a33 460 #define ADC_SC2_DMAEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 461 #define ADC_SC2_DMAEN_SHIFT 2
Jasper_lee 0:b16d94660a33 462 #define ADC_SC2_ACREN_MASK 0x8u
Jasper_lee 0:b16d94660a33 463 #define ADC_SC2_ACREN_SHIFT 3
Jasper_lee 0:b16d94660a33 464 #define ADC_SC2_ACFGT_MASK 0x10u
Jasper_lee 0:b16d94660a33 465 #define ADC_SC2_ACFGT_SHIFT 4
Jasper_lee 0:b16d94660a33 466 #define ADC_SC2_ACFE_MASK 0x20u
Jasper_lee 0:b16d94660a33 467 #define ADC_SC2_ACFE_SHIFT 5
Jasper_lee 0:b16d94660a33 468 #define ADC_SC2_ADTRG_MASK 0x40u
Jasper_lee 0:b16d94660a33 469 #define ADC_SC2_ADTRG_SHIFT 6
Jasper_lee 0:b16d94660a33 470 #define ADC_SC2_ADACT_MASK 0x80u
Jasper_lee 0:b16d94660a33 471 #define ADC_SC2_ADACT_SHIFT 7
Jasper_lee 0:b16d94660a33 472 /* SC3 Bit Fields */
Jasper_lee 0:b16d94660a33 473 #define ADC_SC3_AVGS_MASK 0x3u
Jasper_lee 0:b16d94660a33 474 #define ADC_SC3_AVGS_SHIFT 0
Jasper_lee 0:b16d94660a33 475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
Jasper_lee 0:b16d94660a33 476 #define ADC_SC3_AVGE_MASK 0x4u
Jasper_lee 0:b16d94660a33 477 #define ADC_SC3_AVGE_SHIFT 2
Jasper_lee 0:b16d94660a33 478 #define ADC_SC3_ADCO_MASK 0x8u
Jasper_lee 0:b16d94660a33 479 #define ADC_SC3_ADCO_SHIFT 3
Jasper_lee 0:b16d94660a33 480 #define ADC_SC3_CALF_MASK 0x40u
Jasper_lee 0:b16d94660a33 481 #define ADC_SC3_CALF_SHIFT 6
Jasper_lee 0:b16d94660a33 482 #define ADC_SC3_CAL_MASK 0x80u
Jasper_lee 0:b16d94660a33 483 #define ADC_SC3_CAL_SHIFT 7
Jasper_lee 0:b16d94660a33 484 /* OFS Bit Fields */
Jasper_lee 0:b16d94660a33 485 #define ADC_OFS_OFS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 486 #define ADC_OFS_OFS_SHIFT 0
Jasper_lee 0:b16d94660a33 487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
Jasper_lee 0:b16d94660a33 488 /* PG Bit Fields */
Jasper_lee 0:b16d94660a33 489 #define ADC_PG_PG_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 490 #define ADC_PG_PG_SHIFT 0
Jasper_lee 0:b16d94660a33 491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
Jasper_lee 0:b16d94660a33 492 /* MG Bit Fields */
Jasper_lee 0:b16d94660a33 493 #define ADC_MG_MG_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 494 #define ADC_MG_MG_SHIFT 0
Jasper_lee 0:b16d94660a33 495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
Jasper_lee 0:b16d94660a33 496 /* CLPD Bit Fields */
Jasper_lee 0:b16d94660a33 497 #define ADC_CLPD_CLPD_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 498 #define ADC_CLPD_CLPD_SHIFT 0
Jasper_lee 0:b16d94660a33 499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
Jasper_lee 0:b16d94660a33 500 /* CLPS Bit Fields */
Jasper_lee 0:b16d94660a33 501 #define ADC_CLPS_CLPS_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 502 #define ADC_CLPS_CLPS_SHIFT 0
Jasper_lee 0:b16d94660a33 503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
Jasper_lee 0:b16d94660a33 504 /* CLP4 Bit Fields */
Jasper_lee 0:b16d94660a33 505 #define ADC_CLP4_CLP4_MASK 0x3FFu
Jasper_lee 0:b16d94660a33 506 #define ADC_CLP4_CLP4_SHIFT 0
Jasper_lee 0:b16d94660a33 507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
Jasper_lee 0:b16d94660a33 508 /* CLP3 Bit Fields */
Jasper_lee 0:b16d94660a33 509 #define ADC_CLP3_CLP3_MASK 0x1FFu
Jasper_lee 0:b16d94660a33 510 #define ADC_CLP3_CLP3_SHIFT 0
Jasper_lee 0:b16d94660a33 511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
Jasper_lee 0:b16d94660a33 512 /* CLP2 Bit Fields */
Jasper_lee 0:b16d94660a33 513 #define ADC_CLP2_CLP2_MASK 0xFFu
Jasper_lee 0:b16d94660a33 514 #define ADC_CLP2_CLP2_SHIFT 0
Jasper_lee 0:b16d94660a33 515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
Jasper_lee 0:b16d94660a33 516 /* CLP1 Bit Fields */
Jasper_lee 0:b16d94660a33 517 #define ADC_CLP1_CLP1_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 518 #define ADC_CLP1_CLP1_SHIFT 0
Jasper_lee 0:b16d94660a33 519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
Jasper_lee 0:b16d94660a33 520 /* CLP0 Bit Fields */
Jasper_lee 0:b16d94660a33 521 #define ADC_CLP0_CLP0_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 522 #define ADC_CLP0_CLP0_SHIFT 0
Jasper_lee 0:b16d94660a33 523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
Jasper_lee 0:b16d94660a33 524 /* CLMD Bit Fields */
Jasper_lee 0:b16d94660a33 525 #define ADC_CLMD_CLMD_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 526 #define ADC_CLMD_CLMD_SHIFT 0
Jasper_lee 0:b16d94660a33 527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
Jasper_lee 0:b16d94660a33 528 /* CLMS Bit Fields */
Jasper_lee 0:b16d94660a33 529 #define ADC_CLMS_CLMS_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 530 #define ADC_CLMS_CLMS_SHIFT 0
Jasper_lee 0:b16d94660a33 531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
Jasper_lee 0:b16d94660a33 532 /* CLM4 Bit Fields */
Jasper_lee 0:b16d94660a33 533 #define ADC_CLM4_CLM4_MASK 0x3FFu
Jasper_lee 0:b16d94660a33 534 #define ADC_CLM4_CLM4_SHIFT 0
Jasper_lee 0:b16d94660a33 535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
Jasper_lee 0:b16d94660a33 536 /* CLM3 Bit Fields */
Jasper_lee 0:b16d94660a33 537 #define ADC_CLM3_CLM3_MASK 0x1FFu
Jasper_lee 0:b16d94660a33 538 #define ADC_CLM3_CLM3_SHIFT 0
Jasper_lee 0:b16d94660a33 539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
Jasper_lee 0:b16d94660a33 540 /* CLM2 Bit Fields */
Jasper_lee 0:b16d94660a33 541 #define ADC_CLM2_CLM2_MASK 0xFFu
Jasper_lee 0:b16d94660a33 542 #define ADC_CLM2_CLM2_SHIFT 0
Jasper_lee 0:b16d94660a33 543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
Jasper_lee 0:b16d94660a33 544 /* CLM1 Bit Fields */
Jasper_lee 0:b16d94660a33 545 #define ADC_CLM1_CLM1_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 546 #define ADC_CLM1_CLM1_SHIFT 0
Jasper_lee 0:b16d94660a33 547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
Jasper_lee 0:b16d94660a33 548 /* CLM0 Bit Fields */
Jasper_lee 0:b16d94660a33 549 #define ADC_CLM0_CLM0_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 550 #define ADC_CLM0_CLM0_SHIFT 0
Jasper_lee 0:b16d94660a33 551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
Jasper_lee 0:b16d94660a33 552
Jasper_lee 0:b16d94660a33 553 /*!
Jasper_lee 0:b16d94660a33 554 * @}
Jasper_lee 0:b16d94660a33 555 */ /* end of group ADC_Register_Masks */
Jasper_lee 0:b16d94660a33 556
Jasper_lee 0:b16d94660a33 557
Jasper_lee 0:b16d94660a33 558 /* ADC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 559 /** Peripheral ADC0 base address */
Jasper_lee 0:b16d94660a33 560 #define ADC0_BASE (0x4003B000u)
Jasper_lee 0:b16d94660a33 561 /** Peripheral ADC0 base pointer */
Jasper_lee 0:b16d94660a33 562 #define ADC0 ((ADC_Type *)ADC0_BASE)
Jasper_lee 0:b16d94660a33 563 #define ADC0_BASE_PTR (ADC0)
Jasper_lee 0:b16d94660a33 564 /** Peripheral ADC1 base address */
Jasper_lee 0:b16d94660a33 565 #define ADC1_BASE (0x400BB000u)
Jasper_lee 0:b16d94660a33 566 /** Peripheral ADC1 base pointer */
Jasper_lee 0:b16d94660a33 567 #define ADC1 ((ADC_Type *)ADC1_BASE)
Jasper_lee 0:b16d94660a33 568 #define ADC1_BASE_PTR (ADC1)
Jasper_lee 0:b16d94660a33 569 /** Array initializer of ADC peripheral base addresses */
Jasper_lee 0:b16d94660a33 570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
Jasper_lee 0:b16d94660a33 571 /** Array initializer of ADC peripheral base pointers */
Jasper_lee 0:b16d94660a33 572 #define ADC_BASE_PTRS { ADC0, ADC1 }
Jasper_lee 0:b16d94660a33 573 /** Interrupt vectors for the ADC peripheral type */
Jasper_lee 0:b16d94660a33 574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
Jasper_lee 0:b16d94660a33 575
Jasper_lee 0:b16d94660a33 576 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 577 -- ADC - Register accessor macros
Jasper_lee 0:b16d94660a33 578 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 579
Jasper_lee 0:b16d94660a33 580 /*!
Jasper_lee 0:b16d94660a33 581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Jasper_lee 0:b16d94660a33 582 * @{
Jasper_lee 0:b16d94660a33 583 */
Jasper_lee 0:b16d94660a33 584
Jasper_lee 0:b16d94660a33 585
Jasper_lee 0:b16d94660a33 586 /* ADC - Register instance definitions */
Jasper_lee 0:b16d94660a33 587 /* ADC0 */
Jasper_lee 0:b16d94660a33 588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
Jasper_lee 0:b16d94660a33 589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
Jasper_lee 0:b16d94660a33 590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
Jasper_lee 0:b16d94660a33 591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
Jasper_lee 0:b16d94660a33 592 #define ADC0_RA ADC_R_REG(ADC0,0)
Jasper_lee 0:b16d94660a33 593 #define ADC0_RB ADC_R_REG(ADC0,1)
Jasper_lee 0:b16d94660a33 594 #define ADC0_CV1 ADC_CV1_REG(ADC0)
Jasper_lee 0:b16d94660a33 595 #define ADC0_CV2 ADC_CV2_REG(ADC0)
Jasper_lee 0:b16d94660a33 596 #define ADC0_SC2 ADC_SC2_REG(ADC0)
Jasper_lee 0:b16d94660a33 597 #define ADC0_SC3 ADC_SC3_REG(ADC0)
Jasper_lee 0:b16d94660a33 598 #define ADC0_OFS ADC_OFS_REG(ADC0)
Jasper_lee 0:b16d94660a33 599 #define ADC0_PG ADC_PG_REG(ADC0)
Jasper_lee 0:b16d94660a33 600 #define ADC0_MG ADC_MG_REG(ADC0)
Jasper_lee 0:b16d94660a33 601 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
Jasper_lee 0:b16d94660a33 602 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
Jasper_lee 0:b16d94660a33 603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
Jasper_lee 0:b16d94660a33 604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
Jasper_lee 0:b16d94660a33 605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
Jasper_lee 0:b16d94660a33 606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
Jasper_lee 0:b16d94660a33 607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
Jasper_lee 0:b16d94660a33 608 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
Jasper_lee 0:b16d94660a33 609 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
Jasper_lee 0:b16d94660a33 610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
Jasper_lee 0:b16d94660a33 611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
Jasper_lee 0:b16d94660a33 612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
Jasper_lee 0:b16d94660a33 613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
Jasper_lee 0:b16d94660a33 614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
Jasper_lee 0:b16d94660a33 615 /* ADC1 */
Jasper_lee 0:b16d94660a33 616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
Jasper_lee 0:b16d94660a33 617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
Jasper_lee 0:b16d94660a33 618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
Jasper_lee 0:b16d94660a33 619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
Jasper_lee 0:b16d94660a33 620 #define ADC1_RA ADC_R_REG(ADC1,0)
Jasper_lee 0:b16d94660a33 621 #define ADC1_RB ADC_R_REG(ADC1,1)
Jasper_lee 0:b16d94660a33 622 #define ADC1_CV1 ADC_CV1_REG(ADC1)
Jasper_lee 0:b16d94660a33 623 #define ADC1_CV2 ADC_CV2_REG(ADC1)
Jasper_lee 0:b16d94660a33 624 #define ADC1_SC2 ADC_SC2_REG(ADC1)
Jasper_lee 0:b16d94660a33 625 #define ADC1_SC3 ADC_SC3_REG(ADC1)
Jasper_lee 0:b16d94660a33 626 #define ADC1_OFS ADC_OFS_REG(ADC1)
Jasper_lee 0:b16d94660a33 627 #define ADC1_PG ADC_PG_REG(ADC1)
Jasper_lee 0:b16d94660a33 628 #define ADC1_MG ADC_MG_REG(ADC1)
Jasper_lee 0:b16d94660a33 629 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
Jasper_lee 0:b16d94660a33 630 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
Jasper_lee 0:b16d94660a33 631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
Jasper_lee 0:b16d94660a33 632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
Jasper_lee 0:b16d94660a33 633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
Jasper_lee 0:b16d94660a33 634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
Jasper_lee 0:b16d94660a33 635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
Jasper_lee 0:b16d94660a33 636 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
Jasper_lee 0:b16d94660a33 637 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
Jasper_lee 0:b16d94660a33 638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
Jasper_lee 0:b16d94660a33 639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
Jasper_lee 0:b16d94660a33 640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
Jasper_lee 0:b16d94660a33 641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
Jasper_lee 0:b16d94660a33 642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
Jasper_lee 0:b16d94660a33 643
Jasper_lee 0:b16d94660a33 644 /* ADC - Register array accessors */
Jasper_lee 0:b16d94660a33 645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
Jasper_lee 0:b16d94660a33 646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
Jasper_lee 0:b16d94660a33 647 #define ADC0_R(index) ADC_R_REG(ADC0,index)
Jasper_lee 0:b16d94660a33 648 #define ADC1_R(index) ADC_R_REG(ADC1,index)
Jasper_lee 0:b16d94660a33 649
Jasper_lee 0:b16d94660a33 650 /*!
Jasper_lee 0:b16d94660a33 651 * @}
Jasper_lee 0:b16d94660a33 652 */ /* end of group ADC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 653
Jasper_lee 0:b16d94660a33 654
Jasper_lee 0:b16d94660a33 655 /*!
Jasper_lee 0:b16d94660a33 656 * @}
Jasper_lee 0:b16d94660a33 657 */ /* end of group ADC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 658
Jasper_lee 0:b16d94660a33 659
Jasper_lee 0:b16d94660a33 660 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 661 -- AIPS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 662 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 663
Jasper_lee 0:b16d94660a33 664 /*!
Jasper_lee 0:b16d94660a33 665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 666 * @{
Jasper_lee 0:b16d94660a33 667 */
Jasper_lee 0:b16d94660a33 668
Jasper_lee 0:b16d94660a33 669 /** AIPS - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 670 typedef struct {
Jasper_lee 0:b16d94660a33 671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
Jasper_lee 0:b16d94660a33 672 uint8_t RESERVED_0[28];
Jasper_lee 0:b16d94660a33 673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
Jasper_lee 0:b16d94660a33 674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
Jasper_lee 0:b16d94660a33 675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
Jasper_lee 0:b16d94660a33 676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
Jasper_lee 0:b16d94660a33 677 uint8_t RESERVED_1[16];
Jasper_lee 0:b16d94660a33 678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
Jasper_lee 0:b16d94660a33 679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
Jasper_lee 0:b16d94660a33 680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
Jasper_lee 0:b16d94660a33 681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
Jasper_lee 0:b16d94660a33 682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
Jasper_lee 0:b16d94660a33 683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
Jasper_lee 0:b16d94660a33 684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
Jasper_lee 0:b16d94660a33 685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
Jasper_lee 0:b16d94660a33 686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
Jasper_lee 0:b16d94660a33 687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
Jasper_lee 0:b16d94660a33 688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
Jasper_lee 0:b16d94660a33 689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
Jasper_lee 0:b16d94660a33 690 uint8_t RESERVED_2[16];
Jasper_lee 0:b16d94660a33 691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
Jasper_lee 0:b16d94660a33 692 } AIPS_Type, *AIPS_MemMapPtr;
Jasper_lee 0:b16d94660a33 693
Jasper_lee 0:b16d94660a33 694 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 695 -- AIPS - Register accessor macros
Jasper_lee 0:b16d94660a33 696 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 697
Jasper_lee 0:b16d94660a33 698 /*!
Jasper_lee 0:b16d94660a33 699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
Jasper_lee 0:b16d94660a33 700 * @{
Jasper_lee 0:b16d94660a33 701 */
Jasper_lee 0:b16d94660a33 702
Jasper_lee 0:b16d94660a33 703
Jasper_lee 0:b16d94660a33 704 /* AIPS - Register accessors */
Jasper_lee 0:b16d94660a33 705 #define AIPS_MPRA_REG(base) ((base)->MPRA)
Jasper_lee 0:b16d94660a33 706 #define AIPS_PACRA_REG(base) ((base)->PACRA)
Jasper_lee 0:b16d94660a33 707 #define AIPS_PACRB_REG(base) ((base)->PACRB)
Jasper_lee 0:b16d94660a33 708 #define AIPS_PACRC_REG(base) ((base)->PACRC)
Jasper_lee 0:b16d94660a33 709 #define AIPS_PACRD_REG(base) ((base)->PACRD)
Jasper_lee 0:b16d94660a33 710 #define AIPS_PACRE_REG(base) ((base)->PACRE)
Jasper_lee 0:b16d94660a33 711 #define AIPS_PACRF_REG(base) ((base)->PACRF)
Jasper_lee 0:b16d94660a33 712 #define AIPS_PACRG_REG(base) ((base)->PACRG)
Jasper_lee 0:b16d94660a33 713 #define AIPS_PACRH_REG(base) ((base)->PACRH)
Jasper_lee 0:b16d94660a33 714 #define AIPS_PACRI_REG(base) ((base)->PACRI)
Jasper_lee 0:b16d94660a33 715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
Jasper_lee 0:b16d94660a33 716 #define AIPS_PACRK_REG(base) ((base)->PACRK)
Jasper_lee 0:b16d94660a33 717 #define AIPS_PACRL_REG(base) ((base)->PACRL)
Jasper_lee 0:b16d94660a33 718 #define AIPS_PACRM_REG(base) ((base)->PACRM)
Jasper_lee 0:b16d94660a33 719 #define AIPS_PACRN_REG(base) ((base)->PACRN)
Jasper_lee 0:b16d94660a33 720 #define AIPS_PACRO_REG(base) ((base)->PACRO)
Jasper_lee 0:b16d94660a33 721 #define AIPS_PACRP_REG(base) ((base)->PACRP)
Jasper_lee 0:b16d94660a33 722 #define AIPS_PACRU_REG(base) ((base)->PACRU)
Jasper_lee 0:b16d94660a33 723
Jasper_lee 0:b16d94660a33 724 /*!
Jasper_lee 0:b16d94660a33 725 * @}
Jasper_lee 0:b16d94660a33 726 */ /* end of group AIPS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 727
Jasper_lee 0:b16d94660a33 728
Jasper_lee 0:b16d94660a33 729 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 730 -- AIPS Register Masks
Jasper_lee 0:b16d94660a33 731 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 732
Jasper_lee 0:b16d94660a33 733 /*!
Jasper_lee 0:b16d94660a33 734 * @addtogroup AIPS_Register_Masks AIPS Register Masks
Jasper_lee 0:b16d94660a33 735 * @{
Jasper_lee 0:b16d94660a33 736 */
Jasper_lee 0:b16d94660a33 737
Jasper_lee 0:b16d94660a33 738 /* MPRA Bit Fields */
Jasper_lee 0:b16d94660a33 739 #define AIPS_MPRA_MPL5_MASK 0x100u
Jasper_lee 0:b16d94660a33 740 #define AIPS_MPRA_MPL5_SHIFT 8
Jasper_lee 0:b16d94660a33 741 #define AIPS_MPRA_MTW5_MASK 0x200u
Jasper_lee 0:b16d94660a33 742 #define AIPS_MPRA_MTW5_SHIFT 9
Jasper_lee 0:b16d94660a33 743 #define AIPS_MPRA_MTR5_MASK 0x400u
Jasper_lee 0:b16d94660a33 744 #define AIPS_MPRA_MTR5_SHIFT 10
Jasper_lee 0:b16d94660a33 745 #define AIPS_MPRA_MPL4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 746 #define AIPS_MPRA_MPL4_SHIFT 12
Jasper_lee 0:b16d94660a33 747 #define AIPS_MPRA_MTW4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 748 #define AIPS_MPRA_MTW4_SHIFT 13
Jasper_lee 0:b16d94660a33 749 #define AIPS_MPRA_MTR4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 750 #define AIPS_MPRA_MTR4_SHIFT 14
Jasper_lee 0:b16d94660a33 751 #define AIPS_MPRA_MPL3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 752 #define AIPS_MPRA_MPL3_SHIFT 16
Jasper_lee 0:b16d94660a33 753 #define AIPS_MPRA_MTW3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 754 #define AIPS_MPRA_MTW3_SHIFT 17
Jasper_lee 0:b16d94660a33 755 #define AIPS_MPRA_MTR3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 756 #define AIPS_MPRA_MTR3_SHIFT 18
Jasper_lee 0:b16d94660a33 757 #define AIPS_MPRA_MPL2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 758 #define AIPS_MPRA_MPL2_SHIFT 20
Jasper_lee 0:b16d94660a33 759 #define AIPS_MPRA_MTW2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 760 #define AIPS_MPRA_MTW2_SHIFT 21
Jasper_lee 0:b16d94660a33 761 #define AIPS_MPRA_MTR2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 762 #define AIPS_MPRA_MTR2_SHIFT 22
Jasper_lee 0:b16d94660a33 763 #define AIPS_MPRA_MPL1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 764 #define AIPS_MPRA_MPL1_SHIFT 24
Jasper_lee 0:b16d94660a33 765 #define AIPS_MPRA_MTW1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 766 #define AIPS_MPRA_MTW1_SHIFT 25
Jasper_lee 0:b16d94660a33 767 #define AIPS_MPRA_MTR1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 768 #define AIPS_MPRA_MTR1_SHIFT 26
Jasper_lee 0:b16d94660a33 769 #define AIPS_MPRA_MPL0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 770 #define AIPS_MPRA_MPL0_SHIFT 28
Jasper_lee 0:b16d94660a33 771 #define AIPS_MPRA_MTW0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 772 #define AIPS_MPRA_MTW0_SHIFT 29
Jasper_lee 0:b16d94660a33 773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 774 #define AIPS_MPRA_MTR0_SHIFT 30
Jasper_lee 0:b16d94660a33 775 /* PACRA Bit Fields */
Jasper_lee 0:b16d94660a33 776 #define AIPS_PACRA_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 777 #define AIPS_PACRA_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 778 #define AIPS_PACRA_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 779 #define AIPS_PACRA_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 780 #define AIPS_PACRA_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 781 #define AIPS_PACRA_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 782 #define AIPS_PACRA_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 783 #define AIPS_PACRA_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 784 #define AIPS_PACRA_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 785 #define AIPS_PACRA_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 786 #define AIPS_PACRA_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 787 #define AIPS_PACRA_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 788 #define AIPS_PACRA_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 789 #define AIPS_PACRA_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 790 #define AIPS_PACRA_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 791 #define AIPS_PACRA_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 792 #define AIPS_PACRA_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 793 #define AIPS_PACRA_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 794 #define AIPS_PACRA_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 795 #define AIPS_PACRA_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 796 #define AIPS_PACRA_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 797 #define AIPS_PACRA_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 798 #define AIPS_PACRA_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 799 #define AIPS_PACRA_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 800 #define AIPS_PACRA_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 801 #define AIPS_PACRA_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 802 #define AIPS_PACRA_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 803 #define AIPS_PACRA_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 804 #define AIPS_PACRA_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 805 #define AIPS_PACRA_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 806 #define AIPS_PACRA_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 807 #define AIPS_PACRA_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 808 #define AIPS_PACRA_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 809 #define AIPS_PACRA_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 810 #define AIPS_PACRA_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 811 #define AIPS_PACRA_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 812 #define AIPS_PACRA_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 813 #define AIPS_PACRA_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 814 #define AIPS_PACRA_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 815 #define AIPS_PACRA_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 816 #define AIPS_PACRA_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 817 #define AIPS_PACRA_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 818 #define AIPS_PACRA_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 819 #define AIPS_PACRA_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 820 #define AIPS_PACRA_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 821 #define AIPS_PACRA_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 822 #define AIPS_PACRA_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 823 #define AIPS_PACRA_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 824 /* PACRB Bit Fields */
Jasper_lee 0:b16d94660a33 825 #define AIPS_PACRB_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 826 #define AIPS_PACRB_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 827 #define AIPS_PACRB_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 828 #define AIPS_PACRB_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 829 #define AIPS_PACRB_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 830 #define AIPS_PACRB_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 831 #define AIPS_PACRB_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 832 #define AIPS_PACRB_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 833 #define AIPS_PACRB_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 834 #define AIPS_PACRB_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 835 #define AIPS_PACRB_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 836 #define AIPS_PACRB_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 837 #define AIPS_PACRB_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 838 #define AIPS_PACRB_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 839 #define AIPS_PACRB_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 840 #define AIPS_PACRB_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 841 #define AIPS_PACRB_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 842 #define AIPS_PACRB_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 843 #define AIPS_PACRB_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 844 #define AIPS_PACRB_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 845 #define AIPS_PACRB_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 846 #define AIPS_PACRB_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 847 #define AIPS_PACRB_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 848 #define AIPS_PACRB_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 849 #define AIPS_PACRB_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 850 #define AIPS_PACRB_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 851 #define AIPS_PACRB_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 852 #define AIPS_PACRB_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 853 #define AIPS_PACRB_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 854 #define AIPS_PACRB_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 855 #define AIPS_PACRB_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 856 #define AIPS_PACRB_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 857 #define AIPS_PACRB_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 858 #define AIPS_PACRB_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 859 #define AIPS_PACRB_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 860 #define AIPS_PACRB_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 861 #define AIPS_PACRB_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 862 #define AIPS_PACRB_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 863 #define AIPS_PACRB_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 864 #define AIPS_PACRB_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 865 #define AIPS_PACRB_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 866 #define AIPS_PACRB_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 867 #define AIPS_PACRB_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 868 #define AIPS_PACRB_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 869 #define AIPS_PACRB_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 870 #define AIPS_PACRB_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 871 #define AIPS_PACRB_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 872 #define AIPS_PACRB_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 873 /* PACRC Bit Fields */
Jasper_lee 0:b16d94660a33 874 #define AIPS_PACRC_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 875 #define AIPS_PACRC_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 876 #define AIPS_PACRC_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 877 #define AIPS_PACRC_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 878 #define AIPS_PACRC_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 879 #define AIPS_PACRC_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 880 #define AIPS_PACRC_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 881 #define AIPS_PACRC_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 882 #define AIPS_PACRC_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 883 #define AIPS_PACRC_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 884 #define AIPS_PACRC_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 885 #define AIPS_PACRC_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 886 #define AIPS_PACRC_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 887 #define AIPS_PACRC_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 888 #define AIPS_PACRC_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 889 #define AIPS_PACRC_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 890 #define AIPS_PACRC_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 891 #define AIPS_PACRC_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 892 #define AIPS_PACRC_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 893 #define AIPS_PACRC_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 894 #define AIPS_PACRC_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 895 #define AIPS_PACRC_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 896 #define AIPS_PACRC_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 897 #define AIPS_PACRC_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 898 #define AIPS_PACRC_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 899 #define AIPS_PACRC_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 900 #define AIPS_PACRC_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 901 #define AIPS_PACRC_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 902 #define AIPS_PACRC_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 903 #define AIPS_PACRC_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 904 #define AIPS_PACRC_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 905 #define AIPS_PACRC_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 906 #define AIPS_PACRC_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 907 #define AIPS_PACRC_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 908 #define AIPS_PACRC_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 909 #define AIPS_PACRC_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 910 #define AIPS_PACRC_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 911 #define AIPS_PACRC_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 912 #define AIPS_PACRC_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 913 #define AIPS_PACRC_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 914 #define AIPS_PACRC_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 915 #define AIPS_PACRC_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 916 #define AIPS_PACRC_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 917 #define AIPS_PACRC_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 918 #define AIPS_PACRC_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 919 #define AIPS_PACRC_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 920 #define AIPS_PACRC_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 921 #define AIPS_PACRC_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 922 /* PACRD Bit Fields */
Jasper_lee 0:b16d94660a33 923 #define AIPS_PACRD_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 924 #define AIPS_PACRD_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 925 #define AIPS_PACRD_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 926 #define AIPS_PACRD_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 927 #define AIPS_PACRD_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 928 #define AIPS_PACRD_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 929 #define AIPS_PACRD_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 930 #define AIPS_PACRD_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 931 #define AIPS_PACRD_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 932 #define AIPS_PACRD_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 933 #define AIPS_PACRD_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 934 #define AIPS_PACRD_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 935 #define AIPS_PACRD_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 936 #define AIPS_PACRD_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 937 #define AIPS_PACRD_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 938 #define AIPS_PACRD_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 939 #define AIPS_PACRD_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 940 #define AIPS_PACRD_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 941 #define AIPS_PACRD_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 942 #define AIPS_PACRD_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 943 #define AIPS_PACRD_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 944 #define AIPS_PACRD_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 945 #define AIPS_PACRD_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 946 #define AIPS_PACRD_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 947 #define AIPS_PACRD_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 948 #define AIPS_PACRD_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 949 #define AIPS_PACRD_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 950 #define AIPS_PACRD_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 951 #define AIPS_PACRD_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 952 #define AIPS_PACRD_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 953 #define AIPS_PACRD_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 954 #define AIPS_PACRD_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 955 #define AIPS_PACRD_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 956 #define AIPS_PACRD_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 957 #define AIPS_PACRD_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 958 #define AIPS_PACRD_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 959 #define AIPS_PACRD_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 960 #define AIPS_PACRD_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 961 #define AIPS_PACRD_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 962 #define AIPS_PACRD_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 963 #define AIPS_PACRD_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 964 #define AIPS_PACRD_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 965 #define AIPS_PACRD_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 966 #define AIPS_PACRD_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 967 #define AIPS_PACRD_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 968 #define AIPS_PACRD_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 969 #define AIPS_PACRD_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 970 #define AIPS_PACRD_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 971 /* PACRE Bit Fields */
Jasper_lee 0:b16d94660a33 972 #define AIPS_PACRE_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 973 #define AIPS_PACRE_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 974 #define AIPS_PACRE_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 975 #define AIPS_PACRE_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 976 #define AIPS_PACRE_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 977 #define AIPS_PACRE_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 978 #define AIPS_PACRE_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 979 #define AIPS_PACRE_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 980 #define AIPS_PACRE_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 981 #define AIPS_PACRE_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 982 #define AIPS_PACRE_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 983 #define AIPS_PACRE_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 984 #define AIPS_PACRE_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 985 #define AIPS_PACRE_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 986 #define AIPS_PACRE_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 987 #define AIPS_PACRE_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 988 #define AIPS_PACRE_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 989 #define AIPS_PACRE_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 990 #define AIPS_PACRE_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 991 #define AIPS_PACRE_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 992 #define AIPS_PACRE_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 993 #define AIPS_PACRE_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 994 #define AIPS_PACRE_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 995 #define AIPS_PACRE_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 996 #define AIPS_PACRE_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 997 #define AIPS_PACRE_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 998 #define AIPS_PACRE_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 999 #define AIPS_PACRE_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1000 #define AIPS_PACRE_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1001 #define AIPS_PACRE_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1002 #define AIPS_PACRE_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1003 #define AIPS_PACRE_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1004 #define AIPS_PACRE_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1005 #define AIPS_PACRE_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1006 #define AIPS_PACRE_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1007 #define AIPS_PACRE_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1008 #define AIPS_PACRE_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1009 #define AIPS_PACRE_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1010 #define AIPS_PACRE_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1011 #define AIPS_PACRE_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1012 #define AIPS_PACRE_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1013 #define AIPS_PACRE_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1014 #define AIPS_PACRE_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1015 #define AIPS_PACRE_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1016 #define AIPS_PACRE_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1017 #define AIPS_PACRE_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1018 #define AIPS_PACRE_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1019 #define AIPS_PACRE_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1020 /* PACRF Bit Fields */
Jasper_lee 0:b16d94660a33 1021 #define AIPS_PACRF_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1022 #define AIPS_PACRF_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1023 #define AIPS_PACRF_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1024 #define AIPS_PACRF_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1025 #define AIPS_PACRF_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1026 #define AIPS_PACRF_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1027 #define AIPS_PACRF_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1028 #define AIPS_PACRF_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1029 #define AIPS_PACRF_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1030 #define AIPS_PACRF_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1031 #define AIPS_PACRF_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1032 #define AIPS_PACRF_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1033 #define AIPS_PACRF_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1034 #define AIPS_PACRF_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1035 #define AIPS_PACRF_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1036 #define AIPS_PACRF_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1037 #define AIPS_PACRF_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1038 #define AIPS_PACRF_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1039 #define AIPS_PACRF_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1040 #define AIPS_PACRF_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1041 #define AIPS_PACRF_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1042 #define AIPS_PACRF_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1043 #define AIPS_PACRF_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1044 #define AIPS_PACRF_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1045 #define AIPS_PACRF_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1046 #define AIPS_PACRF_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1047 #define AIPS_PACRF_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1048 #define AIPS_PACRF_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1049 #define AIPS_PACRF_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1050 #define AIPS_PACRF_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1051 #define AIPS_PACRF_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1052 #define AIPS_PACRF_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1053 #define AIPS_PACRF_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1054 #define AIPS_PACRF_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1055 #define AIPS_PACRF_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1056 #define AIPS_PACRF_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1057 #define AIPS_PACRF_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1058 #define AIPS_PACRF_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1059 #define AIPS_PACRF_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1060 #define AIPS_PACRF_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1061 #define AIPS_PACRF_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1062 #define AIPS_PACRF_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1063 #define AIPS_PACRF_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1064 #define AIPS_PACRF_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1065 #define AIPS_PACRF_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1066 #define AIPS_PACRF_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1067 #define AIPS_PACRF_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1068 #define AIPS_PACRF_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1069 /* PACRG Bit Fields */
Jasper_lee 0:b16d94660a33 1070 #define AIPS_PACRG_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1071 #define AIPS_PACRG_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1072 #define AIPS_PACRG_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1073 #define AIPS_PACRG_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1074 #define AIPS_PACRG_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1075 #define AIPS_PACRG_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1076 #define AIPS_PACRG_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1077 #define AIPS_PACRG_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1078 #define AIPS_PACRG_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1079 #define AIPS_PACRG_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1080 #define AIPS_PACRG_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1081 #define AIPS_PACRG_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1082 #define AIPS_PACRG_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1083 #define AIPS_PACRG_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1084 #define AIPS_PACRG_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1085 #define AIPS_PACRG_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1086 #define AIPS_PACRG_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1087 #define AIPS_PACRG_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1088 #define AIPS_PACRG_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1089 #define AIPS_PACRG_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1090 #define AIPS_PACRG_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1091 #define AIPS_PACRG_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1092 #define AIPS_PACRG_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1093 #define AIPS_PACRG_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1094 #define AIPS_PACRG_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1095 #define AIPS_PACRG_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1096 #define AIPS_PACRG_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1097 #define AIPS_PACRG_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1098 #define AIPS_PACRG_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1099 #define AIPS_PACRG_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1100 #define AIPS_PACRG_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1101 #define AIPS_PACRG_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1102 #define AIPS_PACRG_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1103 #define AIPS_PACRG_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1104 #define AIPS_PACRG_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1105 #define AIPS_PACRG_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1106 #define AIPS_PACRG_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1107 #define AIPS_PACRG_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1108 #define AIPS_PACRG_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1109 #define AIPS_PACRG_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1110 #define AIPS_PACRG_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1111 #define AIPS_PACRG_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1112 #define AIPS_PACRG_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1113 #define AIPS_PACRG_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1114 #define AIPS_PACRG_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1115 #define AIPS_PACRG_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1116 #define AIPS_PACRG_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1117 #define AIPS_PACRG_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1118 /* PACRH Bit Fields */
Jasper_lee 0:b16d94660a33 1119 #define AIPS_PACRH_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1120 #define AIPS_PACRH_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1121 #define AIPS_PACRH_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1122 #define AIPS_PACRH_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1123 #define AIPS_PACRH_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1124 #define AIPS_PACRH_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1125 #define AIPS_PACRH_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1126 #define AIPS_PACRH_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1127 #define AIPS_PACRH_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1128 #define AIPS_PACRH_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1129 #define AIPS_PACRH_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1130 #define AIPS_PACRH_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1131 #define AIPS_PACRH_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1132 #define AIPS_PACRH_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1133 #define AIPS_PACRH_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1134 #define AIPS_PACRH_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1135 #define AIPS_PACRH_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1136 #define AIPS_PACRH_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1137 #define AIPS_PACRH_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1138 #define AIPS_PACRH_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1139 #define AIPS_PACRH_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1140 #define AIPS_PACRH_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1141 #define AIPS_PACRH_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1142 #define AIPS_PACRH_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1143 #define AIPS_PACRH_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1144 #define AIPS_PACRH_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1145 #define AIPS_PACRH_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1146 #define AIPS_PACRH_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1147 #define AIPS_PACRH_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1148 #define AIPS_PACRH_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1149 #define AIPS_PACRH_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1150 #define AIPS_PACRH_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1151 #define AIPS_PACRH_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1152 #define AIPS_PACRH_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1153 #define AIPS_PACRH_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1154 #define AIPS_PACRH_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1155 #define AIPS_PACRH_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1156 #define AIPS_PACRH_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1157 #define AIPS_PACRH_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1158 #define AIPS_PACRH_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1159 #define AIPS_PACRH_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1160 #define AIPS_PACRH_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1161 #define AIPS_PACRH_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1162 #define AIPS_PACRH_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1163 #define AIPS_PACRH_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1164 #define AIPS_PACRH_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1165 #define AIPS_PACRH_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1166 #define AIPS_PACRH_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1167 /* PACRI Bit Fields */
Jasper_lee 0:b16d94660a33 1168 #define AIPS_PACRI_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1169 #define AIPS_PACRI_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1170 #define AIPS_PACRI_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1171 #define AIPS_PACRI_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1172 #define AIPS_PACRI_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1173 #define AIPS_PACRI_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1174 #define AIPS_PACRI_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1175 #define AIPS_PACRI_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1176 #define AIPS_PACRI_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1177 #define AIPS_PACRI_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1178 #define AIPS_PACRI_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1179 #define AIPS_PACRI_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1180 #define AIPS_PACRI_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1181 #define AIPS_PACRI_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1182 #define AIPS_PACRI_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1183 #define AIPS_PACRI_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1184 #define AIPS_PACRI_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1185 #define AIPS_PACRI_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1186 #define AIPS_PACRI_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1187 #define AIPS_PACRI_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1188 #define AIPS_PACRI_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1189 #define AIPS_PACRI_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1190 #define AIPS_PACRI_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1191 #define AIPS_PACRI_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1192 #define AIPS_PACRI_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1193 #define AIPS_PACRI_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1194 #define AIPS_PACRI_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1195 #define AIPS_PACRI_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1196 #define AIPS_PACRI_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1197 #define AIPS_PACRI_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1198 #define AIPS_PACRI_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1199 #define AIPS_PACRI_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1200 #define AIPS_PACRI_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1201 #define AIPS_PACRI_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1202 #define AIPS_PACRI_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1203 #define AIPS_PACRI_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1204 #define AIPS_PACRI_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1205 #define AIPS_PACRI_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1206 #define AIPS_PACRI_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1207 #define AIPS_PACRI_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1208 #define AIPS_PACRI_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1209 #define AIPS_PACRI_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1210 #define AIPS_PACRI_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1211 #define AIPS_PACRI_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1212 #define AIPS_PACRI_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1213 #define AIPS_PACRI_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1214 #define AIPS_PACRI_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1215 #define AIPS_PACRI_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1216 /* PACRJ Bit Fields */
Jasper_lee 0:b16d94660a33 1217 #define AIPS_PACRJ_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1218 #define AIPS_PACRJ_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1219 #define AIPS_PACRJ_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1220 #define AIPS_PACRJ_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1221 #define AIPS_PACRJ_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1222 #define AIPS_PACRJ_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1223 #define AIPS_PACRJ_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1224 #define AIPS_PACRJ_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1225 #define AIPS_PACRJ_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1226 #define AIPS_PACRJ_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1227 #define AIPS_PACRJ_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1228 #define AIPS_PACRJ_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1229 #define AIPS_PACRJ_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1230 #define AIPS_PACRJ_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1231 #define AIPS_PACRJ_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1232 #define AIPS_PACRJ_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1233 #define AIPS_PACRJ_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1234 #define AIPS_PACRJ_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1235 #define AIPS_PACRJ_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1236 #define AIPS_PACRJ_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1237 #define AIPS_PACRJ_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1238 #define AIPS_PACRJ_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1239 #define AIPS_PACRJ_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1240 #define AIPS_PACRJ_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1241 #define AIPS_PACRJ_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1242 #define AIPS_PACRJ_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1243 #define AIPS_PACRJ_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1244 #define AIPS_PACRJ_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1245 #define AIPS_PACRJ_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1246 #define AIPS_PACRJ_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1247 #define AIPS_PACRJ_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1248 #define AIPS_PACRJ_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1249 #define AIPS_PACRJ_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1250 #define AIPS_PACRJ_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1251 #define AIPS_PACRJ_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1252 #define AIPS_PACRJ_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1253 #define AIPS_PACRJ_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1254 #define AIPS_PACRJ_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1255 #define AIPS_PACRJ_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1256 #define AIPS_PACRJ_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1257 #define AIPS_PACRJ_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1258 #define AIPS_PACRJ_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1259 #define AIPS_PACRJ_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1260 #define AIPS_PACRJ_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1261 #define AIPS_PACRJ_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1262 #define AIPS_PACRJ_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1263 #define AIPS_PACRJ_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1264 #define AIPS_PACRJ_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1265 /* PACRK Bit Fields */
Jasper_lee 0:b16d94660a33 1266 #define AIPS_PACRK_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1267 #define AIPS_PACRK_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1268 #define AIPS_PACRK_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1269 #define AIPS_PACRK_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1270 #define AIPS_PACRK_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1271 #define AIPS_PACRK_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1272 #define AIPS_PACRK_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1273 #define AIPS_PACRK_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1274 #define AIPS_PACRK_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1275 #define AIPS_PACRK_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1276 #define AIPS_PACRK_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1277 #define AIPS_PACRK_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1278 #define AIPS_PACRK_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1279 #define AIPS_PACRK_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1280 #define AIPS_PACRK_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1281 #define AIPS_PACRK_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1282 #define AIPS_PACRK_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1283 #define AIPS_PACRK_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1284 #define AIPS_PACRK_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1285 #define AIPS_PACRK_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1286 #define AIPS_PACRK_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1287 #define AIPS_PACRK_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1288 #define AIPS_PACRK_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1289 #define AIPS_PACRK_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1290 #define AIPS_PACRK_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1291 #define AIPS_PACRK_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1292 #define AIPS_PACRK_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1293 #define AIPS_PACRK_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1294 #define AIPS_PACRK_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1295 #define AIPS_PACRK_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1296 #define AIPS_PACRK_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1297 #define AIPS_PACRK_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1298 #define AIPS_PACRK_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1299 #define AIPS_PACRK_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1300 #define AIPS_PACRK_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1301 #define AIPS_PACRK_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1302 #define AIPS_PACRK_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1303 #define AIPS_PACRK_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1304 #define AIPS_PACRK_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1305 #define AIPS_PACRK_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1306 #define AIPS_PACRK_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1307 #define AIPS_PACRK_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1308 #define AIPS_PACRK_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1309 #define AIPS_PACRK_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1310 #define AIPS_PACRK_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1311 #define AIPS_PACRK_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1312 #define AIPS_PACRK_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1313 #define AIPS_PACRK_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1314 /* PACRL Bit Fields */
Jasper_lee 0:b16d94660a33 1315 #define AIPS_PACRL_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1316 #define AIPS_PACRL_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1317 #define AIPS_PACRL_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1318 #define AIPS_PACRL_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1319 #define AIPS_PACRL_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1320 #define AIPS_PACRL_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1321 #define AIPS_PACRL_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1322 #define AIPS_PACRL_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1323 #define AIPS_PACRL_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1324 #define AIPS_PACRL_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1325 #define AIPS_PACRL_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1326 #define AIPS_PACRL_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1327 #define AIPS_PACRL_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1328 #define AIPS_PACRL_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1329 #define AIPS_PACRL_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1330 #define AIPS_PACRL_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1331 #define AIPS_PACRL_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1332 #define AIPS_PACRL_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1333 #define AIPS_PACRL_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1334 #define AIPS_PACRL_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1335 #define AIPS_PACRL_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1336 #define AIPS_PACRL_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1337 #define AIPS_PACRL_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1338 #define AIPS_PACRL_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1339 #define AIPS_PACRL_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1340 #define AIPS_PACRL_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1341 #define AIPS_PACRL_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1342 #define AIPS_PACRL_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1343 #define AIPS_PACRL_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1344 #define AIPS_PACRL_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1345 #define AIPS_PACRL_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1346 #define AIPS_PACRL_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1347 #define AIPS_PACRL_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1348 #define AIPS_PACRL_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1349 #define AIPS_PACRL_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1350 #define AIPS_PACRL_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1351 #define AIPS_PACRL_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1352 #define AIPS_PACRL_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1353 #define AIPS_PACRL_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1354 #define AIPS_PACRL_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1355 #define AIPS_PACRL_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1356 #define AIPS_PACRL_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1357 #define AIPS_PACRL_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1358 #define AIPS_PACRL_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1359 #define AIPS_PACRL_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1360 #define AIPS_PACRL_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1361 #define AIPS_PACRL_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1362 #define AIPS_PACRL_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1363 /* PACRM Bit Fields */
Jasper_lee 0:b16d94660a33 1364 #define AIPS_PACRM_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1365 #define AIPS_PACRM_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1366 #define AIPS_PACRM_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1367 #define AIPS_PACRM_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1368 #define AIPS_PACRM_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1369 #define AIPS_PACRM_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1370 #define AIPS_PACRM_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1371 #define AIPS_PACRM_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1372 #define AIPS_PACRM_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1373 #define AIPS_PACRM_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1374 #define AIPS_PACRM_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1375 #define AIPS_PACRM_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1376 #define AIPS_PACRM_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1377 #define AIPS_PACRM_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1378 #define AIPS_PACRM_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1379 #define AIPS_PACRM_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1380 #define AIPS_PACRM_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1381 #define AIPS_PACRM_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1382 #define AIPS_PACRM_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1383 #define AIPS_PACRM_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1384 #define AIPS_PACRM_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1385 #define AIPS_PACRM_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1386 #define AIPS_PACRM_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1387 #define AIPS_PACRM_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1388 #define AIPS_PACRM_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1389 #define AIPS_PACRM_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1390 #define AIPS_PACRM_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1391 #define AIPS_PACRM_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1392 #define AIPS_PACRM_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1393 #define AIPS_PACRM_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1394 #define AIPS_PACRM_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1395 #define AIPS_PACRM_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1396 #define AIPS_PACRM_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1397 #define AIPS_PACRM_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1398 #define AIPS_PACRM_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1399 #define AIPS_PACRM_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1400 #define AIPS_PACRM_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1401 #define AIPS_PACRM_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1402 #define AIPS_PACRM_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1403 #define AIPS_PACRM_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1404 #define AIPS_PACRM_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1405 #define AIPS_PACRM_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1406 #define AIPS_PACRM_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1407 #define AIPS_PACRM_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1408 #define AIPS_PACRM_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1409 #define AIPS_PACRM_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1410 #define AIPS_PACRM_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1411 #define AIPS_PACRM_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1412 /* PACRN Bit Fields */
Jasper_lee 0:b16d94660a33 1413 #define AIPS_PACRN_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1414 #define AIPS_PACRN_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1415 #define AIPS_PACRN_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1416 #define AIPS_PACRN_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1417 #define AIPS_PACRN_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1418 #define AIPS_PACRN_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1419 #define AIPS_PACRN_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1420 #define AIPS_PACRN_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1421 #define AIPS_PACRN_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1422 #define AIPS_PACRN_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1423 #define AIPS_PACRN_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1424 #define AIPS_PACRN_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1425 #define AIPS_PACRN_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1426 #define AIPS_PACRN_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1427 #define AIPS_PACRN_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1428 #define AIPS_PACRN_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1429 #define AIPS_PACRN_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1430 #define AIPS_PACRN_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1431 #define AIPS_PACRN_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1432 #define AIPS_PACRN_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1433 #define AIPS_PACRN_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1434 #define AIPS_PACRN_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1435 #define AIPS_PACRN_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1436 #define AIPS_PACRN_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1437 #define AIPS_PACRN_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1438 #define AIPS_PACRN_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1439 #define AIPS_PACRN_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1440 #define AIPS_PACRN_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1441 #define AIPS_PACRN_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1442 #define AIPS_PACRN_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1443 #define AIPS_PACRN_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1444 #define AIPS_PACRN_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1445 #define AIPS_PACRN_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1446 #define AIPS_PACRN_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1447 #define AIPS_PACRN_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1448 #define AIPS_PACRN_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1449 #define AIPS_PACRN_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1450 #define AIPS_PACRN_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1451 #define AIPS_PACRN_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1452 #define AIPS_PACRN_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1453 #define AIPS_PACRN_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1454 #define AIPS_PACRN_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1455 #define AIPS_PACRN_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1456 #define AIPS_PACRN_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1457 #define AIPS_PACRN_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1458 #define AIPS_PACRN_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1459 #define AIPS_PACRN_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1460 #define AIPS_PACRN_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1461 /* PACRO Bit Fields */
Jasper_lee 0:b16d94660a33 1462 #define AIPS_PACRO_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1463 #define AIPS_PACRO_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1464 #define AIPS_PACRO_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1465 #define AIPS_PACRO_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1466 #define AIPS_PACRO_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1467 #define AIPS_PACRO_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1468 #define AIPS_PACRO_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1469 #define AIPS_PACRO_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1470 #define AIPS_PACRO_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1471 #define AIPS_PACRO_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1472 #define AIPS_PACRO_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1473 #define AIPS_PACRO_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1474 #define AIPS_PACRO_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1475 #define AIPS_PACRO_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1476 #define AIPS_PACRO_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1477 #define AIPS_PACRO_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1478 #define AIPS_PACRO_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1479 #define AIPS_PACRO_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1480 #define AIPS_PACRO_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1481 #define AIPS_PACRO_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1482 #define AIPS_PACRO_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1483 #define AIPS_PACRO_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1484 #define AIPS_PACRO_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1485 #define AIPS_PACRO_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1486 #define AIPS_PACRO_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1487 #define AIPS_PACRO_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1488 #define AIPS_PACRO_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1489 #define AIPS_PACRO_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1490 #define AIPS_PACRO_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1491 #define AIPS_PACRO_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1492 #define AIPS_PACRO_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1493 #define AIPS_PACRO_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1494 #define AIPS_PACRO_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1495 #define AIPS_PACRO_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1496 #define AIPS_PACRO_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1497 #define AIPS_PACRO_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1498 #define AIPS_PACRO_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1499 #define AIPS_PACRO_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1500 #define AIPS_PACRO_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1501 #define AIPS_PACRO_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1502 #define AIPS_PACRO_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1503 #define AIPS_PACRO_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1504 #define AIPS_PACRO_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1505 #define AIPS_PACRO_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1506 #define AIPS_PACRO_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1507 #define AIPS_PACRO_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1508 #define AIPS_PACRO_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1509 #define AIPS_PACRO_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1510 /* PACRP Bit Fields */
Jasper_lee 0:b16d94660a33 1511 #define AIPS_PACRP_TP7_MASK 0x1u
Jasper_lee 0:b16d94660a33 1512 #define AIPS_PACRP_TP7_SHIFT 0
Jasper_lee 0:b16d94660a33 1513 #define AIPS_PACRP_WP7_MASK 0x2u
Jasper_lee 0:b16d94660a33 1514 #define AIPS_PACRP_WP7_SHIFT 1
Jasper_lee 0:b16d94660a33 1515 #define AIPS_PACRP_SP7_MASK 0x4u
Jasper_lee 0:b16d94660a33 1516 #define AIPS_PACRP_SP7_SHIFT 2
Jasper_lee 0:b16d94660a33 1517 #define AIPS_PACRP_TP6_MASK 0x10u
Jasper_lee 0:b16d94660a33 1518 #define AIPS_PACRP_TP6_SHIFT 4
Jasper_lee 0:b16d94660a33 1519 #define AIPS_PACRP_WP6_MASK 0x20u
Jasper_lee 0:b16d94660a33 1520 #define AIPS_PACRP_WP6_SHIFT 5
Jasper_lee 0:b16d94660a33 1521 #define AIPS_PACRP_SP6_MASK 0x40u
Jasper_lee 0:b16d94660a33 1522 #define AIPS_PACRP_SP6_SHIFT 6
Jasper_lee 0:b16d94660a33 1523 #define AIPS_PACRP_TP5_MASK 0x100u
Jasper_lee 0:b16d94660a33 1524 #define AIPS_PACRP_TP5_SHIFT 8
Jasper_lee 0:b16d94660a33 1525 #define AIPS_PACRP_WP5_MASK 0x200u
Jasper_lee 0:b16d94660a33 1526 #define AIPS_PACRP_WP5_SHIFT 9
Jasper_lee 0:b16d94660a33 1527 #define AIPS_PACRP_SP5_MASK 0x400u
Jasper_lee 0:b16d94660a33 1528 #define AIPS_PACRP_SP5_SHIFT 10
Jasper_lee 0:b16d94660a33 1529 #define AIPS_PACRP_TP4_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1530 #define AIPS_PACRP_TP4_SHIFT 12
Jasper_lee 0:b16d94660a33 1531 #define AIPS_PACRP_WP4_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1532 #define AIPS_PACRP_WP4_SHIFT 13
Jasper_lee 0:b16d94660a33 1533 #define AIPS_PACRP_SP4_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1534 #define AIPS_PACRP_SP4_SHIFT 14
Jasper_lee 0:b16d94660a33 1535 #define AIPS_PACRP_TP3_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1536 #define AIPS_PACRP_TP3_SHIFT 16
Jasper_lee 0:b16d94660a33 1537 #define AIPS_PACRP_WP3_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1538 #define AIPS_PACRP_WP3_SHIFT 17
Jasper_lee 0:b16d94660a33 1539 #define AIPS_PACRP_SP3_MASK 0x40000u
Jasper_lee 0:b16d94660a33 1540 #define AIPS_PACRP_SP3_SHIFT 18
Jasper_lee 0:b16d94660a33 1541 #define AIPS_PACRP_TP2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1542 #define AIPS_PACRP_TP2_SHIFT 20
Jasper_lee 0:b16d94660a33 1543 #define AIPS_PACRP_WP2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1544 #define AIPS_PACRP_WP2_SHIFT 21
Jasper_lee 0:b16d94660a33 1545 #define AIPS_PACRP_SP2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1546 #define AIPS_PACRP_SP2_SHIFT 22
Jasper_lee 0:b16d94660a33 1547 #define AIPS_PACRP_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1548 #define AIPS_PACRP_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1549 #define AIPS_PACRP_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1550 #define AIPS_PACRP_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1551 #define AIPS_PACRP_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1552 #define AIPS_PACRP_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1553 #define AIPS_PACRP_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1554 #define AIPS_PACRP_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1555 #define AIPS_PACRP_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1556 #define AIPS_PACRP_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1557 #define AIPS_PACRP_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1558 #define AIPS_PACRP_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1559 /* PACRU Bit Fields */
Jasper_lee 0:b16d94660a33 1560 #define AIPS_PACRU_TP1_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1561 #define AIPS_PACRU_TP1_SHIFT 24
Jasper_lee 0:b16d94660a33 1562 #define AIPS_PACRU_WP1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1563 #define AIPS_PACRU_WP1_SHIFT 25
Jasper_lee 0:b16d94660a33 1564 #define AIPS_PACRU_SP1_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1565 #define AIPS_PACRU_SP1_SHIFT 26
Jasper_lee 0:b16d94660a33 1566 #define AIPS_PACRU_TP0_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1567 #define AIPS_PACRU_TP0_SHIFT 28
Jasper_lee 0:b16d94660a33 1568 #define AIPS_PACRU_WP0_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1569 #define AIPS_PACRU_WP0_SHIFT 29
Jasper_lee 0:b16d94660a33 1570 #define AIPS_PACRU_SP0_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1571 #define AIPS_PACRU_SP0_SHIFT 30
Jasper_lee 0:b16d94660a33 1572
Jasper_lee 0:b16d94660a33 1573 /*!
Jasper_lee 0:b16d94660a33 1574 * @}
Jasper_lee 0:b16d94660a33 1575 */ /* end of group AIPS_Register_Masks */
Jasper_lee 0:b16d94660a33 1576
Jasper_lee 0:b16d94660a33 1577
Jasper_lee 0:b16d94660a33 1578 /* AIPS - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 1579 /** Peripheral AIPS0 base address */
Jasper_lee 0:b16d94660a33 1580 #define AIPS0_BASE (0x40000000u)
Jasper_lee 0:b16d94660a33 1581 /** Peripheral AIPS0 base pointer */
Jasper_lee 0:b16d94660a33 1582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
Jasper_lee 0:b16d94660a33 1583 #define AIPS0_BASE_PTR (AIPS0)
Jasper_lee 0:b16d94660a33 1584 /** Peripheral AIPS1 base address */
Jasper_lee 0:b16d94660a33 1585 #define AIPS1_BASE (0x40080000u)
Jasper_lee 0:b16d94660a33 1586 /** Peripheral AIPS1 base pointer */
Jasper_lee 0:b16d94660a33 1587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
Jasper_lee 0:b16d94660a33 1588 #define AIPS1_BASE_PTR (AIPS1)
Jasper_lee 0:b16d94660a33 1589 /** Array initializer of AIPS peripheral base addresses */
Jasper_lee 0:b16d94660a33 1590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
Jasper_lee 0:b16d94660a33 1591 /** Array initializer of AIPS peripheral base pointers */
Jasper_lee 0:b16d94660a33 1592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
Jasper_lee 0:b16d94660a33 1593
Jasper_lee 0:b16d94660a33 1594 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1595 -- AIPS - Register accessor macros
Jasper_lee 0:b16d94660a33 1596 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1597
Jasper_lee 0:b16d94660a33 1598 /*!
Jasper_lee 0:b16d94660a33 1599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
Jasper_lee 0:b16d94660a33 1600 * @{
Jasper_lee 0:b16d94660a33 1601 */
Jasper_lee 0:b16d94660a33 1602
Jasper_lee 0:b16d94660a33 1603
Jasper_lee 0:b16d94660a33 1604 /* AIPS - Register instance definitions */
Jasper_lee 0:b16d94660a33 1605 /* AIPS0 */
Jasper_lee 0:b16d94660a33 1606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
Jasper_lee 0:b16d94660a33 1624 /* AIPS1 */
Jasper_lee 0:b16d94660a33 1625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
Jasper_lee 0:b16d94660a33 1643
Jasper_lee 0:b16d94660a33 1644 /*!
Jasper_lee 0:b16d94660a33 1645 * @}
Jasper_lee 0:b16d94660a33 1646 */ /* end of group AIPS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 1647
Jasper_lee 0:b16d94660a33 1648
Jasper_lee 0:b16d94660a33 1649 /*!
Jasper_lee 0:b16d94660a33 1650 * @}
Jasper_lee 0:b16d94660a33 1651 */ /* end of group AIPS_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 1652
Jasper_lee 0:b16d94660a33 1653
Jasper_lee 0:b16d94660a33 1654 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1655 -- AXBS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 1656 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1657
Jasper_lee 0:b16d94660a33 1658 /*!
Jasper_lee 0:b16d94660a33 1659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 1660 * @{
Jasper_lee 0:b16d94660a33 1661 */
Jasper_lee 0:b16d94660a33 1662
Jasper_lee 0:b16d94660a33 1663 /** AXBS - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 1664 typedef struct {
Jasper_lee 0:b16d94660a33 1665 struct { /* offset: 0x0, array step: 0x100 */
Jasper_lee 0:b16d94660a33 1666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
Jasper_lee 0:b16d94660a33 1667 uint8_t RESERVED_0[12];
Jasper_lee 0:b16d94660a33 1668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
Jasper_lee 0:b16d94660a33 1669 uint8_t RESERVED_1[236];
Jasper_lee 0:b16d94660a33 1670 } SLAVE[5];
Jasper_lee 0:b16d94660a33 1671 uint8_t RESERVED_0[768];
Jasper_lee 0:b16d94660a33 1672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
Jasper_lee 0:b16d94660a33 1673 uint8_t RESERVED_1[252];
Jasper_lee 0:b16d94660a33 1674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
Jasper_lee 0:b16d94660a33 1675 uint8_t RESERVED_2[252];
Jasper_lee 0:b16d94660a33 1676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
Jasper_lee 0:b16d94660a33 1677 uint8_t RESERVED_3[252];
Jasper_lee 0:b16d94660a33 1678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
Jasper_lee 0:b16d94660a33 1679 uint8_t RESERVED_4[252];
Jasper_lee 0:b16d94660a33 1680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
Jasper_lee 0:b16d94660a33 1681 uint8_t RESERVED_5[252];
Jasper_lee 0:b16d94660a33 1682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
Jasper_lee 0:b16d94660a33 1683 } AXBS_Type, *AXBS_MemMapPtr;
Jasper_lee 0:b16d94660a33 1684
Jasper_lee 0:b16d94660a33 1685 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1686 -- AXBS - Register accessor macros
Jasper_lee 0:b16d94660a33 1687 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1688
Jasper_lee 0:b16d94660a33 1689 /*!
Jasper_lee 0:b16d94660a33 1690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
Jasper_lee 0:b16d94660a33 1691 * @{
Jasper_lee 0:b16d94660a33 1692 */
Jasper_lee 0:b16d94660a33 1693
Jasper_lee 0:b16d94660a33 1694
Jasper_lee 0:b16d94660a33 1695 /* AXBS - Register accessors */
Jasper_lee 0:b16d94660a33 1696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
Jasper_lee 0:b16d94660a33 1697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
Jasper_lee 0:b16d94660a33 1698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
Jasper_lee 0:b16d94660a33 1699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
Jasper_lee 0:b16d94660a33 1700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
Jasper_lee 0:b16d94660a33 1701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
Jasper_lee 0:b16d94660a33 1702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
Jasper_lee 0:b16d94660a33 1703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
Jasper_lee 0:b16d94660a33 1704
Jasper_lee 0:b16d94660a33 1705 /*!
Jasper_lee 0:b16d94660a33 1706 * @}
Jasper_lee 0:b16d94660a33 1707 */ /* end of group AXBS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 1708
Jasper_lee 0:b16d94660a33 1709
Jasper_lee 0:b16d94660a33 1710 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1711 -- AXBS Register Masks
Jasper_lee 0:b16d94660a33 1712 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1713
Jasper_lee 0:b16d94660a33 1714 /*!
Jasper_lee 0:b16d94660a33 1715 * @addtogroup AXBS_Register_Masks AXBS Register Masks
Jasper_lee 0:b16d94660a33 1716 * @{
Jasper_lee 0:b16d94660a33 1717 */
Jasper_lee 0:b16d94660a33 1718
Jasper_lee 0:b16d94660a33 1719 /* PRS Bit Fields */
Jasper_lee 0:b16d94660a33 1720 #define AXBS_PRS_M0_MASK 0x7u
Jasper_lee 0:b16d94660a33 1721 #define AXBS_PRS_M0_SHIFT 0
Jasper_lee 0:b16d94660a33 1722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
Jasper_lee 0:b16d94660a33 1723 #define AXBS_PRS_M1_MASK 0x70u
Jasper_lee 0:b16d94660a33 1724 #define AXBS_PRS_M1_SHIFT 4
Jasper_lee 0:b16d94660a33 1725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
Jasper_lee 0:b16d94660a33 1726 #define AXBS_PRS_M2_MASK 0x700u
Jasper_lee 0:b16d94660a33 1727 #define AXBS_PRS_M2_SHIFT 8
Jasper_lee 0:b16d94660a33 1728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
Jasper_lee 0:b16d94660a33 1729 #define AXBS_PRS_M3_MASK 0x7000u
Jasper_lee 0:b16d94660a33 1730 #define AXBS_PRS_M3_SHIFT 12
Jasper_lee 0:b16d94660a33 1731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
Jasper_lee 0:b16d94660a33 1732 #define AXBS_PRS_M4_MASK 0x70000u
Jasper_lee 0:b16d94660a33 1733 #define AXBS_PRS_M4_SHIFT 16
Jasper_lee 0:b16d94660a33 1734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
Jasper_lee 0:b16d94660a33 1735 #define AXBS_PRS_M5_MASK 0x700000u
Jasper_lee 0:b16d94660a33 1736 #define AXBS_PRS_M5_SHIFT 20
Jasper_lee 0:b16d94660a33 1737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
Jasper_lee 0:b16d94660a33 1738 /* CRS Bit Fields */
Jasper_lee 0:b16d94660a33 1739 #define AXBS_CRS_PARK_MASK 0x7u
Jasper_lee 0:b16d94660a33 1740 #define AXBS_CRS_PARK_SHIFT 0
Jasper_lee 0:b16d94660a33 1741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
Jasper_lee 0:b16d94660a33 1742 #define AXBS_CRS_PCTL_MASK 0x30u
Jasper_lee 0:b16d94660a33 1743 #define AXBS_CRS_PCTL_SHIFT 4
Jasper_lee 0:b16d94660a33 1744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
Jasper_lee 0:b16d94660a33 1745 #define AXBS_CRS_ARB_MASK 0x300u
Jasper_lee 0:b16d94660a33 1746 #define AXBS_CRS_ARB_SHIFT 8
Jasper_lee 0:b16d94660a33 1747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
Jasper_lee 0:b16d94660a33 1748 #define AXBS_CRS_HLP_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1749 #define AXBS_CRS_HLP_SHIFT 30
Jasper_lee 0:b16d94660a33 1750 #define AXBS_CRS_RO_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 1751 #define AXBS_CRS_RO_SHIFT 31
Jasper_lee 0:b16d94660a33 1752 /* MGPCR0 Bit Fields */
Jasper_lee 0:b16d94660a33 1753 #define AXBS_MGPCR0_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1754 #define AXBS_MGPCR0_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
Jasper_lee 0:b16d94660a33 1756 /* MGPCR1 Bit Fields */
Jasper_lee 0:b16d94660a33 1757 #define AXBS_MGPCR1_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1758 #define AXBS_MGPCR1_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
Jasper_lee 0:b16d94660a33 1760 /* MGPCR2 Bit Fields */
Jasper_lee 0:b16d94660a33 1761 #define AXBS_MGPCR2_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1762 #define AXBS_MGPCR2_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
Jasper_lee 0:b16d94660a33 1764 /* MGPCR3 Bit Fields */
Jasper_lee 0:b16d94660a33 1765 #define AXBS_MGPCR3_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1766 #define AXBS_MGPCR3_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
Jasper_lee 0:b16d94660a33 1768 /* MGPCR4 Bit Fields */
Jasper_lee 0:b16d94660a33 1769 #define AXBS_MGPCR4_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1770 #define AXBS_MGPCR4_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
Jasper_lee 0:b16d94660a33 1772 /* MGPCR5 Bit Fields */
Jasper_lee 0:b16d94660a33 1773 #define AXBS_MGPCR5_AULB_MASK 0x7u
Jasper_lee 0:b16d94660a33 1774 #define AXBS_MGPCR5_AULB_SHIFT 0
Jasper_lee 0:b16d94660a33 1775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
Jasper_lee 0:b16d94660a33 1776
Jasper_lee 0:b16d94660a33 1777 /*!
Jasper_lee 0:b16d94660a33 1778 * @}
Jasper_lee 0:b16d94660a33 1779 */ /* end of group AXBS_Register_Masks */
Jasper_lee 0:b16d94660a33 1780
Jasper_lee 0:b16d94660a33 1781
Jasper_lee 0:b16d94660a33 1782 /* AXBS - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 1783 /** Peripheral AXBS base address */
Jasper_lee 0:b16d94660a33 1784 #define AXBS_BASE (0x40004000u)
Jasper_lee 0:b16d94660a33 1785 /** Peripheral AXBS base pointer */
Jasper_lee 0:b16d94660a33 1786 #define AXBS ((AXBS_Type *)AXBS_BASE)
Jasper_lee 0:b16d94660a33 1787 #define AXBS_BASE_PTR (AXBS)
Jasper_lee 0:b16d94660a33 1788 /** Array initializer of AXBS peripheral base addresses */
Jasper_lee 0:b16d94660a33 1789 #define AXBS_BASE_ADDRS { AXBS_BASE }
Jasper_lee 0:b16d94660a33 1790 /** Array initializer of AXBS peripheral base pointers */
Jasper_lee 0:b16d94660a33 1791 #define AXBS_BASE_PTRS { AXBS }
Jasper_lee 0:b16d94660a33 1792
Jasper_lee 0:b16d94660a33 1793 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1794 -- AXBS - Register accessor macros
Jasper_lee 0:b16d94660a33 1795 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1796
Jasper_lee 0:b16d94660a33 1797 /*!
Jasper_lee 0:b16d94660a33 1798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
Jasper_lee 0:b16d94660a33 1799 * @{
Jasper_lee 0:b16d94660a33 1800 */
Jasper_lee 0:b16d94660a33 1801
Jasper_lee 0:b16d94660a33 1802
Jasper_lee 0:b16d94660a33 1803 /* AXBS - Register instance definitions */
Jasper_lee 0:b16d94660a33 1804 /* AXBS */
Jasper_lee 0:b16d94660a33 1805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
Jasper_lee 0:b16d94660a33 1806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
Jasper_lee 0:b16d94660a33 1807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
Jasper_lee 0:b16d94660a33 1808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
Jasper_lee 0:b16d94660a33 1809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
Jasper_lee 0:b16d94660a33 1810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
Jasper_lee 0:b16d94660a33 1811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
Jasper_lee 0:b16d94660a33 1812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
Jasper_lee 0:b16d94660a33 1813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
Jasper_lee 0:b16d94660a33 1814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
Jasper_lee 0:b16d94660a33 1815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
Jasper_lee 0:b16d94660a33 1816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
Jasper_lee 0:b16d94660a33 1817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
Jasper_lee 0:b16d94660a33 1818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
Jasper_lee 0:b16d94660a33 1819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
Jasper_lee 0:b16d94660a33 1820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
Jasper_lee 0:b16d94660a33 1821
Jasper_lee 0:b16d94660a33 1822 /* AXBS - Register array accessors */
Jasper_lee 0:b16d94660a33 1823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
Jasper_lee 0:b16d94660a33 1824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
Jasper_lee 0:b16d94660a33 1825
Jasper_lee 0:b16d94660a33 1826 /*!
Jasper_lee 0:b16d94660a33 1827 * @}
Jasper_lee 0:b16d94660a33 1828 */ /* end of group AXBS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 1829
Jasper_lee 0:b16d94660a33 1830
Jasper_lee 0:b16d94660a33 1831 /*!
Jasper_lee 0:b16d94660a33 1832 * @}
Jasper_lee 0:b16d94660a33 1833 */ /* end of group AXBS_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 1834
Jasper_lee 0:b16d94660a33 1835
Jasper_lee 0:b16d94660a33 1836 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1837 -- CAN Peripheral Access Layer
Jasper_lee 0:b16d94660a33 1838 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1839
Jasper_lee 0:b16d94660a33 1840 /*!
Jasper_lee 0:b16d94660a33 1841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
Jasper_lee 0:b16d94660a33 1842 * @{
Jasper_lee 0:b16d94660a33 1843 */
Jasper_lee 0:b16d94660a33 1844
Jasper_lee 0:b16d94660a33 1845 /** CAN - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 1846 typedef struct {
Jasper_lee 0:b16d94660a33 1847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 1848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 1849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
Jasper_lee 0:b16d94660a33 1850 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 1851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 1852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 1853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 1854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
Jasper_lee 0:b16d94660a33 1855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
Jasper_lee 0:b16d94660a33 1856 uint8_t RESERVED_1[4];
Jasper_lee 0:b16d94660a33 1857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
Jasper_lee 0:b16d94660a33 1858 uint8_t RESERVED_2[4];
Jasper_lee 0:b16d94660a33 1859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
Jasper_lee 0:b16d94660a33 1860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
Jasper_lee 0:b16d94660a33 1861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
Jasper_lee 0:b16d94660a33 1862 uint8_t RESERVED_3[8];
Jasper_lee 0:b16d94660a33 1863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
Jasper_lee 0:b16d94660a33 1864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
Jasper_lee 0:b16d94660a33 1865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
Jasper_lee 0:b16d94660a33 1866 uint8_t RESERVED_4[48];
Jasper_lee 0:b16d94660a33 1867 struct { /* offset: 0x80, array step: 0x10 */
Jasper_lee 0:b16d94660a33 1868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
Jasper_lee 0:b16d94660a33 1869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
Jasper_lee 0:b16d94660a33 1870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
Jasper_lee 0:b16d94660a33 1871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
Jasper_lee 0:b16d94660a33 1872 } MB[16];
Jasper_lee 0:b16d94660a33 1873 uint8_t RESERVED_5[1792];
Jasper_lee 0:b16d94660a33 1874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
Jasper_lee 0:b16d94660a33 1875 } CAN_Type, *CAN_MemMapPtr;
Jasper_lee 0:b16d94660a33 1876
Jasper_lee 0:b16d94660a33 1877 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1878 -- CAN - Register accessor macros
Jasper_lee 0:b16d94660a33 1879 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1880
Jasper_lee 0:b16d94660a33 1881 /*!
Jasper_lee 0:b16d94660a33 1882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
Jasper_lee 0:b16d94660a33 1883 * @{
Jasper_lee 0:b16d94660a33 1884 */
Jasper_lee 0:b16d94660a33 1885
Jasper_lee 0:b16d94660a33 1886
Jasper_lee 0:b16d94660a33 1887 /* CAN - Register accessors */
Jasper_lee 0:b16d94660a33 1888 #define CAN_MCR_REG(base) ((base)->MCR)
Jasper_lee 0:b16d94660a33 1889 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
Jasper_lee 0:b16d94660a33 1890 #define CAN_TIMER_REG(base) ((base)->TIMER)
Jasper_lee 0:b16d94660a33 1891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
Jasper_lee 0:b16d94660a33 1892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
Jasper_lee 0:b16d94660a33 1893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
Jasper_lee 0:b16d94660a33 1894 #define CAN_ECR_REG(base) ((base)->ECR)
Jasper_lee 0:b16d94660a33 1895 #define CAN_ESR1_REG(base) ((base)->ESR1)
Jasper_lee 0:b16d94660a33 1896 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
Jasper_lee 0:b16d94660a33 1897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
Jasper_lee 0:b16d94660a33 1898 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
Jasper_lee 0:b16d94660a33 1899 #define CAN_ESR2_REG(base) ((base)->ESR2)
Jasper_lee 0:b16d94660a33 1900 #define CAN_CRCR_REG(base) ((base)->CRCR)
Jasper_lee 0:b16d94660a33 1901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
Jasper_lee 0:b16d94660a33 1902 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
Jasper_lee 0:b16d94660a33 1903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
Jasper_lee 0:b16d94660a33 1904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
Jasper_lee 0:b16d94660a33 1905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
Jasper_lee 0:b16d94660a33 1906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
Jasper_lee 0:b16d94660a33 1907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
Jasper_lee 0:b16d94660a33 1908
Jasper_lee 0:b16d94660a33 1909 /*!
Jasper_lee 0:b16d94660a33 1910 * @}
Jasper_lee 0:b16d94660a33 1911 */ /* end of group CAN_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 1912
Jasper_lee 0:b16d94660a33 1913
Jasper_lee 0:b16d94660a33 1914 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 1915 -- CAN Register Masks
Jasper_lee 0:b16d94660a33 1916 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 1917
Jasper_lee 0:b16d94660a33 1918 /*!
Jasper_lee 0:b16d94660a33 1919 * @addtogroup CAN_Register_Masks CAN Register Masks
Jasper_lee 0:b16d94660a33 1920 * @{
Jasper_lee 0:b16d94660a33 1921 */
Jasper_lee 0:b16d94660a33 1922
Jasper_lee 0:b16d94660a33 1923 /* MCR Bit Fields */
Jasper_lee 0:b16d94660a33 1924 #define CAN_MCR_MAXMB_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 1925 #define CAN_MCR_MAXMB_SHIFT 0
Jasper_lee 0:b16d94660a33 1926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
Jasper_lee 0:b16d94660a33 1927 #define CAN_MCR_IDAM_MASK 0x300u
Jasper_lee 0:b16d94660a33 1928 #define CAN_MCR_IDAM_SHIFT 8
Jasper_lee 0:b16d94660a33 1929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
Jasper_lee 0:b16d94660a33 1930 #define CAN_MCR_AEN_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1931 #define CAN_MCR_AEN_SHIFT 12
Jasper_lee 0:b16d94660a33 1932 #define CAN_MCR_LPRIOEN_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1933 #define CAN_MCR_LPRIOEN_SHIFT 13
Jasper_lee 0:b16d94660a33 1934 #define CAN_MCR_IRMQ_MASK 0x10000u
Jasper_lee 0:b16d94660a33 1935 #define CAN_MCR_IRMQ_SHIFT 16
Jasper_lee 0:b16d94660a33 1936 #define CAN_MCR_SRXDIS_MASK 0x20000u
Jasper_lee 0:b16d94660a33 1937 #define CAN_MCR_SRXDIS_SHIFT 17
Jasper_lee 0:b16d94660a33 1938 #define CAN_MCR_WAKSRC_MASK 0x80000u
Jasper_lee 0:b16d94660a33 1939 #define CAN_MCR_WAKSRC_SHIFT 19
Jasper_lee 0:b16d94660a33 1940 #define CAN_MCR_LPMACK_MASK 0x100000u
Jasper_lee 0:b16d94660a33 1941 #define CAN_MCR_LPMACK_SHIFT 20
Jasper_lee 0:b16d94660a33 1942 #define CAN_MCR_WRNEN_MASK 0x200000u
Jasper_lee 0:b16d94660a33 1943 #define CAN_MCR_WRNEN_SHIFT 21
Jasper_lee 0:b16d94660a33 1944 #define CAN_MCR_SLFWAK_MASK 0x400000u
Jasper_lee 0:b16d94660a33 1945 #define CAN_MCR_SLFWAK_SHIFT 22
Jasper_lee 0:b16d94660a33 1946 #define CAN_MCR_SUPV_MASK 0x800000u
Jasper_lee 0:b16d94660a33 1947 #define CAN_MCR_SUPV_SHIFT 23
Jasper_lee 0:b16d94660a33 1948 #define CAN_MCR_FRZACK_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 1949 #define CAN_MCR_FRZACK_SHIFT 24
Jasper_lee 0:b16d94660a33 1950 #define CAN_MCR_SOFTRST_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 1951 #define CAN_MCR_SOFTRST_SHIFT 25
Jasper_lee 0:b16d94660a33 1952 #define CAN_MCR_WAKMSK_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 1953 #define CAN_MCR_WAKMSK_SHIFT 26
Jasper_lee 0:b16d94660a33 1954 #define CAN_MCR_NOTRDY_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 1955 #define CAN_MCR_NOTRDY_SHIFT 27
Jasper_lee 0:b16d94660a33 1956 #define CAN_MCR_HALT_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 1957 #define CAN_MCR_HALT_SHIFT 28
Jasper_lee 0:b16d94660a33 1958 #define CAN_MCR_RFEN_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 1959 #define CAN_MCR_RFEN_SHIFT 29
Jasper_lee 0:b16d94660a33 1960 #define CAN_MCR_FRZ_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 1961 #define CAN_MCR_FRZ_SHIFT 30
Jasper_lee 0:b16d94660a33 1962 #define CAN_MCR_MDIS_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 1963 #define CAN_MCR_MDIS_SHIFT 31
Jasper_lee 0:b16d94660a33 1964 /* CTRL1 Bit Fields */
Jasper_lee 0:b16d94660a33 1965 #define CAN_CTRL1_PROPSEG_MASK 0x7u
Jasper_lee 0:b16d94660a33 1966 #define CAN_CTRL1_PROPSEG_SHIFT 0
Jasper_lee 0:b16d94660a33 1967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
Jasper_lee 0:b16d94660a33 1968 #define CAN_CTRL1_LOM_MASK 0x8u
Jasper_lee 0:b16d94660a33 1969 #define CAN_CTRL1_LOM_SHIFT 3
Jasper_lee 0:b16d94660a33 1970 #define CAN_CTRL1_LBUF_MASK 0x10u
Jasper_lee 0:b16d94660a33 1971 #define CAN_CTRL1_LBUF_SHIFT 4
Jasper_lee 0:b16d94660a33 1972 #define CAN_CTRL1_TSYN_MASK 0x20u
Jasper_lee 0:b16d94660a33 1973 #define CAN_CTRL1_TSYN_SHIFT 5
Jasper_lee 0:b16d94660a33 1974 #define CAN_CTRL1_BOFFREC_MASK 0x40u
Jasper_lee 0:b16d94660a33 1975 #define CAN_CTRL1_BOFFREC_SHIFT 6
Jasper_lee 0:b16d94660a33 1976 #define CAN_CTRL1_SMP_MASK 0x80u
Jasper_lee 0:b16d94660a33 1977 #define CAN_CTRL1_SMP_SHIFT 7
Jasper_lee 0:b16d94660a33 1978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
Jasper_lee 0:b16d94660a33 1979 #define CAN_CTRL1_RWRNMSK_SHIFT 10
Jasper_lee 0:b16d94660a33 1980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
Jasper_lee 0:b16d94660a33 1981 #define CAN_CTRL1_TWRNMSK_SHIFT 11
Jasper_lee 0:b16d94660a33 1982 #define CAN_CTRL1_LPB_MASK 0x1000u
Jasper_lee 0:b16d94660a33 1983 #define CAN_CTRL1_LPB_SHIFT 12
Jasper_lee 0:b16d94660a33 1984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
Jasper_lee 0:b16d94660a33 1985 #define CAN_CTRL1_CLKSRC_SHIFT 13
Jasper_lee 0:b16d94660a33 1986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
Jasper_lee 0:b16d94660a33 1987 #define CAN_CTRL1_ERRMSK_SHIFT 14
Jasper_lee 0:b16d94660a33 1988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 1989 #define CAN_CTRL1_BOFFMSK_SHIFT 15
Jasper_lee 0:b16d94660a33 1990 #define CAN_CTRL1_PSEG2_MASK 0x70000u
Jasper_lee 0:b16d94660a33 1991 #define CAN_CTRL1_PSEG2_SHIFT 16
Jasper_lee 0:b16d94660a33 1992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
Jasper_lee 0:b16d94660a33 1993 #define CAN_CTRL1_PSEG1_MASK 0x380000u
Jasper_lee 0:b16d94660a33 1994 #define CAN_CTRL1_PSEG1_SHIFT 19
Jasper_lee 0:b16d94660a33 1995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
Jasper_lee 0:b16d94660a33 1996 #define CAN_CTRL1_RJW_MASK 0xC00000u
Jasper_lee 0:b16d94660a33 1997 #define CAN_CTRL1_RJW_SHIFT 22
Jasper_lee 0:b16d94660a33 1998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
Jasper_lee 0:b16d94660a33 1999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 2000 #define CAN_CTRL1_PRESDIV_SHIFT 24
Jasper_lee 0:b16d94660a33 2001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
Jasper_lee 0:b16d94660a33 2002 /* TIMER Bit Fields */
Jasper_lee 0:b16d94660a33 2003 #define CAN_TIMER_TIMER_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 2004 #define CAN_TIMER_TIMER_SHIFT 0
Jasper_lee 0:b16d94660a33 2005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
Jasper_lee 0:b16d94660a33 2006 /* RXMGMASK Bit Fields */
Jasper_lee 0:b16d94660a33 2007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2008 #define CAN_RXMGMASK_MG_SHIFT 0
Jasper_lee 0:b16d94660a33 2009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
Jasper_lee 0:b16d94660a33 2010 /* RX14MASK Bit Fields */
Jasper_lee 0:b16d94660a33 2011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2012 #define CAN_RX14MASK_RX14M_SHIFT 0
Jasper_lee 0:b16d94660a33 2013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
Jasper_lee 0:b16d94660a33 2014 /* RX15MASK Bit Fields */
Jasper_lee 0:b16d94660a33 2015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2016 #define CAN_RX15MASK_RX15M_SHIFT 0
Jasper_lee 0:b16d94660a33 2017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
Jasper_lee 0:b16d94660a33 2018 /* ECR Bit Fields */
Jasper_lee 0:b16d94660a33 2019 #define CAN_ECR_TXERRCNT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 2020 #define CAN_ECR_TXERRCNT_SHIFT 0
Jasper_lee 0:b16d94660a33 2021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
Jasper_lee 0:b16d94660a33 2022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 2023 #define CAN_ECR_RXERRCNT_SHIFT 8
Jasper_lee 0:b16d94660a33 2024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
Jasper_lee 0:b16d94660a33 2025 /* ESR1 Bit Fields */
Jasper_lee 0:b16d94660a33 2026 #define CAN_ESR1_WAKINT_MASK 0x1u
Jasper_lee 0:b16d94660a33 2027 #define CAN_ESR1_WAKINT_SHIFT 0
Jasper_lee 0:b16d94660a33 2028 #define CAN_ESR1_ERRINT_MASK 0x2u
Jasper_lee 0:b16d94660a33 2029 #define CAN_ESR1_ERRINT_SHIFT 1
Jasper_lee 0:b16d94660a33 2030 #define CAN_ESR1_BOFFINT_MASK 0x4u
Jasper_lee 0:b16d94660a33 2031 #define CAN_ESR1_BOFFINT_SHIFT 2
Jasper_lee 0:b16d94660a33 2032 #define CAN_ESR1_RX_MASK 0x8u
Jasper_lee 0:b16d94660a33 2033 #define CAN_ESR1_RX_SHIFT 3
Jasper_lee 0:b16d94660a33 2034 #define CAN_ESR1_FLTCONF_MASK 0x30u
Jasper_lee 0:b16d94660a33 2035 #define CAN_ESR1_FLTCONF_SHIFT 4
Jasper_lee 0:b16d94660a33 2036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
Jasper_lee 0:b16d94660a33 2037 #define CAN_ESR1_TX_MASK 0x40u
Jasper_lee 0:b16d94660a33 2038 #define CAN_ESR1_TX_SHIFT 6
Jasper_lee 0:b16d94660a33 2039 #define CAN_ESR1_IDLE_MASK 0x80u
Jasper_lee 0:b16d94660a33 2040 #define CAN_ESR1_IDLE_SHIFT 7
Jasper_lee 0:b16d94660a33 2041 #define CAN_ESR1_RXWRN_MASK 0x100u
Jasper_lee 0:b16d94660a33 2042 #define CAN_ESR1_RXWRN_SHIFT 8
Jasper_lee 0:b16d94660a33 2043 #define CAN_ESR1_TXWRN_MASK 0x200u
Jasper_lee 0:b16d94660a33 2044 #define CAN_ESR1_TXWRN_SHIFT 9
Jasper_lee 0:b16d94660a33 2045 #define CAN_ESR1_STFERR_MASK 0x400u
Jasper_lee 0:b16d94660a33 2046 #define CAN_ESR1_STFERR_SHIFT 10
Jasper_lee 0:b16d94660a33 2047 #define CAN_ESR1_FRMERR_MASK 0x800u
Jasper_lee 0:b16d94660a33 2048 #define CAN_ESR1_FRMERR_SHIFT 11
Jasper_lee 0:b16d94660a33 2049 #define CAN_ESR1_CRCERR_MASK 0x1000u
Jasper_lee 0:b16d94660a33 2050 #define CAN_ESR1_CRCERR_SHIFT 12
Jasper_lee 0:b16d94660a33 2051 #define CAN_ESR1_ACKERR_MASK 0x2000u
Jasper_lee 0:b16d94660a33 2052 #define CAN_ESR1_ACKERR_SHIFT 13
Jasper_lee 0:b16d94660a33 2053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
Jasper_lee 0:b16d94660a33 2054 #define CAN_ESR1_BIT0ERR_SHIFT 14
Jasper_lee 0:b16d94660a33 2055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
Jasper_lee 0:b16d94660a33 2056 #define CAN_ESR1_BIT1ERR_SHIFT 15
Jasper_lee 0:b16d94660a33 2057 #define CAN_ESR1_RWRNINT_MASK 0x10000u
Jasper_lee 0:b16d94660a33 2058 #define CAN_ESR1_RWRNINT_SHIFT 16
Jasper_lee 0:b16d94660a33 2059 #define CAN_ESR1_TWRNINT_MASK 0x20000u
Jasper_lee 0:b16d94660a33 2060 #define CAN_ESR1_TWRNINT_SHIFT 17
Jasper_lee 0:b16d94660a33 2061 #define CAN_ESR1_SYNCH_MASK 0x40000u
Jasper_lee 0:b16d94660a33 2062 #define CAN_ESR1_SYNCH_SHIFT 18
Jasper_lee 0:b16d94660a33 2063 /* IMASK1 Bit Fields */
Jasper_lee 0:b16d94660a33 2064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2065 #define CAN_IMASK1_BUFLM_SHIFT 0
Jasper_lee 0:b16d94660a33 2066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
Jasper_lee 0:b16d94660a33 2067 /* IFLAG1 Bit Fields */
Jasper_lee 0:b16d94660a33 2068 #define CAN_IFLAG1_BUF0I_MASK 0x1u
Jasper_lee 0:b16d94660a33 2069 #define CAN_IFLAG1_BUF0I_SHIFT 0
Jasper_lee 0:b16d94660a33 2070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
Jasper_lee 0:b16d94660a33 2071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
Jasper_lee 0:b16d94660a33 2072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
Jasper_lee 0:b16d94660a33 2073 #define CAN_IFLAG1_BUF5I_MASK 0x20u
Jasper_lee 0:b16d94660a33 2074 #define CAN_IFLAG1_BUF5I_SHIFT 5
Jasper_lee 0:b16d94660a33 2075 #define CAN_IFLAG1_BUF6I_MASK 0x40u
Jasper_lee 0:b16d94660a33 2076 #define CAN_IFLAG1_BUF6I_SHIFT 6
Jasper_lee 0:b16d94660a33 2077 #define CAN_IFLAG1_BUF7I_MASK 0x80u
Jasper_lee 0:b16d94660a33 2078 #define CAN_IFLAG1_BUF7I_SHIFT 7
Jasper_lee 0:b16d94660a33 2079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
Jasper_lee 0:b16d94660a33 2080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
Jasper_lee 0:b16d94660a33 2081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
Jasper_lee 0:b16d94660a33 2082 /* CTRL2 Bit Fields */
Jasper_lee 0:b16d94660a33 2083 #define CAN_CTRL2_EACEN_MASK 0x10000u
Jasper_lee 0:b16d94660a33 2084 #define CAN_CTRL2_EACEN_SHIFT 16
Jasper_lee 0:b16d94660a33 2085 #define CAN_CTRL2_RRS_MASK 0x20000u
Jasper_lee 0:b16d94660a33 2086 #define CAN_CTRL2_RRS_SHIFT 17
Jasper_lee 0:b16d94660a33 2087 #define CAN_CTRL2_MRP_MASK 0x40000u
Jasper_lee 0:b16d94660a33 2088 #define CAN_CTRL2_MRP_SHIFT 18
Jasper_lee 0:b16d94660a33 2089 #define CAN_CTRL2_TASD_MASK 0xF80000u
Jasper_lee 0:b16d94660a33 2090 #define CAN_CTRL2_TASD_SHIFT 19
Jasper_lee 0:b16d94660a33 2091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
Jasper_lee 0:b16d94660a33 2092 #define CAN_CTRL2_RFFN_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 2093 #define CAN_CTRL2_RFFN_SHIFT 24
Jasper_lee 0:b16d94660a33 2094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
Jasper_lee 0:b16d94660a33 2095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 2096 #define CAN_CTRL2_WRMFRZ_SHIFT 28
Jasper_lee 0:b16d94660a33 2097 /* ESR2 Bit Fields */
Jasper_lee 0:b16d94660a33 2098 #define CAN_ESR2_IMB_MASK 0x2000u
Jasper_lee 0:b16d94660a33 2099 #define CAN_ESR2_IMB_SHIFT 13
Jasper_lee 0:b16d94660a33 2100 #define CAN_ESR2_VPS_MASK 0x4000u
Jasper_lee 0:b16d94660a33 2101 #define CAN_ESR2_VPS_SHIFT 14
Jasper_lee 0:b16d94660a33 2102 #define CAN_ESR2_LPTM_MASK 0x7F0000u
Jasper_lee 0:b16d94660a33 2103 #define CAN_ESR2_LPTM_SHIFT 16
Jasper_lee 0:b16d94660a33 2104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
Jasper_lee 0:b16d94660a33 2105 /* CRCR Bit Fields */
Jasper_lee 0:b16d94660a33 2106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
Jasper_lee 0:b16d94660a33 2107 #define CAN_CRCR_TXCRC_SHIFT 0
Jasper_lee 0:b16d94660a33 2108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
Jasper_lee 0:b16d94660a33 2109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
Jasper_lee 0:b16d94660a33 2110 #define CAN_CRCR_MBCRC_SHIFT 16
Jasper_lee 0:b16d94660a33 2111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
Jasper_lee 0:b16d94660a33 2112 /* RXFGMASK Bit Fields */
Jasper_lee 0:b16d94660a33 2113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2114 #define CAN_RXFGMASK_FGM_SHIFT 0
Jasper_lee 0:b16d94660a33 2115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
Jasper_lee 0:b16d94660a33 2116 /* RXFIR Bit Fields */
Jasper_lee 0:b16d94660a33 2117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
Jasper_lee 0:b16d94660a33 2118 #define CAN_RXFIR_IDHIT_SHIFT 0
Jasper_lee 0:b16d94660a33 2119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
Jasper_lee 0:b16d94660a33 2120 /* CS Bit Fields */
Jasper_lee 0:b16d94660a33 2121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 2122 #define CAN_CS_TIME_STAMP_SHIFT 0
Jasper_lee 0:b16d94660a33 2123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
Jasper_lee 0:b16d94660a33 2124 #define CAN_CS_DLC_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 2125 #define CAN_CS_DLC_SHIFT 16
Jasper_lee 0:b16d94660a33 2126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
Jasper_lee 0:b16d94660a33 2127 #define CAN_CS_RTR_MASK 0x100000u
Jasper_lee 0:b16d94660a33 2128 #define CAN_CS_RTR_SHIFT 20
Jasper_lee 0:b16d94660a33 2129 #define CAN_CS_IDE_MASK 0x200000u
Jasper_lee 0:b16d94660a33 2130 #define CAN_CS_IDE_SHIFT 21
Jasper_lee 0:b16d94660a33 2131 #define CAN_CS_SRR_MASK 0x400000u
Jasper_lee 0:b16d94660a33 2132 #define CAN_CS_SRR_SHIFT 22
Jasper_lee 0:b16d94660a33 2133 #define CAN_CS_CODE_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 2134 #define CAN_CS_CODE_SHIFT 24
Jasper_lee 0:b16d94660a33 2135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
Jasper_lee 0:b16d94660a33 2136 /* ID Bit Fields */
Jasper_lee 0:b16d94660a33 2137 #define CAN_ID_EXT_MASK 0x3FFFFu
Jasper_lee 0:b16d94660a33 2138 #define CAN_ID_EXT_SHIFT 0
Jasper_lee 0:b16d94660a33 2139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
Jasper_lee 0:b16d94660a33 2140 #define CAN_ID_STD_MASK 0x1FFC0000u
Jasper_lee 0:b16d94660a33 2141 #define CAN_ID_STD_SHIFT 18
Jasper_lee 0:b16d94660a33 2142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
Jasper_lee 0:b16d94660a33 2143 #define CAN_ID_PRIO_MASK 0xE0000000u
Jasper_lee 0:b16d94660a33 2144 #define CAN_ID_PRIO_SHIFT 29
Jasper_lee 0:b16d94660a33 2145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
Jasper_lee 0:b16d94660a33 2146 /* WORD0 Bit Fields */
Jasper_lee 0:b16d94660a33 2147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
Jasper_lee 0:b16d94660a33 2148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
Jasper_lee 0:b16d94660a33 2149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
Jasper_lee 0:b16d94660a33 2150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 2151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
Jasper_lee 0:b16d94660a33 2152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
Jasper_lee 0:b16d94660a33 2153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 2154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
Jasper_lee 0:b16d94660a33 2155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
Jasper_lee 0:b16d94660a33 2156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 2157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
Jasper_lee 0:b16d94660a33 2158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
Jasper_lee 0:b16d94660a33 2159 /* WORD1 Bit Fields */
Jasper_lee 0:b16d94660a33 2160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
Jasper_lee 0:b16d94660a33 2161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
Jasper_lee 0:b16d94660a33 2162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
Jasper_lee 0:b16d94660a33 2163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 2164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
Jasper_lee 0:b16d94660a33 2165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
Jasper_lee 0:b16d94660a33 2166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 2167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
Jasper_lee 0:b16d94660a33 2168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
Jasper_lee 0:b16d94660a33 2169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 2170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
Jasper_lee 0:b16d94660a33 2171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
Jasper_lee 0:b16d94660a33 2172 /* RXIMR Bit Fields */
Jasper_lee 0:b16d94660a33 2173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2174 #define CAN_RXIMR_MI_SHIFT 0
Jasper_lee 0:b16d94660a33 2175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
Jasper_lee 0:b16d94660a33 2176
Jasper_lee 0:b16d94660a33 2177 /*!
Jasper_lee 0:b16d94660a33 2178 * @}
Jasper_lee 0:b16d94660a33 2179 */ /* end of group CAN_Register_Masks */
Jasper_lee 0:b16d94660a33 2180
Jasper_lee 0:b16d94660a33 2181
Jasper_lee 0:b16d94660a33 2182 /* CAN - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 2183 /** Peripheral CAN0 base address */
Jasper_lee 0:b16d94660a33 2184 #define CAN0_BASE (0x40024000u)
Jasper_lee 0:b16d94660a33 2185 /** Peripheral CAN0 base pointer */
Jasper_lee 0:b16d94660a33 2186 #define CAN0 ((CAN_Type *)CAN0_BASE)
Jasper_lee 0:b16d94660a33 2187 #define CAN0_BASE_PTR (CAN0)
Jasper_lee 0:b16d94660a33 2188 /** Array initializer of CAN peripheral base addresses */
Jasper_lee 0:b16d94660a33 2189 #define CAN_BASE_ADDRS { CAN0_BASE }
Jasper_lee 0:b16d94660a33 2190 /** Array initializer of CAN peripheral base pointers */
Jasper_lee 0:b16d94660a33 2191 #define CAN_BASE_PTRS { CAN0 }
Jasper_lee 0:b16d94660a33 2192 /** Interrupt vectors for the CAN peripheral type */
Jasper_lee 0:b16d94660a33 2193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
Jasper_lee 0:b16d94660a33 2194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
Jasper_lee 0:b16d94660a33 2195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
Jasper_lee 0:b16d94660a33 2196 #define CAN_Error_IRQS { CAN0_Error_IRQn }
Jasper_lee 0:b16d94660a33 2197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
Jasper_lee 0:b16d94660a33 2198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
Jasper_lee 0:b16d94660a33 2199
Jasper_lee 0:b16d94660a33 2200 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2201 -- CAN - Register accessor macros
Jasper_lee 0:b16d94660a33 2202 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2203
Jasper_lee 0:b16d94660a33 2204 /*!
Jasper_lee 0:b16d94660a33 2205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
Jasper_lee 0:b16d94660a33 2206 * @{
Jasper_lee 0:b16d94660a33 2207 */
Jasper_lee 0:b16d94660a33 2208
Jasper_lee 0:b16d94660a33 2209
Jasper_lee 0:b16d94660a33 2210 /* CAN - Register instance definitions */
Jasper_lee 0:b16d94660a33 2211 /* CAN0 */
Jasper_lee 0:b16d94660a33 2212 #define CAN0_MCR CAN_MCR_REG(CAN0)
Jasper_lee 0:b16d94660a33 2213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
Jasper_lee 0:b16d94660a33 2214 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
Jasper_lee 0:b16d94660a33 2215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
Jasper_lee 0:b16d94660a33 2216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
Jasper_lee 0:b16d94660a33 2217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
Jasper_lee 0:b16d94660a33 2218 #define CAN0_ECR CAN_ECR_REG(CAN0)
Jasper_lee 0:b16d94660a33 2219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
Jasper_lee 0:b16d94660a33 2220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
Jasper_lee 0:b16d94660a33 2221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
Jasper_lee 0:b16d94660a33 2222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
Jasper_lee 0:b16d94660a33 2223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
Jasper_lee 0:b16d94660a33 2224 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
Jasper_lee 0:b16d94660a33 2225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
Jasper_lee 0:b16d94660a33 2226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
Jasper_lee 0:b16d94660a33 2227 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
Jasper_lee 0:b16d94660a33 2228 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
Jasper_lee 0:b16d94660a33 2229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
Jasper_lee 0:b16d94660a33 2230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
Jasper_lee 0:b16d94660a33 2231 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
Jasper_lee 0:b16d94660a33 2232 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
Jasper_lee 0:b16d94660a33 2233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
Jasper_lee 0:b16d94660a33 2234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
Jasper_lee 0:b16d94660a33 2235 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
Jasper_lee 0:b16d94660a33 2236 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
Jasper_lee 0:b16d94660a33 2237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
Jasper_lee 0:b16d94660a33 2238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
Jasper_lee 0:b16d94660a33 2239 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
Jasper_lee 0:b16d94660a33 2240 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
Jasper_lee 0:b16d94660a33 2241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
Jasper_lee 0:b16d94660a33 2242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
Jasper_lee 0:b16d94660a33 2243 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
Jasper_lee 0:b16d94660a33 2244 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
Jasper_lee 0:b16d94660a33 2245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
Jasper_lee 0:b16d94660a33 2246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
Jasper_lee 0:b16d94660a33 2247 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
Jasper_lee 0:b16d94660a33 2248 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
Jasper_lee 0:b16d94660a33 2249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
Jasper_lee 0:b16d94660a33 2250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
Jasper_lee 0:b16d94660a33 2251 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
Jasper_lee 0:b16d94660a33 2252 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
Jasper_lee 0:b16d94660a33 2253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
Jasper_lee 0:b16d94660a33 2254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
Jasper_lee 0:b16d94660a33 2255 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
Jasper_lee 0:b16d94660a33 2256 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
Jasper_lee 0:b16d94660a33 2257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
Jasper_lee 0:b16d94660a33 2258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
Jasper_lee 0:b16d94660a33 2259 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
Jasper_lee 0:b16d94660a33 2260 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
Jasper_lee 0:b16d94660a33 2261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
Jasper_lee 0:b16d94660a33 2262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
Jasper_lee 0:b16d94660a33 2263 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
Jasper_lee 0:b16d94660a33 2264 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
Jasper_lee 0:b16d94660a33 2265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
Jasper_lee 0:b16d94660a33 2266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
Jasper_lee 0:b16d94660a33 2267 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
Jasper_lee 0:b16d94660a33 2268 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
Jasper_lee 0:b16d94660a33 2269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
Jasper_lee 0:b16d94660a33 2270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
Jasper_lee 0:b16d94660a33 2271 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
Jasper_lee 0:b16d94660a33 2272 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
Jasper_lee 0:b16d94660a33 2273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
Jasper_lee 0:b16d94660a33 2274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
Jasper_lee 0:b16d94660a33 2275 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
Jasper_lee 0:b16d94660a33 2276 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
Jasper_lee 0:b16d94660a33 2277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
Jasper_lee 0:b16d94660a33 2278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
Jasper_lee 0:b16d94660a33 2279 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
Jasper_lee 0:b16d94660a33 2280 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
Jasper_lee 0:b16d94660a33 2281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
Jasper_lee 0:b16d94660a33 2282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
Jasper_lee 0:b16d94660a33 2283 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
Jasper_lee 0:b16d94660a33 2284 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
Jasper_lee 0:b16d94660a33 2285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
Jasper_lee 0:b16d94660a33 2286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
Jasper_lee 0:b16d94660a33 2287 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
Jasper_lee 0:b16d94660a33 2288 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
Jasper_lee 0:b16d94660a33 2289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
Jasper_lee 0:b16d94660a33 2290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
Jasper_lee 0:b16d94660a33 2291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
Jasper_lee 0:b16d94660a33 2292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
Jasper_lee 0:b16d94660a33 2293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
Jasper_lee 0:b16d94660a33 2294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
Jasper_lee 0:b16d94660a33 2295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
Jasper_lee 0:b16d94660a33 2296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
Jasper_lee 0:b16d94660a33 2297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
Jasper_lee 0:b16d94660a33 2298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
Jasper_lee 0:b16d94660a33 2299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
Jasper_lee 0:b16d94660a33 2300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
Jasper_lee 0:b16d94660a33 2301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
Jasper_lee 0:b16d94660a33 2302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
Jasper_lee 0:b16d94660a33 2303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
Jasper_lee 0:b16d94660a33 2304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
Jasper_lee 0:b16d94660a33 2305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
Jasper_lee 0:b16d94660a33 2306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
Jasper_lee 0:b16d94660a33 2307
Jasper_lee 0:b16d94660a33 2308 /* CAN - Register array accessors */
Jasper_lee 0:b16d94660a33 2309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
Jasper_lee 0:b16d94660a33 2310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
Jasper_lee 0:b16d94660a33 2311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
Jasper_lee 0:b16d94660a33 2312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
Jasper_lee 0:b16d94660a33 2313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
Jasper_lee 0:b16d94660a33 2314
Jasper_lee 0:b16d94660a33 2315 /*!
Jasper_lee 0:b16d94660a33 2316 * @}
Jasper_lee 0:b16d94660a33 2317 */ /* end of group CAN_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 2318
Jasper_lee 0:b16d94660a33 2319
Jasper_lee 0:b16d94660a33 2320 /*!
Jasper_lee 0:b16d94660a33 2321 * @}
Jasper_lee 0:b16d94660a33 2322 */ /* end of group CAN_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 2323
Jasper_lee 0:b16d94660a33 2324
Jasper_lee 0:b16d94660a33 2325 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2326 -- CAU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 2327 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2328
Jasper_lee 0:b16d94660a33 2329 /*!
Jasper_lee 0:b16d94660a33 2330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 2331 * @{
Jasper_lee 0:b16d94660a33 2332 */
Jasper_lee 0:b16d94660a33 2333
Jasper_lee 0:b16d94660a33 2334 /** CAU - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 2335 typedef struct {
Jasper_lee 0:b16d94660a33 2336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2337 uint8_t RESERVED_0[2048];
Jasper_lee 0:b16d94660a33 2338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
Jasper_lee 0:b16d94660a33 2339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
Jasper_lee 0:b16d94660a33 2340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2341 uint8_t RESERVED_1[20];
Jasper_lee 0:b16d94660a33 2342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
Jasper_lee 0:b16d94660a33 2343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
Jasper_lee 0:b16d94660a33 2344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2345 uint8_t RESERVED_2[20];
Jasper_lee 0:b16d94660a33 2346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
Jasper_lee 0:b16d94660a33 2347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
Jasper_lee 0:b16d94660a33 2348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2349 uint8_t RESERVED_3[20];
Jasper_lee 0:b16d94660a33 2350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
Jasper_lee 0:b16d94660a33 2351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
Jasper_lee 0:b16d94660a33 2352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2353 uint8_t RESERVED_4[84];
Jasper_lee 0:b16d94660a33 2354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
Jasper_lee 0:b16d94660a33 2355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
Jasper_lee 0:b16d94660a33 2356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2357 uint8_t RESERVED_5[20];
Jasper_lee 0:b16d94660a33 2358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
Jasper_lee 0:b16d94660a33 2359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
Jasper_lee 0:b16d94660a33 2360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2361 uint8_t RESERVED_6[276];
Jasper_lee 0:b16d94660a33 2362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
Jasper_lee 0:b16d94660a33 2363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
Jasper_lee 0:b16d94660a33 2364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2365 uint8_t RESERVED_7[20];
Jasper_lee 0:b16d94660a33 2366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
Jasper_lee 0:b16d94660a33 2367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
Jasper_lee 0:b16d94660a33 2368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
Jasper_lee 0:b16d94660a33 2369 } CAU_Type, *CAU_MemMapPtr;
Jasper_lee 0:b16d94660a33 2370
Jasper_lee 0:b16d94660a33 2371 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2372 -- CAU - Register accessor macros
Jasper_lee 0:b16d94660a33 2373 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2374
Jasper_lee 0:b16d94660a33 2375 /*!
Jasper_lee 0:b16d94660a33 2376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
Jasper_lee 0:b16d94660a33 2377 * @{
Jasper_lee 0:b16d94660a33 2378 */
Jasper_lee 0:b16d94660a33 2379
Jasper_lee 0:b16d94660a33 2380
Jasper_lee 0:b16d94660a33 2381 /* CAU - Register accessors */
Jasper_lee 0:b16d94660a33 2382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
Jasper_lee 0:b16d94660a33 2383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
Jasper_lee 0:b16d94660a33 2384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
Jasper_lee 0:b16d94660a33 2385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
Jasper_lee 0:b16d94660a33 2386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
Jasper_lee 0:b16d94660a33 2387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
Jasper_lee 0:b16d94660a33 2388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
Jasper_lee 0:b16d94660a33 2389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
Jasper_lee 0:b16d94660a33 2390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
Jasper_lee 0:b16d94660a33 2391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
Jasper_lee 0:b16d94660a33 2392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
Jasper_lee 0:b16d94660a33 2393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
Jasper_lee 0:b16d94660a33 2394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
Jasper_lee 0:b16d94660a33 2395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
Jasper_lee 0:b16d94660a33 2396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
Jasper_lee 0:b16d94660a33 2397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
Jasper_lee 0:b16d94660a33 2398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
Jasper_lee 0:b16d94660a33 2399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
Jasper_lee 0:b16d94660a33 2400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
Jasper_lee 0:b16d94660a33 2401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
Jasper_lee 0:b16d94660a33 2402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
Jasper_lee 0:b16d94660a33 2403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
Jasper_lee 0:b16d94660a33 2404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
Jasper_lee 0:b16d94660a33 2405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
Jasper_lee 0:b16d94660a33 2406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
Jasper_lee 0:b16d94660a33 2407
Jasper_lee 0:b16d94660a33 2408 /*!
Jasper_lee 0:b16d94660a33 2409 * @}
Jasper_lee 0:b16d94660a33 2410 */ /* end of group CAU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 2411
Jasper_lee 0:b16d94660a33 2412
Jasper_lee 0:b16d94660a33 2413 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2414 -- CAU Register Masks
Jasper_lee 0:b16d94660a33 2415 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2416
Jasper_lee 0:b16d94660a33 2417 /*!
Jasper_lee 0:b16d94660a33 2418 * @addtogroup CAU_Register_Masks CAU Register Masks
Jasper_lee 0:b16d94660a33 2419 * @{
Jasper_lee 0:b16d94660a33 2420 */
Jasper_lee 0:b16d94660a33 2421
Jasper_lee 0:b16d94660a33 2422 /* DIRECT Bit Fields */
Jasper_lee 0:b16d94660a33 2423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
Jasper_lee 0:b16d94660a33 2425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
Jasper_lee 0:b16d94660a33 2426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
Jasper_lee 0:b16d94660a33 2428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
Jasper_lee 0:b16d94660a33 2429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
Jasper_lee 0:b16d94660a33 2431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
Jasper_lee 0:b16d94660a33 2432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
Jasper_lee 0:b16d94660a33 2434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
Jasper_lee 0:b16d94660a33 2435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
Jasper_lee 0:b16d94660a33 2437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
Jasper_lee 0:b16d94660a33 2438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
Jasper_lee 0:b16d94660a33 2440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
Jasper_lee 0:b16d94660a33 2441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
Jasper_lee 0:b16d94660a33 2443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
Jasper_lee 0:b16d94660a33 2444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
Jasper_lee 0:b16d94660a33 2446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
Jasper_lee 0:b16d94660a33 2447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
Jasper_lee 0:b16d94660a33 2449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
Jasper_lee 0:b16d94660a33 2450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
Jasper_lee 0:b16d94660a33 2452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
Jasper_lee 0:b16d94660a33 2453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
Jasper_lee 0:b16d94660a33 2455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
Jasper_lee 0:b16d94660a33 2456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
Jasper_lee 0:b16d94660a33 2458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
Jasper_lee 0:b16d94660a33 2459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
Jasper_lee 0:b16d94660a33 2461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
Jasper_lee 0:b16d94660a33 2462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
Jasper_lee 0:b16d94660a33 2464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
Jasper_lee 0:b16d94660a33 2465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
Jasper_lee 0:b16d94660a33 2467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
Jasper_lee 0:b16d94660a33 2468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
Jasper_lee 0:b16d94660a33 2470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
Jasper_lee 0:b16d94660a33 2471 /* LDR_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2472 #define CAU_LDR_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2473 #define CAU_LDR_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2474 #define CAU_LDR_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2475 #define CAU_LDR_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2477 #define CAU_LDR_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2479 /* LDR_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2481 #define CAU_LDR_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2483 /* LDR_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2485 #define CAU_LDR_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2488 #define CAU_LDR_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2491 #define CAU_LDR_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2494 #define CAU_LDR_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2497 #define CAU_LDR_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2500 #define CAU_LDR_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2503 #define CAU_LDR_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2506 #define CAU_LDR_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2509 #define CAU_LDR_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2511 /* STR_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2512 #define CAU_STR_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2513 #define CAU_STR_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2514 #define CAU_STR_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2515 #define CAU_STR_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2516 #define CAU_STR_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2517 #define CAU_STR_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2519 /* STR_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2521 #define CAU_STR_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2523 /* STR_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2525 #define CAU_STR_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2528 #define CAU_STR_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2531 #define CAU_STR_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2534 #define CAU_STR_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2537 #define CAU_STR_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2540 #define CAU_STR_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2543 #define CAU_STR_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2546 #define CAU_STR_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2549 #define CAU_STR_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2551 /* ADR_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2552 #define CAU_ADR_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2553 #define CAU_ADR_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2554 #define CAU_ADR_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2555 #define CAU_ADR_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2557 #define CAU_ADR_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2559 /* ADR_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2561 #define CAU_ADR_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2563 /* ADR_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2565 #define CAU_ADR_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2568 #define CAU_ADR_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2571 #define CAU_ADR_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2574 #define CAU_ADR_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2577 #define CAU_ADR_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2580 #define CAU_ADR_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2583 #define CAU_ADR_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2586 #define CAU_ADR_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2589 #define CAU_ADR_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2591 /* RADR_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2592 #define CAU_RADR_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2593 #define CAU_RADR_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2594 #define CAU_RADR_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2595 #define CAU_RADR_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2597 #define CAU_RADR_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2599 /* RADR_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2601 #define CAU_RADR_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2603 /* RADR_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2605 #define CAU_RADR_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2608 #define CAU_RADR_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2611 #define CAU_RADR_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2614 #define CAU_RADR_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2617 #define CAU_RADR_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2620 #define CAU_RADR_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2623 #define CAU_RADR_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2626 #define CAU_RADR_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2629 #define CAU_RADR_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2631 /* XOR_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2632 #define CAU_XOR_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2633 #define CAU_XOR_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2634 #define CAU_XOR_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2635 #define CAU_XOR_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2637 #define CAU_XOR_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2639 /* XOR_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2641 #define CAU_XOR_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2643 /* XOR_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2645 #define CAU_XOR_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2648 #define CAU_XOR_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2651 #define CAU_XOR_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2654 #define CAU_XOR_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2657 #define CAU_XOR_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2660 #define CAU_XOR_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2663 #define CAU_XOR_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2666 #define CAU_XOR_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2669 #define CAU_XOR_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2671 /* ROTL_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2672 #define CAU_ROTL_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2673 #define CAU_ROTL_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2674 #define CAU_ROTL_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2675 #define CAU_ROTL_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2677 #define CAU_ROTL_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2679 /* ROTL_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2681 #define CAU_ROTL_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2683 /* ROTL_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2685 #define CAU_ROTL_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2688 #define CAU_ROTL_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2691 #define CAU_ROTL_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2694 #define CAU_ROTL_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2697 #define CAU_ROTL_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2700 #define CAU_ROTL_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2703 #define CAU_ROTL_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2706 #define CAU_ROTL_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2709 #define CAU_ROTL_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2711 /* AESC_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2712 #define CAU_AESC_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2713 #define CAU_AESC_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2714 #define CAU_AESC_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2715 #define CAU_AESC_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2717 #define CAU_AESC_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2719 /* AESC_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2721 #define CAU_AESC_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2723 /* AESC_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2725 #define CAU_AESC_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2728 #define CAU_AESC_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2731 #define CAU_AESC_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2734 #define CAU_AESC_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2737 #define CAU_AESC_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2740 #define CAU_AESC_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2743 #define CAU_AESC_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2746 #define CAU_AESC_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2749 #define CAU_AESC_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2751 /* AESIC_CASR Bit Fields */
Jasper_lee 0:b16d94660a33 2752 #define CAU_AESIC_CASR_IC_MASK 0x1u
Jasper_lee 0:b16d94660a33 2753 #define CAU_AESIC_CASR_IC_SHIFT 0
Jasper_lee 0:b16d94660a33 2754 #define CAU_AESIC_CASR_DPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 2755 #define CAU_AESIC_CASR_DPE_SHIFT 1
Jasper_lee 0:b16d94660a33 2756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 2757 #define CAU_AESIC_CASR_VER_SHIFT 28
Jasper_lee 0:b16d94660a33 2758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
Jasper_lee 0:b16d94660a33 2759 /* AESIC_CAA Bit Fields */
Jasper_lee 0:b16d94660a33 2760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2761 #define CAU_AESIC_CAA_ACC_SHIFT 0
Jasper_lee 0:b16d94660a33 2762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
Jasper_lee 0:b16d94660a33 2763 /* AESIC_CA Bit Fields */
Jasper_lee 0:b16d94660a33 2764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2765 #define CAU_AESIC_CA_CA0_SHIFT 0
Jasper_lee 0:b16d94660a33 2766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
Jasper_lee 0:b16d94660a33 2767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2768 #define CAU_AESIC_CA_CA1_SHIFT 0
Jasper_lee 0:b16d94660a33 2769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
Jasper_lee 0:b16d94660a33 2770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2771 #define CAU_AESIC_CA_CA2_SHIFT 0
Jasper_lee 0:b16d94660a33 2772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
Jasper_lee 0:b16d94660a33 2773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2774 #define CAU_AESIC_CA_CA3_SHIFT 0
Jasper_lee 0:b16d94660a33 2775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
Jasper_lee 0:b16d94660a33 2776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2777 #define CAU_AESIC_CA_CA4_SHIFT 0
Jasper_lee 0:b16d94660a33 2778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
Jasper_lee 0:b16d94660a33 2779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2780 #define CAU_AESIC_CA_CA5_SHIFT 0
Jasper_lee 0:b16d94660a33 2781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
Jasper_lee 0:b16d94660a33 2782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2783 #define CAU_AESIC_CA_CA6_SHIFT 0
Jasper_lee 0:b16d94660a33 2784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
Jasper_lee 0:b16d94660a33 2785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2786 #define CAU_AESIC_CA_CA7_SHIFT 0
Jasper_lee 0:b16d94660a33 2787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
Jasper_lee 0:b16d94660a33 2788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 2789 #define CAU_AESIC_CA_CA8_SHIFT 0
Jasper_lee 0:b16d94660a33 2790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
Jasper_lee 0:b16d94660a33 2791
Jasper_lee 0:b16d94660a33 2792 /*!
Jasper_lee 0:b16d94660a33 2793 * @}
Jasper_lee 0:b16d94660a33 2794 */ /* end of group CAU_Register_Masks */
Jasper_lee 0:b16d94660a33 2795
Jasper_lee 0:b16d94660a33 2796
Jasper_lee 0:b16d94660a33 2797 /* CAU - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 2798 /** Peripheral CAU base address */
Jasper_lee 0:b16d94660a33 2799 #define CAU_BASE (0xE0081000u)
Jasper_lee 0:b16d94660a33 2800 /** Peripheral CAU base pointer */
Jasper_lee 0:b16d94660a33 2801 #define CAU ((CAU_Type *)CAU_BASE)
Jasper_lee 0:b16d94660a33 2802 #define CAU_BASE_PTR (CAU)
Jasper_lee 0:b16d94660a33 2803 /** Array initializer of CAU peripheral base addresses */
Jasper_lee 0:b16d94660a33 2804 #define CAU_BASE_ADDRS { CAU_BASE }
Jasper_lee 0:b16d94660a33 2805 /** Array initializer of CAU peripheral base pointers */
Jasper_lee 0:b16d94660a33 2806 #define CAU_BASE_PTRS { CAU }
Jasper_lee 0:b16d94660a33 2807
Jasper_lee 0:b16d94660a33 2808 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2809 -- CAU - Register accessor macros
Jasper_lee 0:b16d94660a33 2810 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2811
Jasper_lee 0:b16d94660a33 2812 /*!
Jasper_lee 0:b16d94660a33 2813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
Jasper_lee 0:b16d94660a33 2814 * @{
Jasper_lee 0:b16d94660a33 2815 */
Jasper_lee 0:b16d94660a33 2816
Jasper_lee 0:b16d94660a33 2817
Jasper_lee 0:b16d94660a33 2818 /* CAU - Register instance definitions */
Jasper_lee 0:b16d94660a33 2819 /* CAU */
Jasper_lee 0:b16d94660a33 2820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
Jasper_lee 0:b16d94660a33 2830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
Jasper_lee 0:b16d94660a33 2831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
Jasper_lee 0:b16d94660a33 2832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
Jasper_lee 0:b16d94660a33 2833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
Jasper_lee 0:b16d94660a33 2834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
Jasper_lee 0:b16d94660a33 2835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
Jasper_lee 0:b16d94660a33 2836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
Jasper_lee 0:b16d94660a33 2914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
Jasper_lee 0:b16d94660a33 2915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
Jasper_lee 0:b16d94660a33 2916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
Jasper_lee 0:b16d94660a33 2917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
Jasper_lee 0:b16d94660a33 2918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
Jasper_lee 0:b16d94660a33 2919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
Jasper_lee 0:b16d94660a33 2920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
Jasper_lee 0:b16d94660a33 2921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
Jasper_lee 0:b16d94660a33 2922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
Jasper_lee 0:b16d94660a33 2923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
Jasper_lee 0:b16d94660a33 2924
Jasper_lee 0:b16d94660a33 2925 /* CAU - Register array accessors */
Jasper_lee 0:b16d94660a33 2926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
Jasper_lee 0:b16d94660a33 2935
Jasper_lee 0:b16d94660a33 2936 /*!
Jasper_lee 0:b16d94660a33 2937 * @}
Jasper_lee 0:b16d94660a33 2938 */ /* end of group CAU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 2939
Jasper_lee 0:b16d94660a33 2940
Jasper_lee 0:b16d94660a33 2941 /*!
Jasper_lee 0:b16d94660a33 2942 * @}
Jasper_lee 0:b16d94660a33 2943 */ /* end of group CAU_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 2944
Jasper_lee 0:b16d94660a33 2945
Jasper_lee 0:b16d94660a33 2946 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2947 -- CMP Peripheral Access Layer
Jasper_lee 0:b16d94660a33 2948 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2949
Jasper_lee 0:b16d94660a33 2950 /*!
Jasper_lee 0:b16d94660a33 2951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Jasper_lee 0:b16d94660a33 2952 * @{
Jasper_lee 0:b16d94660a33 2953 */
Jasper_lee 0:b16d94660a33 2954
Jasper_lee 0:b16d94660a33 2955 /** CMP - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 2956 typedef struct {
Jasper_lee 0:b16d94660a33 2957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
Jasper_lee 0:b16d94660a33 2958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
Jasper_lee 0:b16d94660a33 2959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 2960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 2961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 2962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
Jasper_lee 0:b16d94660a33 2963 } CMP_Type, *CMP_MemMapPtr;
Jasper_lee 0:b16d94660a33 2964
Jasper_lee 0:b16d94660a33 2965 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2966 -- CMP - Register accessor macros
Jasper_lee 0:b16d94660a33 2967 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2968
Jasper_lee 0:b16d94660a33 2969 /*!
Jasper_lee 0:b16d94660a33 2970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Jasper_lee 0:b16d94660a33 2971 * @{
Jasper_lee 0:b16d94660a33 2972 */
Jasper_lee 0:b16d94660a33 2973
Jasper_lee 0:b16d94660a33 2974
Jasper_lee 0:b16d94660a33 2975 /* CMP - Register accessors */
Jasper_lee 0:b16d94660a33 2976 #define CMP_CR0_REG(base) ((base)->CR0)
Jasper_lee 0:b16d94660a33 2977 #define CMP_CR1_REG(base) ((base)->CR1)
Jasper_lee 0:b16d94660a33 2978 #define CMP_FPR_REG(base) ((base)->FPR)
Jasper_lee 0:b16d94660a33 2979 #define CMP_SCR_REG(base) ((base)->SCR)
Jasper_lee 0:b16d94660a33 2980 #define CMP_DACCR_REG(base) ((base)->DACCR)
Jasper_lee 0:b16d94660a33 2981 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
Jasper_lee 0:b16d94660a33 2982
Jasper_lee 0:b16d94660a33 2983 /*!
Jasper_lee 0:b16d94660a33 2984 * @}
Jasper_lee 0:b16d94660a33 2985 */ /* end of group CMP_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 2986
Jasper_lee 0:b16d94660a33 2987
Jasper_lee 0:b16d94660a33 2988 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 2989 -- CMP Register Masks
Jasper_lee 0:b16d94660a33 2990 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 2991
Jasper_lee 0:b16d94660a33 2992 /*!
Jasper_lee 0:b16d94660a33 2993 * @addtogroup CMP_Register_Masks CMP Register Masks
Jasper_lee 0:b16d94660a33 2994 * @{
Jasper_lee 0:b16d94660a33 2995 */
Jasper_lee 0:b16d94660a33 2996
Jasper_lee 0:b16d94660a33 2997 /* CR0 Bit Fields */
Jasper_lee 0:b16d94660a33 2998 #define CMP_CR0_HYSTCTR_MASK 0x3u
Jasper_lee 0:b16d94660a33 2999 #define CMP_CR0_HYSTCTR_SHIFT 0
Jasper_lee 0:b16d94660a33 3000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
Jasper_lee 0:b16d94660a33 3001 #define CMP_CR0_FILTER_CNT_MASK 0x70u
Jasper_lee 0:b16d94660a33 3002 #define CMP_CR0_FILTER_CNT_SHIFT 4
Jasper_lee 0:b16d94660a33 3003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
Jasper_lee 0:b16d94660a33 3004 /* CR1 Bit Fields */
Jasper_lee 0:b16d94660a33 3005 #define CMP_CR1_EN_MASK 0x1u
Jasper_lee 0:b16d94660a33 3006 #define CMP_CR1_EN_SHIFT 0
Jasper_lee 0:b16d94660a33 3007 #define CMP_CR1_OPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 3008 #define CMP_CR1_OPE_SHIFT 1
Jasper_lee 0:b16d94660a33 3009 #define CMP_CR1_COS_MASK 0x4u
Jasper_lee 0:b16d94660a33 3010 #define CMP_CR1_COS_SHIFT 2
Jasper_lee 0:b16d94660a33 3011 #define CMP_CR1_INV_MASK 0x8u
Jasper_lee 0:b16d94660a33 3012 #define CMP_CR1_INV_SHIFT 3
Jasper_lee 0:b16d94660a33 3013 #define CMP_CR1_PMODE_MASK 0x10u
Jasper_lee 0:b16d94660a33 3014 #define CMP_CR1_PMODE_SHIFT 4
Jasper_lee 0:b16d94660a33 3015 #define CMP_CR1_WE_MASK 0x40u
Jasper_lee 0:b16d94660a33 3016 #define CMP_CR1_WE_SHIFT 6
Jasper_lee 0:b16d94660a33 3017 #define CMP_CR1_SE_MASK 0x80u
Jasper_lee 0:b16d94660a33 3018 #define CMP_CR1_SE_SHIFT 7
Jasper_lee 0:b16d94660a33 3019 /* FPR Bit Fields */
Jasper_lee 0:b16d94660a33 3020 #define CMP_FPR_FILT_PER_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3021 #define CMP_FPR_FILT_PER_SHIFT 0
Jasper_lee 0:b16d94660a33 3022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
Jasper_lee 0:b16d94660a33 3023 /* SCR Bit Fields */
Jasper_lee 0:b16d94660a33 3024 #define CMP_SCR_COUT_MASK 0x1u
Jasper_lee 0:b16d94660a33 3025 #define CMP_SCR_COUT_SHIFT 0
Jasper_lee 0:b16d94660a33 3026 #define CMP_SCR_CFF_MASK 0x2u
Jasper_lee 0:b16d94660a33 3027 #define CMP_SCR_CFF_SHIFT 1
Jasper_lee 0:b16d94660a33 3028 #define CMP_SCR_CFR_MASK 0x4u
Jasper_lee 0:b16d94660a33 3029 #define CMP_SCR_CFR_SHIFT 2
Jasper_lee 0:b16d94660a33 3030 #define CMP_SCR_IEF_MASK 0x8u
Jasper_lee 0:b16d94660a33 3031 #define CMP_SCR_IEF_SHIFT 3
Jasper_lee 0:b16d94660a33 3032 #define CMP_SCR_IER_MASK 0x10u
Jasper_lee 0:b16d94660a33 3033 #define CMP_SCR_IER_SHIFT 4
Jasper_lee 0:b16d94660a33 3034 #define CMP_SCR_DMAEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 3035 #define CMP_SCR_DMAEN_SHIFT 6
Jasper_lee 0:b16d94660a33 3036 /* DACCR Bit Fields */
Jasper_lee 0:b16d94660a33 3037 #define CMP_DACCR_VOSEL_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 3038 #define CMP_DACCR_VOSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 3039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
Jasper_lee 0:b16d94660a33 3040 #define CMP_DACCR_VRSEL_MASK 0x40u
Jasper_lee 0:b16d94660a33 3041 #define CMP_DACCR_VRSEL_SHIFT 6
Jasper_lee 0:b16d94660a33 3042 #define CMP_DACCR_DACEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 3043 #define CMP_DACCR_DACEN_SHIFT 7
Jasper_lee 0:b16d94660a33 3044 /* MUXCR Bit Fields */
Jasper_lee 0:b16d94660a33 3045 #define CMP_MUXCR_MSEL_MASK 0x7u
Jasper_lee 0:b16d94660a33 3046 #define CMP_MUXCR_MSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 3047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
Jasper_lee 0:b16d94660a33 3048 #define CMP_MUXCR_PSEL_MASK 0x38u
Jasper_lee 0:b16d94660a33 3049 #define CMP_MUXCR_PSEL_SHIFT 3
Jasper_lee 0:b16d94660a33 3050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
Jasper_lee 0:b16d94660a33 3051 #define CMP_MUXCR_PSTM_MASK 0x80u
Jasper_lee 0:b16d94660a33 3052 #define CMP_MUXCR_PSTM_SHIFT 7
Jasper_lee 0:b16d94660a33 3053
Jasper_lee 0:b16d94660a33 3054 /*!
Jasper_lee 0:b16d94660a33 3055 * @}
Jasper_lee 0:b16d94660a33 3056 */ /* end of group CMP_Register_Masks */
Jasper_lee 0:b16d94660a33 3057
Jasper_lee 0:b16d94660a33 3058
Jasper_lee 0:b16d94660a33 3059 /* CMP - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 3060 /** Peripheral CMP0 base address */
Jasper_lee 0:b16d94660a33 3061 #define CMP0_BASE (0x40073000u)
Jasper_lee 0:b16d94660a33 3062 /** Peripheral CMP0 base pointer */
Jasper_lee 0:b16d94660a33 3063 #define CMP0 ((CMP_Type *)CMP0_BASE)
Jasper_lee 0:b16d94660a33 3064 #define CMP0_BASE_PTR (CMP0)
Jasper_lee 0:b16d94660a33 3065 /** Peripheral CMP1 base address */
Jasper_lee 0:b16d94660a33 3066 #define CMP1_BASE (0x40073008u)
Jasper_lee 0:b16d94660a33 3067 /** Peripheral CMP1 base pointer */
Jasper_lee 0:b16d94660a33 3068 #define CMP1 ((CMP_Type *)CMP1_BASE)
Jasper_lee 0:b16d94660a33 3069 #define CMP1_BASE_PTR (CMP1)
Jasper_lee 0:b16d94660a33 3070 /** Peripheral CMP2 base address */
Jasper_lee 0:b16d94660a33 3071 #define CMP2_BASE (0x40073010u)
Jasper_lee 0:b16d94660a33 3072 /** Peripheral CMP2 base pointer */
Jasper_lee 0:b16d94660a33 3073 #define CMP2 ((CMP_Type *)CMP2_BASE)
Jasper_lee 0:b16d94660a33 3074 #define CMP2_BASE_PTR (CMP2)
Jasper_lee 0:b16d94660a33 3075 /** Array initializer of CMP peripheral base addresses */
Jasper_lee 0:b16d94660a33 3076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
Jasper_lee 0:b16d94660a33 3077 /** Array initializer of CMP peripheral base pointers */
Jasper_lee 0:b16d94660a33 3078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
Jasper_lee 0:b16d94660a33 3079 /** Interrupt vectors for the CMP peripheral type */
Jasper_lee 0:b16d94660a33 3080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
Jasper_lee 0:b16d94660a33 3081
Jasper_lee 0:b16d94660a33 3082 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3083 -- CMP - Register accessor macros
Jasper_lee 0:b16d94660a33 3084 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3085
Jasper_lee 0:b16d94660a33 3086 /*!
Jasper_lee 0:b16d94660a33 3087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Jasper_lee 0:b16d94660a33 3088 * @{
Jasper_lee 0:b16d94660a33 3089 */
Jasper_lee 0:b16d94660a33 3090
Jasper_lee 0:b16d94660a33 3091
Jasper_lee 0:b16d94660a33 3092 /* CMP - Register instance definitions */
Jasper_lee 0:b16d94660a33 3093 /* CMP0 */
Jasper_lee 0:b16d94660a33 3094 #define CMP0_CR0 CMP_CR0_REG(CMP0)
Jasper_lee 0:b16d94660a33 3095 #define CMP0_CR1 CMP_CR1_REG(CMP0)
Jasper_lee 0:b16d94660a33 3096 #define CMP0_FPR CMP_FPR_REG(CMP0)
Jasper_lee 0:b16d94660a33 3097 #define CMP0_SCR CMP_SCR_REG(CMP0)
Jasper_lee 0:b16d94660a33 3098 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
Jasper_lee 0:b16d94660a33 3099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
Jasper_lee 0:b16d94660a33 3100 /* CMP1 */
Jasper_lee 0:b16d94660a33 3101 #define CMP1_CR0 CMP_CR0_REG(CMP1)
Jasper_lee 0:b16d94660a33 3102 #define CMP1_CR1 CMP_CR1_REG(CMP1)
Jasper_lee 0:b16d94660a33 3103 #define CMP1_FPR CMP_FPR_REG(CMP1)
Jasper_lee 0:b16d94660a33 3104 #define CMP1_SCR CMP_SCR_REG(CMP1)
Jasper_lee 0:b16d94660a33 3105 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
Jasper_lee 0:b16d94660a33 3106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
Jasper_lee 0:b16d94660a33 3107 /* CMP2 */
Jasper_lee 0:b16d94660a33 3108 #define CMP2_CR0 CMP_CR0_REG(CMP2)
Jasper_lee 0:b16d94660a33 3109 #define CMP2_CR1 CMP_CR1_REG(CMP2)
Jasper_lee 0:b16d94660a33 3110 #define CMP2_FPR CMP_FPR_REG(CMP2)
Jasper_lee 0:b16d94660a33 3111 #define CMP2_SCR CMP_SCR_REG(CMP2)
Jasper_lee 0:b16d94660a33 3112 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
Jasper_lee 0:b16d94660a33 3113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
Jasper_lee 0:b16d94660a33 3114
Jasper_lee 0:b16d94660a33 3115 /*!
Jasper_lee 0:b16d94660a33 3116 * @}
Jasper_lee 0:b16d94660a33 3117 */ /* end of group CMP_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3118
Jasper_lee 0:b16d94660a33 3119
Jasper_lee 0:b16d94660a33 3120 /*!
Jasper_lee 0:b16d94660a33 3121 * @}
Jasper_lee 0:b16d94660a33 3122 */ /* end of group CMP_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 3123
Jasper_lee 0:b16d94660a33 3124
Jasper_lee 0:b16d94660a33 3125 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3126 -- CMT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3127 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3128
Jasper_lee 0:b16d94660a33 3129 /*!
Jasper_lee 0:b16d94660a33 3130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3131 * @{
Jasper_lee 0:b16d94660a33 3132 */
Jasper_lee 0:b16d94660a33 3133
Jasper_lee 0:b16d94660a33 3134 /** CMT - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 3135 typedef struct {
Jasper_lee 0:b16d94660a33 3136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
Jasper_lee 0:b16d94660a33 3137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
Jasper_lee 0:b16d94660a33 3138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
Jasper_lee 0:b16d94660a33 3139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
Jasper_lee 0:b16d94660a33 3140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 3141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
Jasper_lee 0:b16d94660a33 3142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
Jasper_lee 0:b16d94660a33 3143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
Jasper_lee 0:b16d94660a33 3144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
Jasper_lee 0:b16d94660a33 3145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
Jasper_lee 0:b16d94660a33 3146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
Jasper_lee 0:b16d94660a33 3147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
Jasper_lee 0:b16d94660a33 3148 } CMT_Type, *CMT_MemMapPtr;
Jasper_lee 0:b16d94660a33 3149
Jasper_lee 0:b16d94660a33 3150 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3151 -- CMT - Register accessor macros
Jasper_lee 0:b16d94660a33 3152 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3153
Jasper_lee 0:b16d94660a33 3154 /*!
Jasper_lee 0:b16d94660a33 3155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
Jasper_lee 0:b16d94660a33 3156 * @{
Jasper_lee 0:b16d94660a33 3157 */
Jasper_lee 0:b16d94660a33 3158
Jasper_lee 0:b16d94660a33 3159
Jasper_lee 0:b16d94660a33 3160 /* CMT - Register accessors */
Jasper_lee 0:b16d94660a33 3161 #define CMT_CGH1_REG(base) ((base)->CGH1)
Jasper_lee 0:b16d94660a33 3162 #define CMT_CGL1_REG(base) ((base)->CGL1)
Jasper_lee 0:b16d94660a33 3163 #define CMT_CGH2_REG(base) ((base)->CGH2)
Jasper_lee 0:b16d94660a33 3164 #define CMT_CGL2_REG(base) ((base)->CGL2)
Jasper_lee 0:b16d94660a33 3165 #define CMT_OC_REG(base) ((base)->OC)
Jasper_lee 0:b16d94660a33 3166 #define CMT_MSC_REG(base) ((base)->MSC)
Jasper_lee 0:b16d94660a33 3167 #define CMT_CMD1_REG(base) ((base)->CMD1)
Jasper_lee 0:b16d94660a33 3168 #define CMT_CMD2_REG(base) ((base)->CMD2)
Jasper_lee 0:b16d94660a33 3169 #define CMT_CMD3_REG(base) ((base)->CMD3)
Jasper_lee 0:b16d94660a33 3170 #define CMT_CMD4_REG(base) ((base)->CMD4)
Jasper_lee 0:b16d94660a33 3171 #define CMT_PPS_REG(base) ((base)->PPS)
Jasper_lee 0:b16d94660a33 3172 #define CMT_DMA_REG(base) ((base)->DMA)
Jasper_lee 0:b16d94660a33 3173
Jasper_lee 0:b16d94660a33 3174 /*!
Jasper_lee 0:b16d94660a33 3175 * @}
Jasper_lee 0:b16d94660a33 3176 */ /* end of group CMT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3177
Jasper_lee 0:b16d94660a33 3178
Jasper_lee 0:b16d94660a33 3179 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3180 -- CMT Register Masks
Jasper_lee 0:b16d94660a33 3181 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3182
Jasper_lee 0:b16d94660a33 3183 /*!
Jasper_lee 0:b16d94660a33 3184 * @addtogroup CMT_Register_Masks CMT Register Masks
Jasper_lee 0:b16d94660a33 3185 * @{
Jasper_lee 0:b16d94660a33 3186 */
Jasper_lee 0:b16d94660a33 3187
Jasper_lee 0:b16d94660a33 3188 /* CGH1 Bit Fields */
Jasper_lee 0:b16d94660a33 3189 #define CMT_CGH1_PH_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3190 #define CMT_CGH1_PH_SHIFT 0
Jasper_lee 0:b16d94660a33 3191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
Jasper_lee 0:b16d94660a33 3192 /* CGL1 Bit Fields */
Jasper_lee 0:b16d94660a33 3193 #define CMT_CGL1_PL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3194 #define CMT_CGL1_PL_SHIFT 0
Jasper_lee 0:b16d94660a33 3195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
Jasper_lee 0:b16d94660a33 3196 /* CGH2 Bit Fields */
Jasper_lee 0:b16d94660a33 3197 #define CMT_CGH2_SH_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3198 #define CMT_CGH2_SH_SHIFT 0
Jasper_lee 0:b16d94660a33 3199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
Jasper_lee 0:b16d94660a33 3200 /* CGL2 Bit Fields */
Jasper_lee 0:b16d94660a33 3201 #define CMT_CGL2_SL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3202 #define CMT_CGL2_SL_SHIFT 0
Jasper_lee 0:b16d94660a33 3203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
Jasper_lee 0:b16d94660a33 3204 /* OC Bit Fields */
Jasper_lee 0:b16d94660a33 3205 #define CMT_OC_IROPEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 3206 #define CMT_OC_IROPEN_SHIFT 5
Jasper_lee 0:b16d94660a33 3207 #define CMT_OC_CMTPOL_MASK 0x40u
Jasper_lee 0:b16d94660a33 3208 #define CMT_OC_CMTPOL_SHIFT 6
Jasper_lee 0:b16d94660a33 3209 #define CMT_OC_IROL_MASK 0x80u
Jasper_lee 0:b16d94660a33 3210 #define CMT_OC_IROL_SHIFT 7
Jasper_lee 0:b16d94660a33 3211 /* MSC Bit Fields */
Jasper_lee 0:b16d94660a33 3212 #define CMT_MSC_MCGEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 3213 #define CMT_MSC_MCGEN_SHIFT 0
Jasper_lee 0:b16d94660a33 3214 #define CMT_MSC_EOCIE_MASK 0x2u
Jasper_lee 0:b16d94660a33 3215 #define CMT_MSC_EOCIE_SHIFT 1
Jasper_lee 0:b16d94660a33 3216 #define CMT_MSC_FSK_MASK 0x4u
Jasper_lee 0:b16d94660a33 3217 #define CMT_MSC_FSK_SHIFT 2
Jasper_lee 0:b16d94660a33 3218 #define CMT_MSC_BASE_MASK 0x8u
Jasper_lee 0:b16d94660a33 3219 #define CMT_MSC_BASE_SHIFT 3
Jasper_lee 0:b16d94660a33 3220 #define CMT_MSC_EXSPC_MASK 0x10u
Jasper_lee 0:b16d94660a33 3221 #define CMT_MSC_EXSPC_SHIFT 4
Jasper_lee 0:b16d94660a33 3222 #define CMT_MSC_CMTDIV_MASK 0x60u
Jasper_lee 0:b16d94660a33 3223 #define CMT_MSC_CMTDIV_SHIFT 5
Jasper_lee 0:b16d94660a33 3224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
Jasper_lee 0:b16d94660a33 3225 #define CMT_MSC_EOCF_MASK 0x80u
Jasper_lee 0:b16d94660a33 3226 #define CMT_MSC_EOCF_SHIFT 7
Jasper_lee 0:b16d94660a33 3227 /* CMD1 Bit Fields */
Jasper_lee 0:b16d94660a33 3228 #define CMT_CMD1_MB_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3229 #define CMT_CMD1_MB_SHIFT 0
Jasper_lee 0:b16d94660a33 3230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
Jasper_lee 0:b16d94660a33 3231 /* CMD2 Bit Fields */
Jasper_lee 0:b16d94660a33 3232 #define CMT_CMD2_MB_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3233 #define CMT_CMD2_MB_SHIFT 0
Jasper_lee 0:b16d94660a33 3234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
Jasper_lee 0:b16d94660a33 3235 /* CMD3 Bit Fields */
Jasper_lee 0:b16d94660a33 3236 #define CMT_CMD3_SB_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3237 #define CMT_CMD3_SB_SHIFT 0
Jasper_lee 0:b16d94660a33 3238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
Jasper_lee 0:b16d94660a33 3239 /* CMD4 Bit Fields */
Jasper_lee 0:b16d94660a33 3240 #define CMT_CMD4_SB_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3241 #define CMT_CMD4_SB_SHIFT 0
Jasper_lee 0:b16d94660a33 3242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
Jasper_lee 0:b16d94660a33 3243 /* PPS Bit Fields */
Jasper_lee 0:b16d94660a33 3244 #define CMT_PPS_PPSDIV_MASK 0xFu
Jasper_lee 0:b16d94660a33 3245 #define CMT_PPS_PPSDIV_SHIFT 0
Jasper_lee 0:b16d94660a33 3246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
Jasper_lee 0:b16d94660a33 3247 /* DMA Bit Fields */
Jasper_lee 0:b16d94660a33 3248 #define CMT_DMA_DMA_MASK 0x1u
Jasper_lee 0:b16d94660a33 3249 #define CMT_DMA_DMA_SHIFT 0
Jasper_lee 0:b16d94660a33 3250
Jasper_lee 0:b16d94660a33 3251 /*!
Jasper_lee 0:b16d94660a33 3252 * @}
Jasper_lee 0:b16d94660a33 3253 */ /* end of group CMT_Register_Masks */
Jasper_lee 0:b16d94660a33 3254
Jasper_lee 0:b16d94660a33 3255
Jasper_lee 0:b16d94660a33 3256 /* CMT - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 3257 /** Peripheral CMT base address */
Jasper_lee 0:b16d94660a33 3258 #define CMT_BASE (0x40062000u)
Jasper_lee 0:b16d94660a33 3259 /** Peripheral CMT base pointer */
Jasper_lee 0:b16d94660a33 3260 #define CMT ((CMT_Type *)CMT_BASE)
Jasper_lee 0:b16d94660a33 3261 #define CMT_BASE_PTR (CMT)
Jasper_lee 0:b16d94660a33 3262 /** Array initializer of CMT peripheral base addresses */
Jasper_lee 0:b16d94660a33 3263 #define CMT_BASE_ADDRS { CMT_BASE }
Jasper_lee 0:b16d94660a33 3264 /** Array initializer of CMT peripheral base pointers */
Jasper_lee 0:b16d94660a33 3265 #define CMT_BASE_PTRS { CMT }
Jasper_lee 0:b16d94660a33 3266 /** Interrupt vectors for the CMT peripheral type */
Jasper_lee 0:b16d94660a33 3267 #define CMT_IRQS { CMT_IRQn }
Jasper_lee 0:b16d94660a33 3268
Jasper_lee 0:b16d94660a33 3269 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3270 -- CMT - Register accessor macros
Jasper_lee 0:b16d94660a33 3271 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3272
Jasper_lee 0:b16d94660a33 3273 /*!
Jasper_lee 0:b16d94660a33 3274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
Jasper_lee 0:b16d94660a33 3275 * @{
Jasper_lee 0:b16d94660a33 3276 */
Jasper_lee 0:b16d94660a33 3277
Jasper_lee 0:b16d94660a33 3278
Jasper_lee 0:b16d94660a33 3279 /* CMT - Register instance definitions */
Jasper_lee 0:b16d94660a33 3280 /* CMT */
Jasper_lee 0:b16d94660a33 3281 #define CMT_CGH1 CMT_CGH1_REG(CMT)
Jasper_lee 0:b16d94660a33 3282 #define CMT_CGL1 CMT_CGL1_REG(CMT)
Jasper_lee 0:b16d94660a33 3283 #define CMT_CGH2 CMT_CGH2_REG(CMT)
Jasper_lee 0:b16d94660a33 3284 #define CMT_CGL2 CMT_CGL2_REG(CMT)
Jasper_lee 0:b16d94660a33 3285 #define CMT_OC CMT_OC_REG(CMT)
Jasper_lee 0:b16d94660a33 3286 #define CMT_MSC CMT_MSC_REG(CMT)
Jasper_lee 0:b16d94660a33 3287 #define CMT_CMD1 CMT_CMD1_REG(CMT)
Jasper_lee 0:b16d94660a33 3288 #define CMT_CMD2 CMT_CMD2_REG(CMT)
Jasper_lee 0:b16d94660a33 3289 #define CMT_CMD3 CMT_CMD3_REG(CMT)
Jasper_lee 0:b16d94660a33 3290 #define CMT_CMD4 CMT_CMD4_REG(CMT)
Jasper_lee 0:b16d94660a33 3291 #define CMT_PPS CMT_PPS_REG(CMT)
Jasper_lee 0:b16d94660a33 3292 #define CMT_DMA CMT_DMA_REG(CMT)
Jasper_lee 0:b16d94660a33 3293
Jasper_lee 0:b16d94660a33 3294 /*!
Jasper_lee 0:b16d94660a33 3295 * @}
Jasper_lee 0:b16d94660a33 3296 */ /* end of group CMT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3297
Jasper_lee 0:b16d94660a33 3298
Jasper_lee 0:b16d94660a33 3299 /*!
Jasper_lee 0:b16d94660a33 3300 * @}
Jasper_lee 0:b16d94660a33 3301 */ /* end of group CMT_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 3302
Jasper_lee 0:b16d94660a33 3303
Jasper_lee 0:b16d94660a33 3304 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3305 -- CRC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3306 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3307
Jasper_lee 0:b16d94660a33 3308 /*!
Jasper_lee 0:b16d94660a33 3309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3310 * @{
Jasper_lee 0:b16d94660a33 3311 */
Jasper_lee 0:b16d94660a33 3312
Jasper_lee 0:b16d94660a33 3313 /** CRC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 3314 typedef struct {
Jasper_lee 0:b16d94660a33 3315 union { /* offset: 0x0 */
Jasper_lee 0:b16d94660a33 3316 struct { /* offset: 0x0 */
Jasper_lee 0:b16d94660a33 3317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
Jasper_lee 0:b16d94660a33 3318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
Jasper_lee 0:b16d94660a33 3319 } ACCESS16BIT;
Jasper_lee 0:b16d94660a33 3320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 3321 struct { /* offset: 0x0 */
Jasper_lee 0:b16d94660a33 3322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
Jasper_lee 0:b16d94660a33 3323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
Jasper_lee 0:b16d94660a33 3324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
Jasper_lee 0:b16d94660a33 3325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
Jasper_lee 0:b16d94660a33 3326 } ACCESS8BIT;
Jasper_lee 0:b16d94660a33 3327 };
Jasper_lee 0:b16d94660a33 3328 union { /* offset: 0x4 */
Jasper_lee 0:b16d94660a33 3329 struct { /* offset: 0x4 */
Jasper_lee 0:b16d94660a33 3330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
Jasper_lee 0:b16d94660a33 3331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
Jasper_lee 0:b16d94660a33 3332 } GPOLY_ACCESS16BIT;
Jasper_lee 0:b16d94660a33 3333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 3334 struct { /* offset: 0x4 */
Jasper_lee 0:b16d94660a33 3335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
Jasper_lee 0:b16d94660a33 3336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
Jasper_lee 0:b16d94660a33 3337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
Jasper_lee 0:b16d94660a33 3338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
Jasper_lee 0:b16d94660a33 3339 } GPOLY_ACCESS8BIT;
Jasper_lee 0:b16d94660a33 3340 };
Jasper_lee 0:b16d94660a33 3341 union { /* offset: 0x8 */
Jasper_lee 0:b16d94660a33 3342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 3343 struct { /* offset: 0x8 */
Jasper_lee 0:b16d94660a33 3344 uint8_t RESERVED_0[3];
Jasper_lee 0:b16d94660a33 3345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
Jasper_lee 0:b16d94660a33 3346 } CTRL_ACCESS8BIT;
Jasper_lee 0:b16d94660a33 3347 };
Jasper_lee 0:b16d94660a33 3348 } CRC_Type, *CRC_MemMapPtr;
Jasper_lee 0:b16d94660a33 3349
Jasper_lee 0:b16d94660a33 3350 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3351 -- CRC - Register accessor macros
Jasper_lee 0:b16d94660a33 3352 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3353
Jasper_lee 0:b16d94660a33 3354 /*!
Jasper_lee 0:b16d94660a33 3355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
Jasper_lee 0:b16d94660a33 3356 * @{
Jasper_lee 0:b16d94660a33 3357 */
Jasper_lee 0:b16d94660a33 3358
Jasper_lee 0:b16d94660a33 3359
Jasper_lee 0:b16d94660a33 3360 /* CRC - Register accessors */
Jasper_lee 0:b16d94660a33 3361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
Jasper_lee 0:b16d94660a33 3362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
Jasper_lee 0:b16d94660a33 3363 #define CRC_DATA_REG(base) ((base)->DATA)
Jasper_lee 0:b16d94660a33 3364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
Jasper_lee 0:b16d94660a33 3365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
Jasper_lee 0:b16d94660a33 3366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
Jasper_lee 0:b16d94660a33 3367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
Jasper_lee 0:b16d94660a33 3368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
Jasper_lee 0:b16d94660a33 3369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
Jasper_lee 0:b16d94660a33 3370 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
Jasper_lee 0:b16d94660a33 3371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
Jasper_lee 0:b16d94660a33 3372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
Jasper_lee 0:b16d94660a33 3373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
Jasper_lee 0:b16d94660a33 3374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
Jasper_lee 0:b16d94660a33 3375 #define CRC_CTRL_REG(base) ((base)->CTRL)
Jasper_lee 0:b16d94660a33 3376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
Jasper_lee 0:b16d94660a33 3377
Jasper_lee 0:b16d94660a33 3378 /*!
Jasper_lee 0:b16d94660a33 3379 * @}
Jasper_lee 0:b16d94660a33 3380 */ /* end of group CRC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3381
Jasper_lee 0:b16d94660a33 3382
Jasper_lee 0:b16d94660a33 3383 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3384 -- CRC Register Masks
Jasper_lee 0:b16d94660a33 3385 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3386
Jasper_lee 0:b16d94660a33 3387 /*!
Jasper_lee 0:b16d94660a33 3388 * @addtogroup CRC_Register_Masks CRC Register Masks
Jasper_lee 0:b16d94660a33 3389 * @{
Jasper_lee 0:b16d94660a33 3390 */
Jasper_lee 0:b16d94660a33 3391
Jasper_lee 0:b16d94660a33 3392 /* DATAL Bit Fields */
Jasper_lee 0:b16d94660a33 3393 #define CRC_DATAL_DATAL_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 3394 #define CRC_DATAL_DATAL_SHIFT 0
Jasper_lee 0:b16d94660a33 3395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
Jasper_lee 0:b16d94660a33 3396 /* DATAH Bit Fields */
Jasper_lee 0:b16d94660a33 3397 #define CRC_DATAH_DATAH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 3398 #define CRC_DATAH_DATAH_SHIFT 0
Jasper_lee 0:b16d94660a33 3399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
Jasper_lee 0:b16d94660a33 3400 /* DATA Bit Fields */
Jasper_lee 0:b16d94660a33 3401 #define CRC_DATA_LL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3402 #define CRC_DATA_LL_SHIFT 0
Jasper_lee 0:b16d94660a33 3403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
Jasper_lee 0:b16d94660a33 3404 #define CRC_DATA_LU_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 3405 #define CRC_DATA_LU_SHIFT 8
Jasper_lee 0:b16d94660a33 3406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
Jasper_lee 0:b16d94660a33 3407 #define CRC_DATA_HL_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 3408 #define CRC_DATA_HL_SHIFT 16
Jasper_lee 0:b16d94660a33 3409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
Jasper_lee 0:b16d94660a33 3410 #define CRC_DATA_HU_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 3411 #define CRC_DATA_HU_SHIFT 24
Jasper_lee 0:b16d94660a33 3412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
Jasper_lee 0:b16d94660a33 3413 /* DATALL Bit Fields */
Jasper_lee 0:b16d94660a33 3414 #define CRC_DATALL_DATALL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3415 #define CRC_DATALL_DATALL_SHIFT 0
Jasper_lee 0:b16d94660a33 3416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
Jasper_lee 0:b16d94660a33 3417 /* DATALU Bit Fields */
Jasper_lee 0:b16d94660a33 3418 #define CRC_DATALU_DATALU_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3419 #define CRC_DATALU_DATALU_SHIFT 0
Jasper_lee 0:b16d94660a33 3420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
Jasper_lee 0:b16d94660a33 3421 /* DATAHL Bit Fields */
Jasper_lee 0:b16d94660a33 3422 #define CRC_DATAHL_DATAHL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3423 #define CRC_DATAHL_DATAHL_SHIFT 0
Jasper_lee 0:b16d94660a33 3424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
Jasper_lee 0:b16d94660a33 3425 /* DATAHU Bit Fields */
Jasper_lee 0:b16d94660a33 3426 #define CRC_DATAHU_DATAHU_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3427 #define CRC_DATAHU_DATAHU_SHIFT 0
Jasper_lee 0:b16d94660a33 3428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
Jasper_lee 0:b16d94660a33 3429 /* GPOLYL Bit Fields */
Jasper_lee 0:b16d94660a33 3430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 3431 #define CRC_GPOLYL_GPOLYL_SHIFT 0
Jasper_lee 0:b16d94660a33 3432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
Jasper_lee 0:b16d94660a33 3433 /* GPOLYH Bit Fields */
Jasper_lee 0:b16d94660a33 3434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 3435 #define CRC_GPOLYH_GPOLYH_SHIFT 0
Jasper_lee 0:b16d94660a33 3436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
Jasper_lee 0:b16d94660a33 3437 /* GPOLY Bit Fields */
Jasper_lee 0:b16d94660a33 3438 #define CRC_GPOLY_LOW_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 3439 #define CRC_GPOLY_LOW_SHIFT 0
Jasper_lee 0:b16d94660a33 3440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
Jasper_lee 0:b16d94660a33 3441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 3442 #define CRC_GPOLY_HIGH_SHIFT 16
Jasper_lee 0:b16d94660a33 3443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
Jasper_lee 0:b16d94660a33 3444 /* GPOLYLL Bit Fields */
Jasper_lee 0:b16d94660a33 3445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
Jasper_lee 0:b16d94660a33 3447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
Jasper_lee 0:b16d94660a33 3448 /* GPOLYLU Bit Fields */
Jasper_lee 0:b16d94660a33 3449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
Jasper_lee 0:b16d94660a33 3451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
Jasper_lee 0:b16d94660a33 3452 /* GPOLYHL Bit Fields */
Jasper_lee 0:b16d94660a33 3453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
Jasper_lee 0:b16d94660a33 3455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
Jasper_lee 0:b16d94660a33 3456 /* GPOLYHU Bit Fields */
Jasper_lee 0:b16d94660a33 3457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
Jasper_lee 0:b16d94660a33 3459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
Jasper_lee 0:b16d94660a33 3460 /* CTRL Bit Fields */
Jasper_lee 0:b16d94660a33 3461 #define CRC_CTRL_TCRC_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 3462 #define CRC_CTRL_TCRC_SHIFT 24
Jasper_lee 0:b16d94660a33 3463 #define CRC_CTRL_WAS_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 3464 #define CRC_CTRL_WAS_SHIFT 25
Jasper_lee 0:b16d94660a33 3465 #define CRC_CTRL_FXOR_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 3466 #define CRC_CTRL_FXOR_SHIFT 26
Jasper_lee 0:b16d94660a33 3467 #define CRC_CTRL_TOTR_MASK 0x30000000u
Jasper_lee 0:b16d94660a33 3468 #define CRC_CTRL_TOTR_SHIFT 28
Jasper_lee 0:b16d94660a33 3469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
Jasper_lee 0:b16d94660a33 3470 #define CRC_CTRL_TOT_MASK 0xC0000000u
Jasper_lee 0:b16d94660a33 3471 #define CRC_CTRL_TOT_SHIFT 30
Jasper_lee 0:b16d94660a33 3472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
Jasper_lee 0:b16d94660a33 3473 /* CTRLHU Bit Fields */
Jasper_lee 0:b16d94660a33 3474 #define CRC_CTRLHU_TCRC_MASK 0x1u
Jasper_lee 0:b16d94660a33 3475 #define CRC_CTRLHU_TCRC_SHIFT 0
Jasper_lee 0:b16d94660a33 3476 #define CRC_CTRLHU_WAS_MASK 0x2u
Jasper_lee 0:b16d94660a33 3477 #define CRC_CTRLHU_WAS_SHIFT 1
Jasper_lee 0:b16d94660a33 3478 #define CRC_CTRLHU_FXOR_MASK 0x4u
Jasper_lee 0:b16d94660a33 3479 #define CRC_CTRLHU_FXOR_SHIFT 2
Jasper_lee 0:b16d94660a33 3480 #define CRC_CTRLHU_TOTR_MASK 0x30u
Jasper_lee 0:b16d94660a33 3481 #define CRC_CTRLHU_TOTR_SHIFT 4
Jasper_lee 0:b16d94660a33 3482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
Jasper_lee 0:b16d94660a33 3483 #define CRC_CTRLHU_TOT_MASK 0xC0u
Jasper_lee 0:b16d94660a33 3484 #define CRC_CTRLHU_TOT_SHIFT 6
Jasper_lee 0:b16d94660a33 3485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
Jasper_lee 0:b16d94660a33 3486
Jasper_lee 0:b16d94660a33 3487 /*!
Jasper_lee 0:b16d94660a33 3488 * @}
Jasper_lee 0:b16d94660a33 3489 */ /* end of group CRC_Register_Masks */
Jasper_lee 0:b16d94660a33 3490
Jasper_lee 0:b16d94660a33 3491
Jasper_lee 0:b16d94660a33 3492 /* CRC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 3493 /** Peripheral CRC base address */
Jasper_lee 0:b16d94660a33 3494 #define CRC_BASE (0x40032000u)
Jasper_lee 0:b16d94660a33 3495 /** Peripheral CRC base pointer */
Jasper_lee 0:b16d94660a33 3496 #define CRC0 ((CRC_Type *)CRC_BASE)
Jasper_lee 0:b16d94660a33 3497 #define CRC_BASE_PTR (CRC0)
Jasper_lee 0:b16d94660a33 3498 /** Array initializer of CRC peripheral base addresses */
Jasper_lee 0:b16d94660a33 3499 #define CRC_BASE_ADDRS { CRC_BASE }
Jasper_lee 0:b16d94660a33 3500 /** Array initializer of CRC peripheral base pointers */
Jasper_lee 0:b16d94660a33 3501 #define CRC_BASE_PTRS { CRC0 }
Jasper_lee 0:b16d94660a33 3502
Jasper_lee 0:b16d94660a33 3503 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3504 -- CRC - Register accessor macros
Jasper_lee 0:b16d94660a33 3505 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3506
Jasper_lee 0:b16d94660a33 3507 /*!
Jasper_lee 0:b16d94660a33 3508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
Jasper_lee 0:b16d94660a33 3509 * @{
Jasper_lee 0:b16d94660a33 3510 */
Jasper_lee 0:b16d94660a33 3511
Jasper_lee 0:b16d94660a33 3512
Jasper_lee 0:b16d94660a33 3513 /* CRC - Register instance definitions */
Jasper_lee 0:b16d94660a33 3514 /* CRC */
Jasper_lee 0:b16d94660a33 3515 #define CRC_DATA CRC_DATA_REG(CRC0)
Jasper_lee 0:b16d94660a33 3516 #define CRC_DATAL CRC_DATAL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3517 #define CRC_DATALL CRC_DATALL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3518 #define CRC_DATALU CRC_DATALU_REG(CRC0)
Jasper_lee 0:b16d94660a33 3519 #define CRC_DATAH CRC_DATAH_REG(CRC0)
Jasper_lee 0:b16d94660a33 3520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
Jasper_lee 0:b16d94660a33 3522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
Jasper_lee 0:b16d94660a33 3523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
Jasper_lee 0:b16d94660a33 3526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
Jasper_lee 0:b16d94660a33 3527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
Jasper_lee 0:b16d94660a33 3529 #define CRC_CTRL CRC_CTRL_REG(CRC0)
Jasper_lee 0:b16d94660a33 3530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
Jasper_lee 0:b16d94660a33 3531
Jasper_lee 0:b16d94660a33 3532 /*!
Jasper_lee 0:b16d94660a33 3533 * @}
Jasper_lee 0:b16d94660a33 3534 */ /* end of group CRC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3535
Jasper_lee 0:b16d94660a33 3536
Jasper_lee 0:b16d94660a33 3537 /*!
Jasper_lee 0:b16d94660a33 3538 * @}
Jasper_lee 0:b16d94660a33 3539 */ /* end of group CRC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 3540
Jasper_lee 0:b16d94660a33 3541
Jasper_lee 0:b16d94660a33 3542 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3543 -- DAC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3544 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3545
Jasper_lee 0:b16d94660a33 3546 /*!
Jasper_lee 0:b16d94660a33 3547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3548 * @{
Jasper_lee 0:b16d94660a33 3549 */
Jasper_lee 0:b16d94660a33 3550
Jasper_lee 0:b16d94660a33 3551 /** DAC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 3552 typedef struct {
Jasper_lee 0:b16d94660a33 3553 struct { /* offset: 0x0, array step: 0x2 */
Jasper_lee 0:b16d94660a33 3554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
Jasper_lee 0:b16d94660a33 3555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
Jasper_lee 0:b16d94660a33 3556 } DAT[16];
Jasper_lee 0:b16d94660a33 3557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
Jasper_lee 0:b16d94660a33 3558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
Jasper_lee 0:b16d94660a33 3559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
Jasper_lee 0:b16d94660a33 3560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
Jasper_lee 0:b16d94660a33 3561 } DAC_Type, *DAC_MemMapPtr;
Jasper_lee 0:b16d94660a33 3562
Jasper_lee 0:b16d94660a33 3563 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3564 -- DAC - Register accessor macros
Jasper_lee 0:b16d94660a33 3565 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3566
Jasper_lee 0:b16d94660a33 3567 /*!
Jasper_lee 0:b16d94660a33 3568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Jasper_lee 0:b16d94660a33 3569 * @{
Jasper_lee 0:b16d94660a33 3570 */
Jasper_lee 0:b16d94660a33 3571
Jasper_lee 0:b16d94660a33 3572
Jasper_lee 0:b16d94660a33 3573 /* DAC - Register accessors */
Jasper_lee 0:b16d94660a33 3574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
Jasper_lee 0:b16d94660a33 3575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
Jasper_lee 0:b16d94660a33 3576 #define DAC_SR_REG(base) ((base)->SR)
Jasper_lee 0:b16d94660a33 3577 #define DAC_C0_REG(base) ((base)->C0)
Jasper_lee 0:b16d94660a33 3578 #define DAC_C1_REG(base) ((base)->C1)
Jasper_lee 0:b16d94660a33 3579 #define DAC_C2_REG(base) ((base)->C2)
Jasper_lee 0:b16d94660a33 3580
Jasper_lee 0:b16d94660a33 3581 /*!
Jasper_lee 0:b16d94660a33 3582 * @}
Jasper_lee 0:b16d94660a33 3583 */ /* end of group DAC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3584
Jasper_lee 0:b16d94660a33 3585
Jasper_lee 0:b16d94660a33 3586 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3587 -- DAC Register Masks
Jasper_lee 0:b16d94660a33 3588 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3589
Jasper_lee 0:b16d94660a33 3590 /*!
Jasper_lee 0:b16d94660a33 3591 * @addtogroup DAC_Register_Masks DAC Register Masks
Jasper_lee 0:b16d94660a33 3592 * @{
Jasper_lee 0:b16d94660a33 3593 */
Jasper_lee 0:b16d94660a33 3594
Jasper_lee 0:b16d94660a33 3595 /* DATL Bit Fields */
Jasper_lee 0:b16d94660a33 3596 #define DAC_DATL_DATA0_MASK 0xFFu
Jasper_lee 0:b16d94660a33 3597 #define DAC_DATL_DATA0_SHIFT 0
Jasper_lee 0:b16d94660a33 3598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
Jasper_lee 0:b16d94660a33 3599 /* DATH Bit Fields */
Jasper_lee 0:b16d94660a33 3600 #define DAC_DATH_DATA1_MASK 0xFu
Jasper_lee 0:b16d94660a33 3601 #define DAC_DATH_DATA1_SHIFT 0
Jasper_lee 0:b16d94660a33 3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
Jasper_lee 0:b16d94660a33 3603 /* SR Bit Fields */
Jasper_lee 0:b16d94660a33 3604 #define DAC_SR_DACBFRPBF_MASK 0x1u
Jasper_lee 0:b16d94660a33 3605 #define DAC_SR_DACBFRPBF_SHIFT 0
Jasper_lee 0:b16d94660a33 3606 #define DAC_SR_DACBFRPTF_MASK 0x2u
Jasper_lee 0:b16d94660a33 3607 #define DAC_SR_DACBFRPTF_SHIFT 1
Jasper_lee 0:b16d94660a33 3608 #define DAC_SR_DACBFWMF_MASK 0x4u
Jasper_lee 0:b16d94660a33 3609 #define DAC_SR_DACBFWMF_SHIFT 2
Jasper_lee 0:b16d94660a33 3610 /* C0 Bit Fields */
Jasper_lee 0:b16d94660a33 3611 #define DAC_C0_DACBBIEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 3612 #define DAC_C0_DACBBIEN_SHIFT 0
Jasper_lee 0:b16d94660a33 3613 #define DAC_C0_DACBTIEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 3614 #define DAC_C0_DACBTIEN_SHIFT 1
Jasper_lee 0:b16d94660a33 3615 #define DAC_C0_DACBWIEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 3616 #define DAC_C0_DACBWIEN_SHIFT 2
Jasper_lee 0:b16d94660a33 3617 #define DAC_C0_LPEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 3618 #define DAC_C0_LPEN_SHIFT 3
Jasper_lee 0:b16d94660a33 3619 #define DAC_C0_DACSWTRG_MASK 0x10u
Jasper_lee 0:b16d94660a33 3620 #define DAC_C0_DACSWTRG_SHIFT 4
Jasper_lee 0:b16d94660a33 3621 #define DAC_C0_DACTRGSEL_MASK 0x20u
Jasper_lee 0:b16d94660a33 3622 #define DAC_C0_DACTRGSEL_SHIFT 5
Jasper_lee 0:b16d94660a33 3623 #define DAC_C0_DACRFS_MASK 0x40u
Jasper_lee 0:b16d94660a33 3624 #define DAC_C0_DACRFS_SHIFT 6
Jasper_lee 0:b16d94660a33 3625 #define DAC_C0_DACEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 3626 #define DAC_C0_DACEN_SHIFT 7
Jasper_lee 0:b16d94660a33 3627 /* C1 Bit Fields */
Jasper_lee 0:b16d94660a33 3628 #define DAC_C1_DACBFEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 3629 #define DAC_C1_DACBFEN_SHIFT 0
Jasper_lee 0:b16d94660a33 3630 #define DAC_C1_DACBFMD_MASK 0x6u
Jasper_lee 0:b16d94660a33 3631 #define DAC_C1_DACBFMD_SHIFT 1
Jasper_lee 0:b16d94660a33 3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
Jasper_lee 0:b16d94660a33 3633 #define DAC_C1_DACBFWM_MASK 0x18u
Jasper_lee 0:b16d94660a33 3634 #define DAC_C1_DACBFWM_SHIFT 3
Jasper_lee 0:b16d94660a33 3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
Jasper_lee 0:b16d94660a33 3636 #define DAC_C1_DMAEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 3637 #define DAC_C1_DMAEN_SHIFT 7
Jasper_lee 0:b16d94660a33 3638 /* C2 Bit Fields */
Jasper_lee 0:b16d94660a33 3639 #define DAC_C2_DACBFUP_MASK 0xFu
Jasper_lee 0:b16d94660a33 3640 #define DAC_C2_DACBFUP_SHIFT 0
Jasper_lee 0:b16d94660a33 3641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
Jasper_lee 0:b16d94660a33 3642 #define DAC_C2_DACBFRP_MASK 0xF0u
Jasper_lee 0:b16d94660a33 3643 #define DAC_C2_DACBFRP_SHIFT 4
Jasper_lee 0:b16d94660a33 3644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
Jasper_lee 0:b16d94660a33 3645
Jasper_lee 0:b16d94660a33 3646 /*!
Jasper_lee 0:b16d94660a33 3647 * @}
Jasper_lee 0:b16d94660a33 3648 */ /* end of group DAC_Register_Masks */
Jasper_lee 0:b16d94660a33 3649
Jasper_lee 0:b16d94660a33 3650
Jasper_lee 0:b16d94660a33 3651 /* DAC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 3652 /** Peripheral DAC0 base address */
Jasper_lee 0:b16d94660a33 3653 #define DAC0_BASE (0x400CC000u)
Jasper_lee 0:b16d94660a33 3654 /** Peripheral DAC0 base pointer */
Jasper_lee 0:b16d94660a33 3655 #define DAC0 ((DAC_Type *)DAC0_BASE)
Jasper_lee 0:b16d94660a33 3656 #define DAC0_BASE_PTR (DAC0)
Jasper_lee 0:b16d94660a33 3657 /** Peripheral DAC1 base address */
Jasper_lee 0:b16d94660a33 3658 #define DAC1_BASE (0x400CD000u)
Jasper_lee 0:b16d94660a33 3659 /** Peripheral DAC1 base pointer */
Jasper_lee 0:b16d94660a33 3660 #define DAC1 ((DAC_Type *)DAC1_BASE)
Jasper_lee 0:b16d94660a33 3661 #define DAC1_BASE_PTR (DAC1)
Jasper_lee 0:b16d94660a33 3662 /** Array initializer of DAC peripheral base addresses */
Jasper_lee 0:b16d94660a33 3663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
Jasper_lee 0:b16d94660a33 3664 /** Array initializer of DAC peripheral base pointers */
Jasper_lee 0:b16d94660a33 3665 #define DAC_BASE_PTRS { DAC0, DAC1 }
Jasper_lee 0:b16d94660a33 3666 /** Interrupt vectors for the DAC peripheral type */
Jasper_lee 0:b16d94660a33 3667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
Jasper_lee 0:b16d94660a33 3668
Jasper_lee 0:b16d94660a33 3669 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3670 -- DAC - Register accessor macros
Jasper_lee 0:b16d94660a33 3671 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3672
Jasper_lee 0:b16d94660a33 3673 /*!
Jasper_lee 0:b16d94660a33 3674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Jasper_lee 0:b16d94660a33 3675 * @{
Jasper_lee 0:b16d94660a33 3676 */
Jasper_lee 0:b16d94660a33 3677
Jasper_lee 0:b16d94660a33 3678
Jasper_lee 0:b16d94660a33 3679 /* DAC - Register instance definitions */
Jasper_lee 0:b16d94660a33 3680 /* DAC0 */
Jasper_lee 0:b16d94660a33 3681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
Jasper_lee 0:b16d94660a33 3682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
Jasper_lee 0:b16d94660a33 3683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
Jasper_lee 0:b16d94660a33 3684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
Jasper_lee 0:b16d94660a33 3685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
Jasper_lee 0:b16d94660a33 3686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
Jasper_lee 0:b16d94660a33 3687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
Jasper_lee 0:b16d94660a33 3688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
Jasper_lee 0:b16d94660a33 3689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
Jasper_lee 0:b16d94660a33 3690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
Jasper_lee 0:b16d94660a33 3691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
Jasper_lee 0:b16d94660a33 3692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
Jasper_lee 0:b16d94660a33 3693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
Jasper_lee 0:b16d94660a33 3694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
Jasper_lee 0:b16d94660a33 3695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
Jasper_lee 0:b16d94660a33 3696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
Jasper_lee 0:b16d94660a33 3697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
Jasper_lee 0:b16d94660a33 3698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
Jasper_lee 0:b16d94660a33 3699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
Jasper_lee 0:b16d94660a33 3700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
Jasper_lee 0:b16d94660a33 3701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
Jasper_lee 0:b16d94660a33 3702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
Jasper_lee 0:b16d94660a33 3703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
Jasper_lee 0:b16d94660a33 3704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
Jasper_lee 0:b16d94660a33 3705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
Jasper_lee 0:b16d94660a33 3706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
Jasper_lee 0:b16d94660a33 3707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
Jasper_lee 0:b16d94660a33 3708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
Jasper_lee 0:b16d94660a33 3709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
Jasper_lee 0:b16d94660a33 3710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
Jasper_lee 0:b16d94660a33 3711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
Jasper_lee 0:b16d94660a33 3712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
Jasper_lee 0:b16d94660a33 3713 #define DAC0_SR DAC_SR_REG(DAC0)
Jasper_lee 0:b16d94660a33 3714 #define DAC0_C0 DAC_C0_REG(DAC0)
Jasper_lee 0:b16d94660a33 3715 #define DAC0_C1 DAC_C1_REG(DAC0)
Jasper_lee 0:b16d94660a33 3716 #define DAC0_C2 DAC_C2_REG(DAC0)
Jasper_lee 0:b16d94660a33 3717 /* DAC1 */
Jasper_lee 0:b16d94660a33 3718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
Jasper_lee 0:b16d94660a33 3719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
Jasper_lee 0:b16d94660a33 3720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
Jasper_lee 0:b16d94660a33 3721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
Jasper_lee 0:b16d94660a33 3722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
Jasper_lee 0:b16d94660a33 3723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
Jasper_lee 0:b16d94660a33 3724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
Jasper_lee 0:b16d94660a33 3725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
Jasper_lee 0:b16d94660a33 3726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
Jasper_lee 0:b16d94660a33 3727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
Jasper_lee 0:b16d94660a33 3728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
Jasper_lee 0:b16d94660a33 3729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
Jasper_lee 0:b16d94660a33 3730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
Jasper_lee 0:b16d94660a33 3731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
Jasper_lee 0:b16d94660a33 3732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
Jasper_lee 0:b16d94660a33 3733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
Jasper_lee 0:b16d94660a33 3734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
Jasper_lee 0:b16d94660a33 3735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
Jasper_lee 0:b16d94660a33 3736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
Jasper_lee 0:b16d94660a33 3737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
Jasper_lee 0:b16d94660a33 3738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
Jasper_lee 0:b16d94660a33 3739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
Jasper_lee 0:b16d94660a33 3740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
Jasper_lee 0:b16d94660a33 3741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
Jasper_lee 0:b16d94660a33 3742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
Jasper_lee 0:b16d94660a33 3743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
Jasper_lee 0:b16d94660a33 3744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
Jasper_lee 0:b16d94660a33 3745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
Jasper_lee 0:b16d94660a33 3746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
Jasper_lee 0:b16d94660a33 3747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
Jasper_lee 0:b16d94660a33 3748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
Jasper_lee 0:b16d94660a33 3749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
Jasper_lee 0:b16d94660a33 3750 #define DAC1_SR DAC_SR_REG(DAC1)
Jasper_lee 0:b16d94660a33 3751 #define DAC1_C0 DAC_C0_REG(DAC1)
Jasper_lee 0:b16d94660a33 3752 #define DAC1_C1 DAC_C1_REG(DAC1)
Jasper_lee 0:b16d94660a33 3753 #define DAC1_C2 DAC_C2_REG(DAC1)
Jasper_lee 0:b16d94660a33 3754
Jasper_lee 0:b16d94660a33 3755 /* DAC - Register array accessors */
Jasper_lee 0:b16d94660a33 3756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
Jasper_lee 0:b16d94660a33 3757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
Jasper_lee 0:b16d94660a33 3758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
Jasper_lee 0:b16d94660a33 3759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
Jasper_lee 0:b16d94660a33 3760
Jasper_lee 0:b16d94660a33 3761 /*!
Jasper_lee 0:b16d94660a33 3762 * @}
Jasper_lee 0:b16d94660a33 3763 */ /* end of group DAC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3764
Jasper_lee 0:b16d94660a33 3765
Jasper_lee 0:b16d94660a33 3766 /*!
Jasper_lee 0:b16d94660a33 3767 * @}
Jasper_lee 0:b16d94660a33 3768 */ /* end of group DAC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 3769
Jasper_lee 0:b16d94660a33 3770
Jasper_lee 0:b16d94660a33 3771 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3772 -- DMA Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3773 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3774
Jasper_lee 0:b16d94660a33 3775 /*!
Jasper_lee 0:b16d94660a33 3776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Jasper_lee 0:b16d94660a33 3777 * @{
Jasper_lee 0:b16d94660a33 3778 */
Jasper_lee 0:b16d94660a33 3779
Jasper_lee 0:b16d94660a33 3780 /** DMA - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 3781 typedef struct {
Jasper_lee 0:b16d94660a33 3782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 3783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 3784 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 3785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 3786 uint8_t RESERVED_1[4];
Jasper_lee 0:b16d94660a33 3787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 3788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 3789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
Jasper_lee 0:b16d94660a33 3790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
Jasper_lee 0:b16d94660a33 3791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
Jasper_lee 0:b16d94660a33 3792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
Jasper_lee 0:b16d94660a33 3793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
Jasper_lee 0:b16d94660a33 3794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
Jasper_lee 0:b16d94660a33 3795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
Jasper_lee 0:b16d94660a33 3796 uint8_t RESERVED_2[4];
Jasper_lee 0:b16d94660a33 3797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
Jasper_lee 0:b16d94660a33 3798 uint8_t RESERVED_3[4];
Jasper_lee 0:b16d94660a33 3799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
Jasper_lee 0:b16d94660a33 3800 uint8_t RESERVED_4[4];
Jasper_lee 0:b16d94660a33 3801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
Jasper_lee 0:b16d94660a33 3802 uint8_t RESERVED_5[200];
Jasper_lee 0:b16d94660a33 3803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
Jasper_lee 0:b16d94660a33 3804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
Jasper_lee 0:b16d94660a33 3805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
Jasper_lee 0:b16d94660a33 3806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
Jasper_lee 0:b16d94660a33 3807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
Jasper_lee 0:b16d94660a33 3808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
Jasper_lee 0:b16d94660a33 3809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
Jasper_lee 0:b16d94660a33 3810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
Jasper_lee 0:b16d94660a33 3811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
Jasper_lee 0:b16d94660a33 3812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
Jasper_lee 0:b16d94660a33 3813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
Jasper_lee 0:b16d94660a33 3814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
Jasper_lee 0:b16d94660a33 3815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
Jasper_lee 0:b16d94660a33 3816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
Jasper_lee 0:b16d94660a33 3817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
Jasper_lee 0:b16d94660a33 3818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
Jasper_lee 0:b16d94660a33 3819 uint8_t RESERVED_6[3824];
Jasper_lee 0:b16d94660a33 3820 struct { /* offset: 0x1000, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3824 union { /* offset: 0x1008, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3828 };
Jasper_lee 0:b16d94660a33 3829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3832 union { /* offset: 0x1016, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3835 };
Jasper_lee 0:b16d94660a33 3836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3838 union { /* offset: 0x101E, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
Jasper_lee 0:b16d94660a33 3841 };
Jasper_lee 0:b16d94660a33 3842 } TCD[16];
Jasper_lee 0:b16d94660a33 3843 } DMA_Type, *DMA_MemMapPtr;
Jasper_lee 0:b16d94660a33 3844
Jasper_lee 0:b16d94660a33 3845 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3846 -- DMA - Register accessor macros
Jasper_lee 0:b16d94660a33 3847 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3848
Jasper_lee 0:b16d94660a33 3849 /*!
Jasper_lee 0:b16d94660a33 3850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Jasper_lee 0:b16d94660a33 3851 * @{
Jasper_lee 0:b16d94660a33 3852 */
Jasper_lee 0:b16d94660a33 3853
Jasper_lee 0:b16d94660a33 3854
Jasper_lee 0:b16d94660a33 3855 /* DMA - Register accessors */
Jasper_lee 0:b16d94660a33 3856 #define DMA_CR_REG(base) ((base)->CR)
Jasper_lee 0:b16d94660a33 3857 #define DMA_ES_REG(base) ((base)->ES)
Jasper_lee 0:b16d94660a33 3858 #define DMA_ERQ_REG(base) ((base)->ERQ)
Jasper_lee 0:b16d94660a33 3859 #define DMA_EEI_REG(base) ((base)->EEI)
Jasper_lee 0:b16d94660a33 3860 #define DMA_CEEI_REG(base) ((base)->CEEI)
Jasper_lee 0:b16d94660a33 3861 #define DMA_SEEI_REG(base) ((base)->SEEI)
Jasper_lee 0:b16d94660a33 3862 #define DMA_CERQ_REG(base) ((base)->CERQ)
Jasper_lee 0:b16d94660a33 3863 #define DMA_SERQ_REG(base) ((base)->SERQ)
Jasper_lee 0:b16d94660a33 3864 #define DMA_CDNE_REG(base) ((base)->CDNE)
Jasper_lee 0:b16d94660a33 3865 #define DMA_SSRT_REG(base) ((base)->SSRT)
Jasper_lee 0:b16d94660a33 3866 #define DMA_CERR_REG(base) ((base)->CERR)
Jasper_lee 0:b16d94660a33 3867 #define DMA_CINT_REG(base) ((base)->CINT)
Jasper_lee 0:b16d94660a33 3868 #define DMA_INT_REG(base) ((base)->INT)
Jasper_lee 0:b16d94660a33 3869 #define DMA_ERR_REG(base) ((base)->ERR)
Jasper_lee 0:b16d94660a33 3870 #define DMA_HRS_REG(base) ((base)->HRS)
Jasper_lee 0:b16d94660a33 3871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
Jasper_lee 0:b16d94660a33 3872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
Jasper_lee 0:b16d94660a33 3873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
Jasper_lee 0:b16d94660a33 3874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
Jasper_lee 0:b16d94660a33 3875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
Jasper_lee 0:b16d94660a33 3876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
Jasper_lee 0:b16d94660a33 3877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
Jasper_lee 0:b16d94660a33 3878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
Jasper_lee 0:b16d94660a33 3879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
Jasper_lee 0:b16d94660a33 3880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
Jasper_lee 0:b16d94660a33 3881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
Jasper_lee 0:b16d94660a33 3882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
Jasper_lee 0:b16d94660a33 3883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
Jasper_lee 0:b16d94660a33 3884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
Jasper_lee 0:b16d94660a33 3885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
Jasper_lee 0:b16d94660a33 3886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
Jasper_lee 0:b16d94660a33 3887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
Jasper_lee 0:b16d94660a33 3888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
Jasper_lee 0:b16d94660a33 3889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
Jasper_lee 0:b16d94660a33 3890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
Jasper_lee 0:b16d94660a33 3891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
Jasper_lee 0:b16d94660a33 3892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
Jasper_lee 0:b16d94660a33 3893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
Jasper_lee 0:b16d94660a33 3894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
Jasper_lee 0:b16d94660a33 3895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
Jasper_lee 0:b16d94660a33 3896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
Jasper_lee 0:b16d94660a33 3897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
Jasper_lee 0:b16d94660a33 3898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
Jasper_lee 0:b16d94660a33 3899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
Jasper_lee 0:b16d94660a33 3900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
Jasper_lee 0:b16d94660a33 3901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
Jasper_lee 0:b16d94660a33 3902
Jasper_lee 0:b16d94660a33 3903 /*!
Jasper_lee 0:b16d94660a33 3904 * @}
Jasper_lee 0:b16d94660a33 3905 */ /* end of group DMA_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 3906
Jasper_lee 0:b16d94660a33 3907
Jasper_lee 0:b16d94660a33 3908 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 3909 -- DMA Register Masks
Jasper_lee 0:b16d94660a33 3910 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 3911
Jasper_lee 0:b16d94660a33 3912 /*!
Jasper_lee 0:b16d94660a33 3913 * @addtogroup DMA_Register_Masks DMA Register Masks
Jasper_lee 0:b16d94660a33 3914 * @{
Jasper_lee 0:b16d94660a33 3915 */
Jasper_lee 0:b16d94660a33 3916
Jasper_lee 0:b16d94660a33 3917 /* CR Bit Fields */
Jasper_lee 0:b16d94660a33 3918 #define DMA_CR_EDBG_MASK 0x2u
Jasper_lee 0:b16d94660a33 3919 #define DMA_CR_EDBG_SHIFT 1
Jasper_lee 0:b16d94660a33 3920 #define DMA_CR_ERCA_MASK 0x4u
Jasper_lee 0:b16d94660a33 3921 #define DMA_CR_ERCA_SHIFT 2
Jasper_lee 0:b16d94660a33 3922 #define DMA_CR_HOE_MASK 0x10u
Jasper_lee 0:b16d94660a33 3923 #define DMA_CR_HOE_SHIFT 4
Jasper_lee 0:b16d94660a33 3924 #define DMA_CR_HALT_MASK 0x20u
Jasper_lee 0:b16d94660a33 3925 #define DMA_CR_HALT_SHIFT 5
Jasper_lee 0:b16d94660a33 3926 #define DMA_CR_CLM_MASK 0x40u
Jasper_lee 0:b16d94660a33 3927 #define DMA_CR_CLM_SHIFT 6
Jasper_lee 0:b16d94660a33 3928 #define DMA_CR_EMLM_MASK 0x80u
Jasper_lee 0:b16d94660a33 3929 #define DMA_CR_EMLM_SHIFT 7
Jasper_lee 0:b16d94660a33 3930 #define DMA_CR_ECX_MASK 0x10000u
Jasper_lee 0:b16d94660a33 3931 #define DMA_CR_ECX_SHIFT 16
Jasper_lee 0:b16d94660a33 3932 #define DMA_CR_CX_MASK 0x20000u
Jasper_lee 0:b16d94660a33 3933 #define DMA_CR_CX_SHIFT 17
Jasper_lee 0:b16d94660a33 3934 /* ES Bit Fields */
Jasper_lee 0:b16d94660a33 3935 #define DMA_ES_DBE_MASK 0x1u
Jasper_lee 0:b16d94660a33 3936 #define DMA_ES_DBE_SHIFT 0
Jasper_lee 0:b16d94660a33 3937 #define DMA_ES_SBE_MASK 0x2u
Jasper_lee 0:b16d94660a33 3938 #define DMA_ES_SBE_SHIFT 1
Jasper_lee 0:b16d94660a33 3939 #define DMA_ES_SGE_MASK 0x4u
Jasper_lee 0:b16d94660a33 3940 #define DMA_ES_SGE_SHIFT 2
Jasper_lee 0:b16d94660a33 3941 #define DMA_ES_NCE_MASK 0x8u
Jasper_lee 0:b16d94660a33 3942 #define DMA_ES_NCE_SHIFT 3
Jasper_lee 0:b16d94660a33 3943 #define DMA_ES_DOE_MASK 0x10u
Jasper_lee 0:b16d94660a33 3944 #define DMA_ES_DOE_SHIFT 4
Jasper_lee 0:b16d94660a33 3945 #define DMA_ES_DAE_MASK 0x20u
Jasper_lee 0:b16d94660a33 3946 #define DMA_ES_DAE_SHIFT 5
Jasper_lee 0:b16d94660a33 3947 #define DMA_ES_SOE_MASK 0x40u
Jasper_lee 0:b16d94660a33 3948 #define DMA_ES_SOE_SHIFT 6
Jasper_lee 0:b16d94660a33 3949 #define DMA_ES_SAE_MASK 0x80u
Jasper_lee 0:b16d94660a33 3950 #define DMA_ES_SAE_SHIFT 7
Jasper_lee 0:b16d94660a33 3951 #define DMA_ES_ERRCHN_MASK 0xF00u
Jasper_lee 0:b16d94660a33 3952 #define DMA_ES_ERRCHN_SHIFT 8
Jasper_lee 0:b16d94660a33 3953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
Jasper_lee 0:b16d94660a33 3954 #define DMA_ES_CPE_MASK 0x4000u
Jasper_lee 0:b16d94660a33 3955 #define DMA_ES_CPE_SHIFT 14
Jasper_lee 0:b16d94660a33 3956 #define DMA_ES_ECX_MASK 0x10000u
Jasper_lee 0:b16d94660a33 3957 #define DMA_ES_ECX_SHIFT 16
Jasper_lee 0:b16d94660a33 3958 #define DMA_ES_VLD_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 3959 #define DMA_ES_VLD_SHIFT 31
Jasper_lee 0:b16d94660a33 3960 /* ERQ Bit Fields */
Jasper_lee 0:b16d94660a33 3961 #define DMA_ERQ_ERQ0_MASK 0x1u
Jasper_lee 0:b16d94660a33 3962 #define DMA_ERQ_ERQ0_SHIFT 0
Jasper_lee 0:b16d94660a33 3963 #define DMA_ERQ_ERQ1_MASK 0x2u
Jasper_lee 0:b16d94660a33 3964 #define DMA_ERQ_ERQ1_SHIFT 1
Jasper_lee 0:b16d94660a33 3965 #define DMA_ERQ_ERQ2_MASK 0x4u
Jasper_lee 0:b16d94660a33 3966 #define DMA_ERQ_ERQ2_SHIFT 2
Jasper_lee 0:b16d94660a33 3967 #define DMA_ERQ_ERQ3_MASK 0x8u
Jasper_lee 0:b16d94660a33 3968 #define DMA_ERQ_ERQ3_SHIFT 3
Jasper_lee 0:b16d94660a33 3969 #define DMA_ERQ_ERQ4_MASK 0x10u
Jasper_lee 0:b16d94660a33 3970 #define DMA_ERQ_ERQ4_SHIFT 4
Jasper_lee 0:b16d94660a33 3971 #define DMA_ERQ_ERQ5_MASK 0x20u
Jasper_lee 0:b16d94660a33 3972 #define DMA_ERQ_ERQ5_SHIFT 5
Jasper_lee 0:b16d94660a33 3973 #define DMA_ERQ_ERQ6_MASK 0x40u
Jasper_lee 0:b16d94660a33 3974 #define DMA_ERQ_ERQ6_SHIFT 6
Jasper_lee 0:b16d94660a33 3975 #define DMA_ERQ_ERQ7_MASK 0x80u
Jasper_lee 0:b16d94660a33 3976 #define DMA_ERQ_ERQ7_SHIFT 7
Jasper_lee 0:b16d94660a33 3977 #define DMA_ERQ_ERQ8_MASK 0x100u
Jasper_lee 0:b16d94660a33 3978 #define DMA_ERQ_ERQ8_SHIFT 8
Jasper_lee 0:b16d94660a33 3979 #define DMA_ERQ_ERQ9_MASK 0x200u
Jasper_lee 0:b16d94660a33 3980 #define DMA_ERQ_ERQ9_SHIFT 9
Jasper_lee 0:b16d94660a33 3981 #define DMA_ERQ_ERQ10_MASK 0x400u
Jasper_lee 0:b16d94660a33 3982 #define DMA_ERQ_ERQ10_SHIFT 10
Jasper_lee 0:b16d94660a33 3983 #define DMA_ERQ_ERQ11_MASK 0x800u
Jasper_lee 0:b16d94660a33 3984 #define DMA_ERQ_ERQ11_SHIFT 11
Jasper_lee 0:b16d94660a33 3985 #define DMA_ERQ_ERQ12_MASK 0x1000u
Jasper_lee 0:b16d94660a33 3986 #define DMA_ERQ_ERQ12_SHIFT 12
Jasper_lee 0:b16d94660a33 3987 #define DMA_ERQ_ERQ13_MASK 0x2000u
Jasper_lee 0:b16d94660a33 3988 #define DMA_ERQ_ERQ13_SHIFT 13
Jasper_lee 0:b16d94660a33 3989 #define DMA_ERQ_ERQ14_MASK 0x4000u
Jasper_lee 0:b16d94660a33 3990 #define DMA_ERQ_ERQ14_SHIFT 14
Jasper_lee 0:b16d94660a33 3991 #define DMA_ERQ_ERQ15_MASK 0x8000u
Jasper_lee 0:b16d94660a33 3992 #define DMA_ERQ_ERQ15_SHIFT 15
Jasper_lee 0:b16d94660a33 3993 /* EEI Bit Fields */
Jasper_lee 0:b16d94660a33 3994 #define DMA_EEI_EEI0_MASK 0x1u
Jasper_lee 0:b16d94660a33 3995 #define DMA_EEI_EEI0_SHIFT 0
Jasper_lee 0:b16d94660a33 3996 #define DMA_EEI_EEI1_MASK 0x2u
Jasper_lee 0:b16d94660a33 3997 #define DMA_EEI_EEI1_SHIFT 1
Jasper_lee 0:b16d94660a33 3998 #define DMA_EEI_EEI2_MASK 0x4u
Jasper_lee 0:b16d94660a33 3999 #define DMA_EEI_EEI2_SHIFT 2
Jasper_lee 0:b16d94660a33 4000 #define DMA_EEI_EEI3_MASK 0x8u
Jasper_lee 0:b16d94660a33 4001 #define DMA_EEI_EEI3_SHIFT 3
Jasper_lee 0:b16d94660a33 4002 #define DMA_EEI_EEI4_MASK 0x10u
Jasper_lee 0:b16d94660a33 4003 #define DMA_EEI_EEI4_SHIFT 4
Jasper_lee 0:b16d94660a33 4004 #define DMA_EEI_EEI5_MASK 0x20u
Jasper_lee 0:b16d94660a33 4005 #define DMA_EEI_EEI5_SHIFT 5
Jasper_lee 0:b16d94660a33 4006 #define DMA_EEI_EEI6_MASK 0x40u
Jasper_lee 0:b16d94660a33 4007 #define DMA_EEI_EEI6_SHIFT 6
Jasper_lee 0:b16d94660a33 4008 #define DMA_EEI_EEI7_MASK 0x80u
Jasper_lee 0:b16d94660a33 4009 #define DMA_EEI_EEI7_SHIFT 7
Jasper_lee 0:b16d94660a33 4010 #define DMA_EEI_EEI8_MASK 0x100u
Jasper_lee 0:b16d94660a33 4011 #define DMA_EEI_EEI8_SHIFT 8
Jasper_lee 0:b16d94660a33 4012 #define DMA_EEI_EEI9_MASK 0x200u
Jasper_lee 0:b16d94660a33 4013 #define DMA_EEI_EEI9_SHIFT 9
Jasper_lee 0:b16d94660a33 4014 #define DMA_EEI_EEI10_MASK 0x400u
Jasper_lee 0:b16d94660a33 4015 #define DMA_EEI_EEI10_SHIFT 10
Jasper_lee 0:b16d94660a33 4016 #define DMA_EEI_EEI11_MASK 0x800u
Jasper_lee 0:b16d94660a33 4017 #define DMA_EEI_EEI11_SHIFT 11
Jasper_lee 0:b16d94660a33 4018 #define DMA_EEI_EEI12_MASK 0x1000u
Jasper_lee 0:b16d94660a33 4019 #define DMA_EEI_EEI12_SHIFT 12
Jasper_lee 0:b16d94660a33 4020 #define DMA_EEI_EEI13_MASK 0x2000u
Jasper_lee 0:b16d94660a33 4021 #define DMA_EEI_EEI13_SHIFT 13
Jasper_lee 0:b16d94660a33 4022 #define DMA_EEI_EEI14_MASK 0x4000u
Jasper_lee 0:b16d94660a33 4023 #define DMA_EEI_EEI14_SHIFT 14
Jasper_lee 0:b16d94660a33 4024 #define DMA_EEI_EEI15_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4025 #define DMA_EEI_EEI15_SHIFT 15
Jasper_lee 0:b16d94660a33 4026 /* CEEI Bit Fields */
Jasper_lee 0:b16d94660a33 4027 #define DMA_CEEI_CEEI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4028 #define DMA_CEEI_CEEI_SHIFT 0
Jasper_lee 0:b16d94660a33 4029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
Jasper_lee 0:b16d94660a33 4030 #define DMA_CEEI_CAEE_MASK 0x40u
Jasper_lee 0:b16d94660a33 4031 #define DMA_CEEI_CAEE_SHIFT 6
Jasper_lee 0:b16d94660a33 4032 #define DMA_CEEI_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4033 #define DMA_CEEI_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4034 /* SEEI Bit Fields */
Jasper_lee 0:b16d94660a33 4035 #define DMA_SEEI_SEEI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4036 #define DMA_SEEI_SEEI_SHIFT 0
Jasper_lee 0:b16d94660a33 4037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
Jasper_lee 0:b16d94660a33 4038 #define DMA_SEEI_SAEE_MASK 0x40u
Jasper_lee 0:b16d94660a33 4039 #define DMA_SEEI_SAEE_SHIFT 6
Jasper_lee 0:b16d94660a33 4040 #define DMA_SEEI_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4041 #define DMA_SEEI_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4042 /* CERQ Bit Fields */
Jasper_lee 0:b16d94660a33 4043 #define DMA_CERQ_CERQ_MASK 0xFu
Jasper_lee 0:b16d94660a33 4044 #define DMA_CERQ_CERQ_SHIFT 0
Jasper_lee 0:b16d94660a33 4045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
Jasper_lee 0:b16d94660a33 4046 #define DMA_CERQ_CAER_MASK 0x40u
Jasper_lee 0:b16d94660a33 4047 #define DMA_CERQ_CAER_SHIFT 6
Jasper_lee 0:b16d94660a33 4048 #define DMA_CERQ_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4049 #define DMA_CERQ_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4050 /* SERQ Bit Fields */
Jasper_lee 0:b16d94660a33 4051 #define DMA_SERQ_SERQ_MASK 0xFu
Jasper_lee 0:b16d94660a33 4052 #define DMA_SERQ_SERQ_SHIFT 0
Jasper_lee 0:b16d94660a33 4053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
Jasper_lee 0:b16d94660a33 4054 #define DMA_SERQ_SAER_MASK 0x40u
Jasper_lee 0:b16d94660a33 4055 #define DMA_SERQ_SAER_SHIFT 6
Jasper_lee 0:b16d94660a33 4056 #define DMA_SERQ_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4057 #define DMA_SERQ_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4058 /* CDNE Bit Fields */
Jasper_lee 0:b16d94660a33 4059 #define DMA_CDNE_CDNE_MASK 0xFu
Jasper_lee 0:b16d94660a33 4060 #define DMA_CDNE_CDNE_SHIFT 0
Jasper_lee 0:b16d94660a33 4061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
Jasper_lee 0:b16d94660a33 4062 #define DMA_CDNE_CADN_MASK 0x40u
Jasper_lee 0:b16d94660a33 4063 #define DMA_CDNE_CADN_SHIFT 6
Jasper_lee 0:b16d94660a33 4064 #define DMA_CDNE_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4065 #define DMA_CDNE_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4066 /* SSRT Bit Fields */
Jasper_lee 0:b16d94660a33 4067 #define DMA_SSRT_SSRT_MASK 0xFu
Jasper_lee 0:b16d94660a33 4068 #define DMA_SSRT_SSRT_SHIFT 0
Jasper_lee 0:b16d94660a33 4069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
Jasper_lee 0:b16d94660a33 4070 #define DMA_SSRT_SAST_MASK 0x40u
Jasper_lee 0:b16d94660a33 4071 #define DMA_SSRT_SAST_SHIFT 6
Jasper_lee 0:b16d94660a33 4072 #define DMA_SSRT_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4073 #define DMA_SSRT_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4074 /* CERR Bit Fields */
Jasper_lee 0:b16d94660a33 4075 #define DMA_CERR_CERR_MASK 0xFu
Jasper_lee 0:b16d94660a33 4076 #define DMA_CERR_CERR_SHIFT 0
Jasper_lee 0:b16d94660a33 4077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
Jasper_lee 0:b16d94660a33 4078 #define DMA_CERR_CAEI_MASK 0x40u
Jasper_lee 0:b16d94660a33 4079 #define DMA_CERR_CAEI_SHIFT 6
Jasper_lee 0:b16d94660a33 4080 #define DMA_CERR_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4081 #define DMA_CERR_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4082 /* CINT Bit Fields */
Jasper_lee 0:b16d94660a33 4083 #define DMA_CINT_CINT_MASK 0xFu
Jasper_lee 0:b16d94660a33 4084 #define DMA_CINT_CINT_SHIFT 0
Jasper_lee 0:b16d94660a33 4085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
Jasper_lee 0:b16d94660a33 4086 #define DMA_CINT_CAIR_MASK 0x40u
Jasper_lee 0:b16d94660a33 4087 #define DMA_CINT_CAIR_SHIFT 6
Jasper_lee 0:b16d94660a33 4088 #define DMA_CINT_NOP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4089 #define DMA_CINT_NOP_SHIFT 7
Jasper_lee 0:b16d94660a33 4090 /* INT Bit Fields */
Jasper_lee 0:b16d94660a33 4091 #define DMA_INT_INT0_MASK 0x1u
Jasper_lee 0:b16d94660a33 4092 #define DMA_INT_INT0_SHIFT 0
Jasper_lee 0:b16d94660a33 4093 #define DMA_INT_INT1_MASK 0x2u
Jasper_lee 0:b16d94660a33 4094 #define DMA_INT_INT1_SHIFT 1
Jasper_lee 0:b16d94660a33 4095 #define DMA_INT_INT2_MASK 0x4u
Jasper_lee 0:b16d94660a33 4096 #define DMA_INT_INT2_SHIFT 2
Jasper_lee 0:b16d94660a33 4097 #define DMA_INT_INT3_MASK 0x8u
Jasper_lee 0:b16d94660a33 4098 #define DMA_INT_INT3_SHIFT 3
Jasper_lee 0:b16d94660a33 4099 #define DMA_INT_INT4_MASK 0x10u
Jasper_lee 0:b16d94660a33 4100 #define DMA_INT_INT4_SHIFT 4
Jasper_lee 0:b16d94660a33 4101 #define DMA_INT_INT5_MASK 0x20u
Jasper_lee 0:b16d94660a33 4102 #define DMA_INT_INT5_SHIFT 5
Jasper_lee 0:b16d94660a33 4103 #define DMA_INT_INT6_MASK 0x40u
Jasper_lee 0:b16d94660a33 4104 #define DMA_INT_INT6_SHIFT 6
Jasper_lee 0:b16d94660a33 4105 #define DMA_INT_INT7_MASK 0x80u
Jasper_lee 0:b16d94660a33 4106 #define DMA_INT_INT7_SHIFT 7
Jasper_lee 0:b16d94660a33 4107 #define DMA_INT_INT8_MASK 0x100u
Jasper_lee 0:b16d94660a33 4108 #define DMA_INT_INT8_SHIFT 8
Jasper_lee 0:b16d94660a33 4109 #define DMA_INT_INT9_MASK 0x200u
Jasper_lee 0:b16d94660a33 4110 #define DMA_INT_INT9_SHIFT 9
Jasper_lee 0:b16d94660a33 4111 #define DMA_INT_INT10_MASK 0x400u
Jasper_lee 0:b16d94660a33 4112 #define DMA_INT_INT10_SHIFT 10
Jasper_lee 0:b16d94660a33 4113 #define DMA_INT_INT11_MASK 0x800u
Jasper_lee 0:b16d94660a33 4114 #define DMA_INT_INT11_SHIFT 11
Jasper_lee 0:b16d94660a33 4115 #define DMA_INT_INT12_MASK 0x1000u
Jasper_lee 0:b16d94660a33 4116 #define DMA_INT_INT12_SHIFT 12
Jasper_lee 0:b16d94660a33 4117 #define DMA_INT_INT13_MASK 0x2000u
Jasper_lee 0:b16d94660a33 4118 #define DMA_INT_INT13_SHIFT 13
Jasper_lee 0:b16d94660a33 4119 #define DMA_INT_INT14_MASK 0x4000u
Jasper_lee 0:b16d94660a33 4120 #define DMA_INT_INT14_SHIFT 14
Jasper_lee 0:b16d94660a33 4121 #define DMA_INT_INT15_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4122 #define DMA_INT_INT15_SHIFT 15
Jasper_lee 0:b16d94660a33 4123 /* ERR Bit Fields */
Jasper_lee 0:b16d94660a33 4124 #define DMA_ERR_ERR0_MASK 0x1u
Jasper_lee 0:b16d94660a33 4125 #define DMA_ERR_ERR0_SHIFT 0
Jasper_lee 0:b16d94660a33 4126 #define DMA_ERR_ERR1_MASK 0x2u
Jasper_lee 0:b16d94660a33 4127 #define DMA_ERR_ERR1_SHIFT 1
Jasper_lee 0:b16d94660a33 4128 #define DMA_ERR_ERR2_MASK 0x4u
Jasper_lee 0:b16d94660a33 4129 #define DMA_ERR_ERR2_SHIFT 2
Jasper_lee 0:b16d94660a33 4130 #define DMA_ERR_ERR3_MASK 0x8u
Jasper_lee 0:b16d94660a33 4131 #define DMA_ERR_ERR3_SHIFT 3
Jasper_lee 0:b16d94660a33 4132 #define DMA_ERR_ERR4_MASK 0x10u
Jasper_lee 0:b16d94660a33 4133 #define DMA_ERR_ERR4_SHIFT 4
Jasper_lee 0:b16d94660a33 4134 #define DMA_ERR_ERR5_MASK 0x20u
Jasper_lee 0:b16d94660a33 4135 #define DMA_ERR_ERR5_SHIFT 5
Jasper_lee 0:b16d94660a33 4136 #define DMA_ERR_ERR6_MASK 0x40u
Jasper_lee 0:b16d94660a33 4137 #define DMA_ERR_ERR6_SHIFT 6
Jasper_lee 0:b16d94660a33 4138 #define DMA_ERR_ERR7_MASK 0x80u
Jasper_lee 0:b16d94660a33 4139 #define DMA_ERR_ERR7_SHIFT 7
Jasper_lee 0:b16d94660a33 4140 #define DMA_ERR_ERR8_MASK 0x100u
Jasper_lee 0:b16d94660a33 4141 #define DMA_ERR_ERR8_SHIFT 8
Jasper_lee 0:b16d94660a33 4142 #define DMA_ERR_ERR9_MASK 0x200u
Jasper_lee 0:b16d94660a33 4143 #define DMA_ERR_ERR9_SHIFT 9
Jasper_lee 0:b16d94660a33 4144 #define DMA_ERR_ERR10_MASK 0x400u
Jasper_lee 0:b16d94660a33 4145 #define DMA_ERR_ERR10_SHIFT 10
Jasper_lee 0:b16d94660a33 4146 #define DMA_ERR_ERR11_MASK 0x800u
Jasper_lee 0:b16d94660a33 4147 #define DMA_ERR_ERR11_SHIFT 11
Jasper_lee 0:b16d94660a33 4148 #define DMA_ERR_ERR12_MASK 0x1000u
Jasper_lee 0:b16d94660a33 4149 #define DMA_ERR_ERR12_SHIFT 12
Jasper_lee 0:b16d94660a33 4150 #define DMA_ERR_ERR13_MASK 0x2000u
Jasper_lee 0:b16d94660a33 4151 #define DMA_ERR_ERR13_SHIFT 13
Jasper_lee 0:b16d94660a33 4152 #define DMA_ERR_ERR14_MASK 0x4000u
Jasper_lee 0:b16d94660a33 4153 #define DMA_ERR_ERR14_SHIFT 14
Jasper_lee 0:b16d94660a33 4154 #define DMA_ERR_ERR15_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4155 #define DMA_ERR_ERR15_SHIFT 15
Jasper_lee 0:b16d94660a33 4156 /* HRS Bit Fields */
Jasper_lee 0:b16d94660a33 4157 #define DMA_HRS_HRS0_MASK 0x1u
Jasper_lee 0:b16d94660a33 4158 #define DMA_HRS_HRS0_SHIFT 0
Jasper_lee 0:b16d94660a33 4159 #define DMA_HRS_HRS1_MASK 0x2u
Jasper_lee 0:b16d94660a33 4160 #define DMA_HRS_HRS1_SHIFT 1
Jasper_lee 0:b16d94660a33 4161 #define DMA_HRS_HRS2_MASK 0x4u
Jasper_lee 0:b16d94660a33 4162 #define DMA_HRS_HRS2_SHIFT 2
Jasper_lee 0:b16d94660a33 4163 #define DMA_HRS_HRS3_MASK 0x8u
Jasper_lee 0:b16d94660a33 4164 #define DMA_HRS_HRS3_SHIFT 3
Jasper_lee 0:b16d94660a33 4165 #define DMA_HRS_HRS4_MASK 0x10u
Jasper_lee 0:b16d94660a33 4166 #define DMA_HRS_HRS4_SHIFT 4
Jasper_lee 0:b16d94660a33 4167 #define DMA_HRS_HRS5_MASK 0x20u
Jasper_lee 0:b16d94660a33 4168 #define DMA_HRS_HRS5_SHIFT 5
Jasper_lee 0:b16d94660a33 4169 #define DMA_HRS_HRS6_MASK 0x40u
Jasper_lee 0:b16d94660a33 4170 #define DMA_HRS_HRS6_SHIFT 6
Jasper_lee 0:b16d94660a33 4171 #define DMA_HRS_HRS7_MASK 0x80u
Jasper_lee 0:b16d94660a33 4172 #define DMA_HRS_HRS7_SHIFT 7
Jasper_lee 0:b16d94660a33 4173 #define DMA_HRS_HRS8_MASK 0x100u
Jasper_lee 0:b16d94660a33 4174 #define DMA_HRS_HRS8_SHIFT 8
Jasper_lee 0:b16d94660a33 4175 #define DMA_HRS_HRS9_MASK 0x200u
Jasper_lee 0:b16d94660a33 4176 #define DMA_HRS_HRS9_SHIFT 9
Jasper_lee 0:b16d94660a33 4177 #define DMA_HRS_HRS10_MASK 0x400u
Jasper_lee 0:b16d94660a33 4178 #define DMA_HRS_HRS10_SHIFT 10
Jasper_lee 0:b16d94660a33 4179 #define DMA_HRS_HRS11_MASK 0x800u
Jasper_lee 0:b16d94660a33 4180 #define DMA_HRS_HRS11_SHIFT 11
Jasper_lee 0:b16d94660a33 4181 #define DMA_HRS_HRS12_MASK 0x1000u
Jasper_lee 0:b16d94660a33 4182 #define DMA_HRS_HRS12_SHIFT 12
Jasper_lee 0:b16d94660a33 4183 #define DMA_HRS_HRS13_MASK 0x2000u
Jasper_lee 0:b16d94660a33 4184 #define DMA_HRS_HRS13_SHIFT 13
Jasper_lee 0:b16d94660a33 4185 #define DMA_HRS_HRS14_MASK 0x4000u
Jasper_lee 0:b16d94660a33 4186 #define DMA_HRS_HRS14_SHIFT 14
Jasper_lee 0:b16d94660a33 4187 #define DMA_HRS_HRS15_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4188 #define DMA_HRS_HRS15_SHIFT 15
Jasper_lee 0:b16d94660a33 4189 /* DCHPRI3 Bit Fields */
Jasper_lee 0:b16d94660a33 4190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4191 #define DMA_DCHPRI3_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4193 #define DMA_DCHPRI3_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4194 #define DMA_DCHPRI3_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4195 #define DMA_DCHPRI3_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4196 #define DMA_DCHPRI3_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4197 /* DCHPRI2 Bit Fields */
Jasper_lee 0:b16d94660a33 4198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4199 #define DMA_DCHPRI2_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4201 #define DMA_DCHPRI2_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4202 #define DMA_DCHPRI2_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4203 #define DMA_DCHPRI2_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4204 #define DMA_DCHPRI2_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4205 /* DCHPRI1 Bit Fields */
Jasper_lee 0:b16d94660a33 4206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4207 #define DMA_DCHPRI1_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4209 #define DMA_DCHPRI1_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4210 #define DMA_DCHPRI1_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4211 #define DMA_DCHPRI1_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4212 #define DMA_DCHPRI1_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4213 /* DCHPRI0 Bit Fields */
Jasper_lee 0:b16d94660a33 4214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4215 #define DMA_DCHPRI0_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4217 #define DMA_DCHPRI0_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4218 #define DMA_DCHPRI0_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4219 #define DMA_DCHPRI0_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4220 #define DMA_DCHPRI0_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4221 /* DCHPRI7 Bit Fields */
Jasper_lee 0:b16d94660a33 4222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4223 #define DMA_DCHPRI7_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4225 #define DMA_DCHPRI7_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4226 #define DMA_DCHPRI7_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4227 #define DMA_DCHPRI7_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4228 #define DMA_DCHPRI7_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4229 /* DCHPRI6 Bit Fields */
Jasper_lee 0:b16d94660a33 4230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4231 #define DMA_DCHPRI6_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4233 #define DMA_DCHPRI6_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4234 #define DMA_DCHPRI6_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4235 #define DMA_DCHPRI6_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4236 #define DMA_DCHPRI6_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4237 /* DCHPRI5 Bit Fields */
Jasper_lee 0:b16d94660a33 4238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4239 #define DMA_DCHPRI5_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4241 #define DMA_DCHPRI5_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4242 #define DMA_DCHPRI5_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4243 #define DMA_DCHPRI5_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4244 #define DMA_DCHPRI5_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4245 /* DCHPRI4 Bit Fields */
Jasper_lee 0:b16d94660a33 4246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4247 #define DMA_DCHPRI4_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4249 #define DMA_DCHPRI4_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4250 #define DMA_DCHPRI4_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4251 #define DMA_DCHPRI4_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4252 #define DMA_DCHPRI4_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4253 /* DCHPRI11 Bit Fields */
Jasper_lee 0:b16d94660a33 4254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4255 #define DMA_DCHPRI11_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4257 #define DMA_DCHPRI11_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4258 #define DMA_DCHPRI11_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4259 #define DMA_DCHPRI11_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4260 #define DMA_DCHPRI11_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4261 /* DCHPRI10 Bit Fields */
Jasper_lee 0:b16d94660a33 4262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4263 #define DMA_DCHPRI10_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4265 #define DMA_DCHPRI10_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4266 #define DMA_DCHPRI10_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4267 #define DMA_DCHPRI10_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4268 #define DMA_DCHPRI10_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4269 /* DCHPRI9 Bit Fields */
Jasper_lee 0:b16d94660a33 4270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4271 #define DMA_DCHPRI9_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4273 #define DMA_DCHPRI9_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4274 #define DMA_DCHPRI9_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4275 #define DMA_DCHPRI9_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4276 #define DMA_DCHPRI9_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4277 /* DCHPRI8 Bit Fields */
Jasper_lee 0:b16d94660a33 4278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4279 #define DMA_DCHPRI8_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4281 #define DMA_DCHPRI8_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4282 #define DMA_DCHPRI8_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4283 #define DMA_DCHPRI8_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4284 #define DMA_DCHPRI8_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4285 /* DCHPRI15 Bit Fields */
Jasper_lee 0:b16d94660a33 4286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4287 #define DMA_DCHPRI15_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4289 #define DMA_DCHPRI15_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4290 #define DMA_DCHPRI15_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4291 #define DMA_DCHPRI15_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4292 #define DMA_DCHPRI15_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4293 /* DCHPRI14 Bit Fields */
Jasper_lee 0:b16d94660a33 4294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4295 #define DMA_DCHPRI14_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4297 #define DMA_DCHPRI14_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4298 #define DMA_DCHPRI14_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4299 #define DMA_DCHPRI14_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4300 #define DMA_DCHPRI14_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4301 /* DCHPRI13 Bit Fields */
Jasper_lee 0:b16d94660a33 4302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4303 #define DMA_DCHPRI13_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4305 #define DMA_DCHPRI13_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4306 #define DMA_DCHPRI13_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4307 #define DMA_DCHPRI13_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4308 #define DMA_DCHPRI13_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4309 /* DCHPRI12 Bit Fields */
Jasper_lee 0:b16d94660a33 4310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
Jasper_lee 0:b16d94660a33 4311 #define DMA_DCHPRI12_CHPRI_SHIFT 0
Jasper_lee 0:b16d94660a33 4312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
Jasper_lee 0:b16d94660a33 4313 #define DMA_DCHPRI12_DPA_MASK 0x40u
Jasper_lee 0:b16d94660a33 4314 #define DMA_DCHPRI12_DPA_SHIFT 6
Jasper_lee 0:b16d94660a33 4315 #define DMA_DCHPRI12_ECP_MASK 0x80u
Jasper_lee 0:b16d94660a33 4316 #define DMA_DCHPRI12_ECP_SHIFT 7
Jasper_lee 0:b16d94660a33 4317 /* SADDR Bit Fields */
Jasper_lee 0:b16d94660a33 4318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 4319 #define DMA_SADDR_SADDR_SHIFT 0
Jasper_lee 0:b16d94660a33 4320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
Jasper_lee 0:b16d94660a33 4321 /* SOFF Bit Fields */
Jasper_lee 0:b16d94660a33 4322 #define DMA_SOFF_SOFF_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 4323 #define DMA_SOFF_SOFF_SHIFT 0
Jasper_lee 0:b16d94660a33 4324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
Jasper_lee 0:b16d94660a33 4325 /* ATTR Bit Fields */
Jasper_lee 0:b16d94660a33 4326 #define DMA_ATTR_DSIZE_MASK 0x7u
Jasper_lee 0:b16d94660a33 4327 #define DMA_ATTR_DSIZE_SHIFT 0
Jasper_lee 0:b16d94660a33 4328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
Jasper_lee 0:b16d94660a33 4329 #define DMA_ATTR_DMOD_MASK 0xF8u
Jasper_lee 0:b16d94660a33 4330 #define DMA_ATTR_DMOD_SHIFT 3
Jasper_lee 0:b16d94660a33 4331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
Jasper_lee 0:b16d94660a33 4332 #define DMA_ATTR_SSIZE_MASK 0x700u
Jasper_lee 0:b16d94660a33 4333 #define DMA_ATTR_SSIZE_SHIFT 8
Jasper_lee 0:b16d94660a33 4334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
Jasper_lee 0:b16d94660a33 4335 #define DMA_ATTR_SMOD_MASK 0xF800u
Jasper_lee 0:b16d94660a33 4336 #define DMA_ATTR_SMOD_SHIFT 11
Jasper_lee 0:b16d94660a33 4337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
Jasper_lee 0:b16d94660a33 4338 /* NBYTES_MLNO Bit Fields */
Jasper_lee 0:b16d94660a33 4339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 4340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
Jasper_lee 0:b16d94660a33 4341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
Jasper_lee 0:b16d94660a33 4342 /* NBYTES_MLOFFNO Bit Fields */
Jasper_lee 0:b16d94660a33 4343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
Jasper_lee 0:b16d94660a33 4344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
Jasper_lee 0:b16d94660a33 4345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
Jasper_lee 0:b16d94660a33 4346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 4347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
Jasper_lee 0:b16d94660a33 4348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 4349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
Jasper_lee 0:b16d94660a33 4350 /* NBYTES_MLOFFYES Bit Fields */
Jasper_lee 0:b16d94660a33 4351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
Jasper_lee 0:b16d94660a33 4352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
Jasper_lee 0:b16d94660a33 4353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
Jasper_lee 0:b16d94660a33 4354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
Jasper_lee 0:b16d94660a33 4355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
Jasper_lee 0:b16d94660a33 4356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
Jasper_lee 0:b16d94660a33 4357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 4358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
Jasper_lee 0:b16d94660a33 4359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 4360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
Jasper_lee 0:b16d94660a33 4361 /* SLAST Bit Fields */
Jasper_lee 0:b16d94660a33 4362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 4363 #define DMA_SLAST_SLAST_SHIFT 0
Jasper_lee 0:b16d94660a33 4364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
Jasper_lee 0:b16d94660a33 4365 /* DADDR Bit Fields */
Jasper_lee 0:b16d94660a33 4366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 4367 #define DMA_DADDR_DADDR_SHIFT 0
Jasper_lee 0:b16d94660a33 4368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
Jasper_lee 0:b16d94660a33 4369 /* DOFF Bit Fields */
Jasper_lee 0:b16d94660a33 4370 #define DMA_DOFF_DOFF_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 4371 #define DMA_DOFF_DOFF_SHIFT 0
Jasper_lee 0:b16d94660a33 4372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
Jasper_lee 0:b16d94660a33 4373 /* CITER_ELINKNO Bit Fields */
Jasper_lee 0:b16d94660a33 4374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
Jasper_lee 0:b16d94660a33 4375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
Jasper_lee 0:b16d94660a33 4376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
Jasper_lee 0:b16d94660a33 4377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
Jasper_lee 0:b16d94660a33 4379 /* CITER_ELINKYES Bit Fields */
Jasper_lee 0:b16d94660a33 4380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
Jasper_lee 0:b16d94660a33 4381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
Jasper_lee 0:b16d94660a33 4382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
Jasper_lee 0:b16d94660a33 4383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
Jasper_lee 0:b16d94660a33 4384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
Jasper_lee 0:b16d94660a33 4385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
Jasper_lee 0:b16d94660a33 4386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
Jasper_lee 0:b16d94660a33 4388 /* DLAST_SGA Bit Fields */
Jasper_lee 0:b16d94660a33 4389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 4390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
Jasper_lee 0:b16d94660a33 4391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
Jasper_lee 0:b16d94660a33 4392 /* CSR Bit Fields */
Jasper_lee 0:b16d94660a33 4393 #define DMA_CSR_START_MASK 0x1u
Jasper_lee 0:b16d94660a33 4394 #define DMA_CSR_START_SHIFT 0
Jasper_lee 0:b16d94660a33 4395 #define DMA_CSR_INTMAJOR_MASK 0x2u
Jasper_lee 0:b16d94660a33 4396 #define DMA_CSR_INTMAJOR_SHIFT 1
Jasper_lee 0:b16d94660a33 4397 #define DMA_CSR_INTHALF_MASK 0x4u
Jasper_lee 0:b16d94660a33 4398 #define DMA_CSR_INTHALF_SHIFT 2
Jasper_lee 0:b16d94660a33 4399 #define DMA_CSR_DREQ_MASK 0x8u
Jasper_lee 0:b16d94660a33 4400 #define DMA_CSR_DREQ_SHIFT 3
Jasper_lee 0:b16d94660a33 4401 #define DMA_CSR_ESG_MASK 0x10u
Jasper_lee 0:b16d94660a33 4402 #define DMA_CSR_ESG_SHIFT 4
Jasper_lee 0:b16d94660a33 4403 #define DMA_CSR_MAJORELINK_MASK 0x20u
Jasper_lee 0:b16d94660a33 4404 #define DMA_CSR_MAJORELINK_SHIFT 5
Jasper_lee 0:b16d94660a33 4405 #define DMA_CSR_ACTIVE_MASK 0x40u
Jasper_lee 0:b16d94660a33 4406 #define DMA_CSR_ACTIVE_SHIFT 6
Jasper_lee 0:b16d94660a33 4407 #define DMA_CSR_DONE_MASK 0x80u
Jasper_lee 0:b16d94660a33 4408 #define DMA_CSR_DONE_SHIFT 7
Jasper_lee 0:b16d94660a33 4409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
Jasper_lee 0:b16d94660a33 4410 #define DMA_CSR_MAJORLINKCH_SHIFT 8
Jasper_lee 0:b16d94660a33 4411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
Jasper_lee 0:b16d94660a33 4412 #define DMA_CSR_BWC_MASK 0xC000u
Jasper_lee 0:b16d94660a33 4413 #define DMA_CSR_BWC_SHIFT 14
Jasper_lee 0:b16d94660a33 4414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
Jasper_lee 0:b16d94660a33 4415 /* BITER_ELINKNO Bit Fields */
Jasper_lee 0:b16d94660a33 4416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
Jasper_lee 0:b16d94660a33 4417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
Jasper_lee 0:b16d94660a33 4418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
Jasper_lee 0:b16d94660a33 4419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
Jasper_lee 0:b16d94660a33 4421 /* BITER_ELINKYES Bit Fields */
Jasper_lee 0:b16d94660a33 4422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
Jasper_lee 0:b16d94660a33 4423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
Jasper_lee 0:b16d94660a33 4424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
Jasper_lee 0:b16d94660a33 4425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
Jasper_lee 0:b16d94660a33 4426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
Jasper_lee 0:b16d94660a33 4427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
Jasper_lee 0:b16d94660a33 4428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 4429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
Jasper_lee 0:b16d94660a33 4430
Jasper_lee 0:b16d94660a33 4431 /*!
Jasper_lee 0:b16d94660a33 4432 * @}
Jasper_lee 0:b16d94660a33 4433 */ /* end of group DMA_Register_Masks */
Jasper_lee 0:b16d94660a33 4434
Jasper_lee 0:b16d94660a33 4435
Jasper_lee 0:b16d94660a33 4436 /* DMA - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 4437 /** Peripheral DMA base address */
Jasper_lee 0:b16d94660a33 4438 #define DMA_BASE (0x40008000u)
Jasper_lee 0:b16d94660a33 4439 /** Peripheral DMA base pointer */
Jasper_lee 0:b16d94660a33 4440 #define DMA0 ((DMA_Type *)DMA_BASE)
Jasper_lee 0:b16d94660a33 4441 #define DMA_BASE_PTR (DMA0)
Jasper_lee 0:b16d94660a33 4442 /** Array initializer of DMA peripheral base addresses */
Jasper_lee 0:b16d94660a33 4443 #define DMA_BASE_ADDRS { DMA_BASE }
Jasper_lee 0:b16d94660a33 4444 /** Array initializer of DMA peripheral base pointers */
Jasper_lee 0:b16d94660a33 4445 #define DMA_BASE_PTRS { DMA0 }
Jasper_lee 0:b16d94660a33 4446 /** Interrupt vectors for the DMA peripheral type */
Jasper_lee 0:b16d94660a33 4447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
Jasper_lee 0:b16d94660a33 4448 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
Jasper_lee 0:b16d94660a33 4449
Jasper_lee 0:b16d94660a33 4450 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4451 -- DMA - Register accessor macros
Jasper_lee 0:b16d94660a33 4452 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4453
Jasper_lee 0:b16d94660a33 4454 /*!
Jasper_lee 0:b16d94660a33 4455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Jasper_lee 0:b16d94660a33 4456 * @{
Jasper_lee 0:b16d94660a33 4457 */
Jasper_lee 0:b16d94660a33 4458
Jasper_lee 0:b16d94660a33 4459
Jasper_lee 0:b16d94660a33 4460 /* DMA - Register instance definitions */
Jasper_lee 0:b16d94660a33 4461 /* DMA */
Jasper_lee 0:b16d94660a33 4462 #define DMA_CR DMA_CR_REG(DMA0)
Jasper_lee 0:b16d94660a33 4463 #define DMA_ES DMA_ES_REG(DMA0)
Jasper_lee 0:b16d94660a33 4464 #define DMA_ERQ DMA_ERQ_REG(DMA0)
Jasper_lee 0:b16d94660a33 4465 #define DMA_EEI DMA_EEI_REG(DMA0)
Jasper_lee 0:b16d94660a33 4466 #define DMA_CEEI DMA_CEEI_REG(DMA0)
Jasper_lee 0:b16d94660a33 4467 #define DMA_SEEI DMA_SEEI_REG(DMA0)
Jasper_lee 0:b16d94660a33 4468 #define DMA_CERQ DMA_CERQ_REG(DMA0)
Jasper_lee 0:b16d94660a33 4469 #define DMA_SERQ DMA_SERQ_REG(DMA0)
Jasper_lee 0:b16d94660a33 4470 #define DMA_CDNE DMA_CDNE_REG(DMA0)
Jasper_lee 0:b16d94660a33 4471 #define DMA_SSRT DMA_SSRT_REG(DMA0)
Jasper_lee 0:b16d94660a33 4472 #define DMA_CERR DMA_CERR_REG(DMA0)
Jasper_lee 0:b16d94660a33 4473 #define DMA_CINT DMA_CINT_REG(DMA0)
Jasper_lee 0:b16d94660a33 4474 #define DMA_INT DMA_INT_REG(DMA0)
Jasper_lee 0:b16d94660a33 4475 #define DMA_ERR DMA_ERR_REG(DMA0)
Jasper_lee 0:b16d94660a33 4476 #define DMA_HRS DMA_HRS_REG(DMA0)
Jasper_lee 0:b16d94660a33 4477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
Jasper_lee 0:b16d94660a33 4478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
Jasper_lee 0:b16d94660a33 4479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
Jasper_lee 0:b16d94660a33 4480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
Jasper_lee 0:b16d94660a33 4481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
Jasper_lee 0:b16d94660a33 4482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
Jasper_lee 0:b16d94660a33 4483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
Jasper_lee 0:b16d94660a33 4484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
Jasper_lee 0:b16d94660a33 4485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
Jasper_lee 0:b16d94660a33 4486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
Jasper_lee 0:b16d94660a33 4487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
Jasper_lee 0:b16d94660a33 4488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
Jasper_lee 0:b16d94660a33 4489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
Jasper_lee 0:b16d94660a33 4490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
Jasper_lee 0:b16d94660a33 4491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
Jasper_lee 0:b16d94660a33 4492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
Jasper_lee 0:b16d94660a33 4493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
Jasper_lee 0:b16d94660a33 4508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
Jasper_lee 0:b16d94660a33 4523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
Jasper_lee 0:b16d94660a33 4538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
Jasper_lee 0:b16d94660a33 4553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
Jasper_lee 0:b16d94660a33 4568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
Jasper_lee 0:b16d94660a33 4583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
Jasper_lee 0:b16d94660a33 4598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
Jasper_lee 0:b16d94660a33 4613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
Jasper_lee 0:b16d94660a33 4628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
Jasper_lee 0:b16d94660a33 4643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
Jasper_lee 0:b16d94660a33 4658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
Jasper_lee 0:b16d94660a33 4673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
Jasper_lee 0:b16d94660a33 4688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
Jasper_lee 0:b16d94660a33 4703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
Jasper_lee 0:b16d94660a33 4718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
Jasper_lee 0:b16d94660a33 4733
Jasper_lee 0:b16d94660a33 4734 /* DMA - Register array accessors */
Jasper_lee 0:b16d94660a33 4735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
Jasper_lee 0:b16d94660a33 4750
Jasper_lee 0:b16d94660a33 4751 /*!
Jasper_lee 0:b16d94660a33 4752 * @}
Jasper_lee 0:b16d94660a33 4753 */ /* end of group DMA_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 4754
Jasper_lee 0:b16d94660a33 4755
Jasper_lee 0:b16d94660a33 4756 /*!
Jasper_lee 0:b16d94660a33 4757 * @}
Jasper_lee 0:b16d94660a33 4758 */ /* end of group DMA_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 4759
Jasper_lee 0:b16d94660a33 4760
Jasper_lee 0:b16d94660a33 4761 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4762 -- DMAMUX Peripheral Access Layer
Jasper_lee 0:b16d94660a33 4763 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4764
Jasper_lee 0:b16d94660a33 4765 /*!
Jasper_lee 0:b16d94660a33 4766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Jasper_lee 0:b16d94660a33 4767 * @{
Jasper_lee 0:b16d94660a33 4768 */
Jasper_lee 0:b16d94660a33 4769
Jasper_lee 0:b16d94660a33 4770 /** DMAMUX - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 4771 typedef struct {
Jasper_lee 0:b16d94660a33 4772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
Jasper_lee 0:b16d94660a33 4773 } DMAMUX_Type, *DMAMUX_MemMapPtr;
Jasper_lee 0:b16d94660a33 4774
Jasper_lee 0:b16d94660a33 4775 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4776 -- DMAMUX - Register accessor macros
Jasper_lee 0:b16d94660a33 4777 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4778
Jasper_lee 0:b16d94660a33 4779 /*!
Jasper_lee 0:b16d94660a33 4780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Jasper_lee 0:b16d94660a33 4781 * @{
Jasper_lee 0:b16d94660a33 4782 */
Jasper_lee 0:b16d94660a33 4783
Jasper_lee 0:b16d94660a33 4784
Jasper_lee 0:b16d94660a33 4785 /* DMAMUX - Register accessors */
Jasper_lee 0:b16d94660a33 4786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
Jasper_lee 0:b16d94660a33 4787
Jasper_lee 0:b16d94660a33 4788 /*!
Jasper_lee 0:b16d94660a33 4789 * @}
Jasper_lee 0:b16d94660a33 4790 */ /* end of group DMAMUX_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 4791
Jasper_lee 0:b16d94660a33 4792
Jasper_lee 0:b16d94660a33 4793 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4794 -- DMAMUX Register Masks
Jasper_lee 0:b16d94660a33 4795 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4796
Jasper_lee 0:b16d94660a33 4797 /*!
Jasper_lee 0:b16d94660a33 4798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Jasper_lee 0:b16d94660a33 4799 * @{
Jasper_lee 0:b16d94660a33 4800 */
Jasper_lee 0:b16d94660a33 4801
Jasper_lee 0:b16d94660a33 4802 /* CHCFG Bit Fields */
Jasper_lee 0:b16d94660a33 4803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 4804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
Jasper_lee 0:b16d94660a33 4805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
Jasper_lee 0:b16d94660a33 4806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
Jasper_lee 0:b16d94660a33 4807 #define DMAMUX_CHCFG_TRIG_SHIFT 6
Jasper_lee 0:b16d94660a33 4808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
Jasper_lee 0:b16d94660a33 4809 #define DMAMUX_CHCFG_ENBL_SHIFT 7
Jasper_lee 0:b16d94660a33 4810
Jasper_lee 0:b16d94660a33 4811 /*!
Jasper_lee 0:b16d94660a33 4812 * @}
Jasper_lee 0:b16d94660a33 4813 */ /* end of group DMAMUX_Register_Masks */
Jasper_lee 0:b16d94660a33 4814
Jasper_lee 0:b16d94660a33 4815
Jasper_lee 0:b16d94660a33 4816 /* DMAMUX - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 4817 /** Peripheral DMAMUX base address */
Jasper_lee 0:b16d94660a33 4818 #define DMAMUX_BASE (0x40021000u)
Jasper_lee 0:b16d94660a33 4819 /** Peripheral DMAMUX base pointer */
Jasper_lee 0:b16d94660a33 4820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
Jasper_lee 0:b16d94660a33 4821 #define DMAMUX_BASE_PTR (DMAMUX)
Jasper_lee 0:b16d94660a33 4822 /** Array initializer of DMAMUX peripheral base addresses */
Jasper_lee 0:b16d94660a33 4823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
Jasper_lee 0:b16d94660a33 4824 /** Array initializer of DMAMUX peripheral base pointers */
Jasper_lee 0:b16d94660a33 4825 #define DMAMUX_BASE_PTRS { DMAMUX }
Jasper_lee 0:b16d94660a33 4826
Jasper_lee 0:b16d94660a33 4827 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4828 -- DMAMUX - Register accessor macros
Jasper_lee 0:b16d94660a33 4829 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4830
Jasper_lee 0:b16d94660a33 4831 /*!
Jasper_lee 0:b16d94660a33 4832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Jasper_lee 0:b16d94660a33 4833 * @{
Jasper_lee 0:b16d94660a33 4834 */
Jasper_lee 0:b16d94660a33 4835
Jasper_lee 0:b16d94660a33 4836
Jasper_lee 0:b16d94660a33 4837 /* DMAMUX - Register instance definitions */
Jasper_lee 0:b16d94660a33 4838 /* DMAMUX */
Jasper_lee 0:b16d94660a33 4839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
Jasper_lee 0:b16d94660a33 4840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
Jasper_lee 0:b16d94660a33 4841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
Jasper_lee 0:b16d94660a33 4842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
Jasper_lee 0:b16d94660a33 4843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
Jasper_lee 0:b16d94660a33 4844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
Jasper_lee 0:b16d94660a33 4845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
Jasper_lee 0:b16d94660a33 4846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
Jasper_lee 0:b16d94660a33 4847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
Jasper_lee 0:b16d94660a33 4848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
Jasper_lee 0:b16d94660a33 4849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
Jasper_lee 0:b16d94660a33 4850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
Jasper_lee 0:b16d94660a33 4851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
Jasper_lee 0:b16d94660a33 4852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
Jasper_lee 0:b16d94660a33 4853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
Jasper_lee 0:b16d94660a33 4854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
Jasper_lee 0:b16d94660a33 4855
Jasper_lee 0:b16d94660a33 4856 /* DMAMUX - Register array accessors */
Jasper_lee 0:b16d94660a33 4857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
Jasper_lee 0:b16d94660a33 4858
Jasper_lee 0:b16d94660a33 4859 /*!
Jasper_lee 0:b16d94660a33 4860 * @}
Jasper_lee 0:b16d94660a33 4861 */ /* end of group DMAMUX_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 4862
Jasper_lee 0:b16d94660a33 4863
Jasper_lee 0:b16d94660a33 4864 /*!
Jasper_lee 0:b16d94660a33 4865 * @}
Jasper_lee 0:b16d94660a33 4866 */ /* end of group DMAMUX_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 4867
Jasper_lee 0:b16d94660a33 4868
Jasper_lee 0:b16d94660a33 4869 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4870 -- ENET Peripheral Access Layer
Jasper_lee 0:b16d94660a33 4871 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4872
Jasper_lee 0:b16d94660a33 4873 /*!
Jasper_lee 0:b16d94660a33 4874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
Jasper_lee 0:b16d94660a33 4875 * @{
Jasper_lee 0:b16d94660a33 4876 */
Jasper_lee 0:b16d94660a33 4877
Jasper_lee 0:b16d94660a33 4878 /** ENET - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 4879 typedef struct {
Jasper_lee 0:b16d94660a33 4880 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 4881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 4882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 4883 uint8_t RESERVED_1[4];
Jasper_lee 0:b16d94660a33 4884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 4885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 4886 uint8_t RESERVED_2[12];
Jasper_lee 0:b16d94660a33 4887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
Jasper_lee 0:b16d94660a33 4888 uint8_t RESERVED_3[24];
Jasper_lee 0:b16d94660a33 4889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
Jasper_lee 0:b16d94660a33 4890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
Jasper_lee 0:b16d94660a33 4891 uint8_t RESERVED_4[28];
Jasper_lee 0:b16d94660a33 4892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
Jasper_lee 0:b16d94660a33 4893 uint8_t RESERVED_5[28];
Jasper_lee 0:b16d94660a33 4894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
Jasper_lee 0:b16d94660a33 4895 uint8_t RESERVED_6[60];
Jasper_lee 0:b16d94660a33 4896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
Jasper_lee 0:b16d94660a33 4897 uint8_t RESERVED_7[28];
Jasper_lee 0:b16d94660a33 4898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
Jasper_lee 0:b16d94660a33 4899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
Jasper_lee 0:b16d94660a33 4900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
Jasper_lee 0:b16d94660a33 4901 uint8_t RESERVED_8[40];
Jasper_lee 0:b16d94660a33 4902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
Jasper_lee 0:b16d94660a33 4903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
Jasper_lee 0:b16d94660a33 4904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
Jasper_lee 0:b16d94660a33 4905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
Jasper_lee 0:b16d94660a33 4906 uint8_t RESERVED_9[28];
Jasper_lee 0:b16d94660a33 4907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
Jasper_lee 0:b16d94660a33 4908 uint8_t RESERVED_10[56];
Jasper_lee 0:b16d94660a33 4909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
Jasper_lee 0:b16d94660a33 4910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
Jasper_lee 0:b16d94660a33 4911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
Jasper_lee 0:b16d94660a33 4912 uint8_t RESERVED_11[4];
Jasper_lee 0:b16d94660a33 4913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
Jasper_lee 0:b16d94660a33 4914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
Jasper_lee 0:b16d94660a33 4915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
Jasper_lee 0:b16d94660a33 4916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
Jasper_lee 0:b16d94660a33 4917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
Jasper_lee 0:b16d94660a33 4918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
Jasper_lee 0:b16d94660a33 4919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
Jasper_lee 0:b16d94660a33 4920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
Jasper_lee 0:b16d94660a33 4921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
Jasper_lee 0:b16d94660a33 4922 uint8_t RESERVED_12[12];
Jasper_lee 0:b16d94660a33 4923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
Jasper_lee 0:b16d94660a33 4924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
Jasper_lee 0:b16d94660a33 4925 uint8_t RESERVED_13[60];
Jasper_lee 0:b16d94660a33 4926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
Jasper_lee 0:b16d94660a33 4927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
Jasper_lee 0:b16d94660a33 4928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
Jasper_lee 0:b16d94660a33 4929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
Jasper_lee 0:b16d94660a33 4930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
Jasper_lee 0:b16d94660a33 4931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
Jasper_lee 0:b16d94660a33 4932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
Jasper_lee 0:b16d94660a33 4933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
Jasper_lee 0:b16d94660a33 4934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
Jasper_lee 0:b16d94660a33 4935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
Jasper_lee 0:b16d94660a33 4936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
Jasper_lee 0:b16d94660a33 4937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
Jasper_lee 0:b16d94660a33 4938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
Jasper_lee 0:b16d94660a33 4939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
Jasper_lee 0:b16d94660a33 4940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
Jasper_lee 0:b16d94660a33 4941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
Jasper_lee 0:b16d94660a33 4942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
Jasper_lee 0:b16d94660a33 4943 uint8_t RESERVED_14[4];
Jasper_lee 0:b16d94660a33 4944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
Jasper_lee 0:b16d94660a33 4945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
Jasper_lee 0:b16d94660a33 4946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
Jasper_lee 0:b16d94660a33 4947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
Jasper_lee 0:b16d94660a33 4948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
Jasper_lee 0:b16d94660a33 4949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
Jasper_lee 0:b16d94660a33 4950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
Jasper_lee 0:b16d94660a33 4951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
Jasper_lee 0:b16d94660a33 4952 uint8_t RESERVED_15[4];
Jasper_lee 0:b16d94660a33 4953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
Jasper_lee 0:b16d94660a33 4954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
Jasper_lee 0:b16d94660a33 4955 uint8_t RESERVED_16[12];
Jasper_lee 0:b16d94660a33 4956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
Jasper_lee 0:b16d94660a33 4957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
Jasper_lee 0:b16d94660a33 4958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
Jasper_lee 0:b16d94660a33 4959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
Jasper_lee 0:b16d94660a33 4960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
Jasper_lee 0:b16d94660a33 4961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
Jasper_lee 0:b16d94660a33 4962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
Jasper_lee 0:b16d94660a33 4963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
Jasper_lee 0:b16d94660a33 4964 uint8_t RESERVED_17[4];
Jasper_lee 0:b16d94660a33 4965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
Jasper_lee 0:b16d94660a33 4966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
Jasper_lee 0:b16d94660a33 4967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
Jasper_lee 0:b16d94660a33 4968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
Jasper_lee 0:b16d94660a33 4969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
Jasper_lee 0:b16d94660a33 4970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
Jasper_lee 0:b16d94660a33 4971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
Jasper_lee 0:b16d94660a33 4972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
Jasper_lee 0:b16d94660a33 4973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
Jasper_lee 0:b16d94660a33 4974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
Jasper_lee 0:b16d94660a33 4975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
Jasper_lee 0:b16d94660a33 4976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
Jasper_lee 0:b16d94660a33 4977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
Jasper_lee 0:b16d94660a33 4978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
Jasper_lee 0:b16d94660a33 4979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
Jasper_lee 0:b16d94660a33 4980 uint8_t RESERVED_18[284];
Jasper_lee 0:b16d94660a33 4981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
Jasper_lee 0:b16d94660a33 4982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
Jasper_lee 0:b16d94660a33 4983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
Jasper_lee 0:b16d94660a33 4984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
Jasper_lee 0:b16d94660a33 4985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
Jasper_lee 0:b16d94660a33 4986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
Jasper_lee 0:b16d94660a33 4987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
Jasper_lee 0:b16d94660a33 4988 uint8_t RESERVED_19[488];
Jasper_lee 0:b16d94660a33 4989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
Jasper_lee 0:b16d94660a33 4990 struct { /* offset: 0x608, array step: 0x8 */
Jasper_lee 0:b16d94660a33 4991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
Jasper_lee 0:b16d94660a33 4992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
Jasper_lee 0:b16d94660a33 4993 } CHANNEL[4];
Jasper_lee 0:b16d94660a33 4994 } ENET_Type, *ENET_MemMapPtr;
Jasper_lee 0:b16d94660a33 4995
Jasper_lee 0:b16d94660a33 4996 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 4997 -- ENET - Register accessor macros
Jasper_lee 0:b16d94660a33 4998 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 4999
Jasper_lee 0:b16d94660a33 5000 /*!
Jasper_lee 0:b16d94660a33 5001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
Jasper_lee 0:b16d94660a33 5002 * @{
Jasper_lee 0:b16d94660a33 5003 */
Jasper_lee 0:b16d94660a33 5004
Jasper_lee 0:b16d94660a33 5005
Jasper_lee 0:b16d94660a33 5006 /* ENET - Register accessors */
Jasper_lee 0:b16d94660a33 5007 #define ENET_EIR_REG(base) ((base)->EIR)
Jasper_lee 0:b16d94660a33 5008 #define ENET_EIMR_REG(base) ((base)->EIMR)
Jasper_lee 0:b16d94660a33 5009 #define ENET_RDAR_REG(base) ((base)->RDAR)
Jasper_lee 0:b16d94660a33 5010 #define ENET_TDAR_REG(base) ((base)->TDAR)
Jasper_lee 0:b16d94660a33 5011 #define ENET_ECR_REG(base) ((base)->ECR)
Jasper_lee 0:b16d94660a33 5012 #define ENET_MMFR_REG(base) ((base)->MMFR)
Jasper_lee 0:b16d94660a33 5013 #define ENET_MSCR_REG(base) ((base)->MSCR)
Jasper_lee 0:b16d94660a33 5014 #define ENET_MIBC_REG(base) ((base)->MIBC)
Jasper_lee 0:b16d94660a33 5015 #define ENET_RCR_REG(base) ((base)->RCR)
Jasper_lee 0:b16d94660a33 5016 #define ENET_TCR_REG(base) ((base)->TCR)
Jasper_lee 0:b16d94660a33 5017 #define ENET_PALR_REG(base) ((base)->PALR)
Jasper_lee 0:b16d94660a33 5018 #define ENET_PAUR_REG(base) ((base)->PAUR)
Jasper_lee 0:b16d94660a33 5019 #define ENET_OPD_REG(base) ((base)->OPD)
Jasper_lee 0:b16d94660a33 5020 #define ENET_IAUR_REG(base) ((base)->IAUR)
Jasper_lee 0:b16d94660a33 5021 #define ENET_IALR_REG(base) ((base)->IALR)
Jasper_lee 0:b16d94660a33 5022 #define ENET_GAUR_REG(base) ((base)->GAUR)
Jasper_lee 0:b16d94660a33 5023 #define ENET_GALR_REG(base) ((base)->GALR)
Jasper_lee 0:b16d94660a33 5024 #define ENET_TFWR_REG(base) ((base)->TFWR)
Jasper_lee 0:b16d94660a33 5025 #define ENET_RDSR_REG(base) ((base)->RDSR)
Jasper_lee 0:b16d94660a33 5026 #define ENET_TDSR_REG(base) ((base)->TDSR)
Jasper_lee 0:b16d94660a33 5027 #define ENET_MRBR_REG(base) ((base)->MRBR)
Jasper_lee 0:b16d94660a33 5028 #define ENET_RSFL_REG(base) ((base)->RSFL)
Jasper_lee 0:b16d94660a33 5029 #define ENET_RSEM_REG(base) ((base)->RSEM)
Jasper_lee 0:b16d94660a33 5030 #define ENET_RAEM_REG(base) ((base)->RAEM)
Jasper_lee 0:b16d94660a33 5031 #define ENET_RAFL_REG(base) ((base)->RAFL)
Jasper_lee 0:b16d94660a33 5032 #define ENET_TSEM_REG(base) ((base)->TSEM)
Jasper_lee 0:b16d94660a33 5033 #define ENET_TAEM_REG(base) ((base)->TAEM)
Jasper_lee 0:b16d94660a33 5034 #define ENET_TAFL_REG(base) ((base)->TAFL)
Jasper_lee 0:b16d94660a33 5035 #define ENET_TIPG_REG(base) ((base)->TIPG)
Jasper_lee 0:b16d94660a33 5036 #define ENET_FTRL_REG(base) ((base)->FTRL)
Jasper_lee 0:b16d94660a33 5037 #define ENET_TACC_REG(base) ((base)->TACC)
Jasper_lee 0:b16d94660a33 5038 #define ENET_RACC_REG(base) ((base)->RACC)
Jasper_lee 0:b16d94660a33 5039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
Jasper_lee 0:b16d94660a33 5040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
Jasper_lee 0:b16d94660a33 5041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
Jasper_lee 0:b16d94660a33 5042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
Jasper_lee 0:b16d94660a33 5043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
Jasper_lee 0:b16d94660a33 5044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
Jasper_lee 0:b16d94660a33 5045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
Jasper_lee 0:b16d94660a33 5046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
Jasper_lee 0:b16d94660a33 5047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
Jasper_lee 0:b16d94660a33 5048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
Jasper_lee 0:b16d94660a33 5049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
Jasper_lee 0:b16d94660a33 5050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
Jasper_lee 0:b16d94660a33 5051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
Jasper_lee 0:b16d94660a33 5052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
Jasper_lee 0:b16d94660a33 5053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
Jasper_lee 0:b16d94660a33 5054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
Jasper_lee 0:b16d94660a33 5055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
Jasper_lee 0:b16d94660a33 5056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
Jasper_lee 0:b16d94660a33 5057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
Jasper_lee 0:b16d94660a33 5058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
Jasper_lee 0:b16d94660a33 5059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
Jasper_lee 0:b16d94660a33 5060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
Jasper_lee 0:b16d94660a33 5061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
Jasper_lee 0:b16d94660a33 5062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
Jasper_lee 0:b16d94660a33 5063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
Jasper_lee 0:b16d94660a33 5064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
Jasper_lee 0:b16d94660a33 5065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
Jasper_lee 0:b16d94660a33 5066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
Jasper_lee 0:b16d94660a33 5067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
Jasper_lee 0:b16d94660a33 5068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
Jasper_lee 0:b16d94660a33 5069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
Jasper_lee 0:b16d94660a33 5070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
Jasper_lee 0:b16d94660a33 5071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
Jasper_lee 0:b16d94660a33 5072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
Jasper_lee 0:b16d94660a33 5073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
Jasper_lee 0:b16d94660a33 5074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
Jasper_lee 0:b16d94660a33 5075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
Jasper_lee 0:b16d94660a33 5076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
Jasper_lee 0:b16d94660a33 5077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
Jasper_lee 0:b16d94660a33 5078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
Jasper_lee 0:b16d94660a33 5079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
Jasper_lee 0:b16d94660a33 5080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
Jasper_lee 0:b16d94660a33 5081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
Jasper_lee 0:b16d94660a33 5082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
Jasper_lee 0:b16d94660a33 5083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
Jasper_lee 0:b16d94660a33 5084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
Jasper_lee 0:b16d94660a33 5085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
Jasper_lee 0:b16d94660a33 5086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
Jasper_lee 0:b16d94660a33 5087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
Jasper_lee 0:b16d94660a33 5088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
Jasper_lee 0:b16d94660a33 5089 #define ENET_ATCR_REG(base) ((base)->ATCR)
Jasper_lee 0:b16d94660a33 5090 #define ENET_ATVR_REG(base) ((base)->ATVR)
Jasper_lee 0:b16d94660a33 5091 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
Jasper_lee 0:b16d94660a33 5092 #define ENET_ATPER_REG(base) ((base)->ATPER)
Jasper_lee 0:b16d94660a33 5093 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
Jasper_lee 0:b16d94660a33 5094 #define ENET_ATINC_REG(base) ((base)->ATINC)
Jasper_lee 0:b16d94660a33 5095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
Jasper_lee 0:b16d94660a33 5096 #define ENET_TGSR_REG(base) ((base)->TGSR)
Jasper_lee 0:b16d94660a33 5097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
Jasper_lee 0:b16d94660a33 5098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
Jasper_lee 0:b16d94660a33 5099
Jasper_lee 0:b16d94660a33 5100 /*!
Jasper_lee 0:b16d94660a33 5101 * @}
Jasper_lee 0:b16d94660a33 5102 */ /* end of group ENET_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 5103
Jasper_lee 0:b16d94660a33 5104
Jasper_lee 0:b16d94660a33 5105 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5106 -- ENET Register Masks
Jasper_lee 0:b16d94660a33 5107 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5108
Jasper_lee 0:b16d94660a33 5109 /*!
Jasper_lee 0:b16d94660a33 5110 * @addtogroup ENET_Register_Masks ENET Register Masks
Jasper_lee 0:b16d94660a33 5111 * @{
Jasper_lee 0:b16d94660a33 5112 */
Jasper_lee 0:b16d94660a33 5113
Jasper_lee 0:b16d94660a33 5114 /* EIR Bit Fields */
Jasper_lee 0:b16d94660a33 5115 #define ENET_EIR_TS_TIMER_MASK 0x8000u
Jasper_lee 0:b16d94660a33 5116 #define ENET_EIR_TS_TIMER_SHIFT 15
Jasper_lee 0:b16d94660a33 5117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
Jasper_lee 0:b16d94660a33 5118 #define ENET_EIR_TS_AVAIL_SHIFT 16
Jasper_lee 0:b16d94660a33 5119 #define ENET_EIR_WAKEUP_MASK 0x20000u
Jasper_lee 0:b16d94660a33 5120 #define ENET_EIR_WAKEUP_SHIFT 17
Jasper_lee 0:b16d94660a33 5121 #define ENET_EIR_PLR_MASK 0x40000u
Jasper_lee 0:b16d94660a33 5122 #define ENET_EIR_PLR_SHIFT 18
Jasper_lee 0:b16d94660a33 5123 #define ENET_EIR_UN_MASK 0x80000u
Jasper_lee 0:b16d94660a33 5124 #define ENET_EIR_UN_SHIFT 19
Jasper_lee 0:b16d94660a33 5125 #define ENET_EIR_RL_MASK 0x100000u
Jasper_lee 0:b16d94660a33 5126 #define ENET_EIR_RL_SHIFT 20
Jasper_lee 0:b16d94660a33 5127 #define ENET_EIR_LC_MASK 0x200000u
Jasper_lee 0:b16d94660a33 5128 #define ENET_EIR_LC_SHIFT 21
Jasper_lee 0:b16d94660a33 5129 #define ENET_EIR_EBERR_MASK 0x400000u
Jasper_lee 0:b16d94660a33 5130 #define ENET_EIR_EBERR_SHIFT 22
Jasper_lee 0:b16d94660a33 5131 #define ENET_EIR_MII_MASK 0x800000u
Jasper_lee 0:b16d94660a33 5132 #define ENET_EIR_MII_SHIFT 23
Jasper_lee 0:b16d94660a33 5133 #define ENET_EIR_RXB_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 5134 #define ENET_EIR_RXB_SHIFT 24
Jasper_lee 0:b16d94660a33 5135 #define ENET_EIR_RXF_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 5136 #define ENET_EIR_RXF_SHIFT 25
Jasper_lee 0:b16d94660a33 5137 #define ENET_EIR_TXB_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 5138 #define ENET_EIR_TXB_SHIFT 26
Jasper_lee 0:b16d94660a33 5139 #define ENET_EIR_TXF_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 5140 #define ENET_EIR_TXF_SHIFT 27
Jasper_lee 0:b16d94660a33 5141 #define ENET_EIR_GRA_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 5142 #define ENET_EIR_GRA_SHIFT 28
Jasper_lee 0:b16d94660a33 5143 #define ENET_EIR_BABT_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 5144 #define ENET_EIR_BABT_SHIFT 29
Jasper_lee 0:b16d94660a33 5145 #define ENET_EIR_BABR_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 5146 #define ENET_EIR_BABR_SHIFT 30
Jasper_lee 0:b16d94660a33 5147 /* EIMR Bit Fields */
Jasper_lee 0:b16d94660a33 5148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
Jasper_lee 0:b16d94660a33 5149 #define ENET_EIMR_TS_TIMER_SHIFT 15
Jasper_lee 0:b16d94660a33 5150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
Jasper_lee 0:b16d94660a33 5151 #define ENET_EIMR_TS_AVAIL_SHIFT 16
Jasper_lee 0:b16d94660a33 5152 #define ENET_EIMR_WAKEUP_MASK 0x20000u
Jasper_lee 0:b16d94660a33 5153 #define ENET_EIMR_WAKEUP_SHIFT 17
Jasper_lee 0:b16d94660a33 5154 #define ENET_EIMR_PLR_MASK 0x40000u
Jasper_lee 0:b16d94660a33 5155 #define ENET_EIMR_PLR_SHIFT 18
Jasper_lee 0:b16d94660a33 5156 #define ENET_EIMR_UN_MASK 0x80000u
Jasper_lee 0:b16d94660a33 5157 #define ENET_EIMR_UN_SHIFT 19
Jasper_lee 0:b16d94660a33 5158 #define ENET_EIMR_RL_MASK 0x100000u
Jasper_lee 0:b16d94660a33 5159 #define ENET_EIMR_RL_SHIFT 20
Jasper_lee 0:b16d94660a33 5160 #define ENET_EIMR_LC_MASK 0x200000u
Jasper_lee 0:b16d94660a33 5161 #define ENET_EIMR_LC_SHIFT 21
Jasper_lee 0:b16d94660a33 5162 #define ENET_EIMR_EBERR_MASK 0x400000u
Jasper_lee 0:b16d94660a33 5163 #define ENET_EIMR_EBERR_SHIFT 22
Jasper_lee 0:b16d94660a33 5164 #define ENET_EIMR_MII_MASK 0x800000u
Jasper_lee 0:b16d94660a33 5165 #define ENET_EIMR_MII_SHIFT 23
Jasper_lee 0:b16d94660a33 5166 #define ENET_EIMR_RXB_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 5167 #define ENET_EIMR_RXB_SHIFT 24
Jasper_lee 0:b16d94660a33 5168 #define ENET_EIMR_RXF_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 5169 #define ENET_EIMR_RXF_SHIFT 25
Jasper_lee 0:b16d94660a33 5170 #define ENET_EIMR_TXB_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 5171 #define ENET_EIMR_TXB_SHIFT 26
Jasper_lee 0:b16d94660a33 5172 #define ENET_EIMR_TXF_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 5173 #define ENET_EIMR_TXF_SHIFT 27
Jasper_lee 0:b16d94660a33 5174 #define ENET_EIMR_GRA_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 5175 #define ENET_EIMR_GRA_SHIFT 28
Jasper_lee 0:b16d94660a33 5176 #define ENET_EIMR_BABT_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 5177 #define ENET_EIMR_BABT_SHIFT 29
Jasper_lee 0:b16d94660a33 5178 #define ENET_EIMR_BABR_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 5179 #define ENET_EIMR_BABR_SHIFT 30
Jasper_lee 0:b16d94660a33 5180 /* RDAR Bit Fields */
Jasper_lee 0:b16d94660a33 5181 #define ENET_RDAR_RDAR_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 5182 #define ENET_RDAR_RDAR_SHIFT 24
Jasper_lee 0:b16d94660a33 5183 /* TDAR Bit Fields */
Jasper_lee 0:b16d94660a33 5184 #define ENET_TDAR_TDAR_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 5185 #define ENET_TDAR_TDAR_SHIFT 24
Jasper_lee 0:b16d94660a33 5186 /* ECR Bit Fields */
Jasper_lee 0:b16d94660a33 5187 #define ENET_ECR_RESET_MASK 0x1u
Jasper_lee 0:b16d94660a33 5188 #define ENET_ECR_RESET_SHIFT 0
Jasper_lee 0:b16d94660a33 5189 #define ENET_ECR_ETHEREN_MASK 0x2u
Jasper_lee 0:b16d94660a33 5190 #define ENET_ECR_ETHEREN_SHIFT 1
Jasper_lee 0:b16d94660a33 5191 #define ENET_ECR_MAGICEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 5192 #define ENET_ECR_MAGICEN_SHIFT 2
Jasper_lee 0:b16d94660a33 5193 #define ENET_ECR_SLEEP_MASK 0x8u
Jasper_lee 0:b16d94660a33 5194 #define ENET_ECR_SLEEP_SHIFT 3
Jasper_lee 0:b16d94660a33 5195 #define ENET_ECR_EN1588_MASK 0x10u
Jasper_lee 0:b16d94660a33 5196 #define ENET_ECR_EN1588_SHIFT 4
Jasper_lee 0:b16d94660a33 5197 #define ENET_ECR_DBGEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 5198 #define ENET_ECR_DBGEN_SHIFT 6
Jasper_lee 0:b16d94660a33 5199 #define ENET_ECR_STOPEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 5200 #define ENET_ECR_STOPEN_SHIFT 7
Jasper_lee 0:b16d94660a33 5201 #define ENET_ECR_DBSWP_MASK 0x100u
Jasper_lee 0:b16d94660a33 5202 #define ENET_ECR_DBSWP_SHIFT 8
Jasper_lee 0:b16d94660a33 5203 /* MMFR Bit Fields */
Jasper_lee 0:b16d94660a33 5204 #define ENET_MMFR_DATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5205 #define ENET_MMFR_DATA_SHIFT 0
Jasper_lee 0:b16d94660a33 5206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
Jasper_lee 0:b16d94660a33 5207 #define ENET_MMFR_TA_MASK 0x30000u
Jasper_lee 0:b16d94660a33 5208 #define ENET_MMFR_TA_SHIFT 16
Jasper_lee 0:b16d94660a33 5209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
Jasper_lee 0:b16d94660a33 5210 #define ENET_MMFR_RA_MASK 0x7C0000u
Jasper_lee 0:b16d94660a33 5211 #define ENET_MMFR_RA_SHIFT 18
Jasper_lee 0:b16d94660a33 5212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
Jasper_lee 0:b16d94660a33 5213 #define ENET_MMFR_PA_MASK 0xF800000u
Jasper_lee 0:b16d94660a33 5214 #define ENET_MMFR_PA_SHIFT 23
Jasper_lee 0:b16d94660a33 5215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
Jasper_lee 0:b16d94660a33 5216 #define ENET_MMFR_OP_MASK 0x30000000u
Jasper_lee 0:b16d94660a33 5217 #define ENET_MMFR_OP_SHIFT 28
Jasper_lee 0:b16d94660a33 5218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
Jasper_lee 0:b16d94660a33 5219 #define ENET_MMFR_ST_MASK 0xC0000000u
Jasper_lee 0:b16d94660a33 5220 #define ENET_MMFR_ST_SHIFT 30
Jasper_lee 0:b16d94660a33 5221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
Jasper_lee 0:b16d94660a33 5222 /* MSCR Bit Fields */
Jasper_lee 0:b16d94660a33 5223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
Jasper_lee 0:b16d94660a33 5224 #define ENET_MSCR_MII_SPEED_SHIFT 1
Jasper_lee 0:b16d94660a33 5225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
Jasper_lee 0:b16d94660a33 5226 #define ENET_MSCR_DIS_PRE_MASK 0x80u
Jasper_lee 0:b16d94660a33 5227 #define ENET_MSCR_DIS_PRE_SHIFT 7
Jasper_lee 0:b16d94660a33 5228 #define ENET_MSCR_HOLDTIME_MASK 0x700u
Jasper_lee 0:b16d94660a33 5229 #define ENET_MSCR_HOLDTIME_SHIFT 8
Jasper_lee 0:b16d94660a33 5230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
Jasper_lee 0:b16d94660a33 5231 /* MIBC Bit Fields */
Jasper_lee 0:b16d94660a33 5232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 5233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
Jasper_lee 0:b16d94660a33 5234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 5235 #define ENET_MIBC_MIB_IDLE_SHIFT 30
Jasper_lee 0:b16d94660a33 5236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 5237 #define ENET_MIBC_MIB_DIS_SHIFT 31
Jasper_lee 0:b16d94660a33 5238 /* RCR Bit Fields */
Jasper_lee 0:b16d94660a33 5239 #define ENET_RCR_LOOP_MASK 0x1u
Jasper_lee 0:b16d94660a33 5240 #define ENET_RCR_LOOP_SHIFT 0
Jasper_lee 0:b16d94660a33 5241 #define ENET_RCR_DRT_MASK 0x2u
Jasper_lee 0:b16d94660a33 5242 #define ENET_RCR_DRT_SHIFT 1
Jasper_lee 0:b16d94660a33 5243 #define ENET_RCR_MII_MODE_MASK 0x4u
Jasper_lee 0:b16d94660a33 5244 #define ENET_RCR_MII_MODE_SHIFT 2
Jasper_lee 0:b16d94660a33 5245 #define ENET_RCR_PROM_MASK 0x8u
Jasper_lee 0:b16d94660a33 5246 #define ENET_RCR_PROM_SHIFT 3
Jasper_lee 0:b16d94660a33 5247 #define ENET_RCR_BC_REJ_MASK 0x10u
Jasper_lee 0:b16d94660a33 5248 #define ENET_RCR_BC_REJ_SHIFT 4
Jasper_lee 0:b16d94660a33 5249 #define ENET_RCR_FCE_MASK 0x20u
Jasper_lee 0:b16d94660a33 5250 #define ENET_RCR_FCE_SHIFT 5
Jasper_lee 0:b16d94660a33 5251 #define ENET_RCR_RMII_MODE_MASK 0x100u
Jasper_lee 0:b16d94660a33 5252 #define ENET_RCR_RMII_MODE_SHIFT 8
Jasper_lee 0:b16d94660a33 5253 #define ENET_RCR_RMII_10T_MASK 0x200u
Jasper_lee 0:b16d94660a33 5254 #define ENET_RCR_RMII_10T_SHIFT 9
Jasper_lee 0:b16d94660a33 5255 #define ENET_RCR_PADEN_MASK 0x1000u
Jasper_lee 0:b16d94660a33 5256 #define ENET_RCR_PADEN_SHIFT 12
Jasper_lee 0:b16d94660a33 5257 #define ENET_RCR_PAUFWD_MASK 0x2000u
Jasper_lee 0:b16d94660a33 5258 #define ENET_RCR_PAUFWD_SHIFT 13
Jasper_lee 0:b16d94660a33 5259 #define ENET_RCR_CRCFWD_MASK 0x4000u
Jasper_lee 0:b16d94660a33 5260 #define ENET_RCR_CRCFWD_SHIFT 14
Jasper_lee 0:b16d94660a33 5261 #define ENET_RCR_CFEN_MASK 0x8000u
Jasper_lee 0:b16d94660a33 5262 #define ENET_RCR_CFEN_SHIFT 15
Jasper_lee 0:b16d94660a33 5263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
Jasper_lee 0:b16d94660a33 5264 #define ENET_RCR_MAX_FL_SHIFT 16
Jasper_lee 0:b16d94660a33 5265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
Jasper_lee 0:b16d94660a33 5266 #define ENET_RCR_NLC_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 5267 #define ENET_RCR_NLC_SHIFT 30
Jasper_lee 0:b16d94660a33 5268 #define ENET_RCR_GRS_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 5269 #define ENET_RCR_GRS_SHIFT 31
Jasper_lee 0:b16d94660a33 5270 /* TCR Bit Fields */
Jasper_lee 0:b16d94660a33 5271 #define ENET_TCR_GTS_MASK 0x1u
Jasper_lee 0:b16d94660a33 5272 #define ENET_TCR_GTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5273 #define ENET_TCR_FDEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 5274 #define ENET_TCR_FDEN_SHIFT 2
Jasper_lee 0:b16d94660a33 5275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
Jasper_lee 0:b16d94660a33 5276 #define ENET_TCR_TFC_PAUSE_SHIFT 3
Jasper_lee 0:b16d94660a33 5277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
Jasper_lee 0:b16d94660a33 5278 #define ENET_TCR_RFC_PAUSE_SHIFT 4
Jasper_lee 0:b16d94660a33 5279 #define ENET_TCR_ADDSEL_MASK 0xE0u
Jasper_lee 0:b16d94660a33 5280 #define ENET_TCR_ADDSEL_SHIFT 5
Jasper_lee 0:b16d94660a33 5281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
Jasper_lee 0:b16d94660a33 5282 #define ENET_TCR_ADDINS_MASK 0x100u
Jasper_lee 0:b16d94660a33 5283 #define ENET_TCR_ADDINS_SHIFT 8
Jasper_lee 0:b16d94660a33 5284 #define ENET_TCR_CRCFWD_MASK 0x200u
Jasper_lee 0:b16d94660a33 5285 #define ENET_TCR_CRCFWD_SHIFT 9
Jasper_lee 0:b16d94660a33 5286 /* PALR Bit Fields */
Jasper_lee 0:b16d94660a33 5287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5288 #define ENET_PALR_PADDR1_SHIFT 0
Jasper_lee 0:b16d94660a33 5289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
Jasper_lee 0:b16d94660a33 5290 /* PAUR Bit Fields */
Jasper_lee 0:b16d94660a33 5291 #define ENET_PAUR_TYPE_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5292 #define ENET_PAUR_TYPE_SHIFT 0
Jasper_lee 0:b16d94660a33 5293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
Jasper_lee 0:b16d94660a33 5294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 5295 #define ENET_PAUR_PADDR2_SHIFT 16
Jasper_lee 0:b16d94660a33 5296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
Jasper_lee 0:b16d94660a33 5297 /* OPD Bit Fields */
Jasper_lee 0:b16d94660a33 5298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5299 #define ENET_OPD_PAUSE_DUR_SHIFT 0
Jasper_lee 0:b16d94660a33 5300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
Jasper_lee 0:b16d94660a33 5301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 5302 #define ENET_OPD_OPCODE_SHIFT 16
Jasper_lee 0:b16d94660a33 5303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
Jasper_lee 0:b16d94660a33 5304 /* IAUR Bit Fields */
Jasper_lee 0:b16d94660a33 5305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5306 #define ENET_IAUR_IADDR1_SHIFT 0
Jasper_lee 0:b16d94660a33 5307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
Jasper_lee 0:b16d94660a33 5308 /* IALR Bit Fields */
Jasper_lee 0:b16d94660a33 5309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5310 #define ENET_IALR_IADDR2_SHIFT 0
Jasper_lee 0:b16d94660a33 5311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
Jasper_lee 0:b16d94660a33 5312 /* GAUR Bit Fields */
Jasper_lee 0:b16d94660a33 5313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5314 #define ENET_GAUR_GADDR1_SHIFT 0
Jasper_lee 0:b16d94660a33 5315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
Jasper_lee 0:b16d94660a33 5316 /* GALR Bit Fields */
Jasper_lee 0:b16d94660a33 5317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5318 #define ENET_GALR_GADDR2_SHIFT 0
Jasper_lee 0:b16d94660a33 5319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
Jasper_lee 0:b16d94660a33 5320 /* TFWR Bit Fields */
Jasper_lee 0:b16d94660a33 5321 #define ENET_TFWR_TFWR_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 5322 #define ENET_TFWR_TFWR_SHIFT 0
Jasper_lee 0:b16d94660a33 5323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
Jasper_lee 0:b16d94660a33 5324 #define ENET_TFWR_STRFWD_MASK 0x100u
Jasper_lee 0:b16d94660a33 5325 #define ENET_TFWR_STRFWD_SHIFT 8
Jasper_lee 0:b16d94660a33 5326 /* RDSR Bit Fields */
Jasper_lee 0:b16d94660a33 5327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
Jasper_lee 0:b16d94660a33 5328 #define ENET_RDSR_R_DES_START_SHIFT 3
Jasper_lee 0:b16d94660a33 5329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
Jasper_lee 0:b16d94660a33 5330 /* TDSR Bit Fields */
Jasper_lee 0:b16d94660a33 5331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
Jasper_lee 0:b16d94660a33 5332 #define ENET_TDSR_X_DES_START_SHIFT 3
Jasper_lee 0:b16d94660a33 5333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
Jasper_lee 0:b16d94660a33 5334 /* MRBR Bit Fields */
Jasper_lee 0:b16d94660a33 5335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
Jasper_lee 0:b16d94660a33 5336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
Jasper_lee 0:b16d94660a33 5337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
Jasper_lee 0:b16d94660a33 5338 /* RSFL Bit Fields */
Jasper_lee 0:b16d94660a33 5339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
Jasper_lee 0:b16d94660a33 5341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
Jasper_lee 0:b16d94660a33 5342 /* RSEM Bit Fields */
Jasper_lee 0:b16d94660a33 5343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
Jasper_lee 0:b16d94660a33 5345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
Jasper_lee 0:b16d94660a33 5346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
Jasper_lee 0:b16d94660a33 5347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
Jasper_lee 0:b16d94660a33 5348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
Jasper_lee 0:b16d94660a33 5349 /* RAEM Bit Fields */
Jasper_lee 0:b16d94660a33 5350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
Jasper_lee 0:b16d94660a33 5352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
Jasper_lee 0:b16d94660a33 5353 /* RAFL Bit Fields */
Jasper_lee 0:b16d94660a33 5354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
Jasper_lee 0:b16d94660a33 5356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
Jasper_lee 0:b16d94660a33 5357 /* TSEM Bit Fields */
Jasper_lee 0:b16d94660a33 5358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
Jasper_lee 0:b16d94660a33 5360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
Jasper_lee 0:b16d94660a33 5361 /* TAEM Bit Fields */
Jasper_lee 0:b16d94660a33 5362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
Jasper_lee 0:b16d94660a33 5364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
Jasper_lee 0:b16d94660a33 5365 /* TAFL Bit Fields */
Jasper_lee 0:b16d94660a33 5366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
Jasper_lee 0:b16d94660a33 5368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
Jasper_lee 0:b16d94660a33 5369 /* TIPG Bit Fields */
Jasper_lee 0:b16d94660a33 5370 #define ENET_TIPG_IPG_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 5371 #define ENET_TIPG_IPG_SHIFT 0
Jasper_lee 0:b16d94660a33 5372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
Jasper_lee 0:b16d94660a33 5373 /* FTRL Bit Fields */
Jasper_lee 0:b16d94660a33 5374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
Jasper_lee 0:b16d94660a33 5375 #define ENET_FTRL_TRUNC_FL_SHIFT 0
Jasper_lee 0:b16d94660a33 5376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
Jasper_lee 0:b16d94660a33 5377 /* TACC Bit Fields */
Jasper_lee 0:b16d94660a33 5378 #define ENET_TACC_SHIFT16_MASK 0x1u
Jasper_lee 0:b16d94660a33 5379 #define ENET_TACC_SHIFT16_SHIFT 0
Jasper_lee 0:b16d94660a33 5380 #define ENET_TACC_IPCHK_MASK 0x8u
Jasper_lee 0:b16d94660a33 5381 #define ENET_TACC_IPCHK_SHIFT 3
Jasper_lee 0:b16d94660a33 5382 #define ENET_TACC_PROCHK_MASK 0x10u
Jasper_lee 0:b16d94660a33 5383 #define ENET_TACC_PROCHK_SHIFT 4
Jasper_lee 0:b16d94660a33 5384 /* RACC Bit Fields */
Jasper_lee 0:b16d94660a33 5385 #define ENET_RACC_PADREM_MASK 0x1u
Jasper_lee 0:b16d94660a33 5386 #define ENET_RACC_PADREM_SHIFT 0
Jasper_lee 0:b16d94660a33 5387 #define ENET_RACC_IPDIS_MASK 0x2u
Jasper_lee 0:b16d94660a33 5388 #define ENET_RACC_IPDIS_SHIFT 1
Jasper_lee 0:b16d94660a33 5389 #define ENET_RACC_PRODIS_MASK 0x4u
Jasper_lee 0:b16d94660a33 5390 #define ENET_RACC_PRODIS_SHIFT 2
Jasper_lee 0:b16d94660a33 5391 #define ENET_RACC_LINEDIS_MASK 0x40u
Jasper_lee 0:b16d94660a33 5392 #define ENET_RACC_LINEDIS_SHIFT 6
Jasper_lee 0:b16d94660a33 5393 #define ENET_RACC_SHIFT16_MASK 0x80u
Jasper_lee 0:b16d94660a33 5394 #define ENET_RACC_SHIFT16_SHIFT 7
Jasper_lee 0:b16d94660a33 5395 /* RMON_T_PACKETS Bit Fields */
Jasper_lee 0:b16d94660a33 5396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5399 /* RMON_T_BC_PKT Bit Fields */
Jasper_lee 0:b16d94660a33 5400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5403 /* RMON_T_MC_PKT Bit Fields */
Jasper_lee 0:b16d94660a33 5404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5407 /* RMON_T_CRC_ALIGN Bit Fields */
Jasper_lee 0:b16d94660a33 5408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5411 /* RMON_T_UNDERSIZE Bit Fields */
Jasper_lee 0:b16d94660a33 5412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5415 /* RMON_T_OVERSIZE Bit Fields */
Jasper_lee 0:b16d94660a33 5416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5419 /* RMON_T_FRAG Bit Fields */
Jasper_lee 0:b16d94660a33 5420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5423 /* RMON_T_JAB Bit Fields */
Jasper_lee 0:b16d94660a33 5424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5427 /* RMON_T_COL Bit Fields */
Jasper_lee 0:b16d94660a33 5428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5431 /* RMON_T_P64 Bit Fields */
Jasper_lee 0:b16d94660a33 5432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5435 /* RMON_T_P65TO127 Bit Fields */
Jasper_lee 0:b16d94660a33 5436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5439 /* RMON_T_P128TO255 Bit Fields */
Jasper_lee 0:b16d94660a33 5440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5443 /* RMON_T_P256TO511 Bit Fields */
Jasper_lee 0:b16d94660a33 5444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5447 /* RMON_T_P512TO1023 Bit Fields */
Jasper_lee 0:b16d94660a33 5448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5451 /* RMON_T_P1024TO2047 Bit Fields */
Jasper_lee 0:b16d94660a33 5452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5455 /* RMON_T_P_GTE2048 Bit Fields */
Jasper_lee 0:b16d94660a33 5456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
Jasper_lee 0:b16d94660a33 5459 /* RMON_T_OCTETS Bit Fields */
Jasper_lee 0:b16d94660a33 5460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
Jasper_lee 0:b16d94660a33 5462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
Jasper_lee 0:b16d94660a33 5463 /* IEEE_T_FRAME_OK Bit Fields */
Jasper_lee 0:b16d94660a33 5464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5467 /* IEEE_T_1COL Bit Fields */
Jasper_lee 0:b16d94660a33 5468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5471 /* IEEE_T_MCOL Bit Fields */
Jasper_lee 0:b16d94660a33 5472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5475 /* IEEE_T_DEF Bit Fields */
Jasper_lee 0:b16d94660a33 5476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5479 /* IEEE_T_LCOL Bit Fields */
Jasper_lee 0:b16d94660a33 5480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5483 /* IEEE_T_EXCOL Bit Fields */
Jasper_lee 0:b16d94660a33 5484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5487 /* IEEE_T_MACERR Bit Fields */
Jasper_lee 0:b16d94660a33 5488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5491 /* IEEE_T_CSERR Bit Fields */
Jasper_lee 0:b16d94660a33 5492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5495 /* IEEE_T_FDXFC Bit Fields */
Jasper_lee 0:b16d94660a33 5496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5499 /* IEEE_T_OCTETS_OK Bit Fields */
Jasper_lee 0:b16d94660a33 5500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5503 /* RMON_R_PACKETS Bit Fields */
Jasper_lee 0:b16d94660a33 5504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5507 /* RMON_R_BC_PKT Bit Fields */
Jasper_lee 0:b16d94660a33 5508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5511 /* RMON_R_MC_PKT Bit Fields */
Jasper_lee 0:b16d94660a33 5512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5515 /* RMON_R_CRC_ALIGN Bit Fields */
Jasper_lee 0:b16d94660a33 5516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5519 /* RMON_R_UNDERSIZE Bit Fields */
Jasper_lee 0:b16d94660a33 5520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5523 /* RMON_R_OVERSIZE Bit Fields */
Jasper_lee 0:b16d94660a33 5524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5527 /* RMON_R_FRAG Bit Fields */
Jasper_lee 0:b16d94660a33 5528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5531 /* RMON_R_JAB Bit Fields */
Jasper_lee 0:b16d94660a33 5532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5535 /* RMON_R_P64 Bit Fields */
Jasper_lee 0:b16d94660a33 5536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5537 #define ENET_RMON_R_P64_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5539 /* RMON_R_P65TO127 Bit Fields */
Jasper_lee 0:b16d94660a33 5540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5543 /* RMON_R_P128TO255 Bit Fields */
Jasper_lee 0:b16d94660a33 5544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5547 /* RMON_R_P256TO511 Bit Fields */
Jasper_lee 0:b16d94660a33 5548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5551 /* RMON_R_P512TO1023 Bit Fields */
Jasper_lee 0:b16d94660a33 5552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5555 /* RMON_R_P1024TO2047 Bit Fields */
Jasper_lee 0:b16d94660a33 5556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5559 /* RMON_R_P_GTE2048 Bit Fields */
Jasper_lee 0:b16d94660a33 5560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5563 /* RMON_R_OCTETS Bit Fields */
Jasper_lee 0:b16d94660a33 5564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5567 /* IEEE_R_DROP Bit Fields */
Jasper_lee 0:b16d94660a33 5568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5571 /* IEEE_R_FRAME_OK Bit Fields */
Jasper_lee 0:b16d94660a33 5572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5575 /* IEEE_R_CRC Bit Fields */
Jasper_lee 0:b16d94660a33 5576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5579 /* IEEE_R_ALIGN Bit Fields */
Jasper_lee 0:b16d94660a33 5580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5583 /* IEEE_R_MACERR Bit Fields */
Jasper_lee 0:b16d94660a33 5584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5587 /* IEEE_R_FDXFC Bit Fields */
Jasper_lee 0:b16d94660a33 5588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 5589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5591 /* IEEE_R_OCTETS_OK Bit Fields */
Jasper_lee 0:b16d94660a33 5592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 5594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
Jasper_lee 0:b16d94660a33 5595 /* ATCR Bit Fields */
Jasper_lee 0:b16d94660a33 5596 #define ENET_ATCR_EN_MASK 0x1u
Jasper_lee 0:b16d94660a33 5597 #define ENET_ATCR_EN_SHIFT 0
Jasper_lee 0:b16d94660a33 5598 #define ENET_ATCR_OFFEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 5599 #define ENET_ATCR_OFFEN_SHIFT 2
Jasper_lee 0:b16d94660a33 5600 #define ENET_ATCR_OFFRST_MASK 0x8u
Jasper_lee 0:b16d94660a33 5601 #define ENET_ATCR_OFFRST_SHIFT 3
Jasper_lee 0:b16d94660a33 5602 #define ENET_ATCR_PEREN_MASK 0x10u
Jasper_lee 0:b16d94660a33 5603 #define ENET_ATCR_PEREN_SHIFT 4
Jasper_lee 0:b16d94660a33 5604 #define ENET_ATCR_PINPER_MASK 0x80u
Jasper_lee 0:b16d94660a33 5605 #define ENET_ATCR_PINPER_SHIFT 7
Jasper_lee 0:b16d94660a33 5606 #define ENET_ATCR_RESTART_MASK 0x200u
Jasper_lee 0:b16d94660a33 5607 #define ENET_ATCR_RESTART_SHIFT 9
Jasper_lee 0:b16d94660a33 5608 #define ENET_ATCR_CAPTURE_MASK 0x800u
Jasper_lee 0:b16d94660a33 5609 #define ENET_ATCR_CAPTURE_SHIFT 11
Jasper_lee 0:b16d94660a33 5610 #define ENET_ATCR_SLAVE_MASK 0x2000u
Jasper_lee 0:b16d94660a33 5611 #define ENET_ATCR_SLAVE_SHIFT 13
Jasper_lee 0:b16d94660a33 5612 /* ATVR Bit Fields */
Jasper_lee 0:b16d94660a33 5613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5614 #define ENET_ATVR_ATIME_SHIFT 0
Jasper_lee 0:b16d94660a33 5615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
Jasper_lee 0:b16d94660a33 5616 /* ATOFF Bit Fields */
Jasper_lee 0:b16d94660a33 5617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5618 #define ENET_ATOFF_OFFSET_SHIFT 0
Jasper_lee 0:b16d94660a33 5619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
Jasper_lee 0:b16d94660a33 5620 /* ATPER Bit Fields */
Jasper_lee 0:b16d94660a33 5621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5622 #define ENET_ATPER_PERIOD_SHIFT 0
Jasper_lee 0:b16d94660a33 5623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
Jasper_lee 0:b16d94660a33 5624 /* ATCOR Bit Fields */
Jasper_lee 0:b16d94660a33 5625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
Jasper_lee 0:b16d94660a33 5626 #define ENET_ATCOR_COR_SHIFT 0
Jasper_lee 0:b16d94660a33 5627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
Jasper_lee 0:b16d94660a33 5628 /* ATINC Bit Fields */
Jasper_lee 0:b16d94660a33 5629 #define ENET_ATINC_INC_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 5630 #define ENET_ATINC_INC_SHIFT 0
Jasper_lee 0:b16d94660a33 5631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
Jasper_lee 0:b16d94660a33 5632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
Jasper_lee 0:b16d94660a33 5633 #define ENET_ATINC_INC_CORR_SHIFT 8
Jasper_lee 0:b16d94660a33 5634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
Jasper_lee 0:b16d94660a33 5635 /* ATSTMP Bit Fields */
Jasper_lee 0:b16d94660a33 5636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
Jasper_lee 0:b16d94660a33 5638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
Jasper_lee 0:b16d94660a33 5639 /* TGSR Bit Fields */
Jasper_lee 0:b16d94660a33 5640 #define ENET_TGSR_TF0_MASK 0x1u
Jasper_lee 0:b16d94660a33 5641 #define ENET_TGSR_TF0_SHIFT 0
Jasper_lee 0:b16d94660a33 5642 #define ENET_TGSR_TF1_MASK 0x2u
Jasper_lee 0:b16d94660a33 5643 #define ENET_TGSR_TF1_SHIFT 1
Jasper_lee 0:b16d94660a33 5644 #define ENET_TGSR_TF2_MASK 0x4u
Jasper_lee 0:b16d94660a33 5645 #define ENET_TGSR_TF2_SHIFT 2
Jasper_lee 0:b16d94660a33 5646 #define ENET_TGSR_TF3_MASK 0x8u
Jasper_lee 0:b16d94660a33 5647 #define ENET_TGSR_TF3_SHIFT 3
Jasper_lee 0:b16d94660a33 5648 /* TCSR Bit Fields */
Jasper_lee 0:b16d94660a33 5649 #define ENET_TCSR_TDRE_MASK 0x1u
Jasper_lee 0:b16d94660a33 5650 #define ENET_TCSR_TDRE_SHIFT 0
Jasper_lee 0:b16d94660a33 5651 #define ENET_TCSR_TMODE_MASK 0x3Cu
Jasper_lee 0:b16d94660a33 5652 #define ENET_TCSR_TMODE_SHIFT 2
Jasper_lee 0:b16d94660a33 5653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
Jasper_lee 0:b16d94660a33 5654 #define ENET_TCSR_TIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 5655 #define ENET_TCSR_TIE_SHIFT 6
Jasper_lee 0:b16d94660a33 5656 #define ENET_TCSR_TF_MASK 0x80u
Jasper_lee 0:b16d94660a33 5657 #define ENET_TCSR_TF_SHIFT 7
Jasper_lee 0:b16d94660a33 5658 /* TCCR Bit Fields */
Jasper_lee 0:b16d94660a33 5659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 5660 #define ENET_TCCR_TCC_SHIFT 0
Jasper_lee 0:b16d94660a33 5661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
Jasper_lee 0:b16d94660a33 5662
Jasper_lee 0:b16d94660a33 5663 /*!
Jasper_lee 0:b16d94660a33 5664 * @}
Jasper_lee 0:b16d94660a33 5665 */ /* end of group ENET_Register_Masks */
Jasper_lee 0:b16d94660a33 5666
Jasper_lee 0:b16d94660a33 5667
Jasper_lee 0:b16d94660a33 5668 /* ENET - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 5669 /** Peripheral ENET base address */
Jasper_lee 0:b16d94660a33 5670 #define ENET_BASE (0x400C0000u)
Jasper_lee 0:b16d94660a33 5671 /** Peripheral ENET base pointer */
Jasper_lee 0:b16d94660a33 5672 #define ENET ((ENET_Type *)ENET_BASE)
Jasper_lee 0:b16d94660a33 5673 #define ENET_BASE_PTR (ENET)
Jasper_lee 0:b16d94660a33 5674 /** Array initializer of ENET peripheral base addresses */
Jasper_lee 0:b16d94660a33 5675 #define ENET_BASE_ADDRS { ENET_BASE }
Jasper_lee 0:b16d94660a33 5676 /** Array initializer of ENET peripheral base pointers */
Jasper_lee 0:b16d94660a33 5677 #define ENET_BASE_PTRS { ENET }
Jasper_lee 0:b16d94660a33 5678 /** Interrupt vectors for the ENET peripheral type */
Jasper_lee 0:b16d94660a33 5679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
Jasper_lee 0:b16d94660a33 5680 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
Jasper_lee 0:b16d94660a33 5681 #define ENET_Error_IRQS { ENET_Error_IRQn }
Jasper_lee 0:b16d94660a33 5682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
Jasper_lee 0:b16d94660a33 5683
Jasper_lee 0:b16d94660a33 5684 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5685 -- ENET - Register accessor macros
Jasper_lee 0:b16d94660a33 5686 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5687
Jasper_lee 0:b16d94660a33 5688 /*!
Jasper_lee 0:b16d94660a33 5689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
Jasper_lee 0:b16d94660a33 5690 * @{
Jasper_lee 0:b16d94660a33 5691 */
Jasper_lee 0:b16d94660a33 5692
Jasper_lee 0:b16d94660a33 5693
Jasper_lee 0:b16d94660a33 5694 /* ENET - Register instance definitions */
Jasper_lee 0:b16d94660a33 5695 /* ENET */
Jasper_lee 0:b16d94660a33 5696 #define ENET_EIR ENET_EIR_REG(ENET)
Jasper_lee 0:b16d94660a33 5697 #define ENET_EIMR ENET_EIMR_REG(ENET)
Jasper_lee 0:b16d94660a33 5698 #define ENET_RDAR ENET_RDAR_REG(ENET)
Jasper_lee 0:b16d94660a33 5699 #define ENET_TDAR ENET_TDAR_REG(ENET)
Jasper_lee 0:b16d94660a33 5700 #define ENET_ECR ENET_ECR_REG(ENET)
Jasper_lee 0:b16d94660a33 5701 #define ENET_MMFR ENET_MMFR_REG(ENET)
Jasper_lee 0:b16d94660a33 5702 #define ENET_MSCR ENET_MSCR_REG(ENET)
Jasper_lee 0:b16d94660a33 5703 #define ENET_MIBC ENET_MIBC_REG(ENET)
Jasper_lee 0:b16d94660a33 5704 #define ENET_RCR ENET_RCR_REG(ENET)
Jasper_lee 0:b16d94660a33 5705 #define ENET_TCR ENET_TCR_REG(ENET)
Jasper_lee 0:b16d94660a33 5706 #define ENET_PALR ENET_PALR_REG(ENET)
Jasper_lee 0:b16d94660a33 5707 #define ENET_PAUR ENET_PAUR_REG(ENET)
Jasper_lee 0:b16d94660a33 5708 #define ENET_OPD ENET_OPD_REG(ENET)
Jasper_lee 0:b16d94660a33 5709 #define ENET_IAUR ENET_IAUR_REG(ENET)
Jasper_lee 0:b16d94660a33 5710 #define ENET_IALR ENET_IALR_REG(ENET)
Jasper_lee 0:b16d94660a33 5711 #define ENET_GAUR ENET_GAUR_REG(ENET)
Jasper_lee 0:b16d94660a33 5712 #define ENET_GALR ENET_GALR_REG(ENET)
Jasper_lee 0:b16d94660a33 5713 #define ENET_TFWR ENET_TFWR_REG(ENET)
Jasper_lee 0:b16d94660a33 5714 #define ENET_RDSR ENET_RDSR_REG(ENET)
Jasper_lee 0:b16d94660a33 5715 #define ENET_TDSR ENET_TDSR_REG(ENET)
Jasper_lee 0:b16d94660a33 5716 #define ENET_MRBR ENET_MRBR_REG(ENET)
Jasper_lee 0:b16d94660a33 5717 #define ENET_RSFL ENET_RSFL_REG(ENET)
Jasper_lee 0:b16d94660a33 5718 #define ENET_RSEM ENET_RSEM_REG(ENET)
Jasper_lee 0:b16d94660a33 5719 #define ENET_RAEM ENET_RAEM_REG(ENET)
Jasper_lee 0:b16d94660a33 5720 #define ENET_RAFL ENET_RAFL_REG(ENET)
Jasper_lee 0:b16d94660a33 5721 #define ENET_TSEM ENET_TSEM_REG(ENET)
Jasper_lee 0:b16d94660a33 5722 #define ENET_TAEM ENET_TAEM_REG(ENET)
Jasper_lee 0:b16d94660a33 5723 #define ENET_TAFL ENET_TAFL_REG(ENET)
Jasper_lee 0:b16d94660a33 5724 #define ENET_TIPG ENET_TIPG_REG(ENET)
Jasper_lee 0:b16d94660a33 5725 #define ENET_FTRL ENET_FTRL_REG(ENET)
Jasper_lee 0:b16d94660a33 5726 #define ENET_TACC ENET_TACC_REG(ENET)
Jasper_lee 0:b16d94660a33 5727 #define ENET_RACC ENET_RACC_REG(ENET)
Jasper_lee 0:b16d94660a33 5728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
Jasper_lee 0:b16d94660a33 5729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
Jasper_lee 0:b16d94660a33 5730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
Jasper_lee 0:b16d94660a33 5731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
Jasper_lee 0:b16d94660a33 5732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
Jasper_lee 0:b16d94660a33 5733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
Jasper_lee 0:b16d94660a33 5734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
Jasper_lee 0:b16d94660a33 5735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
Jasper_lee 0:b16d94660a33 5736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
Jasper_lee 0:b16d94660a33 5737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
Jasper_lee 0:b16d94660a33 5738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
Jasper_lee 0:b16d94660a33 5739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
Jasper_lee 0:b16d94660a33 5740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
Jasper_lee 0:b16d94660a33 5741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
Jasper_lee 0:b16d94660a33 5742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
Jasper_lee 0:b16d94660a33 5743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
Jasper_lee 0:b16d94660a33 5744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
Jasper_lee 0:b16d94660a33 5745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
Jasper_lee 0:b16d94660a33 5746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
Jasper_lee 0:b16d94660a33 5747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
Jasper_lee 0:b16d94660a33 5748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
Jasper_lee 0:b16d94660a33 5749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
Jasper_lee 0:b16d94660a33 5750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
Jasper_lee 0:b16d94660a33 5751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
Jasper_lee 0:b16d94660a33 5752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
Jasper_lee 0:b16d94660a33 5753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
Jasper_lee 0:b16d94660a33 5754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
Jasper_lee 0:b16d94660a33 5755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
Jasper_lee 0:b16d94660a33 5756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
Jasper_lee 0:b16d94660a33 5757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
Jasper_lee 0:b16d94660a33 5758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
Jasper_lee 0:b16d94660a33 5759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
Jasper_lee 0:b16d94660a33 5760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
Jasper_lee 0:b16d94660a33 5761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
Jasper_lee 0:b16d94660a33 5762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
Jasper_lee 0:b16d94660a33 5763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
Jasper_lee 0:b16d94660a33 5764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
Jasper_lee 0:b16d94660a33 5765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
Jasper_lee 0:b16d94660a33 5766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
Jasper_lee 0:b16d94660a33 5767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
Jasper_lee 0:b16d94660a33 5768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
Jasper_lee 0:b16d94660a33 5769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
Jasper_lee 0:b16d94660a33 5770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
Jasper_lee 0:b16d94660a33 5771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
Jasper_lee 0:b16d94660a33 5772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
Jasper_lee 0:b16d94660a33 5773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
Jasper_lee 0:b16d94660a33 5774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
Jasper_lee 0:b16d94660a33 5775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
Jasper_lee 0:b16d94660a33 5776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
Jasper_lee 0:b16d94660a33 5777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
Jasper_lee 0:b16d94660a33 5778 #define ENET_ATCR ENET_ATCR_REG(ENET)
Jasper_lee 0:b16d94660a33 5779 #define ENET_ATVR ENET_ATVR_REG(ENET)
Jasper_lee 0:b16d94660a33 5780 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
Jasper_lee 0:b16d94660a33 5781 #define ENET_ATPER ENET_ATPER_REG(ENET)
Jasper_lee 0:b16d94660a33 5782 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
Jasper_lee 0:b16d94660a33 5783 #define ENET_ATINC ENET_ATINC_REG(ENET)
Jasper_lee 0:b16d94660a33 5784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
Jasper_lee 0:b16d94660a33 5785 #define ENET_TGSR ENET_TGSR_REG(ENET)
Jasper_lee 0:b16d94660a33 5786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
Jasper_lee 0:b16d94660a33 5787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
Jasper_lee 0:b16d94660a33 5788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
Jasper_lee 0:b16d94660a33 5789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
Jasper_lee 0:b16d94660a33 5790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
Jasper_lee 0:b16d94660a33 5791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
Jasper_lee 0:b16d94660a33 5792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
Jasper_lee 0:b16d94660a33 5793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
Jasper_lee 0:b16d94660a33 5794
Jasper_lee 0:b16d94660a33 5795 /* ENET - Register array accessors */
Jasper_lee 0:b16d94660a33 5796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
Jasper_lee 0:b16d94660a33 5797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
Jasper_lee 0:b16d94660a33 5798
Jasper_lee 0:b16d94660a33 5799 /*!
Jasper_lee 0:b16d94660a33 5800 * @}
Jasper_lee 0:b16d94660a33 5801 */ /* end of group ENET_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 5802
Jasper_lee 0:b16d94660a33 5803
Jasper_lee 0:b16d94660a33 5804 /*!
Jasper_lee 0:b16d94660a33 5805 * @}
Jasper_lee 0:b16d94660a33 5806 */ /* end of group ENET_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 5807
Jasper_lee 0:b16d94660a33 5808
Jasper_lee 0:b16d94660a33 5809 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5810 -- EWM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 5811 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5812
Jasper_lee 0:b16d94660a33 5813 /*!
Jasper_lee 0:b16d94660a33 5814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 5815 * @{
Jasper_lee 0:b16d94660a33 5816 */
Jasper_lee 0:b16d94660a33 5817
Jasper_lee 0:b16d94660a33 5818 /** EWM - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 5819 typedef struct {
Jasper_lee 0:b16d94660a33 5820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 5821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 5822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 5823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 5824 } EWM_Type, *EWM_MemMapPtr;
Jasper_lee 0:b16d94660a33 5825
Jasper_lee 0:b16d94660a33 5826 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5827 -- EWM - Register accessor macros
Jasper_lee 0:b16d94660a33 5828 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5829
Jasper_lee 0:b16d94660a33 5830 /*!
Jasper_lee 0:b16d94660a33 5831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
Jasper_lee 0:b16d94660a33 5832 * @{
Jasper_lee 0:b16d94660a33 5833 */
Jasper_lee 0:b16d94660a33 5834
Jasper_lee 0:b16d94660a33 5835
Jasper_lee 0:b16d94660a33 5836 /* EWM - Register accessors */
Jasper_lee 0:b16d94660a33 5837 #define EWM_CTRL_REG(base) ((base)->CTRL)
Jasper_lee 0:b16d94660a33 5838 #define EWM_SERV_REG(base) ((base)->SERV)
Jasper_lee 0:b16d94660a33 5839 #define EWM_CMPL_REG(base) ((base)->CMPL)
Jasper_lee 0:b16d94660a33 5840 #define EWM_CMPH_REG(base) ((base)->CMPH)
Jasper_lee 0:b16d94660a33 5841
Jasper_lee 0:b16d94660a33 5842 /*!
Jasper_lee 0:b16d94660a33 5843 * @}
Jasper_lee 0:b16d94660a33 5844 */ /* end of group EWM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 5845
Jasper_lee 0:b16d94660a33 5846
Jasper_lee 0:b16d94660a33 5847 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5848 -- EWM Register Masks
Jasper_lee 0:b16d94660a33 5849 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5850
Jasper_lee 0:b16d94660a33 5851 /*!
Jasper_lee 0:b16d94660a33 5852 * @addtogroup EWM_Register_Masks EWM Register Masks
Jasper_lee 0:b16d94660a33 5853 * @{
Jasper_lee 0:b16d94660a33 5854 */
Jasper_lee 0:b16d94660a33 5855
Jasper_lee 0:b16d94660a33 5856 /* CTRL Bit Fields */
Jasper_lee 0:b16d94660a33 5857 #define EWM_CTRL_EWMEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 5858 #define EWM_CTRL_EWMEN_SHIFT 0
Jasper_lee 0:b16d94660a33 5859 #define EWM_CTRL_ASSIN_MASK 0x2u
Jasper_lee 0:b16d94660a33 5860 #define EWM_CTRL_ASSIN_SHIFT 1
Jasper_lee 0:b16d94660a33 5861 #define EWM_CTRL_INEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 5862 #define EWM_CTRL_INEN_SHIFT 2
Jasper_lee 0:b16d94660a33 5863 #define EWM_CTRL_INTEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 5864 #define EWM_CTRL_INTEN_SHIFT 3
Jasper_lee 0:b16d94660a33 5865 /* SERV Bit Fields */
Jasper_lee 0:b16d94660a33 5866 #define EWM_SERV_SERVICE_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5867 #define EWM_SERV_SERVICE_SHIFT 0
Jasper_lee 0:b16d94660a33 5868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
Jasper_lee 0:b16d94660a33 5869 /* CMPL Bit Fields */
Jasper_lee 0:b16d94660a33 5870 #define EWM_CMPL_COMPAREL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5871 #define EWM_CMPL_COMPAREL_SHIFT 0
Jasper_lee 0:b16d94660a33 5872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
Jasper_lee 0:b16d94660a33 5873 /* CMPH Bit Fields */
Jasper_lee 0:b16d94660a33 5874 #define EWM_CMPH_COMPAREH_MASK 0xFFu
Jasper_lee 0:b16d94660a33 5875 #define EWM_CMPH_COMPAREH_SHIFT 0
Jasper_lee 0:b16d94660a33 5876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
Jasper_lee 0:b16d94660a33 5877
Jasper_lee 0:b16d94660a33 5878 /*!
Jasper_lee 0:b16d94660a33 5879 * @}
Jasper_lee 0:b16d94660a33 5880 */ /* end of group EWM_Register_Masks */
Jasper_lee 0:b16d94660a33 5881
Jasper_lee 0:b16d94660a33 5882
Jasper_lee 0:b16d94660a33 5883 /* EWM - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 5884 /** Peripheral EWM base address */
Jasper_lee 0:b16d94660a33 5885 #define EWM_BASE (0x40061000u)
Jasper_lee 0:b16d94660a33 5886 /** Peripheral EWM base pointer */
Jasper_lee 0:b16d94660a33 5887 #define EWM ((EWM_Type *)EWM_BASE)
Jasper_lee 0:b16d94660a33 5888 #define EWM_BASE_PTR (EWM)
Jasper_lee 0:b16d94660a33 5889 /** Array initializer of EWM peripheral base addresses */
Jasper_lee 0:b16d94660a33 5890 #define EWM_BASE_ADDRS { EWM_BASE }
Jasper_lee 0:b16d94660a33 5891 /** Array initializer of EWM peripheral base pointers */
Jasper_lee 0:b16d94660a33 5892 #define EWM_BASE_PTRS { EWM }
Jasper_lee 0:b16d94660a33 5893 /** Interrupt vectors for the EWM peripheral type */
Jasper_lee 0:b16d94660a33 5894 #define EWM_IRQS { Watchdog_IRQn }
Jasper_lee 0:b16d94660a33 5895
Jasper_lee 0:b16d94660a33 5896 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5897 -- EWM - Register accessor macros
Jasper_lee 0:b16d94660a33 5898 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5899
Jasper_lee 0:b16d94660a33 5900 /*!
Jasper_lee 0:b16d94660a33 5901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
Jasper_lee 0:b16d94660a33 5902 * @{
Jasper_lee 0:b16d94660a33 5903 */
Jasper_lee 0:b16d94660a33 5904
Jasper_lee 0:b16d94660a33 5905
Jasper_lee 0:b16d94660a33 5906 /* EWM - Register instance definitions */
Jasper_lee 0:b16d94660a33 5907 /* EWM */
Jasper_lee 0:b16d94660a33 5908 #define EWM_CTRL EWM_CTRL_REG(EWM)
Jasper_lee 0:b16d94660a33 5909 #define EWM_SERV EWM_SERV_REG(EWM)
Jasper_lee 0:b16d94660a33 5910 #define EWM_CMPL EWM_CMPL_REG(EWM)
Jasper_lee 0:b16d94660a33 5911 #define EWM_CMPH EWM_CMPH_REG(EWM)
Jasper_lee 0:b16d94660a33 5912
Jasper_lee 0:b16d94660a33 5913 /*!
Jasper_lee 0:b16d94660a33 5914 * @}
Jasper_lee 0:b16d94660a33 5915 */ /* end of group EWM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 5916
Jasper_lee 0:b16d94660a33 5917
Jasper_lee 0:b16d94660a33 5918 /*!
Jasper_lee 0:b16d94660a33 5919 * @}
Jasper_lee 0:b16d94660a33 5920 */ /* end of group EWM_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 5921
Jasper_lee 0:b16d94660a33 5922
Jasper_lee 0:b16d94660a33 5923 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5924 -- FB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 5925 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5926
Jasper_lee 0:b16d94660a33 5927 /*!
Jasper_lee 0:b16d94660a33 5928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 5929 * @{
Jasper_lee 0:b16d94660a33 5930 */
Jasper_lee 0:b16d94660a33 5931
Jasper_lee 0:b16d94660a33 5932 /** FB - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 5933 typedef struct {
Jasper_lee 0:b16d94660a33 5934 struct { /* offset: 0x0, array step: 0xC */
Jasper_lee 0:b16d94660a33 5935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
Jasper_lee 0:b16d94660a33 5936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
Jasper_lee 0:b16d94660a33 5937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
Jasper_lee 0:b16d94660a33 5938 } CS[6];
Jasper_lee 0:b16d94660a33 5939 uint8_t RESERVED_0[24];
Jasper_lee 0:b16d94660a33 5940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
Jasper_lee 0:b16d94660a33 5941 } FB_Type, *FB_MemMapPtr;
Jasper_lee 0:b16d94660a33 5942
Jasper_lee 0:b16d94660a33 5943 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5944 -- FB - Register accessor macros
Jasper_lee 0:b16d94660a33 5945 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5946
Jasper_lee 0:b16d94660a33 5947 /*!
Jasper_lee 0:b16d94660a33 5948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
Jasper_lee 0:b16d94660a33 5949 * @{
Jasper_lee 0:b16d94660a33 5950 */
Jasper_lee 0:b16d94660a33 5951
Jasper_lee 0:b16d94660a33 5952
Jasper_lee 0:b16d94660a33 5953 /* FB - Register accessors */
Jasper_lee 0:b16d94660a33 5954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
Jasper_lee 0:b16d94660a33 5955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
Jasper_lee 0:b16d94660a33 5956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
Jasper_lee 0:b16d94660a33 5957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
Jasper_lee 0:b16d94660a33 5958
Jasper_lee 0:b16d94660a33 5959 /*!
Jasper_lee 0:b16d94660a33 5960 * @}
Jasper_lee 0:b16d94660a33 5961 */ /* end of group FB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 5962
Jasper_lee 0:b16d94660a33 5963
Jasper_lee 0:b16d94660a33 5964 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 5965 -- FB Register Masks
Jasper_lee 0:b16d94660a33 5966 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 5967
Jasper_lee 0:b16d94660a33 5968 /*!
Jasper_lee 0:b16d94660a33 5969 * @addtogroup FB_Register_Masks FB Register Masks
Jasper_lee 0:b16d94660a33 5970 * @{
Jasper_lee 0:b16d94660a33 5971 */
Jasper_lee 0:b16d94660a33 5972
Jasper_lee 0:b16d94660a33 5973 /* CSAR Bit Fields */
Jasper_lee 0:b16d94660a33 5974 #define FB_CSAR_BA_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 5975 #define FB_CSAR_BA_SHIFT 16
Jasper_lee 0:b16d94660a33 5976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
Jasper_lee 0:b16d94660a33 5977 /* CSMR Bit Fields */
Jasper_lee 0:b16d94660a33 5978 #define FB_CSMR_V_MASK 0x1u
Jasper_lee 0:b16d94660a33 5979 #define FB_CSMR_V_SHIFT 0
Jasper_lee 0:b16d94660a33 5980 #define FB_CSMR_WP_MASK 0x100u
Jasper_lee 0:b16d94660a33 5981 #define FB_CSMR_WP_SHIFT 8
Jasper_lee 0:b16d94660a33 5982 #define FB_CSMR_BAM_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 5983 #define FB_CSMR_BAM_SHIFT 16
Jasper_lee 0:b16d94660a33 5984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
Jasper_lee 0:b16d94660a33 5985 /* CSCR Bit Fields */
Jasper_lee 0:b16d94660a33 5986 #define FB_CSCR_BSTW_MASK 0x8u
Jasper_lee 0:b16d94660a33 5987 #define FB_CSCR_BSTW_SHIFT 3
Jasper_lee 0:b16d94660a33 5988 #define FB_CSCR_BSTR_MASK 0x10u
Jasper_lee 0:b16d94660a33 5989 #define FB_CSCR_BSTR_SHIFT 4
Jasper_lee 0:b16d94660a33 5990 #define FB_CSCR_BEM_MASK 0x20u
Jasper_lee 0:b16d94660a33 5991 #define FB_CSCR_BEM_SHIFT 5
Jasper_lee 0:b16d94660a33 5992 #define FB_CSCR_PS_MASK 0xC0u
Jasper_lee 0:b16d94660a33 5993 #define FB_CSCR_PS_SHIFT 6
Jasper_lee 0:b16d94660a33 5994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
Jasper_lee 0:b16d94660a33 5995 #define FB_CSCR_AA_MASK 0x100u
Jasper_lee 0:b16d94660a33 5996 #define FB_CSCR_AA_SHIFT 8
Jasper_lee 0:b16d94660a33 5997 #define FB_CSCR_BLS_MASK 0x200u
Jasper_lee 0:b16d94660a33 5998 #define FB_CSCR_BLS_SHIFT 9
Jasper_lee 0:b16d94660a33 5999 #define FB_CSCR_WS_MASK 0xFC00u
Jasper_lee 0:b16d94660a33 6000 #define FB_CSCR_WS_SHIFT 10
Jasper_lee 0:b16d94660a33 6001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
Jasper_lee 0:b16d94660a33 6002 #define FB_CSCR_WRAH_MASK 0x30000u
Jasper_lee 0:b16d94660a33 6003 #define FB_CSCR_WRAH_SHIFT 16
Jasper_lee 0:b16d94660a33 6004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
Jasper_lee 0:b16d94660a33 6005 #define FB_CSCR_RDAH_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 6006 #define FB_CSCR_RDAH_SHIFT 18
Jasper_lee 0:b16d94660a33 6007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
Jasper_lee 0:b16d94660a33 6008 #define FB_CSCR_ASET_MASK 0x300000u
Jasper_lee 0:b16d94660a33 6009 #define FB_CSCR_ASET_SHIFT 20
Jasper_lee 0:b16d94660a33 6010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
Jasper_lee 0:b16d94660a33 6011 #define FB_CSCR_EXTS_MASK 0x400000u
Jasper_lee 0:b16d94660a33 6012 #define FB_CSCR_EXTS_SHIFT 22
Jasper_lee 0:b16d94660a33 6013 #define FB_CSCR_SWSEN_MASK 0x800000u
Jasper_lee 0:b16d94660a33 6014 #define FB_CSCR_SWSEN_SHIFT 23
Jasper_lee 0:b16d94660a33 6015 #define FB_CSCR_SWS_MASK 0xFC000000u
Jasper_lee 0:b16d94660a33 6016 #define FB_CSCR_SWS_SHIFT 26
Jasper_lee 0:b16d94660a33 6017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
Jasper_lee 0:b16d94660a33 6018 /* CSPMCR Bit Fields */
Jasper_lee 0:b16d94660a33 6019 #define FB_CSPMCR_GROUP5_MASK 0xF000u
Jasper_lee 0:b16d94660a33 6020 #define FB_CSPMCR_GROUP5_SHIFT 12
Jasper_lee 0:b16d94660a33 6021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
Jasper_lee 0:b16d94660a33 6022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 6023 #define FB_CSPMCR_GROUP4_SHIFT 16
Jasper_lee 0:b16d94660a33 6024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
Jasper_lee 0:b16d94660a33 6025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
Jasper_lee 0:b16d94660a33 6026 #define FB_CSPMCR_GROUP3_SHIFT 20
Jasper_lee 0:b16d94660a33 6027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
Jasper_lee 0:b16d94660a33 6028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 6029 #define FB_CSPMCR_GROUP2_SHIFT 24
Jasper_lee 0:b16d94660a33 6030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
Jasper_lee 0:b16d94660a33 6031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 6032 #define FB_CSPMCR_GROUP1_SHIFT 28
Jasper_lee 0:b16d94660a33 6033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
Jasper_lee 0:b16d94660a33 6034
Jasper_lee 0:b16d94660a33 6035 /*!
Jasper_lee 0:b16d94660a33 6036 * @}
Jasper_lee 0:b16d94660a33 6037 */ /* end of group FB_Register_Masks */
Jasper_lee 0:b16d94660a33 6038
Jasper_lee 0:b16d94660a33 6039
Jasper_lee 0:b16d94660a33 6040 /* FB - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 6041 /** Peripheral FB base address */
Jasper_lee 0:b16d94660a33 6042 #define FB_BASE (0x4000C000u)
Jasper_lee 0:b16d94660a33 6043 /** Peripheral FB base pointer */
Jasper_lee 0:b16d94660a33 6044 #define FB ((FB_Type *)FB_BASE)
Jasper_lee 0:b16d94660a33 6045 #define FB_BASE_PTR (FB)
Jasper_lee 0:b16d94660a33 6046 /** Array initializer of FB peripheral base addresses */
Jasper_lee 0:b16d94660a33 6047 #define FB_BASE_ADDRS { FB_BASE }
Jasper_lee 0:b16d94660a33 6048 /** Array initializer of FB peripheral base pointers */
Jasper_lee 0:b16d94660a33 6049 #define FB_BASE_PTRS { FB }
Jasper_lee 0:b16d94660a33 6050
Jasper_lee 0:b16d94660a33 6051 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6052 -- FB - Register accessor macros
Jasper_lee 0:b16d94660a33 6053 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6054
Jasper_lee 0:b16d94660a33 6055 /*!
Jasper_lee 0:b16d94660a33 6056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
Jasper_lee 0:b16d94660a33 6057 * @{
Jasper_lee 0:b16d94660a33 6058 */
Jasper_lee 0:b16d94660a33 6059
Jasper_lee 0:b16d94660a33 6060
Jasper_lee 0:b16d94660a33 6061 /* FB - Register instance definitions */
Jasper_lee 0:b16d94660a33 6062 /* FB */
Jasper_lee 0:b16d94660a33 6063 #define FB_CSAR0 FB_CSAR_REG(FB,0)
Jasper_lee 0:b16d94660a33 6064 #define FB_CSMR0 FB_CSMR_REG(FB,0)
Jasper_lee 0:b16d94660a33 6065 #define FB_CSCR0 FB_CSCR_REG(FB,0)
Jasper_lee 0:b16d94660a33 6066 #define FB_CSAR1 FB_CSAR_REG(FB,1)
Jasper_lee 0:b16d94660a33 6067 #define FB_CSMR1 FB_CSMR_REG(FB,1)
Jasper_lee 0:b16d94660a33 6068 #define FB_CSCR1 FB_CSCR_REG(FB,1)
Jasper_lee 0:b16d94660a33 6069 #define FB_CSAR2 FB_CSAR_REG(FB,2)
Jasper_lee 0:b16d94660a33 6070 #define FB_CSMR2 FB_CSMR_REG(FB,2)
Jasper_lee 0:b16d94660a33 6071 #define FB_CSCR2 FB_CSCR_REG(FB,2)
Jasper_lee 0:b16d94660a33 6072 #define FB_CSAR3 FB_CSAR_REG(FB,3)
Jasper_lee 0:b16d94660a33 6073 #define FB_CSMR3 FB_CSMR_REG(FB,3)
Jasper_lee 0:b16d94660a33 6074 #define FB_CSCR3 FB_CSCR_REG(FB,3)
Jasper_lee 0:b16d94660a33 6075 #define FB_CSAR4 FB_CSAR_REG(FB,4)
Jasper_lee 0:b16d94660a33 6076 #define FB_CSMR4 FB_CSMR_REG(FB,4)
Jasper_lee 0:b16d94660a33 6077 #define FB_CSCR4 FB_CSCR_REG(FB,4)
Jasper_lee 0:b16d94660a33 6078 #define FB_CSAR5 FB_CSAR_REG(FB,5)
Jasper_lee 0:b16d94660a33 6079 #define FB_CSMR5 FB_CSMR_REG(FB,5)
Jasper_lee 0:b16d94660a33 6080 #define FB_CSCR5 FB_CSCR_REG(FB,5)
Jasper_lee 0:b16d94660a33 6081 #define FB_CSPMCR FB_CSPMCR_REG(FB)
Jasper_lee 0:b16d94660a33 6082
Jasper_lee 0:b16d94660a33 6083 /* FB - Register array accessors */
Jasper_lee 0:b16d94660a33 6084 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
Jasper_lee 0:b16d94660a33 6085 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
Jasper_lee 0:b16d94660a33 6086 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
Jasper_lee 0:b16d94660a33 6087
Jasper_lee 0:b16d94660a33 6088 /*!
Jasper_lee 0:b16d94660a33 6089 * @}
Jasper_lee 0:b16d94660a33 6090 */ /* end of group FB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6091
Jasper_lee 0:b16d94660a33 6092
Jasper_lee 0:b16d94660a33 6093 /*!
Jasper_lee 0:b16d94660a33 6094 * @}
Jasper_lee 0:b16d94660a33 6095 */ /* end of group FB_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 6096
Jasper_lee 0:b16d94660a33 6097
Jasper_lee 0:b16d94660a33 6098 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6099 -- FMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6100 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6101
Jasper_lee 0:b16d94660a33 6102 /*!
Jasper_lee 0:b16d94660a33 6103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6104 * @{
Jasper_lee 0:b16d94660a33 6105 */
Jasper_lee 0:b16d94660a33 6106
Jasper_lee 0:b16d94660a33 6107 /** FMC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 6108 typedef struct {
Jasper_lee 0:b16d94660a33 6109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 6110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 6111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 6112 uint8_t RESERVED_0[244];
Jasper_lee 0:b16d94660a33 6113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
Jasper_lee 0:b16d94660a33 6114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
Jasper_lee 0:b16d94660a33 6115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
Jasper_lee 0:b16d94660a33 6116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
Jasper_lee 0:b16d94660a33 6117 uint8_t RESERVED_1[192];
Jasper_lee 0:b16d94660a33 6118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
Jasper_lee 0:b16d94660a33 6119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
Jasper_lee 0:b16d94660a33 6120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
Jasper_lee 0:b16d94660a33 6121 } SET[4][4];
Jasper_lee 0:b16d94660a33 6122 } FMC_Type, *FMC_MemMapPtr;
Jasper_lee 0:b16d94660a33 6123
Jasper_lee 0:b16d94660a33 6124 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6125 -- FMC - Register accessor macros
Jasper_lee 0:b16d94660a33 6126 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6127
Jasper_lee 0:b16d94660a33 6128 /*!
Jasper_lee 0:b16d94660a33 6129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
Jasper_lee 0:b16d94660a33 6130 * @{
Jasper_lee 0:b16d94660a33 6131 */
Jasper_lee 0:b16d94660a33 6132
Jasper_lee 0:b16d94660a33 6133
Jasper_lee 0:b16d94660a33 6134 /* FMC - Register accessors */
Jasper_lee 0:b16d94660a33 6135 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
Jasper_lee 0:b16d94660a33 6136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
Jasper_lee 0:b16d94660a33 6137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
Jasper_lee 0:b16d94660a33 6138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
Jasper_lee 0:b16d94660a33 6139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
Jasper_lee 0:b16d94660a33 6140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
Jasper_lee 0:b16d94660a33 6141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
Jasper_lee 0:b16d94660a33 6142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
Jasper_lee 0:b16d94660a33 6143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
Jasper_lee 0:b16d94660a33 6144
Jasper_lee 0:b16d94660a33 6145 /*!
Jasper_lee 0:b16d94660a33 6146 * @}
Jasper_lee 0:b16d94660a33 6147 */ /* end of group FMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6148
Jasper_lee 0:b16d94660a33 6149
Jasper_lee 0:b16d94660a33 6150 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6151 -- FMC Register Masks
Jasper_lee 0:b16d94660a33 6152 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6153
Jasper_lee 0:b16d94660a33 6154 /*!
Jasper_lee 0:b16d94660a33 6155 * @addtogroup FMC_Register_Masks FMC Register Masks
Jasper_lee 0:b16d94660a33 6156 * @{
Jasper_lee 0:b16d94660a33 6157 */
Jasper_lee 0:b16d94660a33 6158
Jasper_lee 0:b16d94660a33 6159 /* PFAPR Bit Fields */
Jasper_lee 0:b16d94660a33 6160 #define FMC_PFAPR_M0AP_MASK 0x3u
Jasper_lee 0:b16d94660a33 6161 #define FMC_PFAPR_M0AP_SHIFT 0
Jasper_lee 0:b16d94660a33 6162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
Jasper_lee 0:b16d94660a33 6163 #define FMC_PFAPR_M1AP_MASK 0xCu
Jasper_lee 0:b16d94660a33 6164 #define FMC_PFAPR_M1AP_SHIFT 2
Jasper_lee 0:b16d94660a33 6165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
Jasper_lee 0:b16d94660a33 6166 #define FMC_PFAPR_M2AP_MASK 0x30u
Jasper_lee 0:b16d94660a33 6167 #define FMC_PFAPR_M2AP_SHIFT 4
Jasper_lee 0:b16d94660a33 6168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
Jasper_lee 0:b16d94660a33 6169 #define FMC_PFAPR_M3AP_MASK 0xC0u
Jasper_lee 0:b16d94660a33 6170 #define FMC_PFAPR_M3AP_SHIFT 6
Jasper_lee 0:b16d94660a33 6171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
Jasper_lee 0:b16d94660a33 6172 #define FMC_PFAPR_M4AP_MASK 0x300u
Jasper_lee 0:b16d94660a33 6173 #define FMC_PFAPR_M4AP_SHIFT 8
Jasper_lee 0:b16d94660a33 6174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
Jasper_lee 0:b16d94660a33 6175 #define FMC_PFAPR_M5AP_MASK 0xC00u
Jasper_lee 0:b16d94660a33 6176 #define FMC_PFAPR_M5AP_SHIFT 10
Jasper_lee 0:b16d94660a33 6177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
Jasper_lee 0:b16d94660a33 6178 #define FMC_PFAPR_M6AP_MASK 0x3000u
Jasper_lee 0:b16d94660a33 6179 #define FMC_PFAPR_M6AP_SHIFT 12
Jasper_lee 0:b16d94660a33 6180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
Jasper_lee 0:b16d94660a33 6181 #define FMC_PFAPR_M7AP_MASK 0xC000u
Jasper_lee 0:b16d94660a33 6182 #define FMC_PFAPR_M7AP_SHIFT 14
Jasper_lee 0:b16d94660a33 6183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
Jasper_lee 0:b16d94660a33 6184 #define FMC_PFAPR_M0PFD_MASK 0x10000u
Jasper_lee 0:b16d94660a33 6185 #define FMC_PFAPR_M0PFD_SHIFT 16
Jasper_lee 0:b16d94660a33 6186 #define FMC_PFAPR_M1PFD_MASK 0x20000u
Jasper_lee 0:b16d94660a33 6187 #define FMC_PFAPR_M1PFD_SHIFT 17
Jasper_lee 0:b16d94660a33 6188 #define FMC_PFAPR_M2PFD_MASK 0x40000u
Jasper_lee 0:b16d94660a33 6189 #define FMC_PFAPR_M2PFD_SHIFT 18
Jasper_lee 0:b16d94660a33 6190 #define FMC_PFAPR_M3PFD_MASK 0x80000u
Jasper_lee 0:b16d94660a33 6191 #define FMC_PFAPR_M3PFD_SHIFT 19
Jasper_lee 0:b16d94660a33 6192 #define FMC_PFAPR_M4PFD_MASK 0x100000u
Jasper_lee 0:b16d94660a33 6193 #define FMC_PFAPR_M4PFD_SHIFT 20
Jasper_lee 0:b16d94660a33 6194 #define FMC_PFAPR_M5PFD_MASK 0x200000u
Jasper_lee 0:b16d94660a33 6195 #define FMC_PFAPR_M5PFD_SHIFT 21
Jasper_lee 0:b16d94660a33 6196 #define FMC_PFAPR_M6PFD_MASK 0x400000u
Jasper_lee 0:b16d94660a33 6197 #define FMC_PFAPR_M6PFD_SHIFT 22
Jasper_lee 0:b16d94660a33 6198 #define FMC_PFAPR_M7PFD_MASK 0x800000u
Jasper_lee 0:b16d94660a33 6199 #define FMC_PFAPR_M7PFD_SHIFT 23
Jasper_lee 0:b16d94660a33 6200 /* PFB0CR Bit Fields */
Jasper_lee 0:b16d94660a33 6201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
Jasper_lee 0:b16d94660a33 6202 #define FMC_PFB0CR_B0SEBE_SHIFT 0
Jasper_lee 0:b16d94660a33 6203 #define FMC_PFB0CR_B0IPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 6204 #define FMC_PFB0CR_B0IPE_SHIFT 1
Jasper_lee 0:b16d94660a33 6205 #define FMC_PFB0CR_B0DPE_MASK 0x4u
Jasper_lee 0:b16d94660a33 6206 #define FMC_PFB0CR_B0DPE_SHIFT 2
Jasper_lee 0:b16d94660a33 6207 #define FMC_PFB0CR_B0ICE_MASK 0x8u
Jasper_lee 0:b16d94660a33 6208 #define FMC_PFB0CR_B0ICE_SHIFT 3
Jasper_lee 0:b16d94660a33 6209 #define FMC_PFB0CR_B0DCE_MASK 0x10u
Jasper_lee 0:b16d94660a33 6210 #define FMC_PFB0CR_B0DCE_SHIFT 4
Jasper_lee 0:b16d94660a33 6211 #define FMC_PFB0CR_CRC_MASK 0xE0u
Jasper_lee 0:b16d94660a33 6212 #define FMC_PFB0CR_CRC_SHIFT 5
Jasper_lee 0:b16d94660a33 6213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
Jasper_lee 0:b16d94660a33 6214 #define FMC_PFB0CR_B0MW_MASK 0x60000u
Jasper_lee 0:b16d94660a33 6215 #define FMC_PFB0CR_B0MW_SHIFT 17
Jasper_lee 0:b16d94660a33 6216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
Jasper_lee 0:b16d94660a33 6217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
Jasper_lee 0:b16d94660a33 6218 #define FMC_PFB0CR_S_B_INV_SHIFT 19
Jasper_lee 0:b16d94660a33 6219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
Jasper_lee 0:b16d94660a33 6220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
Jasper_lee 0:b16d94660a33 6221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
Jasper_lee 0:b16d94660a33 6222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 6223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
Jasper_lee 0:b16d94660a33 6224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
Jasper_lee 0:b16d94660a33 6225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 6226 #define FMC_PFB0CR_B0RWSC_SHIFT 28
Jasper_lee 0:b16d94660a33 6227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
Jasper_lee 0:b16d94660a33 6228 /* PFB1CR Bit Fields */
Jasper_lee 0:b16d94660a33 6229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
Jasper_lee 0:b16d94660a33 6230 #define FMC_PFB1CR_B1SEBE_SHIFT 0
Jasper_lee 0:b16d94660a33 6231 #define FMC_PFB1CR_B1IPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 6232 #define FMC_PFB1CR_B1IPE_SHIFT 1
Jasper_lee 0:b16d94660a33 6233 #define FMC_PFB1CR_B1DPE_MASK 0x4u
Jasper_lee 0:b16d94660a33 6234 #define FMC_PFB1CR_B1DPE_SHIFT 2
Jasper_lee 0:b16d94660a33 6235 #define FMC_PFB1CR_B1ICE_MASK 0x8u
Jasper_lee 0:b16d94660a33 6236 #define FMC_PFB1CR_B1ICE_SHIFT 3
Jasper_lee 0:b16d94660a33 6237 #define FMC_PFB1CR_B1DCE_MASK 0x10u
Jasper_lee 0:b16d94660a33 6238 #define FMC_PFB1CR_B1DCE_SHIFT 4
Jasper_lee 0:b16d94660a33 6239 #define FMC_PFB1CR_B1MW_MASK 0x60000u
Jasper_lee 0:b16d94660a33 6240 #define FMC_PFB1CR_B1MW_SHIFT 17
Jasper_lee 0:b16d94660a33 6241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
Jasper_lee 0:b16d94660a33 6242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 6243 #define FMC_PFB1CR_B1RWSC_SHIFT 28
Jasper_lee 0:b16d94660a33 6244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
Jasper_lee 0:b16d94660a33 6245 /* TAGVDW0S Bit Fields */
Jasper_lee 0:b16d94660a33 6246 #define FMC_TAGVDW0S_valid_MASK 0x1u
Jasper_lee 0:b16d94660a33 6247 #define FMC_TAGVDW0S_valid_SHIFT 0
Jasper_lee 0:b16d94660a33 6248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
Jasper_lee 0:b16d94660a33 6249 #define FMC_TAGVDW0S_tag_SHIFT 5
Jasper_lee 0:b16d94660a33 6250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
Jasper_lee 0:b16d94660a33 6251 /* TAGVDW1S Bit Fields */
Jasper_lee 0:b16d94660a33 6252 #define FMC_TAGVDW1S_valid_MASK 0x1u
Jasper_lee 0:b16d94660a33 6253 #define FMC_TAGVDW1S_valid_SHIFT 0
Jasper_lee 0:b16d94660a33 6254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
Jasper_lee 0:b16d94660a33 6255 #define FMC_TAGVDW1S_tag_SHIFT 5
Jasper_lee 0:b16d94660a33 6256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
Jasper_lee 0:b16d94660a33 6257 /* TAGVDW2S Bit Fields */
Jasper_lee 0:b16d94660a33 6258 #define FMC_TAGVDW2S_valid_MASK 0x1u
Jasper_lee 0:b16d94660a33 6259 #define FMC_TAGVDW2S_valid_SHIFT 0
Jasper_lee 0:b16d94660a33 6260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
Jasper_lee 0:b16d94660a33 6261 #define FMC_TAGVDW2S_tag_SHIFT 5
Jasper_lee 0:b16d94660a33 6262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
Jasper_lee 0:b16d94660a33 6263 /* TAGVDW3S Bit Fields */
Jasper_lee 0:b16d94660a33 6264 #define FMC_TAGVDW3S_valid_MASK 0x1u
Jasper_lee 0:b16d94660a33 6265 #define FMC_TAGVDW3S_valid_SHIFT 0
Jasper_lee 0:b16d94660a33 6266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
Jasper_lee 0:b16d94660a33 6267 #define FMC_TAGVDW3S_tag_SHIFT 5
Jasper_lee 0:b16d94660a33 6268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
Jasper_lee 0:b16d94660a33 6269 /* DATA_U Bit Fields */
Jasper_lee 0:b16d94660a33 6270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 6271 #define FMC_DATA_U_data_SHIFT 0
Jasper_lee 0:b16d94660a33 6272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
Jasper_lee 0:b16d94660a33 6273 /* DATA_L Bit Fields */
Jasper_lee 0:b16d94660a33 6274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 6275 #define FMC_DATA_L_data_SHIFT 0
Jasper_lee 0:b16d94660a33 6276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
Jasper_lee 0:b16d94660a33 6277
Jasper_lee 0:b16d94660a33 6278 /*!
Jasper_lee 0:b16d94660a33 6279 * @}
Jasper_lee 0:b16d94660a33 6280 */ /* end of group FMC_Register_Masks */
Jasper_lee 0:b16d94660a33 6281
Jasper_lee 0:b16d94660a33 6282
Jasper_lee 0:b16d94660a33 6283 /* FMC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 6284 /** Peripheral FMC base address */
Jasper_lee 0:b16d94660a33 6285 #define FMC_BASE (0x4001F000u)
Jasper_lee 0:b16d94660a33 6286 /** Peripheral FMC base pointer */
Jasper_lee 0:b16d94660a33 6287 #define FMC ((FMC_Type *)FMC_BASE)
Jasper_lee 0:b16d94660a33 6288 #define FMC_BASE_PTR (FMC)
Jasper_lee 0:b16d94660a33 6289 /** Array initializer of FMC peripheral base addresses */
Jasper_lee 0:b16d94660a33 6290 #define FMC_BASE_ADDRS { FMC_BASE }
Jasper_lee 0:b16d94660a33 6291 /** Array initializer of FMC peripheral base pointers */
Jasper_lee 0:b16d94660a33 6292 #define FMC_BASE_PTRS { FMC }
Jasper_lee 0:b16d94660a33 6293
Jasper_lee 0:b16d94660a33 6294 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6295 -- FMC - Register accessor macros
Jasper_lee 0:b16d94660a33 6296 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6297
Jasper_lee 0:b16d94660a33 6298 /*!
Jasper_lee 0:b16d94660a33 6299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
Jasper_lee 0:b16d94660a33 6300 * @{
Jasper_lee 0:b16d94660a33 6301 */
Jasper_lee 0:b16d94660a33 6302
Jasper_lee 0:b16d94660a33 6303
Jasper_lee 0:b16d94660a33 6304 /* FMC - Register instance definitions */
Jasper_lee 0:b16d94660a33 6305 /* FMC */
Jasper_lee 0:b16d94660a33 6306 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
Jasper_lee 0:b16d94660a33 6307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
Jasper_lee 0:b16d94660a33 6308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
Jasper_lee 0:b16d94660a33 6309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
Jasper_lee 0:b16d94660a33 6310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
Jasper_lee 0:b16d94660a33 6311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
Jasper_lee 0:b16d94660a33 6312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
Jasper_lee 0:b16d94660a33 6313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
Jasper_lee 0:b16d94660a33 6314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
Jasper_lee 0:b16d94660a33 6315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
Jasper_lee 0:b16d94660a33 6316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
Jasper_lee 0:b16d94660a33 6317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
Jasper_lee 0:b16d94660a33 6318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
Jasper_lee 0:b16d94660a33 6319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
Jasper_lee 0:b16d94660a33 6320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
Jasper_lee 0:b16d94660a33 6321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
Jasper_lee 0:b16d94660a33 6322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
Jasper_lee 0:b16d94660a33 6323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
Jasper_lee 0:b16d94660a33 6324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
Jasper_lee 0:b16d94660a33 6325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
Jasper_lee 0:b16d94660a33 6326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
Jasper_lee 0:b16d94660a33 6327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
Jasper_lee 0:b16d94660a33 6328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
Jasper_lee 0:b16d94660a33 6329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
Jasper_lee 0:b16d94660a33 6330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
Jasper_lee 0:b16d94660a33 6331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
Jasper_lee 0:b16d94660a33 6332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
Jasper_lee 0:b16d94660a33 6333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
Jasper_lee 0:b16d94660a33 6334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
Jasper_lee 0:b16d94660a33 6335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
Jasper_lee 0:b16d94660a33 6336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
Jasper_lee 0:b16d94660a33 6337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
Jasper_lee 0:b16d94660a33 6338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
Jasper_lee 0:b16d94660a33 6339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
Jasper_lee 0:b16d94660a33 6340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
Jasper_lee 0:b16d94660a33 6341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
Jasper_lee 0:b16d94660a33 6342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
Jasper_lee 0:b16d94660a33 6343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
Jasper_lee 0:b16d94660a33 6344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
Jasper_lee 0:b16d94660a33 6345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
Jasper_lee 0:b16d94660a33 6346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
Jasper_lee 0:b16d94660a33 6347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
Jasper_lee 0:b16d94660a33 6348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
Jasper_lee 0:b16d94660a33 6349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
Jasper_lee 0:b16d94660a33 6350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
Jasper_lee 0:b16d94660a33 6351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
Jasper_lee 0:b16d94660a33 6352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
Jasper_lee 0:b16d94660a33 6353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
Jasper_lee 0:b16d94660a33 6354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
Jasper_lee 0:b16d94660a33 6355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
Jasper_lee 0:b16d94660a33 6356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
Jasper_lee 0:b16d94660a33 6357
Jasper_lee 0:b16d94660a33 6358 /* FMC - Register array accessors */
Jasper_lee 0:b16d94660a33 6359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
Jasper_lee 0:b16d94660a33 6360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
Jasper_lee 0:b16d94660a33 6361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
Jasper_lee 0:b16d94660a33 6362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
Jasper_lee 0:b16d94660a33 6363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
Jasper_lee 0:b16d94660a33 6364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
Jasper_lee 0:b16d94660a33 6365
Jasper_lee 0:b16d94660a33 6366 /*!
Jasper_lee 0:b16d94660a33 6367 * @}
Jasper_lee 0:b16d94660a33 6368 */ /* end of group FMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6369
Jasper_lee 0:b16d94660a33 6370
Jasper_lee 0:b16d94660a33 6371 /*!
Jasper_lee 0:b16d94660a33 6372 * @}
Jasper_lee 0:b16d94660a33 6373 */ /* end of group FMC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 6374
Jasper_lee 0:b16d94660a33 6375
Jasper_lee 0:b16d94660a33 6376 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6377 -- FTFE Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6378 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6379
Jasper_lee 0:b16d94660a33 6380 /*!
Jasper_lee 0:b16d94660a33 6381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6382 * @{
Jasper_lee 0:b16d94660a33 6383 */
Jasper_lee 0:b16d94660a33 6384
Jasper_lee 0:b16d94660a33 6385 /** FTFE - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 6386 typedef struct {
Jasper_lee 0:b16d94660a33 6387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 6388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 6389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 6390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 6391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
Jasper_lee 0:b16d94660a33 6392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
Jasper_lee 0:b16d94660a33 6393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
Jasper_lee 0:b16d94660a33 6394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
Jasper_lee 0:b16d94660a33 6395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
Jasper_lee 0:b16d94660a33 6396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
Jasper_lee 0:b16d94660a33 6397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
Jasper_lee 0:b16d94660a33 6398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
Jasper_lee 0:b16d94660a33 6399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
Jasper_lee 0:b16d94660a33 6400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
Jasper_lee 0:b16d94660a33 6401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
Jasper_lee 0:b16d94660a33 6402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
Jasper_lee 0:b16d94660a33 6403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
Jasper_lee 0:b16d94660a33 6404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
Jasper_lee 0:b16d94660a33 6405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
Jasper_lee 0:b16d94660a33 6406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
Jasper_lee 0:b16d94660a33 6407 uint8_t RESERVED_0[2];
Jasper_lee 0:b16d94660a33 6408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
Jasper_lee 0:b16d94660a33 6409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
Jasper_lee 0:b16d94660a33 6410 } FTFE_Type, *FTFE_MemMapPtr;
Jasper_lee 0:b16d94660a33 6411
Jasper_lee 0:b16d94660a33 6412 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6413 -- FTFE - Register accessor macros
Jasper_lee 0:b16d94660a33 6414 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6415
Jasper_lee 0:b16d94660a33 6416 /*!
Jasper_lee 0:b16d94660a33 6417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
Jasper_lee 0:b16d94660a33 6418 * @{
Jasper_lee 0:b16d94660a33 6419 */
Jasper_lee 0:b16d94660a33 6420
Jasper_lee 0:b16d94660a33 6421
Jasper_lee 0:b16d94660a33 6422 /* FTFE - Register accessors */
Jasper_lee 0:b16d94660a33 6423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
Jasper_lee 0:b16d94660a33 6424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
Jasper_lee 0:b16d94660a33 6425 #define FTFE_FSEC_REG(base) ((base)->FSEC)
Jasper_lee 0:b16d94660a33 6426 #define FTFE_FOPT_REG(base) ((base)->FOPT)
Jasper_lee 0:b16d94660a33 6427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
Jasper_lee 0:b16d94660a33 6428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
Jasper_lee 0:b16d94660a33 6429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
Jasper_lee 0:b16d94660a33 6430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
Jasper_lee 0:b16d94660a33 6431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
Jasper_lee 0:b16d94660a33 6432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
Jasper_lee 0:b16d94660a33 6433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
Jasper_lee 0:b16d94660a33 6434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
Jasper_lee 0:b16d94660a33 6435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
Jasper_lee 0:b16d94660a33 6436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
Jasper_lee 0:b16d94660a33 6437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
Jasper_lee 0:b16d94660a33 6438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
Jasper_lee 0:b16d94660a33 6439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
Jasper_lee 0:b16d94660a33 6440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
Jasper_lee 0:b16d94660a33 6441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
Jasper_lee 0:b16d94660a33 6442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
Jasper_lee 0:b16d94660a33 6443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
Jasper_lee 0:b16d94660a33 6444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
Jasper_lee 0:b16d94660a33 6445
Jasper_lee 0:b16d94660a33 6446 /*!
Jasper_lee 0:b16d94660a33 6447 * @}
Jasper_lee 0:b16d94660a33 6448 */ /* end of group FTFE_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6449
Jasper_lee 0:b16d94660a33 6450
Jasper_lee 0:b16d94660a33 6451 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6452 -- FTFE Register Masks
Jasper_lee 0:b16d94660a33 6453 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6454
Jasper_lee 0:b16d94660a33 6455 /*!
Jasper_lee 0:b16d94660a33 6456 * @addtogroup FTFE_Register_Masks FTFE Register Masks
Jasper_lee 0:b16d94660a33 6457 * @{
Jasper_lee 0:b16d94660a33 6458 */
Jasper_lee 0:b16d94660a33 6459
Jasper_lee 0:b16d94660a33 6460 /* FSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 6461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
Jasper_lee 0:b16d94660a33 6462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
Jasper_lee 0:b16d94660a33 6463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
Jasper_lee 0:b16d94660a33 6464 #define FTFE_FSTAT_FPVIOL_SHIFT 4
Jasper_lee 0:b16d94660a33 6465 #define FTFE_FSTAT_ACCERR_MASK 0x20u
Jasper_lee 0:b16d94660a33 6466 #define FTFE_FSTAT_ACCERR_SHIFT 5
Jasper_lee 0:b16d94660a33 6467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
Jasper_lee 0:b16d94660a33 6468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
Jasper_lee 0:b16d94660a33 6469 #define FTFE_FSTAT_CCIF_MASK 0x80u
Jasper_lee 0:b16d94660a33 6470 #define FTFE_FSTAT_CCIF_SHIFT 7
Jasper_lee 0:b16d94660a33 6471 /* FCNFG Bit Fields */
Jasper_lee 0:b16d94660a33 6472 #define FTFE_FCNFG_EEERDY_MASK 0x1u
Jasper_lee 0:b16d94660a33 6473 #define FTFE_FCNFG_EEERDY_SHIFT 0
Jasper_lee 0:b16d94660a33 6474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
Jasper_lee 0:b16d94660a33 6475 #define FTFE_FCNFG_RAMRDY_SHIFT 1
Jasper_lee 0:b16d94660a33 6476 #define FTFE_FCNFG_PFLSH_MASK 0x4u
Jasper_lee 0:b16d94660a33 6477 #define FTFE_FCNFG_PFLSH_SHIFT 2
Jasper_lee 0:b16d94660a33 6478 #define FTFE_FCNFG_SWAP_MASK 0x8u
Jasper_lee 0:b16d94660a33 6479 #define FTFE_FCNFG_SWAP_SHIFT 3
Jasper_lee 0:b16d94660a33 6480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
Jasper_lee 0:b16d94660a33 6481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
Jasper_lee 0:b16d94660a33 6482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
Jasper_lee 0:b16d94660a33 6483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
Jasper_lee 0:b16d94660a33 6484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 6485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
Jasper_lee 0:b16d94660a33 6486 #define FTFE_FCNFG_CCIE_MASK 0x80u
Jasper_lee 0:b16d94660a33 6487 #define FTFE_FCNFG_CCIE_SHIFT 7
Jasper_lee 0:b16d94660a33 6488 /* FSEC Bit Fields */
Jasper_lee 0:b16d94660a33 6489 #define FTFE_FSEC_SEC_MASK 0x3u
Jasper_lee 0:b16d94660a33 6490 #define FTFE_FSEC_SEC_SHIFT 0
Jasper_lee 0:b16d94660a33 6491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
Jasper_lee 0:b16d94660a33 6492 #define FTFE_FSEC_FSLACC_MASK 0xCu
Jasper_lee 0:b16d94660a33 6493 #define FTFE_FSEC_FSLACC_SHIFT 2
Jasper_lee 0:b16d94660a33 6494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
Jasper_lee 0:b16d94660a33 6495 #define FTFE_FSEC_MEEN_MASK 0x30u
Jasper_lee 0:b16d94660a33 6496 #define FTFE_FSEC_MEEN_SHIFT 4
Jasper_lee 0:b16d94660a33 6497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
Jasper_lee 0:b16d94660a33 6498 #define FTFE_FSEC_KEYEN_MASK 0xC0u
Jasper_lee 0:b16d94660a33 6499 #define FTFE_FSEC_KEYEN_SHIFT 6
Jasper_lee 0:b16d94660a33 6500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
Jasper_lee 0:b16d94660a33 6501 /* FOPT Bit Fields */
Jasper_lee 0:b16d94660a33 6502 #define FTFE_FOPT_OPT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6503 #define FTFE_FOPT_OPT_SHIFT 0
Jasper_lee 0:b16d94660a33 6504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
Jasper_lee 0:b16d94660a33 6505 /* FCCOB3 Bit Fields */
Jasper_lee 0:b16d94660a33 6506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6507 #define FTFE_FCCOB3_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6509 /* FCCOB2 Bit Fields */
Jasper_lee 0:b16d94660a33 6510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6511 #define FTFE_FCCOB2_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6513 /* FCCOB1 Bit Fields */
Jasper_lee 0:b16d94660a33 6514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6515 #define FTFE_FCCOB1_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6517 /* FCCOB0 Bit Fields */
Jasper_lee 0:b16d94660a33 6518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6519 #define FTFE_FCCOB0_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6521 /* FCCOB7 Bit Fields */
Jasper_lee 0:b16d94660a33 6522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6523 #define FTFE_FCCOB7_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6525 /* FCCOB6 Bit Fields */
Jasper_lee 0:b16d94660a33 6526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6527 #define FTFE_FCCOB6_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6529 /* FCCOB5 Bit Fields */
Jasper_lee 0:b16d94660a33 6530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6531 #define FTFE_FCCOB5_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6533 /* FCCOB4 Bit Fields */
Jasper_lee 0:b16d94660a33 6534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6535 #define FTFE_FCCOB4_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6537 /* FCCOBB Bit Fields */
Jasper_lee 0:b16d94660a33 6538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6539 #define FTFE_FCCOBB_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6541 /* FCCOBA Bit Fields */
Jasper_lee 0:b16d94660a33 6542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6543 #define FTFE_FCCOBA_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6545 /* FCCOB9 Bit Fields */
Jasper_lee 0:b16d94660a33 6546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6547 #define FTFE_FCCOB9_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6549 /* FCCOB8 Bit Fields */
Jasper_lee 0:b16d94660a33 6550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6551 #define FTFE_FCCOB8_CCOBn_SHIFT 0
Jasper_lee 0:b16d94660a33 6552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
Jasper_lee 0:b16d94660a33 6553 /* FPROT3 Bit Fields */
Jasper_lee 0:b16d94660a33 6554 #define FTFE_FPROT3_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6555 #define FTFE_FPROT3_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
Jasper_lee 0:b16d94660a33 6557 /* FPROT2 Bit Fields */
Jasper_lee 0:b16d94660a33 6558 #define FTFE_FPROT2_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6559 #define FTFE_FPROT2_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
Jasper_lee 0:b16d94660a33 6561 /* FPROT1 Bit Fields */
Jasper_lee 0:b16d94660a33 6562 #define FTFE_FPROT1_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6563 #define FTFE_FPROT1_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
Jasper_lee 0:b16d94660a33 6565 /* FPROT0 Bit Fields */
Jasper_lee 0:b16d94660a33 6566 #define FTFE_FPROT0_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6567 #define FTFE_FPROT0_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
Jasper_lee 0:b16d94660a33 6569 /* FEPROT Bit Fields */
Jasper_lee 0:b16d94660a33 6570 #define FTFE_FEPROT_EPROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6571 #define FTFE_FEPROT_EPROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
Jasper_lee 0:b16d94660a33 6573 /* FDPROT Bit Fields */
Jasper_lee 0:b16d94660a33 6574 #define FTFE_FDPROT_DPROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 6575 #define FTFE_FDPROT_DPROT_SHIFT 0
Jasper_lee 0:b16d94660a33 6576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
Jasper_lee 0:b16d94660a33 6577
Jasper_lee 0:b16d94660a33 6578 /*!
Jasper_lee 0:b16d94660a33 6579 * @}
Jasper_lee 0:b16d94660a33 6580 */ /* end of group FTFE_Register_Masks */
Jasper_lee 0:b16d94660a33 6581
Jasper_lee 0:b16d94660a33 6582
Jasper_lee 0:b16d94660a33 6583 /* FTFE - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 6584 /** Peripheral FTFE base address */
Jasper_lee 0:b16d94660a33 6585 #define FTFE_BASE (0x40020000u)
Jasper_lee 0:b16d94660a33 6586 /** Peripheral FTFE base pointer */
Jasper_lee 0:b16d94660a33 6587 #define FTFE ((FTFE_Type *)FTFE_BASE)
Jasper_lee 0:b16d94660a33 6588 #define FTFE_BASE_PTR (FTFE)
Jasper_lee 0:b16d94660a33 6589 /** Array initializer of FTFE peripheral base addresses */
Jasper_lee 0:b16d94660a33 6590 #define FTFE_BASE_ADDRS { FTFE_BASE }
Jasper_lee 0:b16d94660a33 6591 /** Array initializer of FTFE peripheral base pointers */
Jasper_lee 0:b16d94660a33 6592 #define FTFE_BASE_PTRS { FTFE }
Jasper_lee 0:b16d94660a33 6593 /** Interrupt vectors for the FTFE peripheral type */
Jasper_lee 0:b16d94660a33 6594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
Jasper_lee 0:b16d94660a33 6595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
Jasper_lee 0:b16d94660a33 6596
Jasper_lee 0:b16d94660a33 6597 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6598 -- FTFE - Register accessor macros
Jasper_lee 0:b16d94660a33 6599 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6600
Jasper_lee 0:b16d94660a33 6601 /*!
Jasper_lee 0:b16d94660a33 6602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
Jasper_lee 0:b16d94660a33 6603 * @{
Jasper_lee 0:b16d94660a33 6604 */
Jasper_lee 0:b16d94660a33 6605
Jasper_lee 0:b16d94660a33 6606
Jasper_lee 0:b16d94660a33 6607 /* FTFE - Register instance definitions */
Jasper_lee 0:b16d94660a33 6608 /* FTFE */
Jasper_lee 0:b16d94660a33 6609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
Jasper_lee 0:b16d94660a33 6610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
Jasper_lee 0:b16d94660a33 6611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
Jasper_lee 0:b16d94660a33 6612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
Jasper_lee 0:b16d94660a33 6613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
Jasper_lee 0:b16d94660a33 6614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
Jasper_lee 0:b16d94660a33 6615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
Jasper_lee 0:b16d94660a33 6616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
Jasper_lee 0:b16d94660a33 6617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
Jasper_lee 0:b16d94660a33 6618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
Jasper_lee 0:b16d94660a33 6619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
Jasper_lee 0:b16d94660a33 6620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
Jasper_lee 0:b16d94660a33 6621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
Jasper_lee 0:b16d94660a33 6622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
Jasper_lee 0:b16d94660a33 6623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
Jasper_lee 0:b16d94660a33 6624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
Jasper_lee 0:b16d94660a33 6625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
Jasper_lee 0:b16d94660a33 6626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
Jasper_lee 0:b16d94660a33 6627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
Jasper_lee 0:b16d94660a33 6628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
Jasper_lee 0:b16d94660a33 6629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
Jasper_lee 0:b16d94660a33 6630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
Jasper_lee 0:b16d94660a33 6631
Jasper_lee 0:b16d94660a33 6632 /*!
Jasper_lee 0:b16d94660a33 6633 * @}
Jasper_lee 0:b16d94660a33 6634 */ /* end of group FTFE_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6635
Jasper_lee 0:b16d94660a33 6636
Jasper_lee 0:b16d94660a33 6637 /*!
Jasper_lee 0:b16d94660a33 6638 * @}
Jasper_lee 0:b16d94660a33 6639 */ /* end of group FTFE_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 6640
Jasper_lee 0:b16d94660a33 6641
Jasper_lee 0:b16d94660a33 6642 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6643 -- FTM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6644 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6645
Jasper_lee 0:b16d94660a33 6646 /*!
Jasper_lee 0:b16d94660a33 6647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 6648 * @{
Jasper_lee 0:b16d94660a33 6649 */
Jasper_lee 0:b16d94660a33 6650
Jasper_lee 0:b16d94660a33 6651 /** FTM - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 6652 typedef struct {
Jasper_lee 0:b16d94660a33 6653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
Jasper_lee 0:b16d94660a33 6654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
Jasper_lee 0:b16d94660a33 6655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
Jasper_lee 0:b16d94660a33 6656 struct { /* offset: 0xC, array step: 0x8 */
Jasper_lee 0:b16d94660a33 6657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
Jasper_lee 0:b16d94660a33 6658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
Jasper_lee 0:b16d94660a33 6659 } CONTROLS[8];
Jasper_lee 0:b16d94660a33 6660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
Jasper_lee 0:b16d94660a33 6661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
Jasper_lee 0:b16d94660a33 6662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
Jasper_lee 0:b16d94660a33 6663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
Jasper_lee 0:b16d94660a33 6664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
Jasper_lee 0:b16d94660a33 6665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
Jasper_lee 0:b16d94660a33 6666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
Jasper_lee 0:b16d94660a33 6667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
Jasper_lee 0:b16d94660a33 6668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
Jasper_lee 0:b16d94660a33 6669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
Jasper_lee 0:b16d94660a33 6670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
Jasper_lee 0:b16d94660a33 6671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
Jasper_lee 0:b16d94660a33 6672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
Jasper_lee 0:b16d94660a33 6673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
Jasper_lee 0:b16d94660a33 6674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
Jasper_lee 0:b16d94660a33 6675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
Jasper_lee 0:b16d94660a33 6676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
Jasper_lee 0:b16d94660a33 6677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
Jasper_lee 0:b16d94660a33 6678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
Jasper_lee 0:b16d94660a33 6679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
Jasper_lee 0:b16d94660a33 6680 } FTM_Type, *FTM_MemMapPtr;
Jasper_lee 0:b16d94660a33 6681
Jasper_lee 0:b16d94660a33 6682 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6683 -- FTM - Register accessor macros
Jasper_lee 0:b16d94660a33 6684 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6685
Jasper_lee 0:b16d94660a33 6686 /*!
Jasper_lee 0:b16d94660a33 6687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
Jasper_lee 0:b16d94660a33 6688 * @{
Jasper_lee 0:b16d94660a33 6689 */
Jasper_lee 0:b16d94660a33 6690
Jasper_lee 0:b16d94660a33 6691
Jasper_lee 0:b16d94660a33 6692 /* FTM - Register accessors */
Jasper_lee 0:b16d94660a33 6693 #define FTM_SC_REG(base) ((base)->SC)
Jasper_lee 0:b16d94660a33 6694 #define FTM_CNT_REG(base) ((base)->CNT)
Jasper_lee 0:b16d94660a33 6695 #define FTM_MOD_REG(base) ((base)->MOD)
Jasper_lee 0:b16d94660a33 6696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
Jasper_lee 0:b16d94660a33 6697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
Jasper_lee 0:b16d94660a33 6698 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
Jasper_lee 0:b16d94660a33 6699 #define FTM_STATUS_REG(base) ((base)->STATUS)
Jasper_lee 0:b16d94660a33 6700 #define FTM_MODE_REG(base) ((base)->MODE)
Jasper_lee 0:b16d94660a33 6701 #define FTM_SYNC_REG(base) ((base)->SYNC)
Jasper_lee 0:b16d94660a33 6702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
Jasper_lee 0:b16d94660a33 6703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
Jasper_lee 0:b16d94660a33 6704 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
Jasper_lee 0:b16d94660a33 6705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
Jasper_lee 0:b16d94660a33 6706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
Jasper_lee 0:b16d94660a33 6707 #define FTM_POL_REG(base) ((base)->POL)
Jasper_lee 0:b16d94660a33 6708 #define FTM_FMS_REG(base) ((base)->FMS)
Jasper_lee 0:b16d94660a33 6709 #define FTM_FILTER_REG(base) ((base)->FILTER)
Jasper_lee 0:b16d94660a33 6710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
Jasper_lee 0:b16d94660a33 6711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
Jasper_lee 0:b16d94660a33 6712 #define FTM_CONF_REG(base) ((base)->CONF)
Jasper_lee 0:b16d94660a33 6713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
Jasper_lee 0:b16d94660a33 6714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
Jasper_lee 0:b16d94660a33 6715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
Jasper_lee 0:b16d94660a33 6716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
Jasper_lee 0:b16d94660a33 6717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
Jasper_lee 0:b16d94660a33 6718
Jasper_lee 0:b16d94660a33 6719 /*!
Jasper_lee 0:b16d94660a33 6720 * @}
Jasper_lee 0:b16d94660a33 6721 */ /* end of group FTM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 6722
Jasper_lee 0:b16d94660a33 6723
Jasper_lee 0:b16d94660a33 6724 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 6725 -- FTM Register Masks
Jasper_lee 0:b16d94660a33 6726 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 6727
Jasper_lee 0:b16d94660a33 6728 /*!
Jasper_lee 0:b16d94660a33 6729 * @addtogroup FTM_Register_Masks FTM Register Masks
Jasper_lee 0:b16d94660a33 6730 * @{
Jasper_lee 0:b16d94660a33 6731 */
Jasper_lee 0:b16d94660a33 6732
Jasper_lee 0:b16d94660a33 6733 /* SC Bit Fields */
Jasper_lee 0:b16d94660a33 6734 #define FTM_SC_PS_MASK 0x7u
Jasper_lee 0:b16d94660a33 6735 #define FTM_SC_PS_SHIFT 0
Jasper_lee 0:b16d94660a33 6736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
Jasper_lee 0:b16d94660a33 6737 #define FTM_SC_CLKS_MASK 0x18u
Jasper_lee 0:b16d94660a33 6738 #define FTM_SC_CLKS_SHIFT 3
Jasper_lee 0:b16d94660a33 6739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
Jasper_lee 0:b16d94660a33 6740 #define FTM_SC_CPWMS_MASK 0x20u
Jasper_lee 0:b16d94660a33 6741 #define FTM_SC_CPWMS_SHIFT 5
Jasper_lee 0:b16d94660a33 6742 #define FTM_SC_TOIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 6743 #define FTM_SC_TOIE_SHIFT 6
Jasper_lee 0:b16d94660a33 6744 #define FTM_SC_TOF_MASK 0x80u
Jasper_lee 0:b16d94660a33 6745 #define FTM_SC_TOF_SHIFT 7
Jasper_lee 0:b16d94660a33 6746 /* CNT Bit Fields */
Jasper_lee 0:b16d94660a33 6747 #define FTM_CNT_COUNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 6748 #define FTM_CNT_COUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 6749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
Jasper_lee 0:b16d94660a33 6750 /* MOD Bit Fields */
Jasper_lee 0:b16d94660a33 6751 #define FTM_MOD_MOD_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 6752 #define FTM_MOD_MOD_SHIFT 0
Jasper_lee 0:b16d94660a33 6753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
Jasper_lee 0:b16d94660a33 6754 /* CnSC Bit Fields */
Jasper_lee 0:b16d94660a33 6755 #define FTM_CnSC_DMA_MASK 0x1u
Jasper_lee 0:b16d94660a33 6756 #define FTM_CnSC_DMA_SHIFT 0
Jasper_lee 0:b16d94660a33 6757 #define FTM_CnSC_ELSA_MASK 0x4u
Jasper_lee 0:b16d94660a33 6758 #define FTM_CnSC_ELSA_SHIFT 2
Jasper_lee 0:b16d94660a33 6759 #define FTM_CnSC_ELSB_MASK 0x8u
Jasper_lee 0:b16d94660a33 6760 #define FTM_CnSC_ELSB_SHIFT 3
Jasper_lee 0:b16d94660a33 6761 #define FTM_CnSC_MSA_MASK 0x10u
Jasper_lee 0:b16d94660a33 6762 #define FTM_CnSC_MSA_SHIFT 4
Jasper_lee 0:b16d94660a33 6763 #define FTM_CnSC_MSB_MASK 0x20u
Jasper_lee 0:b16d94660a33 6764 #define FTM_CnSC_MSB_SHIFT 5
Jasper_lee 0:b16d94660a33 6765 #define FTM_CnSC_CHIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 6766 #define FTM_CnSC_CHIE_SHIFT 6
Jasper_lee 0:b16d94660a33 6767 #define FTM_CnSC_CHF_MASK 0x80u
Jasper_lee 0:b16d94660a33 6768 #define FTM_CnSC_CHF_SHIFT 7
Jasper_lee 0:b16d94660a33 6769 /* CnV Bit Fields */
Jasper_lee 0:b16d94660a33 6770 #define FTM_CnV_VAL_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 6771 #define FTM_CnV_VAL_SHIFT 0
Jasper_lee 0:b16d94660a33 6772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
Jasper_lee 0:b16d94660a33 6773 /* CNTIN Bit Fields */
Jasper_lee 0:b16d94660a33 6774 #define FTM_CNTIN_INIT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 6775 #define FTM_CNTIN_INIT_SHIFT 0
Jasper_lee 0:b16d94660a33 6776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
Jasper_lee 0:b16d94660a33 6777 /* STATUS Bit Fields */
Jasper_lee 0:b16d94660a33 6778 #define FTM_STATUS_CH0F_MASK 0x1u
Jasper_lee 0:b16d94660a33 6779 #define FTM_STATUS_CH0F_SHIFT 0
Jasper_lee 0:b16d94660a33 6780 #define FTM_STATUS_CH1F_MASK 0x2u
Jasper_lee 0:b16d94660a33 6781 #define FTM_STATUS_CH1F_SHIFT 1
Jasper_lee 0:b16d94660a33 6782 #define FTM_STATUS_CH2F_MASK 0x4u
Jasper_lee 0:b16d94660a33 6783 #define FTM_STATUS_CH2F_SHIFT 2
Jasper_lee 0:b16d94660a33 6784 #define FTM_STATUS_CH3F_MASK 0x8u
Jasper_lee 0:b16d94660a33 6785 #define FTM_STATUS_CH3F_SHIFT 3
Jasper_lee 0:b16d94660a33 6786 #define FTM_STATUS_CH4F_MASK 0x10u
Jasper_lee 0:b16d94660a33 6787 #define FTM_STATUS_CH4F_SHIFT 4
Jasper_lee 0:b16d94660a33 6788 #define FTM_STATUS_CH5F_MASK 0x20u
Jasper_lee 0:b16d94660a33 6789 #define FTM_STATUS_CH5F_SHIFT 5
Jasper_lee 0:b16d94660a33 6790 #define FTM_STATUS_CH6F_MASK 0x40u
Jasper_lee 0:b16d94660a33 6791 #define FTM_STATUS_CH6F_SHIFT 6
Jasper_lee 0:b16d94660a33 6792 #define FTM_STATUS_CH7F_MASK 0x80u
Jasper_lee 0:b16d94660a33 6793 #define FTM_STATUS_CH7F_SHIFT 7
Jasper_lee 0:b16d94660a33 6794 /* MODE Bit Fields */
Jasper_lee 0:b16d94660a33 6795 #define FTM_MODE_FTMEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 6796 #define FTM_MODE_FTMEN_SHIFT 0
Jasper_lee 0:b16d94660a33 6797 #define FTM_MODE_INIT_MASK 0x2u
Jasper_lee 0:b16d94660a33 6798 #define FTM_MODE_INIT_SHIFT 1
Jasper_lee 0:b16d94660a33 6799 #define FTM_MODE_WPDIS_MASK 0x4u
Jasper_lee 0:b16d94660a33 6800 #define FTM_MODE_WPDIS_SHIFT 2
Jasper_lee 0:b16d94660a33 6801 #define FTM_MODE_PWMSYNC_MASK 0x8u
Jasper_lee 0:b16d94660a33 6802 #define FTM_MODE_PWMSYNC_SHIFT 3
Jasper_lee 0:b16d94660a33 6803 #define FTM_MODE_CAPTEST_MASK 0x10u
Jasper_lee 0:b16d94660a33 6804 #define FTM_MODE_CAPTEST_SHIFT 4
Jasper_lee 0:b16d94660a33 6805 #define FTM_MODE_FAULTM_MASK 0x60u
Jasper_lee 0:b16d94660a33 6806 #define FTM_MODE_FAULTM_SHIFT 5
Jasper_lee 0:b16d94660a33 6807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
Jasper_lee 0:b16d94660a33 6808 #define FTM_MODE_FAULTIE_MASK 0x80u
Jasper_lee 0:b16d94660a33 6809 #define FTM_MODE_FAULTIE_SHIFT 7
Jasper_lee 0:b16d94660a33 6810 /* SYNC Bit Fields */
Jasper_lee 0:b16d94660a33 6811 #define FTM_SYNC_CNTMIN_MASK 0x1u
Jasper_lee 0:b16d94660a33 6812 #define FTM_SYNC_CNTMIN_SHIFT 0
Jasper_lee 0:b16d94660a33 6813 #define FTM_SYNC_CNTMAX_MASK 0x2u
Jasper_lee 0:b16d94660a33 6814 #define FTM_SYNC_CNTMAX_SHIFT 1
Jasper_lee 0:b16d94660a33 6815 #define FTM_SYNC_REINIT_MASK 0x4u
Jasper_lee 0:b16d94660a33 6816 #define FTM_SYNC_REINIT_SHIFT 2
Jasper_lee 0:b16d94660a33 6817 #define FTM_SYNC_SYNCHOM_MASK 0x8u
Jasper_lee 0:b16d94660a33 6818 #define FTM_SYNC_SYNCHOM_SHIFT 3
Jasper_lee 0:b16d94660a33 6819 #define FTM_SYNC_TRIG0_MASK 0x10u
Jasper_lee 0:b16d94660a33 6820 #define FTM_SYNC_TRIG0_SHIFT 4
Jasper_lee 0:b16d94660a33 6821 #define FTM_SYNC_TRIG1_MASK 0x20u
Jasper_lee 0:b16d94660a33 6822 #define FTM_SYNC_TRIG1_SHIFT 5
Jasper_lee 0:b16d94660a33 6823 #define FTM_SYNC_TRIG2_MASK 0x40u
Jasper_lee 0:b16d94660a33 6824 #define FTM_SYNC_TRIG2_SHIFT 6
Jasper_lee 0:b16d94660a33 6825 #define FTM_SYNC_SWSYNC_MASK 0x80u
Jasper_lee 0:b16d94660a33 6826 #define FTM_SYNC_SWSYNC_SHIFT 7
Jasper_lee 0:b16d94660a33 6827 /* OUTINIT Bit Fields */
Jasper_lee 0:b16d94660a33 6828 #define FTM_OUTINIT_CH0OI_MASK 0x1u
Jasper_lee 0:b16d94660a33 6829 #define FTM_OUTINIT_CH0OI_SHIFT 0
Jasper_lee 0:b16d94660a33 6830 #define FTM_OUTINIT_CH1OI_MASK 0x2u
Jasper_lee 0:b16d94660a33 6831 #define FTM_OUTINIT_CH1OI_SHIFT 1
Jasper_lee 0:b16d94660a33 6832 #define FTM_OUTINIT_CH2OI_MASK 0x4u
Jasper_lee 0:b16d94660a33 6833 #define FTM_OUTINIT_CH2OI_SHIFT 2
Jasper_lee 0:b16d94660a33 6834 #define FTM_OUTINIT_CH3OI_MASK 0x8u
Jasper_lee 0:b16d94660a33 6835 #define FTM_OUTINIT_CH3OI_SHIFT 3
Jasper_lee 0:b16d94660a33 6836 #define FTM_OUTINIT_CH4OI_MASK 0x10u
Jasper_lee 0:b16d94660a33 6837 #define FTM_OUTINIT_CH4OI_SHIFT 4
Jasper_lee 0:b16d94660a33 6838 #define FTM_OUTINIT_CH5OI_MASK 0x20u
Jasper_lee 0:b16d94660a33 6839 #define FTM_OUTINIT_CH5OI_SHIFT 5
Jasper_lee 0:b16d94660a33 6840 #define FTM_OUTINIT_CH6OI_MASK 0x40u
Jasper_lee 0:b16d94660a33 6841 #define FTM_OUTINIT_CH6OI_SHIFT 6
Jasper_lee 0:b16d94660a33 6842 #define FTM_OUTINIT_CH7OI_MASK 0x80u
Jasper_lee 0:b16d94660a33 6843 #define FTM_OUTINIT_CH7OI_SHIFT 7
Jasper_lee 0:b16d94660a33 6844 /* OUTMASK Bit Fields */
Jasper_lee 0:b16d94660a33 6845 #define FTM_OUTMASK_CH0OM_MASK 0x1u
Jasper_lee 0:b16d94660a33 6846 #define FTM_OUTMASK_CH0OM_SHIFT 0
Jasper_lee 0:b16d94660a33 6847 #define FTM_OUTMASK_CH1OM_MASK 0x2u
Jasper_lee 0:b16d94660a33 6848 #define FTM_OUTMASK_CH1OM_SHIFT 1
Jasper_lee 0:b16d94660a33 6849 #define FTM_OUTMASK_CH2OM_MASK 0x4u
Jasper_lee 0:b16d94660a33 6850 #define FTM_OUTMASK_CH2OM_SHIFT 2
Jasper_lee 0:b16d94660a33 6851 #define FTM_OUTMASK_CH3OM_MASK 0x8u
Jasper_lee 0:b16d94660a33 6852 #define FTM_OUTMASK_CH3OM_SHIFT 3
Jasper_lee 0:b16d94660a33 6853 #define FTM_OUTMASK_CH4OM_MASK 0x10u
Jasper_lee 0:b16d94660a33 6854 #define FTM_OUTMASK_CH4OM_SHIFT 4
Jasper_lee 0:b16d94660a33 6855 #define FTM_OUTMASK_CH5OM_MASK 0x20u
Jasper_lee 0:b16d94660a33 6856 #define FTM_OUTMASK_CH5OM_SHIFT 5
Jasper_lee 0:b16d94660a33 6857 #define FTM_OUTMASK_CH6OM_MASK 0x40u
Jasper_lee 0:b16d94660a33 6858 #define FTM_OUTMASK_CH6OM_SHIFT 6
Jasper_lee 0:b16d94660a33 6859 #define FTM_OUTMASK_CH7OM_MASK 0x80u
Jasper_lee 0:b16d94660a33 6860 #define FTM_OUTMASK_CH7OM_SHIFT 7
Jasper_lee 0:b16d94660a33 6861 /* COMBINE Bit Fields */
Jasper_lee 0:b16d94660a33 6862 #define FTM_COMBINE_COMBINE0_MASK 0x1u
Jasper_lee 0:b16d94660a33 6863 #define FTM_COMBINE_COMBINE0_SHIFT 0
Jasper_lee 0:b16d94660a33 6864 #define FTM_COMBINE_COMP0_MASK 0x2u
Jasper_lee 0:b16d94660a33 6865 #define FTM_COMBINE_COMP0_SHIFT 1
Jasper_lee 0:b16d94660a33 6866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
Jasper_lee 0:b16d94660a33 6867 #define FTM_COMBINE_DECAPEN0_SHIFT 2
Jasper_lee 0:b16d94660a33 6868 #define FTM_COMBINE_DECAP0_MASK 0x8u
Jasper_lee 0:b16d94660a33 6869 #define FTM_COMBINE_DECAP0_SHIFT 3
Jasper_lee 0:b16d94660a33 6870 #define FTM_COMBINE_DTEN0_MASK 0x10u
Jasper_lee 0:b16d94660a33 6871 #define FTM_COMBINE_DTEN0_SHIFT 4
Jasper_lee 0:b16d94660a33 6872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
Jasper_lee 0:b16d94660a33 6873 #define FTM_COMBINE_SYNCEN0_SHIFT 5
Jasper_lee 0:b16d94660a33 6874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
Jasper_lee 0:b16d94660a33 6875 #define FTM_COMBINE_FAULTEN0_SHIFT 6
Jasper_lee 0:b16d94660a33 6876 #define FTM_COMBINE_COMBINE1_MASK 0x100u
Jasper_lee 0:b16d94660a33 6877 #define FTM_COMBINE_COMBINE1_SHIFT 8
Jasper_lee 0:b16d94660a33 6878 #define FTM_COMBINE_COMP1_MASK 0x200u
Jasper_lee 0:b16d94660a33 6879 #define FTM_COMBINE_COMP1_SHIFT 9
Jasper_lee 0:b16d94660a33 6880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
Jasper_lee 0:b16d94660a33 6881 #define FTM_COMBINE_DECAPEN1_SHIFT 10
Jasper_lee 0:b16d94660a33 6882 #define FTM_COMBINE_DECAP1_MASK 0x800u
Jasper_lee 0:b16d94660a33 6883 #define FTM_COMBINE_DECAP1_SHIFT 11
Jasper_lee 0:b16d94660a33 6884 #define FTM_COMBINE_DTEN1_MASK 0x1000u
Jasper_lee 0:b16d94660a33 6885 #define FTM_COMBINE_DTEN1_SHIFT 12
Jasper_lee 0:b16d94660a33 6886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
Jasper_lee 0:b16d94660a33 6887 #define FTM_COMBINE_SYNCEN1_SHIFT 13
Jasper_lee 0:b16d94660a33 6888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
Jasper_lee 0:b16d94660a33 6889 #define FTM_COMBINE_FAULTEN1_SHIFT 14
Jasper_lee 0:b16d94660a33 6890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
Jasper_lee 0:b16d94660a33 6891 #define FTM_COMBINE_COMBINE2_SHIFT 16
Jasper_lee 0:b16d94660a33 6892 #define FTM_COMBINE_COMP2_MASK 0x20000u
Jasper_lee 0:b16d94660a33 6893 #define FTM_COMBINE_COMP2_SHIFT 17
Jasper_lee 0:b16d94660a33 6894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
Jasper_lee 0:b16d94660a33 6895 #define FTM_COMBINE_DECAPEN2_SHIFT 18
Jasper_lee 0:b16d94660a33 6896 #define FTM_COMBINE_DECAP2_MASK 0x80000u
Jasper_lee 0:b16d94660a33 6897 #define FTM_COMBINE_DECAP2_SHIFT 19
Jasper_lee 0:b16d94660a33 6898 #define FTM_COMBINE_DTEN2_MASK 0x100000u
Jasper_lee 0:b16d94660a33 6899 #define FTM_COMBINE_DTEN2_SHIFT 20
Jasper_lee 0:b16d94660a33 6900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
Jasper_lee 0:b16d94660a33 6901 #define FTM_COMBINE_SYNCEN2_SHIFT 21
Jasper_lee 0:b16d94660a33 6902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
Jasper_lee 0:b16d94660a33 6903 #define FTM_COMBINE_FAULTEN2_SHIFT 22
Jasper_lee 0:b16d94660a33 6904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 6905 #define FTM_COMBINE_COMBINE3_SHIFT 24
Jasper_lee 0:b16d94660a33 6906 #define FTM_COMBINE_COMP3_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 6907 #define FTM_COMBINE_COMP3_SHIFT 25
Jasper_lee 0:b16d94660a33 6908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 6909 #define FTM_COMBINE_DECAPEN3_SHIFT 26
Jasper_lee 0:b16d94660a33 6910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 6911 #define FTM_COMBINE_DECAP3_SHIFT 27
Jasper_lee 0:b16d94660a33 6912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 6913 #define FTM_COMBINE_DTEN3_SHIFT 28
Jasper_lee 0:b16d94660a33 6914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 6915 #define FTM_COMBINE_SYNCEN3_SHIFT 29
Jasper_lee 0:b16d94660a33 6916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 6917 #define FTM_COMBINE_FAULTEN3_SHIFT 30
Jasper_lee 0:b16d94660a33 6918 /* DEADTIME Bit Fields */
Jasper_lee 0:b16d94660a33 6919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 6920 #define FTM_DEADTIME_DTVAL_SHIFT 0
Jasper_lee 0:b16d94660a33 6921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
Jasper_lee 0:b16d94660a33 6922 #define FTM_DEADTIME_DTPS_MASK 0xC0u
Jasper_lee 0:b16d94660a33 6923 #define FTM_DEADTIME_DTPS_SHIFT 6
Jasper_lee 0:b16d94660a33 6924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
Jasper_lee 0:b16d94660a33 6925 /* EXTTRIG Bit Fields */
Jasper_lee 0:b16d94660a33 6926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
Jasper_lee 0:b16d94660a33 6927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
Jasper_lee 0:b16d94660a33 6928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
Jasper_lee 0:b16d94660a33 6929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
Jasper_lee 0:b16d94660a33 6930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
Jasper_lee 0:b16d94660a33 6931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
Jasper_lee 0:b16d94660a33 6932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
Jasper_lee 0:b16d94660a33 6933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
Jasper_lee 0:b16d94660a33 6934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
Jasper_lee 0:b16d94660a33 6935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
Jasper_lee 0:b16d94660a33 6936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
Jasper_lee 0:b16d94660a33 6937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
Jasper_lee 0:b16d94660a33 6938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 6939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
Jasper_lee 0:b16d94660a33 6940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
Jasper_lee 0:b16d94660a33 6941 #define FTM_EXTTRIG_TRIGF_SHIFT 7
Jasper_lee 0:b16d94660a33 6942 /* POL Bit Fields */
Jasper_lee 0:b16d94660a33 6943 #define FTM_POL_POL0_MASK 0x1u
Jasper_lee 0:b16d94660a33 6944 #define FTM_POL_POL0_SHIFT 0
Jasper_lee 0:b16d94660a33 6945 #define FTM_POL_POL1_MASK 0x2u
Jasper_lee 0:b16d94660a33 6946 #define FTM_POL_POL1_SHIFT 1
Jasper_lee 0:b16d94660a33 6947 #define FTM_POL_POL2_MASK 0x4u
Jasper_lee 0:b16d94660a33 6948 #define FTM_POL_POL2_SHIFT 2
Jasper_lee 0:b16d94660a33 6949 #define FTM_POL_POL3_MASK 0x8u
Jasper_lee 0:b16d94660a33 6950 #define FTM_POL_POL3_SHIFT 3
Jasper_lee 0:b16d94660a33 6951 #define FTM_POL_POL4_MASK 0x10u
Jasper_lee 0:b16d94660a33 6952 #define FTM_POL_POL4_SHIFT 4
Jasper_lee 0:b16d94660a33 6953 #define FTM_POL_POL5_MASK 0x20u
Jasper_lee 0:b16d94660a33 6954 #define FTM_POL_POL5_SHIFT 5
Jasper_lee 0:b16d94660a33 6955 #define FTM_POL_POL6_MASK 0x40u
Jasper_lee 0:b16d94660a33 6956 #define FTM_POL_POL6_SHIFT 6
Jasper_lee 0:b16d94660a33 6957 #define FTM_POL_POL7_MASK 0x80u
Jasper_lee 0:b16d94660a33 6958 #define FTM_POL_POL7_SHIFT 7
Jasper_lee 0:b16d94660a33 6959 /* FMS Bit Fields */
Jasper_lee 0:b16d94660a33 6960 #define FTM_FMS_FAULTF0_MASK 0x1u
Jasper_lee 0:b16d94660a33 6961 #define FTM_FMS_FAULTF0_SHIFT 0
Jasper_lee 0:b16d94660a33 6962 #define FTM_FMS_FAULTF1_MASK 0x2u
Jasper_lee 0:b16d94660a33 6963 #define FTM_FMS_FAULTF1_SHIFT 1
Jasper_lee 0:b16d94660a33 6964 #define FTM_FMS_FAULTF2_MASK 0x4u
Jasper_lee 0:b16d94660a33 6965 #define FTM_FMS_FAULTF2_SHIFT 2
Jasper_lee 0:b16d94660a33 6966 #define FTM_FMS_FAULTF3_MASK 0x8u
Jasper_lee 0:b16d94660a33 6967 #define FTM_FMS_FAULTF3_SHIFT 3
Jasper_lee 0:b16d94660a33 6968 #define FTM_FMS_FAULTIN_MASK 0x20u
Jasper_lee 0:b16d94660a33 6969 #define FTM_FMS_FAULTIN_SHIFT 5
Jasper_lee 0:b16d94660a33 6970 #define FTM_FMS_WPEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 6971 #define FTM_FMS_WPEN_SHIFT 6
Jasper_lee 0:b16d94660a33 6972 #define FTM_FMS_FAULTF_MASK 0x80u
Jasper_lee 0:b16d94660a33 6973 #define FTM_FMS_FAULTF_SHIFT 7
Jasper_lee 0:b16d94660a33 6974 /* FILTER Bit Fields */
Jasper_lee 0:b16d94660a33 6975 #define FTM_FILTER_CH0FVAL_MASK 0xFu
Jasper_lee 0:b16d94660a33 6976 #define FTM_FILTER_CH0FVAL_SHIFT 0
Jasper_lee 0:b16d94660a33 6977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
Jasper_lee 0:b16d94660a33 6978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
Jasper_lee 0:b16d94660a33 6979 #define FTM_FILTER_CH1FVAL_SHIFT 4
Jasper_lee 0:b16d94660a33 6980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
Jasper_lee 0:b16d94660a33 6981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
Jasper_lee 0:b16d94660a33 6982 #define FTM_FILTER_CH2FVAL_SHIFT 8
Jasper_lee 0:b16d94660a33 6983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
Jasper_lee 0:b16d94660a33 6984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
Jasper_lee 0:b16d94660a33 6985 #define FTM_FILTER_CH3FVAL_SHIFT 12
Jasper_lee 0:b16d94660a33 6986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
Jasper_lee 0:b16d94660a33 6987 /* FLTCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 6988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
Jasper_lee 0:b16d94660a33 6989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
Jasper_lee 0:b16d94660a33 6990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
Jasper_lee 0:b16d94660a33 6991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
Jasper_lee 0:b16d94660a33 6992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
Jasper_lee 0:b16d94660a33 6993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
Jasper_lee 0:b16d94660a33 6994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
Jasper_lee 0:b16d94660a33 6995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
Jasper_lee 0:b16d94660a33 6996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
Jasper_lee 0:b16d94660a33 6997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
Jasper_lee 0:b16d94660a33 6998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
Jasper_lee 0:b16d94660a33 6999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
Jasper_lee 0:b16d94660a33 7000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
Jasper_lee 0:b16d94660a33 7001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
Jasper_lee 0:b16d94660a33 7002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
Jasper_lee 0:b16d94660a33 7003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
Jasper_lee 0:b16d94660a33 7004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
Jasper_lee 0:b16d94660a33 7005 #define FTM_FLTCTRL_FFVAL_SHIFT 8
Jasper_lee 0:b16d94660a33 7006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
Jasper_lee 0:b16d94660a33 7007 /* QDCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 7008 #define FTM_QDCTRL_QUADEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 7009 #define FTM_QDCTRL_QUADEN_SHIFT 0
Jasper_lee 0:b16d94660a33 7010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
Jasper_lee 0:b16d94660a33 7011 #define FTM_QDCTRL_TOFDIR_SHIFT 1
Jasper_lee 0:b16d94660a33 7012 #define FTM_QDCTRL_QUADIR_MASK 0x4u
Jasper_lee 0:b16d94660a33 7013 #define FTM_QDCTRL_QUADIR_SHIFT 2
Jasper_lee 0:b16d94660a33 7014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
Jasper_lee 0:b16d94660a33 7015 #define FTM_QDCTRL_QUADMODE_SHIFT 3
Jasper_lee 0:b16d94660a33 7016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
Jasper_lee 0:b16d94660a33 7017 #define FTM_QDCTRL_PHBPOL_SHIFT 4
Jasper_lee 0:b16d94660a33 7018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
Jasper_lee 0:b16d94660a33 7019 #define FTM_QDCTRL_PHAPOL_SHIFT 5
Jasper_lee 0:b16d94660a33 7020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
Jasper_lee 0:b16d94660a33 7021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
Jasper_lee 0:b16d94660a33 7022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
Jasper_lee 0:b16d94660a33 7023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
Jasper_lee 0:b16d94660a33 7024 /* CONF Bit Fields */
Jasper_lee 0:b16d94660a33 7025 #define FTM_CONF_NUMTOF_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 7026 #define FTM_CONF_NUMTOF_SHIFT 0
Jasper_lee 0:b16d94660a33 7027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
Jasper_lee 0:b16d94660a33 7028 #define FTM_CONF_BDMMODE_MASK 0xC0u
Jasper_lee 0:b16d94660a33 7029 #define FTM_CONF_BDMMODE_SHIFT 6
Jasper_lee 0:b16d94660a33 7030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
Jasper_lee 0:b16d94660a33 7031 #define FTM_CONF_GTBEEN_MASK 0x200u
Jasper_lee 0:b16d94660a33 7032 #define FTM_CONF_GTBEEN_SHIFT 9
Jasper_lee 0:b16d94660a33 7033 #define FTM_CONF_GTBEOUT_MASK 0x400u
Jasper_lee 0:b16d94660a33 7034 #define FTM_CONF_GTBEOUT_SHIFT 10
Jasper_lee 0:b16d94660a33 7035 /* FLTPOL Bit Fields */
Jasper_lee 0:b16d94660a33 7036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
Jasper_lee 0:b16d94660a33 7037 #define FTM_FLTPOL_FLT0POL_SHIFT 0
Jasper_lee 0:b16d94660a33 7038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
Jasper_lee 0:b16d94660a33 7039 #define FTM_FLTPOL_FLT1POL_SHIFT 1
Jasper_lee 0:b16d94660a33 7040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
Jasper_lee 0:b16d94660a33 7041 #define FTM_FLTPOL_FLT2POL_SHIFT 2
Jasper_lee 0:b16d94660a33 7042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
Jasper_lee 0:b16d94660a33 7043 #define FTM_FLTPOL_FLT3POL_SHIFT 3
Jasper_lee 0:b16d94660a33 7044 /* SYNCONF Bit Fields */
Jasper_lee 0:b16d94660a33 7045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
Jasper_lee 0:b16d94660a33 7046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
Jasper_lee 0:b16d94660a33 7047 #define FTM_SYNCONF_CNTINC_MASK 0x4u
Jasper_lee 0:b16d94660a33 7048 #define FTM_SYNCONF_CNTINC_SHIFT 2
Jasper_lee 0:b16d94660a33 7049 #define FTM_SYNCONF_INVC_MASK 0x10u
Jasper_lee 0:b16d94660a33 7050 #define FTM_SYNCONF_INVC_SHIFT 4
Jasper_lee 0:b16d94660a33 7051 #define FTM_SYNCONF_SWOC_MASK 0x20u
Jasper_lee 0:b16d94660a33 7052 #define FTM_SYNCONF_SWOC_SHIFT 5
Jasper_lee 0:b16d94660a33 7053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
Jasper_lee 0:b16d94660a33 7054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
Jasper_lee 0:b16d94660a33 7055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
Jasper_lee 0:b16d94660a33 7056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
Jasper_lee 0:b16d94660a33 7057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
Jasper_lee 0:b16d94660a33 7058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
Jasper_lee 0:b16d94660a33 7059 #define FTM_SYNCONF_SWOM_MASK 0x400u
Jasper_lee 0:b16d94660a33 7060 #define FTM_SYNCONF_SWOM_SHIFT 10
Jasper_lee 0:b16d94660a33 7061 #define FTM_SYNCONF_SWINVC_MASK 0x800u
Jasper_lee 0:b16d94660a33 7062 #define FTM_SYNCONF_SWINVC_SHIFT 11
Jasper_lee 0:b16d94660a33 7063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
Jasper_lee 0:b16d94660a33 7064 #define FTM_SYNCONF_SWSOC_SHIFT 12
Jasper_lee 0:b16d94660a33 7065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
Jasper_lee 0:b16d94660a33 7066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
Jasper_lee 0:b16d94660a33 7067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
Jasper_lee 0:b16d94660a33 7068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
Jasper_lee 0:b16d94660a33 7069 #define FTM_SYNCONF_HWOM_MASK 0x40000u
Jasper_lee 0:b16d94660a33 7070 #define FTM_SYNCONF_HWOM_SHIFT 18
Jasper_lee 0:b16d94660a33 7071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
Jasper_lee 0:b16d94660a33 7072 #define FTM_SYNCONF_HWINVC_SHIFT 19
Jasper_lee 0:b16d94660a33 7073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
Jasper_lee 0:b16d94660a33 7074 #define FTM_SYNCONF_HWSOC_SHIFT 20
Jasper_lee 0:b16d94660a33 7075 /* INVCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 7076 #define FTM_INVCTRL_INV0EN_MASK 0x1u
Jasper_lee 0:b16d94660a33 7077 #define FTM_INVCTRL_INV0EN_SHIFT 0
Jasper_lee 0:b16d94660a33 7078 #define FTM_INVCTRL_INV1EN_MASK 0x2u
Jasper_lee 0:b16d94660a33 7079 #define FTM_INVCTRL_INV1EN_SHIFT 1
Jasper_lee 0:b16d94660a33 7080 #define FTM_INVCTRL_INV2EN_MASK 0x4u
Jasper_lee 0:b16d94660a33 7081 #define FTM_INVCTRL_INV2EN_SHIFT 2
Jasper_lee 0:b16d94660a33 7082 #define FTM_INVCTRL_INV3EN_MASK 0x8u
Jasper_lee 0:b16d94660a33 7083 #define FTM_INVCTRL_INV3EN_SHIFT 3
Jasper_lee 0:b16d94660a33 7084 /* SWOCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 7085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
Jasper_lee 0:b16d94660a33 7086 #define FTM_SWOCTRL_CH0OC_SHIFT 0
Jasper_lee 0:b16d94660a33 7087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
Jasper_lee 0:b16d94660a33 7088 #define FTM_SWOCTRL_CH1OC_SHIFT 1
Jasper_lee 0:b16d94660a33 7089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
Jasper_lee 0:b16d94660a33 7090 #define FTM_SWOCTRL_CH2OC_SHIFT 2
Jasper_lee 0:b16d94660a33 7091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
Jasper_lee 0:b16d94660a33 7092 #define FTM_SWOCTRL_CH3OC_SHIFT 3
Jasper_lee 0:b16d94660a33 7093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
Jasper_lee 0:b16d94660a33 7094 #define FTM_SWOCTRL_CH4OC_SHIFT 4
Jasper_lee 0:b16d94660a33 7095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
Jasper_lee 0:b16d94660a33 7096 #define FTM_SWOCTRL_CH5OC_SHIFT 5
Jasper_lee 0:b16d94660a33 7097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
Jasper_lee 0:b16d94660a33 7098 #define FTM_SWOCTRL_CH6OC_SHIFT 6
Jasper_lee 0:b16d94660a33 7099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
Jasper_lee 0:b16d94660a33 7100 #define FTM_SWOCTRL_CH7OC_SHIFT 7
Jasper_lee 0:b16d94660a33 7101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
Jasper_lee 0:b16d94660a33 7102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
Jasper_lee 0:b16d94660a33 7103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
Jasper_lee 0:b16d94660a33 7104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
Jasper_lee 0:b16d94660a33 7105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
Jasper_lee 0:b16d94660a33 7106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
Jasper_lee 0:b16d94660a33 7107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
Jasper_lee 0:b16d94660a33 7108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
Jasper_lee 0:b16d94660a33 7109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
Jasper_lee 0:b16d94660a33 7110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
Jasper_lee 0:b16d94660a33 7111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
Jasper_lee 0:b16d94660a33 7112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
Jasper_lee 0:b16d94660a33 7113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
Jasper_lee 0:b16d94660a33 7114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
Jasper_lee 0:b16d94660a33 7115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
Jasper_lee 0:b16d94660a33 7116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
Jasper_lee 0:b16d94660a33 7117 /* PWMLOAD Bit Fields */
Jasper_lee 0:b16d94660a33 7118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
Jasper_lee 0:b16d94660a33 7119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
Jasper_lee 0:b16d94660a33 7120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
Jasper_lee 0:b16d94660a33 7121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
Jasper_lee 0:b16d94660a33 7122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
Jasper_lee 0:b16d94660a33 7123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
Jasper_lee 0:b16d94660a33 7124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
Jasper_lee 0:b16d94660a33 7125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
Jasper_lee 0:b16d94660a33 7126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 7127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
Jasper_lee 0:b16d94660a33 7128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
Jasper_lee 0:b16d94660a33 7129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
Jasper_lee 0:b16d94660a33 7130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
Jasper_lee 0:b16d94660a33 7131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
Jasper_lee 0:b16d94660a33 7132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
Jasper_lee 0:b16d94660a33 7133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
Jasper_lee 0:b16d94660a33 7134 #define FTM_PWMLOAD_LDOK_MASK 0x200u
Jasper_lee 0:b16d94660a33 7135 #define FTM_PWMLOAD_LDOK_SHIFT 9
Jasper_lee 0:b16d94660a33 7136
Jasper_lee 0:b16d94660a33 7137 /*!
Jasper_lee 0:b16d94660a33 7138 * @}
Jasper_lee 0:b16d94660a33 7139 */ /* end of group FTM_Register_Masks */
Jasper_lee 0:b16d94660a33 7140
Jasper_lee 0:b16d94660a33 7141
Jasper_lee 0:b16d94660a33 7142 /* FTM - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 7143 /** Peripheral FTM0 base address */
Jasper_lee 0:b16d94660a33 7144 #define FTM0_BASE (0x40038000u)
Jasper_lee 0:b16d94660a33 7145 /** Peripheral FTM0 base pointer */
Jasper_lee 0:b16d94660a33 7146 #define FTM0 ((FTM_Type *)FTM0_BASE)
Jasper_lee 0:b16d94660a33 7147 #define FTM0_BASE_PTR (FTM0)
Jasper_lee 0:b16d94660a33 7148 /** Peripheral FTM1 base address */
Jasper_lee 0:b16d94660a33 7149 #define FTM1_BASE (0x40039000u)
Jasper_lee 0:b16d94660a33 7150 /** Peripheral FTM1 base pointer */
Jasper_lee 0:b16d94660a33 7151 #define FTM1 ((FTM_Type *)FTM1_BASE)
Jasper_lee 0:b16d94660a33 7152 #define FTM1_BASE_PTR (FTM1)
Jasper_lee 0:b16d94660a33 7153 /** Peripheral FTM2 base address */
Jasper_lee 0:b16d94660a33 7154 #define FTM2_BASE (0x4003A000u)
Jasper_lee 0:b16d94660a33 7155 /** Peripheral FTM2 base pointer */
Jasper_lee 0:b16d94660a33 7156 #define FTM2 ((FTM_Type *)FTM2_BASE)
Jasper_lee 0:b16d94660a33 7157 #define FTM2_BASE_PTR (FTM2)
Jasper_lee 0:b16d94660a33 7158 /** Peripheral FTM3 base address */
Jasper_lee 0:b16d94660a33 7159 #define FTM3_BASE (0x400B9000u)
Jasper_lee 0:b16d94660a33 7160 /** Peripheral FTM3 base pointer */
Jasper_lee 0:b16d94660a33 7161 #define FTM3 ((FTM_Type *)FTM3_BASE)
Jasper_lee 0:b16d94660a33 7162 #define FTM3_BASE_PTR (FTM3)
Jasper_lee 0:b16d94660a33 7163 /** Array initializer of FTM peripheral base addresses */
Jasper_lee 0:b16d94660a33 7164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
Jasper_lee 0:b16d94660a33 7165 /** Array initializer of FTM peripheral base pointers */
Jasper_lee 0:b16d94660a33 7166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
Jasper_lee 0:b16d94660a33 7167 /** Interrupt vectors for the FTM peripheral type */
Jasper_lee 0:b16d94660a33 7168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
Jasper_lee 0:b16d94660a33 7169
Jasper_lee 0:b16d94660a33 7170 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7171 -- FTM - Register accessor macros
Jasper_lee 0:b16d94660a33 7172 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7173
Jasper_lee 0:b16d94660a33 7174 /*!
Jasper_lee 0:b16d94660a33 7175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
Jasper_lee 0:b16d94660a33 7176 * @{
Jasper_lee 0:b16d94660a33 7177 */
Jasper_lee 0:b16d94660a33 7178
Jasper_lee 0:b16d94660a33 7179
Jasper_lee 0:b16d94660a33 7180 /* FTM - Register instance definitions */
Jasper_lee 0:b16d94660a33 7181 /* FTM0 */
Jasper_lee 0:b16d94660a33 7182 #define FTM0_SC FTM_SC_REG(FTM0)
Jasper_lee 0:b16d94660a33 7183 #define FTM0_CNT FTM_CNT_REG(FTM0)
Jasper_lee 0:b16d94660a33 7184 #define FTM0_MOD FTM_MOD_REG(FTM0)
Jasper_lee 0:b16d94660a33 7185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
Jasper_lee 0:b16d94660a33 7186 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
Jasper_lee 0:b16d94660a33 7187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
Jasper_lee 0:b16d94660a33 7188 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
Jasper_lee 0:b16d94660a33 7189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
Jasper_lee 0:b16d94660a33 7190 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
Jasper_lee 0:b16d94660a33 7191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
Jasper_lee 0:b16d94660a33 7192 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
Jasper_lee 0:b16d94660a33 7193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
Jasper_lee 0:b16d94660a33 7194 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
Jasper_lee 0:b16d94660a33 7195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
Jasper_lee 0:b16d94660a33 7196 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
Jasper_lee 0:b16d94660a33 7197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
Jasper_lee 0:b16d94660a33 7198 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
Jasper_lee 0:b16d94660a33 7199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
Jasper_lee 0:b16d94660a33 7200 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
Jasper_lee 0:b16d94660a33 7201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
Jasper_lee 0:b16d94660a33 7202 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
Jasper_lee 0:b16d94660a33 7203 #define FTM0_MODE FTM_MODE_REG(FTM0)
Jasper_lee 0:b16d94660a33 7204 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
Jasper_lee 0:b16d94660a33 7205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
Jasper_lee 0:b16d94660a33 7206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
Jasper_lee 0:b16d94660a33 7207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
Jasper_lee 0:b16d94660a33 7208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
Jasper_lee 0:b16d94660a33 7209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
Jasper_lee 0:b16d94660a33 7210 #define FTM0_POL FTM_POL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7211 #define FTM0_FMS FTM_FMS_REG(FTM0)
Jasper_lee 0:b16d94660a33 7212 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
Jasper_lee 0:b16d94660a33 7213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7215 #define FTM0_CONF FTM_CONF_REG(FTM0)
Jasper_lee 0:b16d94660a33 7216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
Jasper_lee 0:b16d94660a33 7218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
Jasper_lee 0:b16d94660a33 7220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
Jasper_lee 0:b16d94660a33 7221 /* FTM1 */
Jasper_lee 0:b16d94660a33 7222 #define FTM1_SC FTM_SC_REG(FTM1)
Jasper_lee 0:b16d94660a33 7223 #define FTM1_CNT FTM_CNT_REG(FTM1)
Jasper_lee 0:b16d94660a33 7224 #define FTM1_MOD FTM_MOD_REG(FTM1)
Jasper_lee 0:b16d94660a33 7225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
Jasper_lee 0:b16d94660a33 7226 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
Jasper_lee 0:b16d94660a33 7227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
Jasper_lee 0:b16d94660a33 7228 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
Jasper_lee 0:b16d94660a33 7229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
Jasper_lee 0:b16d94660a33 7230 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
Jasper_lee 0:b16d94660a33 7231 #define FTM1_MODE FTM_MODE_REG(FTM1)
Jasper_lee 0:b16d94660a33 7232 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
Jasper_lee 0:b16d94660a33 7233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
Jasper_lee 0:b16d94660a33 7234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
Jasper_lee 0:b16d94660a33 7235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
Jasper_lee 0:b16d94660a33 7236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
Jasper_lee 0:b16d94660a33 7237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
Jasper_lee 0:b16d94660a33 7238 #define FTM1_POL FTM_POL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7239 #define FTM1_FMS FTM_FMS_REG(FTM1)
Jasper_lee 0:b16d94660a33 7240 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
Jasper_lee 0:b16d94660a33 7241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7243 #define FTM1_CONF FTM_CONF_REG(FTM1)
Jasper_lee 0:b16d94660a33 7244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
Jasper_lee 0:b16d94660a33 7246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
Jasper_lee 0:b16d94660a33 7248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
Jasper_lee 0:b16d94660a33 7249 /* FTM2 */
Jasper_lee 0:b16d94660a33 7250 #define FTM2_SC FTM_SC_REG(FTM2)
Jasper_lee 0:b16d94660a33 7251 #define FTM2_CNT FTM_CNT_REG(FTM2)
Jasper_lee 0:b16d94660a33 7252 #define FTM2_MOD FTM_MOD_REG(FTM2)
Jasper_lee 0:b16d94660a33 7253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
Jasper_lee 0:b16d94660a33 7254 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
Jasper_lee 0:b16d94660a33 7255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
Jasper_lee 0:b16d94660a33 7256 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
Jasper_lee 0:b16d94660a33 7257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
Jasper_lee 0:b16d94660a33 7258 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
Jasper_lee 0:b16d94660a33 7259 #define FTM2_MODE FTM_MODE_REG(FTM2)
Jasper_lee 0:b16d94660a33 7260 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
Jasper_lee 0:b16d94660a33 7261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
Jasper_lee 0:b16d94660a33 7262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
Jasper_lee 0:b16d94660a33 7263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
Jasper_lee 0:b16d94660a33 7264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
Jasper_lee 0:b16d94660a33 7265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
Jasper_lee 0:b16d94660a33 7266 #define FTM2_POL FTM_POL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7267 #define FTM2_FMS FTM_FMS_REG(FTM2)
Jasper_lee 0:b16d94660a33 7268 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
Jasper_lee 0:b16d94660a33 7269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7271 #define FTM2_CONF FTM_CONF_REG(FTM2)
Jasper_lee 0:b16d94660a33 7272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
Jasper_lee 0:b16d94660a33 7274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
Jasper_lee 0:b16d94660a33 7276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
Jasper_lee 0:b16d94660a33 7277 /* FTM3 */
Jasper_lee 0:b16d94660a33 7278 #define FTM3_SC FTM_SC_REG(FTM3)
Jasper_lee 0:b16d94660a33 7279 #define FTM3_CNT FTM_CNT_REG(FTM3)
Jasper_lee 0:b16d94660a33 7280 #define FTM3_MOD FTM_MOD_REG(FTM3)
Jasper_lee 0:b16d94660a33 7281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
Jasper_lee 0:b16d94660a33 7282 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
Jasper_lee 0:b16d94660a33 7283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
Jasper_lee 0:b16d94660a33 7284 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
Jasper_lee 0:b16d94660a33 7285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
Jasper_lee 0:b16d94660a33 7286 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
Jasper_lee 0:b16d94660a33 7287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
Jasper_lee 0:b16d94660a33 7288 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
Jasper_lee 0:b16d94660a33 7289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
Jasper_lee 0:b16d94660a33 7290 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
Jasper_lee 0:b16d94660a33 7291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
Jasper_lee 0:b16d94660a33 7292 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
Jasper_lee 0:b16d94660a33 7293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
Jasper_lee 0:b16d94660a33 7294 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
Jasper_lee 0:b16d94660a33 7295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
Jasper_lee 0:b16d94660a33 7296 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
Jasper_lee 0:b16d94660a33 7297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
Jasper_lee 0:b16d94660a33 7298 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
Jasper_lee 0:b16d94660a33 7299 #define FTM3_MODE FTM_MODE_REG(FTM3)
Jasper_lee 0:b16d94660a33 7300 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
Jasper_lee 0:b16d94660a33 7301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
Jasper_lee 0:b16d94660a33 7302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
Jasper_lee 0:b16d94660a33 7303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
Jasper_lee 0:b16d94660a33 7304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
Jasper_lee 0:b16d94660a33 7305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
Jasper_lee 0:b16d94660a33 7306 #define FTM3_POL FTM_POL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7307 #define FTM3_FMS FTM_FMS_REG(FTM3)
Jasper_lee 0:b16d94660a33 7308 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
Jasper_lee 0:b16d94660a33 7309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7311 #define FTM3_CONF FTM_CONF_REG(FTM3)
Jasper_lee 0:b16d94660a33 7312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
Jasper_lee 0:b16d94660a33 7314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
Jasper_lee 0:b16d94660a33 7316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
Jasper_lee 0:b16d94660a33 7317
Jasper_lee 0:b16d94660a33 7318 /* FTM - Register array accessors */
Jasper_lee 0:b16d94660a33 7319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
Jasper_lee 0:b16d94660a33 7320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
Jasper_lee 0:b16d94660a33 7321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
Jasper_lee 0:b16d94660a33 7322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
Jasper_lee 0:b16d94660a33 7323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
Jasper_lee 0:b16d94660a33 7324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
Jasper_lee 0:b16d94660a33 7325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
Jasper_lee 0:b16d94660a33 7326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
Jasper_lee 0:b16d94660a33 7327
Jasper_lee 0:b16d94660a33 7328 /*!
Jasper_lee 0:b16d94660a33 7329 * @}
Jasper_lee 0:b16d94660a33 7330 */ /* end of group FTM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7331
Jasper_lee 0:b16d94660a33 7332
Jasper_lee 0:b16d94660a33 7333 /*!
Jasper_lee 0:b16d94660a33 7334 * @}
Jasper_lee 0:b16d94660a33 7335 */ /* end of group FTM_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 7336
Jasper_lee 0:b16d94660a33 7337
Jasper_lee 0:b16d94660a33 7338 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7339 -- GPIO Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7340 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7341
Jasper_lee 0:b16d94660a33 7342 /*!
Jasper_lee 0:b16d94660a33 7343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7344 * @{
Jasper_lee 0:b16d94660a33 7345 */
Jasper_lee 0:b16d94660a33 7346
Jasper_lee 0:b16d94660a33 7347 /** GPIO - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 7348 typedef struct {
Jasper_lee 0:b16d94660a33 7349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 7350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 7351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 7352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 7353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 7354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 7355 } GPIO_Type, *GPIO_MemMapPtr;
Jasper_lee 0:b16d94660a33 7356
Jasper_lee 0:b16d94660a33 7357 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7358 -- GPIO - Register accessor macros
Jasper_lee 0:b16d94660a33 7359 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7360
Jasper_lee 0:b16d94660a33 7361 /*!
Jasper_lee 0:b16d94660a33 7362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Jasper_lee 0:b16d94660a33 7363 * @{
Jasper_lee 0:b16d94660a33 7364 */
Jasper_lee 0:b16d94660a33 7365
Jasper_lee 0:b16d94660a33 7366
Jasper_lee 0:b16d94660a33 7367 /* GPIO - Register accessors */
Jasper_lee 0:b16d94660a33 7368 #define GPIO_PDOR_REG(base) ((base)->PDOR)
Jasper_lee 0:b16d94660a33 7369 #define GPIO_PSOR_REG(base) ((base)->PSOR)
Jasper_lee 0:b16d94660a33 7370 #define GPIO_PCOR_REG(base) ((base)->PCOR)
Jasper_lee 0:b16d94660a33 7371 #define GPIO_PTOR_REG(base) ((base)->PTOR)
Jasper_lee 0:b16d94660a33 7372 #define GPIO_PDIR_REG(base) ((base)->PDIR)
Jasper_lee 0:b16d94660a33 7373 #define GPIO_PDDR_REG(base) ((base)->PDDR)
Jasper_lee 0:b16d94660a33 7374
Jasper_lee 0:b16d94660a33 7375 /*!
Jasper_lee 0:b16d94660a33 7376 * @}
Jasper_lee 0:b16d94660a33 7377 */ /* end of group GPIO_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7378
Jasper_lee 0:b16d94660a33 7379
Jasper_lee 0:b16d94660a33 7380 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7381 -- GPIO Register Masks
Jasper_lee 0:b16d94660a33 7382 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7383
Jasper_lee 0:b16d94660a33 7384 /*!
Jasper_lee 0:b16d94660a33 7385 * @addtogroup GPIO_Register_Masks GPIO Register Masks
Jasper_lee 0:b16d94660a33 7386 * @{
Jasper_lee 0:b16d94660a33 7387 */
Jasper_lee 0:b16d94660a33 7388
Jasper_lee 0:b16d94660a33 7389 /* PDOR Bit Fields */
Jasper_lee 0:b16d94660a33 7390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7391 #define GPIO_PDOR_PDO_SHIFT 0
Jasper_lee 0:b16d94660a33 7392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
Jasper_lee 0:b16d94660a33 7393 /* PSOR Bit Fields */
Jasper_lee 0:b16d94660a33 7394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7395 #define GPIO_PSOR_PTSO_SHIFT 0
Jasper_lee 0:b16d94660a33 7396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
Jasper_lee 0:b16d94660a33 7397 /* PCOR Bit Fields */
Jasper_lee 0:b16d94660a33 7398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7399 #define GPIO_PCOR_PTCO_SHIFT 0
Jasper_lee 0:b16d94660a33 7400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
Jasper_lee 0:b16d94660a33 7401 /* PTOR Bit Fields */
Jasper_lee 0:b16d94660a33 7402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7403 #define GPIO_PTOR_PTTO_SHIFT 0
Jasper_lee 0:b16d94660a33 7404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
Jasper_lee 0:b16d94660a33 7405 /* PDIR Bit Fields */
Jasper_lee 0:b16d94660a33 7406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7407 #define GPIO_PDIR_PDI_SHIFT 0
Jasper_lee 0:b16d94660a33 7408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
Jasper_lee 0:b16d94660a33 7409 /* PDDR Bit Fields */
Jasper_lee 0:b16d94660a33 7410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7411 #define GPIO_PDDR_PDD_SHIFT 0
Jasper_lee 0:b16d94660a33 7412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
Jasper_lee 0:b16d94660a33 7413
Jasper_lee 0:b16d94660a33 7414 /*!
Jasper_lee 0:b16d94660a33 7415 * @}
Jasper_lee 0:b16d94660a33 7416 */ /* end of group GPIO_Register_Masks */
Jasper_lee 0:b16d94660a33 7417
Jasper_lee 0:b16d94660a33 7418
Jasper_lee 0:b16d94660a33 7419 /* GPIO - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 7420 /** Peripheral PTA base address */
Jasper_lee 0:b16d94660a33 7421 #define PTA_BASE (0x400FF000u)
Jasper_lee 0:b16d94660a33 7422 /** Peripheral PTA base pointer */
Jasper_lee 0:b16d94660a33 7423 #define PTA ((GPIO_Type *)PTA_BASE)
Jasper_lee 0:b16d94660a33 7424 #define PTA_BASE_PTR (PTA)
Jasper_lee 0:b16d94660a33 7425 /** Peripheral PTB base address */
Jasper_lee 0:b16d94660a33 7426 #define PTB_BASE (0x400FF040u)
Jasper_lee 0:b16d94660a33 7427 /** Peripheral PTB base pointer */
Jasper_lee 0:b16d94660a33 7428 #define PTB ((GPIO_Type *)PTB_BASE)
Jasper_lee 0:b16d94660a33 7429 #define PTB_BASE_PTR (PTB)
Jasper_lee 0:b16d94660a33 7430 /** Peripheral PTC base address */
Jasper_lee 0:b16d94660a33 7431 #define PTC_BASE (0x400FF080u)
Jasper_lee 0:b16d94660a33 7432 /** Peripheral PTC base pointer */
Jasper_lee 0:b16d94660a33 7433 #define PTC ((GPIO_Type *)PTC_BASE)
Jasper_lee 0:b16d94660a33 7434 #define PTC_BASE_PTR (PTC)
Jasper_lee 0:b16d94660a33 7435 /** Peripheral PTD base address */
Jasper_lee 0:b16d94660a33 7436 #define PTD_BASE (0x400FF0C0u)
Jasper_lee 0:b16d94660a33 7437 /** Peripheral PTD base pointer */
Jasper_lee 0:b16d94660a33 7438 #define PTD ((GPIO_Type *)PTD_BASE)
Jasper_lee 0:b16d94660a33 7439 #define PTD_BASE_PTR (PTD)
Jasper_lee 0:b16d94660a33 7440 /** Peripheral PTE base address */
Jasper_lee 0:b16d94660a33 7441 #define PTE_BASE (0x400FF100u)
Jasper_lee 0:b16d94660a33 7442 /** Peripheral PTE base pointer */
Jasper_lee 0:b16d94660a33 7443 #define PTE ((GPIO_Type *)PTE_BASE)
Jasper_lee 0:b16d94660a33 7444 #define PTE_BASE_PTR (PTE)
Jasper_lee 0:b16d94660a33 7445 /** Array initializer of GPIO peripheral base addresses */
Jasper_lee 0:b16d94660a33 7446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
Jasper_lee 0:b16d94660a33 7447 /** Array initializer of GPIO peripheral base pointers */
Jasper_lee 0:b16d94660a33 7448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
Jasper_lee 0:b16d94660a33 7449
Jasper_lee 0:b16d94660a33 7450 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7451 -- GPIO - Register accessor macros
Jasper_lee 0:b16d94660a33 7452 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7453
Jasper_lee 0:b16d94660a33 7454 /*!
Jasper_lee 0:b16d94660a33 7455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Jasper_lee 0:b16d94660a33 7456 * @{
Jasper_lee 0:b16d94660a33 7457 */
Jasper_lee 0:b16d94660a33 7458
Jasper_lee 0:b16d94660a33 7459
Jasper_lee 0:b16d94660a33 7460 /* GPIO - Register instance definitions */
Jasper_lee 0:b16d94660a33 7461 /* PTA */
Jasper_lee 0:b16d94660a33 7462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
Jasper_lee 0:b16d94660a33 7463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
Jasper_lee 0:b16d94660a33 7464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
Jasper_lee 0:b16d94660a33 7465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
Jasper_lee 0:b16d94660a33 7466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
Jasper_lee 0:b16d94660a33 7467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
Jasper_lee 0:b16d94660a33 7468 /* PTB */
Jasper_lee 0:b16d94660a33 7469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
Jasper_lee 0:b16d94660a33 7470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
Jasper_lee 0:b16d94660a33 7471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
Jasper_lee 0:b16d94660a33 7472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
Jasper_lee 0:b16d94660a33 7473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
Jasper_lee 0:b16d94660a33 7474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
Jasper_lee 0:b16d94660a33 7475 /* PTC */
Jasper_lee 0:b16d94660a33 7476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
Jasper_lee 0:b16d94660a33 7477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
Jasper_lee 0:b16d94660a33 7478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
Jasper_lee 0:b16d94660a33 7479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
Jasper_lee 0:b16d94660a33 7480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
Jasper_lee 0:b16d94660a33 7481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
Jasper_lee 0:b16d94660a33 7482 /* PTD */
Jasper_lee 0:b16d94660a33 7483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
Jasper_lee 0:b16d94660a33 7484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
Jasper_lee 0:b16d94660a33 7485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
Jasper_lee 0:b16d94660a33 7486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
Jasper_lee 0:b16d94660a33 7487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
Jasper_lee 0:b16d94660a33 7488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
Jasper_lee 0:b16d94660a33 7489 /* PTE */
Jasper_lee 0:b16d94660a33 7490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
Jasper_lee 0:b16d94660a33 7491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
Jasper_lee 0:b16d94660a33 7492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
Jasper_lee 0:b16d94660a33 7493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
Jasper_lee 0:b16d94660a33 7494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
Jasper_lee 0:b16d94660a33 7495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
Jasper_lee 0:b16d94660a33 7496
Jasper_lee 0:b16d94660a33 7497 /*!
Jasper_lee 0:b16d94660a33 7498 * @}
Jasper_lee 0:b16d94660a33 7499 */ /* end of group GPIO_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7500
Jasper_lee 0:b16d94660a33 7501
Jasper_lee 0:b16d94660a33 7502 /*!
Jasper_lee 0:b16d94660a33 7503 * @}
Jasper_lee 0:b16d94660a33 7504 */ /* end of group GPIO_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 7505
Jasper_lee 0:b16d94660a33 7506
Jasper_lee 0:b16d94660a33 7507 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7508 -- I2C Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7509 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7510
Jasper_lee 0:b16d94660a33 7511 /*!
Jasper_lee 0:b16d94660a33 7512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7513 * @{
Jasper_lee 0:b16d94660a33 7514 */
Jasper_lee 0:b16d94660a33 7515
Jasper_lee 0:b16d94660a33 7516 /** I2C - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 7517 typedef struct {
Jasper_lee 0:b16d94660a33 7518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
Jasper_lee 0:b16d94660a33 7519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 7520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
Jasper_lee 0:b16d94660a33 7521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 7522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 7523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
Jasper_lee 0:b16d94660a33 7524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
Jasper_lee 0:b16d94660a33 7525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
Jasper_lee 0:b16d94660a33 7526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 7527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
Jasper_lee 0:b16d94660a33 7528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
Jasper_lee 0:b16d94660a33 7529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
Jasper_lee 0:b16d94660a33 7530 } I2C_Type, *I2C_MemMapPtr;
Jasper_lee 0:b16d94660a33 7531
Jasper_lee 0:b16d94660a33 7532 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7533 -- I2C - Register accessor macros
Jasper_lee 0:b16d94660a33 7534 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7535
Jasper_lee 0:b16d94660a33 7536 /*!
Jasper_lee 0:b16d94660a33 7537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Jasper_lee 0:b16d94660a33 7538 * @{
Jasper_lee 0:b16d94660a33 7539 */
Jasper_lee 0:b16d94660a33 7540
Jasper_lee 0:b16d94660a33 7541
Jasper_lee 0:b16d94660a33 7542 /* I2C - Register accessors */
Jasper_lee 0:b16d94660a33 7543 #define I2C_A1_REG(base) ((base)->A1)
Jasper_lee 0:b16d94660a33 7544 #define I2C_F_REG(base) ((base)->F)
Jasper_lee 0:b16d94660a33 7545 #define I2C_C1_REG(base) ((base)->C1)
Jasper_lee 0:b16d94660a33 7546 #define I2C_S_REG(base) ((base)->S)
Jasper_lee 0:b16d94660a33 7547 #define I2C_D_REG(base) ((base)->D)
Jasper_lee 0:b16d94660a33 7548 #define I2C_C2_REG(base) ((base)->C2)
Jasper_lee 0:b16d94660a33 7549 #define I2C_FLT_REG(base) ((base)->FLT)
Jasper_lee 0:b16d94660a33 7550 #define I2C_RA_REG(base) ((base)->RA)
Jasper_lee 0:b16d94660a33 7551 #define I2C_SMB_REG(base) ((base)->SMB)
Jasper_lee 0:b16d94660a33 7552 #define I2C_A2_REG(base) ((base)->A2)
Jasper_lee 0:b16d94660a33 7553 #define I2C_SLTH_REG(base) ((base)->SLTH)
Jasper_lee 0:b16d94660a33 7554 #define I2C_SLTL_REG(base) ((base)->SLTL)
Jasper_lee 0:b16d94660a33 7555
Jasper_lee 0:b16d94660a33 7556 /*!
Jasper_lee 0:b16d94660a33 7557 * @}
Jasper_lee 0:b16d94660a33 7558 */ /* end of group I2C_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7559
Jasper_lee 0:b16d94660a33 7560
Jasper_lee 0:b16d94660a33 7561 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7562 -- I2C Register Masks
Jasper_lee 0:b16d94660a33 7563 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7564
Jasper_lee 0:b16d94660a33 7565 /*!
Jasper_lee 0:b16d94660a33 7566 * @addtogroup I2C_Register_Masks I2C Register Masks
Jasper_lee 0:b16d94660a33 7567 * @{
Jasper_lee 0:b16d94660a33 7568 */
Jasper_lee 0:b16d94660a33 7569
Jasper_lee 0:b16d94660a33 7570 /* A1 Bit Fields */
Jasper_lee 0:b16d94660a33 7571 #define I2C_A1_AD_MASK 0xFEu
Jasper_lee 0:b16d94660a33 7572 #define I2C_A1_AD_SHIFT 1
Jasper_lee 0:b16d94660a33 7573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
Jasper_lee 0:b16d94660a33 7574 /* F Bit Fields */
Jasper_lee 0:b16d94660a33 7575 #define I2C_F_ICR_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 7576 #define I2C_F_ICR_SHIFT 0
Jasper_lee 0:b16d94660a33 7577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
Jasper_lee 0:b16d94660a33 7578 #define I2C_F_MULT_MASK 0xC0u
Jasper_lee 0:b16d94660a33 7579 #define I2C_F_MULT_SHIFT 6
Jasper_lee 0:b16d94660a33 7580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
Jasper_lee 0:b16d94660a33 7581 /* C1 Bit Fields */
Jasper_lee 0:b16d94660a33 7582 #define I2C_C1_DMAEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 7583 #define I2C_C1_DMAEN_SHIFT 0
Jasper_lee 0:b16d94660a33 7584 #define I2C_C1_WUEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 7585 #define I2C_C1_WUEN_SHIFT 1
Jasper_lee 0:b16d94660a33 7586 #define I2C_C1_RSTA_MASK 0x4u
Jasper_lee 0:b16d94660a33 7587 #define I2C_C1_RSTA_SHIFT 2
Jasper_lee 0:b16d94660a33 7588 #define I2C_C1_TXAK_MASK 0x8u
Jasper_lee 0:b16d94660a33 7589 #define I2C_C1_TXAK_SHIFT 3
Jasper_lee 0:b16d94660a33 7590 #define I2C_C1_TX_MASK 0x10u
Jasper_lee 0:b16d94660a33 7591 #define I2C_C1_TX_SHIFT 4
Jasper_lee 0:b16d94660a33 7592 #define I2C_C1_MST_MASK 0x20u
Jasper_lee 0:b16d94660a33 7593 #define I2C_C1_MST_SHIFT 5
Jasper_lee 0:b16d94660a33 7594 #define I2C_C1_IICIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 7595 #define I2C_C1_IICIE_SHIFT 6
Jasper_lee 0:b16d94660a33 7596 #define I2C_C1_IICEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 7597 #define I2C_C1_IICEN_SHIFT 7
Jasper_lee 0:b16d94660a33 7598 /* S Bit Fields */
Jasper_lee 0:b16d94660a33 7599 #define I2C_S_RXAK_MASK 0x1u
Jasper_lee 0:b16d94660a33 7600 #define I2C_S_RXAK_SHIFT 0
Jasper_lee 0:b16d94660a33 7601 #define I2C_S_IICIF_MASK 0x2u
Jasper_lee 0:b16d94660a33 7602 #define I2C_S_IICIF_SHIFT 1
Jasper_lee 0:b16d94660a33 7603 #define I2C_S_SRW_MASK 0x4u
Jasper_lee 0:b16d94660a33 7604 #define I2C_S_SRW_SHIFT 2
Jasper_lee 0:b16d94660a33 7605 #define I2C_S_RAM_MASK 0x8u
Jasper_lee 0:b16d94660a33 7606 #define I2C_S_RAM_SHIFT 3
Jasper_lee 0:b16d94660a33 7607 #define I2C_S_ARBL_MASK 0x10u
Jasper_lee 0:b16d94660a33 7608 #define I2C_S_ARBL_SHIFT 4
Jasper_lee 0:b16d94660a33 7609 #define I2C_S_BUSY_MASK 0x20u
Jasper_lee 0:b16d94660a33 7610 #define I2C_S_BUSY_SHIFT 5
Jasper_lee 0:b16d94660a33 7611 #define I2C_S_IAAS_MASK 0x40u
Jasper_lee 0:b16d94660a33 7612 #define I2C_S_IAAS_SHIFT 6
Jasper_lee 0:b16d94660a33 7613 #define I2C_S_TCF_MASK 0x80u
Jasper_lee 0:b16d94660a33 7614 #define I2C_S_TCF_SHIFT 7
Jasper_lee 0:b16d94660a33 7615 /* D Bit Fields */
Jasper_lee 0:b16d94660a33 7616 #define I2C_D_DATA_MASK 0xFFu
Jasper_lee 0:b16d94660a33 7617 #define I2C_D_DATA_SHIFT 0
Jasper_lee 0:b16d94660a33 7618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
Jasper_lee 0:b16d94660a33 7619 /* C2 Bit Fields */
Jasper_lee 0:b16d94660a33 7620 #define I2C_C2_AD_MASK 0x7u
Jasper_lee 0:b16d94660a33 7621 #define I2C_C2_AD_SHIFT 0
Jasper_lee 0:b16d94660a33 7622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
Jasper_lee 0:b16d94660a33 7623 #define I2C_C2_RMEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 7624 #define I2C_C2_RMEN_SHIFT 3
Jasper_lee 0:b16d94660a33 7625 #define I2C_C2_SBRC_MASK 0x10u
Jasper_lee 0:b16d94660a33 7626 #define I2C_C2_SBRC_SHIFT 4
Jasper_lee 0:b16d94660a33 7627 #define I2C_C2_HDRS_MASK 0x20u
Jasper_lee 0:b16d94660a33 7628 #define I2C_C2_HDRS_SHIFT 5
Jasper_lee 0:b16d94660a33 7629 #define I2C_C2_ADEXT_MASK 0x40u
Jasper_lee 0:b16d94660a33 7630 #define I2C_C2_ADEXT_SHIFT 6
Jasper_lee 0:b16d94660a33 7631 #define I2C_C2_GCAEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 7632 #define I2C_C2_GCAEN_SHIFT 7
Jasper_lee 0:b16d94660a33 7633 /* FLT Bit Fields */
Jasper_lee 0:b16d94660a33 7634 #define I2C_FLT_FLT_MASK 0xFu
Jasper_lee 0:b16d94660a33 7635 #define I2C_FLT_FLT_SHIFT 0
Jasper_lee 0:b16d94660a33 7636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
Jasper_lee 0:b16d94660a33 7637 #define I2C_FLT_STARTF_MASK 0x10u
Jasper_lee 0:b16d94660a33 7638 #define I2C_FLT_STARTF_SHIFT 4
Jasper_lee 0:b16d94660a33 7639 #define I2C_FLT_SSIE_MASK 0x20u
Jasper_lee 0:b16d94660a33 7640 #define I2C_FLT_SSIE_SHIFT 5
Jasper_lee 0:b16d94660a33 7641 #define I2C_FLT_STOPF_MASK 0x40u
Jasper_lee 0:b16d94660a33 7642 #define I2C_FLT_STOPF_SHIFT 6
Jasper_lee 0:b16d94660a33 7643 #define I2C_FLT_SHEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 7644 #define I2C_FLT_SHEN_SHIFT 7
Jasper_lee 0:b16d94660a33 7645 /* RA Bit Fields */
Jasper_lee 0:b16d94660a33 7646 #define I2C_RA_RAD_MASK 0xFEu
Jasper_lee 0:b16d94660a33 7647 #define I2C_RA_RAD_SHIFT 1
Jasper_lee 0:b16d94660a33 7648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
Jasper_lee 0:b16d94660a33 7649 /* SMB Bit Fields */
Jasper_lee 0:b16d94660a33 7650 #define I2C_SMB_SHTF2IE_MASK 0x1u
Jasper_lee 0:b16d94660a33 7651 #define I2C_SMB_SHTF2IE_SHIFT 0
Jasper_lee 0:b16d94660a33 7652 #define I2C_SMB_SHTF2_MASK 0x2u
Jasper_lee 0:b16d94660a33 7653 #define I2C_SMB_SHTF2_SHIFT 1
Jasper_lee 0:b16d94660a33 7654 #define I2C_SMB_SHTF1_MASK 0x4u
Jasper_lee 0:b16d94660a33 7655 #define I2C_SMB_SHTF1_SHIFT 2
Jasper_lee 0:b16d94660a33 7656 #define I2C_SMB_SLTF_MASK 0x8u
Jasper_lee 0:b16d94660a33 7657 #define I2C_SMB_SLTF_SHIFT 3
Jasper_lee 0:b16d94660a33 7658 #define I2C_SMB_TCKSEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 7659 #define I2C_SMB_TCKSEL_SHIFT 4
Jasper_lee 0:b16d94660a33 7660 #define I2C_SMB_SIICAEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 7661 #define I2C_SMB_SIICAEN_SHIFT 5
Jasper_lee 0:b16d94660a33 7662 #define I2C_SMB_ALERTEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 7663 #define I2C_SMB_ALERTEN_SHIFT 6
Jasper_lee 0:b16d94660a33 7664 #define I2C_SMB_FACK_MASK 0x80u
Jasper_lee 0:b16d94660a33 7665 #define I2C_SMB_FACK_SHIFT 7
Jasper_lee 0:b16d94660a33 7666 /* A2 Bit Fields */
Jasper_lee 0:b16d94660a33 7667 #define I2C_A2_SAD_MASK 0xFEu
Jasper_lee 0:b16d94660a33 7668 #define I2C_A2_SAD_SHIFT 1
Jasper_lee 0:b16d94660a33 7669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
Jasper_lee 0:b16d94660a33 7670 /* SLTH Bit Fields */
Jasper_lee 0:b16d94660a33 7671 #define I2C_SLTH_SSLT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 7672 #define I2C_SLTH_SSLT_SHIFT 0
Jasper_lee 0:b16d94660a33 7673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
Jasper_lee 0:b16d94660a33 7674 /* SLTL Bit Fields */
Jasper_lee 0:b16d94660a33 7675 #define I2C_SLTL_SSLT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 7676 #define I2C_SLTL_SSLT_SHIFT 0
Jasper_lee 0:b16d94660a33 7677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
Jasper_lee 0:b16d94660a33 7678
Jasper_lee 0:b16d94660a33 7679 /*!
Jasper_lee 0:b16d94660a33 7680 * @}
Jasper_lee 0:b16d94660a33 7681 */ /* end of group I2C_Register_Masks */
Jasper_lee 0:b16d94660a33 7682
Jasper_lee 0:b16d94660a33 7683
Jasper_lee 0:b16d94660a33 7684 /* I2C - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 7685 /** Peripheral I2C0 base address */
Jasper_lee 0:b16d94660a33 7686 #define I2C0_BASE (0x40066000u)
Jasper_lee 0:b16d94660a33 7687 /** Peripheral I2C0 base pointer */
Jasper_lee 0:b16d94660a33 7688 #define I2C0 ((I2C_Type *)I2C0_BASE)
Jasper_lee 0:b16d94660a33 7689 #define I2C0_BASE_PTR (I2C0)
Jasper_lee 0:b16d94660a33 7690 /** Peripheral I2C1 base address */
Jasper_lee 0:b16d94660a33 7691 #define I2C1_BASE (0x40067000u)
Jasper_lee 0:b16d94660a33 7692 /** Peripheral I2C1 base pointer */
Jasper_lee 0:b16d94660a33 7693 #define I2C1 ((I2C_Type *)I2C1_BASE)
Jasper_lee 0:b16d94660a33 7694 #define I2C1_BASE_PTR (I2C1)
Jasper_lee 0:b16d94660a33 7695 /** Peripheral I2C2 base address */
Jasper_lee 0:b16d94660a33 7696 #define I2C2_BASE (0x400E6000u)
Jasper_lee 0:b16d94660a33 7697 /** Peripheral I2C2 base pointer */
Jasper_lee 0:b16d94660a33 7698 #define I2C2 ((I2C_Type *)I2C2_BASE)
Jasper_lee 0:b16d94660a33 7699 #define I2C2_BASE_PTR (I2C2)
Jasper_lee 0:b16d94660a33 7700 /** Array initializer of I2C peripheral base addresses */
Jasper_lee 0:b16d94660a33 7701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
Jasper_lee 0:b16d94660a33 7702 /** Array initializer of I2C peripheral base pointers */
Jasper_lee 0:b16d94660a33 7703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
Jasper_lee 0:b16d94660a33 7704 /** Interrupt vectors for the I2C peripheral type */
Jasper_lee 0:b16d94660a33 7705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
Jasper_lee 0:b16d94660a33 7706
Jasper_lee 0:b16d94660a33 7707 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7708 -- I2C - Register accessor macros
Jasper_lee 0:b16d94660a33 7709 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7710
Jasper_lee 0:b16d94660a33 7711 /*!
Jasper_lee 0:b16d94660a33 7712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Jasper_lee 0:b16d94660a33 7713 * @{
Jasper_lee 0:b16d94660a33 7714 */
Jasper_lee 0:b16d94660a33 7715
Jasper_lee 0:b16d94660a33 7716
Jasper_lee 0:b16d94660a33 7717 /* I2C - Register instance definitions */
Jasper_lee 0:b16d94660a33 7718 /* I2C0 */
Jasper_lee 0:b16d94660a33 7719 #define I2C0_A1 I2C_A1_REG(I2C0)
Jasper_lee 0:b16d94660a33 7720 #define I2C0_F I2C_F_REG(I2C0)
Jasper_lee 0:b16d94660a33 7721 #define I2C0_C1 I2C_C1_REG(I2C0)
Jasper_lee 0:b16d94660a33 7722 #define I2C0_S I2C_S_REG(I2C0)
Jasper_lee 0:b16d94660a33 7723 #define I2C0_D I2C_D_REG(I2C0)
Jasper_lee 0:b16d94660a33 7724 #define I2C0_C2 I2C_C2_REG(I2C0)
Jasper_lee 0:b16d94660a33 7725 #define I2C0_FLT I2C_FLT_REG(I2C0)
Jasper_lee 0:b16d94660a33 7726 #define I2C0_RA I2C_RA_REG(I2C0)
Jasper_lee 0:b16d94660a33 7727 #define I2C0_SMB I2C_SMB_REG(I2C0)
Jasper_lee 0:b16d94660a33 7728 #define I2C0_A2 I2C_A2_REG(I2C0)
Jasper_lee 0:b16d94660a33 7729 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
Jasper_lee 0:b16d94660a33 7730 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
Jasper_lee 0:b16d94660a33 7731 /* I2C1 */
Jasper_lee 0:b16d94660a33 7732 #define I2C1_A1 I2C_A1_REG(I2C1)
Jasper_lee 0:b16d94660a33 7733 #define I2C1_F I2C_F_REG(I2C1)
Jasper_lee 0:b16d94660a33 7734 #define I2C1_C1 I2C_C1_REG(I2C1)
Jasper_lee 0:b16d94660a33 7735 #define I2C1_S I2C_S_REG(I2C1)
Jasper_lee 0:b16d94660a33 7736 #define I2C1_D I2C_D_REG(I2C1)
Jasper_lee 0:b16d94660a33 7737 #define I2C1_C2 I2C_C2_REG(I2C1)
Jasper_lee 0:b16d94660a33 7738 #define I2C1_FLT I2C_FLT_REG(I2C1)
Jasper_lee 0:b16d94660a33 7739 #define I2C1_RA I2C_RA_REG(I2C1)
Jasper_lee 0:b16d94660a33 7740 #define I2C1_SMB I2C_SMB_REG(I2C1)
Jasper_lee 0:b16d94660a33 7741 #define I2C1_A2 I2C_A2_REG(I2C1)
Jasper_lee 0:b16d94660a33 7742 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
Jasper_lee 0:b16d94660a33 7743 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
Jasper_lee 0:b16d94660a33 7744 /* I2C2 */
Jasper_lee 0:b16d94660a33 7745 #define I2C2_A1 I2C_A1_REG(I2C2)
Jasper_lee 0:b16d94660a33 7746 #define I2C2_F I2C_F_REG(I2C2)
Jasper_lee 0:b16d94660a33 7747 #define I2C2_C1 I2C_C1_REG(I2C2)
Jasper_lee 0:b16d94660a33 7748 #define I2C2_S I2C_S_REG(I2C2)
Jasper_lee 0:b16d94660a33 7749 #define I2C2_D I2C_D_REG(I2C2)
Jasper_lee 0:b16d94660a33 7750 #define I2C2_C2 I2C_C2_REG(I2C2)
Jasper_lee 0:b16d94660a33 7751 #define I2C2_FLT I2C_FLT_REG(I2C2)
Jasper_lee 0:b16d94660a33 7752 #define I2C2_RA I2C_RA_REG(I2C2)
Jasper_lee 0:b16d94660a33 7753 #define I2C2_SMB I2C_SMB_REG(I2C2)
Jasper_lee 0:b16d94660a33 7754 #define I2C2_A2 I2C_A2_REG(I2C2)
Jasper_lee 0:b16d94660a33 7755 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
Jasper_lee 0:b16d94660a33 7756 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
Jasper_lee 0:b16d94660a33 7757
Jasper_lee 0:b16d94660a33 7758 /*!
Jasper_lee 0:b16d94660a33 7759 * @}
Jasper_lee 0:b16d94660a33 7760 */ /* end of group I2C_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7761
Jasper_lee 0:b16d94660a33 7762
Jasper_lee 0:b16d94660a33 7763 /*!
Jasper_lee 0:b16d94660a33 7764 * @}
Jasper_lee 0:b16d94660a33 7765 */ /* end of group I2C_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 7766
Jasper_lee 0:b16d94660a33 7767
Jasper_lee 0:b16d94660a33 7768 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7769 -- I2S Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7770 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7771
Jasper_lee 0:b16d94660a33 7772 /*!
Jasper_lee 0:b16d94660a33 7773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Jasper_lee 0:b16d94660a33 7774 * @{
Jasper_lee 0:b16d94660a33 7775 */
Jasper_lee 0:b16d94660a33 7776
Jasper_lee 0:b16d94660a33 7777 /** I2S - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 7778 typedef struct {
Jasper_lee 0:b16d94660a33 7779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 7780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 7781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 7782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 7783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 7784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 7785 uint8_t RESERVED_0[8];
Jasper_lee 0:b16d94660a33 7786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
Jasper_lee 0:b16d94660a33 7787 uint8_t RESERVED_1[24];
Jasper_lee 0:b16d94660a33 7788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
Jasper_lee 0:b16d94660a33 7789 uint8_t RESERVED_2[24];
Jasper_lee 0:b16d94660a33 7790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
Jasper_lee 0:b16d94660a33 7791 uint8_t RESERVED_3[28];
Jasper_lee 0:b16d94660a33 7792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
Jasper_lee 0:b16d94660a33 7793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
Jasper_lee 0:b16d94660a33 7794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
Jasper_lee 0:b16d94660a33 7795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
Jasper_lee 0:b16d94660a33 7796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
Jasper_lee 0:b16d94660a33 7797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
Jasper_lee 0:b16d94660a33 7798 uint8_t RESERVED_4[8];
Jasper_lee 0:b16d94660a33 7799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 7800 uint8_t RESERVED_5[24];
Jasper_lee 0:b16d94660a33 7801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 7802 uint8_t RESERVED_6[24];
Jasper_lee 0:b16d94660a33 7803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
Jasper_lee 0:b16d94660a33 7804 uint8_t RESERVED_7[28];
Jasper_lee 0:b16d94660a33 7805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
Jasper_lee 0:b16d94660a33 7806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
Jasper_lee 0:b16d94660a33 7807 } I2S_Type, *I2S_MemMapPtr;
Jasper_lee 0:b16d94660a33 7808
Jasper_lee 0:b16d94660a33 7809 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7810 -- I2S - Register accessor macros
Jasper_lee 0:b16d94660a33 7811 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7812
Jasper_lee 0:b16d94660a33 7813 /*!
Jasper_lee 0:b16d94660a33 7814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Jasper_lee 0:b16d94660a33 7815 * @{
Jasper_lee 0:b16d94660a33 7816 */
Jasper_lee 0:b16d94660a33 7817
Jasper_lee 0:b16d94660a33 7818
Jasper_lee 0:b16d94660a33 7819 /* I2S - Register accessors */
Jasper_lee 0:b16d94660a33 7820 #define I2S_TCSR_REG(base) ((base)->TCSR)
Jasper_lee 0:b16d94660a33 7821 #define I2S_TCR1_REG(base) ((base)->TCR1)
Jasper_lee 0:b16d94660a33 7822 #define I2S_TCR2_REG(base) ((base)->TCR2)
Jasper_lee 0:b16d94660a33 7823 #define I2S_TCR3_REG(base) ((base)->TCR3)
Jasper_lee 0:b16d94660a33 7824 #define I2S_TCR4_REG(base) ((base)->TCR4)
Jasper_lee 0:b16d94660a33 7825 #define I2S_TCR5_REG(base) ((base)->TCR5)
Jasper_lee 0:b16d94660a33 7826 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
Jasper_lee 0:b16d94660a33 7827 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
Jasper_lee 0:b16d94660a33 7828 #define I2S_TMR_REG(base) ((base)->TMR)
Jasper_lee 0:b16d94660a33 7829 #define I2S_RCSR_REG(base) ((base)->RCSR)
Jasper_lee 0:b16d94660a33 7830 #define I2S_RCR1_REG(base) ((base)->RCR1)
Jasper_lee 0:b16d94660a33 7831 #define I2S_RCR2_REG(base) ((base)->RCR2)
Jasper_lee 0:b16d94660a33 7832 #define I2S_RCR3_REG(base) ((base)->RCR3)
Jasper_lee 0:b16d94660a33 7833 #define I2S_RCR4_REG(base) ((base)->RCR4)
Jasper_lee 0:b16d94660a33 7834 #define I2S_RCR5_REG(base) ((base)->RCR5)
Jasper_lee 0:b16d94660a33 7835 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
Jasper_lee 0:b16d94660a33 7836 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
Jasper_lee 0:b16d94660a33 7837 #define I2S_RMR_REG(base) ((base)->RMR)
Jasper_lee 0:b16d94660a33 7838 #define I2S_MCR_REG(base) ((base)->MCR)
Jasper_lee 0:b16d94660a33 7839 #define I2S_MDR_REG(base) ((base)->MDR)
Jasper_lee 0:b16d94660a33 7840
Jasper_lee 0:b16d94660a33 7841 /*!
Jasper_lee 0:b16d94660a33 7842 * @}
Jasper_lee 0:b16d94660a33 7843 */ /* end of group I2S_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 7844
Jasper_lee 0:b16d94660a33 7845
Jasper_lee 0:b16d94660a33 7846 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 7847 -- I2S Register Masks
Jasper_lee 0:b16d94660a33 7848 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 7849
Jasper_lee 0:b16d94660a33 7850 /*!
Jasper_lee 0:b16d94660a33 7851 * @addtogroup I2S_Register_Masks I2S Register Masks
Jasper_lee 0:b16d94660a33 7852 * @{
Jasper_lee 0:b16d94660a33 7853 */
Jasper_lee 0:b16d94660a33 7854
Jasper_lee 0:b16d94660a33 7855 /* TCSR Bit Fields */
Jasper_lee 0:b16d94660a33 7856 #define I2S_TCSR_FRDE_MASK 0x1u
Jasper_lee 0:b16d94660a33 7857 #define I2S_TCSR_FRDE_SHIFT 0
Jasper_lee 0:b16d94660a33 7858 #define I2S_TCSR_FWDE_MASK 0x2u
Jasper_lee 0:b16d94660a33 7859 #define I2S_TCSR_FWDE_SHIFT 1
Jasper_lee 0:b16d94660a33 7860 #define I2S_TCSR_FRIE_MASK 0x100u
Jasper_lee 0:b16d94660a33 7861 #define I2S_TCSR_FRIE_SHIFT 8
Jasper_lee 0:b16d94660a33 7862 #define I2S_TCSR_FWIE_MASK 0x200u
Jasper_lee 0:b16d94660a33 7863 #define I2S_TCSR_FWIE_SHIFT 9
Jasper_lee 0:b16d94660a33 7864 #define I2S_TCSR_FEIE_MASK 0x400u
Jasper_lee 0:b16d94660a33 7865 #define I2S_TCSR_FEIE_SHIFT 10
Jasper_lee 0:b16d94660a33 7866 #define I2S_TCSR_SEIE_MASK 0x800u
Jasper_lee 0:b16d94660a33 7867 #define I2S_TCSR_SEIE_SHIFT 11
Jasper_lee 0:b16d94660a33 7868 #define I2S_TCSR_WSIE_MASK 0x1000u
Jasper_lee 0:b16d94660a33 7869 #define I2S_TCSR_WSIE_SHIFT 12
Jasper_lee 0:b16d94660a33 7870 #define I2S_TCSR_FRF_MASK 0x10000u
Jasper_lee 0:b16d94660a33 7871 #define I2S_TCSR_FRF_SHIFT 16
Jasper_lee 0:b16d94660a33 7872 #define I2S_TCSR_FWF_MASK 0x20000u
Jasper_lee 0:b16d94660a33 7873 #define I2S_TCSR_FWF_SHIFT 17
Jasper_lee 0:b16d94660a33 7874 #define I2S_TCSR_FEF_MASK 0x40000u
Jasper_lee 0:b16d94660a33 7875 #define I2S_TCSR_FEF_SHIFT 18
Jasper_lee 0:b16d94660a33 7876 #define I2S_TCSR_SEF_MASK 0x80000u
Jasper_lee 0:b16d94660a33 7877 #define I2S_TCSR_SEF_SHIFT 19
Jasper_lee 0:b16d94660a33 7878 #define I2S_TCSR_WSF_MASK 0x100000u
Jasper_lee 0:b16d94660a33 7879 #define I2S_TCSR_WSF_SHIFT 20
Jasper_lee 0:b16d94660a33 7880 #define I2S_TCSR_SR_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 7881 #define I2S_TCSR_SR_SHIFT 24
Jasper_lee 0:b16d94660a33 7882 #define I2S_TCSR_FR_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 7883 #define I2S_TCSR_FR_SHIFT 25
Jasper_lee 0:b16d94660a33 7884 #define I2S_TCSR_BCE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 7885 #define I2S_TCSR_BCE_SHIFT 28
Jasper_lee 0:b16d94660a33 7886 #define I2S_TCSR_DBGE_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 7887 #define I2S_TCSR_DBGE_SHIFT 29
Jasper_lee 0:b16d94660a33 7888 #define I2S_TCSR_STOPE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 7889 #define I2S_TCSR_STOPE_SHIFT 30
Jasper_lee 0:b16d94660a33 7890 #define I2S_TCSR_TE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 7891 #define I2S_TCSR_TE_SHIFT 31
Jasper_lee 0:b16d94660a33 7892 /* TCR1 Bit Fields */
Jasper_lee 0:b16d94660a33 7893 #define I2S_TCR1_TFW_MASK 0x7u
Jasper_lee 0:b16d94660a33 7894 #define I2S_TCR1_TFW_SHIFT 0
Jasper_lee 0:b16d94660a33 7895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
Jasper_lee 0:b16d94660a33 7896 /* TCR2 Bit Fields */
Jasper_lee 0:b16d94660a33 7897 #define I2S_TCR2_DIV_MASK 0xFFu
Jasper_lee 0:b16d94660a33 7898 #define I2S_TCR2_DIV_SHIFT 0
Jasper_lee 0:b16d94660a33 7899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
Jasper_lee 0:b16d94660a33 7900 #define I2S_TCR2_BCD_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 7901 #define I2S_TCR2_BCD_SHIFT 24
Jasper_lee 0:b16d94660a33 7902 #define I2S_TCR2_BCP_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 7903 #define I2S_TCR2_BCP_SHIFT 25
Jasper_lee 0:b16d94660a33 7904 #define I2S_TCR2_MSEL_MASK 0xC000000u
Jasper_lee 0:b16d94660a33 7905 #define I2S_TCR2_MSEL_SHIFT 26
Jasper_lee 0:b16d94660a33 7906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
Jasper_lee 0:b16d94660a33 7907 #define I2S_TCR2_BCI_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 7908 #define I2S_TCR2_BCI_SHIFT 28
Jasper_lee 0:b16d94660a33 7909 #define I2S_TCR2_BCS_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 7910 #define I2S_TCR2_BCS_SHIFT 29
Jasper_lee 0:b16d94660a33 7911 #define I2S_TCR2_SYNC_MASK 0xC0000000u
Jasper_lee 0:b16d94660a33 7912 #define I2S_TCR2_SYNC_SHIFT 30
Jasper_lee 0:b16d94660a33 7913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
Jasper_lee 0:b16d94660a33 7914 /* TCR3 Bit Fields */
Jasper_lee 0:b16d94660a33 7915 #define I2S_TCR3_WDFL_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 7916 #define I2S_TCR3_WDFL_SHIFT 0
Jasper_lee 0:b16d94660a33 7917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
Jasper_lee 0:b16d94660a33 7918 #define I2S_TCR3_TCE_MASK 0x30000u
Jasper_lee 0:b16d94660a33 7919 #define I2S_TCR3_TCE_SHIFT 16
Jasper_lee 0:b16d94660a33 7920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
Jasper_lee 0:b16d94660a33 7921 /* TCR4 Bit Fields */
Jasper_lee 0:b16d94660a33 7922 #define I2S_TCR4_FSD_MASK 0x1u
Jasper_lee 0:b16d94660a33 7923 #define I2S_TCR4_FSD_SHIFT 0
Jasper_lee 0:b16d94660a33 7924 #define I2S_TCR4_FSP_MASK 0x2u
Jasper_lee 0:b16d94660a33 7925 #define I2S_TCR4_FSP_SHIFT 1
Jasper_lee 0:b16d94660a33 7926 #define I2S_TCR4_FSE_MASK 0x8u
Jasper_lee 0:b16d94660a33 7927 #define I2S_TCR4_FSE_SHIFT 3
Jasper_lee 0:b16d94660a33 7928 #define I2S_TCR4_MF_MASK 0x10u
Jasper_lee 0:b16d94660a33 7929 #define I2S_TCR4_MF_SHIFT 4
Jasper_lee 0:b16d94660a33 7930 #define I2S_TCR4_SYWD_MASK 0x1F00u
Jasper_lee 0:b16d94660a33 7931 #define I2S_TCR4_SYWD_SHIFT 8
Jasper_lee 0:b16d94660a33 7932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
Jasper_lee 0:b16d94660a33 7933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
Jasper_lee 0:b16d94660a33 7934 #define I2S_TCR4_FRSZ_SHIFT 16
Jasper_lee 0:b16d94660a33 7935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
Jasper_lee 0:b16d94660a33 7936 /* TCR5 Bit Fields */
Jasper_lee 0:b16d94660a33 7937 #define I2S_TCR5_FBT_MASK 0x1F00u
Jasper_lee 0:b16d94660a33 7938 #define I2S_TCR5_FBT_SHIFT 8
Jasper_lee 0:b16d94660a33 7939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
Jasper_lee 0:b16d94660a33 7940 #define I2S_TCR5_W0W_MASK 0x1F0000u
Jasper_lee 0:b16d94660a33 7941 #define I2S_TCR5_W0W_SHIFT 16
Jasper_lee 0:b16d94660a33 7942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
Jasper_lee 0:b16d94660a33 7943 #define I2S_TCR5_WNW_MASK 0x1F000000u
Jasper_lee 0:b16d94660a33 7944 #define I2S_TCR5_WNW_SHIFT 24
Jasper_lee 0:b16d94660a33 7945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
Jasper_lee 0:b16d94660a33 7946 /* TDR Bit Fields */
Jasper_lee 0:b16d94660a33 7947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7948 #define I2S_TDR_TDR_SHIFT 0
Jasper_lee 0:b16d94660a33 7949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
Jasper_lee 0:b16d94660a33 7950 /* TFR Bit Fields */
Jasper_lee 0:b16d94660a33 7951 #define I2S_TFR_RFP_MASK 0xFu
Jasper_lee 0:b16d94660a33 7952 #define I2S_TFR_RFP_SHIFT 0
Jasper_lee 0:b16d94660a33 7953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
Jasper_lee 0:b16d94660a33 7954 #define I2S_TFR_WFP_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 7955 #define I2S_TFR_WFP_SHIFT 16
Jasper_lee 0:b16d94660a33 7956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
Jasper_lee 0:b16d94660a33 7957 /* TMR Bit Fields */
Jasper_lee 0:b16d94660a33 7958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 7959 #define I2S_TMR_TWM_SHIFT 0
Jasper_lee 0:b16d94660a33 7960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
Jasper_lee 0:b16d94660a33 7961 /* RCSR Bit Fields */
Jasper_lee 0:b16d94660a33 7962 #define I2S_RCSR_FRDE_MASK 0x1u
Jasper_lee 0:b16d94660a33 7963 #define I2S_RCSR_FRDE_SHIFT 0
Jasper_lee 0:b16d94660a33 7964 #define I2S_RCSR_FWDE_MASK 0x2u
Jasper_lee 0:b16d94660a33 7965 #define I2S_RCSR_FWDE_SHIFT 1
Jasper_lee 0:b16d94660a33 7966 #define I2S_RCSR_FRIE_MASK 0x100u
Jasper_lee 0:b16d94660a33 7967 #define I2S_RCSR_FRIE_SHIFT 8
Jasper_lee 0:b16d94660a33 7968 #define I2S_RCSR_FWIE_MASK 0x200u
Jasper_lee 0:b16d94660a33 7969 #define I2S_RCSR_FWIE_SHIFT 9
Jasper_lee 0:b16d94660a33 7970 #define I2S_RCSR_FEIE_MASK 0x400u
Jasper_lee 0:b16d94660a33 7971 #define I2S_RCSR_FEIE_SHIFT 10
Jasper_lee 0:b16d94660a33 7972 #define I2S_RCSR_SEIE_MASK 0x800u
Jasper_lee 0:b16d94660a33 7973 #define I2S_RCSR_SEIE_SHIFT 11
Jasper_lee 0:b16d94660a33 7974 #define I2S_RCSR_WSIE_MASK 0x1000u
Jasper_lee 0:b16d94660a33 7975 #define I2S_RCSR_WSIE_SHIFT 12
Jasper_lee 0:b16d94660a33 7976 #define I2S_RCSR_FRF_MASK 0x10000u
Jasper_lee 0:b16d94660a33 7977 #define I2S_RCSR_FRF_SHIFT 16
Jasper_lee 0:b16d94660a33 7978 #define I2S_RCSR_FWF_MASK 0x20000u
Jasper_lee 0:b16d94660a33 7979 #define I2S_RCSR_FWF_SHIFT 17
Jasper_lee 0:b16d94660a33 7980 #define I2S_RCSR_FEF_MASK 0x40000u
Jasper_lee 0:b16d94660a33 7981 #define I2S_RCSR_FEF_SHIFT 18
Jasper_lee 0:b16d94660a33 7982 #define I2S_RCSR_SEF_MASK 0x80000u
Jasper_lee 0:b16d94660a33 7983 #define I2S_RCSR_SEF_SHIFT 19
Jasper_lee 0:b16d94660a33 7984 #define I2S_RCSR_WSF_MASK 0x100000u
Jasper_lee 0:b16d94660a33 7985 #define I2S_RCSR_WSF_SHIFT 20
Jasper_lee 0:b16d94660a33 7986 #define I2S_RCSR_SR_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 7987 #define I2S_RCSR_SR_SHIFT 24
Jasper_lee 0:b16d94660a33 7988 #define I2S_RCSR_FR_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 7989 #define I2S_RCSR_FR_SHIFT 25
Jasper_lee 0:b16d94660a33 7990 #define I2S_RCSR_BCE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 7991 #define I2S_RCSR_BCE_SHIFT 28
Jasper_lee 0:b16d94660a33 7992 #define I2S_RCSR_DBGE_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 7993 #define I2S_RCSR_DBGE_SHIFT 29
Jasper_lee 0:b16d94660a33 7994 #define I2S_RCSR_STOPE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 7995 #define I2S_RCSR_STOPE_SHIFT 30
Jasper_lee 0:b16d94660a33 7996 #define I2S_RCSR_RE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 7997 #define I2S_RCSR_RE_SHIFT 31
Jasper_lee 0:b16d94660a33 7998 /* RCR1 Bit Fields */
Jasper_lee 0:b16d94660a33 7999 #define I2S_RCR1_RFW_MASK 0x7u
Jasper_lee 0:b16d94660a33 8000 #define I2S_RCR1_RFW_SHIFT 0
Jasper_lee 0:b16d94660a33 8001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
Jasper_lee 0:b16d94660a33 8002 /* RCR2 Bit Fields */
Jasper_lee 0:b16d94660a33 8003 #define I2S_RCR2_DIV_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8004 #define I2S_RCR2_DIV_SHIFT 0
Jasper_lee 0:b16d94660a33 8005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
Jasper_lee 0:b16d94660a33 8006 #define I2S_RCR2_BCD_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 8007 #define I2S_RCR2_BCD_SHIFT 24
Jasper_lee 0:b16d94660a33 8008 #define I2S_RCR2_BCP_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 8009 #define I2S_RCR2_BCP_SHIFT 25
Jasper_lee 0:b16d94660a33 8010 #define I2S_RCR2_MSEL_MASK 0xC000000u
Jasper_lee 0:b16d94660a33 8011 #define I2S_RCR2_MSEL_SHIFT 26
Jasper_lee 0:b16d94660a33 8012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
Jasper_lee 0:b16d94660a33 8013 #define I2S_RCR2_BCI_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 8014 #define I2S_RCR2_BCI_SHIFT 28
Jasper_lee 0:b16d94660a33 8015 #define I2S_RCR2_BCS_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 8016 #define I2S_RCR2_BCS_SHIFT 29
Jasper_lee 0:b16d94660a33 8017 #define I2S_RCR2_SYNC_MASK 0xC0000000u
Jasper_lee 0:b16d94660a33 8018 #define I2S_RCR2_SYNC_SHIFT 30
Jasper_lee 0:b16d94660a33 8019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
Jasper_lee 0:b16d94660a33 8020 /* RCR3 Bit Fields */
Jasper_lee 0:b16d94660a33 8021 #define I2S_RCR3_WDFL_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 8022 #define I2S_RCR3_WDFL_SHIFT 0
Jasper_lee 0:b16d94660a33 8023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
Jasper_lee 0:b16d94660a33 8024 #define I2S_RCR3_RCE_MASK 0x30000u
Jasper_lee 0:b16d94660a33 8025 #define I2S_RCR3_RCE_SHIFT 16
Jasper_lee 0:b16d94660a33 8026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
Jasper_lee 0:b16d94660a33 8027 /* RCR4 Bit Fields */
Jasper_lee 0:b16d94660a33 8028 #define I2S_RCR4_FSD_MASK 0x1u
Jasper_lee 0:b16d94660a33 8029 #define I2S_RCR4_FSD_SHIFT 0
Jasper_lee 0:b16d94660a33 8030 #define I2S_RCR4_FSP_MASK 0x2u
Jasper_lee 0:b16d94660a33 8031 #define I2S_RCR4_FSP_SHIFT 1
Jasper_lee 0:b16d94660a33 8032 #define I2S_RCR4_FSE_MASK 0x8u
Jasper_lee 0:b16d94660a33 8033 #define I2S_RCR4_FSE_SHIFT 3
Jasper_lee 0:b16d94660a33 8034 #define I2S_RCR4_MF_MASK 0x10u
Jasper_lee 0:b16d94660a33 8035 #define I2S_RCR4_MF_SHIFT 4
Jasper_lee 0:b16d94660a33 8036 #define I2S_RCR4_SYWD_MASK 0x1F00u
Jasper_lee 0:b16d94660a33 8037 #define I2S_RCR4_SYWD_SHIFT 8
Jasper_lee 0:b16d94660a33 8038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
Jasper_lee 0:b16d94660a33 8039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
Jasper_lee 0:b16d94660a33 8040 #define I2S_RCR4_FRSZ_SHIFT 16
Jasper_lee 0:b16d94660a33 8041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
Jasper_lee 0:b16d94660a33 8042 /* RCR5 Bit Fields */
Jasper_lee 0:b16d94660a33 8043 #define I2S_RCR5_FBT_MASK 0x1F00u
Jasper_lee 0:b16d94660a33 8044 #define I2S_RCR5_FBT_SHIFT 8
Jasper_lee 0:b16d94660a33 8045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
Jasper_lee 0:b16d94660a33 8046 #define I2S_RCR5_W0W_MASK 0x1F0000u
Jasper_lee 0:b16d94660a33 8047 #define I2S_RCR5_W0W_SHIFT 16
Jasper_lee 0:b16d94660a33 8048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
Jasper_lee 0:b16d94660a33 8049 #define I2S_RCR5_WNW_MASK 0x1F000000u
Jasper_lee 0:b16d94660a33 8050 #define I2S_RCR5_WNW_SHIFT 24
Jasper_lee 0:b16d94660a33 8051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
Jasper_lee 0:b16d94660a33 8052 /* RDR Bit Fields */
Jasper_lee 0:b16d94660a33 8053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 8054 #define I2S_RDR_RDR_SHIFT 0
Jasper_lee 0:b16d94660a33 8055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
Jasper_lee 0:b16d94660a33 8056 /* RFR Bit Fields */
Jasper_lee 0:b16d94660a33 8057 #define I2S_RFR_RFP_MASK 0xFu
Jasper_lee 0:b16d94660a33 8058 #define I2S_RFR_RFP_SHIFT 0
Jasper_lee 0:b16d94660a33 8059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
Jasper_lee 0:b16d94660a33 8060 #define I2S_RFR_WFP_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 8061 #define I2S_RFR_WFP_SHIFT 16
Jasper_lee 0:b16d94660a33 8062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
Jasper_lee 0:b16d94660a33 8063 /* RMR Bit Fields */
Jasper_lee 0:b16d94660a33 8064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 8065 #define I2S_RMR_RWM_SHIFT 0
Jasper_lee 0:b16d94660a33 8066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
Jasper_lee 0:b16d94660a33 8067 /* MCR Bit Fields */
Jasper_lee 0:b16d94660a33 8068 #define I2S_MCR_MICS_MASK 0x3000000u
Jasper_lee 0:b16d94660a33 8069 #define I2S_MCR_MICS_SHIFT 24
Jasper_lee 0:b16d94660a33 8070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
Jasper_lee 0:b16d94660a33 8071 #define I2S_MCR_MOE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 8072 #define I2S_MCR_MOE_SHIFT 30
Jasper_lee 0:b16d94660a33 8073 #define I2S_MCR_DUF_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 8074 #define I2S_MCR_DUF_SHIFT 31
Jasper_lee 0:b16d94660a33 8075 /* MDR Bit Fields */
Jasper_lee 0:b16d94660a33 8076 #define I2S_MDR_DIVIDE_MASK 0xFFFu
Jasper_lee 0:b16d94660a33 8077 #define I2S_MDR_DIVIDE_SHIFT 0
Jasper_lee 0:b16d94660a33 8078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
Jasper_lee 0:b16d94660a33 8079 #define I2S_MDR_FRACT_MASK 0xFF000u
Jasper_lee 0:b16d94660a33 8080 #define I2S_MDR_FRACT_SHIFT 12
Jasper_lee 0:b16d94660a33 8081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
Jasper_lee 0:b16d94660a33 8082
Jasper_lee 0:b16d94660a33 8083 /*!
Jasper_lee 0:b16d94660a33 8084 * @}
Jasper_lee 0:b16d94660a33 8085 */ /* end of group I2S_Register_Masks */
Jasper_lee 0:b16d94660a33 8086
Jasper_lee 0:b16d94660a33 8087
Jasper_lee 0:b16d94660a33 8088 /* I2S - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 8089 /** Peripheral I2S0 base address */
Jasper_lee 0:b16d94660a33 8090 #define I2S0_BASE (0x4002F000u)
Jasper_lee 0:b16d94660a33 8091 /** Peripheral I2S0 base pointer */
Jasper_lee 0:b16d94660a33 8092 #define I2S0 ((I2S_Type *)I2S0_BASE)
Jasper_lee 0:b16d94660a33 8093 #define I2S0_BASE_PTR (I2S0)
Jasper_lee 0:b16d94660a33 8094 /** Array initializer of I2S peripheral base addresses */
Jasper_lee 0:b16d94660a33 8095 #define I2S_BASE_ADDRS { I2S0_BASE }
Jasper_lee 0:b16d94660a33 8096 /** Array initializer of I2S peripheral base pointers */
Jasper_lee 0:b16d94660a33 8097 #define I2S_BASE_PTRS { I2S0 }
Jasper_lee 0:b16d94660a33 8098 /** Interrupt vectors for the I2S peripheral type */
Jasper_lee 0:b16d94660a33 8099 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
Jasper_lee 0:b16d94660a33 8100 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
Jasper_lee 0:b16d94660a33 8101
Jasper_lee 0:b16d94660a33 8102 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8103 -- I2S - Register accessor macros
Jasper_lee 0:b16d94660a33 8104 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8105
Jasper_lee 0:b16d94660a33 8106 /*!
Jasper_lee 0:b16d94660a33 8107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Jasper_lee 0:b16d94660a33 8108 * @{
Jasper_lee 0:b16d94660a33 8109 */
Jasper_lee 0:b16d94660a33 8110
Jasper_lee 0:b16d94660a33 8111
Jasper_lee 0:b16d94660a33 8112 /* I2S - Register instance definitions */
Jasper_lee 0:b16d94660a33 8113 /* I2S0 */
Jasper_lee 0:b16d94660a33 8114 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
Jasper_lee 0:b16d94660a33 8116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
Jasper_lee 0:b16d94660a33 8117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
Jasper_lee 0:b16d94660a33 8118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
Jasper_lee 0:b16d94660a33 8119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
Jasper_lee 0:b16d94660a33 8120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
Jasper_lee 0:b16d94660a33 8121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
Jasper_lee 0:b16d94660a33 8122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
Jasper_lee 0:b16d94660a33 8123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
Jasper_lee 0:b16d94660a33 8124 #define I2S0_TMR I2S_TMR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8125 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
Jasper_lee 0:b16d94660a33 8127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
Jasper_lee 0:b16d94660a33 8128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
Jasper_lee 0:b16d94660a33 8129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
Jasper_lee 0:b16d94660a33 8130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
Jasper_lee 0:b16d94660a33 8131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
Jasper_lee 0:b16d94660a33 8132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
Jasper_lee 0:b16d94660a33 8133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
Jasper_lee 0:b16d94660a33 8134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
Jasper_lee 0:b16d94660a33 8135 #define I2S0_RMR I2S_RMR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8136 #define I2S0_MCR I2S_MCR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8137 #define I2S0_MDR I2S_MDR_REG(I2S0)
Jasper_lee 0:b16d94660a33 8138
Jasper_lee 0:b16d94660a33 8139 /* I2S - Register array accessors */
Jasper_lee 0:b16d94660a33 8140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
Jasper_lee 0:b16d94660a33 8141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
Jasper_lee 0:b16d94660a33 8142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
Jasper_lee 0:b16d94660a33 8143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
Jasper_lee 0:b16d94660a33 8144
Jasper_lee 0:b16d94660a33 8145 /*!
Jasper_lee 0:b16d94660a33 8146 * @}
Jasper_lee 0:b16d94660a33 8147 */ /* end of group I2S_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8148
Jasper_lee 0:b16d94660a33 8149
Jasper_lee 0:b16d94660a33 8150 /*!
Jasper_lee 0:b16d94660a33 8151 * @}
Jasper_lee 0:b16d94660a33 8152 */ /* end of group I2S_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 8153
Jasper_lee 0:b16d94660a33 8154
Jasper_lee 0:b16d94660a33 8155 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8156 -- LLWU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8157 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8158
Jasper_lee 0:b16d94660a33 8159 /*!
Jasper_lee 0:b16d94660a33 8160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8161 * @{
Jasper_lee 0:b16d94660a33 8162 */
Jasper_lee 0:b16d94660a33 8163
Jasper_lee 0:b16d94660a33 8164 /** LLWU - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 8165 typedef struct {
Jasper_lee 0:b16d94660a33 8166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 8167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 8168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 8169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 8170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 8171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
Jasper_lee 0:b16d94660a33 8172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
Jasper_lee 0:b16d94660a33 8173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
Jasper_lee 0:b16d94660a33 8174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 8175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
Jasper_lee 0:b16d94660a33 8176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
Jasper_lee 0:b16d94660a33 8177 } LLWU_Type, *LLWU_MemMapPtr;
Jasper_lee 0:b16d94660a33 8178
Jasper_lee 0:b16d94660a33 8179 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8180 -- LLWU - Register accessor macros
Jasper_lee 0:b16d94660a33 8181 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8182
Jasper_lee 0:b16d94660a33 8183 /*!
Jasper_lee 0:b16d94660a33 8184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Jasper_lee 0:b16d94660a33 8185 * @{
Jasper_lee 0:b16d94660a33 8186 */
Jasper_lee 0:b16d94660a33 8187
Jasper_lee 0:b16d94660a33 8188
Jasper_lee 0:b16d94660a33 8189 /* LLWU - Register accessors */
Jasper_lee 0:b16d94660a33 8190 #define LLWU_PE1_REG(base) ((base)->PE1)
Jasper_lee 0:b16d94660a33 8191 #define LLWU_PE2_REG(base) ((base)->PE2)
Jasper_lee 0:b16d94660a33 8192 #define LLWU_PE3_REG(base) ((base)->PE3)
Jasper_lee 0:b16d94660a33 8193 #define LLWU_PE4_REG(base) ((base)->PE4)
Jasper_lee 0:b16d94660a33 8194 #define LLWU_ME_REG(base) ((base)->ME)
Jasper_lee 0:b16d94660a33 8195 #define LLWU_F1_REG(base) ((base)->F1)
Jasper_lee 0:b16d94660a33 8196 #define LLWU_F2_REG(base) ((base)->F2)
Jasper_lee 0:b16d94660a33 8197 #define LLWU_F3_REG(base) ((base)->F3)
Jasper_lee 0:b16d94660a33 8198 #define LLWU_FILT1_REG(base) ((base)->FILT1)
Jasper_lee 0:b16d94660a33 8199 #define LLWU_FILT2_REG(base) ((base)->FILT2)
Jasper_lee 0:b16d94660a33 8200 #define LLWU_RST_REG(base) ((base)->RST)
Jasper_lee 0:b16d94660a33 8201
Jasper_lee 0:b16d94660a33 8202 /*!
Jasper_lee 0:b16d94660a33 8203 * @}
Jasper_lee 0:b16d94660a33 8204 */ /* end of group LLWU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8205
Jasper_lee 0:b16d94660a33 8206
Jasper_lee 0:b16d94660a33 8207 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8208 -- LLWU Register Masks
Jasper_lee 0:b16d94660a33 8209 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8210
Jasper_lee 0:b16d94660a33 8211 /*!
Jasper_lee 0:b16d94660a33 8212 * @addtogroup LLWU_Register_Masks LLWU Register Masks
Jasper_lee 0:b16d94660a33 8213 * @{
Jasper_lee 0:b16d94660a33 8214 */
Jasper_lee 0:b16d94660a33 8215
Jasper_lee 0:b16d94660a33 8216 /* PE1 Bit Fields */
Jasper_lee 0:b16d94660a33 8217 #define LLWU_PE1_WUPE0_MASK 0x3u
Jasper_lee 0:b16d94660a33 8218 #define LLWU_PE1_WUPE0_SHIFT 0
Jasper_lee 0:b16d94660a33 8219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
Jasper_lee 0:b16d94660a33 8220 #define LLWU_PE1_WUPE1_MASK 0xCu
Jasper_lee 0:b16d94660a33 8221 #define LLWU_PE1_WUPE1_SHIFT 2
Jasper_lee 0:b16d94660a33 8222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
Jasper_lee 0:b16d94660a33 8223 #define LLWU_PE1_WUPE2_MASK 0x30u
Jasper_lee 0:b16d94660a33 8224 #define LLWU_PE1_WUPE2_SHIFT 4
Jasper_lee 0:b16d94660a33 8225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
Jasper_lee 0:b16d94660a33 8226 #define LLWU_PE1_WUPE3_MASK 0xC0u
Jasper_lee 0:b16d94660a33 8227 #define LLWU_PE1_WUPE3_SHIFT 6
Jasper_lee 0:b16d94660a33 8228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
Jasper_lee 0:b16d94660a33 8229 /* PE2 Bit Fields */
Jasper_lee 0:b16d94660a33 8230 #define LLWU_PE2_WUPE4_MASK 0x3u
Jasper_lee 0:b16d94660a33 8231 #define LLWU_PE2_WUPE4_SHIFT 0
Jasper_lee 0:b16d94660a33 8232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
Jasper_lee 0:b16d94660a33 8233 #define LLWU_PE2_WUPE5_MASK 0xCu
Jasper_lee 0:b16d94660a33 8234 #define LLWU_PE2_WUPE5_SHIFT 2
Jasper_lee 0:b16d94660a33 8235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
Jasper_lee 0:b16d94660a33 8236 #define LLWU_PE2_WUPE6_MASK 0x30u
Jasper_lee 0:b16d94660a33 8237 #define LLWU_PE2_WUPE6_SHIFT 4
Jasper_lee 0:b16d94660a33 8238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
Jasper_lee 0:b16d94660a33 8239 #define LLWU_PE2_WUPE7_MASK 0xC0u
Jasper_lee 0:b16d94660a33 8240 #define LLWU_PE2_WUPE7_SHIFT 6
Jasper_lee 0:b16d94660a33 8241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
Jasper_lee 0:b16d94660a33 8242 /* PE3 Bit Fields */
Jasper_lee 0:b16d94660a33 8243 #define LLWU_PE3_WUPE8_MASK 0x3u
Jasper_lee 0:b16d94660a33 8244 #define LLWU_PE3_WUPE8_SHIFT 0
Jasper_lee 0:b16d94660a33 8245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
Jasper_lee 0:b16d94660a33 8246 #define LLWU_PE3_WUPE9_MASK 0xCu
Jasper_lee 0:b16d94660a33 8247 #define LLWU_PE3_WUPE9_SHIFT 2
Jasper_lee 0:b16d94660a33 8248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
Jasper_lee 0:b16d94660a33 8249 #define LLWU_PE3_WUPE10_MASK 0x30u
Jasper_lee 0:b16d94660a33 8250 #define LLWU_PE3_WUPE10_SHIFT 4
Jasper_lee 0:b16d94660a33 8251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
Jasper_lee 0:b16d94660a33 8252 #define LLWU_PE3_WUPE11_MASK 0xC0u
Jasper_lee 0:b16d94660a33 8253 #define LLWU_PE3_WUPE11_SHIFT 6
Jasper_lee 0:b16d94660a33 8254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
Jasper_lee 0:b16d94660a33 8255 /* PE4 Bit Fields */
Jasper_lee 0:b16d94660a33 8256 #define LLWU_PE4_WUPE12_MASK 0x3u
Jasper_lee 0:b16d94660a33 8257 #define LLWU_PE4_WUPE12_SHIFT 0
Jasper_lee 0:b16d94660a33 8258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
Jasper_lee 0:b16d94660a33 8259 #define LLWU_PE4_WUPE13_MASK 0xCu
Jasper_lee 0:b16d94660a33 8260 #define LLWU_PE4_WUPE13_SHIFT 2
Jasper_lee 0:b16d94660a33 8261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
Jasper_lee 0:b16d94660a33 8262 #define LLWU_PE4_WUPE14_MASK 0x30u
Jasper_lee 0:b16d94660a33 8263 #define LLWU_PE4_WUPE14_SHIFT 4
Jasper_lee 0:b16d94660a33 8264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
Jasper_lee 0:b16d94660a33 8265 #define LLWU_PE4_WUPE15_MASK 0xC0u
Jasper_lee 0:b16d94660a33 8266 #define LLWU_PE4_WUPE15_SHIFT 6
Jasper_lee 0:b16d94660a33 8267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
Jasper_lee 0:b16d94660a33 8268 /* ME Bit Fields */
Jasper_lee 0:b16d94660a33 8269 #define LLWU_ME_WUME0_MASK 0x1u
Jasper_lee 0:b16d94660a33 8270 #define LLWU_ME_WUME0_SHIFT 0
Jasper_lee 0:b16d94660a33 8271 #define LLWU_ME_WUME1_MASK 0x2u
Jasper_lee 0:b16d94660a33 8272 #define LLWU_ME_WUME1_SHIFT 1
Jasper_lee 0:b16d94660a33 8273 #define LLWU_ME_WUME2_MASK 0x4u
Jasper_lee 0:b16d94660a33 8274 #define LLWU_ME_WUME2_SHIFT 2
Jasper_lee 0:b16d94660a33 8275 #define LLWU_ME_WUME3_MASK 0x8u
Jasper_lee 0:b16d94660a33 8276 #define LLWU_ME_WUME3_SHIFT 3
Jasper_lee 0:b16d94660a33 8277 #define LLWU_ME_WUME4_MASK 0x10u
Jasper_lee 0:b16d94660a33 8278 #define LLWU_ME_WUME4_SHIFT 4
Jasper_lee 0:b16d94660a33 8279 #define LLWU_ME_WUME5_MASK 0x20u
Jasper_lee 0:b16d94660a33 8280 #define LLWU_ME_WUME5_SHIFT 5
Jasper_lee 0:b16d94660a33 8281 #define LLWU_ME_WUME6_MASK 0x40u
Jasper_lee 0:b16d94660a33 8282 #define LLWU_ME_WUME6_SHIFT 6
Jasper_lee 0:b16d94660a33 8283 #define LLWU_ME_WUME7_MASK 0x80u
Jasper_lee 0:b16d94660a33 8284 #define LLWU_ME_WUME7_SHIFT 7
Jasper_lee 0:b16d94660a33 8285 /* F1 Bit Fields */
Jasper_lee 0:b16d94660a33 8286 #define LLWU_F1_WUF0_MASK 0x1u
Jasper_lee 0:b16d94660a33 8287 #define LLWU_F1_WUF0_SHIFT 0
Jasper_lee 0:b16d94660a33 8288 #define LLWU_F1_WUF1_MASK 0x2u
Jasper_lee 0:b16d94660a33 8289 #define LLWU_F1_WUF1_SHIFT 1
Jasper_lee 0:b16d94660a33 8290 #define LLWU_F1_WUF2_MASK 0x4u
Jasper_lee 0:b16d94660a33 8291 #define LLWU_F1_WUF2_SHIFT 2
Jasper_lee 0:b16d94660a33 8292 #define LLWU_F1_WUF3_MASK 0x8u
Jasper_lee 0:b16d94660a33 8293 #define LLWU_F1_WUF3_SHIFT 3
Jasper_lee 0:b16d94660a33 8294 #define LLWU_F1_WUF4_MASK 0x10u
Jasper_lee 0:b16d94660a33 8295 #define LLWU_F1_WUF4_SHIFT 4
Jasper_lee 0:b16d94660a33 8296 #define LLWU_F1_WUF5_MASK 0x20u
Jasper_lee 0:b16d94660a33 8297 #define LLWU_F1_WUF5_SHIFT 5
Jasper_lee 0:b16d94660a33 8298 #define LLWU_F1_WUF6_MASK 0x40u
Jasper_lee 0:b16d94660a33 8299 #define LLWU_F1_WUF6_SHIFT 6
Jasper_lee 0:b16d94660a33 8300 #define LLWU_F1_WUF7_MASK 0x80u
Jasper_lee 0:b16d94660a33 8301 #define LLWU_F1_WUF7_SHIFT 7
Jasper_lee 0:b16d94660a33 8302 /* F2 Bit Fields */
Jasper_lee 0:b16d94660a33 8303 #define LLWU_F2_WUF8_MASK 0x1u
Jasper_lee 0:b16d94660a33 8304 #define LLWU_F2_WUF8_SHIFT 0
Jasper_lee 0:b16d94660a33 8305 #define LLWU_F2_WUF9_MASK 0x2u
Jasper_lee 0:b16d94660a33 8306 #define LLWU_F2_WUF9_SHIFT 1
Jasper_lee 0:b16d94660a33 8307 #define LLWU_F2_WUF10_MASK 0x4u
Jasper_lee 0:b16d94660a33 8308 #define LLWU_F2_WUF10_SHIFT 2
Jasper_lee 0:b16d94660a33 8309 #define LLWU_F2_WUF11_MASK 0x8u
Jasper_lee 0:b16d94660a33 8310 #define LLWU_F2_WUF11_SHIFT 3
Jasper_lee 0:b16d94660a33 8311 #define LLWU_F2_WUF12_MASK 0x10u
Jasper_lee 0:b16d94660a33 8312 #define LLWU_F2_WUF12_SHIFT 4
Jasper_lee 0:b16d94660a33 8313 #define LLWU_F2_WUF13_MASK 0x20u
Jasper_lee 0:b16d94660a33 8314 #define LLWU_F2_WUF13_SHIFT 5
Jasper_lee 0:b16d94660a33 8315 #define LLWU_F2_WUF14_MASK 0x40u
Jasper_lee 0:b16d94660a33 8316 #define LLWU_F2_WUF14_SHIFT 6
Jasper_lee 0:b16d94660a33 8317 #define LLWU_F2_WUF15_MASK 0x80u
Jasper_lee 0:b16d94660a33 8318 #define LLWU_F2_WUF15_SHIFT 7
Jasper_lee 0:b16d94660a33 8319 /* F3 Bit Fields */
Jasper_lee 0:b16d94660a33 8320 #define LLWU_F3_MWUF0_MASK 0x1u
Jasper_lee 0:b16d94660a33 8321 #define LLWU_F3_MWUF0_SHIFT 0
Jasper_lee 0:b16d94660a33 8322 #define LLWU_F3_MWUF1_MASK 0x2u
Jasper_lee 0:b16d94660a33 8323 #define LLWU_F3_MWUF1_SHIFT 1
Jasper_lee 0:b16d94660a33 8324 #define LLWU_F3_MWUF2_MASK 0x4u
Jasper_lee 0:b16d94660a33 8325 #define LLWU_F3_MWUF2_SHIFT 2
Jasper_lee 0:b16d94660a33 8326 #define LLWU_F3_MWUF3_MASK 0x8u
Jasper_lee 0:b16d94660a33 8327 #define LLWU_F3_MWUF3_SHIFT 3
Jasper_lee 0:b16d94660a33 8328 #define LLWU_F3_MWUF4_MASK 0x10u
Jasper_lee 0:b16d94660a33 8329 #define LLWU_F3_MWUF4_SHIFT 4
Jasper_lee 0:b16d94660a33 8330 #define LLWU_F3_MWUF5_MASK 0x20u
Jasper_lee 0:b16d94660a33 8331 #define LLWU_F3_MWUF5_SHIFT 5
Jasper_lee 0:b16d94660a33 8332 #define LLWU_F3_MWUF6_MASK 0x40u
Jasper_lee 0:b16d94660a33 8333 #define LLWU_F3_MWUF6_SHIFT 6
Jasper_lee 0:b16d94660a33 8334 #define LLWU_F3_MWUF7_MASK 0x80u
Jasper_lee 0:b16d94660a33 8335 #define LLWU_F3_MWUF7_SHIFT 7
Jasper_lee 0:b16d94660a33 8336 /* FILT1 Bit Fields */
Jasper_lee 0:b16d94660a33 8337 #define LLWU_FILT1_FILTSEL_MASK 0xFu
Jasper_lee 0:b16d94660a33 8338 #define LLWU_FILT1_FILTSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 8339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
Jasper_lee 0:b16d94660a33 8340 #define LLWU_FILT1_FILTE_MASK 0x60u
Jasper_lee 0:b16d94660a33 8341 #define LLWU_FILT1_FILTE_SHIFT 5
Jasper_lee 0:b16d94660a33 8342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
Jasper_lee 0:b16d94660a33 8343 #define LLWU_FILT1_FILTF_MASK 0x80u
Jasper_lee 0:b16d94660a33 8344 #define LLWU_FILT1_FILTF_SHIFT 7
Jasper_lee 0:b16d94660a33 8345 /* FILT2 Bit Fields */
Jasper_lee 0:b16d94660a33 8346 #define LLWU_FILT2_FILTSEL_MASK 0xFu
Jasper_lee 0:b16d94660a33 8347 #define LLWU_FILT2_FILTSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 8348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
Jasper_lee 0:b16d94660a33 8349 #define LLWU_FILT2_FILTE_MASK 0x60u
Jasper_lee 0:b16d94660a33 8350 #define LLWU_FILT2_FILTE_SHIFT 5
Jasper_lee 0:b16d94660a33 8351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
Jasper_lee 0:b16d94660a33 8352 #define LLWU_FILT2_FILTF_MASK 0x80u
Jasper_lee 0:b16d94660a33 8353 #define LLWU_FILT2_FILTF_SHIFT 7
Jasper_lee 0:b16d94660a33 8354 /* RST Bit Fields */
Jasper_lee 0:b16d94660a33 8355 #define LLWU_RST_RSTFILT_MASK 0x1u
Jasper_lee 0:b16d94660a33 8356 #define LLWU_RST_RSTFILT_SHIFT 0
Jasper_lee 0:b16d94660a33 8357 #define LLWU_RST_LLRSTE_MASK 0x2u
Jasper_lee 0:b16d94660a33 8358 #define LLWU_RST_LLRSTE_SHIFT 1
Jasper_lee 0:b16d94660a33 8359
Jasper_lee 0:b16d94660a33 8360 /*!
Jasper_lee 0:b16d94660a33 8361 * @}
Jasper_lee 0:b16d94660a33 8362 */ /* end of group LLWU_Register_Masks */
Jasper_lee 0:b16d94660a33 8363
Jasper_lee 0:b16d94660a33 8364
Jasper_lee 0:b16d94660a33 8365 /* LLWU - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 8366 /** Peripheral LLWU base address */
Jasper_lee 0:b16d94660a33 8367 #define LLWU_BASE (0x4007C000u)
Jasper_lee 0:b16d94660a33 8368 /** Peripheral LLWU base pointer */
Jasper_lee 0:b16d94660a33 8369 #define LLWU ((LLWU_Type *)LLWU_BASE)
Jasper_lee 0:b16d94660a33 8370 #define LLWU_BASE_PTR (LLWU)
Jasper_lee 0:b16d94660a33 8371 /** Array initializer of LLWU peripheral base addresses */
Jasper_lee 0:b16d94660a33 8372 #define LLWU_BASE_ADDRS { LLWU_BASE }
Jasper_lee 0:b16d94660a33 8373 /** Array initializer of LLWU peripheral base pointers */
Jasper_lee 0:b16d94660a33 8374 #define LLWU_BASE_PTRS { LLWU }
Jasper_lee 0:b16d94660a33 8375 /** Interrupt vectors for the LLWU peripheral type */
Jasper_lee 0:b16d94660a33 8376 #define LLWU_IRQS { LLW_IRQn }
Jasper_lee 0:b16d94660a33 8377
Jasper_lee 0:b16d94660a33 8378 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8379 -- LLWU - Register accessor macros
Jasper_lee 0:b16d94660a33 8380 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8381
Jasper_lee 0:b16d94660a33 8382 /*!
Jasper_lee 0:b16d94660a33 8383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Jasper_lee 0:b16d94660a33 8384 * @{
Jasper_lee 0:b16d94660a33 8385 */
Jasper_lee 0:b16d94660a33 8386
Jasper_lee 0:b16d94660a33 8387
Jasper_lee 0:b16d94660a33 8388 /* LLWU - Register instance definitions */
Jasper_lee 0:b16d94660a33 8389 /* LLWU */
Jasper_lee 0:b16d94660a33 8390 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
Jasper_lee 0:b16d94660a33 8391 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
Jasper_lee 0:b16d94660a33 8392 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
Jasper_lee 0:b16d94660a33 8393 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
Jasper_lee 0:b16d94660a33 8394 #define LLWU_ME LLWU_ME_REG(LLWU)
Jasper_lee 0:b16d94660a33 8395 #define LLWU_F1 LLWU_F1_REG(LLWU)
Jasper_lee 0:b16d94660a33 8396 #define LLWU_F2 LLWU_F2_REG(LLWU)
Jasper_lee 0:b16d94660a33 8397 #define LLWU_F3 LLWU_F3_REG(LLWU)
Jasper_lee 0:b16d94660a33 8398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
Jasper_lee 0:b16d94660a33 8399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
Jasper_lee 0:b16d94660a33 8400 #define LLWU_RST LLWU_RST_REG(LLWU)
Jasper_lee 0:b16d94660a33 8401
Jasper_lee 0:b16d94660a33 8402 /*!
Jasper_lee 0:b16d94660a33 8403 * @}
Jasper_lee 0:b16d94660a33 8404 */ /* end of group LLWU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8405
Jasper_lee 0:b16d94660a33 8406
Jasper_lee 0:b16d94660a33 8407 /*!
Jasper_lee 0:b16d94660a33 8408 * @}
Jasper_lee 0:b16d94660a33 8409 */ /* end of group LLWU_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 8410
Jasper_lee 0:b16d94660a33 8411
Jasper_lee 0:b16d94660a33 8412 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8413 -- LPTMR Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8414 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8415
Jasper_lee 0:b16d94660a33 8416 /*!
Jasper_lee 0:b16d94660a33 8417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8418 * @{
Jasper_lee 0:b16d94660a33 8419 */
Jasper_lee 0:b16d94660a33 8420
Jasper_lee 0:b16d94660a33 8421 /** LPTMR - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 8422 typedef struct {
Jasper_lee 0:b16d94660a33 8423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 8424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 8425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 8426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 8427 } LPTMR_Type, *LPTMR_MemMapPtr;
Jasper_lee 0:b16d94660a33 8428
Jasper_lee 0:b16d94660a33 8429 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8430 -- LPTMR - Register accessor macros
Jasper_lee 0:b16d94660a33 8431 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8432
Jasper_lee 0:b16d94660a33 8433 /*!
Jasper_lee 0:b16d94660a33 8434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Jasper_lee 0:b16d94660a33 8435 * @{
Jasper_lee 0:b16d94660a33 8436 */
Jasper_lee 0:b16d94660a33 8437
Jasper_lee 0:b16d94660a33 8438
Jasper_lee 0:b16d94660a33 8439 /* LPTMR - Register accessors */
Jasper_lee 0:b16d94660a33 8440 #define LPTMR_CSR_REG(base) ((base)->CSR)
Jasper_lee 0:b16d94660a33 8441 #define LPTMR_PSR_REG(base) ((base)->PSR)
Jasper_lee 0:b16d94660a33 8442 #define LPTMR_CMR_REG(base) ((base)->CMR)
Jasper_lee 0:b16d94660a33 8443 #define LPTMR_CNR_REG(base) ((base)->CNR)
Jasper_lee 0:b16d94660a33 8444
Jasper_lee 0:b16d94660a33 8445 /*!
Jasper_lee 0:b16d94660a33 8446 * @}
Jasper_lee 0:b16d94660a33 8447 */ /* end of group LPTMR_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8448
Jasper_lee 0:b16d94660a33 8449
Jasper_lee 0:b16d94660a33 8450 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8451 -- LPTMR Register Masks
Jasper_lee 0:b16d94660a33 8452 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8453
Jasper_lee 0:b16d94660a33 8454 /*!
Jasper_lee 0:b16d94660a33 8455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Jasper_lee 0:b16d94660a33 8456 * @{
Jasper_lee 0:b16d94660a33 8457 */
Jasper_lee 0:b16d94660a33 8458
Jasper_lee 0:b16d94660a33 8459 /* CSR Bit Fields */
Jasper_lee 0:b16d94660a33 8460 #define LPTMR_CSR_TEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 8461 #define LPTMR_CSR_TEN_SHIFT 0
Jasper_lee 0:b16d94660a33 8462 #define LPTMR_CSR_TMS_MASK 0x2u
Jasper_lee 0:b16d94660a33 8463 #define LPTMR_CSR_TMS_SHIFT 1
Jasper_lee 0:b16d94660a33 8464 #define LPTMR_CSR_TFC_MASK 0x4u
Jasper_lee 0:b16d94660a33 8465 #define LPTMR_CSR_TFC_SHIFT 2
Jasper_lee 0:b16d94660a33 8466 #define LPTMR_CSR_TPP_MASK 0x8u
Jasper_lee 0:b16d94660a33 8467 #define LPTMR_CSR_TPP_SHIFT 3
Jasper_lee 0:b16d94660a33 8468 #define LPTMR_CSR_TPS_MASK 0x30u
Jasper_lee 0:b16d94660a33 8469 #define LPTMR_CSR_TPS_SHIFT 4
Jasper_lee 0:b16d94660a33 8470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
Jasper_lee 0:b16d94660a33 8471 #define LPTMR_CSR_TIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 8472 #define LPTMR_CSR_TIE_SHIFT 6
Jasper_lee 0:b16d94660a33 8473 #define LPTMR_CSR_TCF_MASK 0x80u
Jasper_lee 0:b16d94660a33 8474 #define LPTMR_CSR_TCF_SHIFT 7
Jasper_lee 0:b16d94660a33 8475 /* PSR Bit Fields */
Jasper_lee 0:b16d94660a33 8476 #define LPTMR_PSR_PCS_MASK 0x3u
Jasper_lee 0:b16d94660a33 8477 #define LPTMR_PSR_PCS_SHIFT 0
Jasper_lee 0:b16d94660a33 8478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
Jasper_lee 0:b16d94660a33 8479 #define LPTMR_PSR_PBYP_MASK 0x4u
Jasper_lee 0:b16d94660a33 8480 #define LPTMR_PSR_PBYP_SHIFT 2
Jasper_lee 0:b16d94660a33 8481 #define LPTMR_PSR_PRESCALE_MASK 0x78u
Jasper_lee 0:b16d94660a33 8482 #define LPTMR_PSR_PRESCALE_SHIFT 3
Jasper_lee 0:b16d94660a33 8483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
Jasper_lee 0:b16d94660a33 8484 /* CMR Bit Fields */
Jasper_lee 0:b16d94660a33 8485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 8486 #define LPTMR_CMR_COMPARE_SHIFT 0
Jasper_lee 0:b16d94660a33 8487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
Jasper_lee 0:b16d94660a33 8488 /* CNR Bit Fields */
Jasper_lee 0:b16d94660a33 8489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 8490 #define LPTMR_CNR_COUNTER_SHIFT 0
Jasper_lee 0:b16d94660a33 8491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
Jasper_lee 0:b16d94660a33 8492
Jasper_lee 0:b16d94660a33 8493 /*!
Jasper_lee 0:b16d94660a33 8494 * @}
Jasper_lee 0:b16d94660a33 8495 */ /* end of group LPTMR_Register_Masks */
Jasper_lee 0:b16d94660a33 8496
Jasper_lee 0:b16d94660a33 8497
Jasper_lee 0:b16d94660a33 8498 /* LPTMR - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 8499 /** Peripheral LPTMR0 base address */
Jasper_lee 0:b16d94660a33 8500 #define LPTMR0_BASE (0x40040000u)
Jasper_lee 0:b16d94660a33 8501 /** Peripheral LPTMR0 base pointer */
Jasper_lee 0:b16d94660a33 8502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Jasper_lee 0:b16d94660a33 8503 #define LPTMR0_BASE_PTR (LPTMR0)
Jasper_lee 0:b16d94660a33 8504 /** Array initializer of LPTMR peripheral base addresses */
Jasper_lee 0:b16d94660a33 8505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
Jasper_lee 0:b16d94660a33 8506 /** Array initializer of LPTMR peripheral base pointers */
Jasper_lee 0:b16d94660a33 8507 #define LPTMR_BASE_PTRS { LPTMR0 }
Jasper_lee 0:b16d94660a33 8508 /** Interrupt vectors for the LPTMR peripheral type */
Jasper_lee 0:b16d94660a33 8509 #define LPTMR_IRQS { LPTimer_IRQn }
Jasper_lee 0:b16d94660a33 8510
Jasper_lee 0:b16d94660a33 8511 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8512 -- LPTMR - Register accessor macros
Jasper_lee 0:b16d94660a33 8513 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8514
Jasper_lee 0:b16d94660a33 8515 /*!
Jasper_lee 0:b16d94660a33 8516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Jasper_lee 0:b16d94660a33 8517 * @{
Jasper_lee 0:b16d94660a33 8518 */
Jasper_lee 0:b16d94660a33 8519
Jasper_lee 0:b16d94660a33 8520
Jasper_lee 0:b16d94660a33 8521 /* LPTMR - Register instance definitions */
Jasper_lee 0:b16d94660a33 8522 /* LPTMR0 */
Jasper_lee 0:b16d94660a33 8523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
Jasper_lee 0:b16d94660a33 8524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
Jasper_lee 0:b16d94660a33 8525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
Jasper_lee 0:b16d94660a33 8526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
Jasper_lee 0:b16d94660a33 8527
Jasper_lee 0:b16d94660a33 8528 /*!
Jasper_lee 0:b16d94660a33 8529 * @}
Jasper_lee 0:b16d94660a33 8530 */ /* end of group LPTMR_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8531
Jasper_lee 0:b16d94660a33 8532
Jasper_lee 0:b16d94660a33 8533 /*!
Jasper_lee 0:b16d94660a33 8534 * @}
Jasper_lee 0:b16d94660a33 8535 */ /* end of group LPTMR_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 8536
Jasper_lee 0:b16d94660a33 8537
Jasper_lee 0:b16d94660a33 8538 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8539 -- MCG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8540 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8541
Jasper_lee 0:b16d94660a33 8542 /*!
Jasper_lee 0:b16d94660a33 8543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8544 * @{
Jasper_lee 0:b16d94660a33 8545 */
Jasper_lee 0:b16d94660a33 8546
Jasper_lee 0:b16d94660a33 8547 /** MCG - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 8548 typedef struct {
Jasper_lee 0:b16d94660a33 8549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 8550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 8551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 8552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 8553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 8554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
Jasper_lee 0:b16d94660a33 8555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
Jasper_lee 0:b16d94660a33 8556 uint8_t RESERVED_0[1];
Jasper_lee 0:b16d94660a33 8557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 8558 uint8_t RESERVED_1[1];
Jasper_lee 0:b16d94660a33 8559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
Jasper_lee 0:b16d94660a33 8560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
Jasper_lee 0:b16d94660a33 8561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 8562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
Jasper_lee 0:b16d94660a33 8563 } MCG_Type, *MCG_MemMapPtr;
Jasper_lee 0:b16d94660a33 8564
Jasper_lee 0:b16d94660a33 8565 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8566 -- MCG - Register accessor macros
Jasper_lee 0:b16d94660a33 8567 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8568
Jasper_lee 0:b16d94660a33 8569 /*!
Jasper_lee 0:b16d94660a33 8570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Jasper_lee 0:b16d94660a33 8571 * @{
Jasper_lee 0:b16d94660a33 8572 */
Jasper_lee 0:b16d94660a33 8573
Jasper_lee 0:b16d94660a33 8574
Jasper_lee 0:b16d94660a33 8575 /* MCG - Register accessors */
Jasper_lee 0:b16d94660a33 8576 #define MCG_C1_REG(base) ((base)->C1)
Jasper_lee 0:b16d94660a33 8577 #define MCG_C2_REG(base) ((base)->C2)
Jasper_lee 0:b16d94660a33 8578 #define MCG_C3_REG(base) ((base)->C3)
Jasper_lee 0:b16d94660a33 8579 #define MCG_C4_REG(base) ((base)->C4)
Jasper_lee 0:b16d94660a33 8580 #define MCG_C5_REG(base) ((base)->C5)
Jasper_lee 0:b16d94660a33 8581 #define MCG_C6_REG(base) ((base)->C6)
Jasper_lee 0:b16d94660a33 8582 #define MCG_S_REG(base) ((base)->S)
Jasper_lee 0:b16d94660a33 8583 #define MCG_SC_REG(base) ((base)->SC)
Jasper_lee 0:b16d94660a33 8584 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
Jasper_lee 0:b16d94660a33 8585 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
Jasper_lee 0:b16d94660a33 8586 #define MCG_C7_REG(base) ((base)->C7)
Jasper_lee 0:b16d94660a33 8587 #define MCG_C8_REG(base) ((base)->C8)
Jasper_lee 0:b16d94660a33 8588
Jasper_lee 0:b16d94660a33 8589 /*!
Jasper_lee 0:b16d94660a33 8590 * @}
Jasper_lee 0:b16d94660a33 8591 */ /* end of group MCG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8592
Jasper_lee 0:b16d94660a33 8593
Jasper_lee 0:b16d94660a33 8594 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8595 -- MCG Register Masks
Jasper_lee 0:b16d94660a33 8596 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8597
Jasper_lee 0:b16d94660a33 8598 /*!
Jasper_lee 0:b16d94660a33 8599 * @addtogroup MCG_Register_Masks MCG Register Masks
Jasper_lee 0:b16d94660a33 8600 * @{
Jasper_lee 0:b16d94660a33 8601 */
Jasper_lee 0:b16d94660a33 8602
Jasper_lee 0:b16d94660a33 8603 /* C1 Bit Fields */
Jasper_lee 0:b16d94660a33 8604 #define MCG_C1_IREFSTEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 8605 #define MCG_C1_IREFSTEN_SHIFT 0
Jasper_lee 0:b16d94660a33 8606 #define MCG_C1_IRCLKEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 8607 #define MCG_C1_IRCLKEN_SHIFT 1
Jasper_lee 0:b16d94660a33 8608 #define MCG_C1_IREFS_MASK 0x4u
Jasper_lee 0:b16d94660a33 8609 #define MCG_C1_IREFS_SHIFT 2
Jasper_lee 0:b16d94660a33 8610 #define MCG_C1_FRDIV_MASK 0x38u
Jasper_lee 0:b16d94660a33 8611 #define MCG_C1_FRDIV_SHIFT 3
Jasper_lee 0:b16d94660a33 8612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
Jasper_lee 0:b16d94660a33 8613 #define MCG_C1_CLKS_MASK 0xC0u
Jasper_lee 0:b16d94660a33 8614 #define MCG_C1_CLKS_SHIFT 6
Jasper_lee 0:b16d94660a33 8615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
Jasper_lee 0:b16d94660a33 8616 /* C2 Bit Fields */
Jasper_lee 0:b16d94660a33 8617 #define MCG_C2_IRCS_MASK 0x1u
Jasper_lee 0:b16d94660a33 8618 #define MCG_C2_IRCS_SHIFT 0
Jasper_lee 0:b16d94660a33 8619 #define MCG_C2_LP_MASK 0x2u
Jasper_lee 0:b16d94660a33 8620 #define MCG_C2_LP_SHIFT 1
Jasper_lee 0:b16d94660a33 8621 #define MCG_C2_EREFS_MASK 0x4u
Jasper_lee 0:b16d94660a33 8622 #define MCG_C2_EREFS_SHIFT 2
Jasper_lee 0:b16d94660a33 8623 #define MCG_C2_HGO_MASK 0x8u
Jasper_lee 0:b16d94660a33 8624 #define MCG_C2_HGO_SHIFT 3
Jasper_lee 0:b16d94660a33 8625 #define MCG_C2_RANGE_MASK 0x30u
Jasper_lee 0:b16d94660a33 8626 #define MCG_C2_RANGE_SHIFT 4
Jasper_lee 0:b16d94660a33 8627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
Jasper_lee 0:b16d94660a33 8628 #define MCG_C2_FCFTRIM_MASK 0x40u
Jasper_lee 0:b16d94660a33 8629 #define MCG_C2_FCFTRIM_SHIFT 6
Jasper_lee 0:b16d94660a33 8630 #define MCG_C2_LOCRE0_MASK 0x80u
Jasper_lee 0:b16d94660a33 8631 #define MCG_C2_LOCRE0_SHIFT 7
Jasper_lee 0:b16d94660a33 8632 /* C3 Bit Fields */
Jasper_lee 0:b16d94660a33 8633 #define MCG_C3_SCTRIM_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8634 #define MCG_C3_SCTRIM_SHIFT 0
Jasper_lee 0:b16d94660a33 8635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
Jasper_lee 0:b16d94660a33 8636 /* C4 Bit Fields */
Jasper_lee 0:b16d94660a33 8637 #define MCG_C4_SCFTRIM_MASK 0x1u
Jasper_lee 0:b16d94660a33 8638 #define MCG_C4_SCFTRIM_SHIFT 0
Jasper_lee 0:b16d94660a33 8639 #define MCG_C4_FCTRIM_MASK 0x1Eu
Jasper_lee 0:b16d94660a33 8640 #define MCG_C4_FCTRIM_SHIFT 1
Jasper_lee 0:b16d94660a33 8641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
Jasper_lee 0:b16d94660a33 8642 #define MCG_C4_DRST_DRS_MASK 0x60u
Jasper_lee 0:b16d94660a33 8643 #define MCG_C4_DRST_DRS_SHIFT 5
Jasper_lee 0:b16d94660a33 8644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
Jasper_lee 0:b16d94660a33 8645 #define MCG_C4_DMX32_MASK 0x80u
Jasper_lee 0:b16d94660a33 8646 #define MCG_C4_DMX32_SHIFT 7
Jasper_lee 0:b16d94660a33 8647 /* C5 Bit Fields */
Jasper_lee 0:b16d94660a33 8648 #define MCG_C5_PRDIV0_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 8649 #define MCG_C5_PRDIV0_SHIFT 0
Jasper_lee 0:b16d94660a33 8650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
Jasper_lee 0:b16d94660a33 8651 #define MCG_C5_PLLSTEN0_MASK 0x20u
Jasper_lee 0:b16d94660a33 8652 #define MCG_C5_PLLSTEN0_SHIFT 5
Jasper_lee 0:b16d94660a33 8653 #define MCG_C5_PLLCLKEN0_MASK 0x40u
Jasper_lee 0:b16d94660a33 8654 #define MCG_C5_PLLCLKEN0_SHIFT 6
Jasper_lee 0:b16d94660a33 8655 /* C6 Bit Fields */
Jasper_lee 0:b16d94660a33 8656 #define MCG_C6_VDIV0_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 8657 #define MCG_C6_VDIV0_SHIFT 0
Jasper_lee 0:b16d94660a33 8658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
Jasper_lee 0:b16d94660a33 8659 #define MCG_C6_CME0_MASK 0x20u
Jasper_lee 0:b16d94660a33 8660 #define MCG_C6_CME0_SHIFT 5
Jasper_lee 0:b16d94660a33 8661 #define MCG_C6_PLLS_MASK 0x40u
Jasper_lee 0:b16d94660a33 8662 #define MCG_C6_PLLS_SHIFT 6
Jasper_lee 0:b16d94660a33 8663 #define MCG_C6_LOLIE0_MASK 0x80u
Jasper_lee 0:b16d94660a33 8664 #define MCG_C6_LOLIE0_SHIFT 7
Jasper_lee 0:b16d94660a33 8665 /* S Bit Fields */
Jasper_lee 0:b16d94660a33 8666 #define MCG_S_IRCST_MASK 0x1u
Jasper_lee 0:b16d94660a33 8667 #define MCG_S_IRCST_SHIFT 0
Jasper_lee 0:b16d94660a33 8668 #define MCG_S_OSCINIT0_MASK 0x2u
Jasper_lee 0:b16d94660a33 8669 #define MCG_S_OSCINIT0_SHIFT 1
Jasper_lee 0:b16d94660a33 8670 #define MCG_S_CLKST_MASK 0xCu
Jasper_lee 0:b16d94660a33 8671 #define MCG_S_CLKST_SHIFT 2
Jasper_lee 0:b16d94660a33 8672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
Jasper_lee 0:b16d94660a33 8673 #define MCG_S_IREFST_MASK 0x10u
Jasper_lee 0:b16d94660a33 8674 #define MCG_S_IREFST_SHIFT 4
Jasper_lee 0:b16d94660a33 8675 #define MCG_S_PLLST_MASK 0x20u
Jasper_lee 0:b16d94660a33 8676 #define MCG_S_PLLST_SHIFT 5
Jasper_lee 0:b16d94660a33 8677 #define MCG_S_LOCK0_MASK 0x40u
Jasper_lee 0:b16d94660a33 8678 #define MCG_S_LOCK0_SHIFT 6
Jasper_lee 0:b16d94660a33 8679 #define MCG_S_LOLS0_MASK 0x80u
Jasper_lee 0:b16d94660a33 8680 #define MCG_S_LOLS0_SHIFT 7
Jasper_lee 0:b16d94660a33 8681 /* SC Bit Fields */
Jasper_lee 0:b16d94660a33 8682 #define MCG_SC_LOCS0_MASK 0x1u
Jasper_lee 0:b16d94660a33 8683 #define MCG_SC_LOCS0_SHIFT 0
Jasper_lee 0:b16d94660a33 8684 #define MCG_SC_FCRDIV_MASK 0xEu
Jasper_lee 0:b16d94660a33 8685 #define MCG_SC_FCRDIV_SHIFT 1
Jasper_lee 0:b16d94660a33 8686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
Jasper_lee 0:b16d94660a33 8687 #define MCG_SC_FLTPRSRV_MASK 0x10u
Jasper_lee 0:b16d94660a33 8688 #define MCG_SC_FLTPRSRV_SHIFT 4
Jasper_lee 0:b16d94660a33 8689 #define MCG_SC_ATMF_MASK 0x20u
Jasper_lee 0:b16d94660a33 8690 #define MCG_SC_ATMF_SHIFT 5
Jasper_lee 0:b16d94660a33 8691 #define MCG_SC_ATMS_MASK 0x40u
Jasper_lee 0:b16d94660a33 8692 #define MCG_SC_ATMS_SHIFT 6
Jasper_lee 0:b16d94660a33 8693 #define MCG_SC_ATME_MASK 0x80u
Jasper_lee 0:b16d94660a33 8694 #define MCG_SC_ATME_SHIFT 7
Jasper_lee 0:b16d94660a33 8695 /* ATCVH Bit Fields */
Jasper_lee 0:b16d94660a33 8696 #define MCG_ATCVH_ATCVH_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8697 #define MCG_ATCVH_ATCVH_SHIFT 0
Jasper_lee 0:b16d94660a33 8698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
Jasper_lee 0:b16d94660a33 8699 /* ATCVL Bit Fields */
Jasper_lee 0:b16d94660a33 8700 #define MCG_ATCVL_ATCVL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8701 #define MCG_ATCVL_ATCVL_SHIFT 0
Jasper_lee 0:b16d94660a33 8702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
Jasper_lee 0:b16d94660a33 8703 /* C7 Bit Fields */
Jasper_lee 0:b16d94660a33 8704 #define MCG_C7_OSCSEL_MASK 0x3u
Jasper_lee 0:b16d94660a33 8705 #define MCG_C7_OSCSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 8706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
Jasper_lee 0:b16d94660a33 8707 /* C8 Bit Fields */
Jasper_lee 0:b16d94660a33 8708 #define MCG_C8_LOCS1_MASK 0x1u
Jasper_lee 0:b16d94660a33 8709 #define MCG_C8_LOCS1_SHIFT 0
Jasper_lee 0:b16d94660a33 8710 #define MCG_C8_CME1_MASK 0x20u
Jasper_lee 0:b16d94660a33 8711 #define MCG_C8_CME1_SHIFT 5
Jasper_lee 0:b16d94660a33 8712 #define MCG_C8_LOLRE_MASK 0x40u
Jasper_lee 0:b16d94660a33 8713 #define MCG_C8_LOLRE_SHIFT 6
Jasper_lee 0:b16d94660a33 8714 #define MCG_C8_LOCRE1_MASK 0x80u
Jasper_lee 0:b16d94660a33 8715 #define MCG_C8_LOCRE1_SHIFT 7
Jasper_lee 0:b16d94660a33 8716
Jasper_lee 0:b16d94660a33 8717 /*!
Jasper_lee 0:b16d94660a33 8718 * @}
Jasper_lee 0:b16d94660a33 8719 */ /* end of group MCG_Register_Masks */
Jasper_lee 0:b16d94660a33 8720
Jasper_lee 0:b16d94660a33 8721
Jasper_lee 0:b16d94660a33 8722 /* MCG - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 8723 /** Peripheral MCG base address */
Jasper_lee 0:b16d94660a33 8724 #define MCG_BASE (0x40064000u)
Jasper_lee 0:b16d94660a33 8725 /** Peripheral MCG base pointer */
Jasper_lee 0:b16d94660a33 8726 #define MCG ((MCG_Type *)MCG_BASE)
Jasper_lee 0:b16d94660a33 8727 #define MCG_BASE_PTR (MCG)
Jasper_lee 0:b16d94660a33 8728 /** Array initializer of MCG peripheral base addresses */
Jasper_lee 0:b16d94660a33 8729 #define MCG_BASE_ADDRS { MCG_BASE }
Jasper_lee 0:b16d94660a33 8730 /** Array initializer of MCG peripheral base pointers */
Jasper_lee 0:b16d94660a33 8731 #define MCG_BASE_PTRS { MCG }
Jasper_lee 0:b16d94660a33 8732
Jasper_lee 0:b16d94660a33 8733 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8734 -- MCG - Register accessor macros
Jasper_lee 0:b16d94660a33 8735 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8736
Jasper_lee 0:b16d94660a33 8737 /*!
Jasper_lee 0:b16d94660a33 8738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Jasper_lee 0:b16d94660a33 8739 * @{
Jasper_lee 0:b16d94660a33 8740 */
Jasper_lee 0:b16d94660a33 8741
Jasper_lee 0:b16d94660a33 8742
Jasper_lee 0:b16d94660a33 8743 /* MCG - Register instance definitions */
Jasper_lee 0:b16d94660a33 8744 /* MCG */
Jasper_lee 0:b16d94660a33 8745 #define MCG_C1 MCG_C1_REG(MCG)
Jasper_lee 0:b16d94660a33 8746 #define MCG_C2 MCG_C2_REG(MCG)
Jasper_lee 0:b16d94660a33 8747 #define MCG_C3 MCG_C3_REG(MCG)
Jasper_lee 0:b16d94660a33 8748 #define MCG_C4 MCG_C4_REG(MCG)
Jasper_lee 0:b16d94660a33 8749 #define MCG_C5 MCG_C5_REG(MCG)
Jasper_lee 0:b16d94660a33 8750 #define MCG_C6 MCG_C6_REG(MCG)
Jasper_lee 0:b16d94660a33 8751 #define MCG_S MCG_S_REG(MCG)
Jasper_lee 0:b16d94660a33 8752 #define MCG_SC MCG_SC_REG(MCG)
Jasper_lee 0:b16d94660a33 8753 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
Jasper_lee 0:b16d94660a33 8754 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
Jasper_lee 0:b16d94660a33 8755 #define MCG_C7 MCG_C7_REG(MCG)
Jasper_lee 0:b16d94660a33 8756 #define MCG_C8 MCG_C8_REG(MCG)
Jasper_lee 0:b16d94660a33 8757
Jasper_lee 0:b16d94660a33 8758 /*!
Jasper_lee 0:b16d94660a33 8759 * @}
Jasper_lee 0:b16d94660a33 8760 */ /* end of group MCG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8761
Jasper_lee 0:b16d94660a33 8762
Jasper_lee 0:b16d94660a33 8763 /*!
Jasper_lee 0:b16d94660a33 8764 * @}
Jasper_lee 0:b16d94660a33 8765 */ /* end of group MCG_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 8766
Jasper_lee 0:b16d94660a33 8767
Jasper_lee 0:b16d94660a33 8768 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8769 -- MCM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8770 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8771
Jasper_lee 0:b16d94660a33 8772 /*!
Jasper_lee 0:b16d94660a33 8773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8774 * @{
Jasper_lee 0:b16d94660a33 8775 */
Jasper_lee 0:b16d94660a33 8776
Jasper_lee 0:b16d94660a33 8777 /** MCM - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 8778 typedef struct {
Jasper_lee 0:b16d94660a33 8779 uint8_t RESERVED_0[8];
Jasper_lee 0:b16d94660a33 8780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
Jasper_lee 0:b16d94660a33 8781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
Jasper_lee 0:b16d94660a33 8782 __IO uint32_t CR; /**< Control Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 8783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 8784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 8785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 8786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
Jasper_lee 0:b16d94660a33 8787 uint8_t RESERVED_1[16];
Jasper_lee 0:b16d94660a33 8788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
Jasper_lee 0:b16d94660a33 8789 } MCM_Type, *MCM_MemMapPtr;
Jasper_lee 0:b16d94660a33 8790
Jasper_lee 0:b16d94660a33 8791 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8792 -- MCM - Register accessor macros
Jasper_lee 0:b16d94660a33 8793 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8794
Jasper_lee 0:b16d94660a33 8795 /*!
Jasper_lee 0:b16d94660a33 8796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Jasper_lee 0:b16d94660a33 8797 * @{
Jasper_lee 0:b16d94660a33 8798 */
Jasper_lee 0:b16d94660a33 8799
Jasper_lee 0:b16d94660a33 8800
Jasper_lee 0:b16d94660a33 8801 /* MCM - Register accessors */
Jasper_lee 0:b16d94660a33 8802 #define MCM_PLASC_REG(base) ((base)->PLASC)
Jasper_lee 0:b16d94660a33 8803 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
Jasper_lee 0:b16d94660a33 8804 #define MCM_CR_REG(base) ((base)->CR)
Jasper_lee 0:b16d94660a33 8805 #define MCM_ISCR_REG(base) ((base)->ISCR)
Jasper_lee 0:b16d94660a33 8806 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
Jasper_lee 0:b16d94660a33 8807 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
Jasper_lee 0:b16d94660a33 8808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
Jasper_lee 0:b16d94660a33 8809 #define MCM_PID_REG(base) ((base)->PID)
Jasper_lee 0:b16d94660a33 8810
Jasper_lee 0:b16d94660a33 8811 /*!
Jasper_lee 0:b16d94660a33 8812 * @}
Jasper_lee 0:b16d94660a33 8813 */ /* end of group MCM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8814
Jasper_lee 0:b16d94660a33 8815
Jasper_lee 0:b16d94660a33 8816 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8817 -- MCM Register Masks
Jasper_lee 0:b16d94660a33 8818 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8819
Jasper_lee 0:b16d94660a33 8820 /*!
Jasper_lee 0:b16d94660a33 8821 * @addtogroup MCM_Register_Masks MCM Register Masks
Jasper_lee 0:b16d94660a33 8822 * @{
Jasper_lee 0:b16d94660a33 8823 */
Jasper_lee 0:b16d94660a33 8824
Jasper_lee 0:b16d94660a33 8825 /* PLASC Bit Fields */
Jasper_lee 0:b16d94660a33 8826 #define MCM_PLASC_ASC_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8827 #define MCM_PLASC_ASC_SHIFT 0
Jasper_lee 0:b16d94660a33 8828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
Jasper_lee 0:b16d94660a33 8829 /* PLAMC Bit Fields */
Jasper_lee 0:b16d94660a33 8830 #define MCM_PLAMC_AMC_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8831 #define MCM_PLAMC_AMC_SHIFT 0
Jasper_lee 0:b16d94660a33 8832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
Jasper_lee 0:b16d94660a33 8833 /* CR Bit Fields */
Jasper_lee 0:b16d94660a33 8834 #define MCM_CR_SRAMUAP_MASK 0x3000000u
Jasper_lee 0:b16d94660a33 8835 #define MCM_CR_SRAMUAP_SHIFT 24
Jasper_lee 0:b16d94660a33 8836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
Jasper_lee 0:b16d94660a33 8837 #define MCM_CR_SRAMUWP_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 8838 #define MCM_CR_SRAMUWP_SHIFT 26
Jasper_lee 0:b16d94660a33 8839 #define MCM_CR_SRAMLAP_MASK 0x30000000u
Jasper_lee 0:b16d94660a33 8840 #define MCM_CR_SRAMLAP_SHIFT 28
Jasper_lee 0:b16d94660a33 8841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
Jasper_lee 0:b16d94660a33 8842 #define MCM_CR_SRAMLWP_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 8843 #define MCM_CR_SRAMLWP_SHIFT 30
Jasper_lee 0:b16d94660a33 8844 /* ISCR Bit Fields */
Jasper_lee 0:b16d94660a33 8845 #define MCM_ISCR_IRQ_MASK 0x2u
Jasper_lee 0:b16d94660a33 8846 #define MCM_ISCR_IRQ_SHIFT 1
Jasper_lee 0:b16d94660a33 8847 #define MCM_ISCR_NMI_MASK 0x4u
Jasper_lee 0:b16d94660a33 8848 #define MCM_ISCR_NMI_SHIFT 2
Jasper_lee 0:b16d94660a33 8849 #define MCM_ISCR_DHREQ_MASK 0x8u
Jasper_lee 0:b16d94660a33 8850 #define MCM_ISCR_DHREQ_SHIFT 3
Jasper_lee 0:b16d94660a33 8851 #define MCM_ISCR_FIOC_MASK 0x100u
Jasper_lee 0:b16d94660a33 8852 #define MCM_ISCR_FIOC_SHIFT 8
Jasper_lee 0:b16d94660a33 8853 #define MCM_ISCR_FDZC_MASK 0x200u
Jasper_lee 0:b16d94660a33 8854 #define MCM_ISCR_FDZC_SHIFT 9
Jasper_lee 0:b16d94660a33 8855 #define MCM_ISCR_FOFC_MASK 0x400u
Jasper_lee 0:b16d94660a33 8856 #define MCM_ISCR_FOFC_SHIFT 10
Jasper_lee 0:b16d94660a33 8857 #define MCM_ISCR_FUFC_MASK 0x800u
Jasper_lee 0:b16d94660a33 8858 #define MCM_ISCR_FUFC_SHIFT 11
Jasper_lee 0:b16d94660a33 8859 #define MCM_ISCR_FIXC_MASK 0x1000u
Jasper_lee 0:b16d94660a33 8860 #define MCM_ISCR_FIXC_SHIFT 12
Jasper_lee 0:b16d94660a33 8861 #define MCM_ISCR_FIDC_MASK 0x8000u
Jasper_lee 0:b16d94660a33 8862 #define MCM_ISCR_FIDC_SHIFT 15
Jasper_lee 0:b16d94660a33 8863 #define MCM_ISCR_FIOCE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 8864 #define MCM_ISCR_FIOCE_SHIFT 24
Jasper_lee 0:b16d94660a33 8865 #define MCM_ISCR_FDZCE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 8866 #define MCM_ISCR_FDZCE_SHIFT 25
Jasper_lee 0:b16d94660a33 8867 #define MCM_ISCR_FOFCE_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 8868 #define MCM_ISCR_FOFCE_SHIFT 26
Jasper_lee 0:b16d94660a33 8869 #define MCM_ISCR_FUFCE_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 8870 #define MCM_ISCR_FUFCE_SHIFT 27
Jasper_lee 0:b16d94660a33 8871 #define MCM_ISCR_FIXCE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 8872 #define MCM_ISCR_FIXCE_SHIFT 28
Jasper_lee 0:b16d94660a33 8873 #define MCM_ISCR_FIDCE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 8874 #define MCM_ISCR_FIDCE_SHIFT 31
Jasper_lee 0:b16d94660a33 8875 /* ETBCC Bit Fields */
Jasper_lee 0:b16d94660a33 8876 #define MCM_ETBCC_CNTEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 8877 #define MCM_ETBCC_CNTEN_SHIFT 0
Jasper_lee 0:b16d94660a33 8878 #define MCM_ETBCC_RSPT_MASK 0x6u
Jasper_lee 0:b16d94660a33 8879 #define MCM_ETBCC_RSPT_SHIFT 1
Jasper_lee 0:b16d94660a33 8880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
Jasper_lee 0:b16d94660a33 8881 #define MCM_ETBCC_RLRQ_MASK 0x8u
Jasper_lee 0:b16d94660a33 8882 #define MCM_ETBCC_RLRQ_SHIFT 3
Jasper_lee 0:b16d94660a33 8883 #define MCM_ETBCC_ETDIS_MASK 0x10u
Jasper_lee 0:b16d94660a33 8884 #define MCM_ETBCC_ETDIS_SHIFT 4
Jasper_lee 0:b16d94660a33 8885 #define MCM_ETBCC_ITDIS_MASK 0x20u
Jasper_lee 0:b16d94660a33 8886 #define MCM_ETBCC_ITDIS_SHIFT 5
Jasper_lee 0:b16d94660a33 8887 /* ETBRL Bit Fields */
Jasper_lee 0:b16d94660a33 8888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
Jasper_lee 0:b16d94660a33 8889 #define MCM_ETBRL_RELOAD_SHIFT 0
Jasper_lee 0:b16d94660a33 8890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
Jasper_lee 0:b16d94660a33 8891 /* ETBCNT Bit Fields */
Jasper_lee 0:b16d94660a33 8892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
Jasper_lee 0:b16d94660a33 8893 #define MCM_ETBCNT_COUNTER_SHIFT 0
Jasper_lee 0:b16d94660a33 8894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
Jasper_lee 0:b16d94660a33 8895 /* PID Bit Fields */
Jasper_lee 0:b16d94660a33 8896 #define MCM_PID_PID_MASK 0xFFu
Jasper_lee 0:b16d94660a33 8897 #define MCM_PID_PID_SHIFT 0
Jasper_lee 0:b16d94660a33 8898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
Jasper_lee 0:b16d94660a33 8899
Jasper_lee 0:b16d94660a33 8900 /*!
Jasper_lee 0:b16d94660a33 8901 * @}
Jasper_lee 0:b16d94660a33 8902 */ /* end of group MCM_Register_Masks */
Jasper_lee 0:b16d94660a33 8903
Jasper_lee 0:b16d94660a33 8904
Jasper_lee 0:b16d94660a33 8905 /* MCM - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 8906 /** Peripheral MCM base address */
Jasper_lee 0:b16d94660a33 8907 #define MCM_BASE (0xE0080000u)
Jasper_lee 0:b16d94660a33 8908 /** Peripheral MCM base pointer */
Jasper_lee 0:b16d94660a33 8909 #define MCM ((MCM_Type *)MCM_BASE)
Jasper_lee 0:b16d94660a33 8910 #define MCM_BASE_PTR (MCM)
Jasper_lee 0:b16d94660a33 8911 /** Array initializer of MCM peripheral base addresses */
Jasper_lee 0:b16d94660a33 8912 #define MCM_BASE_ADDRS { MCM_BASE }
Jasper_lee 0:b16d94660a33 8913 /** Array initializer of MCM peripheral base pointers */
Jasper_lee 0:b16d94660a33 8914 #define MCM_BASE_PTRS { MCM }
Jasper_lee 0:b16d94660a33 8915
Jasper_lee 0:b16d94660a33 8916 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8917 -- MCM - Register accessor macros
Jasper_lee 0:b16d94660a33 8918 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8919
Jasper_lee 0:b16d94660a33 8920 /*!
Jasper_lee 0:b16d94660a33 8921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Jasper_lee 0:b16d94660a33 8922 * @{
Jasper_lee 0:b16d94660a33 8923 */
Jasper_lee 0:b16d94660a33 8924
Jasper_lee 0:b16d94660a33 8925
Jasper_lee 0:b16d94660a33 8926 /* MCM - Register instance definitions */
Jasper_lee 0:b16d94660a33 8927 /* MCM */
Jasper_lee 0:b16d94660a33 8928 #define MCM_PLASC MCM_PLASC_REG(MCM)
Jasper_lee 0:b16d94660a33 8929 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
Jasper_lee 0:b16d94660a33 8930 #define MCM_CR MCM_CR_REG(MCM)
Jasper_lee 0:b16d94660a33 8931 #define MCM_ISCR MCM_ISCR_REG(MCM)
Jasper_lee 0:b16d94660a33 8932 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
Jasper_lee 0:b16d94660a33 8933 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
Jasper_lee 0:b16d94660a33 8934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
Jasper_lee 0:b16d94660a33 8935 #define MCM_PID MCM_PID_REG(MCM)
Jasper_lee 0:b16d94660a33 8936
Jasper_lee 0:b16d94660a33 8937 /*!
Jasper_lee 0:b16d94660a33 8938 * @}
Jasper_lee 0:b16d94660a33 8939 */ /* end of group MCM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8940
Jasper_lee 0:b16d94660a33 8941
Jasper_lee 0:b16d94660a33 8942 /*!
Jasper_lee 0:b16d94660a33 8943 * @}
Jasper_lee 0:b16d94660a33 8944 */ /* end of group MCM_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 8945
Jasper_lee 0:b16d94660a33 8946
Jasper_lee 0:b16d94660a33 8947 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8948 -- MPU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8949 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8950
Jasper_lee 0:b16d94660a33 8951 /*!
Jasper_lee 0:b16d94660a33 8952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
Jasper_lee 0:b16d94660a33 8953 * @{
Jasper_lee 0:b16d94660a33 8954 */
Jasper_lee 0:b16d94660a33 8955
Jasper_lee 0:b16d94660a33 8956 /** MPU - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 8957 typedef struct {
Jasper_lee 0:b16d94660a33 8958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 8959 uint8_t RESERVED_0[12];
Jasper_lee 0:b16d94660a33 8960 struct { /* offset: 0x10, array step: 0x8 */
Jasper_lee 0:b16d94660a33 8961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
Jasper_lee 0:b16d94660a33 8962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
Jasper_lee 0:b16d94660a33 8963 } SP[5];
Jasper_lee 0:b16d94660a33 8964 uint8_t RESERVED_1[968];
Jasper_lee 0:b16d94660a33 8965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
Jasper_lee 0:b16d94660a33 8966 uint8_t RESERVED_2[832];
Jasper_lee 0:b16d94660a33 8967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
Jasper_lee 0:b16d94660a33 8968 } MPU_Type, *MPU_MemMapPtr;
Jasper_lee 0:b16d94660a33 8969
Jasper_lee 0:b16d94660a33 8970 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8971 -- MPU - Register accessor macros
Jasper_lee 0:b16d94660a33 8972 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8973
Jasper_lee 0:b16d94660a33 8974 /*!
Jasper_lee 0:b16d94660a33 8975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
Jasper_lee 0:b16d94660a33 8976 * @{
Jasper_lee 0:b16d94660a33 8977 */
Jasper_lee 0:b16d94660a33 8978
Jasper_lee 0:b16d94660a33 8979
Jasper_lee 0:b16d94660a33 8980 /* MPU - Register accessors */
Jasper_lee 0:b16d94660a33 8981 #define MPU_CESR_REG(base) ((base)->CESR)
Jasper_lee 0:b16d94660a33 8982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
Jasper_lee 0:b16d94660a33 8983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
Jasper_lee 0:b16d94660a33 8984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
Jasper_lee 0:b16d94660a33 8985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
Jasper_lee 0:b16d94660a33 8986
Jasper_lee 0:b16d94660a33 8987 /*!
Jasper_lee 0:b16d94660a33 8988 * @}
Jasper_lee 0:b16d94660a33 8989 */ /* end of group MPU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 8990
Jasper_lee 0:b16d94660a33 8991
Jasper_lee 0:b16d94660a33 8992 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 8993 -- MPU Register Masks
Jasper_lee 0:b16d94660a33 8994 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 8995
Jasper_lee 0:b16d94660a33 8996 /*!
Jasper_lee 0:b16d94660a33 8997 * @addtogroup MPU_Register_Masks MPU Register Masks
Jasper_lee 0:b16d94660a33 8998 * @{
Jasper_lee 0:b16d94660a33 8999 */
Jasper_lee 0:b16d94660a33 9000
Jasper_lee 0:b16d94660a33 9001 /* CESR Bit Fields */
Jasper_lee 0:b16d94660a33 9002 #define MPU_CESR_VLD_MASK 0x1u
Jasper_lee 0:b16d94660a33 9003 #define MPU_CESR_VLD_SHIFT 0
Jasper_lee 0:b16d94660a33 9004 #define MPU_CESR_NRGD_MASK 0xF00u
Jasper_lee 0:b16d94660a33 9005 #define MPU_CESR_NRGD_SHIFT 8
Jasper_lee 0:b16d94660a33 9006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
Jasper_lee 0:b16d94660a33 9007 #define MPU_CESR_NSP_MASK 0xF000u
Jasper_lee 0:b16d94660a33 9008 #define MPU_CESR_NSP_SHIFT 12
Jasper_lee 0:b16d94660a33 9009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
Jasper_lee 0:b16d94660a33 9010 #define MPU_CESR_HRL_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 9011 #define MPU_CESR_HRL_SHIFT 16
Jasper_lee 0:b16d94660a33 9012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
Jasper_lee 0:b16d94660a33 9013 #define MPU_CESR_SPERR_MASK 0xF8000000u
Jasper_lee 0:b16d94660a33 9014 #define MPU_CESR_SPERR_SHIFT 27
Jasper_lee 0:b16d94660a33 9015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
Jasper_lee 0:b16d94660a33 9016 /* EAR Bit Fields */
Jasper_lee 0:b16d94660a33 9017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 9018 #define MPU_EAR_EADDR_SHIFT 0
Jasper_lee 0:b16d94660a33 9019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
Jasper_lee 0:b16d94660a33 9020 /* EDR Bit Fields */
Jasper_lee 0:b16d94660a33 9021 #define MPU_EDR_ERW_MASK 0x1u
Jasper_lee 0:b16d94660a33 9022 #define MPU_EDR_ERW_SHIFT 0
Jasper_lee 0:b16d94660a33 9023 #define MPU_EDR_EATTR_MASK 0xEu
Jasper_lee 0:b16d94660a33 9024 #define MPU_EDR_EATTR_SHIFT 1
Jasper_lee 0:b16d94660a33 9025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
Jasper_lee 0:b16d94660a33 9026 #define MPU_EDR_EMN_MASK 0xF0u
Jasper_lee 0:b16d94660a33 9027 #define MPU_EDR_EMN_SHIFT 4
Jasper_lee 0:b16d94660a33 9028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
Jasper_lee 0:b16d94660a33 9029 #define MPU_EDR_EPID_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 9030 #define MPU_EDR_EPID_SHIFT 8
Jasper_lee 0:b16d94660a33 9031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
Jasper_lee 0:b16d94660a33 9032 #define MPU_EDR_EACD_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 9033 #define MPU_EDR_EACD_SHIFT 16
Jasper_lee 0:b16d94660a33 9034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
Jasper_lee 0:b16d94660a33 9035 /* WORD Bit Fields */
Jasper_lee 0:b16d94660a33 9036 #define MPU_WORD_VLD_MASK 0x1u
Jasper_lee 0:b16d94660a33 9037 #define MPU_WORD_VLD_SHIFT 0
Jasper_lee 0:b16d94660a33 9038 #define MPU_WORD_M0UM_MASK 0x7u
Jasper_lee 0:b16d94660a33 9039 #define MPU_WORD_M0UM_SHIFT 0
Jasper_lee 0:b16d94660a33 9040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
Jasper_lee 0:b16d94660a33 9041 #define MPU_WORD_M0SM_MASK 0x18u
Jasper_lee 0:b16d94660a33 9042 #define MPU_WORD_M0SM_SHIFT 3
Jasper_lee 0:b16d94660a33 9043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
Jasper_lee 0:b16d94660a33 9044 #define MPU_WORD_M0PE_MASK 0x20u
Jasper_lee 0:b16d94660a33 9045 #define MPU_WORD_M0PE_SHIFT 5
Jasper_lee 0:b16d94660a33 9046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
Jasper_lee 0:b16d94660a33 9047 #define MPU_WORD_ENDADDR_SHIFT 5
Jasper_lee 0:b16d94660a33 9048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
Jasper_lee 0:b16d94660a33 9049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
Jasper_lee 0:b16d94660a33 9050 #define MPU_WORD_SRTADDR_SHIFT 5
Jasper_lee 0:b16d94660a33 9051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
Jasper_lee 0:b16d94660a33 9052 #define MPU_WORD_M1UM_MASK 0x1C0u
Jasper_lee 0:b16d94660a33 9053 #define MPU_WORD_M1UM_SHIFT 6
Jasper_lee 0:b16d94660a33 9054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
Jasper_lee 0:b16d94660a33 9055 #define MPU_WORD_M1SM_MASK 0x600u
Jasper_lee 0:b16d94660a33 9056 #define MPU_WORD_M1SM_SHIFT 9
Jasper_lee 0:b16d94660a33 9057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
Jasper_lee 0:b16d94660a33 9058 #define MPU_WORD_M1PE_MASK 0x800u
Jasper_lee 0:b16d94660a33 9059 #define MPU_WORD_M1PE_SHIFT 11
Jasper_lee 0:b16d94660a33 9060 #define MPU_WORD_M2UM_MASK 0x7000u
Jasper_lee 0:b16d94660a33 9061 #define MPU_WORD_M2UM_SHIFT 12
Jasper_lee 0:b16d94660a33 9062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
Jasper_lee 0:b16d94660a33 9063 #define MPU_WORD_M2SM_MASK 0x18000u
Jasper_lee 0:b16d94660a33 9064 #define MPU_WORD_M2SM_SHIFT 15
Jasper_lee 0:b16d94660a33 9065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
Jasper_lee 0:b16d94660a33 9066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 9067 #define MPU_WORD_PIDMASK_SHIFT 16
Jasper_lee 0:b16d94660a33 9068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
Jasper_lee 0:b16d94660a33 9069 #define MPU_WORD_M2PE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 9070 #define MPU_WORD_M2PE_SHIFT 17
Jasper_lee 0:b16d94660a33 9071 #define MPU_WORD_M3UM_MASK 0x1C0000u
Jasper_lee 0:b16d94660a33 9072 #define MPU_WORD_M3UM_SHIFT 18
Jasper_lee 0:b16d94660a33 9073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
Jasper_lee 0:b16d94660a33 9074 #define MPU_WORD_M3SM_MASK 0x600000u
Jasper_lee 0:b16d94660a33 9075 #define MPU_WORD_M3SM_SHIFT 21
Jasper_lee 0:b16d94660a33 9076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
Jasper_lee 0:b16d94660a33 9077 #define MPU_WORD_M3PE_MASK 0x800000u
Jasper_lee 0:b16d94660a33 9078 #define MPU_WORD_M3PE_SHIFT 23
Jasper_lee 0:b16d94660a33 9079 #define MPU_WORD_PID_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 9080 #define MPU_WORD_PID_SHIFT 24
Jasper_lee 0:b16d94660a33 9081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
Jasper_lee 0:b16d94660a33 9082 #define MPU_WORD_M4WE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 9083 #define MPU_WORD_M4WE_SHIFT 24
Jasper_lee 0:b16d94660a33 9084 #define MPU_WORD_M4RE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 9085 #define MPU_WORD_M4RE_SHIFT 25
Jasper_lee 0:b16d94660a33 9086 #define MPU_WORD_M5WE_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 9087 #define MPU_WORD_M5WE_SHIFT 26
Jasper_lee 0:b16d94660a33 9088 #define MPU_WORD_M5RE_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 9089 #define MPU_WORD_M5RE_SHIFT 27
Jasper_lee 0:b16d94660a33 9090 #define MPU_WORD_M6WE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 9091 #define MPU_WORD_M6WE_SHIFT 28
Jasper_lee 0:b16d94660a33 9092 #define MPU_WORD_M6RE_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 9093 #define MPU_WORD_M6RE_SHIFT 29
Jasper_lee 0:b16d94660a33 9094 #define MPU_WORD_M7WE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 9095 #define MPU_WORD_M7WE_SHIFT 30
Jasper_lee 0:b16d94660a33 9096 #define MPU_WORD_M7RE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 9097 #define MPU_WORD_M7RE_SHIFT 31
Jasper_lee 0:b16d94660a33 9098 /* RGDAAC Bit Fields */
Jasper_lee 0:b16d94660a33 9099 #define MPU_RGDAAC_M0UM_MASK 0x7u
Jasper_lee 0:b16d94660a33 9100 #define MPU_RGDAAC_M0UM_SHIFT 0
Jasper_lee 0:b16d94660a33 9101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
Jasper_lee 0:b16d94660a33 9102 #define MPU_RGDAAC_M0SM_MASK 0x18u
Jasper_lee 0:b16d94660a33 9103 #define MPU_RGDAAC_M0SM_SHIFT 3
Jasper_lee 0:b16d94660a33 9104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
Jasper_lee 0:b16d94660a33 9105 #define MPU_RGDAAC_M0PE_MASK 0x20u
Jasper_lee 0:b16d94660a33 9106 #define MPU_RGDAAC_M0PE_SHIFT 5
Jasper_lee 0:b16d94660a33 9107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
Jasper_lee 0:b16d94660a33 9108 #define MPU_RGDAAC_M1UM_SHIFT 6
Jasper_lee 0:b16d94660a33 9109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
Jasper_lee 0:b16d94660a33 9110 #define MPU_RGDAAC_M1SM_MASK 0x600u
Jasper_lee 0:b16d94660a33 9111 #define MPU_RGDAAC_M1SM_SHIFT 9
Jasper_lee 0:b16d94660a33 9112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
Jasper_lee 0:b16d94660a33 9113 #define MPU_RGDAAC_M1PE_MASK 0x800u
Jasper_lee 0:b16d94660a33 9114 #define MPU_RGDAAC_M1PE_SHIFT 11
Jasper_lee 0:b16d94660a33 9115 #define MPU_RGDAAC_M2UM_MASK 0x7000u
Jasper_lee 0:b16d94660a33 9116 #define MPU_RGDAAC_M2UM_SHIFT 12
Jasper_lee 0:b16d94660a33 9117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
Jasper_lee 0:b16d94660a33 9118 #define MPU_RGDAAC_M2SM_MASK 0x18000u
Jasper_lee 0:b16d94660a33 9119 #define MPU_RGDAAC_M2SM_SHIFT 15
Jasper_lee 0:b16d94660a33 9120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
Jasper_lee 0:b16d94660a33 9121 #define MPU_RGDAAC_M2PE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 9122 #define MPU_RGDAAC_M2PE_SHIFT 17
Jasper_lee 0:b16d94660a33 9123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
Jasper_lee 0:b16d94660a33 9124 #define MPU_RGDAAC_M3UM_SHIFT 18
Jasper_lee 0:b16d94660a33 9125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
Jasper_lee 0:b16d94660a33 9126 #define MPU_RGDAAC_M3SM_MASK 0x600000u
Jasper_lee 0:b16d94660a33 9127 #define MPU_RGDAAC_M3SM_SHIFT 21
Jasper_lee 0:b16d94660a33 9128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
Jasper_lee 0:b16d94660a33 9129 #define MPU_RGDAAC_M3PE_MASK 0x800000u
Jasper_lee 0:b16d94660a33 9130 #define MPU_RGDAAC_M3PE_SHIFT 23
Jasper_lee 0:b16d94660a33 9131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 9132 #define MPU_RGDAAC_M4WE_SHIFT 24
Jasper_lee 0:b16d94660a33 9133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 9134 #define MPU_RGDAAC_M4RE_SHIFT 25
Jasper_lee 0:b16d94660a33 9135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 9136 #define MPU_RGDAAC_M5WE_SHIFT 26
Jasper_lee 0:b16d94660a33 9137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 9138 #define MPU_RGDAAC_M5RE_SHIFT 27
Jasper_lee 0:b16d94660a33 9139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 9140 #define MPU_RGDAAC_M6WE_SHIFT 28
Jasper_lee 0:b16d94660a33 9141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 9142 #define MPU_RGDAAC_M6RE_SHIFT 29
Jasper_lee 0:b16d94660a33 9143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 9144 #define MPU_RGDAAC_M7WE_SHIFT 30
Jasper_lee 0:b16d94660a33 9145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 9146 #define MPU_RGDAAC_M7RE_SHIFT 31
Jasper_lee 0:b16d94660a33 9147
Jasper_lee 0:b16d94660a33 9148 /*!
Jasper_lee 0:b16d94660a33 9149 * @}
Jasper_lee 0:b16d94660a33 9150 */ /* end of group MPU_Register_Masks */
Jasper_lee 0:b16d94660a33 9151
Jasper_lee 0:b16d94660a33 9152
Jasper_lee 0:b16d94660a33 9153 /* MPU - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 9154 /** Peripheral MPU base address */
Jasper_lee 0:b16d94660a33 9155 #define MPU_BASE (0x4000D000u)
Jasper_lee 0:b16d94660a33 9156 /** Peripheral MPU base pointer */
Jasper_lee 0:b16d94660a33 9157 #define MPU ((MPU_Type *)MPU_BASE)
Jasper_lee 0:b16d94660a33 9158 #define MPU_BASE_PTR (MPU)
Jasper_lee 0:b16d94660a33 9159 /** Array initializer of MPU peripheral base addresses */
Jasper_lee 0:b16d94660a33 9160 #define MPU_BASE_ADDRS { MPU_BASE }
Jasper_lee 0:b16d94660a33 9161 /** Array initializer of MPU peripheral base pointers */
Jasper_lee 0:b16d94660a33 9162 #define MPU_BASE_PTRS { MPU }
Jasper_lee 0:b16d94660a33 9163
Jasper_lee 0:b16d94660a33 9164 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9165 -- MPU - Register accessor macros
Jasper_lee 0:b16d94660a33 9166 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9167
Jasper_lee 0:b16d94660a33 9168 /*!
Jasper_lee 0:b16d94660a33 9169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
Jasper_lee 0:b16d94660a33 9170 * @{
Jasper_lee 0:b16d94660a33 9171 */
Jasper_lee 0:b16d94660a33 9172
Jasper_lee 0:b16d94660a33 9173
Jasper_lee 0:b16d94660a33 9174 /* MPU - Register instance definitions */
Jasper_lee 0:b16d94660a33 9175 /* MPU */
Jasper_lee 0:b16d94660a33 9176 #define MPU_CESR MPU_CESR_REG(MPU)
Jasper_lee 0:b16d94660a33 9177 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
Jasper_lee 0:b16d94660a33 9178 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
Jasper_lee 0:b16d94660a33 9179 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
Jasper_lee 0:b16d94660a33 9180 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
Jasper_lee 0:b16d94660a33 9181 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
Jasper_lee 0:b16d94660a33 9182 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
Jasper_lee 0:b16d94660a33 9183 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
Jasper_lee 0:b16d94660a33 9184 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
Jasper_lee 0:b16d94660a33 9185 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
Jasper_lee 0:b16d94660a33 9186 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
Jasper_lee 0:b16d94660a33 9187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
Jasper_lee 0:b16d94660a33 9188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
Jasper_lee 0:b16d94660a33 9189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
Jasper_lee 0:b16d94660a33 9190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
Jasper_lee 0:b16d94660a33 9191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
Jasper_lee 0:b16d94660a33 9192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
Jasper_lee 0:b16d94660a33 9193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
Jasper_lee 0:b16d94660a33 9194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
Jasper_lee 0:b16d94660a33 9195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
Jasper_lee 0:b16d94660a33 9196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
Jasper_lee 0:b16d94660a33 9197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
Jasper_lee 0:b16d94660a33 9198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
Jasper_lee 0:b16d94660a33 9199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
Jasper_lee 0:b16d94660a33 9200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
Jasper_lee 0:b16d94660a33 9201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
Jasper_lee 0:b16d94660a33 9202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
Jasper_lee 0:b16d94660a33 9203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
Jasper_lee 0:b16d94660a33 9204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
Jasper_lee 0:b16d94660a33 9205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
Jasper_lee 0:b16d94660a33 9206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
Jasper_lee 0:b16d94660a33 9207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
Jasper_lee 0:b16d94660a33 9208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
Jasper_lee 0:b16d94660a33 9209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
Jasper_lee 0:b16d94660a33 9210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
Jasper_lee 0:b16d94660a33 9211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
Jasper_lee 0:b16d94660a33 9212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
Jasper_lee 0:b16d94660a33 9213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
Jasper_lee 0:b16d94660a33 9214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
Jasper_lee 0:b16d94660a33 9215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
Jasper_lee 0:b16d94660a33 9216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
Jasper_lee 0:b16d94660a33 9217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
Jasper_lee 0:b16d94660a33 9218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
Jasper_lee 0:b16d94660a33 9219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
Jasper_lee 0:b16d94660a33 9220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
Jasper_lee 0:b16d94660a33 9221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
Jasper_lee 0:b16d94660a33 9222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
Jasper_lee 0:b16d94660a33 9223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
Jasper_lee 0:b16d94660a33 9224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
Jasper_lee 0:b16d94660a33 9225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
Jasper_lee 0:b16d94660a33 9226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
Jasper_lee 0:b16d94660a33 9227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
Jasper_lee 0:b16d94660a33 9228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
Jasper_lee 0:b16d94660a33 9229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
Jasper_lee 0:b16d94660a33 9230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
Jasper_lee 0:b16d94660a33 9231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
Jasper_lee 0:b16d94660a33 9232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
Jasper_lee 0:b16d94660a33 9233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
Jasper_lee 0:b16d94660a33 9234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
Jasper_lee 0:b16d94660a33 9235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
Jasper_lee 0:b16d94660a33 9236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
Jasper_lee 0:b16d94660a33 9237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
Jasper_lee 0:b16d94660a33 9238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
Jasper_lee 0:b16d94660a33 9239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
Jasper_lee 0:b16d94660a33 9240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
Jasper_lee 0:b16d94660a33 9241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
Jasper_lee 0:b16d94660a33 9242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
Jasper_lee 0:b16d94660a33 9243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
Jasper_lee 0:b16d94660a33 9244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
Jasper_lee 0:b16d94660a33 9245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
Jasper_lee 0:b16d94660a33 9246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
Jasper_lee 0:b16d94660a33 9247
Jasper_lee 0:b16d94660a33 9248 /* MPU - Register array accessors */
Jasper_lee 0:b16d94660a33 9249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
Jasper_lee 0:b16d94660a33 9250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
Jasper_lee 0:b16d94660a33 9251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
Jasper_lee 0:b16d94660a33 9252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
Jasper_lee 0:b16d94660a33 9253
Jasper_lee 0:b16d94660a33 9254 /*!
Jasper_lee 0:b16d94660a33 9255 * @}
Jasper_lee 0:b16d94660a33 9256 */ /* end of group MPU_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9257
Jasper_lee 0:b16d94660a33 9258
Jasper_lee 0:b16d94660a33 9259 /*!
Jasper_lee 0:b16d94660a33 9260 * @}
Jasper_lee 0:b16d94660a33 9261 */ /* end of group MPU_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 9262
Jasper_lee 0:b16d94660a33 9263
Jasper_lee 0:b16d94660a33 9264 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9265 -- NV Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9266 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9267
Jasper_lee 0:b16d94660a33 9268 /*!
Jasper_lee 0:b16d94660a33 9269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9270 * @{
Jasper_lee 0:b16d94660a33 9271 */
Jasper_lee 0:b16d94660a33 9272
Jasper_lee 0:b16d94660a33 9273 /** NV - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 9274 typedef struct {
Jasper_lee 0:b16d94660a33 9275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
Jasper_lee 0:b16d94660a33 9276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
Jasper_lee 0:b16d94660a33 9277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
Jasper_lee 0:b16d94660a33 9278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
Jasper_lee 0:b16d94660a33 9279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
Jasper_lee 0:b16d94660a33 9280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
Jasper_lee 0:b16d94660a33 9281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
Jasper_lee 0:b16d94660a33 9282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
Jasper_lee 0:b16d94660a33 9283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 9284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
Jasper_lee 0:b16d94660a33 9285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
Jasper_lee 0:b16d94660a33 9286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
Jasper_lee 0:b16d94660a33 9287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 9288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
Jasper_lee 0:b16d94660a33 9289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
Jasper_lee 0:b16d94660a33 9290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
Jasper_lee 0:b16d94660a33 9291 } NV_Type, *NV_MemMapPtr;
Jasper_lee 0:b16d94660a33 9292
Jasper_lee 0:b16d94660a33 9293 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9294 -- NV - Register accessor macros
Jasper_lee 0:b16d94660a33 9295 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9296
Jasper_lee 0:b16d94660a33 9297 /*!
Jasper_lee 0:b16d94660a33 9298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Jasper_lee 0:b16d94660a33 9299 * @{
Jasper_lee 0:b16d94660a33 9300 */
Jasper_lee 0:b16d94660a33 9301
Jasper_lee 0:b16d94660a33 9302
Jasper_lee 0:b16d94660a33 9303 /* NV - Register accessors */
Jasper_lee 0:b16d94660a33 9304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
Jasper_lee 0:b16d94660a33 9305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
Jasper_lee 0:b16d94660a33 9306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
Jasper_lee 0:b16d94660a33 9307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
Jasper_lee 0:b16d94660a33 9308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
Jasper_lee 0:b16d94660a33 9309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
Jasper_lee 0:b16d94660a33 9310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
Jasper_lee 0:b16d94660a33 9311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
Jasper_lee 0:b16d94660a33 9312 #define NV_FPROT3_REG(base) ((base)->FPROT3)
Jasper_lee 0:b16d94660a33 9313 #define NV_FPROT2_REG(base) ((base)->FPROT2)
Jasper_lee 0:b16d94660a33 9314 #define NV_FPROT1_REG(base) ((base)->FPROT1)
Jasper_lee 0:b16d94660a33 9315 #define NV_FPROT0_REG(base) ((base)->FPROT0)
Jasper_lee 0:b16d94660a33 9316 #define NV_FSEC_REG(base) ((base)->FSEC)
Jasper_lee 0:b16d94660a33 9317 #define NV_FOPT_REG(base) ((base)->FOPT)
Jasper_lee 0:b16d94660a33 9318 #define NV_FEPROT_REG(base) ((base)->FEPROT)
Jasper_lee 0:b16d94660a33 9319 #define NV_FDPROT_REG(base) ((base)->FDPROT)
Jasper_lee 0:b16d94660a33 9320
Jasper_lee 0:b16d94660a33 9321 /*!
Jasper_lee 0:b16d94660a33 9322 * @}
Jasper_lee 0:b16d94660a33 9323 */ /* end of group NV_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9324
Jasper_lee 0:b16d94660a33 9325
Jasper_lee 0:b16d94660a33 9326 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9327 -- NV Register Masks
Jasper_lee 0:b16d94660a33 9328 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9329
Jasper_lee 0:b16d94660a33 9330 /*!
Jasper_lee 0:b16d94660a33 9331 * @addtogroup NV_Register_Masks NV Register Masks
Jasper_lee 0:b16d94660a33 9332 * @{
Jasper_lee 0:b16d94660a33 9333 */
Jasper_lee 0:b16d94660a33 9334
Jasper_lee 0:b16d94660a33 9335 /* BACKKEY3 Bit Fields */
Jasper_lee 0:b16d94660a33 9336 #define NV_BACKKEY3_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9337 #define NV_BACKKEY3_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
Jasper_lee 0:b16d94660a33 9339 /* BACKKEY2 Bit Fields */
Jasper_lee 0:b16d94660a33 9340 #define NV_BACKKEY2_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9341 #define NV_BACKKEY2_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
Jasper_lee 0:b16d94660a33 9343 /* BACKKEY1 Bit Fields */
Jasper_lee 0:b16d94660a33 9344 #define NV_BACKKEY1_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9345 #define NV_BACKKEY1_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
Jasper_lee 0:b16d94660a33 9347 /* BACKKEY0 Bit Fields */
Jasper_lee 0:b16d94660a33 9348 #define NV_BACKKEY0_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9349 #define NV_BACKKEY0_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
Jasper_lee 0:b16d94660a33 9351 /* BACKKEY7 Bit Fields */
Jasper_lee 0:b16d94660a33 9352 #define NV_BACKKEY7_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9353 #define NV_BACKKEY7_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
Jasper_lee 0:b16d94660a33 9355 /* BACKKEY6 Bit Fields */
Jasper_lee 0:b16d94660a33 9356 #define NV_BACKKEY6_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9357 #define NV_BACKKEY6_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
Jasper_lee 0:b16d94660a33 9359 /* BACKKEY5 Bit Fields */
Jasper_lee 0:b16d94660a33 9360 #define NV_BACKKEY5_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9361 #define NV_BACKKEY5_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
Jasper_lee 0:b16d94660a33 9363 /* BACKKEY4 Bit Fields */
Jasper_lee 0:b16d94660a33 9364 #define NV_BACKKEY4_KEY_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9365 #define NV_BACKKEY4_KEY_SHIFT 0
Jasper_lee 0:b16d94660a33 9366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
Jasper_lee 0:b16d94660a33 9367 /* FPROT3 Bit Fields */
Jasper_lee 0:b16d94660a33 9368 #define NV_FPROT3_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9369 #define NV_FPROT3_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
Jasper_lee 0:b16d94660a33 9371 /* FPROT2 Bit Fields */
Jasper_lee 0:b16d94660a33 9372 #define NV_FPROT2_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9373 #define NV_FPROT2_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
Jasper_lee 0:b16d94660a33 9375 /* FPROT1 Bit Fields */
Jasper_lee 0:b16d94660a33 9376 #define NV_FPROT1_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9377 #define NV_FPROT1_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
Jasper_lee 0:b16d94660a33 9379 /* FPROT0 Bit Fields */
Jasper_lee 0:b16d94660a33 9380 #define NV_FPROT0_PROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9381 #define NV_FPROT0_PROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
Jasper_lee 0:b16d94660a33 9383 /* FSEC Bit Fields */
Jasper_lee 0:b16d94660a33 9384 #define NV_FSEC_SEC_MASK 0x3u
Jasper_lee 0:b16d94660a33 9385 #define NV_FSEC_SEC_SHIFT 0
Jasper_lee 0:b16d94660a33 9386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
Jasper_lee 0:b16d94660a33 9387 #define NV_FSEC_FSLACC_MASK 0xCu
Jasper_lee 0:b16d94660a33 9388 #define NV_FSEC_FSLACC_SHIFT 2
Jasper_lee 0:b16d94660a33 9389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
Jasper_lee 0:b16d94660a33 9390 #define NV_FSEC_MEEN_MASK 0x30u
Jasper_lee 0:b16d94660a33 9391 #define NV_FSEC_MEEN_SHIFT 4
Jasper_lee 0:b16d94660a33 9392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
Jasper_lee 0:b16d94660a33 9393 #define NV_FSEC_KEYEN_MASK 0xC0u
Jasper_lee 0:b16d94660a33 9394 #define NV_FSEC_KEYEN_SHIFT 6
Jasper_lee 0:b16d94660a33 9395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
Jasper_lee 0:b16d94660a33 9396 /* FOPT Bit Fields */
Jasper_lee 0:b16d94660a33 9397 #define NV_FOPT_LPBOOT_MASK 0x1u
Jasper_lee 0:b16d94660a33 9398 #define NV_FOPT_LPBOOT_SHIFT 0
Jasper_lee 0:b16d94660a33 9399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
Jasper_lee 0:b16d94660a33 9400 #define NV_FOPT_EZPORT_DIS_SHIFT 1
Jasper_lee 0:b16d94660a33 9401 /* FEPROT Bit Fields */
Jasper_lee 0:b16d94660a33 9402 #define NV_FEPROT_EPROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9403 #define NV_FEPROT_EPROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
Jasper_lee 0:b16d94660a33 9405 /* FDPROT Bit Fields */
Jasper_lee 0:b16d94660a33 9406 #define NV_FDPROT_DPROT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9407 #define NV_FDPROT_DPROT_SHIFT 0
Jasper_lee 0:b16d94660a33 9408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
Jasper_lee 0:b16d94660a33 9409
Jasper_lee 0:b16d94660a33 9410 /*!
Jasper_lee 0:b16d94660a33 9411 * @}
Jasper_lee 0:b16d94660a33 9412 */ /* end of group NV_Register_Masks */
Jasper_lee 0:b16d94660a33 9413
Jasper_lee 0:b16d94660a33 9414
Jasper_lee 0:b16d94660a33 9415 /* NV - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 9416 /** Peripheral FTFE_FlashConfig base address */
Jasper_lee 0:b16d94660a33 9417 #define FTFE_FlashConfig_BASE (0x400u)
Jasper_lee 0:b16d94660a33 9418 /** Peripheral FTFE_FlashConfig base pointer */
Jasper_lee 0:b16d94660a33 9419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
Jasper_lee 0:b16d94660a33 9420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9421 /** Array initializer of NV peripheral base addresses */
Jasper_lee 0:b16d94660a33 9422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
Jasper_lee 0:b16d94660a33 9423 /** Array initializer of NV peripheral base pointers */
Jasper_lee 0:b16d94660a33 9424 #define NV_BASE_PTRS { FTFE_FlashConfig }
Jasper_lee 0:b16d94660a33 9425
Jasper_lee 0:b16d94660a33 9426 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9427 -- NV - Register accessor macros
Jasper_lee 0:b16d94660a33 9428 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9429
Jasper_lee 0:b16d94660a33 9430 /*!
Jasper_lee 0:b16d94660a33 9431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Jasper_lee 0:b16d94660a33 9432 * @{
Jasper_lee 0:b16d94660a33 9433 */
Jasper_lee 0:b16d94660a33 9434
Jasper_lee 0:b16d94660a33 9435
Jasper_lee 0:b16d94660a33 9436 /* NV - Register instance definitions */
Jasper_lee 0:b16d94660a33 9437 /* FTFE_FlashConfig */
Jasper_lee 0:b16d94660a33 9438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
Jasper_lee 0:b16d94660a33 9454
Jasper_lee 0:b16d94660a33 9455 /*!
Jasper_lee 0:b16d94660a33 9456 * @}
Jasper_lee 0:b16d94660a33 9457 */ /* end of group NV_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9458
Jasper_lee 0:b16d94660a33 9459
Jasper_lee 0:b16d94660a33 9460 /*!
Jasper_lee 0:b16d94660a33 9461 * @}
Jasper_lee 0:b16d94660a33 9462 */ /* end of group NV_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 9463
Jasper_lee 0:b16d94660a33 9464
Jasper_lee 0:b16d94660a33 9465 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9466 -- OSC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9467 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9468
Jasper_lee 0:b16d94660a33 9469 /*!
Jasper_lee 0:b16d94660a33 9470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9471 * @{
Jasper_lee 0:b16d94660a33 9472 */
Jasper_lee 0:b16d94660a33 9473
Jasper_lee 0:b16d94660a33 9474 /** OSC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 9475 typedef struct {
Jasper_lee 0:b16d94660a33 9476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 9477 } OSC_Type, *OSC_MemMapPtr;
Jasper_lee 0:b16d94660a33 9478
Jasper_lee 0:b16d94660a33 9479 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9480 -- OSC - Register accessor macros
Jasper_lee 0:b16d94660a33 9481 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9482
Jasper_lee 0:b16d94660a33 9483 /*!
Jasper_lee 0:b16d94660a33 9484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Jasper_lee 0:b16d94660a33 9485 * @{
Jasper_lee 0:b16d94660a33 9486 */
Jasper_lee 0:b16d94660a33 9487
Jasper_lee 0:b16d94660a33 9488
Jasper_lee 0:b16d94660a33 9489 /* OSC - Register accessors */
Jasper_lee 0:b16d94660a33 9490 #define OSC_CR_REG(base) ((base)->CR)
Jasper_lee 0:b16d94660a33 9491
Jasper_lee 0:b16d94660a33 9492 /*!
Jasper_lee 0:b16d94660a33 9493 * @}
Jasper_lee 0:b16d94660a33 9494 */ /* end of group OSC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9495
Jasper_lee 0:b16d94660a33 9496
Jasper_lee 0:b16d94660a33 9497 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9498 -- OSC Register Masks
Jasper_lee 0:b16d94660a33 9499 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9500
Jasper_lee 0:b16d94660a33 9501 /*!
Jasper_lee 0:b16d94660a33 9502 * @addtogroup OSC_Register_Masks OSC Register Masks
Jasper_lee 0:b16d94660a33 9503 * @{
Jasper_lee 0:b16d94660a33 9504 */
Jasper_lee 0:b16d94660a33 9505
Jasper_lee 0:b16d94660a33 9506 /* CR Bit Fields */
Jasper_lee 0:b16d94660a33 9507 #define OSC_CR_SC16P_MASK 0x1u
Jasper_lee 0:b16d94660a33 9508 #define OSC_CR_SC16P_SHIFT 0
Jasper_lee 0:b16d94660a33 9509 #define OSC_CR_SC8P_MASK 0x2u
Jasper_lee 0:b16d94660a33 9510 #define OSC_CR_SC8P_SHIFT 1
Jasper_lee 0:b16d94660a33 9511 #define OSC_CR_SC4P_MASK 0x4u
Jasper_lee 0:b16d94660a33 9512 #define OSC_CR_SC4P_SHIFT 2
Jasper_lee 0:b16d94660a33 9513 #define OSC_CR_SC2P_MASK 0x8u
Jasper_lee 0:b16d94660a33 9514 #define OSC_CR_SC2P_SHIFT 3
Jasper_lee 0:b16d94660a33 9515 #define OSC_CR_EREFSTEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 9516 #define OSC_CR_EREFSTEN_SHIFT 5
Jasper_lee 0:b16d94660a33 9517 #define OSC_CR_ERCLKEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 9518 #define OSC_CR_ERCLKEN_SHIFT 7
Jasper_lee 0:b16d94660a33 9519
Jasper_lee 0:b16d94660a33 9520 /*!
Jasper_lee 0:b16d94660a33 9521 * @}
Jasper_lee 0:b16d94660a33 9522 */ /* end of group OSC_Register_Masks */
Jasper_lee 0:b16d94660a33 9523
Jasper_lee 0:b16d94660a33 9524
Jasper_lee 0:b16d94660a33 9525 /* OSC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 9526 /** Peripheral OSC base address */
Jasper_lee 0:b16d94660a33 9527 #define OSC_BASE (0x40065000u)
Jasper_lee 0:b16d94660a33 9528 /** Peripheral OSC base pointer */
Jasper_lee 0:b16d94660a33 9529 #define OSC ((OSC_Type *)OSC_BASE)
Jasper_lee 0:b16d94660a33 9530 #define OSC_BASE_PTR (OSC)
Jasper_lee 0:b16d94660a33 9531 /** Array initializer of OSC peripheral base addresses */
Jasper_lee 0:b16d94660a33 9532 #define OSC_BASE_ADDRS { OSC_BASE }
Jasper_lee 0:b16d94660a33 9533 /** Array initializer of OSC peripheral base pointers */
Jasper_lee 0:b16d94660a33 9534 #define OSC_BASE_PTRS { OSC }
Jasper_lee 0:b16d94660a33 9535
Jasper_lee 0:b16d94660a33 9536 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9537 -- OSC - Register accessor macros
Jasper_lee 0:b16d94660a33 9538 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9539
Jasper_lee 0:b16d94660a33 9540 /*!
Jasper_lee 0:b16d94660a33 9541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Jasper_lee 0:b16d94660a33 9542 * @{
Jasper_lee 0:b16d94660a33 9543 */
Jasper_lee 0:b16d94660a33 9544
Jasper_lee 0:b16d94660a33 9545
Jasper_lee 0:b16d94660a33 9546 /* OSC - Register instance definitions */
Jasper_lee 0:b16d94660a33 9547 /* OSC */
Jasper_lee 0:b16d94660a33 9548 #define OSC_CR OSC_CR_REG(OSC)
Jasper_lee 0:b16d94660a33 9549
Jasper_lee 0:b16d94660a33 9550 /*!
Jasper_lee 0:b16d94660a33 9551 * @}
Jasper_lee 0:b16d94660a33 9552 */ /* end of group OSC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9553
Jasper_lee 0:b16d94660a33 9554
Jasper_lee 0:b16d94660a33 9555 /*!
Jasper_lee 0:b16d94660a33 9556 * @}
Jasper_lee 0:b16d94660a33 9557 */ /* end of group OSC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 9558
Jasper_lee 0:b16d94660a33 9559
Jasper_lee 0:b16d94660a33 9560 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9561 -- PDB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9562 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9563
Jasper_lee 0:b16d94660a33 9564 /*!
Jasper_lee 0:b16d94660a33 9565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9566 * @{
Jasper_lee 0:b16d94660a33 9567 */
Jasper_lee 0:b16d94660a33 9568
Jasper_lee 0:b16d94660a33 9569 /** PDB - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 9570 typedef struct {
Jasper_lee 0:b16d94660a33 9571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 9572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 9573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 9574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
Jasper_lee 0:b16d94660a33 9575 struct { /* offset: 0x10, array step: 0x28 */
Jasper_lee 0:b16d94660a33 9576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
Jasper_lee 0:b16d94660a33 9577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
Jasper_lee 0:b16d94660a33 9578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
Jasper_lee 0:b16d94660a33 9579 uint8_t RESERVED_0[24];
Jasper_lee 0:b16d94660a33 9580 } CH[2];
Jasper_lee 0:b16d94660a33 9581 uint8_t RESERVED_0[240];
Jasper_lee 0:b16d94660a33 9582 struct { /* offset: 0x150, array step: 0x8 */
Jasper_lee 0:b16d94660a33 9583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
Jasper_lee 0:b16d94660a33 9584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
Jasper_lee 0:b16d94660a33 9585 } DAC[2];
Jasper_lee 0:b16d94660a33 9586 uint8_t RESERVED_1[48];
Jasper_lee 0:b16d94660a33 9587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
Jasper_lee 0:b16d94660a33 9588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
Jasper_lee 0:b16d94660a33 9589 } PDB_Type, *PDB_MemMapPtr;
Jasper_lee 0:b16d94660a33 9590
Jasper_lee 0:b16d94660a33 9591 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9592 -- PDB - Register accessor macros
Jasper_lee 0:b16d94660a33 9593 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9594
Jasper_lee 0:b16d94660a33 9595 /*!
Jasper_lee 0:b16d94660a33 9596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
Jasper_lee 0:b16d94660a33 9597 * @{
Jasper_lee 0:b16d94660a33 9598 */
Jasper_lee 0:b16d94660a33 9599
Jasper_lee 0:b16d94660a33 9600
Jasper_lee 0:b16d94660a33 9601 /* PDB - Register accessors */
Jasper_lee 0:b16d94660a33 9602 #define PDB_SC_REG(base) ((base)->SC)
Jasper_lee 0:b16d94660a33 9603 #define PDB_MOD_REG(base) ((base)->MOD)
Jasper_lee 0:b16d94660a33 9604 #define PDB_CNT_REG(base) ((base)->CNT)
Jasper_lee 0:b16d94660a33 9605 #define PDB_IDLY_REG(base) ((base)->IDLY)
Jasper_lee 0:b16d94660a33 9606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
Jasper_lee 0:b16d94660a33 9607 #define PDB_S_REG(base,index) ((base)->CH[index].S)
Jasper_lee 0:b16d94660a33 9608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
Jasper_lee 0:b16d94660a33 9609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
Jasper_lee 0:b16d94660a33 9610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
Jasper_lee 0:b16d94660a33 9611 #define PDB_POEN_REG(base) ((base)->POEN)
Jasper_lee 0:b16d94660a33 9612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
Jasper_lee 0:b16d94660a33 9613
Jasper_lee 0:b16d94660a33 9614 /*!
Jasper_lee 0:b16d94660a33 9615 * @}
Jasper_lee 0:b16d94660a33 9616 */ /* end of group PDB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9617
Jasper_lee 0:b16d94660a33 9618
Jasper_lee 0:b16d94660a33 9619 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9620 -- PDB Register Masks
Jasper_lee 0:b16d94660a33 9621 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9622
Jasper_lee 0:b16d94660a33 9623 /*!
Jasper_lee 0:b16d94660a33 9624 * @addtogroup PDB_Register_Masks PDB Register Masks
Jasper_lee 0:b16d94660a33 9625 * @{
Jasper_lee 0:b16d94660a33 9626 */
Jasper_lee 0:b16d94660a33 9627
Jasper_lee 0:b16d94660a33 9628 /* SC Bit Fields */
Jasper_lee 0:b16d94660a33 9629 #define PDB_SC_LDOK_MASK 0x1u
Jasper_lee 0:b16d94660a33 9630 #define PDB_SC_LDOK_SHIFT 0
Jasper_lee 0:b16d94660a33 9631 #define PDB_SC_CONT_MASK 0x2u
Jasper_lee 0:b16d94660a33 9632 #define PDB_SC_CONT_SHIFT 1
Jasper_lee 0:b16d94660a33 9633 #define PDB_SC_MULT_MASK 0xCu
Jasper_lee 0:b16d94660a33 9634 #define PDB_SC_MULT_SHIFT 2
Jasper_lee 0:b16d94660a33 9635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
Jasper_lee 0:b16d94660a33 9636 #define PDB_SC_PDBIE_MASK 0x20u
Jasper_lee 0:b16d94660a33 9637 #define PDB_SC_PDBIE_SHIFT 5
Jasper_lee 0:b16d94660a33 9638 #define PDB_SC_PDBIF_MASK 0x40u
Jasper_lee 0:b16d94660a33 9639 #define PDB_SC_PDBIF_SHIFT 6
Jasper_lee 0:b16d94660a33 9640 #define PDB_SC_PDBEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 9641 #define PDB_SC_PDBEN_SHIFT 7
Jasper_lee 0:b16d94660a33 9642 #define PDB_SC_TRGSEL_MASK 0xF00u
Jasper_lee 0:b16d94660a33 9643 #define PDB_SC_TRGSEL_SHIFT 8
Jasper_lee 0:b16d94660a33 9644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
Jasper_lee 0:b16d94660a33 9645 #define PDB_SC_PRESCALER_MASK 0x7000u
Jasper_lee 0:b16d94660a33 9646 #define PDB_SC_PRESCALER_SHIFT 12
Jasper_lee 0:b16d94660a33 9647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
Jasper_lee 0:b16d94660a33 9648 #define PDB_SC_DMAEN_MASK 0x8000u
Jasper_lee 0:b16d94660a33 9649 #define PDB_SC_DMAEN_SHIFT 15
Jasper_lee 0:b16d94660a33 9650 #define PDB_SC_SWTRIG_MASK 0x10000u
Jasper_lee 0:b16d94660a33 9651 #define PDB_SC_SWTRIG_SHIFT 16
Jasper_lee 0:b16d94660a33 9652 #define PDB_SC_PDBEIE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 9653 #define PDB_SC_PDBEIE_SHIFT 17
Jasper_lee 0:b16d94660a33 9654 #define PDB_SC_LDMOD_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 9655 #define PDB_SC_LDMOD_SHIFT 18
Jasper_lee 0:b16d94660a33 9656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
Jasper_lee 0:b16d94660a33 9657 /* MOD Bit Fields */
Jasper_lee 0:b16d94660a33 9658 #define PDB_MOD_MOD_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9659 #define PDB_MOD_MOD_SHIFT 0
Jasper_lee 0:b16d94660a33 9660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
Jasper_lee 0:b16d94660a33 9661 /* CNT Bit Fields */
Jasper_lee 0:b16d94660a33 9662 #define PDB_CNT_CNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9663 #define PDB_CNT_CNT_SHIFT 0
Jasper_lee 0:b16d94660a33 9664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
Jasper_lee 0:b16d94660a33 9665 /* IDLY Bit Fields */
Jasper_lee 0:b16d94660a33 9666 #define PDB_IDLY_IDLY_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9667 #define PDB_IDLY_IDLY_SHIFT 0
Jasper_lee 0:b16d94660a33 9668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
Jasper_lee 0:b16d94660a33 9669 /* C1 Bit Fields */
Jasper_lee 0:b16d94660a33 9670 #define PDB_C1_EN_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9671 #define PDB_C1_EN_SHIFT 0
Jasper_lee 0:b16d94660a33 9672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
Jasper_lee 0:b16d94660a33 9673 #define PDB_C1_TOS_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 9674 #define PDB_C1_TOS_SHIFT 8
Jasper_lee 0:b16d94660a33 9675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
Jasper_lee 0:b16d94660a33 9676 #define PDB_C1_BB_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 9677 #define PDB_C1_BB_SHIFT 16
Jasper_lee 0:b16d94660a33 9678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
Jasper_lee 0:b16d94660a33 9679 /* S Bit Fields */
Jasper_lee 0:b16d94660a33 9680 #define PDB_S_ERR_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9681 #define PDB_S_ERR_SHIFT 0
Jasper_lee 0:b16d94660a33 9682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
Jasper_lee 0:b16d94660a33 9683 #define PDB_S_CF_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 9684 #define PDB_S_CF_SHIFT 16
Jasper_lee 0:b16d94660a33 9685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
Jasper_lee 0:b16d94660a33 9686 /* DLY Bit Fields */
Jasper_lee 0:b16d94660a33 9687 #define PDB_DLY_DLY_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9688 #define PDB_DLY_DLY_SHIFT 0
Jasper_lee 0:b16d94660a33 9689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
Jasper_lee 0:b16d94660a33 9690 /* INTC Bit Fields */
Jasper_lee 0:b16d94660a33 9691 #define PDB_INTC_TOE_MASK 0x1u
Jasper_lee 0:b16d94660a33 9692 #define PDB_INTC_TOE_SHIFT 0
Jasper_lee 0:b16d94660a33 9693 #define PDB_INTC_EXT_MASK 0x2u
Jasper_lee 0:b16d94660a33 9694 #define PDB_INTC_EXT_SHIFT 1
Jasper_lee 0:b16d94660a33 9695 /* INT Bit Fields */
Jasper_lee 0:b16d94660a33 9696 #define PDB_INT_INT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9697 #define PDB_INT_INT_SHIFT 0
Jasper_lee 0:b16d94660a33 9698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
Jasper_lee 0:b16d94660a33 9699 /* POEN Bit Fields */
Jasper_lee 0:b16d94660a33 9700 #define PDB_POEN_POEN_MASK 0xFFu
Jasper_lee 0:b16d94660a33 9701 #define PDB_POEN_POEN_SHIFT 0
Jasper_lee 0:b16d94660a33 9702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
Jasper_lee 0:b16d94660a33 9703 /* PODLY Bit Fields */
Jasper_lee 0:b16d94660a33 9704 #define PDB_PODLY_DLY2_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 9705 #define PDB_PODLY_DLY2_SHIFT 0
Jasper_lee 0:b16d94660a33 9706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
Jasper_lee 0:b16d94660a33 9707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 9708 #define PDB_PODLY_DLY1_SHIFT 16
Jasper_lee 0:b16d94660a33 9709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
Jasper_lee 0:b16d94660a33 9710
Jasper_lee 0:b16d94660a33 9711 /*!
Jasper_lee 0:b16d94660a33 9712 * @}
Jasper_lee 0:b16d94660a33 9713 */ /* end of group PDB_Register_Masks */
Jasper_lee 0:b16d94660a33 9714
Jasper_lee 0:b16d94660a33 9715
Jasper_lee 0:b16d94660a33 9716 /* PDB - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 9717 /** Peripheral PDB0 base address */
Jasper_lee 0:b16d94660a33 9718 #define PDB0_BASE (0x40036000u)
Jasper_lee 0:b16d94660a33 9719 /** Peripheral PDB0 base pointer */
Jasper_lee 0:b16d94660a33 9720 #define PDB0 ((PDB_Type *)PDB0_BASE)
Jasper_lee 0:b16d94660a33 9721 #define PDB0_BASE_PTR (PDB0)
Jasper_lee 0:b16d94660a33 9722 /** Array initializer of PDB peripheral base addresses */
Jasper_lee 0:b16d94660a33 9723 #define PDB_BASE_ADDRS { PDB0_BASE }
Jasper_lee 0:b16d94660a33 9724 /** Array initializer of PDB peripheral base pointers */
Jasper_lee 0:b16d94660a33 9725 #define PDB_BASE_PTRS { PDB0 }
Jasper_lee 0:b16d94660a33 9726 /** Interrupt vectors for the PDB peripheral type */
Jasper_lee 0:b16d94660a33 9727 #define PDB_IRQS { PDB0_IRQn }
Jasper_lee 0:b16d94660a33 9728
Jasper_lee 0:b16d94660a33 9729 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9730 -- PDB - Register accessor macros
Jasper_lee 0:b16d94660a33 9731 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9732
Jasper_lee 0:b16d94660a33 9733 /*!
Jasper_lee 0:b16d94660a33 9734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
Jasper_lee 0:b16d94660a33 9735 * @{
Jasper_lee 0:b16d94660a33 9736 */
Jasper_lee 0:b16d94660a33 9737
Jasper_lee 0:b16d94660a33 9738
Jasper_lee 0:b16d94660a33 9739 /* PDB - Register instance definitions */
Jasper_lee 0:b16d94660a33 9740 /* PDB0 */
Jasper_lee 0:b16d94660a33 9741 #define PDB0_SC PDB_SC_REG(PDB0)
Jasper_lee 0:b16d94660a33 9742 #define PDB0_MOD PDB_MOD_REG(PDB0)
Jasper_lee 0:b16d94660a33 9743 #define PDB0_CNT PDB_CNT_REG(PDB0)
Jasper_lee 0:b16d94660a33 9744 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
Jasper_lee 0:b16d94660a33 9745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
Jasper_lee 0:b16d94660a33 9746 #define PDB0_CH0S PDB_S_REG(PDB0,0)
Jasper_lee 0:b16d94660a33 9747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
Jasper_lee 0:b16d94660a33 9748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
Jasper_lee 0:b16d94660a33 9749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
Jasper_lee 0:b16d94660a33 9750 #define PDB0_CH1S PDB_S_REG(PDB0,1)
Jasper_lee 0:b16d94660a33 9751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
Jasper_lee 0:b16d94660a33 9752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
Jasper_lee 0:b16d94660a33 9753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
Jasper_lee 0:b16d94660a33 9754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
Jasper_lee 0:b16d94660a33 9755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
Jasper_lee 0:b16d94660a33 9756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
Jasper_lee 0:b16d94660a33 9757 #define PDB0_POEN PDB_POEN_REG(PDB0)
Jasper_lee 0:b16d94660a33 9758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
Jasper_lee 0:b16d94660a33 9759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
Jasper_lee 0:b16d94660a33 9760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
Jasper_lee 0:b16d94660a33 9761
Jasper_lee 0:b16d94660a33 9762 /* PDB - Register array accessors */
Jasper_lee 0:b16d94660a33 9763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
Jasper_lee 0:b16d94660a33 9764 #define PDB0_S(index) PDB_S_REG(PDB0,index)
Jasper_lee 0:b16d94660a33 9765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
Jasper_lee 0:b16d94660a33 9766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
Jasper_lee 0:b16d94660a33 9767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
Jasper_lee 0:b16d94660a33 9768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
Jasper_lee 0:b16d94660a33 9769
Jasper_lee 0:b16d94660a33 9770 /*!
Jasper_lee 0:b16d94660a33 9771 * @}
Jasper_lee 0:b16d94660a33 9772 */ /* end of group PDB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9773
Jasper_lee 0:b16d94660a33 9774
Jasper_lee 0:b16d94660a33 9775 /*!
Jasper_lee 0:b16d94660a33 9776 * @}
Jasper_lee 0:b16d94660a33 9777 */ /* end of group PDB_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 9778
Jasper_lee 0:b16d94660a33 9779
Jasper_lee 0:b16d94660a33 9780 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9781 -- PIT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9782 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9783
Jasper_lee 0:b16d94660a33 9784 /*!
Jasper_lee 0:b16d94660a33 9785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9786 * @{
Jasper_lee 0:b16d94660a33 9787 */
Jasper_lee 0:b16d94660a33 9788
Jasper_lee 0:b16d94660a33 9789 /** PIT - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 9790 typedef struct {
Jasper_lee 0:b16d94660a33 9791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 9792 uint8_t RESERVED_0[252];
Jasper_lee 0:b16d94660a33 9793 struct { /* offset: 0x100, array step: 0x10 */
Jasper_lee 0:b16d94660a33 9794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
Jasper_lee 0:b16d94660a33 9795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
Jasper_lee 0:b16d94660a33 9796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
Jasper_lee 0:b16d94660a33 9797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
Jasper_lee 0:b16d94660a33 9798 } CHANNEL[4];
Jasper_lee 0:b16d94660a33 9799 } PIT_Type, *PIT_MemMapPtr;
Jasper_lee 0:b16d94660a33 9800
Jasper_lee 0:b16d94660a33 9801 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9802 -- PIT - Register accessor macros
Jasper_lee 0:b16d94660a33 9803 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9804
Jasper_lee 0:b16d94660a33 9805 /*!
Jasper_lee 0:b16d94660a33 9806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Jasper_lee 0:b16d94660a33 9807 * @{
Jasper_lee 0:b16d94660a33 9808 */
Jasper_lee 0:b16d94660a33 9809
Jasper_lee 0:b16d94660a33 9810
Jasper_lee 0:b16d94660a33 9811 /* PIT - Register accessors */
Jasper_lee 0:b16d94660a33 9812 #define PIT_MCR_REG(base) ((base)->MCR)
Jasper_lee 0:b16d94660a33 9813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
Jasper_lee 0:b16d94660a33 9814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
Jasper_lee 0:b16d94660a33 9815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
Jasper_lee 0:b16d94660a33 9816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
Jasper_lee 0:b16d94660a33 9817
Jasper_lee 0:b16d94660a33 9818 /*!
Jasper_lee 0:b16d94660a33 9819 * @}
Jasper_lee 0:b16d94660a33 9820 */ /* end of group PIT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9821
Jasper_lee 0:b16d94660a33 9822
Jasper_lee 0:b16d94660a33 9823 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9824 -- PIT Register Masks
Jasper_lee 0:b16d94660a33 9825 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9826
Jasper_lee 0:b16d94660a33 9827 /*!
Jasper_lee 0:b16d94660a33 9828 * @addtogroup PIT_Register_Masks PIT Register Masks
Jasper_lee 0:b16d94660a33 9829 * @{
Jasper_lee 0:b16d94660a33 9830 */
Jasper_lee 0:b16d94660a33 9831
Jasper_lee 0:b16d94660a33 9832 /* MCR Bit Fields */
Jasper_lee 0:b16d94660a33 9833 #define PIT_MCR_FRZ_MASK 0x1u
Jasper_lee 0:b16d94660a33 9834 #define PIT_MCR_FRZ_SHIFT 0
Jasper_lee 0:b16d94660a33 9835 #define PIT_MCR_MDIS_MASK 0x2u
Jasper_lee 0:b16d94660a33 9836 #define PIT_MCR_MDIS_SHIFT 1
Jasper_lee 0:b16d94660a33 9837 /* LDVAL Bit Fields */
Jasper_lee 0:b16d94660a33 9838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 9839 #define PIT_LDVAL_TSV_SHIFT 0
Jasper_lee 0:b16d94660a33 9840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
Jasper_lee 0:b16d94660a33 9841 /* CVAL Bit Fields */
Jasper_lee 0:b16d94660a33 9842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 9843 #define PIT_CVAL_TVL_SHIFT 0
Jasper_lee 0:b16d94660a33 9844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
Jasper_lee 0:b16d94660a33 9845 /* TCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 9846 #define PIT_TCTRL_TEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 9847 #define PIT_TCTRL_TEN_SHIFT 0
Jasper_lee 0:b16d94660a33 9848 #define PIT_TCTRL_TIE_MASK 0x2u
Jasper_lee 0:b16d94660a33 9849 #define PIT_TCTRL_TIE_SHIFT 1
Jasper_lee 0:b16d94660a33 9850 #define PIT_TCTRL_CHN_MASK 0x4u
Jasper_lee 0:b16d94660a33 9851 #define PIT_TCTRL_CHN_SHIFT 2
Jasper_lee 0:b16d94660a33 9852 /* TFLG Bit Fields */
Jasper_lee 0:b16d94660a33 9853 #define PIT_TFLG_TIF_MASK 0x1u
Jasper_lee 0:b16d94660a33 9854 #define PIT_TFLG_TIF_SHIFT 0
Jasper_lee 0:b16d94660a33 9855
Jasper_lee 0:b16d94660a33 9856 /*!
Jasper_lee 0:b16d94660a33 9857 * @}
Jasper_lee 0:b16d94660a33 9858 */ /* end of group PIT_Register_Masks */
Jasper_lee 0:b16d94660a33 9859
Jasper_lee 0:b16d94660a33 9860
Jasper_lee 0:b16d94660a33 9861 /* PIT - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 9862 /** Peripheral PIT base address */
Jasper_lee 0:b16d94660a33 9863 #define PIT_BASE (0x40037000u)
Jasper_lee 0:b16d94660a33 9864 /** Peripheral PIT base pointer */
Jasper_lee 0:b16d94660a33 9865 #define PIT ((PIT_Type *)PIT_BASE)
Jasper_lee 0:b16d94660a33 9866 #define PIT_BASE_PTR (PIT)
Jasper_lee 0:b16d94660a33 9867 /** Array initializer of PIT peripheral base addresses */
Jasper_lee 0:b16d94660a33 9868 #define PIT_BASE_ADDRS { PIT_BASE }
Jasper_lee 0:b16d94660a33 9869 /** Array initializer of PIT peripheral base pointers */
Jasper_lee 0:b16d94660a33 9870 #define PIT_BASE_PTRS { PIT }
Jasper_lee 0:b16d94660a33 9871 /** Interrupt vectors for the PIT peripheral type */
Jasper_lee 0:b16d94660a33 9872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
Jasper_lee 0:b16d94660a33 9873
Jasper_lee 0:b16d94660a33 9874 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9875 -- PIT - Register accessor macros
Jasper_lee 0:b16d94660a33 9876 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9877
Jasper_lee 0:b16d94660a33 9878 /*!
Jasper_lee 0:b16d94660a33 9879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Jasper_lee 0:b16d94660a33 9880 * @{
Jasper_lee 0:b16d94660a33 9881 */
Jasper_lee 0:b16d94660a33 9882
Jasper_lee 0:b16d94660a33 9883
Jasper_lee 0:b16d94660a33 9884 /* PIT - Register instance definitions */
Jasper_lee 0:b16d94660a33 9885 /* PIT */
Jasper_lee 0:b16d94660a33 9886 #define PIT_MCR PIT_MCR_REG(PIT)
Jasper_lee 0:b16d94660a33 9887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
Jasper_lee 0:b16d94660a33 9888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
Jasper_lee 0:b16d94660a33 9889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
Jasper_lee 0:b16d94660a33 9890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
Jasper_lee 0:b16d94660a33 9891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
Jasper_lee 0:b16d94660a33 9892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
Jasper_lee 0:b16d94660a33 9893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
Jasper_lee 0:b16d94660a33 9894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
Jasper_lee 0:b16d94660a33 9895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
Jasper_lee 0:b16d94660a33 9896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
Jasper_lee 0:b16d94660a33 9897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
Jasper_lee 0:b16d94660a33 9898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
Jasper_lee 0:b16d94660a33 9899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
Jasper_lee 0:b16d94660a33 9900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
Jasper_lee 0:b16d94660a33 9901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
Jasper_lee 0:b16d94660a33 9902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
Jasper_lee 0:b16d94660a33 9903
Jasper_lee 0:b16d94660a33 9904 /* PIT - Register array accessors */
Jasper_lee 0:b16d94660a33 9905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
Jasper_lee 0:b16d94660a33 9906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
Jasper_lee 0:b16d94660a33 9907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
Jasper_lee 0:b16d94660a33 9908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
Jasper_lee 0:b16d94660a33 9909
Jasper_lee 0:b16d94660a33 9910 /*!
Jasper_lee 0:b16d94660a33 9911 * @}
Jasper_lee 0:b16d94660a33 9912 */ /* end of group PIT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9913
Jasper_lee 0:b16d94660a33 9914
Jasper_lee 0:b16d94660a33 9915 /*!
Jasper_lee 0:b16d94660a33 9916 * @}
Jasper_lee 0:b16d94660a33 9917 */ /* end of group PIT_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 9918
Jasper_lee 0:b16d94660a33 9919
Jasper_lee 0:b16d94660a33 9920 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9921 -- PMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9922 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9923
Jasper_lee 0:b16d94660a33 9924 /*!
Jasper_lee 0:b16d94660a33 9925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 9926 * @{
Jasper_lee 0:b16d94660a33 9927 */
Jasper_lee 0:b16d94660a33 9928
Jasper_lee 0:b16d94660a33 9929 /** PMC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 9930 typedef struct {
Jasper_lee 0:b16d94660a33 9931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 9932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 9933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 9934 } PMC_Type, *PMC_MemMapPtr;
Jasper_lee 0:b16d94660a33 9935
Jasper_lee 0:b16d94660a33 9936 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9937 -- PMC - Register accessor macros
Jasper_lee 0:b16d94660a33 9938 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9939
Jasper_lee 0:b16d94660a33 9940 /*!
Jasper_lee 0:b16d94660a33 9941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Jasper_lee 0:b16d94660a33 9942 * @{
Jasper_lee 0:b16d94660a33 9943 */
Jasper_lee 0:b16d94660a33 9944
Jasper_lee 0:b16d94660a33 9945
Jasper_lee 0:b16d94660a33 9946 /* PMC - Register accessors */
Jasper_lee 0:b16d94660a33 9947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
Jasper_lee 0:b16d94660a33 9948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
Jasper_lee 0:b16d94660a33 9949 #define PMC_REGSC_REG(base) ((base)->REGSC)
Jasper_lee 0:b16d94660a33 9950
Jasper_lee 0:b16d94660a33 9951 /*!
Jasper_lee 0:b16d94660a33 9952 * @}
Jasper_lee 0:b16d94660a33 9953 */ /* end of group PMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 9954
Jasper_lee 0:b16d94660a33 9955
Jasper_lee 0:b16d94660a33 9956 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 9957 -- PMC Register Masks
Jasper_lee 0:b16d94660a33 9958 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 9959
Jasper_lee 0:b16d94660a33 9960 /*!
Jasper_lee 0:b16d94660a33 9961 * @addtogroup PMC_Register_Masks PMC Register Masks
Jasper_lee 0:b16d94660a33 9962 * @{
Jasper_lee 0:b16d94660a33 9963 */
Jasper_lee 0:b16d94660a33 9964
Jasper_lee 0:b16d94660a33 9965 /* LVDSC1 Bit Fields */
Jasper_lee 0:b16d94660a33 9966 #define PMC_LVDSC1_LVDV_MASK 0x3u
Jasper_lee 0:b16d94660a33 9967 #define PMC_LVDSC1_LVDV_SHIFT 0
Jasper_lee 0:b16d94660a33 9968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
Jasper_lee 0:b16d94660a33 9969 #define PMC_LVDSC1_LVDRE_MASK 0x10u
Jasper_lee 0:b16d94660a33 9970 #define PMC_LVDSC1_LVDRE_SHIFT 4
Jasper_lee 0:b16d94660a33 9971 #define PMC_LVDSC1_LVDIE_MASK 0x20u
Jasper_lee 0:b16d94660a33 9972 #define PMC_LVDSC1_LVDIE_SHIFT 5
Jasper_lee 0:b16d94660a33 9973 #define PMC_LVDSC1_LVDACK_MASK 0x40u
Jasper_lee 0:b16d94660a33 9974 #define PMC_LVDSC1_LVDACK_SHIFT 6
Jasper_lee 0:b16d94660a33 9975 #define PMC_LVDSC1_LVDF_MASK 0x80u
Jasper_lee 0:b16d94660a33 9976 #define PMC_LVDSC1_LVDF_SHIFT 7
Jasper_lee 0:b16d94660a33 9977 /* LVDSC2 Bit Fields */
Jasper_lee 0:b16d94660a33 9978 #define PMC_LVDSC2_LVWV_MASK 0x3u
Jasper_lee 0:b16d94660a33 9979 #define PMC_LVDSC2_LVWV_SHIFT 0
Jasper_lee 0:b16d94660a33 9980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
Jasper_lee 0:b16d94660a33 9981 #define PMC_LVDSC2_LVWIE_MASK 0x20u
Jasper_lee 0:b16d94660a33 9982 #define PMC_LVDSC2_LVWIE_SHIFT 5
Jasper_lee 0:b16d94660a33 9983 #define PMC_LVDSC2_LVWACK_MASK 0x40u
Jasper_lee 0:b16d94660a33 9984 #define PMC_LVDSC2_LVWACK_SHIFT 6
Jasper_lee 0:b16d94660a33 9985 #define PMC_LVDSC2_LVWF_MASK 0x80u
Jasper_lee 0:b16d94660a33 9986 #define PMC_LVDSC2_LVWF_SHIFT 7
Jasper_lee 0:b16d94660a33 9987 /* REGSC Bit Fields */
Jasper_lee 0:b16d94660a33 9988 #define PMC_REGSC_BGBE_MASK 0x1u
Jasper_lee 0:b16d94660a33 9989 #define PMC_REGSC_BGBE_SHIFT 0
Jasper_lee 0:b16d94660a33 9990 #define PMC_REGSC_REGONS_MASK 0x4u
Jasper_lee 0:b16d94660a33 9991 #define PMC_REGSC_REGONS_SHIFT 2
Jasper_lee 0:b16d94660a33 9992 #define PMC_REGSC_ACKISO_MASK 0x8u
Jasper_lee 0:b16d94660a33 9993 #define PMC_REGSC_ACKISO_SHIFT 3
Jasper_lee 0:b16d94660a33 9994 #define PMC_REGSC_BGEN_MASK 0x10u
Jasper_lee 0:b16d94660a33 9995 #define PMC_REGSC_BGEN_SHIFT 4
Jasper_lee 0:b16d94660a33 9996
Jasper_lee 0:b16d94660a33 9997 /*!
Jasper_lee 0:b16d94660a33 9998 * @}
Jasper_lee 0:b16d94660a33 9999 */ /* end of group PMC_Register_Masks */
Jasper_lee 0:b16d94660a33 10000
Jasper_lee 0:b16d94660a33 10001
Jasper_lee 0:b16d94660a33 10002 /* PMC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10003 /** Peripheral PMC base address */
Jasper_lee 0:b16d94660a33 10004 #define PMC_BASE (0x4007D000u)
Jasper_lee 0:b16d94660a33 10005 /** Peripheral PMC base pointer */
Jasper_lee 0:b16d94660a33 10006 #define PMC ((PMC_Type *)PMC_BASE)
Jasper_lee 0:b16d94660a33 10007 #define PMC_BASE_PTR (PMC)
Jasper_lee 0:b16d94660a33 10008 /** Array initializer of PMC peripheral base addresses */
Jasper_lee 0:b16d94660a33 10009 #define PMC_BASE_ADDRS { PMC_BASE }
Jasper_lee 0:b16d94660a33 10010 /** Array initializer of PMC peripheral base pointers */
Jasper_lee 0:b16d94660a33 10011 #define PMC_BASE_PTRS { PMC }
Jasper_lee 0:b16d94660a33 10012 /** Interrupt vectors for the PMC peripheral type */
Jasper_lee 0:b16d94660a33 10013 #define PMC_IRQS { LVD_LVW_IRQn }
Jasper_lee 0:b16d94660a33 10014
Jasper_lee 0:b16d94660a33 10015 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10016 -- PMC - Register accessor macros
Jasper_lee 0:b16d94660a33 10017 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10018
Jasper_lee 0:b16d94660a33 10019 /*!
Jasper_lee 0:b16d94660a33 10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Jasper_lee 0:b16d94660a33 10021 * @{
Jasper_lee 0:b16d94660a33 10022 */
Jasper_lee 0:b16d94660a33 10023
Jasper_lee 0:b16d94660a33 10024
Jasper_lee 0:b16d94660a33 10025 /* PMC - Register instance definitions */
Jasper_lee 0:b16d94660a33 10026 /* PMC */
Jasper_lee 0:b16d94660a33 10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
Jasper_lee 0:b16d94660a33 10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
Jasper_lee 0:b16d94660a33 10029 #define PMC_REGSC PMC_REGSC_REG(PMC)
Jasper_lee 0:b16d94660a33 10030
Jasper_lee 0:b16d94660a33 10031 /*!
Jasper_lee 0:b16d94660a33 10032 * @}
Jasper_lee 0:b16d94660a33 10033 */ /* end of group PMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10034
Jasper_lee 0:b16d94660a33 10035
Jasper_lee 0:b16d94660a33 10036 /*!
Jasper_lee 0:b16d94660a33 10037 * @}
Jasper_lee 0:b16d94660a33 10038 */ /* end of group PMC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10039
Jasper_lee 0:b16d94660a33 10040
Jasper_lee 0:b16d94660a33 10041 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10042 -- PORT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10043 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10044
Jasper_lee 0:b16d94660a33 10045 /*!
Jasper_lee 0:b16d94660a33 10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10047 * @{
Jasper_lee 0:b16d94660a33 10048 */
Jasper_lee 0:b16d94660a33 10049
Jasper_lee 0:b16d94660a33 10050 /** PORT - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10051 typedef struct {
Jasper_lee 0:b16d94660a33 10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
Jasper_lee 0:b16d94660a33 10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
Jasper_lee 0:b16d94660a33 10055 uint8_t RESERVED_0[24];
Jasper_lee 0:b16d94660a33 10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
Jasper_lee 0:b16d94660a33 10057 uint8_t RESERVED_1[28];
Jasper_lee 0:b16d94660a33 10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
Jasper_lee 0:b16d94660a33 10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
Jasper_lee 0:b16d94660a33 10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
Jasper_lee 0:b16d94660a33 10061 } PORT_Type, *PORT_MemMapPtr;
Jasper_lee 0:b16d94660a33 10062
Jasper_lee 0:b16d94660a33 10063 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10064 -- PORT - Register accessor macros
Jasper_lee 0:b16d94660a33 10065 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10066
Jasper_lee 0:b16d94660a33 10067 /*!
Jasper_lee 0:b16d94660a33 10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Jasper_lee 0:b16d94660a33 10069 * @{
Jasper_lee 0:b16d94660a33 10070 */
Jasper_lee 0:b16d94660a33 10071
Jasper_lee 0:b16d94660a33 10072
Jasper_lee 0:b16d94660a33 10073 /* PORT - Register accessors */
Jasper_lee 0:b16d94660a33 10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
Jasper_lee 0:b16d94660a33 10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
Jasper_lee 0:b16d94660a33 10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
Jasper_lee 0:b16d94660a33 10077 #define PORT_ISFR_REG(base) ((base)->ISFR)
Jasper_lee 0:b16d94660a33 10078 #define PORT_DFER_REG(base) ((base)->DFER)
Jasper_lee 0:b16d94660a33 10079 #define PORT_DFCR_REG(base) ((base)->DFCR)
Jasper_lee 0:b16d94660a33 10080 #define PORT_DFWR_REG(base) ((base)->DFWR)
Jasper_lee 0:b16d94660a33 10081
Jasper_lee 0:b16d94660a33 10082 /*!
Jasper_lee 0:b16d94660a33 10083 * @}
Jasper_lee 0:b16d94660a33 10084 */ /* end of group PORT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10085
Jasper_lee 0:b16d94660a33 10086
Jasper_lee 0:b16d94660a33 10087 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10088 -- PORT Register Masks
Jasper_lee 0:b16d94660a33 10089 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10090
Jasper_lee 0:b16d94660a33 10091 /*!
Jasper_lee 0:b16d94660a33 10092 * @addtogroup PORT_Register_Masks PORT Register Masks
Jasper_lee 0:b16d94660a33 10093 * @{
Jasper_lee 0:b16d94660a33 10094 */
Jasper_lee 0:b16d94660a33 10095
Jasper_lee 0:b16d94660a33 10096 /* PCR Bit Fields */
Jasper_lee 0:b16d94660a33 10097 #define PORT_PCR_PS_MASK 0x1u
Jasper_lee 0:b16d94660a33 10098 #define PORT_PCR_PS_SHIFT 0
Jasper_lee 0:b16d94660a33 10099 #define PORT_PCR_PE_MASK 0x2u
Jasper_lee 0:b16d94660a33 10100 #define PORT_PCR_PE_SHIFT 1
Jasper_lee 0:b16d94660a33 10101 #define PORT_PCR_SRE_MASK 0x4u
Jasper_lee 0:b16d94660a33 10102 #define PORT_PCR_SRE_SHIFT 2
Jasper_lee 0:b16d94660a33 10103 #define PORT_PCR_PFE_MASK 0x10u
Jasper_lee 0:b16d94660a33 10104 #define PORT_PCR_PFE_SHIFT 4
Jasper_lee 0:b16d94660a33 10105 #define PORT_PCR_ODE_MASK 0x20u
Jasper_lee 0:b16d94660a33 10106 #define PORT_PCR_ODE_SHIFT 5
Jasper_lee 0:b16d94660a33 10107 #define PORT_PCR_DSE_MASK 0x40u
Jasper_lee 0:b16d94660a33 10108 #define PORT_PCR_DSE_SHIFT 6
Jasper_lee 0:b16d94660a33 10109 #define PORT_PCR_MUX_MASK 0x700u
Jasper_lee 0:b16d94660a33 10110 #define PORT_PCR_MUX_SHIFT 8
Jasper_lee 0:b16d94660a33 10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
Jasper_lee 0:b16d94660a33 10112 #define PORT_PCR_LK_MASK 0x8000u
Jasper_lee 0:b16d94660a33 10113 #define PORT_PCR_LK_SHIFT 15
Jasper_lee 0:b16d94660a33 10114 #define PORT_PCR_IRQC_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 10115 #define PORT_PCR_IRQC_SHIFT 16
Jasper_lee 0:b16d94660a33 10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
Jasper_lee 0:b16d94660a33 10117 #define PORT_PCR_ISF_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 10118 #define PORT_PCR_ISF_SHIFT 24
Jasper_lee 0:b16d94660a33 10119 /* GPCLR Bit Fields */
Jasper_lee 0:b16d94660a33 10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 10121 #define PORT_GPCLR_GPWD_SHIFT 0
Jasper_lee 0:b16d94660a33 10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
Jasper_lee 0:b16d94660a33 10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 10124 #define PORT_GPCLR_GPWE_SHIFT 16
Jasper_lee 0:b16d94660a33 10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
Jasper_lee 0:b16d94660a33 10126 /* GPCHR Bit Fields */
Jasper_lee 0:b16d94660a33 10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 10128 #define PORT_GPCHR_GPWD_SHIFT 0
Jasper_lee 0:b16d94660a33 10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
Jasper_lee 0:b16d94660a33 10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 10131 #define PORT_GPCHR_GPWE_SHIFT 16
Jasper_lee 0:b16d94660a33 10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
Jasper_lee 0:b16d94660a33 10133 /* ISFR Bit Fields */
Jasper_lee 0:b16d94660a33 10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10135 #define PORT_ISFR_ISF_SHIFT 0
Jasper_lee 0:b16d94660a33 10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
Jasper_lee 0:b16d94660a33 10137 /* DFER Bit Fields */
Jasper_lee 0:b16d94660a33 10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10139 #define PORT_DFER_DFE_SHIFT 0
Jasper_lee 0:b16d94660a33 10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
Jasper_lee 0:b16d94660a33 10141 /* DFCR Bit Fields */
Jasper_lee 0:b16d94660a33 10142 #define PORT_DFCR_CS_MASK 0x1u
Jasper_lee 0:b16d94660a33 10143 #define PORT_DFCR_CS_SHIFT 0
Jasper_lee 0:b16d94660a33 10144 /* DFWR Bit Fields */
Jasper_lee 0:b16d94660a33 10145 #define PORT_DFWR_FILT_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 10146 #define PORT_DFWR_FILT_SHIFT 0
Jasper_lee 0:b16d94660a33 10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
Jasper_lee 0:b16d94660a33 10148
Jasper_lee 0:b16d94660a33 10149 /*!
Jasper_lee 0:b16d94660a33 10150 * @}
Jasper_lee 0:b16d94660a33 10151 */ /* end of group PORT_Register_Masks */
Jasper_lee 0:b16d94660a33 10152
Jasper_lee 0:b16d94660a33 10153
Jasper_lee 0:b16d94660a33 10154 /* PORT - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10155 /** Peripheral PORTA base address */
Jasper_lee 0:b16d94660a33 10156 #define PORTA_BASE (0x40049000u)
Jasper_lee 0:b16d94660a33 10157 /** Peripheral PORTA base pointer */
Jasper_lee 0:b16d94660a33 10158 #define PORTA ((PORT_Type *)PORTA_BASE)
Jasper_lee 0:b16d94660a33 10159 #define PORTA_BASE_PTR (PORTA)
Jasper_lee 0:b16d94660a33 10160 /** Peripheral PORTB base address */
Jasper_lee 0:b16d94660a33 10161 #define PORTB_BASE (0x4004A000u)
Jasper_lee 0:b16d94660a33 10162 /** Peripheral PORTB base pointer */
Jasper_lee 0:b16d94660a33 10163 #define PORTB ((PORT_Type *)PORTB_BASE)
Jasper_lee 0:b16d94660a33 10164 #define PORTB_BASE_PTR (PORTB)
Jasper_lee 0:b16d94660a33 10165 /** Peripheral PORTC base address */
Jasper_lee 0:b16d94660a33 10166 #define PORTC_BASE (0x4004B000u)
Jasper_lee 0:b16d94660a33 10167 /** Peripheral PORTC base pointer */
Jasper_lee 0:b16d94660a33 10168 #define PORTC ((PORT_Type *)PORTC_BASE)
Jasper_lee 0:b16d94660a33 10169 #define PORTC_BASE_PTR (PORTC)
Jasper_lee 0:b16d94660a33 10170 /** Peripheral PORTD base address */
Jasper_lee 0:b16d94660a33 10171 #define PORTD_BASE (0x4004C000u)
Jasper_lee 0:b16d94660a33 10172 /** Peripheral PORTD base pointer */
Jasper_lee 0:b16d94660a33 10173 #define PORTD ((PORT_Type *)PORTD_BASE)
Jasper_lee 0:b16d94660a33 10174 #define PORTD_BASE_PTR (PORTD)
Jasper_lee 0:b16d94660a33 10175 /** Peripheral PORTE base address */
Jasper_lee 0:b16d94660a33 10176 #define PORTE_BASE (0x4004D000u)
Jasper_lee 0:b16d94660a33 10177 /** Peripheral PORTE base pointer */
Jasper_lee 0:b16d94660a33 10178 #define PORTE ((PORT_Type *)PORTE_BASE)
Jasper_lee 0:b16d94660a33 10179 #define PORTE_BASE_PTR (PORTE)
Jasper_lee 0:b16d94660a33 10180 /** Array initializer of PORT peripheral base addresses */
Jasper_lee 0:b16d94660a33 10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
Jasper_lee 0:b16d94660a33 10182 /** Array initializer of PORT peripheral base pointers */
Jasper_lee 0:b16d94660a33 10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
Jasper_lee 0:b16d94660a33 10184 /** Interrupt vectors for the PORT peripheral type */
Jasper_lee 0:b16d94660a33 10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
Jasper_lee 0:b16d94660a33 10186
Jasper_lee 0:b16d94660a33 10187 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10188 -- PORT - Register accessor macros
Jasper_lee 0:b16d94660a33 10189 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10190
Jasper_lee 0:b16d94660a33 10191 /*!
Jasper_lee 0:b16d94660a33 10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Jasper_lee 0:b16d94660a33 10193 * @{
Jasper_lee 0:b16d94660a33 10194 */
Jasper_lee 0:b16d94660a33 10195
Jasper_lee 0:b16d94660a33 10196
Jasper_lee 0:b16d94660a33 10197 /* PORT - Register instance definitions */
Jasper_lee 0:b16d94660a33 10198 /* PORTA */
Jasper_lee 0:b16d94660a33 10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
Jasper_lee 0:b16d94660a33 10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
Jasper_lee 0:b16d94660a33 10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
Jasper_lee 0:b16d94660a33 10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
Jasper_lee 0:b16d94660a33 10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
Jasper_lee 0:b16d94660a33 10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
Jasper_lee 0:b16d94660a33 10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
Jasper_lee 0:b16d94660a33 10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
Jasper_lee 0:b16d94660a33 10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
Jasper_lee 0:b16d94660a33 10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
Jasper_lee 0:b16d94660a33 10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
Jasper_lee 0:b16d94660a33 10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
Jasper_lee 0:b16d94660a33 10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
Jasper_lee 0:b16d94660a33 10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
Jasper_lee 0:b16d94660a33 10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
Jasper_lee 0:b16d94660a33 10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
Jasper_lee 0:b16d94660a33 10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
Jasper_lee 0:b16d94660a33 10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
Jasper_lee 0:b16d94660a33 10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
Jasper_lee 0:b16d94660a33 10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
Jasper_lee 0:b16d94660a33 10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
Jasper_lee 0:b16d94660a33 10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
Jasper_lee 0:b16d94660a33 10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
Jasper_lee 0:b16d94660a33 10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
Jasper_lee 0:b16d94660a33 10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
Jasper_lee 0:b16d94660a33 10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
Jasper_lee 0:b16d94660a33 10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
Jasper_lee 0:b16d94660a33 10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
Jasper_lee 0:b16d94660a33 10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
Jasper_lee 0:b16d94660a33 10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
Jasper_lee 0:b16d94660a33 10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
Jasper_lee 0:b16d94660a33 10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
Jasper_lee 0:b16d94660a33 10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
Jasper_lee 0:b16d94660a33 10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
Jasper_lee 0:b16d94660a33 10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
Jasper_lee 0:b16d94660a33 10234 /* PORTB */
Jasper_lee 0:b16d94660a33 10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
Jasper_lee 0:b16d94660a33 10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
Jasper_lee 0:b16d94660a33 10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
Jasper_lee 0:b16d94660a33 10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
Jasper_lee 0:b16d94660a33 10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
Jasper_lee 0:b16d94660a33 10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
Jasper_lee 0:b16d94660a33 10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
Jasper_lee 0:b16d94660a33 10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
Jasper_lee 0:b16d94660a33 10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
Jasper_lee 0:b16d94660a33 10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
Jasper_lee 0:b16d94660a33 10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
Jasper_lee 0:b16d94660a33 10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
Jasper_lee 0:b16d94660a33 10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
Jasper_lee 0:b16d94660a33 10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
Jasper_lee 0:b16d94660a33 10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
Jasper_lee 0:b16d94660a33 10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
Jasper_lee 0:b16d94660a33 10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
Jasper_lee 0:b16d94660a33 10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
Jasper_lee 0:b16d94660a33 10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
Jasper_lee 0:b16d94660a33 10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
Jasper_lee 0:b16d94660a33 10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
Jasper_lee 0:b16d94660a33 10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
Jasper_lee 0:b16d94660a33 10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
Jasper_lee 0:b16d94660a33 10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
Jasper_lee 0:b16d94660a33 10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
Jasper_lee 0:b16d94660a33 10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
Jasper_lee 0:b16d94660a33 10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
Jasper_lee 0:b16d94660a33 10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
Jasper_lee 0:b16d94660a33 10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
Jasper_lee 0:b16d94660a33 10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
Jasper_lee 0:b16d94660a33 10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
Jasper_lee 0:b16d94660a33 10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
Jasper_lee 0:b16d94660a33 10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
Jasper_lee 0:b16d94660a33 10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
Jasper_lee 0:b16d94660a33 10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
Jasper_lee 0:b16d94660a33 10270 /* PORTC */
Jasper_lee 0:b16d94660a33 10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
Jasper_lee 0:b16d94660a33 10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
Jasper_lee 0:b16d94660a33 10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
Jasper_lee 0:b16d94660a33 10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
Jasper_lee 0:b16d94660a33 10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
Jasper_lee 0:b16d94660a33 10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
Jasper_lee 0:b16d94660a33 10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
Jasper_lee 0:b16d94660a33 10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
Jasper_lee 0:b16d94660a33 10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
Jasper_lee 0:b16d94660a33 10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
Jasper_lee 0:b16d94660a33 10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
Jasper_lee 0:b16d94660a33 10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
Jasper_lee 0:b16d94660a33 10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
Jasper_lee 0:b16d94660a33 10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
Jasper_lee 0:b16d94660a33 10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
Jasper_lee 0:b16d94660a33 10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
Jasper_lee 0:b16d94660a33 10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
Jasper_lee 0:b16d94660a33 10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
Jasper_lee 0:b16d94660a33 10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
Jasper_lee 0:b16d94660a33 10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
Jasper_lee 0:b16d94660a33 10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
Jasper_lee 0:b16d94660a33 10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
Jasper_lee 0:b16d94660a33 10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
Jasper_lee 0:b16d94660a33 10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
Jasper_lee 0:b16d94660a33 10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
Jasper_lee 0:b16d94660a33 10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
Jasper_lee 0:b16d94660a33 10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
Jasper_lee 0:b16d94660a33 10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
Jasper_lee 0:b16d94660a33 10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
Jasper_lee 0:b16d94660a33 10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
Jasper_lee 0:b16d94660a33 10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
Jasper_lee 0:b16d94660a33 10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
Jasper_lee 0:b16d94660a33 10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
Jasper_lee 0:b16d94660a33 10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
Jasper_lee 0:b16d94660a33 10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
Jasper_lee 0:b16d94660a33 10306 /* PORTD */
Jasper_lee 0:b16d94660a33 10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
Jasper_lee 0:b16d94660a33 10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
Jasper_lee 0:b16d94660a33 10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
Jasper_lee 0:b16d94660a33 10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
Jasper_lee 0:b16d94660a33 10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
Jasper_lee 0:b16d94660a33 10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
Jasper_lee 0:b16d94660a33 10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
Jasper_lee 0:b16d94660a33 10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
Jasper_lee 0:b16d94660a33 10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
Jasper_lee 0:b16d94660a33 10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
Jasper_lee 0:b16d94660a33 10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
Jasper_lee 0:b16d94660a33 10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
Jasper_lee 0:b16d94660a33 10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
Jasper_lee 0:b16d94660a33 10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
Jasper_lee 0:b16d94660a33 10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
Jasper_lee 0:b16d94660a33 10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
Jasper_lee 0:b16d94660a33 10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
Jasper_lee 0:b16d94660a33 10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
Jasper_lee 0:b16d94660a33 10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
Jasper_lee 0:b16d94660a33 10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
Jasper_lee 0:b16d94660a33 10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
Jasper_lee 0:b16d94660a33 10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
Jasper_lee 0:b16d94660a33 10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
Jasper_lee 0:b16d94660a33 10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
Jasper_lee 0:b16d94660a33 10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
Jasper_lee 0:b16d94660a33 10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
Jasper_lee 0:b16d94660a33 10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
Jasper_lee 0:b16d94660a33 10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
Jasper_lee 0:b16d94660a33 10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
Jasper_lee 0:b16d94660a33 10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
Jasper_lee 0:b16d94660a33 10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
Jasper_lee 0:b16d94660a33 10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
Jasper_lee 0:b16d94660a33 10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
Jasper_lee 0:b16d94660a33 10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
Jasper_lee 0:b16d94660a33 10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
Jasper_lee 0:b16d94660a33 10342 #define PORTD_DFER PORT_DFER_REG(PORTD)
Jasper_lee 0:b16d94660a33 10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
Jasper_lee 0:b16d94660a33 10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
Jasper_lee 0:b16d94660a33 10345 /* PORTE */
Jasper_lee 0:b16d94660a33 10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
Jasper_lee 0:b16d94660a33 10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
Jasper_lee 0:b16d94660a33 10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
Jasper_lee 0:b16d94660a33 10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
Jasper_lee 0:b16d94660a33 10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
Jasper_lee 0:b16d94660a33 10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
Jasper_lee 0:b16d94660a33 10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
Jasper_lee 0:b16d94660a33 10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
Jasper_lee 0:b16d94660a33 10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
Jasper_lee 0:b16d94660a33 10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
Jasper_lee 0:b16d94660a33 10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
Jasper_lee 0:b16d94660a33 10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
Jasper_lee 0:b16d94660a33 10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
Jasper_lee 0:b16d94660a33 10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
Jasper_lee 0:b16d94660a33 10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
Jasper_lee 0:b16d94660a33 10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
Jasper_lee 0:b16d94660a33 10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
Jasper_lee 0:b16d94660a33 10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
Jasper_lee 0:b16d94660a33 10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
Jasper_lee 0:b16d94660a33 10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
Jasper_lee 0:b16d94660a33 10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
Jasper_lee 0:b16d94660a33 10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
Jasper_lee 0:b16d94660a33 10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
Jasper_lee 0:b16d94660a33 10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
Jasper_lee 0:b16d94660a33 10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
Jasper_lee 0:b16d94660a33 10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
Jasper_lee 0:b16d94660a33 10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
Jasper_lee 0:b16d94660a33 10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
Jasper_lee 0:b16d94660a33 10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
Jasper_lee 0:b16d94660a33 10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
Jasper_lee 0:b16d94660a33 10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
Jasper_lee 0:b16d94660a33 10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
Jasper_lee 0:b16d94660a33 10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
Jasper_lee 0:b16d94660a33 10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
Jasper_lee 0:b16d94660a33 10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
Jasper_lee 0:b16d94660a33 10381
Jasper_lee 0:b16d94660a33 10382 /* PORT - Register array accessors */
Jasper_lee 0:b16d94660a33 10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
Jasper_lee 0:b16d94660a33 10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
Jasper_lee 0:b16d94660a33 10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
Jasper_lee 0:b16d94660a33 10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
Jasper_lee 0:b16d94660a33 10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
Jasper_lee 0:b16d94660a33 10388
Jasper_lee 0:b16d94660a33 10389 /*!
Jasper_lee 0:b16d94660a33 10390 * @}
Jasper_lee 0:b16d94660a33 10391 */ /* end of group PORT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10392
Jasper_lee 0:b16d94660a33 10393
Jasper_lee 0:b16d94660a33 10394 /*!
Jasper_lee 0:b16d94660a33 10395 * @}
Jasper_lee 0:b16d94660a33 10396 */ /* end of group PORT_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10397
Jasper_lee 0:b16d94660a33 10398
Jasper_lee 0:b16d94660a33 10399 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10400 -- RCM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10401 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10402
Jasper_lee 0:b16d94660a33 10403 /*!
Jasper_lee 0:b16d94660a33 10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10405 * @{
Jasper_lee 0:b16d94660a33 10406 */
Jasper_lee 0:b16d94660a33 10407
Jasper_lee 0:b16d94660a33 10408 /** RCM - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10409 typedef struct {
Jasper_lee 0:b16d94660a33 10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
Jasper_lee 0:b16d94660a33 10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
Jasper_lee 0:b16d94660a33 10412 uint8_t RESERVED_0[2];
Jasper_lee 0:b16d94660a33 10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
Jasper_lee 0:b16d94660a33 10415 uint8_t RESERVED_1[1];
Jasper_lee 0:b16d94660a33 10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
Jasper_lee 0:b16d94660a33 10417 } RCM_Type, *RCM_MemMapPtr;
Jasper_lee 0:b16d94660a33 10418
Jasper_lee 0:b16d94660a33 10419 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10420 -- RCM - Register accessor macros
Jasper_lee 0:b16d94660a33 10421 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10422
Jasper_lee 0:b16d94660a33 10423 /*!
Jasper_lee 0:b16d94660a33 10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Jasper_lee 0:b16d94660a33 10425 * @{
Jasper_lee 0:b16d94660a33 10426 */
Jasper_lee 0:b16d94660a33 10427
Jasper_lee 0:b16d94660a33 10428
Jasper_lee 0:b16d94660a33 10429 /* RCM - Register accessors */
Jasper_lee 0:b16d94660a33 10430 #define RCM_SRS0_REG(base) ((base)->SRS0)
Jasper_lee 0:b16d94660a33 10431 #define RCM_SRS1_REG(base) ((base)->SRS1)
Jasper_lee 0:b16d94660a33 10432 #define RCM_RPFC_REG(base) ((base)->RPFC)
Jasper_lee 0:b16d94660a33 10433 #define RCM_RPFW_REG(base) ((base)->RPFW)
Jasper_lee 0:b16d94660a33 10434 #define RCM_MR_REG(base) ((base)->MR)
Jasper_lee 0:b16d94660a33 10435
Jasper_lee 0:b16d94660a33 10436 /*!
Jasper_lee 0:b16d94660a33 10437 * @}
Jasper_lee 0:b16d94660a33 10438 */ /* end of group RCM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10439
Jasper_lee 0:b16d94660a33 10440
Jasper_lee 0:b16d94660a33 10441 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10442 -- RCM Register Masks
Jasper_lee 0:b16d94660a33 10443 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10444
Jasper_lee 0:b16d94660a33 10445 /*!
Jasper_lee 0:b16d94660a33 10446 * @addtogroup RCM_Register_Masks RCM Register Masks
Jasper_lee 0:b16d94660a33 10447 * @{
Jasper_lee 0:b16d94660a33 10448 */
Jasper_lee 0:b16d94660a33 10449
Jasper_lee 0:b16d94660a33 10450 /* SRS0 Bit Fields */
Jasper_lee 0:b16d94660a33 10451 #define RCM_SRS0_WAKEUP_MASK 0x1u
Jasper_lee 0:b16d94660a33 10452 #define RCM_SRS0_WAKEUP_SHIFT 0
Jasper_lee 0:b16d94660a33 10453 #define RCM_SRS0_LVD_MASK 0x2u
Jasper_lee 0:b16d94660a33 10454 #define RCM_SRS0_LVD_SHIFT 1
Jasper_lee 0:b16d94660a33 10455 #define RCM_SRS0_LOC_MASK 0x4u
Jasper_lee 0:b16d94660a33 10456 #define RCM_SRS0_LOC_SHIFT 2
Jasper_lee 0:b16d94660a33 10457 #define RCM_SRS0_LOL_MASK 0x8u
Jasper_lee 0:b16d94660a33 10458 #define RCM_SRS0_LOL_SHIFT 3
Jasper_lee 0:b16d94660a33 10459 #define RCM_SRS0_WDOG_MASK 0x20u
Jasper_lee 0:b16d94660a33 10460 #define RCM_SRS0_WDOG_SHIFT 5
Jasper_lee 0:b16d94660a33 10461 #define RCM_SRS0_PIN_MASK 0x40u
Jasper_lee 0:b16d94660a33 10462 #define RCM_SRS0_PIN_SHIFT 6
Jasper_lee 0:b16d94660a33 10463 #define RCM_SRS0_POR_MASK 0x80u
Jasper_lee 0:b16d94660a33 10464 #define RCM_SRS0_POR_SHIFT 7
Jasper_lee 0:b16d94660a33 10465 /* SRS1 Bit Fields */
Jasper_lee 0:b16d94660a33 10466 #define RCM_SRS1_JTAG_MASK 0x1u
Jasper_lee 0:b16d94660a33 10467 #define RCM_SRS1_JTAG_SHIFT 0
Jasper_lee 0:b16d94660a33 10468 #define RCM_SRS1_LOCKUP_MASK 0x2u
Jasper_lee 0:b16d94660a33 10469 #define RCM_SRS1_LOCKUP_SHIFT 1
Jasper_lee 0:b16d94660a33 10470 #define RCM_SRS1_SW_MASK 0x4u
Jasper_lee 0:b16d94660a33 10471 #define RCM_SRS1_SW_SHIFT 2
Jasper_lee 0:b16d94660a33 10472 #define RCM_SRS1_MDM_AP_MASK 0x8u
Jasper_lee 0:b16d94660a33 10473 #define RCM_SRS1_MDM_AP_SHIFT 3
Jasper_lee 0:b16d94660a33 10474 #define RCM_SRS1_EZPT_MASK 0x10u
Jasper_lee 0:b16d94660a33 10475 #define RCM_SRS1_EZPT_SHIFT 4
Jasper_lee 0:b16d94660a33 10476 #define RCM_SRS1_SACKERR_MASK 0x20u
Jasper_lee 0:b16d94660a33 10477 #define RCM_SRS1_SACKERR_SHIFT 5
Jasper_lee 0:b16d94660a33 10478 /* RPFC Bit Fields */
Jasper_lee 0:b16d94660a33 10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
Jasper_lee 0:b16d94660a33 10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
Jasper_lee 0:b16d94660a33 10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
Jasper_lee 0:b16d94660a33 10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
Jasper_lee 0:b16d94660a33 10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2
Jasper_lee 0:b16d94660a33 10484 /* RPFW Bit Fields */
Jasper_lee 0:b16d94660a33 10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
Jasper_lee 0:b16d94660a33 10488 /* MR Bit Fields */
Jasper_lee 0:b16d94660a33 10489 #define RCM_MR_EZP_MS_MASK 0x2u
Jasper_lee 0:b16d94660a33 10490 #define RCM_MR_EZP_MS_SHIFT 1
Jasper_lee 0:b16d94660a33 10491
Jasper_lee 0:b16d94660a33 10492 /*!
Jasper_lee 0:b16d94660a33 10493 * @}
Jasper_lee 0:b16d94660a33 10494 */ /* end of group RCM_Register_Masks */
Jasper_lee 0:b16d94660a33 10495
Jasper_lee 0:b16d94660a33 10496
Jasper_lee 0:b16d94660a33 10497 /* RCM - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10498 /** Peripheral RCM base address */
Jasper_lee 0:b16d94660a33 10499 #define RCM_BASE (0x4007F000u)
Jasper_lee 0:b16d94660a33 10500 /** Peripheral RCM base pointer */
Jasper_lee 0:b16d94660a33 10501 #define RCM ((RCM_Type *)RCM_BASE)
Jasper_lee 0:b16d94660a33 10502 #define RCM_BASE_PTR (RCM)
Jasper_lee 0:b16d94660a33 10503 /** Array initializer of RCM peripheral base addresses */
Jasper_lee 0:b16d94660a33 10504 #define RCM_BASE_ADDRS { RCM_BASE }
Jasper_lee 0:b16d94660a33 10505 /** Array initializer of RCM peripheral base pointers */
Jasper_lee 0:b16d94660a33 10506 #define RCM_BASE_PTRS { RCM }
Jasper_lee 0:b16d94660a33 10507
Jasper_lee 0:b16d94660a33 10508 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10509 -- RCM - Register accessor macros
Jasper_lee 0:b16d94660a33 10510 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10511
Jasper_lee 0:b16d94660a33 10512 /*!
Jasper_lee 0:b16d94660a33 10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Jasper_lee 0:b16d94660a33 10514 * @{
Jasper_lee 0:b16d94660a33 10515 */
Jasper_lee 0:b16d94660a33 10516
Jasper_lee 0:b16d94660a33 10517
Jasper_lee 0:b16d94660a33 10518 /* RCM - Register instance definitions */
Jasper_lee 0:b16d94660a33 10519 /* RCM */
Jasper_lee 0:b16d94660a33 10520 #define RCM_SRS0 RCM_SRS0_REG(RCM)
Jasper_lee 0:b16d94660a33 10521 #define RCM_SRS1 RCM_SRS1_REG(RCM)
Jasper_lee 0:b16d94660a33 10522 #define RCM_RPFC RCM_RPFC_REG(RCM)
Jasper_lee 0:b16d94660a33 10523 #define RCM_RPFW RCM_RPFW_REG(RCM)
Jasper_lee 0:b16d94660a33 10524 #define RCM_MR RCM_MR_REG(RCM)
Jasper_lee 0:b16d94660a33 10525
Jasper_lee 0:b16d94660a33 10526 /*!
Jasper_lee 0:b16d94660a33 10527 * @}
Jasper_lee 0:b16d94660a33 10528 */ /* end of group RCM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10529
Jasper_lee 0:b16d94660a33 10530
Jasper_lee 0:b16d94660a33 10531 /*!
Jasper_lee 0:b16d94660a33 10532 * @}
Jasper_lee 0:b16d94660a33 10533 */ /* end of group RCM_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10534
Jasper_lee 0:b16d94660a33 10535
Jasper_lee 0:b16d94660a33 10536 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10537 -- RFSYS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10538 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10539
Jasper_lee 0:b16d94660a33 10540 /*!
Jasper_lee 0:b16d94660a33 10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10542 * @{
Jasper_lee 0:b16d94660a33 10543 */
Jasper_lee 0:b16d94660a33 10544
Jasper_lee 0:b16d94660a33 10545 /** RFSYS - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10546 typedef struct {
Jasper_lee 0:b16d94660a33 10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 10548 } RFSYS_Type, *RFSYS_MemMapPtr;
Jasper_lee 0:b16d94660a33 10549
Jasper_lee 0:b16d94660a33 10550 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10551 -- RFSYS - Register accessor macros
Jasper_lee 0:b16d94660a33 10552 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10553
Jasper_lee 0:b16d94660a33 10554 /*!
Jasper_lee 0:b16d94660a33 10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Jasper_lee 0:b16d94660a33 10556 * @{
Jasper_lee 0:b16d94660a33 10557 */
Jasper_lee 0:b16d94660a33 10558
Jasper_lee 0:b16d94660a33 10559
Jasper_lee 0:b16d94660a33 10560 /* RFSYS - Register accessors */
Jasper_lee 0:b16d94660a33 10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
Jasper_lee 0:b16d94660a33 10562
Jasper_lee 0:b16d94660a33 10563 /*!
Jasper_lee 0:b16d94660a33 10564 * @}
Jasper_lee 0:b16d94660a33 10565 */ /* end of group RFSYS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10566
Jasper_lee 0:b16d94660a33 10567
Jasper_lee 0:b16d94660a33 10568 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10569 -- RFSYS Register Masks
Jasper_lee 0:b16d94660a33 10570 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10571
Jasper_lee 0:b16d94660a33 10572 /*!
Jasper_lee 0:b16d94660a33 10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
Jasper_lee 0:b16d94660a33 10574 * @{
Jasper_lee 0:b16d94660a33 10575 */
Jasper_lee 0:b16d94660a33 10576
Jasper_lee 0:b16d94660a33 10577 /* REG Bit Fields */
Jasper_lee 0:b16d94660a33 10578 #define RFSYS_REG_LL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 10579 #define RFSYS_REG_LL_SHIFT 0
Jasper_lee 0:b16d94660a33 10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
Jasper_lee 0:b16d94660a33 10581 #define RFSYS_REG_LH_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 10582 #define RFSYS_REG_LH_SHIFT 8
Jasper_lee 0:b16d94660a33 10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
Jasper_lee 0:b16d94660a33 10584 #define RFSYS_REG_HL_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 10585 #define RFSYS_REG_HL_SHIFT 16
Jasper_lee 0:b16d94660a33 10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
Jasper_lee 0:b16d94660a33 10587 #define RFSYS_REG_HH_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 10588 #define RFSYS_REG_HH_SHIFT 24
Jasper_lee 0:b16d94660a33 10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
Jasper_lee 0:b16d94660a33 10590
Jasper_lee 0:b16d94660a33 10591 /*!
Jasper_lee 0:b16d94660a33 10592 * @}
Jasper_lee 0:b16d94660a33 10593 */ /* end of group RFSYS_Register_Masks */
Jasper_lee 0:b16d94660a33 10594
Jasper_lee 0:b16d94660a33 10595
Jasper_lee 0:b16d94660a33 10596 /* RFSYS - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10597 /** Peripheral RFSYS base address */
Jasper_lee 0:b16d94660a33 10598 #define RFSYS_BASE (0x40041000u)
Jasper_lee 0:b16d94660a33 10599 /** Peripheral RFSYS base pointer */
Jasper_lee 0:b16d94660a33 10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
Jasper_lee 0:b16d94660a33 10601 #define RFSYS_BASE_PTR (RFSYS)
Jasper_lee 0:b16d94660a33 10602 /** Array initializer of RFSYS peripheral base addresses */
Jasper_lee 0:b16d94660a33 10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
Jasper_lee 0:b16d94660a33 10604 /** Array initializer of RFSYS peripheral base pointers */
Jasper_lee 0:b16d94660a33 10605 #define RFSYS_BASE_PTRS { RFSYS }
Jasper_lee 0:b16d94660a33 10606
Jasper_lee 0:b16d94660a33 10607 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10608 -- RFSYS - Register accessor macros
Jasper_lee 0:b16d94660a33 10609 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10610
Jasper_lee 0:b16d94660a33 10611 /*!
Jasper_lee 0:b16d94660a33 10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Jasper_lee 0:b16d94660a33 10613 * @{
Jasper_lee 0:b16d94660a33 10614 */
Jasper_lee 0:b16d94660a33 10615
Jasper_lee 0:b16d94660a33 10616
Jasper_lee 0:b16d94660a33 10617 /* RFSYS - Register instance definitions */
Jasper_lee 0:b16d94660a33 10618 /* RFSYS */
Jasper_lee 0:b16d94660a33 10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
Jasper_lee 0:b16d94660a33 10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
Jasper_lee 0:b16d94660a33 10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
Jasper_lee 0:b16d94660a33 10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
Jasper_lee 0:b16d94660a33 10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
Jasper_lee 0:b16d94660a33 10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
Jasper_lee 0:b16d94660a33 10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
Jasper_lee 0:b16d94660a33 10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
Jasper_lee 0:b16d94660a33 10627
Jasper_lee 0:b16d94660a33 10628 /* RFSYS - Register array accessors */
Jasper_lee 0:b16d94660a33 10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
Jasper_lee 0:b16d94660a33 10630
Jasper_lee 0:b16d94660a33 10631 /*!
Jasper_lee 0:b16d94660a33 10632 * @}
Jasper_lee 0:b16d94660a33 10633 */ /* end of group RFSYS_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10634
Jasper_lee 0:b16d94660a33 10635
Jasper_lee 0:b16d94660a33 10636 /*!
Jasper_lee 0:b16d94660a33 10637 * @}
Jasper_lee 0:b16d94660a33 10638 */ /* end of group RFSYS_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10639
Jasper_lee 0:b16d94660a33 10640
Jasper_lee 0:b16d94660a33 10641 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10642 -- RFVBAT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10643 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10644
Jasper_lee 0:b16d94660a33 10645 /*!
Jasper_lee 0:b16d94660a33 10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10647 * @{
Jasper_lee 0:b16d94660a33 10648 */
Jasper_lee 0:b16d94660a33 10649
Jasper_lee 0:b16d94660a33 10650 /** RFVBAT - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10651 typedef struct {
Jasper_lee 0:b16d94660a33 10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 10653 } RFVBAT_Type, *RFVBAT_MemMapPtr;
Jasper_lee 0:b16d94660a33 10654
Jasper_lee 0:b16d94660a33 10655 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10656 -- RFVBAT - Register accessor macros
Jasper_lee 0:b16d94660a33 10657 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10658
Jasper_lee 0:b16d94660a33 10659 /*!
Jasper_lee 0:b16d94660a33 10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
Jasper_lee 0:b16d94660a33 10661 * @{
Jasper_lee 0:b16d94660a33 10662 */
Jasper_lee 0:b16d94660a33 10663
Jasper_lee 0:b16d94660a33 10664
Jasper_lee 0:b16d94660a33 10665 /* RFVBAT - Register accessors */
Jasper_lee 0:b16d94660a33 10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
Jasper_lee 0:b16d94660a33 10667
Jasper_lee 0:b16d94660a33 10668 /*!
Jasper_lee 0:b16d94660a33 10669 * @}
Jasper_lee 0:b16d94660a33 10670 */ /* end of group RFVBAT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10671
Jasper_lee 0:b16d94660a33 10672
Jasper_lee 0:b16d94660a33 10673 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10674 -- RFVBAT Register Masks
Jasper_lee 0:b16d94660a33 10675 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10676
Jasper_lee 0:b16d94660a33 10677 /*!
Jasper_lee 0:b16d94660a33 10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
Jasper_lee 0:b16d94660a33 10679 * @{
Jasper_lee 0:b16d94660a33 10680 */
Jasper_lee 0:b16d94660a33 10681
Jasper_lee 0:b16d94660a33 10682 /* REG Bit Fields */
Jasper_lee 0:b16d94660a33 10683 #define RFVBAT_REG_LL_MASK 0xFFu
Jasper_lee 0:b16d94660a33 10684 #define RFVBAT_REG_LL_SHIFT 0
Jasper_lee 0:b16d94660a33 10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
Jasper_lee 0:b16d94660a33 10686 #define RFVBAT_REG_LH_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 10687 #define RFVBAT_REG_LH_SHIFT 8
Jasper_lee 0:b16d94660a33 10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
Jasper_lee 0:b16d94660a33 10689 #define RFVBAT_REG_HL_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 10690 #define RFVBAT_REG_HL_SHIFT 16
Jasper_lee 0:b16d94660a33 10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
Jasper_lee 0:b16d94660a33 10692 #define RFVBAT_REG_HH_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 10693 #define RFVBAT_REG_HH_SHIFT 24
Jasper_lee 0:b16d94660a33 10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
Jasper_lee 0:b16d94660a33 10695
Jasper_lee 0:b16d94660a33 10696 /*!
Jasper_lee 0:b16d94660a33 10697 * @}
Jasper_lee 0:b16d94660a33 10698 */ /* end of group RFVBAT_Register_Masks */
Jasper_lee 0:b16d94660a33 10699
Jasper_lee 0:b16d94660a33 10700
Jasper_lee 0:b16d94660a33 10701 /* RFVBAT - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10702 /** Peripheral RFVBAT base address */
Jasper_lee 0:b16d94660a33 10703 #define RFVBAT_BASE (0x4003E000u)
Jasper_lee 0:b16d94660a33 10704 /** Peripheral RFVBAT base pointer */
Jasper_lee 0:b16d94660a33 10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
Jasper_lee 0:b16d94660a33 10706 #define RFVBAT_BASE_PTR (RFVBAT)
Jasper_lee 0:b16d94660a33 10707 /** Array initializer of RFVBAT peripheral base addresses */
Jasper_lee 0:b16d94660a33 10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
Jasper_lee 0:b16d94660a33 10709 /** Array initializer of RFVBAT peripheral base pointers */
Jasper_lee 0:b16d94660a33 10710 #define RFVBAT_BASE_PTRS { RFVBAT }
Jasper_lee 0:b16d94660a33 10711
Jasper_lee 0:b16d94660a33 10712 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10713 -- RFVBAT - Register accessor macros
Jasper_lee 0:b16d94660a33 10714 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10715
Jasper_lee 0:b16d94660a33 10716 /*!
Jasper_lee 0:b16d94660a33 10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
Jasper_lee 0:b16d94660a33 10718 * @{
Jasper_lee 0:b16d94660a33 10719 */
Jasper_lee 0:b16d94660a33 10720
Jasper_lee 0:b16d94660a33 10721
Jasper_lee 0:b16d94660a33 10722 /* RFVBAT - Register instance definitions */
Jasper_lee 0:b16d94660a33 10723 /* RFVBAT */
Jasper_lee 0:b16d94660a33 10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
Jasper_lee 0:b16d94660a33 10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
Jasper_lee 0:b16d94660a33 10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
Jasper_lee 0:b16d94660a33 10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
Jasper_lee 0:b16d94660a33 10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
Jasper_lee 0:b16d94660a33 10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
Jasper_lee 0:b16d94660a33 10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
Jasper_lee 0:b16d94660a33 10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
Jasper_lee 0:b16d94660a33 10732
Jasper_lee 0:b16d94660a33 10733 /* RFVBAT - Register array accessors */
Jasper_lee 0:b16d94660a33 10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
Jasper_lee 0:b16d94660a33 10735
Jasper_lee 0:b16d94660a33 10736 /*!
Jasper_lee 0:b16d94660a33 10737 * @}
Jasper_lee 0:b16d94660a33 10738 */ /* end of group RFVBAT_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10739
Jasper_lee 0:b16d94660a33 10740
Jasper_lee 0:b16d94660a33 10741 /*!
Jasper_lee 0:b16d94660a33 10742 * @}
Jasper_lee 0:b16d94660a33 10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10744
Jasper_lee 0:b16d94660a33 10745
Jasper_lee 0:b16d94660a33 10746 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10747 -- RNG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10748 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10749
Jasper_lee 0:b16d94660a33 10750 /*!
Jasper_lee 0:b16d94660a33 10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10752 * @{
Jasper_lee 0:b16d94660a33 10753 */
Jasper_lee 0:b16d94660a33 10754
Jasper_lee 0:b16d94660a33 10755 /** RNG - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10756 typedef struct {
Jasper_lee 0:b16d94660a33 10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 10761 } RNG_Type, *RNG_MemMapPtr;
Jasper_lee 0:b16d94660a33 10762
Jasper_lee 0:b16d94660a33 10763 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10764 -- RNG - Register accessor macros
Jasper_lee 0:b16d94660a33 10765 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10766
Jasper_lee 0:b16d94660a33 10767 /*!
Jasper_lee 0:b16d94660a33 10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
Jasper_lee 0:b16d94660a33 10769 * @{
Jasper_lee 0:b16d94660a33 10770 */
Jasper_lee 0:b16d94660a33 10771
Jasper_lee 0:b16d94660a33 10772
Jasper_lee 0:b16d94660a33 10773 /* RNG - Register accessors */
Jasper_lee 0:b16d94660a33 10774 #define RNG_CR_REG(base) ((base)->CR)
Jasper_lee 0:b16d94660a33 10775 #define RNG_SR_REG(base) ((base)->SR)
Jasper_lee 0:b16d94660a33 10776 #define RNG_ER_REG(base) ((base)->ER)
Jasper_lee 0:b16d94660a33 10777 #define RNG_OR_REG(base) ((base)->OR)
Jasper_lee 0:b16d94660a33 10778
Jasper_lee 0:b16d94660a33 10779 /*!
Jasper_lee 0:b16d94660a33 10780 * @}
Jasper_lee 0:b16d94660a33 10781 */ /* end of group RNG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10782
Jasper_lee 0:b16d94660a33 10783
Jasper_lee 0:b16d94660a33 10784 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10785 -- RNG Register Masks
Jasper_lee 0:b16d94660a33 10786 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10787
Jasper_lee 0:b16d94660a33 10788 /*!
Jasper_lee 0:b16d94660a33 10789 * @addtogroup RNG_Register_Masks RNG Register Masks
Jasper_lee 0:b16d94660a33 10790 * @{
Jasper_lee 0:b16d94660a33 10791 */
Jasper_lee 0:b16d94660a33 10792
Jasper_lee 0:b16d94660a33 10793 /* CR Bit Fields */
Jasper_lee 0:b16d94660a33 10794 #define RNG_CR_GO_MASK 0x1u
Jasper_lee 0:b16d94660a33 10795 #define RNG_CR_GO_SHIFT 0
Jasper_lee 0:b16d94660a33 10796 #define RNG_CR_HA_MASK 0x2u
Jasper_lee 0:b16d94660a33 10797 #define RNG_CR_HA_SHIFT 1
Jasper_lee 0:b16d94660a33 10798 #define RNG_CR_INTM_MASK 0x4u
Jasper_lee 0:b16d94660a33 10799 #define RNG_CR_INTM_SHIFT 2
Jasper_lee 0:b16d94660a33 10800 #define RNG_CR_CLRI_MASK 0x8u
Jasper_lee 0:b16d94660a33 10801 #define RNG_CR_CLRI_SHIFT 3
Jasper_lee 0:b16d94660a33 10802 #define RNG_CR_SLP_MASK 0x10u
Jasper_lee 0:b16d94660a33 10803 #define RNG_CR_SLP_SHIFT 4
Jasper_lee 0:b16d94660a33 10804 /* SR Bit Fields */
Jasper_lee 0:b16d94660a33 10805 #define RNG_SR_SECV_MASK 0x1u
Jasper_lee 0:b16d94660a33 10806 #define RNG_SR_SECV_SHIFT 0
Jasper_lee 0:b16d94660a33 10807 #define RNG_SR_LRS_MASK 0x2u
Jasper_lee 0:b16d94660a33 10808 #define RNG_SR_LRS_SHIFT 1
Jasper_lee 0:b16d94660a33 10809 #define RNG_SR_ORU_MASK 0x4u
Jasper_lee 0:b16d94660a33 10810 #define RNG_SR_ORU_SHIFT 2
Jasper_lee 0:b16d94660a33 10811 #define RNG_SR_ERRI_MASK 0x8u
Jasper_lee 0:b16d94660a33 10812 #define RNG_SR_ERRI_SHIFT 3
Jasper_lee 0:b16d94660a33 10813 #define RNG_SR_SLP_MASK 0x10u
Jasper_lee 0:b16d94660a33 10814 #define RNG_SR_SLP_SHIFT 4
Jasper_lee 0:b16d94660a33 10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 10816 #define RNG_SR_OREG_LVL_SHIFT 8
Jasper_lee 0:b16d94660a33 10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
Jasper_lee 0:b16d94660a33 10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 10819 #define RNG_SR_OREG_SIZE_SHIFT 16
Jasper_lee 0:b16d94660a33 10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
Jasper_lee 0:b16d94660a33 10821 /* ER Bit Fields */
Jasper_lee 0:b16d94660a33 10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10823 #define RNG_ER_EXT_ENT_SHIFT 0
Jasper_lee 0:b16d94660a33 10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
Jasper_lee 0:b16d94660a33 10825 /* OR Bit Fields */
Jasper_lee 0:b16d94660a33 10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10827 #define RNG_OR_RANDOUT_SHIFT 0
Jasper_lee 0:b16d94660a33 10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
Jasper_lee 0:b16d94660a33 10829
Jasper_lee 0:b16d94660a33 10830 /*!
Jasper_lee 0:b16d94660a33 10831 * @}
Jasper_lee 0:b16d94660a33 10832 */ /* end of group RNG_Register_Masks */
Jasper_lee 0:b16d94660a33 10833
Jasper_lee 0:b16d94660a33 10834
Jasper_lee 0:b16d94660a33 10835 /* RNG - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 10836 /** Peripheral RNG base address */
Jasper_lee 0:b16d94660a33 10837 #define RNG_BASE (0x40029000u)
Jasper_lee 0:b16d94660a33 10838 /** Peripheral RNG base pointer */
Jasper_lee 0:b16d94660a33 10839 #define RNG ((RNG_Type *)RNG_BASE)
Jasper_lee 0:b16d94660a33 10840 #define RNG_BASE_PTR (RNG)
Jasper_lee 0:b16d94660a33 10841 /** Array initializer of RNG peripheral base addresses */
Jasper_lee 0:b16d94660a33 10842 #define RNG_BASE_ADDRS { RNG_BASE }
Jasper_lee 0:b16d94660a33 10843 /** Array initializer of RNG peripheral base pointers */
Jasper_lee 0:b16d94660a33 10844 #define RNG_BASE_PTRS { RNG }
Jasper_lee 0:b16d94660a33 10845 /** Interrupt vectors for the RNG peripheral type */
Jasper_lee 0:b16d94660a33 10846 #define RNG_IRQS { RNG_IRQn }
Jasper_lee 0:b16d94660a33 10847
Jasper_lee 0:b16d94660a33 10848 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10849 -- RNG - Register accessor macros
Jasper_lee 0:b16d94660a33 10850 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10851
Jasper_lee 0:b16d94660a33 10852 /*!
Jasper_lee 0:b16d94660a33 10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
Jasper_lee 0:b16d94660a33 10854 * @{
Jasper_lee 0:b16d94660a33 10855 */
Jasper_lee 0:b16d94660a33 10856
Jasper_lee 0:b16d94660a33 10857
Jasper_lee 0:b16d94660a33 10858 /* RNG - Register instance definitions */
Jasper_lee 0:b16d94660a33 10859 /* RNG */
Jasper_lee 0:b16d94660a33 10860 #define RNG_CR RNG_CR_REG(RNG)
Jasper_lee 0:b16d94660a33 10861 #define RNG_SR RNG_SR_REG(RNG)
Jasper_lee 0:b16d94660a33 10862 #define RNG_ER RNG_ER_REG(RNG)
Jasper_lee 0:b16d94660a33 10863 #define RNG_OR RNG_OR_REG(RNG)
Jasper_lee 0:b16d94660a33 10864
Jasper_lee 0:b16d94660a33 10865 /*!
Jasper_lee 0:b16d94660a33 10866 * @}
Jasper_lee 0:b16d94660a33 10867 */ /* end of group RNG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10868
Jasper_lee 0:b16d94660a33 10869
Jasper_lee 0:b16d94660a33 10870 /*!
Jasper_lee 0:b16d94660a33 10871 * @}
Jasper_lee 0:b16d94660a33 10872 */ /* end of group RNG_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 10873
Jasper_lee 0:b16d94660a33 10874
Jasper_lee 0:b16d94660a33 10875 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10876 -- RTC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10877 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10878
Jasper_lee 0:b16d94660a33 10879 /*!
Jasper_lee 0:b16d94660a33 10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 10881 * @{
Jasper_lee 0:b16d94660a33 10882 */
Jasper_lee 0:b16d94660a33 10883
Jasper_lee 0:b16d94660a33 10884 /** RTC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 10885 typedef struct {
Jasper_lee 0:b16d94660a33 10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
Jasper_lee 0:b16d94660a33 10894 uint8_t RESERVED_0[2016];
Jasper_lee 0:b16d94660a33 10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
Jasper_lee 0:b16d94660a33 10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
Jasper_lee 0:b16d94660a33 10897 } RTC_Type, *RTC_MemMapPtr;
Jasper_lee 0:b16d94660a33 10898
Jasper_lee 0:b16d94660a33 10899 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10900 -- RTC - Register accessor macros
Jasper_lee 0:b16d94660a33 10901 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10902
Jasper_lee 0:b16d94660a33 10903 /*!
Jasper_lee 0:b16d94660a33 10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Jasper_lee 0:b16d94660a33 10905 * @{
Jasper_lee 0:b16d94660a33 10906 */
Jasper_lee 0:b16d94660a33 10907
Jasper_lee 0:b16d94660a33 10908
Jasper_lee 0:b16d94660a33 10909 /* RTC - Register accessors */
Jasper_lee 0:b16d94660a33 10910 #define RTC_TSR_REG(base) ((base)->TSR)
Jasper_lee 0:b16d94660a33 10911 #define RTC_TPR_REG(base) ((base)->TPR)
Jasper_lee 0:b16d94660a33 10912 #define RTC_TAR_REG(base) ((base)->TAR)
Jasper_lee 0:b16d94660a33 10913 #define RTC_TCR_REG(base) ((base)->TCR)
Jasper_lee 0:b16d94660a33 10914 #define RTC_CR_REG(base) ((base)->CR)
Jasper_lee 0:b16d94660a33 10915 #define RTC_SR_REG(base) ((base)->SR)
Jasper_lee 0:b16d94660a33 10916 #define RTC_LR_REG(base) ((base)->LR)
Jasper_lee 0:b16d94660a33 10917 #define RTC_IER_REG(base) ((base)->IER)
Jasper_lee 0:b16d94660a33 10918 #define RTC_WAR_REG(base) ((base)->WAR)
Jasper_lee 0:b16d94660a33 10919 #define RTC_RAR_REG(base) ((base)->RAR)
Jasper_lee 0:b16d94660a33 10920
Jasper_lee 0:b16d94660a33 10921 /*!
Jasper_lee 0:b16d94660a33 10922 * @}
Jasper_lee 0:b16d94660a33 10923 */ /* end of group RTC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 10924
Jasper_lee 0:b16d94660a33 10925
Jasper_lee 0:b16d94660a33 10926 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 10927 -- RTC Register Masks
Jasper_lee 0:b16d94660a33 10928 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 10929
Jasper_lee 0:b16d94660a33 10930 /*!
Jasper_lee 0:b16d94660a33 10931 * @addtogroup RTC_Register_Masks RTC Register Masks
Jasper_lee 0:b16d94660a33 10932 * @{
Jasper_lee 0:b16d94660a33 10933 */
Jasper_lee 0:b16d94660a33 10934
Jasper_lee 0:b16d94660a33 10935 /* TSR Bit Fields */
Jasper_lee 0:b16d94660a33 10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10937 #define RTC_TSR_TSR_SHIFT 0
Jasper_lee 0:b16d94660a33 10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
Jasper_lee 0:b16d94660a33 10939 /* TPR Bit Fields */
Jasper_lee 0:b16d94660a33 10940 #define RTC_TPR_TPR_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 10941 #define RTC_TPR_TPR_SHIFT 0
Jasper_lee 0:b16d94660a33 10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
Jasper_lee 0:b16d94660a33 10943 /* TAR Bit Fields */
Jasper_lee 0:b16d94660a33 10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 10945 #define RTC_TAR_TAR_SHIFT 0
Jasper_lee 0:b16d94660a33 10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
Jasper_lee 0:b16d94660a33 10947 /* TCR Bit Fields */
Jasper_lee 0:b16d94660a33 10948 #define RTC_TCR_TCR_MASK 0xFFu
Jasper_lee 0:b16d94660a33 10949 #define RTC_TCR_TCR_SHIFT 0
Jasper_lee 0:b16d94660a33 10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
Jasper_lee 0:b16d94660a33 10951 #define RTC_TCR_CIR_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 10952 #define RTC_TCR_CIR_SHIFT 8
Jasper_lee 0:b16d94660a33 10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
Jasper_lee 0:b16d94660a33 10954 #define RTC_TCR_TCV_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 10955 #define RTC_TCR_TCV_SHIFT 16
Jasper_lee 0:b16d94660a33 10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
Jasper_lee 0:b16d94660a33 10957 #define RTC_TCR_CIC_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 10958 #define RTC_TCR_CIC_SHIFT 24
Jasper_lee 0:b16d94660a33 10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
Jasper_lee 0:b16d94660a33 10960 /* CR Bit Fields */
Jasper_lee 0:b16d94660a33 10961 #define RTC_CR_SWR_MASK 0x1u
Jasper_lee 0:b16d94660a33 10962 #define RTC_CR_SWR_SHIFT 0
Jasper_lee 0:b16d94660a33 10963 #define RTC_CR_WPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 10964 #define RTC_CR_WPE_SHIFT 1
Jasper_lee 0:b16d94660a33 10965 #define RTC_CR_SUP_MASK 0x4u
Jasper_lee 0:b16d94660a33 10966 #define RTC_CR_SUP_SHIFT 2
Jasper_lee 0:b16d94660a33 10967 #define RTC_CR_UM_MASK 0x8u
Jasper_lee 0:b16d94660a33 10968 #define RTC_CR_UM_SHIFT 3
Jasper_lee 0:b16d94660a33 10969 #define RTC_CR_WPS_MASK 0x10u
Jasper_lee 0:b16d94660a33 10970 #define RTC_CR_WPS_SHIFT 4
Jasper_lee 0:b16d94660a33 10971 #define RTC_CR_OSCE_MASK 0x100u
Jasper_lee 0:b16d94660a33 10972 #define RTC_CR_OSCE_SHIFT 8
Jasper_lee 0:b16d94660a33 10973 #define RTC_CR_CLKO_MASK 0x200u
Jasper_lee 0:b16d94660a33 10974 #define RTC_CR_CLKO_SHIFT 9
Jasper_lee 0:b16d94660a33 10975 #define RTC_CR_SC16P_MASK 0x400u
Jasper_lee 0:b16d94660a33 10976 #define RTC_CR_SC16P_SHIFT 10
Jasper_lee 0:b16d94660a33 10977 #define RTC_CR_SC8P_MASK 0x800u
Jasper_lee 0:b16d94660a33 10978 #define RTC_CR_SC8P_SHIFT 11
Jasper_lee 0:b16d94660a33 10979 #define RTC_CR_SC4P_MASK 0x1000u
Jasper_lee 0:b16d94660a33 10980 #define RTC_CR_SC4P_SHIFT 12
Jasper_lee 0:b16d94660a33 10981 #define RTC_CR_SC2P_MASK 0x2000u
Jasper_lee 0:b16d94660a33 10982 #define RTC_CR_SC2P_SHIFT 13
Jasper_lee 0:b16d94660a33 10983 /* SR Bit Fields */
Jasper_lee 0:b16d94660a33 10984 #define RTC_SR_TIF_MASK 0x1u
Jasper_lee 0:b16d94660a33 10985 #define RTC_SR_TIF_SHIFT 0
Jasper_lee 0:b16d94660a33 10986 #define RTC_SR_TOF_MASK 0x2u
Jasper_lee 0:b16d94660a33 10987 #define RTC_SR_TOF_SHIFT 1
Jasper_lee 0:b16d94660a33 10988 #define RTC_SR_TAF_MASK 0x4u
Jasper_lee 0:b16d94660a33 10989 #define RTC_SR_TAF_SHIFT 2
Jasper_lee 0:b16d94660a33 10990 #define RTC_SR_TCE_MASK 0x10u
Jasper_lee 0:b16d94660a33 10991 #define RTC_SR_TCE_SHIFT 4
Jasper_lee 0:b16d94660a33 10992 /* LR Bit Fields */
Jasper_lee 0:b16d94660a33 10993 #define RTC_LR_TCL_MASK 0x8u
Jasper_lee 0:b16d94660a33 10994 #define RTC_LR_TCL_SHIFT 3
Jasper_lee 0:b16d94660a33 10995 #define RTC_LR_CRL_MASK 0x10u
Jasper_lee 0:b16d94660a33 10996 #define RTC_LR_CRL_SHIFT 4
Jasper_lee 0:b16d94660a33 10997 #define RTC_LR_SRL_MASK 0x20u
Jasper_lee 0:b16d94660a33 10998 #define RTC_LR_SRL_SHIFT 5
Jasper_lee 0:b16d94660a33 10999 #define RTC_LR_LRL_MASK 0x40u
Jasper_lee 0:b16d94660a33 11000 #define RTC_LR_LRL_SHIFT 6
Jasper_lee 0:b16d94660a33 11001 /* IER Bit Fields */
Jasper_lee 0:b16d94660a33 11002 #define RTC_IER_TIIE_MASK 0x1u
Jasper_lee 0:b16d94660a33 11003 #define RTC_IER_TIIE_SHIFT 0
Jasper_lee 0:b16d94660a33 11004 #define RTC_IER_TOIE_MASK 0x2u
Jasper_lee 0:b16d94660a33 11005 #define RTC_IER_TOIE_SHIFT 1
Jasper_lee 0:b16d94660a33 11006 #define RTC_IER_TAIE_MASK 0x4u
Jasper_lee 0:b16d94660a33 11007 #define RTC_IER_TAIE_SHIFT 2
Jasper_lee 0:b16d94660a33 11008 #define RTC_IER_TSIE_MASK 0x10u
Jasper_lee 0:b16d94660a33 11009 #define RTC_IER_TSIE_SHIFT 4
Jasper_lee 0:b16d94660a33 11010 #define RTC_IER_WPON_MASK 0x80u
Jasper_lee 0:b16d94660a33 11011 #define RTC_IER_WPON_SHIFT 7
Jasper_lee 0:b16d94660a33 11012 /* WAR Bit Fields */
Jasper_lee 0:b16d94660a33 11013 #define RTC_WAR_TSRW_MASK 0x1u
Jasper_lee 0:b16d94660a33 11014 #define RTC_WAR_TSRW_SHIFT 0
Jasper_lee 0:b16d94660a33 11015 #define RTC_WAR_TPRW_MASK 0x2u
Jasper_lee 0:b16d94660a33 11016 #define RTC_WAR_TPRW_SHIFT 1
Jasper_lee 0:b16d94660a33 11017 #define RTC_WAR_TARW_MASK 0x4u
Jasper_lee 0:b16d94660a33 11018 #define RTC_WAR_TARW_SHIFT 2
Jasper_lee 0:b16d94660a33 11019 #define RTC_WAR_TCRW_MASK 0x8u
Jasper_lee 0:b16d94660a33 11020 #define RTC_WAR_TCRW_SHIFT 3
Jasper_lee 0:b16d94660a33 11021 #define RTC_WAR_CRW_MASK 0x10u
Jasper_lee 0:b16d94660a33 11022 #define RTC_WAR_CRW_SHIFT 4
Jasper_lee 0:b16d94660a33 11023 #define RTC_WAR_SRW_MASK 0x20u
Jasper_lee 0:b16d94660a33 11024 #define RTC_WAR_SRW_SHIFT 5
Jasper_lee 0:b16d94660a33 11025 #define RTC_WAR_LRW_MASK 0x40u
Jasper_lee 0:b16d94660a33 11026 #define RTC_WAR_LRW_SHIFT 6
Jasper_lee 0:b16d94660a33 11027 #define RTC_WAR_IERW_MASK 0x80u
Jasper_lee 0:b16d94660a33 11028 #define RTC_WAR_IERW_SHIFT 7
Jasper_lee 0:b16d94660a33 11029 /* RAR Bit Fields */
Jasper_lee 0:b16d94660a33 11030 #define RTC_RAR_TSRR_MASK 0x1u
Jasper_lee 0:b16d94660a33 11031 #define RTC_RAR_TSRR_SHIFT 0
Jasper_lee 0:b16d94660a33 11032 #define RTC_RAR_TPRR_MASK 0x2u
Jasper_lee 0:b16d94660a33 11033 #define RTC_RAR_TPRR_SHIFT 1
Jasper_lee 0:b16d94660a33 11034 #define RTC_RAR_TARR_MASK 0x4u
Jasper_lee 0:b16d94660a33 11035 #define RTC_RAR_TARR_SHIFT 2
Jasper_lee 0:b16d94660a33 11036 #define RTC_RAR_TCRR_MASK 0x8u
Jasper_lee 0:b16d94660a33 11037 #define RTC_RAR_TCRR_SHIFT 3
Jasper_lee 0:b16d94660a33 11038 #define RTC_RAR_CRR_MASK 0x10u
Jasper_lee 0:b16d94660a33 11039 #define RTC_RAR_CRR_SHIFT 4
Jasper_lee 0:b16d94660a33 11040 #define RTC_RAR_SRR_MASK 0x20u
Jasper_lee 0:b16d94660a33 11041 #define RTC_RAR_SRR_SHIFT 5
Jasper_lee 0:b16d94660a33 11042 #define RTC_RAR_LRR_MASK 0x40u
Jasper_lee 0:b16d94660a33 11043 #define RTC_RAR_LRR_SHIFT 6
Jasper_lee 0:b16d94660a33 11044 #define RTC_RAR_IERR_MASK 0x80u
Jasper_lee 0:b16d94660a33 11045 #define RTC_RAR_IERR_SHIFT 7
Jasper_lee 0:b16d94660a33 11046
Jasper_lee 0:b16d94660a33 11047 /*!
Jasper_lee 0:b16d94660a33 11048 * @}
Jasper_lee 0:b16d94660a33 11049 */ /* end of group RTC_Register_Masks */
Jasper_lee 0:b16d94660a33 11050
Jasper_lee 0:b16d94660a33 11051
Jasper_lee 0:b16d94660a33 11052 /* RTC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 11053 /** Peripheral RTC base address */
Jasper_lee 0:b16d94660a33 11054 #define RTC_BASE (0x4003D000u)
Jasper_lee 0:b16d94660a33 11055 /** Peripheral RTC base pointer */
Jasper_lee 0:b16d94660a33 11056 #define RTC ((RTC_Type *)RTC_BASE)
Jasper_lee 0:b16d94660a33 11057 #define RTC_BASE_PTR (RTC)
Jasper_lee 0:b16d94660a33 11058 /** Array initializer of RTC peripheral base addresses */
Jasper_lee 0:b16d94660a33 11059 #define RTC_BASE_ADDRS { RTC_BASE }
Jasper_lee 0:b16d94660a33 11060 /** Array initializer of RTC peripheral base pointers */
Jasper_lee 0:b16d94660a33 11061 #define RTC_BASE_PTRS { RTC }
Jasper_lee 0:b16d94660a33 11062 /** Interrupt vectors for the RTC peripheral type */
Jasper_lee 0:b16d94660a33 11063 #define RTC_IRQS { RTC_IRQn }
Jasper_lee 0:b16d94660a33 11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
Jasper_lee 0:b16d94660a33 11065
Jasper_lee 0:b16d94660a33 11066 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11067 -- RTC - Register accessor macros
Jasper_lee 0:b16d94660a33 11068 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11069
Jasper_lee 0:b16d94660a33 11070 /*!
Jasper_lee 0:b16d94660a33 11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Jasper_lee 0:b16d94660a33 11072 * @{
Jasper_lee 0:b16d94660a33 11073 */
Jasper_lee 0:b16d94660a33 11074
Jasper_lee 0:b16d94660a33 11075
Jasper_lee 0:b16d94660a33 11076 /* RTC - Register instance definitions */
Jasper_lee 0:b16d94660a33 11077 /* RTC */
Jasper_lee 0:b16d94660a33 11078 #define RTC_TSR RTC_TSR_REG(RTC)
Jasper_lee 0:b16d94660a33 11079 #define RTC_TPR RTC_TPR_REG(RTC)
Jasper_lee 0:b16d94660a33 11080 #define RTC_TAR RTC_TAR_REG(RTC)
Jasper_lee 0:b16d94660a33 11081 #define RTC_TCR RTC_TCR_REG(RTC)
Jasper_lee 0:b16d94660a33 11082 #define RTC_CR RTC_CR_REG(RTC)
Jasper_lee 0:b16d94660a33 11083 #define RTC_SR RTC_SR_REG(RTC)
Jasper_lee 0:b16d94660a33 11084 #define RTC_LR RTC_LR_REG(RTC)
Jasper_lee 0:b16d94660a33 11085 #define RTC_IER RTC_IER_REG(RTC)
Jasper_lee 0:b16d94660a33 11086 #define RTC_WAR RTC_WAR_REG(RTC)
Jasper_lee 0:b16d94660a33 11087 #define RTC_RAR RTC_RAR_REG(RTC)
Jasper_lee 0:b16d94660a33 11088
Jasper_lee 0:b16d94660a33 11089 /*!
Jasper_lee 0:b16d94660a33 11090 * @}
Jasper_lee 0:b16d94660a33 11091 */ /* end of group RTC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 11092
Jasper_lee 0:b16d94660a33 11093
Jasper_lee 0:b16d94660a33 11094 /*!
Jasper_lee 0:b16d94660a33 11095 * @}
Jasper_lee 0:b16d94660a33 11096 */ /* end of group RTC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 11097
Jasper_lee 0:b16d94660a33 11098
Jasper_lee 0:b16d94660a33 11099 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11100 -- SDHC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 11101 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11102
Jasper_lee 0:b16d94660a33 11103 /*!
Jasper_lee 0:b16d94660a33 11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 11105 * @{
Jasper_lee 0:b16d94660a33 11106 */
Jasper_lee 0:b16d94660a33 11107
Jasper_lee 0:b16d94660a33 11108 /** SDHC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 11109 typedef struct {
Jasper_lee 0:b16d94660a33 11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
Jasper_lee 0:b16d94660a33 11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
Jasper_lee 0:b16d94660a33 11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
Jasper_lee 0:b16d94660a33 11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
Jasper_lee 0:b16d94660a33 11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
Jasper_lee 0:b16d94660a33 11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
Jasper_lee 0:b16d94660a33 11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
Jasper_lee 0:b16d94660a33 11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
Jasper_lee 0:b16d94660a33 11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
Jasper_lee 0:b16d94660a33 11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
Jasper_lee 0:b16d94660a33 11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
Jasper_lee 0:b16d94660a33 11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
Jasper_lee 0:b16d94660a33 11125 uint8_t RESERVED_0[8];
Jasper_lee 0:b16d94660a33 11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
Jasper_lee 0:b16d94660a33 11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
Jasper_lee 0:b16d94660a33 11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
Jasper_lee 0:b16d94660a33 11129 uint8_t RESERVED_1[100];
Jasper_lee 0:b16d94660a33 11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
Jasper_lee 0:b16d94660a33 11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
Jasper_lee 0:b16d94660a33 11132 uint8_t RESERVED_2[52];
Jasper_lee 0:b16d94660a33 11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
Jasper_lee 0:b16d94660a33 11134 } SDHC_Type, *SDHC_MemMapPtr;
Jasper_lee 0:b16d94660a33 11135
Jasper_lee 0:b16d94660a33 11136 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11137 -- SDHC - Register accessor macros
Jasper_lee 0:b16d94660a33 11138 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11139
Jasper_lee 0:b16d94660a33 11140 /*!
Jasper_lee 0:b16d94660a33 11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
Jasper_lee 0:b16d94660a33 11142 * @{
Jasper_lee 0:b16d94660a33 11143 */
Jasper_lee 0:b16d94660a33 11144
Jasper_lee 0:b16d94660a33 11145
Jasper_lee 0:b16d94660a33 11146 /* SDHC - Register accessors */
Jasper_lee 0:b16d94660a33 11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
Jasper_lee 0:b16d94660a33 11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
Jasper_lee 0:b16d94660a33 11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
Jasper_lee 0:b16d94660a33 11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
Jasper_lee 0:b16d94660a33 11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
Jasper_lee 0:b16d94660a33 11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
Jasper_lee 0:b16d94660a33 11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
Jasper_lee 0:b16d94660a33 11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
Jasper_lee 0:b16d94660a33 11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
Jasper_lee 0:b16d94660a33 11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
Jasper_lee 0:b16d94660a33 11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
Jasper_lee 0:b16d94660a33 11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
Jasper_lee 0:b16d94660a33 11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
Jasper_lee 0:b16d94660a33 11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
Jasper_lee 0:b16d94660a33 11161 #define SDHC_WML_REG(base) ((base)->WML)
Jasper_lee 0:b16d94660a33 11162 #define SDHC_FEVT_REG(base) ((base)->FEVT)
Jasper_lee 0:b16d94660a33 11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
Jasper_lee 0:b16d94660a33 11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
Jasper_lee 0:b16d94660a33 11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
Jasper_lee 0:b16d94660a33 11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
Jasper_lee 0:b16d94660a33 11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
Jasper_lee 0:b16d94660a33 11168
Jasper_lee 0:b16d94660a33 11169 /*!
Jasper_lee 0:b16d94660a33 11170 * @}
Jasper_lee 0:b16d94660a33 11171 */ /* end of group SDHC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 11172
Jasper_lee 0:b16d94660a33 11173
Jasper_lee 0:b16d94660a33 11174 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11175 -- SDHC Register Masks
Jasper_lee 0:b16d94660a33 11176 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11177
Jasper_lee 0:b16d94660a33 11178 /*!
Jasper_lee 0:b16d94660a33 11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks
Jasper_lee 0:b16d94660a33 11180 * @{
Jasper_lee 0:b16d94660a33 11181 */
Jasper_lee 0:b16d94660a33 11182
Jasper_lee 0:b16d94660a33 11183 /* DSADDR Bit Fields */
Jasper_lee 0:b16d94660a33 11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
Jasper_lee 0:b16d94660a33 11185 #define SDHC_DSADDR_DSADDR_SHIFT 2
Jasper_lee 0:b16d94660a33 11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
Jasper_lee 0:b16d94660a33 11187 /* BLKATTR Bit Fields */
Jasper_lee 0:b16d94660a33 11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
Jasper_lee 0:b16d94660a33 11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
Jasper_lee 0:b16d94660a33 11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
Jasper_lee 0:b16d94660a33 11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
Jasper_lee 0:b16d94660a33 11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
Jasper_lee 0:b16d94660a33 11194 /* CMDARG Bit Fields */
Jasper_lee 0:b16d94660a33 11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11196 #define SDHC_CMDARG_CMDARG_SHIFT 0
Jasper_lee 0:b16d94660a33 11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
Jasper_lee 0:b16d94660a33 11198 /* XFERTYP Bit Fields */
Jasper_lee 0:b16d94660a33 11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0
Jasper_lee 0:b16d94660a33 11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 11202 #define SDHC_XFERTYP_BCEN_SHIFT 1
Jasper_lee 0:b16d94660a33 11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
Jasper_lee 0:b16d94660a33 11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2
Jasper_lee 0:b16d94660a33 11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
Jasper_lee 0:b16d94660a33 11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
Jasper_lee 0:b16d94660a33 11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
Jasper_lee 0:b16d94660a33 11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
Jasper_lee 0:b16d94660a33 11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
Jasper_lee 0:b16d94660a33 11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
Jasper_lee 0:b16d94660a33 11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19
Jasper_lee 0:b16d94660a33 11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11215 #define SDHC_XFERTYP_CICEN_SHIFT 20
Jasper_lee 0:b16d94660a33 11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21
Jasper_lee 0:b16d94660a33 11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
Jasper_lee 0:b16d94660a33 11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
Jasper_lee 0:b16d94660a33 11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
Jasper_lee 0:b16d94660a33 11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
Jasper_lee 0:b16d94660a33 11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24
Jasper_lee 0:b16d94660a33 11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
Jasper_lee 0:b16d94660a33 11224 /* CMDRSP Bit Fields */
Jasper_lee 0:b16d94660a33 11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
Jasper_lee 0:b16d94660a33 11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
Jasper_lee 0:b16d94660a33 11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
Jasper_lee 0:b16d94660a33 11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
Jasper_lee 0:b16d94660a33 11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
Jasper_lee 0:b16d94660a33 11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
Jasper_lee 0:b16d94660a33 11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
Jasper_lee 0:b16d94660a33 11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
Jasper_lee 0:b16d94660a33 11237 /* DATPORT Bit Fields */
Jasper_lee 0:b16d94660a33 11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11239 #define SDHC_DATPORT_DATCONT_SHIFT 0
Jasper_lee 0:b16d94660a33 11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
Jasper_lee 0:b16d94660a33 11241 /* PRSSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
Jasper_lee 0:b16d94660a33 11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0
Jasper_lee 0:b16d94660a33 11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
Jasper_lee 0:b16d94660a33 11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
Jasper_lee 0:b16d94660a33 11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u
Jasper_lee 0:b16d94660a33 11247 #define SDHC_PRSSTAT_DLA_SHIFT 2
Jasper_lee 0:b16d94660a33 11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
Jasper_lee 0:b16d94660a33 11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
Jasper_lee 0:b16d94660a33 11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
Jasper_lee 0:b16d94660a33 11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
Jasper_lee 0:b16d94660a33 11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
Jasper_lee 0:b16d94660a33 11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
Jasper_lee 0:b16d94660a33 11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
Jasper_lee 0:b16d94660a33 11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
Jasper_lee 0:b16d94660a33 11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
Jasper_lee 0:b16d94660a33 11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
Jasper_lee 0:b16d94660a33 11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u
Jasper_lee 0:b16d94660a33 11259 #define SDHC_PRSSTAT_WTA_SHIFT 8
Jasper_lee 0:b16d94660a33 11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u
Jasper_lee 0:b16d94660a33 11261 #define SDHC_PRSSTAT_RTA_SHIFT 9
Jasper_lee 0:b16d94660a33 11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
Jasper_lee 0:b16d94660a33 11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10
Jasper_lee 0:b16d94660a33 11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u
Jasper_lee 0:b16d94660a33 11265 #define SDHC_PRSSTAT_BREN_SHIFT 11
Jasper_lee 0:b16d94660a33 11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11267 #define SDHC_PRSSTAT_CINS_SHIFT 16
Jasper_lee 0:b16d94660a33 11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
Jasper_lee 0:b16d94660a33 11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23
Jasper_lee 0:b16d94660a33 11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
Jasper_lee 0:b16d94660a33 11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24
Jasper_lee 0:b16d94660a33 11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
Jasper_lee 0:b16d94660a33 11273 /* PROCTL Bit Fields */
Jasper_lee 0:b16d94660a33 11274 #define SDHC_PROCTL_LCTL_MASK 0x1u
Jasper_lee 0:b16d94660a33 11275 #define SDHC_PROCTL_LCTL_SHIFT 0
Jasper_lee 0:b16d94660a33 11276 #define SDHC_PROCTL_DTW_MASK 0x6u
Jasper_lee 0:b16d94660a33 11277 #define SDHC_PROCTL_DTW_SHIFT 1
Jasper_lee 0:b16d94660a33 11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
Jasper_lee 0:b16d94660a33 11279 #define SDHC_PROCTL_D3CD_MASK 0x8u
Jasper_lee 0:b16d94660a33 11280 #define SDHC_PROCTL_D3CD_SHIFT 3
Jasper_lee 0:b16d94660a33 11281 #define SDHC_PROCTL_EMODE_MASK 0x30u
Jasper_lee 0:b16d94660a33 11282 #define SDHC_PROCTL_EMODE_SHIFT 4
Jasper_lee 0:b16d94660a33 11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
Jasper_lee 0:b16d94660a33 11284 #define SDHC_PROCTL_CDTL_MASK 0x40u
Jasper_lee 0:b16d94660a33 11285 #define SDHC_PROCTL_CDTL_SHIFT 6
Jasper_lee 0:b16d94660a33 11286 #define SDHC_PROCTL_CDSS_MASK 0x80u
Jasper_lee 0:b16d94660a33 11287 #define SDHC_PROCTL_CDSS_SHIFT 7
Jasper_lee 0:b16d94660a33 11288 #define SDHC_PROCTL_DMAS_MASK 0x300u
Jasper_lee 0:b16d94660a33 11289 #define SDHC_PROCTL_DMAS_SHIFT 8
Jasper_lee 0:b16d94660a33 11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
Jasper_lee 0:b16d94660a33 11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16
Jasper_lee 0:b16d94660a33 11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11294 #define SDHC_PROCTL_CREQ_SHIFT 17
Jasper_lee 0:b16d94660a33 11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11296 #define SDHC_PROCTL_RWCTL_SHIFT 18
Jasper_lee 0:b16d94660a33 11297 #define SDHC_PROCTL_IABG_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11298 #define SDHC_PROCTL_IABG_SHIFT 19
Jasper_lee 0:b16d94660a33 11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11300 #define SDHC_PROCTL_WECINT_SHIFT 24
Jasper_lee 0:b16d94660a33 11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11302 #define SDHC_PROCTL_WECINS_SHIFT 25
Jasper_lee 0:b16d94660a33 11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 11304 #define SDHC_PROCTL_WECRM_SHIFT 26
Jasper_lee 0:b16d94660a33 11305 /* SYSCTL Bit Fields */
Jasper_lee 0:b16d94660a33 11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0
Jasper_lee 0:b16d94660a33 11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1
Jasper_lee 0:b16d94660a33 11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u
Jasper_lee 0:b16d94660a33 11311 #define SDHC_SYSCTL_PEREN_SHIFT 2
Jasper_lee 0:b16d94660a33 11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
Jasper_lee 0:b16d94660a33 11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u
Jasper_lee 0:b16d94660a33 11315 #define SDHC_SYSCTL_DVS_SHIFT 4
Jasper_lee 0:b16d94660a33 11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
Jasper_lee 0:b16d94660a33 11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
Jasper_lee 0:b16d94660a33 11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
Jasper_lee 0:b16d94660a33 11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16
Jasper_lee 0:b16d94660a33 11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
Jasper_lee 0:b16d94660a33 11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11324 #define SDHC_SYSCTL_RSTA_SHIFT 24
Jasper_lee 0:b16d94660a33 11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11326 #define SDHC_SYSCTL_RSTC_SHIFT 25
Jasper_lee 0:b16d94660a33 11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 11328 #define SDHC_SYSCTL_RSTD_SHIFT 26
Jasper_lee 0:b16d94660a33 11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 11330 #define SDHC_SYSCTL_INITA_SHIFT 27
Jasper_lee 0:b16d94660a33 11331 /* IRQSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 11332 #define SDHC_IRQSTAT_CC_MASK 0x1u
Jasper_lee 0:b16d94660a33 11333 #define SDHC_IRQSTAT_CC_SHIFT 0
Jasper_lee 0:b16d94660a33 11334 #define SDHC_IRQSTAT_TC_MASK 0x2u
Jasper_lee 0:b16d94660a33 11335 #define SDHC_IRQSTAT_TC_SHIFT 1
Jasper_lee 0:b16d94660a33 11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u
Jasper_lee 0:b16d94660a33 11337 #define SDHC_IRQSTAT_BGE_SHIFT 2
Jasper_lee 0:b16d94660a33 11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u
Jasper_lee 0:b16d94660a33 11339 #define SDHC_IRQSTAT_DINT_SHIFT 3
Jasper_lee 0:b16d94660a33 11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u
Jasper_lee 0:b16d94660a33 11341 #define SDHC_IRQSTAT_BWR_SHIFT 4
Jasper_lee 0:b16d94660a33 11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u
Jasper_lee 0:b16d94660a33 11343 #define SDHC_IRQSTAT_BRR_SHIFT 5
Jasper_lee 0:b16d94660a33 11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u
Jasper_lee 0:b16d94660a33 11345 #define SDHC_IRQSTAT_CINS_SHIFT 6
Jasper_lee 0:b16d94660a33 11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u
Jasper_lee 0:b16d94660a33 11347 #define SDHC_IRQSTAT_CRM_SHIFT 7
Jasper_lee 0:b16d94660a33 11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u
Jasper_lee 0:b16d94660a33 11349 #define SDHC_IRQSTAT_CINT_SHIFT 8
Jasper_lee 0:b16d94660a33 11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16
Jasper_lee 0:b16d94660a33 11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11353 #define SDHC_IRQSTAT_CCE_SHIFT 17
Jasper_lee 0:b16d94660a33 11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18
Jasper_lee 0:b16d94660a33 11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11357 #define SDHC_IRQSTAT_CIE_SHIFT 19
Jasper_lee 0:b16d94660a33 11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20
Jasper_lee 0:b16d94660a33 11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11361 #define SDHC_IRQSTAT_DCE_SHIFT 21
Jasper_lee 0:b16d94660a33 11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22
Jasper_lee 0:b16d94660a33 11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24
Jasper_lee 0:b16d94660a33 11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28
Jasper_lee 0:b16d94660a33 11368 /* IRQSTATEN Bit Fields */
Jasper_lee 0:b16d94660a33 11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
Jasper_lee 0:b16d94660a33 11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
Jasper_lee 0:b16d94660a33 11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
Jasper_lee 0:b16d94660a33 11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
Jasper_lee 0:b16d94660a33 11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
Jasper_lee 0:b16d94660a33 11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
Jasper_lee 0:b16d94660a33 11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
Jasper_lee 0:b16d94660a33 11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
Jasper_lee 0:b16d94660a33 11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
Jasper_lee 0:b16d94660a33 11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
Jasper_lee 0:b16d94660a33 11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
Jasper_lee 0:b16d94660a33 11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
Jasper_lee 0:b16d94660a33 11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
Jasper_lee 0:b16d94660a33 11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
Jasper_lee 0:b16d94660a33 11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
Jasper_lee 0:b16d94660a33 11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
Jasper_lee 0:b16d94660a33 11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
Jasper_lee 0:b16d94660a33 11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
Jasper_lee 0:b16d94660a33 11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
Jasper_lee 0:b16d94660a33 11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
Jasper_lee 0:b16d94660a33 11405 /* IRQSIGEN Bit Fields */
Jasper_lee 0:b16d94660a33 11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
Jasper_lee 0:b16d94660a33 11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
Jasper_lee 0:b16d94660a33 11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
Jasper_lee 0:b16d94660a33 11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
Jasper_lee 0:b16d94660a33 11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
Jasper_lee 0:b16d94660a33 11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
Jasper_lee 0:b16d94660a33 11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
Jasper_lee 0:b16d94660a33 11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
Jasper_lee 0:b16d94660a33 11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
Jasper_lee 0:b16d94660a33 11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
Jasper_lee 0:b16d94660a33 11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
Jasper_lee 0:b16d94660a33 11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
Jasper_lee 0:b16d94660a33 11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
Jasper_lee 0:b16d94660a33 11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
Jasper_lee 0:b16d94660a33 11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
Jasper_lee 0:b16d94660a33 11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
Jasper_lee 0:b16d94660a33 11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
Jasper_lee 0:b16d94660a33 11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
Jasper_lee 0:b16d94660a33 11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
Jasper_lee 0:b16d94660a33 11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
Jasper_lee 0:b16d94660a33 11442 /* AC12ERR Bit Fields */
Jasper_lee 0:b16d94660a33 11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
Jasper_lee 0:b16d94660a33 11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0
Jasper_lee 0:b16d94660a33 11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
Jasper_lee 0:b16d94660a33 11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
Jasper_lee 0:b16d94660a33 11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
Jasper_lee 0:b16d94660a33 11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
Jasper_lee 0:b16d94660a33 11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
Jasper_lee 0:b16d94660a33 11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3
Jasper_lee 0:b16d94660a33 11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
Jasper_lee 0:b16d94660a33 11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4
Jasper_lee 0:b16d94660a33 11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
Jasper_lee 0:b16d94660a33 11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
Jasper_lee 0:b16d94660a33 11455 /* HTCAPBLT Bit Fields */
Jasper_lee 0:b16d94660a33 11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
Jasper_lee 0:b16d94660a33 11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16
Jasper_lee 0:b16d94660a33 11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
Jasper_lee 0:b16d94660a33 11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
Jasper_lee 0:b16d94660a33 11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21
Jasper_lee 0:b16d94660a33 11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
Jasper_lee 0:b16d94660a33 11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
Jasper_lee 0:b16d94660a33 11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23
Jasper_lee 0:b16d94660a33 11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24
Jasper_lee 0:b16d94660a33 11469 /* WML Bit Fields */
Jasper_lee 0:b16d94660a33 11470 #define SDHC_WML_RDWML_MASK 0xFFu
Jasper_lee 0:b16d94660a33 11471 #define SDHC_WML_RDWML_SHIFT 0
Jasper_lee 0:b16d94660a33 11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
Jasper_lee 0:b16d94660a33 11473 #define SDHC_WML_WRWML_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 11474 #define SDHC_WML_WRWML_SHIFT 16
Jasper_lee 0:b16d94660a33 11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
Jasper_lee 0:b16d94660a33 11476 /* FEVT Bit Fields */
Jasper_lee 0:b16d94660a33 11477 #define SDHC_FEVT_AC12NE_MASK 0x1u
Jasper_lee 0:b16d94660a33 11478 #define SDHC_FEVT_AC12NE_SHIFT 0
Jasper_lee 0:b16d94660a33 11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u
Jasper_lee 0:b16d94660a33 11480 #define SDHC_FEVT_AC12TOE_SHIFT 1
Jasper_lee 0:b16d94660a33 11481 #define SDHC_FEVT_AC12CE_MASK 0x4u
Jasper_lee 0:b16d94660a33 11482 #define SDHC_FEVT_AC12CE_SHIFT 2
Jasper_lee 0:b16d94660a33 11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u
Jasper_lee 0:b16d94660a33 11484 #define SDHC_FEVT_AC12EBE_SHIFT 3
Jasper_lee 0:b16d94660a33 11485 #define SDHC_FEVT_AC12IE_MASK 0x10u
Jasper_lee 0:b16d94660a33 11486 #define SDHC_FEVT_AC12IE_SHIFT 4
Jasper_lee 0:b16d94660a33 11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
Jasper_lee 0:b16d94660a33 11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
Jasper_lee 0:b16d94660a33 11489 #define SDHC_FEVT_CTOE_MASK 0x10000u
Jasper_lee 0:b16d94660a33 11490 #define SDHC_FEVT_CTOE_SHIFT 16
Jasper_lee 0:b16d94660a33 11491 #define SDHC_FEVT_CCE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11492 #define SDHC_FEVT_CCE_SHIFT 17
Jasper_lee 0:b16d94660a33 11493 #define SDHC_FEVT_CEBE_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11494 #define SDHC_FEVT_CEBE_SHIFT 18
Jasper_lee 0:b16d94660a33 11495 #define SDHC_FEVT_CIE_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11496 #define SDHC_FEVT_CIE_SHIFT 19
Jasper_lee 0:b16d94660a33 11497 #define SDHC_FEVT_DTOE_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11498 #define SDHC_FEVT_DTOE_SHIFT 20
Jasper_lee 0:b16d94660a33 11499 #define SDHC_FEVT_DCE_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11500 #define SDHC_FEVT_DCE_SHIFT 21
Jasper_lee 0:b16d94660a33 11501 #define SDHC_FEVT_DEBE_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11502 #define SDHC_FEVT_DEBE_SHIFT 22
Jasper_lee 0:b16d94660a33 11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11504 #define SDHC_FEVT_AC12E_SHIFT 24
Jasper_lee 0:b16d94660a33 11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 11506 #define SDHC_FEVT_DMAE_SHIFT 28
Jasper_lee 0:b16d94660a33 11507 #define SDHC_FEVT_CINT_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 11508 #define SDHC_FEVT_CINT_SHIFT 31
Jasper_lee 0:b16d94660a33 11509 /* ADMAES Bit Fields */
Jasper_lee 0:b16d94660a33 11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u
Jasper_lee 0:b16d94660a33 11511 #define SDHC_ADMAES_ADMAES_SHIFT 0
Jasper_lee 0:b16d94660a33 11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
Jasper_lee 0:b16d94660a33 11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u
Jasper_lee 0:b16d94660a33 11514 #define SDHC_ADMAES_ADMALME_SHIFT 2
Jasper_lee 0:b16d94660a33 11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
Jasper_lee 0:b16d94660a33 11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3
Jasper_lee 0:b16d94660a33 11517 /* ADSADDR Bit Fields */
Jasper_lee 0:b16d94660a33 11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
Jasper_lee 0:b16d94660a33 11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
Jasper_lee 0:b16d94660a33 11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
Jasper_lee 0:b16d94660a33 11521 /* VENDOR Bit Fields */
Jasper_lee 0:b16d94660a33 11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
Jasper_lee 0:b16d94660a33 11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
Jasper_lee 0:b16d94660a33 11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
Jasper_lee 0:b16d94660a33 11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
Jasper_lee 0:b16d94660a33 11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
Jasper_lee 0:b16d94660a33 11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
Jasper_lee 0:b16d94660a33 11529 /* MMCBOOT Bit Fields */
Jasper_lee 0:b16d94660a33 11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
Jasper_lee 0:b16d94660a33 11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
Jasper_lee 0:b16d94660a33 11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
Jasper_lee 0:b16d94660a33 11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
Jasper_lee 0:b16d94660a33 11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
Jasper_lee 0:b16d94660a33 11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
Jasper_lee 0:b16d94660a33 11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
Jasper_lee 0:b16d94660a33 11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
Jasper_lee 0:b16d94660a33 11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
Jasper_lee 0:b16d94660a33 11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
Jasper_lee 0:b16d94660a33 11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
Jasper_lee 0:b16d94660a33 11544 /* HOSTVER Bit Fields */
Jasper_lee 0:b16d94660a33 11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu
Jasper_lee 0:b16d94660a33 11546 #define SDHC_HOSTVER_SVN_SHIFT 0
Jasper_lee 0:b16d94660a33 11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
Jasper_lee 0:b16d94660a33 11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
Jasper_lee 0:b16d94660a33 11549 #define SDHC_HOSTVER_VVN_SHIFT 8
Jasper_lee 0:b16d94660a33 11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
Jasper_lee 0:b16d94660a33 11551
Jasper_lee 0:b16d94660a33 11552 /*!
Jasper_lee 0:b16d94660a33 11553 * @}
Jasper_lee 0:b16d94660a33 11554 */ /* end of group SDHC_Register_Masks */
Jasper_lee 0:b16d94660a33 11555
Jasper_lee 0:b16d94660a33 11556
Jasper_lee 0:b16d94660a33 11557 /* SDHC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 11558 /** Peripheral SDHC base address */
Jasper_lee 0:b16d94660a33 11559 #define SDHC_BASE (0x400B1000u)
Jasper_lee 0:b16d94660a33 11560 /** Peripheral SDHC base pointer */
Jasper_lee 0:b16d94660a33 11561 #define SDHC ((SDHC_Type *)SDHC_BASE)
Jasper_lee 0:b16d94660a33 11562 #define SDHC_BASE_PTR (SDHC)
Jasper_lee 0:b16d94660a33 11563 /** Array initializer of SDHC peripheral base addresses */
Jasper_lee 0:b16d94660a33 11564 #define SDHC_BASE_ADDRS { SDHC_BASE }
Jasper_lee 0:b16d94660a33 11565 /** Array initializer of SDHC peripheral base pointers */
Jasper_lee 0:b16d94660a33 11566 #define SDHC_BASE_PTRS { SDHC }
Jasper_lee 0:b16d94660a33 11567 /** Interrupt vectors for the SDHC peripheral type */
Jasper_lee 0:b16d94660a33 11568 #define SDHC_IRQS { SDHC_IRQn }
Jasper_lee 0:b16d94660a33 11569
Jasper_lee 0:b16d94660a33 11570 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11571 -- SDHC - Register accessor macros
Jasper_lee 0:b16d94660a33 11572 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11573
Jasper_lee 0:b16d94660a33 11574 /*!
Jasper_lee 0:b16d94660a33 11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
Jasper_lee 0:b16d94660a33 11576 * @{
Jasper_lee 0:b16d94660a33 11577 */
Jasper_lee 0:b16d94660a33 11578
Jasper_lee 0:b16d94660a33 11579
Jasper_lee 0:b16d94660a33 11580 /* SDHC - Register instance definitions */
Jasper_lee 0:b16d94660a33 11581 /* SDHC */
Jasper_lee 0:b16d94660a33 11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
Jasper_lee 0:b16d94660a33 11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
Jasper_lee 0:b16d94660a33 11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
Jasper_lee 0:b16d94660a33 11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
Jasper_lee 0:b16d94660a33 11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
Jasper_lee 0:b16d94660a33 11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
Jasper_lee 0:b16d94660a33 11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
Jasper_lee 0:b16d94660a33 11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
Jasper_lee 0:b16d94660a33 11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
Jasper_lee 0:b16d94660a33 11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
Jasper_lee 0:b16d94660a33 11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
Jasper_lee 0:b16d94660a33 11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
Jasper_lee 0:b16d94660a33 11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
Jasper_lee 0:b16d94660a33 11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11599 #define SDHC_WML SDHC_WML_REG(SDHC)
Jasper_lee 0:b16d94660a33 11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
Jasper_lee 0:b16d94660a33 11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
Jasper_lee 0:b16d94660a33 11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
Jasper_lee 0:b16d94660a33 11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
Jasper_lee 0:b16d94660a33 11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
Jasper_lee 0:b16d94660a33 11606
Jasper_lee 0:b16d94660a33 11607 /* SDHC - Register array accessors */
Jasper_lee 0:b16d94660a33 11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
Jasper_lee 0:b16d94660a33 11609
Jasper_lee 0:b16d94660a33 11610 /*!
Jasper_lee 0:b16d94660a33 11611 * @}
Jasper_lee 0:b16d94660a33 11612 */ /* end of group SDHC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 11613
Jasper_lee 0:b16d94660a33 11614
Jasper_lee 0:b16d94660a33 11615 /*!
Jasper_lee 0:b16d94660a33 11616 * @}
Jasper_lee 0:b16d94660a33 11617 */ /* end of group SDHC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 11618
Jasper_lee 0:b16d94660a33 11619
Jasper_lee 0:b16d94660a33 11620 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11621 -- SIM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 11622 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11623
Jasper_lee 0:b16d94660a33 11624 /*!
Jasper_lee 0:b16d94660a33 11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Jasper_lee 0:b16d94660a33 11626 * @{
Jasper_lee 0:b16d94660a33 11627 */
Jasper_lee 0:b16d94660a33 11628
Jasper_lee 0:b16d94660a33 11629 /** SIM - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 11630 typedef struct {
Jasper_lee 0:b16d94660a33 11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
Jasper_lee 0:b16d94660a33 11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 11633 uint8_t RESERVED_0[4092];
Jasper_lee 0:b16d94660a33 11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
Jasper_lee 0:b16d94660a33 11635 uint8_t RESERVED_1[4];
Jasper_lee 0:b16d94660a33 11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
Jasper_lee 0:b16d94660a33 11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
Jasper_lee 0:b16d94660a33 11638 uint8_t RESERVED_2[4];
Jasper_lee 0:b16d94660a33 11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
Jasper_lee 0:b16d94660a33 11640 uint8_t RESERVED_3[8];
Jasper_lee 0:b16d94660a33 11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
Jasper_lee 0:b16d94660a33 11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
Jasper_lee 0:b16d94660a33 11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
Jasper_lee 0:b16d94660a33 11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
Jasper_lee 0:b16d94660a33 11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
Jasper_lee 0:b16d94660a33 11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
Jasper_lee 0:b16d94660a33 11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
Jasper_lee 0:b16d94660a33 11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
Jasper_lee 0:b16d94660a33 11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
Jasper_lee 0:b16d94660a33 11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
Jasper_lee 0:b16d94660a33 11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
Jasper_lee 0:b16d94660a33 11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
Jasper_lee 0:b16d94660a33 11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
Jasper_lee 0:b16d94660a33 11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
Jasper_lee 0:b16d94660a33 11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
Jasper_lee 0:b16d94660a33 11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
Jasper_lee 0:b16d94660a33 11657 } SIM_Type, *SIM_MemMapPtr;
Jasper_lee 0:b16d94660a33 11658
Jasper_lee 0:b16d94660a33 11659 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11660 -- SIM - Register accessor macros
Jasper_lee 0:b16d94660a33 11661 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11662
Jasper_lee 0:b16d94660a33 11663 /*!
Jasper_lee 0:b16d94660a33 11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Jasper_lee 0:b16d94660a33 11665 * @{
Jasper_lee 0:b16d94660a33 11666 */
Jasper_lee 0:b16d94660a33 11667
Jasper_lee 0:b16d94660a33 11668
Jasper_lee 0:b16d94660a33 11669 /* SIM - Register accessors */
Jasper_lee 0:b16d94660a33 11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
Jasper_lee 0:b16d94660a33 11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
Jasper_lee 0:b16d94660a33 11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
Jasper_lee 0:b16d94660a33 11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
Jasper_lee 0:b16d94660a33 11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
Jasper_lee 0:b16d94660a33 11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
Jasper_lee 0:b16d94660a33 11676 #define SIM_SDID_REG(base) ((base)->SDID)
Jasper_lee 0:b16d94660a33 11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
Jasper_lee 0:b16d94660a33 11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
Jasper_lee 0:b16d94660a33 11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
Jasper_lee 0:b16d94660a33 11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
Jasper_lee 0:b16d94660a33 11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
Jasper_lee 0:b16d94660a33 11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
Jasper_lee 0:b16d94660a33 11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
Jasper_lee 0:b16d94660a33 11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
Jasper_lee 0:b16d94660a33 11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
Jasper_lee 0:b16d94660a33 11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
Jasper_lee 0:b16d94660a33 11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
Jasper_lee 0:b16d94660a33 11688 #define SIM_UIDH_REG(base) ((base)->UIDH)
Jasper_lee 0:b16d94660a33 11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
Jasper_lee 0:b16d94660a33 11690 #define SIM_UIDML_REG(base) ((base)->UIDML)
Jasper_lee 0:b16d94660a33 11691 #define SIM_UIDL_REG(base) ((base)->UIDL)
Jasper_lee 0:b16d94660a33 11692
Jasper_lee 0:b16d94660a33 11693 /*!
Jasper_lee 0:b16d94660a33 11694 * @}
Jasper_lee 0:b16d94660a33 11695 */ /* end of group SIM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 11696
Jasper_lee 0:b16d94660a33 11697
Jasper_lee 0:b16d94660a33 11698 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 11699 -- SIM Register Masks
Jasper_lee 0:b16d94660a33 11700 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 11701
Jasper_lee 0:b16d94660a33 11702 /*!
Jasper_lee 0:b16d94660a33 11703 * @addtogroup SIM_Register_Masks SIM Register Masks
Jasper_lee 0:b16d94660a33 11704 * @{
Jasper_lee 0:b16d94660a33 11705 */
Jasper_lee 0:b16d94660a33 11706
Jasper_lee 0:b16d94660a33 11707 /* SOPT1 Bit Fields */
Jasper_lee 0:b16d94660a33 11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
Jasper_lee 0:b16d94660a33 11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12
Jasper_lee 0:b16d94660a33 11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
Jasper_lee 0:b16d94660a33 11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
Jasper_lee 0:b16d94660a33 11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
Jasper_lee 0:b16d94660a33 11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29
Jasper_lee 0:b16d94660a33 11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30
Jasper_lee 0:b16d94660a33 11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 11719 #define SIM_SOPT1_USBREGEN_SHIFT 31
Jasper_lee 0:b16d94660a33 11720 /* SOPT1CFG Bit Fields */
Jasper_lee 0:b16d94660a33 11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11722 #define SIM_SOPT1CFG_URWE_SHIFT 24
Jasper_lee 0:b16d94660a33 11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
Jasper_lee 0:b16d94660a33 11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26
Jasper_lee 0:b16d94660a33 11727 /* SOPT2 Bit Fields */
Jasper_lee 0:b16d94660a33 11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
Jasper_lee 0:b16d94660a33 11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
Jasper_lee 0:b16d94660a33 11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
Jasper_lee 0:b16d94660a33 11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
Jasper_lee 0:b16d94660a33 11733 #define SIM_SOPT2_FBSL_MASK 0x300u
Jasper_lee 0:b16d94660a33 11734 #define SIM_SOPT2_FBSL_SHIFT 8
Jasper_lee 0:b16d94660a33 11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
Jasper_lee 0:b16d94660a33 11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
Jasper_lee 0:b16d94660a33 11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11
Jasper_lee 0:b16d94660a33 11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
Jasper_lee 0:b16d94660a33 11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
Jasper_lee 0:b16d94660a33 11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
Jasper_lee 0:b16d94660a33 11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
Jasper_lee 0:b16d94660a33 11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11744 #define SIM_SOPT2_USBSRC_SHIFT 18
Jasper_lee 0:b16d94660a33 11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11746 #define SIM_SOPT2_RMIISRC_SHIFT 19
Jasper_lee 0:b16d94660a33 11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
Jasper_lee 0:b16d94660a33 11748 #define SIM_SOPT2_TIMESRC_SHIFT 20
Jasper_lee 0:b16d94660a33 11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
Jasper_lee 0:b16d94660a33 11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
Jasper_lee 0:b16d94660a33 11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28
Jasper_lee 0:b16d94660a33 11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
Jasper_lee 0:b16d94660a33 11753 /* SOPT4 Bit Fields */
Jasper_lee 0:b16d94660a33 11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
Jasper_lee 0:b16d94660a33 11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
Jasper_lee 0:b16d94660a33 11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
Jasper_lee 0:b16d94660a33 11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
Jasper_lee 0:b16d94660a33 11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
Jasper_lee 0:b16d94660a33 11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
Jasper_lee 0:b16d94660a33 11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
Jasper_lee 0:b16d94660a33 11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
Jasper_lee 0:b16d94660a33 11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
Jasper_lee 0:b16d94660a33 11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
Jasper_lee 0:b16d94660a33 11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
Jasper_lee 0:b16d94660a33 11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
Jasper_lee 0:b16d94660a33 11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
Jasper_lee 0:b16d94660a33 11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
Jasper_lee 0:b16d94660a33 11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
Jasper_lee 0:b16d94660a33 11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
Jasper_lee 0:b16d94660a33 11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
Jasper_lee 0:b16d94660a33 11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
Jasper_lee 0:b16d94660a33 11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
Jasper_lee 0:b16d94660a33 11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
Jasper_lee 0:b16d94660a33 11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
Jasper_lee 0:b16d94660a33 11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
Jasper_lee 0:b16d94660a33 11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
Jasper_lee 0:b16d94660a33 11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
Jasper_lee 0:b16d94660a33 11788 /* SOPT5 Bit Fields */
Jasper_lee 0:b16d94660a33 11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
Jasper_lee 0:b16d94660a33 11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
Jasper_lee 0:b16d94660a33 11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
Jasper_lee 0:b16d94660a33 11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
Jasper_lee 0:b16d94660a33 11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
Jasper_lee 0:b16d94660a33 11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
Jasper_lee 0:b16d94660a33 11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
Jasper_lee 0:b16d94660a33 11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
Jasper_lee 0:b16d94660a33 11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
Jasper_lee 0:b16d94660a33 11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
Jasper_lee 0:b16d94660a33 11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
Jasper_lee 0:b16d94660a33 11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
Jasper_lee 0:b16d94660a33 11801 /* SOPT7 Bit Fields */
Jasper_lee 0:b16d94660a33 11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
Jasper_lee 0:b16d94660a33 11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
Jasper_lee 0:b16d94660a33 11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
Jasper_lee 0:b16d94660a33 11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
Jasper_lee 0:b16d94660a33 11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
Jasper_lee 0:b16d94660a33 11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
Jasper_lee 0:b16d94660a33 11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
Jasper_lee 0:b16d94660a33 11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
Jasper_lee 0:b16d94660a33 11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
Jasper_lee 0:b16d94660a33 11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
Jasper_lee 0:b16d94660a33 11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
Jasper_lee 0:b16d94660a33 11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
Jasper_lee 0:b16d94660a33 11816 /* SDID Bit Fields */
Jasper_lee 0:b16d94660a33 11817 #define SIM_SDID_PINID_MASK 0xFu
Jasper_lee 0:b16d94660a33 11818 #define SIM_SDID_PINID_SHIFT 0
Jasper_lee 0:b16d94660a33 11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
Jasper_lee 0:b16d94660a33 11820 #define SIM_SDID_FAMID_MASK 0x70u
Jasper_lee 0:b16d94660a33 11821 #define SIM_SDID_FAMID_SHIFT 4
Jasper_lee 0:b16d94660a33 11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
Jasper_lee 0:b16d94660a33 11823 #define SIM_SDID_DIEID_MASK 0xF80u
Jasper_lee 0:b16d94660a33 11824 #define SIM_SDID_DIEID_SHIFT 7
Jasper_lee 0:b16d94660a33 11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
Jasper_lee 0:b16d94660a33 11826 #define SIM_SDID_REVID_MASK 0xF000u
Jasper_lee 0:b16d94660a33 11827 #define SIM_SDID_REVID_SHIFT 12
Jasper_lee 0:b16d94660a33 11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
Jasper_lee 0:b16d94660a33 11829 #define SIM_SDID_SERIESID_MASK 0xF00000u
Jasper_lee 0:b16d94660a33 11830 #define SIM_SDID_SERIESID_SHIFT 20
Jasper_lee 0:b16d94660a33 11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
Jasper_lee 0:b16d94660a33 11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 11833 #define SIM_SDID_SUBFAMID_SHIFT 24
Jasper_lee 0:b16d94660a33 11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
Jasper_lee 0:b16d94660a33 11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 11836 #define SIM_SDID_FAMILYID_SHIFT 28
Jasper_lee 0:b16d94660a33 11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
Jasper_lee 0:b16d94660a33 11838 /* SCGC1 Bit Fields */
Jasper_lee 0:b16d94660a33 11839 #define SIM_SCGC1_I2C2_MASK 0x40u
Jasper_lee 0:b16d94660a33 11840 #define SIM_SCGC1_I2C2_SHIFT 6
Jasper_lee 0:b16d94660a33 11841 #define SIM_SCGC1_UART4_MASK 0x400u
Jasper_lee 0:b16d94660a33 11842 #define SIM_SCGC1_UART4_SHIFT 10
Jasper_lee 0:b16d94660a33 11843 #define SIM_SCGC1_UART5_MASK 0x800u
Jasper_lee 0:b16d94660a33 11844 #define SIM_SCGC1_UART5_SHIFT 11
Jasper_lee 0:b16d94660a33 11845 /* SCGC2 Bit Fields */
Jasper_lee 0:b16d94660a33 11846 #define SIM_SCGC2_ENET_MASK 0x1u
Jasper_lee 0:b16d94660a33 11847 #define SIM_SCGC2_ENET_SHIFT 0
Jasper_lee 0:b16d94660a33 11848 #define SIM_SCGC2_DAC0_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11849 #define SIM_SCGC2_DAC0_SHIFT 12
Jasper_lee 0:b16d94660a33 11850 #define SIM_SCGC2_DAC1_MASK 0x2000u
Jasper_lee 0:b16d94660a33 11851 #define SIM_SCGC2_DAC1_SHIFT 13
Jasper_lee 0:b16d94660a33 11852 /* SCGC3 Bit Fields */
Jasper_lee 0:b16d94660a33 11853 #define SIM_SCGC3_RNGA_MASK 0x1u
Jasper_lee 0:b16d94660a33 11854 #define SIM_SCGC3_RNGA_SHIFT 0
Jasper_lee 0:b16d94660a33 11855 #define SIM_SCGC3_SPI2_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11856 #define SIM_SCGC3_SPI2_SHIFT 12
Jasper_lee 0:b16d94660a33 11857 #define SIM_SCGC3_SDHC_MASK 0x20000u
Jasper_lee 0:b16d94660a33 11858 #define SIM_SCGC3_SDHC_SHIFT 17
Jasper_lee 0:b16d94660a33 11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11860 #define SIM_SCGC3_FTM2_SHIFT 24
Jasper_lee 0:b16d94660a33 11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11862 #define SIM_SCGC3_FTM3_SHIFT 25
Jasper_lee 0:b16d94660a33 11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 11864 #define SIM_SCGC3_ADC1_SHIFT 27
Jasper_lee 0:b16d94660a33 11865 /* SCGC4 Bit Fields */
Jasper_lee 0:b16d94660a33 11866 #define SIM_SCGC4_EWM_MASK 0x2u
Jasper_lee 0:b16d94660a33 11867 #define SIM_SCGC4_EWM_SHIFT 1
Jasper_lee 0:b16d94660a33 11868 #define SIM_SCGC4_CMT_MASK 0x4u
Jasper_lee 0:b16d94660a33 11869 #define SIM_SCGC4_CMT_SHIFT 2
Jasper_lee 0:b16d94660a33 11870 #define SIM_SCGC4_I2C0_MASK 0x40u
Jasper_lee 0:b16d94660a33 11871 #define SIM_SCGC4_I2C0_SHIFT 6
Jasper_lee 0:b16d94660a33 11872 #define SIM_SCGC4_I2C1_MASK 0x80u
Jasper_lee 0:b16d94660a33 11873 #define SIM_SCGC4_I2C1_SHIFT 7
Jasper_lee 0:b16d94660a33 11874 #define SIM_SCGC4_UART0_MASK 0x400u
Jasper_lee 0:b16d94660a33 11875 #define SIM_SCGC4_UART0_SHIFT 10
Jasper_lee 0:b16d94660a33 11876 #define SIM_SCGC4_UART1_MASK 0x800u
Jasper_lee 0:b16d94660a33 11877 #define SIM_SCGC4_UART1_SHIFT 11
Jasper_lee 0:b16d94660a33 11878 #define SIM_SCGC4_UART2_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11879 #define SIM_SCGC4_UART2_SHIFT 12
Jasper_lee 0:b16d94660a33 11880 #define SIM_SCGC4_UART3_MASK 0x2000u
Jasper_lee 0:b16d94660a33 11881 #define SIM_SCGC4_UART3_SHIFT 13
Jasper_lee 0:b16d94660a33 11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11883 #define SIM_SCGC4_USBOTG_SHIFT 18
Jasper_lee 0:b16d94660a33 11884 #define SIM_SCGC4_CMP_MASK 0x80000u
Jasper_lee 0:b16d94660a33 11885 #define SIM_SCGC4_CMP_SHIFT 19
Jasper_lee 0:b16d94660a33 11886 #define SIM_SCGC4_VREF_MASK 0x100000u
Jasper_lee 0:b16d94660a33 11887 #define SIM_SCGC4_VREF_SHIFT 20
Jasper_lee 0:b16d94660a33 11888 /* SCGC5 Bit Fields */
Jasper_lee 0:b16d94660a33 11889 #define SIM_SCGC5_LPTMR_MASK 0x1u
Jasper_lee 0:b16d94660a33 11890 #define SIM_SCGC5_LPTMR_SHIFT 0
Jasper_lee 0:b16d94660a33 11891 #define SIM_SCGC5_PORTA_MASK 0x200u
Jasper_lee 0:b16d94660a33 11892 #define SIM_SCGC5_PORTA_SHIFT 9
Jasper_lee 0:b16d94660a33 11893 #define SIM_SCGC5_PORTB_MASK 0x400u
Jasper_lee 0:b16d94660a33 11894 #define SIM_SCGC5_PORTB_SHIFT 10
Jasper_lee 0:b16d94660a33 11895 #define SIM_SCGC5_PORTC_MASK 0x800u
Jasper_lee 0:b16d94660a33 11896 #define SIM_SCGC5_PORTC_SHIFT 11
Jasper_lee 0:b16d94660a33 11897 #define SIM_SCGC5_PORTD_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11898 #define SIM_SCGC5_PORTD_SHIFT 12
Jasper_lee 0:b16d94660a33 11899 #define SIM_SCGC5_PORTE_MASK 0x2000u
Jasper_lee 0:b16d94660a33 11900 #define SIM_SCGC5_PORTE_SHIFT 13
Jasper_lee 0:b16d94660a33 11901 /* SCGC6 Bit Fields */
Jasper_lee 0:b16d94660a33 11902 #define SIM_SCGC6_FTF_MASK 0x1u
Jasper_lee 0:b16d94660a33 11903 #define SIM_SCGC6_FTF_SHIFT 0
Jasper_lee 0:b16d94660a33 11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u
Jasper_lee 0:b16d94660a33 11905 #define SIM_SCGC6_DMAMUX_SHIFT 1
Jasper_lee 0:b16d94660a33 11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
Jasper_lee 0:b16d94660a33 11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
Jasper_lee 0:b16d94660a33 11908 #define SIM_SCGC6_RNGA_MASK 0x200u
Jasper_lee 0:b16d94660a33 11909 #define SIM_SCGC6_RNGA_SHIFT 9
Jasper_lee 0:b16d94660a33 11910 #define SIM_SCGC6_SPI0_MASK 0x1000u
Jasper_lee 0:b16d94660a33 11911 #define SIM_SCGC6_SPI0_SHIFT 12
Jasper_lee 0:b16d94660a33 11912 #define SIM_SCGC6_SPI1_MASK 0x2000u
Jasper_lee 0:b16d94660a33 11913 #define SIM_SCGC6_SPI1_SHIFT 13
Jasper_lee 0:b16d94660a33 11914 #define SIM_SCGC6_I2S_MASK 0x8000u
Jasper_lee 0:b16d94660a33 11915 #define SIM_SCGC6_I2S_SHIFT 15
Jasper_lee 0:b16d94660a33 11916 #define SIM_SCGC6_CRC_MASK 0x40000u
Jasper_lee 0:b16d94660a33 11917 #define SIM_SCGC6_CRC_SHIFT 18
Jasper_lee 0:b16d94660a33 11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u
Jasper_lee 0:b16d94660a33 11919 #define SIM_SCGC6_USBDCD_SHIFT 21
Jasper_lee 0:b16d94660a33 11920 #define SIM_SCGC6_PDB_MASK 0x400000u
Jasper_lee 0:b16d94660a33 11921 #define SIM_SCGC6_PDB_SHIFT 22
Jasper_lee 0:b16d94660a33 11922 #define SIM_SCGC6_PIT_MASK 0x800000u
Jasper_lee 0:b16d94660a33 11923 #define SIM_SCGC6_PIT_SHIFT 23
Jasper_lee 0:b16d94660a33 11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 11925 #define SIM_SCGC6_FTM0_SHIFT 24
Jasper_lee 0:b16d94660a33 11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 11927 #define SIM_SCGC6_FTM1_SHIFT 25
Jasper_lee 0:b16d94660a33 11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 11929 #define SIM_SCGC6_FTM2_SHIFT 26
Jasper_lee 0:b16d94660a33 11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 11931 #define SIM_SCGC6_ADC0_SHIFT 27
Jasper_lee 0:b16d94660a33 11932 #define SIM_SCGC6_RTC_MASK 0x20000000u
Jasper_lee 0:b16d94660a33 11933 #define SIM_SCGC6_RTC_SHIFT 29
Jasper_lee 0:b16d94660a33 11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 11935 #define SIM_SCGC6_DAC0_SHIFT 31
Jasper_lee 0:b16d94660a33 11936 /* SCGC7 Bit Fields */
Jasper_lee 0:b16d94660a33 11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
Jasper_lee 0:b16d94660a33 11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0
Jasper_lee 0:b16d94660a33 11939 #define SIM_SCGC7_DMA_MASK 0x2u
Jasper_lee 0:b16d94660a33 11940 #define SIM_SCGC7_DMA_SHIFT 1
Jasper_lee 0:b16d94660a33 11941 #define SIM_SCGC7_MPU_MASK 0x4u
Jasper_lee 0:b16d94660a33 11942 #define SIM_SCGC7_MPU_SHIFT 2
Jasper_lee 0:b16d94660a33 11943 /* CLKDIV1 Bit Fields */
Jasper_lee 0:b16d94660a33 11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
Jasper_lee 0:b16d94660a33 11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
Jasper_lee 0:b16d94660a33 11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
Jasper_lee 0:b16d94660a33 11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
Jasper_lee 0:b16d94660a33 11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
Jasper_lee 0:b16d94660a33 11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
Jasper_lee 0:b16d94660a33 11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
Jasper_lee 0:b16d94660a33 11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
Jasper_lee 0:b16d94660a33 11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
Jasper_lee 0:b16d94660a33 11956 /* CLKDIV2 Bit Fields */
Jasper_lee 0:b16d94660a33 11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
Jasper_lee 0:b16d94660a33 11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
Jasper_lee 0:b16d94660a33 11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
Jasper_lee 0:b16d94660a33 11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1
Jasper_lee 0:b16d94660a33 11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
Jasper_lee 0:b16d94660a33 11962 /* FCFG1 Bit Fields */
Jasper_lee 0:b16d94660a33 11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
Jasper_lee 0:b16d94660a33 11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0
Jasper_lee 0:b16d94660a33 11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
Jasper_lee 0:b16d94660a33 11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
Jasper_lee 0:b16d94660a33 11967 #define SIM_FCFG1_DEPART_MASK 0xF00u
Jasper_lee 0:b16d94660a33 11968 #define SIM_FCFG1_DEPART_SHIFT 8
Jasper_lee 0:b16d94660a33 11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
Jasper_lee 0:b16d94660a33 11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
Jasper_lee 0:b16d94660a33 11971 #define SIM_FCFG1_EESIZE_SHIFT 16
Jasper_lee 0:b16d94660a33 11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
Jasper_lee 0:b16d94660a33 11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
Jasper_lee 0:b16d94660a33 11974 #define SIM_FCFG1_PFSIZE_SHIFT 24
Jasper_lee 0:b16d94660a33 11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
Jasper_lee 0:b16d94660a33 11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
Jasper_lee 0:b16d94660a33 11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28
Jasper_lee 0:b16d94660a33 11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
Jasper_lee 0:b16d94660a33 11979 /* FCFG2 Bit Fields */
Jasper_lee 0:b16d94660a33 11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
Jasper_lee 0:b16d94660a33 11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16
Jasper_lee 0:b16d94660a33 11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
Jasper_lee 0:b16d94660a33 11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u
Jasper_lee 0:b16d94660a33 11984 #define SIM_FCFG2_PFLSH_SHIFT 23
Jasper_lee 0:b16d94660a33 11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
Jasper_lee 0:b16d94660a33 11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24
Jasper_lee 0:b16d94660a33 11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
Jasper_lee 0:b16d94660a33 11988 /* UIDH Bit Fields */
Jasper_lee 0:b16d94660a33 11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11990 #define SIM_UIDH_UID_SHIFT 0
Jasper_lee 0:b16d94660a33 11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
Jasper_lee 0:b16d94660a33 11992 /* UIDMH Bit Fields */
Jasper_lee 0:b16d94660a33 11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11994 #define SIM_UIDMH_UID_SHIFT 0
Jasper_lee 0:b16d94660a33 11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
Jasper_lee 0:b16d94660a33 11996 /* UIDML Bit Fields */
Jasper_lee 0:b16d94660a33 11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 11998 #define SIM_UIDML_UID_SHIFT 0
Jasper_lee 0:b16d94660a33 11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
Jasper_lee 0:b16d94660a33 12000 /* UIDL Bit Fields */
Jasper_lee 0:b16d94660a33 12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12002 #define SIM_UIDL_UID_SHIFT 0
Jasper_lee 0:b16d94660a33 12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
Jasper_lee 0:b16d94660a33 12004
Jasper_lee 0:b16d94660a33 12005 /*!
Jasper_lee 0:b16d94660a33 12006 * @}
Jasper_lee 0:b16d94660a33 12007 */ /* end of group SIM_Register_Masks */
Jasper_lee 0:b16d94660a33 12008
Jasper_lee 0:b16d94660a33 12009
Jasper_lee 0:b16d94660a33 12010 /* SIM - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 12011 /** Peripheral SIM base address */
Jasper_lee 0:b16d94660a33 12012 #define SIM_BASE (0x40047000u)
Jasper_lee 0:b16d94660a33 12013 /** Peripheral SIM base pointer */
Jasper_lee 0:b16d94660a33 12014 #define SIM ((SIM_Type *)SIM_BASE)
Jasper_lee 0:b16d94660a33 12015 #define SIM_BASE_PTR (SIM)
Jasper_lee 0:b16d94660a33 12016 /** Array initializer of SIM peripheral base addresses */
Jasper_lee 0:b16d94660a33 12017 #define SIM_BASE_ADDRS { SIM_BASE }
Jasper_lee 0:b16d94660a33 12018 /** Array initializer of SIM peripheral base pointers */
Jasper_lee 0:b16d94660a33 12019 #define SIM_BASE_PTRS { SIM }
Jasper_lee 0:b16d94660a33 12020
Jasper_lee 0:b16d94660a33 12021 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12022 -- SIM - Register accessor macros
Jasper_lee 0:b16d94660a33 12023 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12024
Jasper_lee 0:b16d94660a33 12025 /*!
Jasper_lee 0:b16d94660a33 12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Jasper_lee 0:b16d94660a33 12027 * @{
Jasper_lee 0:b16d94660a33 12028 */
Jasper_lee 0:b16d94660a33 12029
Jasper_lee 0:b16d94660a33 12030
Jasper_lee 0:b16d94660a33 12031 /* SIM - Register instance definitions */
Jasper_lee 0:b16d94660a33 12032 /* SIM */
Jasper_lee 0:b16d94660a33 12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
Jasper_lee 0:b16d94660a33 12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
Jasper_lee 0:b16d94660a33 12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
Jasper_lee 0:b16d94660a33 12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
Jasper_lee 0:b16d94660a33 12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
Jasper_lee 0:b16d94660a33 12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
Jasper_lee 0:b16d94660a33 12039 #define SIM_SDID SIM_SDID_REG(SIM)
Jasper_lee 0:b16d94660a33 12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
Jasper_lee 0:b16d94660a33 12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
Jasper_lee 0:b16d94660a33 12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
Jasper_lee 0:b16d94660a33 12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
Jasper_lee 0:b16d94660a33 12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
Jasper_lee 0:b16d94660a33 12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
Jasper_lee 0:b16d94660a33 12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
Jasper_lee 0:b16d94660a33 12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
Jasper_lee 0:b16d94660a33 12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
Jasper_lee 0:b16d94660a33 12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
Jasper_lee 0:b16d94660a33 12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
Jasper_lee 0:b16d94660a33 12051 #define SIM_UIDH SIM_UIDH_REG(SIM)
Jasper_lee 0:b16d94660a33 12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
Jasper_lee 0:b16d94660a33 12053 #define SIM_UIDML SIM_UIDML_REG(SIM)
Jasper_lee 0:b16d94660a33 12054 #define SIM_UIDL SIM_UIDL_REG(SIM)
Jasper_lee 0:b16d94660a33 12055
Jasper_lee 0:b16d94660a33 12056 /*!
Jasper_lee 0:b16d94660a33 12057 * @}
Jasper_lee 0:b16d94660a33 12058 */ /* end of group SIM_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12059
Jasper_lee 0:b16d94660a33 12060
Jasper_lee 0:b16d94660a33 12061 /*!
Jasper_lee 0:b16d94660a33 12062 * @}
Jasper_lee 0:b16d94660a33 12063 */ /* end of group SIM_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 12064
Jasper_lee 0:b16d94660a33 12065
Jasper_lee 0:b16d94660a33 12066 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12067 -- SMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12068 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12069
Jasper_lee 0:b16d94660a33 12070 /*!
Jasper_lee 0:b16d94660a33 12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12072 * @{
Jasper_lee 0:b16d94660a33 12073 */
Jasper_lee 0:b16d94660a33 12074
Jasper_lee 0:b16d94660a33 12075 /** SMC - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 12076 typedef struct {
Jasper_lee 0:b16d94660a33 12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
Jasper_lee 0:b16d94660a33 12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
Jasper_lee 0:b16d94660a33 12081 } SMC_Type, *SMC_MemMapPtr;
Jasper_lee 0:b16d94660a33 12082
Jasper_lee 0:b16d94660a33 12083 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12084 -- SMC - Register accessor macros
Jasper_lee 0:b16d94660a33 12085 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12086
Jasper_lee 0:b16d94660a33 12087 /*!
Jasper_lee 0:b16d94660a33 12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Jasper_lee 0:b16d94660a33 12089 * @{
Jasper_lee 0:b16d94660a33 12090 */
Jasper_lee 0:b16d94660a33 12091
Jasper_lee 0:b16d94660a33 12092
Jasper_lee 0:b16d94660a33 12093 /* SMC - Register accessors */
Jasper_lee 0:b16d94660a33 12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
Jasper_lee 0:b16d94660a33 12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
Jasper_lee 0:b16d94660a33 12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
Jasper_lee 0:b16d94660a33 12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
Jasper_lee 0:b16d94660a33 12098
Jasper_lee 0:b16d94660a33 12099 /*!
Jasper_lee 0:b16d94660a33 12100 * @}
Jasper_lee 0:b16d94660a33 12101 */ /* end of group SMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12102
Jasper_lee 0:b16d94660a33 12103
Jasper_lee 0:b16d94660a33 12104 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12105 -- SMC Register Masks
Jasper_lee 0:b16d94660a33 12106 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12107
Jasper_lee 0:b16d94660a33 12108 /*!
Jasper_lee 0:b16d94660a33 12109 * @addtogroup SMC_Register_Masks SMC Register Masks
Jasper_lee 0:b16d94660a33 12110 * @{
Jasper_lee 0:b16d94660a33 12111 */
Jasper_lee 0:b16d94660a33 12112
Jasper_lee 0:b16d94660a33 12113 /* PMPROT Bit Fields */
Jasper_lee 0:b16d94660a33 12114 #define SMC_PMPROT_AVLLS_MASK 0x2u
Jasper_lee 0:b16d94660a33 12115 #define SMC_PMPROT_AVLLS_SHIFT 1
Jasper_lee 0:b16d94660a33 12116 #define SMC_PMPROT_ALLS_MASK 0x8u
Jasper_lee 0:b16d94660a33 12117 #define SMC_PMPROT_ALLS_SHIFT 3
Jasper_lee 0:b16d94660a33 12118 #define SMC_PMPROT_AVLP_MASK 0x20u
Jasper_lee 0:b16d94660a33 12119 #define SMC_PMPROT_AVLP_SHIFT 5
Jasper_lee 0:b16d94660a33 12120 /* PMCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 12121 #define SMC_PMCTRL_STOPM_MASK 0x7u
Jasper_lee 0:b16d94660a33 12122 #define SMC_PMCTRL_STOPM_SHIFT 0
Jasper_lee 0:b16d94660a33 12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
Jasper_lee 0:b16d94660a33 12124 #define SMC_PMCTRL_STOPA_MASK 0x8u
Jasper_lee 0:b16d94660a33 12125 #define SMC_PMCTRL_STOPA_SHIFT 3
Jasper_lee 0:b16d94660a33 12126 #define SMC_PMCTRL_RUNM_MASK 0x60u
Jasper_lee 0:b16d94660a33 12127 #define SMC_PMCTRL_RUNM_SHIFT 5
Jasper_lee 0:b16d94660a33 12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
Jasper_lee 0:b16d94660a33 12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u
Jasper_lee 0:b16d94660a33 12130 #define SMC_PMCTRL_LPWUI_SHIFT 7
Jasper_lee 0:b16d94660a33 12131 /* VLLSCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
Jasper_lee 0:b16d94660a33 12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
Jasper_lee 0:b16d94660a33 12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
Jasper_lee 0:b16d94660a33 12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
Jasper_lee 0:b16d94660a33 12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5
Jasper_lee 0:b16d94660a33 12137 /* PMSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0
Jasper_lee 0:b16d94660a33 12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
Jasper_lee 0:b16d94660a33 12141
Jasper_lee 0:b16d94660a33 12142 /*!
Jasper_lee 0:b16d94660a33 12143 * @}
Jasper_lee 0:b16d94660a33 12144 */ /* end of group SMC_Register_Masks */
Jasper_lee 0:b16d94660a33 12145
Jasper_lee 0:b16d94660a33 12146
Jasper_lee 0:b16d94660a33 12147 /* SMC - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 12148 /** Peripheral SMC base address */
Jasper_lee 0:b16d94660a33 12149 #define SMC_BASE (0x4007E000u)
Jasper_lee 0:b16d94660a33 12150 /** Peripheral SMC base pointer */
Jasper_lee 0:b16d94660a33 12151 #define SMC ((SMC_Type *)SMC_BASE)
Jasper_lee 0:b16d94660a33 12152 #define SMC_BASE_PTR (SMC)
Jasper_lee 0:b16d94660a33 12153 /** Array initializer of SMC peripheral base addresses */
Jasper_lee 0:b16d94660a33 12154 #define SMC_BASE_ADDRS { SMC_BASE }
Jasper_lee 0:b16d94660a33 12155 /** Array initializer of SMC peripheral base pointers */
Jasper_lee 0:b16d94660a33 12156 #define SMC_BASE_PTRS { SMC }
Jasper_lee 0:b16d94660a33 12157
Jasper_lee 0:b16d94660a33 12158 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12159 -- SMC - Register accessor macros
Jasper_lee 0:b16d94660a33 12160 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12161
Jasper_lee 0:b16d94660a33 12162 /*!
Jasper_lee 0:b16d94660a33 12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Jasper_lee 0:b16d94660a33 12164 * @{
Jasper_lee 0:b16d94660a33 12165 */
Jasper_lee 0:b16d94660a33 12166
Jasper_lee 0:b16d94660a33 12167
Jasper_lee 0:b16d94660a33 12168 /* SMC - Register instance definitions */
Jasper_lee 0:b16d94660a33 12169 /* SMC */
Jasper_lee 0:b16d94660a33 12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
Jasper_lee 0:b16d94660a33 12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
Jasper_lee 0:b16d94660a33 12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
Jasper_lee 0:b16d94660a33 12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
Jasper_lee 0:b16d94660a33 12174
Jasper_lee 0:b16d94660a33 12175 /*!
Jasper_lee 0:b16d94660a33 12176 * @}
Jasper_lee 0:b16d94660a33 12177 */ /* end of group SMC_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12178
Jasper_lee 0:b16d94660a33 12179
Jasper_lee 0:b16d94660a33 12180 /*!
Jasper_lee 0:b16d94660a33 12181 * @}
Jasper_lee 0:b16d94660a33 12182 */ /* end of group SMC_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 12183
Jasper_lee 0:b16d94660a33 12184
Jasper_lee 0:b16d94660a33 12185 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12186 -- SPI Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12187 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12188
Jasper_lee 0:b16d94660a33 12189 /*!
Jasper_lee 0:b16d94660a33 12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12191 * @{
Jasper_lee 0:b16d94660a33 12192 */
Jasper_lee 0:b16d94660a33 12193
Jasper_lee 0:b16d94660a33 12194 /** SPI - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 12195 typedef struct {
Jasper_lee 0:b16d94660a33 12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 12197 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 12199 union { /* offset: 0xC */
Jasper_lee 0:b16d94660a33 12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
Jasper_lee 0:b16d94660a33 12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
Jasper_lee 0:b16d94660a33 12202 };
Jasper_lee 0:b16d94660a33 12203 uint8_t RESERVED_1[24];
Jasper_lee 0:b16d94660a33 12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
Jasper_lee 0:b16d94660a33 12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
Jasper_lee 0:b16d94660a33 12206 union { /* offset: 0x34 */
Jasper_lee 0:b16d94660a33 12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
Jasper_lee 0:b16d94660a33 12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
Jasper_lee 0:b16d94660a33 12209 };
Jasper_lee 0:b16d94660a33 12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
Jasper_lee 0:b16d94660a33 12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
Jasper_lee 0:b16d94660a33 12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
Jasper_lee 0:b16d94660a33 12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
Jasper_lee 0:b16d94660a33 12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
Jasper_lee 0:b16d94660a33 12215 uint8_t RESERVED_2[48];
Jasper_lee 0:b16d94660a33 12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
Jasper_lee 0:b16d94660a33 12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
Jasper_lee 0:b16d94660a33 12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
Jasper_lee 0:b16d94660a33 12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
Jasper_lee 0:b16d94660a33 12220 } SPI_Type, *SPI_MemMapPtr;
Jasper_lee 0:b16d94660a33 12221
Jasper_lee 0:b16d94660a33 12222 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12223 -- SPI - Register accessor macros
Jasper_lee 0:b16d94660a33 12224 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12225
Jasper_lee 0:b16d94660a33 12226 /*!
Jasper_lee 0:b16d94660a33 12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Jasper_lee 0:b16d94660a33 12228 * @{
Jasper_lee 0:b16d94660a33 12229 */
Jasper_lee 0:b16d94660a33 12230
Jasper_lee 0:b16d94660a33 12231
Jasper_lee 0:b16d94660a33 12232 /* SPI - Register accessors */
Jasper_lee 0:b16d94660a33 12233 #define SPI_MCR_REG(base) ((base)->MCR)
Jasper_lee 0:b16d94660a33 12234 #define SPI_TCR_REG(base) ((base)->TCR)
Jasper_lee 0:b16d94660a33 12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
Jasper_lee 0:b16d94660a33 12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
Jasper_lee 0:b16d94660a33 12237 #define SPI_SR_REG(base) ((base)->SR)
Jasper_lee 0:b16d94660a33 12238 #define SPI_RSER_REG(base) ((base)->RSER)
Jasper_lee 0:b16d94660a33 12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
Jasper_lee 0:b16d94660a33 12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
Jasper_lee 0:b16d94660a33 12241 #define SPI_POPR_REG(base) ((base)->POPR)
Jasper_lee 0:b16d94660a33 12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
Jasper_lee 0:b16d94660a33 12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
Jasper_lee 0:b16d94660a33 12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
Jasper_lee 0:b16d94660a33 12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
Jasper_lee 0:b16d94660a33 12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
Jasper_lee 0:b16d94660a33 12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
Jasper_lee 0:b16d94660a33 12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
Jasper_lee 0:b16d94660a33 12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
Jasper_lee 0:b16d94660a33 12250
Jasper_lee 0:b16d94660a33 12251 /*!
Jasper_lee 0:b16d94660a33 12252 * @}
Jasper_lee 0:b16d94660a33 12253 */ /* end of group SPI_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12254
Jasper_lee 0:b16d94660a33 12255
Jasper_lee 0:b16d94660a33 12256 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12257 -- SPI Register Masks
Jasper_lee 0:b16d94660a33 12258 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12259
Jasper_lee 0:b16d94660a33 12260 /*!
Jasper_lee 0:b16d94660a33 12261 * @addtogroup SPI_Register_Masks SPI Register Masks
Jasper_lee 0:b16d94660a33 12262 * @{
Jasper_lee 0:b16d94660a33 12263 */
Jasper_lee 0:b16d94660a33 12264
Jasper_lee 0:b16d94660a33 12265 /* MCR Bit Fields */
Jasper_lee 0:b16d94660a33 12266 #define SPI_MCR_HALT_MASK 0x1u
Jasper_lee 0:b16d94660a33 12267 #define SPI_MCR_HALT_SHIFT 0
Jasper_lee 0:b16d94660a33 12268 #define SPI_MCR_SMPL_PT_MASK 0x300u
Jasper_lee 0:b16d94660a33 12269 #define SPI_MCR_SMPL_PT_SHIFT 8
Jasper_lee 0:b16d94660a33 12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
Jasper_lee 0:b16d94660a33 12271 #define SPI_MCR_CLR_RXF_MASK 0x400u
Jasper_lee 0:b16d94660a33 12272 #define SPI_MCR_CLR_RXF_SHIFT 10
Jasper_lee 0:b16d94660a33 12273 #define SPI_MCR_CLR_TXF_MASK 0x800u
Jasper_lee 0:b16d94660a33 12274 #define SPI_MCR_CLR_TXF_SHIFT 11
Jasper_lee 0:b16d94660a33 12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u
Jasper_lee 0:b16d94660a33 12276 #define SPI_MCR_DIS_RXF_SHIFT 12
Jasper_lee 0:b16d94660a33 12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u
Jasper_lee 0:b16d94660a33 12278 #define SPI_MCR_DIS_TXF_SHIFT 13
Jasper_lee 0:b16d94660a33 12279 #define SPI_MCR_MDIS_MASK 0x4000u
Jasper_lee 0:b16d94660a33 12280 #define SPI_MCR_MDIS_SHIFT 14
Jasper_lee 0:b16d94660a33 12281 #define SPI_MCR_DOZE_MASK 0x8000u
Jasper_lee 0:b16d94660a33 12282 #define SPI_MCR_DOZE_SHIFT 15
Jasper_lee 0:b16d94660a33 12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u
Jasper_lee 0:b16d94660a33 12284 #define SPI_MCR_PCSIS_SHIFT 16
Jasper_lee 0:b16d94660a33 12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
Jasper_lee 0:b16d94660a33 12286 #define SPI_MCR_ROOE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 12287 #define SPI_MCR_ROOE_SHIFT 24
Jasper_lee 0:b16d94660a33 12288 #define SPI_MCR_PCSSE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 12289 #define SPI_MCR_PCSSE_SHIFT 25
Jasper_lee 0:b16d94660a33 12290 #define SPI_MCR_MTFE_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 12291 #define SPI_MCR_MTFE_SHIFT 26
Jasper_lee 0:b16d94660a33 12292 #define SPI_MCR_FRZ_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 12293 #define SPI_MCR_FRZ_SHIFT 27
Jasper_lee 0:b16d94660a33 12294 #define SPI_MCR_DCONF_MASK 0x30000000u
Jasper_lee 0:b16d94660a33 12295 #define SPI_MCR_DCONF_SHIFT 28
Jasper_lee 0:b16d94660a33 12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
Jasper_lee 0:b16d94660a33 12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 12298 #define SPI_MCR_CONT_SCKE_SHIFT 30
Jasper_lee 0:b16d94660a33 12299 #define SPI_MCR_MSTR_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 12300 #define SPI_MCR_MSTR_SHIFT 31
Jasper_lee 0:b16d94660a33 12301 /* TCR Bit Fields */
Jasper_lee 0:b16d94660a33 12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 12303 #define SPI_TCR_SPI_TCNT_SHIFT 16
Jasper_lee 0:b16d94660a33 12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
Jasper_lee 0:b16d94660a33 12305 /* CTAR Bit Fields */
Jasper_lee 0:b16d94660a33 12306 #define SPI_CTAR_BR_MASK 0xFu
Jasper_lee 0:b16d94660a33 12307 #define SPI_CTAR_BR_SHIFT 0
Jasper_lee 0:b16d94660a33 12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
Jasper_lee 0:b16d94660a33 12309 #define SPI_CTAR_DT_MASK 0xF0u
Jasper_lee 0:b16d94660a33 12310 #define SPI_CTAR_DT_SHIFT 4
Jasper_lee 0:b16d94660a33 12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
Jasper_lee 0:b16d94660a33 12312 #define SPI_CTAR_ASC_MASK 0xF00u
Jasper_lee 0:b16d94660a33 12313 #define SPI_CTAR_ASC_SHIFT 8
Jasper_lee 0:b16d94660a33 12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
Jasper_lee 0:b16d94660a33 12315 #define SPI_CTAR_CSSCK_MASK 0xF000u
Jasper_lee 0:b16d94660a33 12316 #define SPI_CTAR_CSSCK_SHIFT 12
Jasper_lee 0:b16d94660a33 12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
Jasper_lee 0:b16d94660a33 12318 #define SPI_CTAR_PBR_MASK 0x30000u
Jasper_lee 0:b16d94660a33 12319 #define SPI_CTAR_PBR_SHIFT 16
Jasper_lee 0:b16d94660a33 12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
Jasper_lee 0:b16d94660a33 12321 #define SPI_CTAR_PDT_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 12322 #define SPI_CTAR_PDT_SHIFT 18
Jasper_lee 0:b16d94660a33 12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
Jasper_lee 0:b16d94660a33 12324 #define SPI_CTAR_PASC_MASK 0x300000u
Jasper_lee 0:b16d94660a33 12325 #define SPI_CTAR_PASC_SHIFT 20
Jasper_lee 0:b16d94660a33 12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
Jasper_lee 0:b16d94660a33 12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
Jasper_lee 0:b16d94660a33 12328 #define SPI_CTAR_PCSSCK_SHIFT 22
Jasper_lee 0:b16d94660a33 12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
Jasper_lee 0:b16d94660a33 12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 12331 #define SPI_CTAR_LSBFE_SHIFT 24
Jasper_lee 0:b16d94660a33 12332 #define SPI_CTAR_CPHA_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 12333 #define SPI_CTAR_CPHA_SHIFT 25
Jasper_lee 0:b16d94660a33 12334 #define SPI_CTAR_CPOL_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 12335 #define SPI_CTAR_CPOL_SHIFT 26
Jasper_lee 0:b16d94660a33 12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u
Jasper_lee 0:b16d94660a33 12337 #define SPI_CTAR_FMSZ_SHIFT 27
Jasper_lee 0:b16d94660a33 12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
Jasper_lee 0:b16d94660a33 12339 #define SPI_CTAR_DBR_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 12340 #define SPI_CTAR_DBR_SHIFT 31
Jasper_lee 0:b16d94660a33 12341 /* CTAR_SLAVE Bit Fields */
Jasper_lee 0:b16d94660a33 12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
Jasper_lee 0:b16d94660a33 12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
Jasper_lee 0:b16d94660a33 12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
Jasper_lee 0:b16d94660a33 12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
Jasper_lee 0:b16d94660a33 12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
Jasper_lee 0:b16d94660a33 12349 /* SR Bit Fields */
Jasper_lee 0:b16d94660a33 12350 #define SPI_SR_POPNXTPTR_MASK 0xFu
Jasper_lee 0:b16d94660a33 12351 #define SPI_SR_POPNXTPTR_SHIFT 0
Jasper_lee 0:b16d94660a33 12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
Jasper_lee 0:b16d94660a33 12353 #define SPI_SR_RXCTR_MASK 0xF0u
Jasper_lee 0:b16d94660a33 12354 #define SPI_SR_RXCTR_SHIFT 4
Jasper_lee 0:b16d94660a33 12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
Jasper_lee 0:b16d94660a33 12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u
Jasper_lee 0:b16d94660a33 12357 #define SPI_SR_TXNXTPTR_SHIFT 8
Jasper_lee 0:b16d94660a33 12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
Jasper_lee 0:b16d94660a33 12359 #define SPI_SR_TXCTR_MASK 0xF000u
Jasper_lee 0:b16d94660a33 12360 #define SPI_SR_TXCTR_SHIFT 12
Jasper_lee 0:b16d94660a33 12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
Jasper_lee 0:b16d94660a33 12362 #define SPI_SR_RFDF_MASK 0x20000u
Jasper_lee 0:b16d94660a33 12363 #define SPI_SR_RFDF_SHIFT 17
Jasper_lee 0:b16d94660a33 12364 #define SPI_SR_RFOF_MASK 0x80000u
Jasper_lee 0:b16d94660a33 12365 #define SPI_SR_RFOF_SHIFT 19
Jasper_lee 0:b16d94660a33 12366 #define SPI_SR_TFFF_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 12367 #define SPI_SR_TFFF_SHIFT 25
Jasper_lee 0:b16d94660a33 12368 #define SPI_SR_TFUF_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 12369 #define SPI_SR_TFUF_SHIFT 27
Jasper_lee 0:b16d94660a33 12370 #define SPI_SR_EOQF_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 12371 #define SPI_SR_EOQF_SHIFT 28
Jasper_lee 0:b16d94660a33 12372 #define SPI_SR_TXRXS_MASK 0x40000000u
Jasper_lee 0:b16d94660a33 12373 #define SPI_SR_TXRXS_SHIFT 30
Jasper_lee 0:b16d94660a33 12374 #define SPI_SR_TCF_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 12375 #define SPI_SR_TCF_SHIFT 31
Jasper_lee 0:b16d94660a33 12376 /* RSER Bit Fields */
Jasper_lee 0:b16d94660a33 12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
Jasper_lee 0:b16d94660a33 12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16
Jasper_lee 0:b16d94660a33 12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u
Jasper_lee 0:b16d94660a33 12380 #define SPI_RSER_RFDF_RE_SHIFT 17
Jasper_lee 0:b16d94660a33 12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u
Jasper_lee 0:b16d94660a33 12382 #define SPI_RSER_RFOF_RE_SHIFT 19
Jasper_lee 0:b16d94660a33 12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24
Jasper_lee 0:b16d94660a33 12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 12386 #define SPI_RSER_TFFF_RE_SHIFT 25
Jasper_lee 0:b16d94660a33 12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 12388 #define SPI_RSER_TFUF_RE_SHIFT 27
Jasper_lee 0:b16d94660a33 12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
Jasper_lee 0:b16d94660a33 12390 #define SPI_RSER_EOQF_RE_SHIFT 28
Jasper_lee 0:b16d94660a33 12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 12392 #define SPI_RSER_TCF_RE_SHIFT 31
Jasper_lee 0:b16d94660a33 12393 /* PUSHR Bit Fields */
Jasper_lee 0:b16d94660a33 12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 12395 #define SPI_PUSHR_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u
Jasper_lee 0:b16d94660a33 12398 #define SPI_PUSHR_PCS_SHIFT 16
Jasper_lee 0:b16d94660a33 12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
Jasper_lee 0:b16d94660a33 12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
Jasper_lee 0:b16d94660a33 12401 #define SPI_PUSHR_CTCNT_SHIFT 26
Jasper_lee 0:b16d94660a33 12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u
Jasper_lee 0:b16d94660a33 12403 #define SPI_PUSHR_EOQ_SHIFT 27
Jasper_lee 0:b16d94660a33 12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u
Jasper_lee 0:b16d94660a33 12405 #define SPI_PUSHR_CTAS_SHIFT 28
Jasper_lee 0:b16d94660a33 12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
Jasper_lee 0:b16d94660a33 12407 #define SPI_PUSHR_CONT_MASK 0x80000000u
Jasper_lee 0:b16d94660a33 12408 #define SPI_PUSHR_CONT_SHIFT 31
Jasper_lee 0:b16d94660a33 12409 /* PUSHR_SLAVE Bit Fields */
Jasper_lee 0:b16d94660a33 12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12413 /* POPR Bit Fields */
Jasper_lee 0:b16d94660a33 12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12415 #define SPI_POPR_RXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
Jasper_lee 0:b16d94660a33 12417 /* TXFR0 Bit Fields */
Jasper_lee 0:b16d94660a33 12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 12419 #define SPI_TXFR0_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
Jasper_lee 0:b16d94660a33 12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12424 /* TXFR1 Bit Fields */
Jasper_lee 0:b16d94660a33 12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 12426 #define SPI_TXFR1_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
Jasper_lee 0:b16d94660a33 12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12431 /* TXFR2 Bit Fields */
Jasper_lee 0:b16d94660a33 12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 12433 #define SPI_TXFR2_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
Jasper_lee 0:b16d94660a33 12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12438 /* TXFR3 Bit Fields */
Jasper_lee 0:b16d94660a33 12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 12440 #define SPI_TXFR3_TXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
Jasper_lee 0:b16d94660a33 12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
Jasper_lee 0:b16d94660a33 12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
Jasper_lee 0:b16d94660a33 12445 /* RXFR0 Bit Fields */
Jasper_lee 0:b16d94660a33 12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12447 #define SPI_RXFR0_RXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
Jasper_lee 0:b16d94660a33 12449 /* RXFR1 Bit Fields */
Jasper_lee 0:b16d94660a33 12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12451 #define SPI_RXFR1_RXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
Jasper_lee 0:b16d94660a33 12453 /* RXFR2 Bit Fields */
Jasper_lee 0:b16d94660a33 12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12455 #define SPI_RXFR2_RXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
Jasper_lee 0:b16d94660a33 12457 /* RXFR3 Bit Fields */
Jasper_lee 0:b16d94660a33 12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
Jasper_lee 0:b16d94660a33 12459 #define SPI_RXFR3_RXDATA_SHIFT 0
Jasper_lee 0:b16d94660a33 12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
Jasper_lee 0:b16d94660a33 12461
Jasper_lee 0:b16d94660a33 12462 /*!
Jasper_lee 0:b16d94660a33 12463 * @}
Jasper_lee 0:b16d94660a33 12464 */ /* end of group SPI_Register_Masks */
Jasper_lee 0:b16d94660a33 12465
Jasper_lee 0:b16d94660a33 12466
Jasper_lee 0:b16d94660a33 12467 /* SPI - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 12468 /** Peripheral SPI0 base address */
Jasper_lee 0:b16d94660a33 12469 #define SPI0_BASE (0x4002C000u)
Jasper_lee 0:b16d94660a33 12470 /** Peripheral SPI0 base pointer */
Jasper_lee 0:b16d94660a33 12471 #define SPI0 ((SPI_Type *)SPI0_BASE)
Jasper_lee 0:b16d94660a33 12472 #define SPI0_BASE_PTR (SPI0)
Jasper_lee 0:b16d94660a33 12473 /** Peripheral SPI1 base address */
Jasper_lee 0:b16d94660a33 12474 #define SPI1_BASE (0x4002D000u)
Jasper_lee 0:b16d94660a33 12475 /** Peripheral SPI1 base pointer */
Jasper_lee 0:b16d94660a33 12476 #define SPI1 ((SPI_Type *)SPI1_BASE)
Jasper_lee 0:b16d94660a33 12477 #define SPI1_BASE_PTR (SPI1)
Jasper_lee 0:b16d94660a33 12478 /** Peripheral SPI2 base address */
Jasper_lee 0:b16d94660a33 12479 #define SPI2_BASE (0x400AC000u)
Jasper_lee 0:b16d94660a33 12480 /** Peripheral SPI2 base pointer */
Jasper_lee 0:b16d94660a33 12481 #define SPI2 ((SPI_Type *)SPI2_BASE)
Jasper_lee 0:b16d94660a33 12482 #define SPI2_BASE_PTR (SPI2)
Jasper_lee 0:b16d94660a33 12483 /** Array initializer of SPI peripheral base addresses */
Jasper_lee 0:b16d94660a33 12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
Jasper_lee 0:b16d94660a33 12485 /** Array initializer of SPI peripheral base pointers */
Jasper_lee 0:b16d94660a33 12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
Jasper_lee 0:b16d94660a33 12487 /** Interrupt vectors for the SPI peripheral type */
Jasper_lee 0:b16d94660a33 12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
Jasper_lee 0:b16d94660a33 12489
Jasper_lee 0:b16d94660a33 12490 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12491 -- SPI - Register accessor macros
Jasper_lee 0:b16d94660a33 12492 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12493
Jasper_lee 0:b16d94660a33 12494 /*!
Jasper_lee 0:b16d94660a33 12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Jasper_lee 0:b16d94660a33 12496 * @{
Jasper_lee 0:b16d94660a33 12497 */
Jasper_lee 0:b16d94660a33 12498
Jasper_lee 0:b16d94660a33 12499
Jasper_lee 0:b16d94660a33 12500 /* SPI - Register instance definitions */
Jasper_lee 0:b16d94660a33 12501 /* SPI0 */
Jasper_lee 0:b16d94660a33 12502 #define SPI0_MCR SPI_MCR_REG(SPI0)
Jasper_lee 0:b16d94660a33 12503 #define SPI0_TCR SPI_TCR_REG(SPI0)
Jasper_lee 0:b16d94660a33 12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
Jasper_lee 0:b16d94660a33 12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
Jasper_lee 0:b16d94660a33 12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
Jasper_lee 0:b16d94660a33 12507 #define SPI0_SR SPI_SR_REG(SPI0)
Jasper_lee 0:b16d94660a33 12508 #define SPI0_RSER SPI_RSER_REG(SPI0)
Jasper_lee 0:b16d94660a33 12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
Jasper_lee 0:b16d94660a33 12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
Jasper_lee 0:b16d94660a33 12511 #define SPI0_POPR SPI_POPR_REG(SPI0)
Jasper_lee 0:b16d94660a33 12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
Jasper_lee 0:b16d94660a33 12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
Jasper_lee 0:b16d94660a33 12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
Jasper_lee 0:b16d94660a33 12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
Jasper_lee 0:b16d94660a33 12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
Jasper_lee 0:b16d94660a33 12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
Jasper_lee 0:b16d94660a33 12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
Jasper_lee 0:b16d94660a33 12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
Jasper_lee 0:b16d94660a33 12520 /* SPI1 */
Jasper_lee 0:b16d94660a33 12521 #define SPI1_MCR SPI_MCR_REG(SPI1)
Jasper_lee 0:b16d94660a33 12522 #define SPI1_TCR SPI_TCR_REG(SPI1)
Jasper_lee 0:b16d94660a33 12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
Jasper_lee 0:b16d94660a33 12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
Jasper_lee 0:b16d94660a33 12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
Jasper_lee 0:b16d94660a33 12526 #define SPI1_SR SPI_SR_REG(SPI1)
Jasper_lee 0:b16d94660a33 12527 #define SPI1_RSER SPI_RSER_REG(SPI1)
Jasper_lee 0:b16d94660a33 12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
Jasper_lee 0:b16d94660a33 12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
Jasper_lee 0:b16d94660a33 12530 #define SPI1_POPR SPI_POPR_REG(SPI1)
Jasper_lee 0:b16d94660a33 12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
Jasper_lee 0:b16d94660a33 12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
Jasper_lee 0:b16d94660a33 12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
Jasper_lee 0:b16d94660a33 12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
Jasper_lee 0:b16d94660a33 12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
Jasper_lee 0:b16d94660a33 12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
Jasper_lee 0:b16d94660a33 12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
Jasper_lee 0:b16d94660a33 12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
Jasper_lee 0:b16d94660a33 12539 /* SPI2 */
Jasper_lee 0:b16d94660a33 12540 #define SPI2_MCR SPI_MCR_REG(SPI2)
Jasper_lee 0:b16d94660a33 12541 #define SPI2_TCR SPI_TCR_REG(SPI2)
Jasper_lee 0:b16d94660a33 12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
Jasper_lee 0:b16d94660a33 12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
Jasper_lee 0:b16d94660a33 12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
Jasper_lee 0:b16d94660a33 12545 #define SPI2_SR SPI_SR_REG(SPI2)
Jasper_lee 0:b16d94660a33 12546 #define SPI2_RSER SPI_RSER_REG(SPI2)
Jasper_lee 0:b16d94660a33 12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
Jasper_lee 0:b16d94660a33 12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
Jasper_lee 0:b16d94660a33 12549 #define SPI2_POPR SPI_POPR_REG(SPI2)
Jasper_lee 0:b16d94660a33 12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
Jasper_lee 0:b16d94660a33 12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
Jasper_lee 0:b16d94660a33 12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
Jasper_lee 0:b16d94660a33 12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
Jasper_lee 0:b16d94660a33 12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
Jasper_lee 0:b16d94660a33 12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
Jasper_lee 0:b16d94660a33 12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
Jasper_lee 0:b16d94660a33 12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
Jasper_lee 0:b16d94660a33 12558
Jasper_lee 0:b16d94660a33 12559 /* SPI - Register array accessors */
Jasper_lee 0:b16d94660a33 12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
Jasper_lee 0:b16d94660a33 12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
Jasper_lee 0:b16d94660a33 12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
Jasper_lee 0:b16d94660a33 12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
Jasper_lee 0:b16d94660a33 12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
Jasper_lee 0:b16d94660a33 12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
Jasper_lee 0:b16d94660a33 12566
Jasper_lee 0:b16d94660a33 12567 /*!
Jasper_lee 0:b16d94660a33 12568 * @}
Jasper_lee 0:b16d94660a33 12569 */ /* end of group SPI_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12570
Jasper_lee 0:b16d94660a33 12571
Jasper_lee 0:b16d94660a33 12572 /*!
Jasper_lee 0:b16d94660a33 12573 * @}
Jasper_lee 0:b16d94660a33 12574 */ /* end of group SPI_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 12575
Jasper_lee 0:b16d94660a33 12576
Jasper_lee 0:b16d94660a33 12577 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12578 -- UART Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12579 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12580
Jasper_lee 0:b16d94660a33 12581 /*!
Jasper_lee 0:b16d94660a33 12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Jasper_lee 0:b16d94660a33 12583 * @{
Jasper_lee 0:b16d94660a33 12584 */
Jasper_lee 0:b16d94660a33 12585
Jasper_lee 0:b16d94660a33 12586 /** UART - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 12587 typedef struct {
Jasper_lee 0:b16d94660a33 12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
Jasper_lee 0:b16d94660a33 12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
Jasper_lee 0:b16d94660a33 12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
Jasper_lee 0:b16d94660a33 12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
Jasper_lee 0:b16d94660a33 12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
Jasper_lee 0:b16d94660a33 12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
Jasper_lee 0:b16d94660a33 12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
Jasper_lee 0:b16d94660a33 12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
Jasper_lee 0:b16d94660a33 12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
Jasper_lee 0:b16d94660a33 12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
Jasper_lee 0:b16d94660a33 12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
Jasper_lee 0:b16d94660a33 12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
Jasper_lee 0:b16d94660a33 12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
Jasper_lee 0:b16d94660a33 12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
Jasper_lee 0:b16d94660a33 12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
Jasper_lee 0:b16d94660a33 12603 uint8_t RESERVED_0[1];
Jasper_lee 0:b16d94660a33 12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
Jasper_lee 0:b16d94660a33 12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
Jasper_lee 0:b16d94660a33 12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
Jasper_lee 0:b16d94660a33 12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
Jasper_lee 0:b16d94660a33 12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
Jasper_lee 0:b16d94660a33 12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
Jasper_lee 0:b16d94660a33 12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
Jasper_lee 0:b16d94660a33 12611 uint8_t RESERVED_1[1];
Jasper_lee 0:b16d94660a33 12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
Jasper_lee 0:b16d94660a33 12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
Jasper_lee 0:b16d94660a33 12615 union { /* offset: 0x1B */
Jasper_lee 0:b16d94660a33 12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
Jasper_lee 0:b16d94660a33 12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
Jasper_lee 0:b16d94660a33 12618 };
Jasper_lee 0:b16d94660a33 12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
Jasper_lee 0:b16d94660a33 12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
Jasper_lee 0:b16d94660a33 12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
Jasper_lee 0:b16d94660a33 12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
Jasper_lee 0:b16d94660a33 12623 } UART_Type, *UART_MemMapPtr;
Jasper_lee 0:b16d94660a33 12624
Jasper_lee 0:b16d94660a33 12625 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12626 -- UART - Register accessor macros
Jasper_lee 0:b16d94660a33 12627 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12628
Jasper_lee 0:b16d94660a33 12629 /*!
Jasper_lee 0:b16d94660a33 12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Jasper_lee 0:b16d94660a33 12631 * @{
Jasper_lee 0:b16d94660a33 12632 */
Jasper_lee 0:b16d94660a33 12633
Jasper_lee 0:b16d94660a33 12634
Jasper_lee 0:b16d94660a33 12635 /* UART - Register accessors */
Jasper_lee 0:b16d94660a33 12636 #define UART_BDH_REG(base) ((base)->BDH)
Jasper_lee 0:b16d94660a33 12637 #define UART_BDL_REG(base) ((base)->BDL)
Jasper_lee 0:b16d94660a33 12638 #define UART_C1_REG(base) ((base)->C1)
Jasper_lee 0:b16d94660a33 12639 #define UART_C2_REG(base) ((base)->C2)
Jasper_lee 0:b16d94660a33 12640 #define UART_S1_REG(base) ((base)->S1)
Jasper_lee 0:b16d94660a33 12641 #define UART_S2_REG(base) ((base)->S2)
Jasper_lee 0:b16d94660a33 12642 #define UART_C3_REG(base) ((base)->C3)
Jasper_lee 0:b16d94660a33 12643 #define UART_D_REG(base) ((base)->D)
Jasper_lee 0:b16d94660a33 12644 #define UART_MA1_REG(base) ((base)->MA1)
Jasper_lee 0:b16d94660a33 12645 #define UART_MA2_REG(base) ((base)->MA2)
Jasper_lee 0:b16d94660a33 12646 #define UART_C4_REG(base) ((base)->C4)
Jasper_lee 0:b16d94660a33 12647 #define UART_C5_REG(base) ((base)->C5)
Jasper_lee 0:b16d94660a33 12648 #define UART_ED_REG(base) ((base)->ED)
Jasper_lee 0:b16d94660a33 12649 #define UART_MODEM_REG(base) ((base)->MODEM)
Jasper_lee 0:b16d94660a33 12650 #define UART_IR_REG(base) ((base)->IR)
Jasper_lee 0:b16d94660a33 12651 #define UART_PFIFO_REG(base) ((base)->PFIFO)
Jasper_lee 0:b16d94660a33 12652 #define UART_CFIFO_REG(base) ((base)->CFIFO)
Jasper_lee 0:b16d94660a33 12653 #define UART_SFIFO_REG(base) ((base)->SFIFO)
Jasper_lee 0:b16d94660a33 12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
Jasper_lee 0:b16d94660a33 12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
Jasper_lee 0:b16d94660a33 12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
Jasper_lee 0:b16d94660a33 12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
Jasper_lee 0:b16d94660a33 12658 #define UART_C7816_REG(base) ((base)->C7816)
Jasper_lee 0:b16d94660a33 12659 #define UART_IE7816_REG(base) ((base)->IE7816)
Jasper_lee 0:b16d94660a33 12660 #define UART_IS7816_REG(base) ((base)->IS7816)
Jasper_lee 0:b16d94660a33 12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0)
Jasper_lee 0:b16d94660a33 12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1)
Jasper_lee 0:b16d94660a33 12663 #define UART_WN7816_REG(base) ((base)->WN7816)
Jasper_lee 0:b16d94660a33 12664 #define UART_WF7816_REG(base) ((base)->WF7816)
Jasper_lee 0:b16d94660a33 12665 #define UART_ET7816_REG(base) ((base)->ET7816)
Jasper_lee 0:b16d94660a33 12666 #define UART_TL7816_REG(base) ((base)->TL7816)
Jasper_lee 0:b16d94660a33 12667
Jasper_lee 0:b16d94660a33 12668 /*!
Jasper_lee 0:b16d94660a33 12669 * @}
Jasper_lee 0:b16d94660a33 12670 */ /* end of group UART_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 12671
Jasper_lee 0:b16d94660a33 12672
Jasper_lee 0:b16d94660a33 12673 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 12674 -- UART Register Masks
Jasper_lee 0:b16d94660a33 12675 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 12676
Jasper_lee 0:b16d94660a33 12677 /*!
Jasper_lee 0:b16d94660a33 12678 * @addtogroup UART_Register_Masks UART Register Masks
Jasper_lee 0:b16d94660a33 12679 * @{
Jasper_lee 0:b16d94660a33 12680 */
Jasper_lee 0:b16d94660a33 12681
Jasper_lee 0:b16d94660a33 12682 /* BDH Bit Fields */
Jasper_lee 0:b16d94660a33 12683 #define UART_BDH_SBR_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 12684 #define UART_BDH_SBR_SHIFT 0
Jasper_lee 0:b16d94660a33 12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
Jasper_lee 0:b16d94660a33 12686 #define UART_BDH_SBNS_MASK 0x20u
Jasper_lee 0:b16d94660a33 12687 #define UART_BDH_SBNS_SHIFT 5
Jasper_lee 0:b16d94660a33 12688 #define UART_BDH_RXEDGIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 12689 #define UART_BDH_RXEDGIE_SHIFT 6
Jasper_lee 0:b16d94660a33 12690 #define UART_BDH_LBKDIE_MASK 0x80u
Jasper_lee 0:b16d94660a33 12691 #define UART_BDH_LBKDIE_SHIFT 7
Jasper_lee 0:b16d94660a33 12692 /* BDL Bit Fields */
Jasper_lee 0:b16d94660a33 12693 #define UART_BDL_SBR_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12694 #define UART_BDL_SBR_SHIFT 0
Jasper_lee 0:b16d94660a33 12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
Jasper_lee 0:b16d94660a33 12696 /* C1 Bit Fields */
Jasper_lee 0:b16d94660a33 12697 #define UART_C1_PT_MASK 0x1u
Jasper_lee 0:b16d94660a33 12698 #define UART_C1_PT_SHIFT 0
Jasper_lee 0:b16d94660a33 12699 #define UART_C1_PE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12700 #define UART_C1_PE_SHIFT 1
Jasper_lee 0:b16d94660a33 12701 #define UART_C1_ILT_MASK 0x4u
Jasper_lee 0:b16d94660a33 12702 #define UART_C1_ILT_SHIFT 2
Jasper_lee 0:b16d94660a33 12703 #define UART_C1_WAKE_MASK 0x8u
Jasper_lee 0:b16d94660a33 12704 #define UART_C1_WAKE_SHIFT 3
Jasper_lee 0:b16d94660a33 12705 #define UART_C1_M_MASK 0x10u
Jasper_lee 0:b16d94660a33 12706 #define UART_C1_M_SHIFT 4
Jasper_lee 0:b16d94660a33 12707 #define UART_C1_RSRC_MASK 0x20u
Jasper_lee 0:b16d94660a33 12708 #define UART_C1_RSRC_SHIFT 5
Jasper_lee 0:b16d94660a33 12709 #define UART_C1_UARTSWAI_MASK 0x40u
Jasper_lee 0:b16d94660a33 12710 #define UART_C1_UARTSWAI_SHIFT 6
Jasper_lee 0:b16d94660a33 12711 #define UART_C1_LOOPS_MASK 0x80u
Jasper_lee 0:b16d94660a33 12712 #define UART_C1_LOOPS_SHIFT 7
Jasper_lee 0:b16d94660a33 12713 /* C2 Bit Fields */
Jasper_lee 0:b16d94660a33 12714 #define UART_C2_SBK_MASK 0x1u
Jasper_lee 0:b16d94660a33 12715 #define UART_C2_SBK_SHIFT 0
Jasper_lee 0:b16d94660a33 12716 #define UART_C2_RWU_MASK 0x2u
Jasper_lee 0:b16d94660a33 12717 #define UART_C2_RWU_SHIFT 1
Jasper_lee 0:b16d94660a33 12718 #define UART_C2_RE_MASK 0x4u
Jasper_lee 0:b16d94660a33 12719 #define UART_C2_RE_SHIFT 2
Jasper_lee 0:b16d94660a33 12720 #define UART_C2_TE_MASK 0x8u
Jasper_lee 0:b16d94660a33 12721 #define UART_C2_TE_SHIFT 3
Jasper_lee 0:b16d94660a33 12722 #define UART_C2_ILIE_MASK 0x10u
Jasper_lee 0:b16d94660a33 12723 #define UART_C2_ILIE_SHIFT 4
Jasper_lee 0:b16d94660a33 12724 #define UART_C2_RIE_MASK 0x20u
Jasper_lee 0:b16d94660a33 12725 #define UART_C2_RIE_SHIFT 5
Jasper_lee 0:b16d94660a33 12726 #define UART_C2_TCIE_MASK 0x40u
Jasper_lee 0:b16d94660a33 12727 #define UART_C2_TCIE_SHIFT 6
Jasper_lee 0:b16d94660a33 12728 #define UART_C2_TIE_MASK 0x80u
Jasper_lee 0:b16d94660a33 12729 #define UART_C2_TIE_SHIFT 7
Jasper_lee 0:b16d94660a33 12730 /* S1 Bit Fields */
Jasper_lee 0:b16d94660a33 12731 #define UART_S1_PF_MASK 0x1u
Jasper_lee 0:b16d94660a33 12732 #define UART_S1_PF_SHIFT 0
Jasper_lee 0:b16d94660a33 12733 #define UART_S1_FE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12734 #define UART_S1_FE_SHIFT 1
Jasper_lee 0:b16d94660a33 12735 #define UART_S1_NF_MASK 0x4u
Jasper_lee 0:b16d94660a33 12736 #define UART_S1_NF_SHIFT 2
Jasper_lee 0:b16d94660a33 12737 #define UART_S1_OR_MASK 0x8u
Jasper_lee 0:b16d94660a33 12738 #define UART_S1_OR_SHIFT 3
Jasper_lee 0:b16d94660a33 12739 #define UART_S1_IDLE_MASK 0x10u
Jasper_lee 0:b16d94660a33 12740 #define UART_S1_IDLE_SHIFT 4
Jasper_lee 0:b16d94660a33 12741 #define UART_S1_RDRF_MASK 0x20u
Jasper_lee 0:b16d94660a33 12742 #define UART_S1_RDRF_SHIFT 5
Jasper_lee 0:b16d94660a33 12743 #define UART_S1_TC_MASK 0x40u
Jasper_lee 0:b16d94660a33 12744 #define UART_S1_TC_SHIFT 6
Jasper_lee 0:b16d94660a33 12745 #define UART_S1_TDRE_MASK 0x80u
Jasper_lee 0:b16d94660a33 12746 #define UART_S1_TDRE_SHIFT 7
Jasper_lee 0:b16d94660a33 12747 /* S2 Bit Fields */
Jasper_lee 0:b16d94660a33 12748 #define UART_S2_RAF_MASK 0x1u
Jasper_lee 0:b16d94660a33 12749 #define UART_S2_RAF_SHIFT 0
Jasper_lee 0:b16d94660a33 12750 #define UART_S2_LBKDE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12751 #define UART_S2_LBKDE_SHIFT 1
Jasper_lee 0:b16d94660a33 12752 #define UART_S2_BRK13_MASK 0x4u
Jasper_lee 0:b16d94660a33 12753 #define UART_S2_BRK13_SHIFT 2
Jasper_lee 0:b16d94660a33 12754 #define UART_S2_RWUID_MASK 0x8u
Jasper_lee 0:b16d94660a33 12755 #define UART_S2_RWUID_SHIFT 3
Jasper_lee 0:b16d94660a33 12756 #define UART_S2_RXINV_MASK 0x10u
Jasper_lee 0:b16d94660a33 12757 #define UART_S2_RXINV_SHIFT 4
Jasper_lee 0:b16d94660a33 12758 #define UART_S2_MSBF_MASK 0x20u
Jasper_lee 0:b16d94660a33 12759 #define UART_S2_MSBF_SHIFT 5
Jasper_lee 0:b16d94660a33 12760 #define UART_S2_RXEDGIF_MASK 0x40u
Jasper_lee 0:b16d94660a33 12761 #define UART_S2_RXEDGIF_SHIFT 6
Jasper_lee 0:b16d94660a33 12762 #define UART_S2_LBKDIF_MASK 0x80u
Jasper_lee 0:b16d94660a33 12763 #define UART_S2_LBKDIF_SHIFT 7
Jasper_lee 0:b16d94660a33 12764 /* C3 Bit Fields */
Jasper_lee 0:b16d94660a33 12765 #define UART_C3_PEIE_MASK 0x1u
Jasper_lee 0:b16d94660a33 12766 #define UART_C3_PEIE_SHIFT 0
Jasper_lee 0:b16d94660a33 12767 #define UART_C3_FEIE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12768 #define UART_C3_FEIE_SHIFT 1
Jasper_lee 0:b16d94660a33 12769 #define UART_C3_NEIE_MASK 0x4u
Jasper_lee 0:b16d94660a33 12770 #define UART_C3_NEIE_SHIFT 2
Jasper_lee 0:b16d94660a33 12771 #define UART_C3_ORIE_MASK 0x8u
Jasper_lee 0:b16d94660a33 12772 #define UART_C3_ORIE_SHIFT 3
Jasper_lee 0:b16d94660a33 12773 #define UART_C3_TXINV_MASK 0x10u
Jasper_lee 0:b16d94660a33 12774 #define UART_C3_TXINV_SHIFT 4
Jasper_lee 0:b16d94660a33 12775 #define UART_C3_TXDIR_MASK 0x20u
Jasper_lee 0:b16d94660a33 12776 #define UART_C3_TXDIR_SHIFT 5
Jasper_lee 0:b16d94660a33 12777 #define UART_C3_T8_MASK 0x40u
Jasper_lee 0:b16d94660a33 12778 #define UART_C3_T8_SHIFT 6
Jasper_lee 0:b16d94660a33 12779 #define UART_C3_R8_MASK 0x80u
Jasper_lee 0:b16d94660a33 12780 #define UART_C3_R8_SHIFT 7
Jasper_lee 0:b16d94660a33 12781 /* D Bit Fields */
Jasper_lee 0:b16d94660a33 12782 #define UART_D_RT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12783 #define UART_D_RT_SHIFT 0
Jasper_lee 0:b16d94660a33 12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
Jasper_lee 0:b16d94660a33 12785 /* MA1 Bit Fields */
Jasper_lee 0:b16d94660a33 12786 #define UART_MA1_MA_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12787 #define UART_MA1_MA_SHIFT 0
Jasper_lee 0:b16d94660a33 12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
Jasper_lee 0:b16d94660a33 12789 /* MA2 Bit Fields */
Jasper_lee 0:b16d94660a33 12790 #define UART_MA2_MA_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12791 #define UART_MA2_MA_SHIFT 0
Jasper_lee 0:b16d94660a33 12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
Jasper_lee 0:b16d94660a33 12793 /* C4 Bit Fields */
Jasper_lee 0:b16d94660a33 12794 #define UART_C4_BRFA_MASK 0x1Fu
Jasper_lee 0:b16d94660a33 12795 #define UART_C4_BRFA_SHIFT 0
Jasper_lee 0:b16d94660a33 12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
Jasper_lee 0:b16d94660a33 12797 #define UART_C4_M10_MASK 0x20u
Jasper_lee 0:b16d94660a33 12798 #define UART_C4_M10_SHIFT 5
Jasper_lee 0:b16d94660a33 12799 #define UART_C4_MAEN2_MASK 0x40u
Jasper_lee 0:b16d94660a33 12800 #define UART_C4_MAEN2_SHIFT 6
Jasper_lee 0:b16d94660a33 12801 #define UART_C4_MAEN1_MASK 0x80u
Jasper_lee 0:b16d94660a33 12802 #define UART_C4_MAEN1_SHIFT 7
Jasper_lee 0:b16d94660a33 12803 /* C5 Bit Fields */
Jasper_lee 0:b16d94660a33 12804 #define UART_C5_LBKDDMAS_MASK 0x8u
Jasper_lee 0:b16d94660a33 12805 #define UART_C5_LBKDDMAS_SHIFT 3
Jasper_lee 0:b16d94660a33 12806 #define UART_C5_ILDMAS_MASK 0x10u
Jasper_lee 0:b16d94660a33 12807 #define UART_C5_ILDMAS_SHIFT 4
Jasper_lee 0:b16d94660a33 12808 #define UART_C5_RDMAS_MASK 0x20u
Jasper_lee 0:b16d94660a33 12809 #define UART_C5_RDMAS_SHIFT 5
Jasper_lee 0:b16d94660a33 12810 #define UART_C5_TCDMAS_MASK 0x40u
Jasper_lee 0:b16d94660a33 12811 #define UART_C5_TCDMAS_SHIFT 6
Jasper_lee 0:b16d94660a33 12812 #define UART_C5_TDMAS_MASK 0x80u
Jasper_lee 0:b16d94660a33 12813 #define UART_C5_TDMAS_SHIFT 7
Jasper_lee 0:b16d94660a33 12814 /* ED Bit Fields */
Jasper_lee 0:b16d94660a33 12815 #define UART_ED_PARITYE_MASK 0x40u
Jasper_lee 0:b16d94660a33 12816 #define UART_ED_PARITYE_SHIFT 6
Jasper_lee 0:b16d94660a33 12817 #define UART_ED_NOISY_MASK 0x80u
Jasper_lee 0:b16d94660a33 12818 #define UART_ED_NOISY_SHIFT 7
Jasper_lee 0:b16d94660a33 12819 /* MODEM Bit Fields */
Jasper_lee 0:b16d94660a33 12820 #define UART_MODEM_TXCTSE_MASK 0x1u
Jasper_lee 0:b16d94660a33 12821 #define UART_MODEM_TXCTSE_SHIFT 0
Jasper_lee 0:b16d94660a33 12822 #define UART_MODEM_TXRTSE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12823 #define UART_MODEM_TXRTSE_SHIFT 1
Jasper_lee 0:b16d94660a33 12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u
Jasper_lee 0:b16d94660a33 12825 #define UART_MODEM_TXRTSPOL_SHIFT 2
Jasper_lee 0:b16d94660a33 12826 #define UART_MODEM_RXRTSE_MASK 0x8u
Jasper_lee 0:b16d94660a33 12827 #define UART_MODEM_RXRTSE_SHIFT 3
Jasper_lee 0:b16d94660a33 12828 /* IR Bit Fields */
Jasper_lee 0:b16d94660a33 12829 #define UART_IR_TNP_MASK 0x3u
Jasper_lee 0:b16d94660a33 12830 #define UART_IR_TNP_SHIFT 0
Jasper_lee 0:b16d94660a33 12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
Jasper_lee 0:b16d94660a33 12832 #define UART_IR_IREN_MASK 0x4u
Jasper_lee 0:b16d94660a33 12833 #define UART_IR_IREN_SHIFT 2
Jasper_lee 0:b16d94660a33 12834 /* PFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
Jasper_lee 0:b16d94660a33 12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
Jasper_lee 0:b16d94660a33 12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
Jasper_lee 0:b16d94660a33 12838 #define UART_PFIFO_RXFE_MASK 0x8u
Jasper_lee 0:b16d94660a33 12839 #define UART_PFIFO_RXFE_SHIFT 3
Jasper_lee 0:b16d94660a33 12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
Jasper_lee 0:b16d94660a33 12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
Jasper_lee 0:b16d94660a33 12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
Jasper_lee 0:b16d94660a33 12843 #define UART_PFIFO_TXFE_MASK 0x80u
Jasper_lee 0:b16d94660a33 12844 #define UART_PFIFO_TXFE_SHIFT 7
Jasper_lee 0:b16d94660a33 12845 /* CFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12846 #define UART_CFIFO_RXUFE_MASK 0x1u
Jasper_lee 0:b16d94660a33 12847 #define UART_CFIFO_RXUFE_SHIFT 0
Jasper_lee 0:b16d94660a33 12848 #define UART_CFIFO_TXOFE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12849 #define UART_CFIFO_TXOFE_SHIFT 1
Jasper_lee 0:b16d94660a33 12850 #define UART_CFIFO_RXOFE_MASK 0x4u
Jasper_lee 0:b16d94660a33 12851 #define UART_CFIFO_RXOFE_SHIFT 2
Jasper_lee 0:b16d94660a33 12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u
Jasper_lee 0:b16d94660a33 12853 #define UART_CFIFO_RXFLUSH_SHIFT 6
Jasper_lee 0:b16d94660a33 12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u
Jasper_lee 0:b16d94660a33 12855 #define UART_CFIFO_TXFLUSH_SHIFT 7
Jasper_lee 0:b16d94660a33 12856 /* SFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12857 #define UART_SFIFO_RXUF_MASK 0x1u
Jasper_lee 0:b16d94660a33 12858 #define UART_SFIFO_RXUF_SHIFT 0
Jasper_lee 0:b16d94660a33 12859 #define UART_SFIFO_TXOF_MASK 0x2u
Jasper_lee 0:b16d94660a33 12860 #define UART_SFIFO_TXOF_SHIFT 1
Jasper_lee 0:b16d94660a33 12861 #define UART_SFIFO_RXOF_MASK 0x4u
Jasper_lee 0:b16d94660a33 12862 #define UART_SFIFO_RXOF_SHIFT 2
Jasper_lee 0:b16d94660a33 12863 #define UART_SFIFO_RXEMPT_MASK 0x40u
Jasper_lee 0:b16d94660a33 12864 #define UART_SFIFO_RXEMPT_SHIFT 6
Jasper_lee 0:b16d94660a33 12865 #define UART_SFIFO_TXEMPT_MASK 0x80u
Jasper_lee 0:b16d94660a33 12866 #define UART_SFIFO_TXEMPT_SHIFT 7
Jasper_lee 0:b16d94660a33 12867 /* TWFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12869 #define UART_TWFIFO_TXWATER_SHIFT 0
Jasper_lee 0:b16d94660a33 12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
Jasper_lee 0:b16d94660a33 12871 /* TCFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
Jasper_lee 0:b16d94660a33 12875 /* RWFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12877 #define UART_RWFIFO_RXWATER_SHIFT 0
Jasper_lee 0:b16d94660a33 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
Jasper_lee 0:b16d94660a33 12879 /* RCFIFO Bit Fields */
Jasper_lee 0:b16d94660a33 12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0
Jasper_lee 0:b16d94660a33 12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
Jasper_lee 0:b16d94660a33 12883 /* C7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12884 #define UART_C7816_ISO_7816E_MASK 0x1u
Jasper_lee 0:b16d94660a33 12885 #define UART_C7816_ISO_7816E_SHIFT 0
Jasper_lee 0:b16d94660a33 12886 #define UART_C7816_TTYPE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12887 #define UART_C7816_TTYPE_SHIFT 1
Jasper_lee 0:b16d94660a33 12888 #define UART_C7816_INIT_MASK 0x4u
Jasper_lee 0:b16d94660a33 12889 #define UART_C7816_INIT_SHIFT 2
Jasper_lee 0:b16d94660a33 12890 #define UART_C7816_ANACK_MASK 0x8u
Jasper_lee 0:b16d94660a33 12891 #define UART_C7816_ANACK_SHIFT 3
Jasper_lee 0:b16d94660a33 12892 #define UART_C7816_ONACK_MASK 0x10u
Jasper_lee 0:b16d94660a33 12893 #define UART_C7816_ONACK_SHIFT 4
Jasper_lee 0:b16d94660a33 12894 /* IE7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12895 #define UART_IE7816_RXTE_MASK 0x1u
Jasper_lee 0:b16d94660a33 12896 #define UART_IE7816_RXTE_SHIFT 0
Jasper_lee 0:b16d94660a33 12897 #define UART_IE7816_TXTE_MASK 0x2u
Jasper_lee 0:b16d94660a33 12898 #define UART_IE7816_TXTE_SHIFT 1
Jasper_lee 0:b16d94660a33 12899 #define UART_IE7816_GTVE_MASK 0x4u
Jasper_lee 0:b16d94660a33 12900 #define UART_IE7816_GTVE_SHIFT 2
Jasper_lee 0:b16d94660a33 12901 #define UART_IE7816_INITDE_MASK 0x10u
Jasper_lee 0:b16d94660a33 12902 #define UART_IE7816_INITDE_SHIFT 4
Jasper_lee 0:b16d94660a33 12903 #define UART_IE7816_BWTE_MASK 0x20u
Jasper_lee 0:b16d94660a33 12904 #define UART_IE7816_BWTE_SHIFT 5
Jasper_lee 0:b16d94660a33 12905 #define UART_IE7816_CWTE_MASK 0x40u
Jasper_lee 0:b16d94660a33 12906 #define UART_IE7816_CWTE_SHIFT 6
Jasper_lee 0:b16d94660a33 12907 #define UART_IE7816_WTE_MASK 0x80u
Jasper_lee 0:b16d94660a33 12908 #define UART_IE7816_WTE_SHIFT 7
Jasper_lee 0:b16d94660a33 12909 /* IS7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12910 #define UART_IS7816_RXT_MASK 0x1u
Jasper_lee 0:b16d94660a33 12911 #define UART_IS7816_RXT_SHIFT 0
Jasper_lee 0:b16d94660a33 12912 #define UART_IS7816_TXT_MASK 0x2u
Jasper_lee 0:b16d94660a33 12913 #define UART_IS7816_TXT_SHIFT 1
Jasper_lee 0:b16d94660a33 12914 #define UART_IS7816_GTV_MASK 0x4u
Jasper_lee 0:b16d94660a33 12915 #define UART_IS7816_GTV_SHIFT 2
Jasper_lee 0:b16d94660a33 12916 #define UART_IS7816_INITD_MASK 0x10u
Jasper_lee 0:b16d94660a33 12917 #define UART_IS7816_INITD_SHIFT 4
Jasper_lee 0:b16d94660a33 12918 #define UART_IS7816_BWT_MASK 0x20u
Jasper_lee 0:b16d94660a33 12919 #define UART_IS7816_BWT_SHIFT 5
Jasper_lee 0:b16d94660a33 12920 #define UART_IS7816_CWT_MASK 0x40u
Jasper_lee 0:b16d94660a33 12921 #define UART_IS7816_CWT_SHIFT 6
Jasper_lee 0:b16d94660a33 12922 #define UART_IS7816_WT_MASK 0x80u
Jasper_lee 0:b16d94660a33 12923 #define UART_IS7816_WT_SHIFT 7
Jasper_lee 0:b16d94660a33 12924 /* WP7816T0 Bit Fields */
Jasper_lee 0:b16d94660a33 12925 #define UART_WP7816T0_WI_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12926 #define UART_WP7816T0_WI_SHIFT 0
Jasper_lee 0:b16d94660a33 12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
Jasper_lee 0:b16d94660a33 12928 /* WP7816T1 Bit Fields */
Jasper_lee 0:b16d94660a33 12929 #define UART_WP7816T1_BWI_MASK 0xFu
Jasper_lee 0:b16d94660a33 12930 #define UART_WP7816T1_BWI_SHIFT 0
Jasper_lee 0:b16d94660a33 12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
Jasper_lee 0:b16d94660a33 12932 #define UART_WP7816T1_CWI_MASK 0xF0u
Jasper_lee 0:b16d94660a33 12933 #define UART_WP7816T1_CWI_SHIFT 4
Jasper_lee 0:b16d94660a33 12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
Jasper_lee 0:b16d94660a33 12935 /* WN7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12936 #define UART_WN7816_GTN_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12937 #define UART_WN7816_GTN_SHIFT 0
Jasper_lee 0:b16d94660a33 12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
Jasper_lee 0:b16d94660a33 12939 /* WF7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12940 #define UART_WF7816_GTFD_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12941 #define UART_WF7816_GTFD_SHIFT 0
Jasper_lee 0:b16d94660a33 12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
Jasper_lee 0:b16d94660a33 12943 /* ET7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
Jasper_lee 0:b16d94660a33 12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
Jasper_lee 0:b16d94660a33 12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
Jasper_lee 0:b16d94660a33 12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
Jasper_lee 0:b16d94660a33 12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
Jasper_lee 0:b16d94660a33 12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
Jasper_lee 0:b16d94660a33 12950 /* TL7816 Bit Fields */
Jasper_lee 0:b16d94660a33 12951 #define UART_TL7816_TLEN_MASK 0xFFu
Jasper_lee 0:b16d94660a33 12952 #define UART_TL7816_TLEN_SHIFT 0
Jasper_lee 0:b16d94660a33 12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
Jasper_lee 0:b16d94660a33 12954
Jasper_lee 0:b16d94660a33 12955 /*!
Jasper_lee 0:b16d94660a33 12956 * @}
Jasper_lee 0:b16d94660a33 12957 */ /* end of group UART_Register_Masks */
Jasper_lee 0:b16d94660a33 12958
Jasper_lee 0:b16d94660a33 12959
Jasper_lee 0:b16d94660a33 12960 /* UART - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 12961 /** Peripheral UART0 base address */
Jasper_lee 0:b16d94660a33 12962 #define UART0_BASE (0x4006A000u)
Jasper_lee 0:b16d94660a33 12963 /** Peripheral UART0 base pointer */
Jasper_lee 0:b16d94660a33 12964 #define UART0 ((UART_Type *)UART0_BASE)
Jasper_lee 0:b16d94660a33 12965 #define UART0_BASE_PTR (UART0)
Jasper_lee 0:b16d94660a33 12966 /** Peripheral UART1 base address */
Jasper_lee 0:b16d94660a33 12967 #define UART1_BASE (0x4006B000u)
Jasper_lee 0:b16d94660a33 12968 /** Peripheral UART1 base pointer */
Jasper_lee 0:b16d94660a33 12969 #define UART1 ((UART_Type *)UART1_BASE)
Jasper_lee 0:b16d94660a33 12970 #define UART1_BASE_PTR (UART1)
Jasper_lee 0:b16d94660a33 12971 /** Peripheral UART2 base address */
Jasper_lee 0:b16d94660a33 12972 #define UART2_BASE (0x4006C000u)
Jasper_lee 0:b16d94660a33 12973 /** Peripheral UART2 base pointer */
Jasper_lee 0:b16d94660a33 12974 #define UART2 ((UART_Type *)UART2_BASE)
Jasper_lee 0:b16d94660a33 12975 #define UART2_BASE_PTR (UART2)
Jasper_lee 0:b16d94660a33 12976 /** Peripheral UART3 base address */
Jasper_lee 0:b16d94660a33 12977 #define UART3_BASE (0x4006D000u)
Jasper_lee 0:b16d94660a33 12978 /** Peripheral UART3 base pointer */
Jasper_lee 0:b16d94660a33 12979 #define UART3 ((UART_Type *)UART3_BASE)
Jasper_lee 0:b16d94660a33 12980 #define UART3_BASE_PTR (UART3)
Jasper_lee 0:b16d94660a33 12981 /** Peripheral UART4 base address */
Jasper_lee 0:b16d94660a33 12982 #define UART4_BASE (0x400EA000u)
Jasper_lee 0:b16d94660a33 12983 /** Peripheral UART4 base pointer */
Jasper_lee 0:b16d94660a33 12984 #define UART4 ((UART_Type *)UART4_BASE)
Jasper_lee 0:b16d94660a33 12985 #define UART4_BASE_PTR (UART4)
Jasper_lee 0:b16d94660a33 12986 /** Peripheral UART5 base address */
Jasper_lee 0:b16d94660a33 12987 #define UART5_BASE (0x400EB000u)
Jasper_lee 0:b16d94660a33 12988 /** Peripheral UART5 base pointer */
Jasper_lee 0:b16d94660a33 12989 #define UART5 ((UART_Type *)UART5_BASE)
Jasper_lee 0:b16d94660a33 12990 #define UART5_BASE_PTR (UART5)
Jasper_lee 0:b16d94660a33 12991 /** Array initializer of UART peripheral base addresses */
Jasper_lee 0:b16d94660a33 12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
Jasper_lee 0:b16d94660a33 12993 /** Array initializer of UART peripheral base pointers */
Jasper_lee 0:b16d94660a33 12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
Jasper_lee 0:b16d94660a33 12995 /** Interrupt vectors for the UART peripheral type */
Jasper_lee 0:b16d94660a33 12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
Jasper_lee 0:b16d94660a33 12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
Jasper_lee 0:b16d94660a33 12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
Jasper_lee 0:b16d94660a33 12999
Jasper_lee 0:b16d94660a33 13000 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13001 -- UART - Register accessor macros
Jasper_lee 0:b16d94660a33 13002 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13003
Jasper_lee 0:b16d94660a33 13004 /*!
Jasper_lee 0:b16d94660a33 13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Jasper_lee 0:b16d94660a33 13006 * @{
Jasper_lee 0:b16d94660a33 13007 */
Jasper_lee 0:b16d94660a33 13008
Jasper_lee 0:b16d94660a33 13009
Jasper_lee 0:b16d94660a33 13010 /* UART - Register instance definitions */
Jasper_lee 0:b16d94660a33 13011 /* UART0 */
Jasper_lee 0:b16d94660a33 13012 #define UART0_BDH UART_BDH_REG(UART0)
Jasper_lee 0:b16d94660a33 13013 #define UART0_BDL UART_BDL_REG(UART0)
Jasper_lee 0:b16d94660a33 13014 #define UART0_C1 UART_C1_REG(UART0)
Jasper_lee 0:b16d94660a33 13015 #define UART0_C2 UART_C2_REG(UART0)
Jasper_lee 0:b16d94660a33 13016 #define UART0_S1 UART_S1_REG(UART0)
Jasper_lee 0:b16d94660a33 13017 #define UART0_S2 UART_S2_REG(UART0)
Jasper_lee 0:b16d94660a33 13018 #define UART0_C3 UART_C3_REG(UART0)
Jasper_lee 0:b16d94660a33 13019 #define UART0_D UART_D_REG(UART0)
Jasper_lee 0:b16d94660a33 13020 #define UART0_MA1 UART_MA1_REG(UART0)
Jasper_lee 0:b16d94660a33 13021 #define UART0_MA2 UART_MA2_REG(UART0)
Jasper_lee 0:b16d94660a33 13022 #define UART0_C4 UART_C4_REG(UART0)
Jasper_lee 0:b16d94660a33 13023 #define UART0_C5 UART_C5_REG(UART0)
Jasper_lee 0:b16d94660a33 13024 #define UART0_ED UART_ED_REG(UART0)
Jasper_lee 0:b16d94660a33 13025 #define UART0_MODEM UART_MODEM_REG(UART0)
Jasper_lee 0:b16d94660a33 13026 #define UART0_IR UART_IR_REG(UART0)
Jasper_lee 0:b16d94660a33 13027 #define UART0_PFIFO UART_PFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13028 #define UART0_CFIFO UART_CFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13029 #define UART0_SFIFO UART_SFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
Jasper_lee 0:b16d94660a33 13034 #define UART0_C7816 UART_C7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13035 #define UART0_IE7816 UART_IE7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13036 #define UART0_IS7816 UART_IS7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
Jasper_lee 0:b16d94660a33 13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
Jasper_lee 0:b16d94660a33 13039 #define UART0_WN7816 UART_WN7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13040 #define UART0_WF7816 UART_WF7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13041 #define UART0_ET7816 UART_ET7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13042 #define UART0_TL7816 UART_TL7816_REG(UART0)
Jasper_lee 0:b16d94660a33 13043 /* UART1 */
Jasper_lee 0:b16d94660a33 13044 #define UART1_BDH UART_BDH_REG(UART1)
Jasper_lee 0:b16d94660a33 13045 #define UART1_BDL UART_BDL_REG(UART1)
Jasper_lee 0:b16d94660a33 13046 #define UART1_C1 UART_C1_REG(UART1)
Jasper_lee 0:b16d94660a33 13047 #define UART1_C2 UART_C2_REG(UART1)
Jasper_lee 0:b16d94660a33 13048 #define UART1_S1 UART_S1_REG(UART1)
Jasper_lee 0:b16d94660a33 13049 #define UART1_S2 UART_S2_REG(UART1)
Jasper_lee 0:b16d94660a33 13050 #define UART1_C3 UART_C3_REG(UART1)
Jasper_lee 0:b16d94660a33 13051 #define UART1_D UART_D_REG(UART1)
Jasper_lee 0:b16d94660a33 13052 #define UART1_MA1 UART_MA1_REG(UART1)
Jasper_lee 0:b16d94660a33 13053 #define UART1_MA2 UART_MA2_REG(UART1)
Jasper_lee 0:b16d94660a33 13054 #define UART1_C4 UART_C4_REG(UART1)
Jasper_lee 0:b16d94660a33 13055 #define UART1_C5 UART_C5_REG(UART1)
Jasper_lee 0:b16d94660a33 13056 #define UART1_ED UART_ED_REG(UART1)
Jasper_lee 0:b16d94660a33 13057 #define UART1_MODEM UART_MODEM_REG(UART1)
Jasper_lee 0:b16d94660a33 13058 #define UART1_IR UART_IR_REG(UART1)
Jasper_lee 0:b16d94660a33 13059 #define UART1_PFIFO UART_PFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13060 #define UART1_CFIFO UART_CFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13061 #define UART1_SFIFO UART_SFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
Jasper_lee 0:b16d94660a33 13066 /* UART2 */
Jasper_lee 0:b16d94660a33 13067 #define UART2_BDH UART_BDH_REG(UART2)
Jasper_lee 0:b16d94660a33 13068 #define UART2_BDL UART_BDL_REG(UART2)
Jasper_lee 0:b16d94660a33 13069 #define UART2_C1 UART_C1_REG(UART2)
Jasper_lee 0:b16d94660a33 13070 #define UART2_C2 UART_C2_REG(UART2)
Jasper_lee 0:b16d94660a33 13071 #define UART2_S1 UART_S1_REG(UART2)
Jasper_lee 0:b16d94660a33 13072 #define UART2_S2 UART_S2_REG(UART2)
Jasper_lee 0:b16d94660a33 13073 #define UART2_C3 UART_C3_REG(UART2)
Jasper_lee 0:b16d94660a33 13074 #define UART2_D UART_D_REG(UART2)
Jasper_lee 0:b16d94660a33 13075 #define UART2_MA1 UART_MA1_REG(UART2)
Jasper_lee 0:b16d94660a33 13076 #define UART2_MA2 UART_MA2_REG(UART2)
Jasper_lee 0:b16d94660a33 13077 #define UART2_C4 UART_C4_REG(UART2)
Jasper_lee 0:b16d94660a33 13078 #define UART2_C5 UART_C5_REG(UART2)
Jasper_lee 0:b16d94660a33 13079 #define UART2_ED UART_ED_REG(UART2)
Jasper_lee 0:b16d94660a33 13080 #define UART2_MODEM UART_MODEM_REG(UART2)
Jasper_lee 0:b16d94660a33 13081 #define UART2_IR UART_IR_REG(UART2)
Jasper_lee 0:b16d94660a33 13082 #define UART2_PFIFO UART_PFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13083 #define UART2_CFIFO UART_CFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13084 #define UART2_SFIFO UART_SFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
Jasper_lee 0:b16d94660a33 13089 /* UART3 */
Jasper_lee 0:b16d94660a33 13090 #define UART3_BDH UART_BDH_REG(UART3)
Jasper_lee 0:b16d94660a33 13091 #define UART3_BDL UART_BDL_REG(UART3)
Jasper_lee 0:b16d94660a33 13092 #define UART3_C1 UART_C1_REG(UART3)
Jasper_lee 0:b16d94660a33 13093 #define UART3_C2 UART_C2_REG(UART3)
Jasper_lee 0:b16d94660a33 13094 #define UART3_S1 UART_S1_REG(UART3)
Jasper_lee 0:b16d94660a33 13095 #define UART3_S2 UART_S2_REG(UART3)
Jasper_lee 0:b16d94660a33 13096 #define UART3_C3 UART_C3_REG(UART3)
Jasper_lee 0:b16d94660a33 13097 #define UART3_D UART_D_REG(UART3)
Jasper_lee 0:b16d94660a33 13098 #define UART3_MA1 UART_MA1_REG(UART3)
Jasper_lee 0:b16d94660a33 13099 #define UART3_MA2 UART_MA2_REG(UART3)
Jasper_lee 0:b16d94660a33 13100 #define UART3_C4 UART_C4_REG(UART3)
Jasper_lee 0:b16d94660a33 13101 #define UART3_C5 UART_C5_REG(UART3)
Jasper_lee 0:b16d94660a33 13102 #define UART3_ED UART_ED_REG(UART3)
Jasper_lee 0:b16d94660a33 13103 #define UART3_MODEM UART_MODEM_REG(UART3)
Jasper_lee 0:b16d94660a33 13104 #define UART3_IR UART_IR_REG(UART3)
Jasper_lee 0:b16d94660a33 13105 #define UART3_PFIFO UART_PFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13106 #define UART3_CFIFO UART_CFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13107 #define UART3_SFIFO UART_SFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
Jasper_lee 0:b16d94660a33 13112 /* UART4 */
Jasper_lee 0:b16d94660a33 13113 #define UART4_BDH UART_BDH_REG(UART4)
Jasper_lee 0:b16d94660a33 13114 #define UART4_BDL UART_BDL_REG(UART4)
Jasper_lee 0:b16d94660a33 13115 #define UART4_C1 UART_C1_REG(UART4)
Jasper_lee 0:b16d94660a33 13116 #define UART4_C2 UART_C2_REG(UART4)
Jasper_lee 0:b16d94660a33 13117 #define UART4_S1 UART_S1_REG(UART4)
Jasper_lee 0:b16d94660a33 13118 #define UART4_S2 UART_S2_REG(UART4)
Jasper_lee 0:b16d94660a33 13119 #define UART4_C3 UART_C3_REG(UART4)
Jasper_lee 0:b16d94660a33 13120 #define UART4_D UART_D_REG(UART4)
Jasper_lee 0:b16d94660a33 13121 #define UART4_MA1 UART_MA1_REG(UART4)
Jasper_lee 0:b16d94660a33 13122 #define UART4_MA2 UART_MA2_REG(UART4)
Jasper_lee 0:b16d94660a33 13123 #define UART4_C4 UART_C4_REG(UART4)
Jasper_lee 0:b16d94660a33 13124 #define UART4_C5 UART_C5_REG(UART4)
Jasper_lee 0:b16d94660a33 13125 #define UART4_ED UART_ED_REG(UART4)
Jasper_lee 0:b16d94660a33 13126 #define UART4_MODEM UART_MODEM_REG(UART4)
Jasper_lee 0:b16d94660a33 13127 #define UART4_IR UART_IR_REG(UART4)
Jasper_lee 0:b16d94660a33 13128 #define UART4_PFIFO UART_PFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13129 #define UART4_CFIFO UART_CFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13130 #define UART4_SFIFO UART_SFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
Jasper_lee 0:b16d94660a33 13135 /* UART5 */
Jasper_lee 0:b16d94660a33 13136 #define UART5_BDH UART_BDH_REG(UART5)
Jasper_lee 0:b16d94660a33 13137 #define UART5_BDL UART_BDL_REG(UART5)
Jasper_lee 0:b16d94660a33 13138 #define UART5_C1 UART_C1_REG(UART5)
Jasper_lee 0:b16d94660a33 13139 #define UART5_C2 UART_C2_REG(UART5)
Jasper_lee 0:b16d94660a33 13140 #define UART5_S1 UART_S1_REG(UART5)
Jasper_lee 0:b16d94660a33 13141 #define UART5_S2 UART_S2_REG(UART5)
Jasper_lee 0:b16d94660a33 13142 #define UART5_C3 UART_C3_REG(UART5)
Jasper_lee 0:b16d94660a33 13143 #define UART5_D UART_D_REG(UART5)
Jasper_lee 0:b16d94660a33 13144 #define UART5_MA1 UART_MA1_REG(UART5)
Jasper_lee 0:b16d94660a33 13145 #define UART5_MA2 UART_MA2_REG(UART5)
Jasper_lee 0:b16d94660a33 13146 #define UART5_C4 UART_C4_REG(UART5)
Jasper_lee 0:b16d94660a33 13147 #define UART5_C5 UART_C5_REG(UART5)
Jasper_lee 0:b16d94660a33 13148 #define UART5_ED UART_ED_REG(UART5)
Jasper_lee 0:b16d94660a33 13149 #define UART5_MODEM UART_MODEM_REG(UART5)
Jasper_lee 0:b16d94660a33 13150 #define UART5_IR UART_IR_REG(UART5)
Jasper_lee 0:b16d94660a33 13151 #define UART5_PFIFO UART_PFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13152 #define UART5_CFIFO UART_CFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13153 #define UART5_SFIFO UART_SFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
Jasper_lee 0:b16d94660a33 13158
Jasper_lee 0:b16d94660a33 13159 /*!
Jasper_lee 0:b16d94660a33 13160 * @}
Jasper_lee 0:b16d94660a33 13161 */ /* end of group UART_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13162
Jasper_lee 0:b16d94660a33 13163
Jasper_lee 0:b16d94660a33 13164 /*!
Jasper_lee 0:b16d94660a33 13165 * @}
Jasper_lee 0:b16d94660a33 13166 */ /* end of group UART_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 13167
Jasper_lee 0:b16d94660a33 13168
Jasper_lee 0:b16d94660a33 13169 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13170 -- USB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13171 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13172
Jasper_lee 0:b16d94660a33 13173 /*!
Jasper_lee 0:b16d94660a33 13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13175 * @{
Jasper_lee 0:b16d94660a33 13176 */
Jasper_lee 0:b16d94660a33 13177
Jasper_lee 0:b16d94660a33 13178 /** USB - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 13179 typedef struct {
Jasper_lee 0:b16d94660a33 13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 13181 uint8_t RESERVED_0[3];
Jasper_lee 0:b16d94660a33 13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 13183 uint8_t RESERVED_1[3];
Jasper_lee 0:b16d94660a33 13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 13185 uint8_t RESERVED_2[3];
Jasper_lee 0:b16d94660a33 13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
Jasper_lee 0:b16d94660a33 13187 uint8_t RESERVED_3[3];
Jasper_lee 0:b16d94660a33 13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 13189 uint8_t RESERVED_4[3];
Jasper_lee 0:b16d94660a33 13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 13191 uint8_t RESERVED_5[3];
Jasper_lee 0:b16d94660a33 13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 13193 uint8_t RESERVED_6[3];
Jasper_lee 0:b16d94660a33 13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
Jasper_lee 0:b16d94660a33 13195 uint8_t RESERVED_7[99];
Jasper_lee 0:b16d94660a33 13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
Jasper_lee 0:b16d94660a33 13197 uint8_t RESERVED_8[3];
Jasper_lee 0:b16d94660a33 13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
Jasper_lee 0:b16d94660a33 13199 uint8_t RESERVED_9[3];
Jasper_lee 0:b16d94660a33 13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
Jasper_lee 0:b16d94660a33 13201 uint8_t RESERVED_10[3];
Jasper_lee 0:b16d94660a33 13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
Jasper_lee 0:b16d94660a33 13203 uint8_t RESERVED_11[3];
Jasper_lee 0:b16d94660a33 13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */
Jasper_lee 0:b16d94660a33 13205 uint8_t RESERVED_12[3];
Jasper_lee 0:b16d94660a33 13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
Jasper_lee 0:b16d94660a33 13207 uint8_t RESERVED_13[3];
Jasper_lee 0:b16d94660a33 13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
Jasper_lee 0:b16d94660a33 13209 uint8_t RESERVED_14[3];
Jasper_lee 0:b16d94660a33 13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
Jasper_lee 0:b16d94660a33 13211 uint8_t RESERVED_15[3];
Jasper_lee 0:b16d94660a33 13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
Jasper_lee 0:b16d94660a33 13213 uint8_t RESERVED_16[3];
Jasper_lee 0:b16d94660a33 13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
Jasper_lee 0:b16d94660a33 13215 uint8_t RESERVED_17[3];
Jasper_lee 0:b16d94660a33 13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
Jasper_lee 0:b16d94660a33 13217 uint8_t RESERVED_18[3];
Jasper_lee 0:b16d94660a33 13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
Jasper_lee 0:b16d94660a33 13219 uint8_t RESERVED_19[3];
Jasper_lee 0:b16d94660a33 13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
Jasper_lee 0:b16d94660a33 13221 uint8_t RESERVED_20[3];
Jasper_lee 0:b16d94660a33 13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
Jasper_lee 0:b16d94660a33 13223 uint8_t RESERVED_21[11];
Jasper_lee 0:b16d94660a33 13224 struct { /* offset: 0xC0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
Jasper_lee 0:b16d94660a33 13226 uint8_t RESERVED_0[3];
Jasper_lee 0:b16d94660a33 13227 } ENDPOINT[16];
Jasper_lee 0:b16d94660a33 13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
Jasper_lee 0:b16d94660a33 13229 uint8_t RESERVED_22[3];
Jasper_lee 0:b16d94660a33 13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
Jasper_lee 0:b16d94660a33 13231 uint8_t RESERVED_23[3];
Jasper_lee 0:b16d94660a33 13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
Jasper_lee 0:b16d94660a33 13233 uint8_t RESERVED_24[3];
Jasper_lee 0:b16d94660a33 13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
Jasper_lee 0:b16d94660a33 13235 uint8_t RESERVED_25[7];
Jasper_lee 0:b16d94660a33 13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
Jasper_lee 0:b16d94660a33 13237 uint8_t RESERVED_26[43];
Jasper_lee 0:b16d94660a33 13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
Jasper_lee 0:b16d94660a33 13239 uint8_t RESERVED_27[3];
Jasper_lee 0:b16d94660a33 13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
Jasper_lee 0:b16d94660a33 13241 uint8_t RESERVED_28[23];
Jasper_lee 0:b16d94660a33 13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
Jasper_lee 0:b16d94660a33 13243 } USB_Type, *USB_MemMapPtr;
Jasper_lee 0:b16d94660a33 13244
Jasper_lee 0:b16d94660a33 13245 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13246 -- USB - Register accessor macros
Jasper_lee 0:b16d94660a33 13247 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13248
Jasper_lee 0:b16d94660a33 13249 /*!
Jasper_lee 0:b16d94660a33 13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Jasper_lee 0:b16d94660a33 13251 * @{
Jasper_lee 0:b16d94660a33 13252 */
Jasper_lee 0:b16d94660a33 13253
Jasper_lee 0:b16d94660a33 13254
Jasper_lee 0:b16d94660a33 13255 /* USB - Register accessors */
Jasper_lee 0:b16d94660a33 13256 #define USB_PERID_REG(base) ((base)->PERID)
Jasper_lee 0:b16d94660a33 13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
Jasper_lee 0:b16d94660a33 13258 #define USB_REV_REG(base) ((base)->REV)
Jasper_lee 0:b16d94660a33 13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
Jasper_lee 0:b16d94660a33 13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
Jasper_lee 0:b16d94660a33 13261 #define USB_OTGICR_REG(base) ((base)->OTGICR)
Jasper_lee 0:b16d94660a33 13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
Jasper_lee 0:b16d94660a33 13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
Jasper_lee 0:b16d94660a33 13264 #define USB_ISTAT_REG(base) ((base)->ISTAT)
Jasper_lee 0:b16d94660a33 13265 #define USB_INTEN_REG(base) ((base)->INTEN)
Jasper_lee 0:b16d94660a33 13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
Jasper_lee 0:b16d94660a33 13267 #define USB_ERREN_REG(base) ((base)->ERREN)
Jasper_lee 0:b16d94660a33 13268 #define USB_STAT_REG(base) ((base)->STAT)
Jasper_lee 0:b16d94660a33 13269 #define USB_CTL_REG(base) ((base)->CTL)
Jasper_lee 0:b16d94660a33 13270 #define USB_ADDR_REG(base) ((base)->ADDR)
Jasper_lee 0:b16d94660a33 13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
Jasper_lee 0:b16d94660a33 13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
Jasper_lee 0:b16d94660a33 13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
Jasper_lee 0:b16d94660a33 13274 #define USB_TOKEN_REG(base) ((base)->TOKEN)
Jasper_lee 0:b16d94660a33 13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
Jasper_lee 0:b16d94660a33 13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
Jasper_lee 0:b16d94660a33 13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
Jasper_lee 0:b16d94660a33 13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
Jasper_lee 0:b16d94660a33 13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
Jasper_lee 0:b16d94660a33 13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
Jasper_lee 0:b16d94660a33 13281 #define USB_CONTROL_REG(base) ((base)->CONTROL)
Jasper_lee 0:b16d94660a33 13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
Jasper_lee 0:b16d94660a33 13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
Jasper_lee 0:b16d94660a33 13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
Jasper_lee 0:b16d94660a33 13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
Jasper_lee 0:b16d94660a33 13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
Jasper_lee 0:b16d94660a33 13287
Jasper_lee 0:b16d94660a33 13288 /*!
Jasper_lee 0:b16d94660a33 13289 * @}
Jasper_lee 0:b16d94660a33 13290 */ /* end of group USB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13291
Jasper_lee 0:b16d94660a33 13292
Jasper_lee 0:b16d94660a33 13293 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13294 -- USB Register Masks
Jasper_lee 0:b16d94660a33 13295 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13296
Jasper_lee 0:b16d94660a33 13297 /*!
Jasper_lee 0:b16d94660a33 13298 * @addtogroup USB_Register_Masks USB Register Masks
Jasper_lee 0:b16d94660a33 13299 * @{
Jasper_lee 0:b16d94660a33 13300 */
Jasper_lee 0:b16d94660a33 13301
Jasper_lee 0:b16d94660a33 13302 /* PERID Bit Fields */
Jasper_lee 0:b16d94660a33 13303 #define USB_PERID_ID_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 13304 #define USB_PERID_ID_SHIFT 0
Jasper_lee 0:b16d94660a33 13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
Jasper_lee 0:b16d94660a33 13306 /* IDCOMP Bit Fields */
Jasper_lee 0:b16d94660a33 13307 #define USB_IDCOMP_NID_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 13308 #define USB_IDCOMP_NID_SHIFT 0
Jasper_lee 0:b16d94660a33 13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
Jasper_lee 0:b16d94660a33 13310 /* REV Bit Fields */
Jasper_lee 0:b16d94660a33 13311 #define USB_REV_REV_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13312 #define USB_REV_REV_SHIFT 0
Jasper_lee 0:b16d94660a33 13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
Jasper_lee 0:b16d94660a33 13314 /* ADDINFO Bit Fields */
Jasper_lee 0:b16d94660a33 13315 #define USB_ADDINFO_IEHOST_MASK 0x1u
Jasper_lee 0:b16d94660a33 13316 #define USB_ADDINFO_IEHOST_SHIFT 0
Jasper_lee 0:b16d94660a33 13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
Jasper_lee 0:b16d94660a33 13318 #define USB_ADDINFO_IRQNUM_SHIFT 3
Jasper_lee 0:b16d94660a33 13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
Jasper_lee 0:b16d94660a33 13320 /* OTGISTAT Bit Fields */
Jasper_lee 0:b16d94660a33 13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
Jasper_lee 0:b16d94660a33 13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
Jasper_lee 0:b16d94660a33 13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
Jasper_lee 0:b16d94660a33 13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
Jasper_lee 0:b16d94660a33 13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
Jasper_lee 0:b16d94660a33 13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
Jasper_lee 0:b16d94660a33 13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
Jasper_lee 0:b16d94660a33 13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
Jasper_lee 0:b16d94660a33 13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
Jasper_lee 0:b16d94660a33 13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
Jasper_lee 0:b16d94660a33 13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u
Jasper_lee 0:b16d94660a33 13332 #define USB_OTGISTAT_IDCHG_SHIFT 7
Jasper_lee 0:b16d94660a33 13333 /* OTGICR Bit Fields */
Jasper_lee 0:b16d94660a33 13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13335 #define USB_OTGICR_AVBUSEN_SHIFT 0
Jasper_lee 0:b16d94660a33 13336 #define USB_OTGICR_BSESSEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13337 #define USB_OTGICR_BSESSEN_SHIFT 2
Jasper_lee 0:b16d94660a33 13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3
Jasper_lee 0:b16d94660a33 13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5
Jasper_lee 0:b16d94660a33 13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13344 #define USB_OTGICR_IDEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13345 #define USB_OTGICR_IDEN_SHIFT 7
Jasper_lee 0:b16d94660a33 13346 /* OTGSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
Jasper_lee 0:b16d94660a33 13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
Jasper_lee 0:b16d94660a33 13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
Jasper_lee 0:b16d94660a33 13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2
Jasper_lee 0:b16d94660a33 13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
Jasper_lee 0:b16d94660a33 13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
Jasper_lee 0:b16d94660a33 13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
Jasper_lee 0:b16d94660a33 13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
Jasper_lee 0:b16d94660a33 13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13357 #define USB_OTGSTAT_ID_MASK 0x80u
Jasper_lee 0:b16d94660a33 13358 #define USB_OTGSTAT_ID_SHIFT 7
Jasper_lee 0:b16d94660a33 13359 /* OTGCTL Bit Fields */
Jasper_lee 0:b16d94660a33 13360 #define USB_OTGCTL_OTGEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13361 #define USB_OTGCTL_OTGEN_SHIFT 2
Jasper_lee 0:b16d94660a33 13362 #define USB_OTGCTL_DMLOW_MASK 0x10u
Jasper_lee 0:b16d94660a33 13363 #define USB_OTGCTL_DMLOW_SHIFT 4
Jasper_lee 0:b16d94660a33 13364 #define USB_OTGCTL_DPLOW_MASK 0x20u
Jasper_lee 0:b16d94660a33 13365 #define USB_OTGCTL_DPLOW_SHIFT 5
Jasper_lee 0:b16d94660a33 13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u
Jasper_lee 0:b16d94660a33 13367 #define USB_OTGCTL_DPHIGH_SHIFT 7
Jasper_lee 0:b16d94660a33 13368 /* ISTAT Bit Fields */
Jasper_lee 0:b16d94660a33 13369 #define USB_ISTAT_USBRST_MASK 0x1u
Jasper_lee 0:b16d94660a33 13370 #define USB_ISTAT_USBRST_SHIFT 0
Jasper_lee 0:b16d94660a33 13371 #define USB_ISTAT_ERROR_MASK 0x2u
Jasper_lee 0:b16d94660a33 13372 #define USB_ISTAT_ERROR_SHIFT 1
Jasper_lee 0:b16d94660a33 13373 #define USB_ISTAT_SOFTOK_MASK 0x4u
Jasper_lee 0:b16d94660a33 13374 #define USB_ISTAT_SOFTOK_SHIFT 2
Jasper_lee 0:b16d94660a33 13375 #define USB_ISTAT_TOKDNE_MASK 0x8u
Jasper_lee 0:b16d94660a33 13376 #define USB_ISTAT_TOKDNE_SHIFT 3
Jasper_lee 0:b16d94660a33 13377 #define USB_ISTAT_SLEEP_MASK 0x10u
Jasper_lee 0:b16d94660a33 13378 #define USB_ISTAT_SLEEP_SHIFT 4
Jasper_lee 0:b16d94660a33 13379 #define USB_ISTAT_RESUME_MASK 0x20u
Jasper_lee 0:b16d94660a33 13380 #define USB_ISTAT_RESUME_SHIFT 5
Jasper_lee 0:b16d94660a33 13381 #define USB_ISTAT_ATTACH_MASK 0x40u
Jasper_lee 0:b16d94660a33 13382 #define USB_ISTAT_ATTACH_SHIFT 6
Jasper_lee 0:b16d94660a33 13383 #define USB_ISTAT_STALL_MASK 0x80u
Jasper_lee 0:b16d94660a33 13384 #define USB_ISTAT_STALL_SHIFT 7
Jasper_lee 0:b16d94660a33 13385 /* INTEN Bit Fields */
Jasper_lee 0:b16d94660a33 13386 #define USB_INTEN_USBRSTEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13387 #define USB_INTEN_USBRSTEN_SHIFT 0
Jasper_lee 0:b16d94660a33 13388 #define USB_INTEN_ERROREN_MASK 0x2u
Jasper_lee 0:b16d94660a33 13389 #define USB_INTEN_ERROREN_SHIFT 1
Jasper_lee 0:b16d94660a33 13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13391 #define USB_INTEN_SOFTOKEN_SHIFT 2
Jasper_lee 0:b16d94660a33 13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13393 #define USB_INTEN_TOKDNEEN_SHIFT 3
Jasper_lee 0:b16d94660a33 13394 #define USB_INTEN_SLEEPEN_MASK 0x10u
Jasper_lee 0:b16d94660a33 13395 #define USB_INTEN_SLEEPEN_SHIFT 4
Jasper_lee 0:b16d94660a33 13396 #define USB_INTEN_RESUMEEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13397 #define USB_INTEN_RESUMEEN_SHIFT 5
Jasper_lee 0:b16d94660a33 13398 #define USB_INTEN_ATTACHEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13399 #define USB_INTEN_ATTACHEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13400 #define USB_INTEN_STALLEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13401 #define USB_INTEN_STALLEN_SHIFT 7
Jasper_lee 0:b16d94660a33 13402 /* ERRSTAT Bit Fields */
Jasper_lee 0:b16d94660a33 13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u
Jasper_lee 0:b16d94660a33 13404 #define USB_ERRSTAT_PIDERR_SHIFT 0
Jasper_lee 0:b16d94660a33 13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
Jasper_lee 0:b16d94660a33 13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
Jasper_lee 0:b16d94660a33 13407 #define USB_ERRSTAT_CRC16_MASK 0x4u
Jasper_lee 0:b16d94660a33 13408 #define USB_ERRSTAT_CRC16_SHIFT 2
Jasper_lee 0:b16d94660a33 13409 #define USB_ERRSTAT_DFN8_MASK 0x8u
Jasper_lee 0:b16d94660a33 13410 #define USB_ERRSTAT_DFN8_SHIFT 3
Jasper_lee 0:b16d94660a33 13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u
Jasper_lee 0:b16d94660a33 13412 #define USB_ERRSTAT_BTOERR_SHIFT 4
Jasper_lee 0:b16d94660a33 13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u
Jasper_lee 0:b16d94660a33 13414 #define USB_ERRSTAT_DMAERR_SHIFT 5
Jasper_lee 0:b16d94660a33 13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u
Jasper_lee 0:b16d94660a33 13416 #define USB_ERRSTAT_BTSERR_SHIFT 7
Jasper_lee 0:b16d94660a33 13417 /* ERREN Bit Fields */
Jasper_lee 0:b16d94660a33 13418 #define USB_ERREN_PIDERREN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13419 #define USB_ERREN_PIDERREN_SHIFT 0
Jasper_lee 0:b16d94660a33 13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
Jasper_lee 0:b16d94660a33 13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1
Jasper_lee 0:b16d94660a33 13422 #define USB_ERREN_CRC16EN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13423 #define USB_ERREN_CRC16EN_SHIFT 2
Jasper_lee 0:b16d94660a33 13424 #define USB_ERREN_DFN8EN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13425 #define USB_ERREN_DFN8EN_SHIFT 3
Jasper_lee 0:b16d94660a33 13426 #define USB_ERREN_BTOERREN_MASK 0x10u
Jasper_lee 0:b16d94660a33 13427 #define USB_ERREN_BTOERREN_SHIFT 4
Jasper_lee 0:b16d94660a33 13428 #define USB_ERREN_DMAERREN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13429 #define USB_ERREN_DMAERREN_SHIFT 5
Jasper_lee 0:b16d94660a33 13430 #define USB_ERREN_BTSERREN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13431 #define USB_ERREN_BTSERREN_SHIFT 7
Jasper_lee 0:b16d94660a33 13432 /* STAT Bit Fields */
Jasper_lee 0:b16d94660a33 13433 #define USB_STAT_ODD_MASK 0x4u
Jasper_lee 0:b16d94660a33 13434 #define USB_STAT_ODD_SHIFT 2
Jasper_lee 0:b16d94660a33 13435 #define USB_STAT_TX_MASK 0x8u
Jasper_lee 0:b16d94660a33 13436 #define USB_STAT_TX_SHIFT 3
Jasper_lee 0:b16d94660a33 13437 #define USB_STAT_ENDP_MASK 0xF0u
Jasper_lee 0:b16d94660a33 13438 #define USB_STAT_ENDP_SHIFT 4
Jasper_lee 0:b16d94660a33 13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
Jasper_lee 0:b16d94660a33 13440 /* CTL Bit Fields */
Jasper_lee 0:b16d94660a33 13441 #define USB_CTL_USBENSOFEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13442 #define USB_CTL_USBENSOFEN_SHIFT 0
Jasper_lee 0:b16d94660a33 13443 #define USB_CTL_ODDRST_MASK 0x2u
Jasper_lee 0:b16d94660a33 13444 #define USB_CTL_ODDRST_SHIFT 1
Jasper_lee 0:b16d94660a33 13445 #define USB_CTL_RESUME_MASK 0x4u
Jasper_lee 0:b16d94660a33 13446 #define USB_CTL_RESUME_SHIFT 2
Jasper_lee 0:b16d94660a33 13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13448 #define USB_CTL_HOSTMODEEN_SHIFT 3
Jasper_lee 0:b16d94660a33 13449 #define USB_CTL_RESET_MASK 0x10u
Jasper_lee 0:b16d94660a33 13450 #define USB_CTL_RESET_SHIFT 4
Jasper_lee 0:b16d94660a33 13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
Jasper_lee 0:b16d94660a33 13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
Jasper_lee 0:b16d94660a33 13453 #define USB_CTL_SE0_MASK 0x40u
Jasper_lee 0:b16d94660a33 13454 #define USB_CTL_SE0_SHIFT 6
Jasper_lee 0:b16d94660a33 13455 #define USB_CTL_JSTATE_MASK 0x80u
Jasper_lee 0:b16d94660a33 13456 #define USB_CTL_JSTATE_SHIFT 7
Jasper_lee 0:b16d94660a33 13457 /* ADDR Bit Fields */
Jasper_lee 0:b16d94660a33 13458 #define USB_ADDR_ADDR_MASK 0x7Fu
Jasper_lee 0:b16d94660a33 13459 #define USB_ADDR_ADDR_SHIFT 0
Jasper_lee 0:b16d94660a33 13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
Jasper_lee 0:b16d94660a33 13461 #define USB_ADDR_LSEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13462 #define USB_ADDR_LSEN_SHIFT 7
Jasper_lee 0:b16d94660a33 13463 /* BDTPAGE1 Bit Fields */
Jasper_lee 0:b16d94660a33 13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
Jasper_lee 0:b16d94660a33 13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1
Jasper_lee 0:b16d94660a33 13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
Jasper_lee 0:b16d94660a33 13467 /* FRMNUML Bit Fields */
Jasper_lee 0:b16d94660a33 13468 #define USB_FRMNUML_FRM_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13469 #define USB_FRMNUML_FRM_SHIFT 0
Jasper_lee 0:b16d94660a33 13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
Jasper_lee 0:b16d94660a33 13471 /* FRMNUMH Bit Fields */
Jasper_lee 0:b16d94660a33 13472 #define USB_FRMNUMH_FRM_MASK 0x7u
Jasper_lee 0:b16d94660a33 13473 #define USB_FRMNUMH_FRM_SHIFT 0
Jasper_lee 0:b16d94660a33 13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
Jasper_lee 0:b16d94660a33 13475 /* TOKEN Bit Fields */
Jasper_lee 0:b16d94660a33 13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
Jasper_lee 0:b16d94660a33 13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0
Jasper_lee 0:b16d94660a33 13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
Jasper_lee 0:b16d94660a33 13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u
Jasper_lee 0:b16d94660a33 13480 #define USB_TOKEN_TOKENPID_SHIFT 4
Jasper_lee 0:b16d94660a33 13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
Jasper_lee 0:b16d94660a33 13482 /* SOFTHLD Bit Fields */
Jasper_lee 0:b16d94660a33 13483 #define USB_SOFTHLD_CNT_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13484 #define USB_SOFTHLD_CNT_SHIFT 0
Jasper_lee 0:b16d94660a33 13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
Jasper_lee 0:b16d94660a33 13486 /* BDTPAGE2 Bit Fields */
Jasper_lee 0:b16d94660a33 13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0
Jasper_lee 0:b16d94660a33 13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
Jasper_lee 0:b16d94660a33 13490 /* BDTPAGE3 Bit Fields */
Jasper_lee 0:b16d94660a33 13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0
Jasper_lee 0:b16d94660a33 13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
Jasper_lee 0:b16d94660a33 13494 /* ENDPT Bit Fields */
Jasper_lee 0:b16d94660a33 13495 #define USB_ENDPT_EPHSHK_MASK 0x1u
Jasper_lee 0:b16d94660a33 13496 #define USB_ENDPT_EPHSHK_SHIFT 0
Jasper_lee 0:b16d94660a33 13497 #define USB_ENDPT_EPSTALL_MASK 0x2u
Jasper_lee 0:b16d94660a33 13498 #define USB_ENDPT_EPSTALL_SHIFT 1
Jasper_lee 0:b16d94660a33 13499 #define USB_ENDPT_EPTXEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13500 #define USB_ENDPT_EPTXEN_SHIFT 2
Jasper_lee 0:b16d94660a33 13501 #define USB_ENDPT_EPRXEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13502 #define USB_ENDPT_EPRXEN_SHIFT 3
Jasper_lee 0:b16d94660a33 13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
Jasper_lee 0:b16d94660a33 13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4
Jasper_lee 0:b16d94660a33 13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u
Jasper_lee 0:b16d94660a33 13506 #define USB_ENDPT_RETRYDIS_SHIFT 6
Jasper_lee 0:b16d94660a33 13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
Jasper_lee 0:b16d94660a33 13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
Jasper_lee 0:b16d94660a33 13509 /* USBCTRL Bit Fields */
Jasper_lee 0:b16d94660a33 13510 #define USB_USBCTRL_PDE_MASK 0x40u
Jasper_lee 0:b16d94660a33 13511 #define USB_USBCTRL_PDE_SHIFT 6
Jasper_lee 0:b16d94660a33 13512 #define USB_USBCTRL_SUSP_MASK 0x80u
Jasper_lee 0:b16d94660a33 13513 #define USB_USBCTRL_SUSP_SHIFT 7
Jasper_lee 0:b16d94660a33 13514 /* OBSERVE Bit Fields */
Jasper_lee 0:b16d94660a33 13515 #define USB_OBSERVE_DMPD_MASK 0x10u
Jasper_lee 0:b16d94660a33 13516 #define USB_OBSERVE_DMPD_SHIFT 4
Jasper_lee 0:b16d94660a33 13517 #define USB_OBSERVE_DPPD_MASK 0x40u
Jasper_lee 0:b16d94660a33 13518 #define USB_OBSERVE_DPPD_SHIFT 6
Jasper_lee 0:b16d94660a33 13519 #define USB_OBSERVE_DPPU_MASK 0x80u
Jasper_lee 0:b16d94660a33 13520 #define USB_OBSERVE_DPPU_SHIFT 7
Jasper_lee 0:b16d94660a33 13521 /* CONTROL Bit Fields */
Jasper_lee 0:b16d94660a33 13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
Jasper_lee 0:b16d94660a33 13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
Jasper_lee 0:b16d94660a33 13524 /* USBTRC0 Bit Fields */
Jasper_lee 0:b16d94660a33 13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
Jasper_lee 0:b16d94660a33 13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
Jasper_lee 0:b16d94660a33 13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
Jasper_lee 0:b16d94660a33 13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1
Jasper_lee 0:b16d94660a33 13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
Jasper_lee 0:b16d94660a33 13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
Jasper_lee 0:b16d94660a33 13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5
Jasper_lee 0:b16d94660a33 13533 #define USB_USBTRC0_USBRESET_MASK 0x80u
Jasper_lee 0:b16d94660a33 13534 #define USB_USBTRC0_USBRESET_SHIFT 7
Jasper_lee 0:b16d94660a33 13535 /* USBFRMADJUST Bit Fields */
Jasper_lee 0:b16d94660a33 13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
Jasper_lee 0:b16d94660a33 13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0
Jasper_lee 0:b16d94660a33 13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
Jasper_lee 0:b16d94660a33 13539 /* CLK_RECOVER_CTRL Bit Fields */
Jasper_lee 0:b16d94660a33 13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
Jasper_lee 0:b16d94660a33 13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
Jasper_lee 0:b16d94660a33 13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
Jasper_lee 0:b16d94660a33 13546 /* CLK_RECOVER_IRC_EN Bit Fields */
Jasper_lee 0:b16d94660a33 13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
Jasper_lee 0:b16d94660a33 13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
Jasper_lee 0:b16d94660a33 13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
Jasper_lee 0:b16d94660a33 13551 /* CLK_RECOVER_INT_STATUS Bit Fields */
Jasper_lee 0:b16d94660a33 13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
Jasper_lee 0:b16d94660a33 13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
Jasper_lee 0:b16d94660a33 13554
Jasper_lee 0:b16d94660a33 13555 /*!
Jasper_lee 0:b16d94660a33 13556 * @}
Jasper_lee 0:b16d94660a33 13557 */ /* end of group USB_Register_Masks */
Jasper_lee 0:b16d94660a33 13558
Jasper_lee 0:b16d94660a33 13559
Jasper_lee 0:b16d94660a33 13560 /* USB - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 13561 /** Peripheral USB0 base address */
Jasper_lee 0:b16d94660a33 13562 #define USB0_BASE (0x40072000u)
Jasper_lee 0:b16d94660a33 13563 /** Peripheral USB0 base pointer */
Jasper_lee 0:b16d94660a33 13564 #define USB0 ((USB_Type *)USB0_BASE)
Jasper_lee 0:b16d94660a33 13565 #define USB0_BASE_PTR (USB0)
Jasper_lee 0:b16d94660a33 13566 /** Array initializer of USB peripheral base addresses */
Jasper_lee 0:b16d94660a33 13567 #define USB_BASE_ADDRS { USB0_BASE }
Jasper_lee 0:b16d94660a33 13568 /** Array initializer of USB peripheral base pointers */
Jasper_lee 0:b16d94660a33 13569 #define USB_BASE_PTRS { USB0 }
Jasper_lee 0:b16d94660a33 13570 /** Interrupt vectors for the USB peripheral type */
Jasper_lee 0:b16d94660a33 13571 #define USB_IRQS { USB0_IRQn }
Jasper_lee 0:b16d94660a33 13572
Jasper_lee 0:b16d94660a33 13573 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13574 -- USB - Register accessor macros
Jasper_lee 0:b16d94660a33 13575 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13576
Jasper_lee 0:b16d94660a33 13577 /*!
Jasper_lee 0:b16d94660a33 13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Jasper_lee 0:b16d94660a33 13579 * @{
Jasper_lee 0:b16d94660a33 13580 */
Jasper_lee 0:b16d94660a33 13581
Jasper_lee 0:b16d94660a33 13582
Jasper_lee 0:b16d94660a33 13583 /* USB - Register instance definitions */
Jasper_lee 0:b16d94660a33 13584 /* USB0 */
Jasper_lee 0:b16d94660a33 13585 #define USB0_PERID USB_PERID_REG(USB0)
Jasper_lee 0:b16d94660a33 13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
Jasper_lee 0:b16d94660a33 13587 #define USB0_REV USB_REV_REG(USB0)
Jasper_lee 0:b16d94660a33 13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
Jasper_lee 0:b16d94660a33 13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
Jasper_lee 0:b16d94660a33 13590 #define USB0_OTGICR USB_OTGICR_REG(USB0)
Jasper_lee 0:b16d94660a33 13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
Jasper_lee 0:b16d94660a33 13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
Jasper_lee 0:b16d94660a33 13593 #define USB0_ISTAT USB_ISTAT_REG(USB0)
Jasper_lee 0:b16d94660a33 13594 #define USB0_INTEN USB_INTEN_REG(USB0)
Jasper_lee 0:b16d94660a33 13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
Jasper_lee 0:b16d94660a33 13596 #define USB0_ERREN USB_ERREN_REG(USB0)
Jasper_lee 0:b16d94660a33 13597 #define USB0_STAT USB_STAT_REG(USB0)
Jasper_lee 0:b16d94660a33 13598 #define USB0_CTL USB_CTL_REG(USB0)
Jasper_lee 0:b16d94660a33 13599 #define USB0_ADDR USB_ADDR_REG(USB0)
Jasper_lee 0:b16d94660a33 13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
Jasper_lee 0:b16d94660a33 13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
Jasper_lee 0:b16d94660a33 13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
Jasper_lee 0:b16d94660a33 13603 #define USB0_TOKEN USB_TOKEN_REG(USB0)
Jasper_lee 0:b16d94660a33 13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
Jasper_lee 0:b16d94660a33 13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
Jasper_lee 0:b16d94660a33 13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
Jasper_lee 0:b16d94660a33 13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
Jasper_lee 0:b16d94660a33 13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
Jasper_lee 0:b16d94660a33 13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
Jasper_lee 0:b16d94660a33 13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
Jasper_lee 0:b16d94660a33 13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
Jasper_lee 0:b16d94660a33 13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
Jasper_lee 0:b16d94660a33 13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
Jasper_lee 0:b16d94660a33 13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
Jasper_lee 0:b16d94660a33 13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
Jasper_lee 0:b16d94660a33 13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
Jasper_lee 0:b16d94660a33 13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
Jasper_lee 0:b16d94660a33 13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
Jasper_lee 0:b16d94660a33 13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
Jasper_lee 0:b16d94660a33 13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
Jasper_lee 0:b16d94660a33 13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
Jasper_lee 0:b16d94660a33 13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
Jasper_lee 0:b16d94660a33 13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
Jasper_lee 0:b16d94660a33 13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
Jasper_lee 0:b16d94660a33 13625 #define USB0_CONTROL USB_CONTROL_REG(USB0)
Jasper_lee 0:b16d94660a33 13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
Jasper_lee 0:b16d94660a33 13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
Jasper_lee 0:b16d94660a33 13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
Jasper_lee 0:b16d94660a33 13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
Jasper_lee 0:b16d94660a33 13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
Jasper_lee 0:b16d94660a33 13631
Jasper_lee 0:b16d94660a33 13632 /* USB - Register array accessors */
Jasper_lee 0:b16d94660a33 13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
Jasper_lee 0:b16d94660a33 13634
Jasper_lee 0:b16d94660a33 13635 /*!
Jasper_lee 0:b16d94660a33 13636 * @}
Jasper_lee 0:b16d94660a33 13637 */ /* end of group USB_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13638
Jasper_lee 0:b16d94660a33 13639
Jasper_lee 0:b16d94660a33 13640 /*!
Jasper_lee 0:b16d94660a33 13641 * @}
Jasper_lee 0:b16d94660a33 13642 */ /* end of group USB_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 13643
Jasper_lee 0:b16d94660a33 13644
Jasper_lee 0:b16d94660a33 13645 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13646 -- USBDCD Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13647 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13648
Jasper_lee 0:b16d94660a33 13649 /*!
Jasper_lee 0:b16d94660a33 13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13651 * @{
Jasper_lee 0:b16d94660a33 13652 */
Jasper_lee 0:b16d94660a33 13653
Jasper_lee 0:b16d94660a33 13654 /** USBDCD - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 13655 typedef struct {
Jasper_lee 0:b16d94660a33 13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
Jasper_lee 0:b16d94660a33 13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
Jasper_lee 0:b16d94660a33 13659 uint8_t RESERVED_0[4];
Jasper_lee 0:b16d94660a33 13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
Jasper_lee 0:b16d94660a33 13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 13662 union { /* offset: 0x18 */
Jasper_lee 0:b16d94660a33 13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
Jasper_lee 0:b16d94660a33 13665 };
Jasper_lee 0:b16d94660a33 13666 } USBDCD_Type, *USBDCD_MemMapPtr;
Jasper_lee 0:b16d94660a33 13667
Jasper_lee 0:b16d94660a33 13668 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13669 -- USBDCD - Register accessor macros
Jasper_lee 0:b16d94660a33 13670 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13671
Jasper_lee 0:b16d94660a33 13672 /*!
Jasper_lee 0:b16d94660a33 13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
Jasper_lee 0:b16d94660a33 13674 * @{
Jasper_lee 0:b16d94660a33 13675 */
Jasper_lee 0:b16d94660a33 13676
Jasper_lee 0:b16d94660a33 13677
Jasper_lee 0:b16d94660a33 13678 /* USBDCD - Register accessors */
Jasper_lee 0:b16d94660a33 13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
Jasper_lee 0:b16d94660a33 13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
Jasper_lee 0:b16d94660a33 13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
Jasper_lee 0:b16d94660a33 13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
Jasper_lee 0:b16d94660a33 13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
Jasper_lee 0:b16d94660a33 13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
Jasper_lee 0:b16d94660a33 13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
Jasper_lee 0:b16d94660a33 13686
Jasper_lee 0:b16d94660a33 13687 /*!
Jasper_lee 0:b16d94660a33 13688 * @}
Jasper_lee 0:b16d94660a33 13689 */ /* end of group USBDCD_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13690
Jasper_lee 0:b16d94660a33 13691
Jasper_lee 0:b16d94660a33 13692 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13693 -- USBDCD Register Masks
Jasper_lee 0:b16d94660a33 13694 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13695
Jasper_lee 0:b16d94660a33 13696 /*!
Jasper_lee 0:b16d94660a33 13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
Jasper_lee 0:b16d94660a33 13698 * @{
Jasper_lee 0:b16d94660a33 13699 */
Jasper_lee 0:b16d94660a33 13700
Jasper_lee 0:b16d94660a33 13701 /* CONTROL Bit Fields */
Jasper_lee 0:b16d94660a33 13702 #define USBDCD_CONTROL_IACK_MASK 0x1u
Jasper_lee 0:b16d94660a33 13703 #define USBDCD_CONTROL_IACK_SHIFT 0
Jasper_lee 0:b16d94660a33 13704 #define USBDCD_CONTROL_IF_MASK 0x100u
Jasper_lee 0:b16d94660a33 13705 #define USBDCD_CONTROL_IF_SHIFT 8
Jasper_lee 0:b16d94660a33 13706 #define USBDCD_CONTROL_IE_MASK 0x10000u
Jasper_lee 0:b16d94660a33 13707 #define USBDCD_CONTROL_IE_SHIFT 16
Jasper_lee 0:b16d94660a33 13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u
Jasper_lee 0:b16d94660a33 13709 #define USBDCD_CONTROL_BC12_SHIFT 17
Jasper_lee 0:b16d94660a33 13710 #define USBDCD_CONTROL_START_MASK 0x1000000u
Jasper_lee 0:b16d94660a33 13711 #define USBDCD_CONTROL_START_SHIFT 24
Jasper_lee 0:b16d94660a33 13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u
Jasper_lee 0:b16d94660a33 13713 #define USBDCD_CONTROL_SR_SHIFT 25
Jasper_lee 0:b16d94660a33 13714 /* CLOCK Bit Fields */
Jasper_lee 0:b16d94660a33 13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
Jasper_lee 0:b16d94660a33 13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
Jasper_lee 0:b16d94660a33 13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
Jasper_lee 0:b16d94660a33 13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
Jasper_lee 0:b16d94660a33 13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
Jasper_lee 0:b16d94660a33 13720 /* STATUS Bit Fields */
Jasper_lee 0:b16d94660a33 13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
Jasper_lee 0:b16d94660a33 13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
Jasper_lee 0:b16d94660a33 13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
Jasper_lee 0:b16d94660a33 13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
Jasper_lee 0:b16d94660a33 13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
Jasper_lee 0:b16d94660a33 13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
Jasper_lee 0:b16d94660a33 13727 #define USBDCD_STATUS_ERR_MASK 0x100000u
Jasper_lee 0:b16d94660a33 13728 #define USBDCD_STATUS_ERR_SHIFT 20
Jasper_lee 0:b16d94660a33 13729 #define USBDCD_STATUS_TO_MASK 0x200000u
Jasper_lee 0:b16d94660a33 13730 #define USBDCD_STATUS_TO_SHIFT 21
Jasper_lee 0:b16d94660a33 13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
Jasper_lee 0:b16d94660a33 13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22
Jasper_lee 0:b16d94660a33 13733 /* TIMER0 Bit Fields */
Jasper_lee 0:b16d94660a33 13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
Jasper_lee 0:b16d94660a33 13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
Jasper_lee 0:b16d94660a33 13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
Jasper_lee 0:b16d94660a33 13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
Jasper_lee 0:b16d94660a33 13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
Jasper_lee 0:b16d94660a33 13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
Jasper_lee 0:b16d94660a33 13740 /* TIMER1 Bit Fields */
Jasper_lee 0:b16d94660a33 13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
Jasper_lee 0:b16d94660a33 13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
Jasper_lee 0:b16d94660a33 13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
Jasper_lee 0:b16d94660a33 13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
Jasper_lee 0:b16d94660a33 13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
Jasper_lee 0:b16d94660a33 13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
Jasper_lee 0:b16d94660a33 13747 /* TIMER2_BC11 Bit Fields */
Jasper_lee 0:b16d94660a33 13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
Jasper_lee 0:b16d94660a33 13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
Jasper_lee 0:b16d94660a33 13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
Jasper_lee 0:b16d94660a33 13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
Jasper_lee 0:b16d94660a33 13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
Jasper_lee 0:b16d94660a33 13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
Jasper_lee 0:b16d94660a33 13754 /* TIMER2_BC12 Bit Fields */
Jasper_lee 0:b16d94660a33 13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
Jasper_lee 0:b16d94660a33 13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
Jasper_lee 0:b16d94660a33 13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
Jasper_lee 0:b16d94660a33 13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
Jasper_lee 0:b16d94660a33 13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
Jasper_lee 0:b16d94660a33 13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
Jasper_lee 0:b16d94660a33 13761
Jasper_lee 0:b16d94660a33 13762 /*!
Jasper_lee 0:b16d94660a33 13763 * @}
Jasper_lee 0:b16d94660a33 13764 */ /* end of group USBDCD_Register_Masks */
Jasper_lee 0:b16d94660a33 13765
Jasper_lee 0:b16d94660a33 13766
Jasper_lee 0:b16d94660a33 13767 /* USBDCD - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 13768 /** Peripheral USBDCD base address */
Jasper_lee 0:b16d94660a33 13769 #define USBDCD_BASE (0x40035000u)
Jasper_lee 0:b16d94660a33 13770 /** Peripheral USBDCD base pointer */
Jasper_lee 0:b16d94660a33 13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
Jasper_lee 0:b16d94660a33 13772 #define USBDCD_BASE_PTR (USBDCD)
Jasper_lee 0:b16d94660a33 13773 /** Array initializer of USBDCD peripheral base addresses */
Jasper_lee 0:b16d94660a33 13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
Jasper_lee 0:b16d94660a33 13775 /** Array initializer of USBDCD peripheral base pointers */
Jasper_lee 0:b16d94660a33 13776 #define USBDCD_BASE_PTRS { USBDCD }
Jasper_lee 0:b16d94660a33 13777 /** Interrupt vectors for the USBDCD peripheral type */
Jasper_lee 0:b16d94660a33 13778 #define USBDCD_IRQS { USBDCD_IRQn }
Jasper_lee 0:b16d94660a33 13779
Jasper_lee 0:b16d94660a33 13780 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13781 -- USBDCD - Register accessor macros
Jasper_lee 0:b16d94660a33 13782 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13783
Jasper_lee 0:b16d94660a33 13784 /*!
Jasper_lee 0:b16d94660a33 13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
Jasper_lee 0:b16d94660a33 13786 * @{
Jasper_lee 0:b16d94660a33 13787 */
Jasper_lee 0:b16d94660a33 13788
Jasper_lee 0:b16d94660a33 13789
Jasper_lee 0:b16d94660a33 13790 /* USBDCD - Register instance definitions */
Jasper_lee 0:b16d94660a33 13791 /* USBDCD */
Jasper_lee 0:b16d94660a33 13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
Jasper_lee 0:b16d94660a33 13799
Jasper_lee 0:b16d94660a33 13800 /*!
Jasper_lee 0:b16d94660a33 13801 * @}
Jasper_lee 0:b16d94660a33 13802 */ /* end of group USBDCD_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13803
Jasper_lee 0:b16d94660a33 13804
Jasper_lee 0:b16d94660a33 13805 /*!
Jasper_lee 0:b16d94660a33 13806 * @}
Jasper_lee 0:b16d94660a33 13807 */ /* end of group USBDCD_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 13808
Jasper_lee 0:b16d94660a33 13809
Jasper_lee 0:b16d94660a33 13810 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13811 -- VREF Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13812 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13813
Jasper_lee 0:b16d94660a33 13814 /*!
Jasper_lee 0:b16d94660a33 13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13816 * @{
Jasper_lee 0:b16d94660a33 13817 */
Jasper_lee 0:b16d94660a33 13818
Jasper_lee 0:b16d94660a33 13819 /** VREF - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 13820 typedef struct {
Jasper_lee 0:b16d94660a33 13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
Jasper_lee 0:b16d94660a33 13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
Jasper_lee 0:b16d94660a33 13823 } VREF_Type, *VREF_MemMapPtr;
Jasper_lee 0:b16d94660a33 13824
Jasper_lee 0:b16d94660a33 13825 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13826 -- VREF - Register accessor macros
Jasper_lee 0:b16d94660a33 13827 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13828
Jasper_lee 0:b16d94660a33 13829 /*!
Jasper_lee 0:b16d94660a33 13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Jasper_lee 0:b16d94660a33 13831 * @{
Jasper_lee 0:b16d94660a33 13832 */
Jasper_lee 0:b16d94660a33 13833
Jasper_lee 0:b16d94660a33 13834
Jasper_lee 0:b16d94660a33 13835 /* VREF - Register accessors */
Jasper_lee 0:b16d94660a33 13836 #define VREF_TRM_REG(base) ((base)->TRM)
Jasper_lee 0:b16d94660a33 13837 #define VREF_SC_REG(base) ((base)->SC)
Jasper_lee 0:b16d94660a33 13838
Jasper_lee 0:b16d94660a33 13839 /*!
Jasper_lee 0:b16d94660a33 13840 * @}
Jasper_lee 0:b16d94660a33 13841 */ /* end of group VREF_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13842
Jasper_lee 0:b16d94660a33 13843
Jasper_lee 0:b16d94660a33 13844 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13845 -- VREF Register Masks
Jasper_lee 0:b16d94660a33 13846 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13847
Jasper_lee 0:b16d94660a33 13848 /*!
Jasper_lee 0:b16d94660a33 13849 * @addtogroup VREF_Register_Masks VREF Register Masks
Jasper_lee 0:b16d94660a33 13850 * @{
Jasper_lee 0:b16d94660a33 13851 */
Jasper_lee 0:b16d94660a33 13852
Jasper_lee 0:b16d94660a33 13853 /* TRM Bit Fields */
Jasper_lee 0:b16d94660a33 13854 #define VREF_TRM_TRIM_MASK 0x3Fu
Jasper_lee 0:b16d94660a33 13855 #define VREF_TRM_TRIM_SHIFT 0
Jasper_lee 0:b16d94660a33 13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
Jasper_lee 0:b16d94660a33 13857 #define VREF_TRM_CHOPEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13858 #define VREF_TRM_CHOPEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13859 /* SC Bit Fields */
Jasper_lee 0:b16d94660a33 13860 #define VREF_SC_MODE_LV_MASK 0x3u
Jasper_lee 0:b16d94660a33 13861 #define VREF_SC_MODE_LV_SHIFT 0
Jasper_lee 0:b16d94660a33 13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
Jasper_lee 0:b16d94660a33 13863 #define VREF_SC_VREFST_MASK 0x4u
Jasper_lee 0:b16d94660a33 13864 #define VREF_SC_VREFST_SHIFT 2
Jasper_lee 0:b16d94660a33 13865 #define VREF_SC_ICOMPEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13866 #define VREF_SC_ICOMPEN_SHIFT 5
Jasper_lee 0:b16d94660a33 13867 #define VREF_SC_REGEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13868 #define VREF_SC_REGEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13869 #define VREF_SC_VREFEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13870 #define VREF_SC_VREFEN_SHIFT 7
Jasper_lee 0:b16d94660a33 13871
Jasper_lee 0:b16d94660a33 13872 /*!
Jasper_lee 0:b16d94660a33 13873 * @}
Jasper_lee 0:b16d94660a33 13874 */ /* end of group VREF_Register_Masks */
Jasper_lee 0:b16d94660a33 13875
Jasper_lee 0:b16d94660a33 13876
Jasper_lee 0:b16d94660a33 13877 /* VREF - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 13878 /** Peripheral VREF base address */
Jasper_lee 0:b16d94660a33 13879 #define VREF_BASE (0x40074000u)
Jasper_lee 0:b16d94660a33 13880 /** Peripheral VREF base pointer */
Jasper_lee 0:b16d94660a33 13881 #define VREF ((VREF_Type *)VREF_BASE)
Jasper_lee 0:b16d94660a33 13882 #define VREF_BASE_PTR (VREF)
Jasper_lee 0:b16d94660a33 13883 /** Array initializer of VREF peripheral base addresses */
Jasper_lee 0:b16d94660a33 13884 #define VREF_BASE_ADDRS { VREF_BASE }
Jasper_lee 0:b16d94660a33 13885 /** Array initializer of VREF peripheral base pointers */
Jasper_lee 0:b16d94660a33 13886 #define VREF_BASE_PTRS { VREF }
Jasper_lee 0:b16d94660a33 13887
Jasper_lee 0:b16d94660a33 13888 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13889 -- VREF - Register accessor macros
Jasper_lee 0:b16d94660a33 13890 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13891
Jasper_lee 0:b16d94660a33 13892 /*!
Jasper_lee 0:b16d94660a33 13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Jasper_lee 0:b16d94660a33 13894 * @{
Jasper_lee 0:b16d94660a33 13895 */
Jasper_lee 0:b16d94660a33 13896
Jasper_lee 0:b16d94660a33 13897
Jasper_lee 0:b16d94660a33 13898 /* VREF - Register instance definitions */
Jasper_lee 0:b16d94660a33 13899 /* VREF */
Jasper_lee 0:b16d94660a33 13900 #define VREF_TRM VREF_TRM_REG(VREF)
Jasper_lee 0:b16d94660a33 13901 #define VREF_SC VREF_SC_REG(VREF)
Jasper_lee 0:b16d94660a33 13902
Jasper_lee 0:b16d94660a33 13903 /*!
Jasper_lee 0:b16d94660a33 13904 * @}
Jasper_lee 0:b16d94660a33 13905 */ /* end of group VREF_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13906
Jasper_lee 0:b16d94660a33 13907
Jasper_lee 0:b16d94660a33 13908 /*!
Jasper_lee 0:b16d94660a33 13909 * @}
Jasper_lee 0:b16d94660a33 13910 */ /* end of group VREF_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 13911
Jasper_lee 0:b16d94660a33 13912
Jasper_lee 0:b16d94660a33 13913 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13914 -- WDOG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13915 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13916
Jasper_lee 0:b16d94660a33 13917 /*!
Jasper_lee 0:b16d94660a33 13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
Jasper_lee 0:b16d94660a33 13919 * @{
Jasper_lee 0:b16d94660a33 13920 */
Jasper_lee 0:b16d94660a33 13921
Jasper_lee 0:b16d94660a33 13922 /** WDOG - Register Layout Typedef */
Jasper_lee 0:b16d94660a33 13923 typedef struct {
Jasper_lee 0:b16d94660a33 13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
Jasper_lee 0:b16d94660a33 13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
Jasper_lee 0:b16d94660a33 13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
Jasper_lee 0:b16d94660a33 13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
Jasper_lee 0:b16d94660a33 13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
Jasper_lee 0:b16d94660a33 13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
Jasper_lee 0:b16d94660a33 13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
Jasper_lee 0:b16d94660a33 13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
Jasper_lee 0:b16d94660a33 13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
Jasper_lee 0:b16d94660a33 13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
Jasper_lee 0:b16d94660a33 13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
Jasper_lee 0:b16d94660a33 13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
Jasper_lee 0:b16d94660a33 13936 } WDOG_Type, *WDOG_MemMapPtr;
Jasper_lee 0:b16d94660a33 13937
Jasper_lee 0:b16d94660a33 13938 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13939 -- WDOG - Register accessor macros
Jasper_lee 0:b16d94660a33 13940 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13941
Jasper_lee 0:b16d94660a33 13942 /*!
Jasper_lee 0:b16d94660a33 13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
Jasper_lee 0:b16d94660a33 13944 * @{
Jasper_lee 0:b16d94660a33 13945 */
Jasper_lee 0:b16d94660a33 13946
Jasper_lee 0:b16d94660a33 13947
Jasper_lee 0:b16d94660a33 13948 /* WDOG - Register accessors */
Jasper_lee 0:b16d94660a33 13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
Jasper_lee 0:b16d94660a33 13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
Jasper_lee 0:b16d94660a33 13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
Jasper_lee 0:b16d94660a33 13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
Jasper_lee 0:b16d94660a33 13953 #define WDOG_WINH_REG(base) ((base)->WINH)
Jasper_lee 0:b16d94660a33 13954 #define WDOG_WINL_REG(base) ((base)->WINL)
Jasper_lee 0:b16d94660a33 13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
Jasper_lee 0:b16d94660a33 13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
Jasper_lee 0:b16d94660a33 13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
Jasper_lee 0:b16d94660a33 13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
Jasper_lee 0:b16d94660a33 13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
Jasper_lee 0:b16d94660a33 13960 #define WDOG_PRESC_REG(base) ((base)->PRESC)
Jasper_lee 0:b16d94660a33 13961
Jasper_lee 0:b16d94660a33 13962 /*!
Jasper_lee 0:b16d94660a33 13963 * @}
Jasper_lee 0:b16d94660a33 13964 */ /* end of group WDOG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 13965
Jasper_lee 0:b16d94660a33 13966
Jasper_lee 0:b16d94660a33 13967 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 13968 -- WDOG Register Masks
Jasper_lee 0:b16d94660a33 13969 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 13970
Jasper_lee 0:b16d94660a33 13971 /*!
Jasper_lee 0:b16d94660a33 13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks
Jasper_lee 0:b16d94660a33 13973 * @{
Jasper_lee 0:b16d94660a33 13974 */
Jasper_lee 0:b16d94660a33 13975
Jasper_lee 0:b16d94660a33 13976 /* STCTRLH Bit Fields */
Jasper_lee 0:b16d94660a33 13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
Jasper_lee 0:b16d94660a33 13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
Jasper_lee 0:b16d94660a33 13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
Jasper_lee 0:b16d94660a33 13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
Jasper_lee 0:b16d94660a33 13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
Jasper_lee 0:b16d94660a33 13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
Jasper_lee 0:b16d94660a33 13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u
Jasper_lee 0:b16d94660a33 13984 #define WDOG_STCTRLH_WINEN_SHIFT 3
Jasper_lee 0:b16d94660a33 13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
Jasper_lee 0:b16d94660a33 13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
Jasper_lee 0:b16d94660a33 13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
Jasper_lee 0:b16d94660a33 13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5
Jasper_lee 0:b16d94660a33 13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
Jasper_lee 0:b16d94660a33 13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6
Jasper_lee 0:b16d94660a33 13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
Jasper_lee 0:b16d94660a33 13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7
Jasper_lee 0:b16d94660a33 13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
Jasper_lee 0:b16d94660a33 13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
Jasper_lee 0:b16d94660a33 13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
Jasper_lee 0:b16d94660a33 13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
Jasper_lee 0:b16d94660a33 13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
Jasper_lee 0:b16d94660a33 13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
Jasper_lee 0:b16d94660a33 13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
Jasper_lee 0:b16d94660a33 14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
Jasper_lee 0:b16d94660a33 14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
Jasper_lee 0:b16d94660a33 14002 /* STCTRLL Bit Fields */
Jasper_lee 0:b16d94660a33 14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
Jasper_lee 0:b16d94660a33 14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15
Jasper_lee 0:b16d94660a33 14005 /* TOVALH Bit Fields */
Jasper_lee 0:b16d94660a33 14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
Jasper_lee 0:b16d94660a33 14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
Jasper_lee 0:b16d94660a33 14009 /* TOVALL Bit Fields */
Jasper_lee 0:b16d94660a33 14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
Jasper_lee 0:b16d94660a33 14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
Jasper_lee 0:b16d94660a33 14013 /* WINH Bit Fields */
Jasper_lee 0:b16d94660a33 14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14015 #define WDOG_WINH_WINHIGH_SHIFT 0
Jasper_lee 0:b16d94660a33 14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
Jasper_lee 0:b16d94660a33 14017 /* WINL Bit Fields */
Jasper_lee 0:b16d94660a33 14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14019 #define WDOG_WINL_WINLOW_SHIFT 0
Jasper_lee 0:b16d94660a33 14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
Jasper_lee 0:b16d94660a33 14021 /* REFRESH Bit Fields */
Jasper_lee 0:b16d94660a33 14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
Jasper_lee 0:b16d94660a33 14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
Jasper_lee 0:b16d94660a33 14025 /* UNLOCK Bit Fields */
Jasper_lee 0:b16d94660a33 14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
Jasper_lee 0:b16d94660a33 14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
Jasper_lee 0:b16d94660a33 14029 /* TMROUTH Bit Fields */
Jasper_lee 0:b16d94660a33 14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
Jasper_lee 0:b16d94660a33 14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
Jasper_lee 0:b16d94660a33 14033 /* TMROUTL Bit Fields */
Jasper_lee 0:b16d94660a33 14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
Jasper_lee 0:b16d94660a33 14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
Jasper_lee 0:b16d94660a33 14037 /* RSTCNT Bit Fields */
Jasper_lee 0:b16d94660a33 14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
Jasper_lee 0:b16d94660a33 14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
Jasper_lee 0:b16d94660a33 14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
Jasper_lee 0:b16d94660a33 14041 /* PRESC Bit Fields */
Jasper_lee 0:b16d94660a33 14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
Jasper_lee 0:b16d94660a33 14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8
Jasper_lee 0:b16d94660a33 14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
Jasper_lee 0:b16d94660a33 14045
Jasper_lee 0:b16d94660a33 14046 /*!
Jasper_lee 0:b16d94660a33 14047 * @}
Jasper_lee 0:b16d94660a33 14048 */ /* end of group WDOG_Register_Masks */
Jasper_lee 0:b16d94660a33 14049
Jasper_lee 0:b16d94660a33 14050
Jasper_lee 0:b16d94660a33 14051 /* WDOG - Peripheral instance base addresses */
Jasper_lee 0:b16d94660a33 14052 /** Peripheral WDOG base address */
Jasper_lee 0:b16d94660a33 14053 #define WDOG_BASE (0x40052000u)
Jasper_lee 0:b16d94660a33 14054 /** Peripheral WDOG base pointer */
Jasper_lee 0:b16d94660a33 14055 #define WDOG ((WDOG_Type *)WDOG_BASE)
Jasper_lee 0:b16d94660a33 14056 #define WDOG_BASE_PTR (WDOG)
Jasper_lee 0:b16d94660a33 14057 /** Array initializer of WDOG peripheral base addresses */
Jasper_lee 0:b16d94660a33 14058 #define WDOG_BASE_ADDRS { WDOG_BASE }
Jasper_lee 0:b16d94660a33 14059 /** Array initializer of WDOG peripheral base pointers */
Jasper_lee 0:b16d94660a33 14060 #define WDOG_BASE_PTRS { WDOG }
Jasper_lee 0:b16d94660a33 14061 /** Interrupt vectors for the WDOG peripheral type */
Jasper_lee 0:b16d94660a33 14062 #define WDOG_IRQS { Watchdog_IRQn }
Jasper_lee 0:b16d94660a33 14063
Jasper_lee 0:b16d94660a33 14064 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 14065 -- WDOG - Register accessor macros
Jasper_lee 0:b16d94660a33 14066 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 14067
Jasper_lee 0:b16d94660a33 14068 /*!
Jasper_lee 0:b16d94660a33 14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
Jasper_lee 0:b16d94660a33 14070 * @{
Jasper_lee 0:b16d94660a33 14071 */
Jasper_lee 0:b16d94660a33 14072
Jasper_lee 0:b16d94660a33 14073
Jasper_lee 0:b16d94660a33 14074 /* WDOG - Register instance definitions */
Jasper_lee 0:b16d94660a33 14075 /* WDOG */
Jasper_lee 0:b16d94660a33 14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
Jasper_lee 0:b16d94660a33 14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
Jasper_lee 0:b16d94660a33 14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
Jasper_lee 0:b16d94660a33 14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
Jasper_lee 0:b16d94660a33 14080 #define WDOG_WINH WDOG_WINH_REG(WDOG)
Jasper_lee 0:b16d94660a33 14081 #define WDOG_WINL WDOG_WINL_REG(WDOG)
Jasper_lee 0:b16d94660a33 14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
Jasper_lee 0:b16d94660a33 14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
Jasper_lee 0:b16d94660a33 14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
Jasper_lee 0:b16d94660a33 14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
Jasper_lee 0:b16d94660a33 14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
Jasper_lee 0:b16d94660a33 14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
Jasper_lee 0:b16d94660a33 14088
Jasper_lee 0:b16d94660a33 14089 /*!
Jasper_lee 0:b16d94660a33 14090 * @}
Jasper_lee 0:b16d94660a33 14091 */ /* end of group WDOG_Register_Accessor_Macros */
Jasper_lee 0:b16d94660a33 14092
Jasper_lee 0:b16d94660a33 14093
Jasper_lee 0:b16d94660a33 14094 /*!
Jasper_lee 0:b16d94660a33 14095 * @}
Jasper_lee 0:b16d94660a33 14096 */ /* end of group WDOG_Peripheral_Access_Layer */
Jasper_lee 0:b16d94660a33 14097
Jasper_lee 0:b16d94660a33 14098
Jasper_lee 0:b16d94660a33 14099 /*
Jasper_lee 0:b16d94660a33 14100 ** End of section using anonymous unions
Jasper_lee 0:b16d94660a33 14101 */
Jasper_lee 0:b16d94660a33 14102
Jasper_lee 0:b16d94660a33 14103 #if defined(__ARMCC_VERSION)
Jasper_lee 0:b16d94660a33 14104 #pragma pop
Jasper_lee 0:b16d94660a33 14105 #elif defined(__CWCC__)
Jasper_lee 0:b16d94660a33 14106 #pragma pop
Jasper_lee 0:b16d94660a33 14107 #elif defined(__GNUC__)
Jasper_lee 0:b16d94660a33 14108 /* leave anonymous unions enabled */
Jasper_lee 0:b16d94660a33 14109 #elif defined(__IAR_SYSTEMS_ICC__)
Jasper_lee 0:b16d94660a33 14110 #pragma language=default
Jasper_lee 0:b16d94660a33 14111 #else
Jasper_lee 0:b16d94660a33 14112 #error Not supported compiler type
Jasper_lee 0:b16d94660a33 14113 #endif
Jasper_lee 0:b16d94660a33 14114
Jasper_lee 0:b16d94660a33 14115 /*!
Jasper_lee 0:b16d94660a33 14116 * @}
Jasper_lee 0:b16d94660a33 14117 */ /* end of group Peripheral_access_layer */
Jasper_lee 0:b16d94660a33 14118
Jasper_lee 0:b16d94660a33 14119
Jasper_lee 0:b16d94660a33 14120 /* ----------------------------------------------------------------------------
Jasper_lee 0:b16d94660a33 14121 -- Backward Compatibility
Jasper_lee 0:b16d94660a33 14122 ---------------------------------------------------------------------------- */
Jasper_lee 0:b16d94660a33 14123
Jasper_lee 0:b16d94660a33 14124 /*!
Jasper_lee 0:b16d94660a33 14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
Jasper_lee 0:b16d94660a33 14126 * @{
Jasper_lee 0:b16d94660a33 14127 */
Jasper_lee 0:b16d94660a33 14128
Jasper_lee 0:b16d94660a33 14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14130 #define DMA_EARS This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
Jasper_lee 0:b16d94660a33 14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
Jasper_lee 0:b16d94660a33 14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
Jasper_lee 0:b16d94660a33 14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
Jasper_lee 0:b16d94660a33 14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
Jasper_lee 0:b16d94660a33 14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
Jasper_lee 0:b16d94660a33 14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
Jasper_lee 0:b16d94660a33 14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
Jasper_lee 0:b16d94660a33 14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
Jasper_lee 0:b16d94660a33 14181 #define MCG_C9 This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14185 #define MCM_PLACR This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14186 #define ADC_BASES ADC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14187 #define AIPS_BASES AIPS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14188 #define AXBS_BASES AXBS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14189 #define CAN_BASES CAN_BASE_PTRS
Jasper_lee 0:b16d94660a33 14190 #define CAU_BASES CAU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14191 #define CMP_BASES CMP_BASE_PTRS
Jasper_lee 0:b16d94660a33 14192 #define CMT_BASES CMT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14193 #define CRC_BASES CRC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14194 #define DAC_BASES DAC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14195 #define DMA_BASES DMA_BASE_PTRS
Jasper_lee 0:b16d94660a33 14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS
Jasper_lee 0:b16d94660a33 14197 #define ENET_BASES ENET_BASE_PTRS
Jasper_lee 0:b16d94660a33 14198 #define EWM_BASES EWM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14199 #define FB_BASES FB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14200 #define FMC_BASES FMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14201 #define FTFE_BASES FTFE_BASE_PTRS
Jasper_lee 0:b16d94660a33 14202 #define FTM_BASES FTM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14203 #define GPIO_BASES GPIO_BASE_PTRS
Jasper_lee 0:b16d94660a33 14204 #define I2C_BASES I2C_BASE_PTRS
Jasper_lee 0:b16d94660a33 14205 #define I2S_BASES I2S_BASE_PTRS
Jasper_lee 0:b16d94660a33 14206 #define LLWU_BASES LLWU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14207 #define LPTMR_BASES LPTMR_BASE_PTRS
Jasper_lee 0:b16d94660a33 14208 #define MCG_BASES MCG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
Jasper_lee 0:b16d94660a33 14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
Jasper_lee 0:b16d94660a33 14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
Jasper_lee 0:b16d94660a33 14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
Jasper_lee 0:b16d94660a33 14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
Jasper_lee 0:b16d94660a33 14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
Jasper_lee 0:b16d94660a33 14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
Jasper_lee 0:b16d94660a33 14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
Jasper_lee 0:b16d94660a33 14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
Jasper_lee 0:b16d94660a33 14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
Jasper_lee 0:b16d94660a33 14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
Jasper_lee 0:b16d94660a33 14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
Jasper_lee 0:b16d94660a33 14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
Jasper_lee 0:b16d94660a33 14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
Jasper_lee 0:b16d94660a33 14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
Jasper_lee 0:b16d94660a33 14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
Jasper_lee 0:b16d94660a33 14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
Jasper_lee 0:b16d94660a33 14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
Jasper_lee 0:b16d94660a33 14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
Jasper_lee 0:b16d94660a33 14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
Jasper_lee 0:b16d94660a33 14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
Jasper_lee 0:b16d94660a33 14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
Jasper_lee 0:b16d94660a33 14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
Jasper_lee 0:b16d94660a33 14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
Jasper_lee 0:b16d94660a33 14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
Jasper_lee 0:b16d94660a33 14234 #define MCM_BASES MCM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14235 #define MPU_BASES MPU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14236 #define NV_BASES NV_BASE_PTRS
Jasper_lee 0:b16d94660a33 14237 #define OSC_BASES OSC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14238 #define PDB_BASES PDB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14239 #define PIT_BASES PIT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14240 #define PMC_BASES PMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14241 #define PORT_BASES PORT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14242 #define RCM_BASES RCM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14243 #define RFSYS_BASES RFSYS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14245 #define RNG_BASES RNG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14246 #define RTC_BASES RTC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14247 #define SDHC_BASES SDHC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14248 #define SIM_BASES SIM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14249 #define SMC_BASES SMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14250 #define SPI_BASES SPI_BASE_PTRS
Jasper_lee 0:b16d94660a33 14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
Jasper_lee 0:b16d94660a33 14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
Jasper_lee 0:b16d94660a33 14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
Jasper_lee 0:b16d94660a33 14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
Jasper_lee 0:b16d94660a33 14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
Jasper_lee 0:b16d94660a33 14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
Jasper_lee 0:b16d94660a33 14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
Jasper_lee 0:b16d94660a33 14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
Jasper_lee 0:b16d94660a33 14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
Jasper_lee 0:b16d94660a33 14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
Jasper_lee 0:b16d94660a33 14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
Jasper_lee 0:b16d94660a33 14262 #define UART_BASES UART_BASE_PTRS
Jasper_lee 0:b16d94660a33 14263 #define USB_BASES USB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14264 #define USBDCD_BASES USBDCD_BASE_PTRS
Jasper_lee 0:b16d94660a33 14265 #define VREF_BASES VREF_BASE_PTRS
Jasper_lee 0:b16d94660a33 14266 #define WDOG_BASES WDOG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14268 #define DMA_EARS This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
Jasper_lee 0:b16d94660a33 14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
Jasper_lee 0:b16d94660a33 14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
Jasper_lee 0:b16d94660a33 14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
Jasper_lee 0:b16d94660a33 14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
Jasper_lee 0:b16d94660a33 14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
Jasper_lee 0:b16d94660a33 14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
Jasper_lee 0:b16d94660a33 14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
Jasper_lee 0:b16d94660a33 14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
Jasper_lee 0:b16d94660a33 14319 #define MCG_C9 This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14323 #define MCM_PLACR This_symbol_has_been_deprecated
Jasper_lee 0:b16d94660a33 14324 #define ADC_BASES ADC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14325 #define AIPS_BASES AIPS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14326 #define AXBS_BASES AXBS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14327 #define CAN_BASES CAN_BASE_PTRS
Jasper_lee 0:b16d94660a33 14328 #define CAU_BASES CAU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14329 #define CMP_BASES CMP_BASE_PTRS
Jasper_lee 0:b16d94660a33 14330 #define CMT_BASES CMT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14331 #define CRC_BASES CRC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14332 #define DAC_BASES DAC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14333 #define DMA_BASES DMA_BASE_PTRS
Jasper_lee 0:b16d94660a33 14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS
Jasper_lee 0:b16d94660a33 14335 #define ENET_BASES ENET_BASE_PTRS
Jasper_lee 0:b16d94660a33 14336 #define EWM_BASES EWM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14337 #define FB_BASES FB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14338 #define FMC_BASES FMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14339 #define FTFE_BASES FTFE_BASE_PTRS
Jasper_lee 0:b16d94660a33 14340 #define FTM_BASES FTM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14341 #define GPIO_BASES GPIO_BASE_PTRS
Jasper_lee 0:b16d94660a33 14342 #define I2C_BASES I2C_BASE_PTRS
Jasper_lee 0:b16d94660a33 14343 #define I2S_BASES I2S_BASE_PTRS
Jasper_lee 0:b16d94660a33 14344 #define LLWU_BASES LLWU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14345 #define LPTMR_BASES LPTMR_BASE_PTRS
Jasper_lee 0:b16d94660a33 14346 #define MCG_BASES MCG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
Jasper_lee 0:b16d94660a33 14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
Jasper_lee 0:b16d94660a33 14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
Jasper_lee 0:b16d94660a33 14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
Jasper_lee 0:b16d94660a33 14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
Jasper_lee 0:b16d94660a33 14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
Jasper_lee 0:b16d94660a33 14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
Jasper_lee 0:b16d94660a33 14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
Jasper_lee 0:b16d94660a33 14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
Jasper_lee 0:b16d94660a33 14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
Jasper_lee 0:b16d94660a33 14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
Jasper_lee 0:b16d94660a33 14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
Jasper_lee 0:b16d94660a33 14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
Jasper_lee 0:b16d94660a33 14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
Jasper_lee 0:b16d94660a33 14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
Jasper_lee 0:b16d94660a33 14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
Jasper_lee 0:b16d94660a33 14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
Jasper_lee 0:b16d94660a33 14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
Jasper_lee 0:b16d94660a33 14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
Jasper_lee 0:b16d94660a33 14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
Jasper_lee 0:b16d94660a33 14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
Jasper_lee 0:b16d94660a33 14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
Jasper_lee 0:b16d94660a33 14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
Jasper_lee 0:b16d94660a33 14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
Jasper_lee 0:b16d94660a33 14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
Jasper_lee 0:b16d94660a33 14372 #define MCM_BASES MCM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14373 #define MPU_BASES MPU_BASE_PTRS
Jasper_lee 0:b16d94660a33 14374 #define NV_BASES NV_BASE_PTRS
Jasper_lee 0:b16d94660a33 14375 #define OSC_BASES OSC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14376 #define PDB_BASES PDB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14377 #define PIT_BASES PIT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14378 #define PMC_BASES PMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14379 #define PORT_BASES PORT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14380 #define RCM_BASES RCM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14381 #define RFSYS_BASES RFSYS_BASE_PTRS
Jasper_lee 0:b16d94660a33 14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS
Jasper_lee 0:b16d94660a33 14383 #define RNG_BASES RNG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14384 #define RTC_BASES RTC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14385 #define SDHC_BASES SDHC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14386 #define SIM_BASES SIM_BASE_PTRS
Jasper_lee 0:b16d94660a33 14387 #define SMC_BASES SMC_BASE_PTRS
Jasper_lee 0:b16d94660a33 14388 #define SPI_BASES SPI_BASE_PTRS
Jasper_lee 0:b16d94660a33 14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
Jasper_lee 0:b16d94660a33 14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
Jasper_lee 0:b16d94660a33 14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
Jasper_lee 0:b16d94660a33 14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
Jasper_lee 0:b16d94660a33 14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
Jasper_lee 0:b16d94660a33 14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
Jasper_lee 0:b16d94660a33 14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
Jasper_lee 0:b16d94660a33 14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
Jasper_lee 0:b16d94660a33 14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
Jasper_lee 0:b16d94660a33 14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
Jasper_lee 0:b16d94660a33 14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
Jasper_lee 0:b16d94660a33 14400 #define UART_BASES UART_BASE_PTRS
Jasper_lee 0:b16d94660a33 14401 #define USB_BASES USB_BASE_PTRS
Jasper_lee 0:b16d94660a33 14402 #define USBDCD_BASES USBDCD_BASE_PTRS
Jasper_lee 0:b16d94660a33 14403 #define VREF_BASES VREF_BASE_PTRS
Jasper_lee 0:b16d94660a33 14404 #define WDOG_BASES WDOG_BASE_PTRS
Jasper_lee 0:b16d94660a33 14405
Jasper_lee 0:b16d94660a33 14406 /*!
Jasper_lee 0:b16d94660a33 14407 * @}
Jasper_lee 0:b16d94660a33 14408 */ /* end of group Backward_Compatibility_Symbols */
Jasper_lee 0:b16d94660a33 14409
Jasper_lee 0:b16d94660a33 14410
Jasper_lee 0:b16d94660a33 14411 #else /* #if !defined(MK64F12_H_) */
Jasper_lee 0:b16d94660a33 14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
Jasper_lee 0:b16d94660a33 14413 #if (MCU_MEM_MAP_VERSION != 0x0200u)
Jasper_lee 0:b16d94660a33 14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
Jasper_lee 0:b16d94660a33 14415 #warning There are included two not compatible versions of memory maps. Please check possible differences.
Jasper_lee 0:b16d94660a33 14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
Jasper_lee 0:b16d94660a33 14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
Jasper_lee 0:b16d94660a33 14418 #endif /* #if !defined(MK64F12_H_) */
Jasper_lee 0:b16d94660a33 14419
Jasper_lee 0:b16d94660a33 14420 /* MK64F12.h, eof. */