Jasper Lee / mbed_helloworld

change some io settings for TWR-K22F-120M

Dependents:   twr_helloworld

TARGET_K22F/system_MK22F51212.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:
Jasper_lee
Date:
Tue Dec 23 03:35:08 2014 +0000
Revision:
0:b16d94660a33
change some io setting used in TWR-K22F120M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jasper_lee 0:b16d94660a33 1 /*
Jasper_lee 0:b16d94660a33 2 ** ###################################################################
Jasper_lee 0:b16d94660a33 3 ** Compilers: Keil ARM C/C++ Compiler
Jasper_lee 0:b16d94660a33 4 ** Freescale C/C++ for Embedded ARM
Jasper_lee 0:b16d94660a33 5 ** GNU C Compiler
Jasper_lee 0:b16d94660a33 6 ** GNU C Compiler - CodeSourcery Sourcery G++
Jasper_lee 0:b16d94660a33 7 ** IAR ANSI C/C++ Compiler for ARM
Jasper_lee 0:b16d94660a33 8 **
Jasper_lee 0:b16d94660a33 9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
Jasper_lee 0:b16d94660a33 10 ** Version: rev. 2.5, 2014-05-06
Jasper_lee 0:b16d94660a33 11 ** Build: b140611
Jasper_lee 0:b16d94660a33 12 **
Jasper_lee 0:b16d94660a33 13 ** Abstract:
Jasper_lee 0:b16d94660a33 14 ** Provides a system configuration function and a global variable that
Jasper_lee 0:b16d94660a33 15 ** contains the system frequency. It configures the device and initializes
Jasper_lee 0:b16d94660a33 16 ** the oscillator (PLL) that is part of the microcontroller device.
Jasper_lee 0:b16d94660a33 17 **
Jasper_lee 0:b16d94660a33 18 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
Jasper_lee 0:b16d94660a33 19 ** All rights reserved.
Jasper_lee 0:b16d94660a33 20 **
Jasper_lee 0:b16d94660a33 21 ** Redistribution and use in source and binary forms, with or without modification,
Jasper_lee 0:b16d94660a33 22 ** are permitted provided that the following conditions are met:
Jasper_lee 0:b16d94660a33 23 **
Jasper_lee 0:b16d94660a33 24 ** o Redistributions of source code must retain the above copyright notice, this list
Jasper_lee 0:b16d94660a33 25 ** of conditions and the following disclaimer.
Jasper_lee 0:b16d94660a33 26 **
Jasper_lee 0:b16d94660a33 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
Jasper_lee 0:b16d94660a33 28 ** list of conditions and the following disclaimer in the documentation and/or
Jasper_lee 0:b16d94660a33 29 ** other materials provided with the distribution.
Jasper_lee 0:b16d94660a33 30 **
Jasper_lee 0:b16d94660a33 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Jasper_lee 0:b16d94660a33 32 ** contributors may be used to endorse or promote products derived from this
Jasper_lee 0:b16d94660a33 33 ** software without specific prior written permission.
Jasper_lee 0:b16d94660a33 34 **
Jasper_lee 0:b16d94660a33 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Jasper_lee 0:b16d94660a33 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Jasper_lee 0:b16d94660a33 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jasper_lee 0:b16d94660a33 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Jasper_lee 0:b16d94660a33 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Jasper_lee 0:b16d94660a33 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Jasper_lee 0:b16d94660a33 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Jasper_lee 0:b16d94660a33 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Jasper_lee 0:b16d94660a33 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Jasper_lee 0:b16d94660a33 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jasper_lee 0:b16d94660a33 45 **
Jasper_lee 0:b16d94660a33 46 ** http: www.freescale.com
Jasper_lee 0:b16d94660a33 47 ** mail: support@freescale.com
Jasper_lee 0:b16d94660a33 48 **
Jasper_lee 0:b16d94660a33 49 ** Revisions:
Jasper_lee 0:b16d94660a33 50 ** - rev. 1.0 (2013-07-23)
Jasper_lee 0:b16d94660a33 51 ** Initial version.
Jasper_lee 0:b16d94660a33 52 ** - rev. 1.1 (2013-09-17)
Jasper_lee 0:b16d94660a33 53 ** RM rev. 0.4 update.
Jasper_lee 0:b16d94660a33 54 ** - rev. 2.0 (2013-10-29)
Jasper_lee 0:b16d94660a33 55 ** Register accessor macros added to the memory map.
Jasper_lee 0:b16d94660a33 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
Jasper_lee 0:b16d94660a33 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
Jasper_lee 0:b16d94660a33 58 ** System initialization updated.
Jasper_lee 0:b16d94660a33 59 ** - rev. 2.1 (2013-10-30)
Jasper_lee 0:b16d94660a33 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
Jasper_lee 0:b16d94660a33 61 ** - rev. 2.2 (2013-12-20)
Jasper_lee 0:b16d94660a33 62 ** Update according to reference manual rev. 0.6,
Jasper_lee 0:b16d94660a33 63 ** - rev. 2.3 (2014-01-13)
Jasper_lee 0:b16d94660a33 64 ** Update according to reference manual rev. 0.61,
Jasper_lee 0:b16d94660a33 65 ** - rev. 2.4 (2014-02-10)
Jasper_lee 0:b16d94660a33 66 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
Jasper_lee 0:b16d94660a33 67 ** - rev. 2.5 (2014-05-06)
Jasper_lee 0:b16d94660a33 68 ** Update according to reference manual rev. 1.0,
Jasper_lee 0:b16d94660a33 69 ** Update of system and startup files.
Jasper_lee 0:b16d94660a33 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
Jasper_lee 0:b16d94660a33 71 **
Jasper_lee 0:b16d94660a33 72 ** ###################################################################
Jasper_lee 0:b16d94660a33 73 */
Jasper_lee 0:b16d94660a33 74
Jasper_lee 0:b16d94660a33 75 /*!
Jasper_lee 0:b16d94660a33 76 * @file MK22F51212
Jasper_lee 0:b16d94660a33 77 * @version 2.5
Jasper_lee 0:b16d94660a33 78 * @date 2014-05-06
Jasper_lee 0:b16d94660a33 79 * @brief Device specific configuration file for MK22F51212 (header file)
Jasper_lee 0:b16d94660a33 80 *
Jasper_lee 0:b16d94660a33 81 * Provides a system configuration function and a global variable that contains
Jasper_lee 0:b16d94660a33 82 * the system frequency. It configures the device and initializes the oscillator
Jasper_lee 0:b16d94660a33 83 * (PLL) that is part of the microcontroller device.
Jasper_lee 0:b16d94660a33 84 */
Jasper_lee 0:b16d94660a33 85
Jasper_lee 0:b16d94660a33 86 #ifndef SYSTEM_MK22F51212_H_
Jasper_lee 0:b16d94660a33 87 #define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
Jasper_lee 0:b16d94660a33 88
Jasper_lee 0:b16d94660a33 89 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 90 extern "C" {
Jasper_lee 0:b16d94660a33 91 #endif
Jasper_lee 0:b16d94660a33 92
Jasper_lee 0:b16d94660a33 93 #include <stdint.h>
Jasper_lee 0:b16d94660a33 94
Jasper_lee 0:b16d94660a33 95
Jasper_lee 0:b16d94660a33 96 #define DISABLE_WDOG 1
Jasper_lee 0:b16d94660a33 97
Jasper_lee 0:b16d94660a33 98 #ifndef CLOCK_SETUP
Jasper_lee 0:b16d94660a33 99 #define CLOCK_SETUP 4
Jasper_lee 0:b16d94660a33 100 #endif
Jasper_lee 0:b16d94660a33 101
Jasper_lee 0:b16d94660a33 102 /* MCG mode constants */
Jasper_lee 0:b16d94660a33 103
Jasper_lee 0:b16d94660a33 104 #define MCG_MODE_FEI 0U
Jasper_lee 0:b16d94660a33 105 #define MCG_MODE_FBI 1U
Jasper_lee 0:b16d94660a33 106 #define MCG_MODE_BLPI 2U
Jasper_lee 0:b16d94660a33 107 #define MCG_MODE_FEE 3U
Jasper_lee 0:b16d94660a33 108 #define MCG_MODE_FBE 4U
Jasper_lee 0:b16d94660a33 109 #define MCG_MODE_BLPE 5U
Jasper_lee 0:b16d94660a33 110 #define MCG_MODE_PBE 6U
Jasper_lee 0:b16d94660a33 111 #define MCG_MODE_PEE 7U
Jasper_lee 0:b16d94660a33 112
Jasper_lee 0:b16d94660a33 113 /* Predefined clock setups
Jasper_lee 0:b16d94660a33 114 0 ... Default part configuration
Jasper_lee 0:b16d94660a33 115 Multipurpose Clock Generator (MCG) in FEI mode.
Jasper_lee 0:b16d94660a33 116 Reference clock source for MCG module: Slow internal reference clock
Jasper_lee 0:b16d94660a33 117 Core clock = 20.97152MHz
Jasper_lee 0:b16d94660a33 118 Bus clock = 20.97152MHz
Jasper_lee 0:b16d94660a33 119 1 ... Maximum achievable clock frequency configuration
Jasper_lee 0:b16d94660a33 120 Multipurpose Clock Generator (MCG) in PEE mode.
Jasper_lee 0:b16d94660a33 121 Reference clock source for MCG module: System oscillator 0 reference clock
Jasper_lee 0:b16d94660a33 122 Core clock = 120MHz
Jasper_lee 0:b16d94660a33 123 Bus clock = 60MHz
Jasper_lee 0:b16d94660a33 124 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
Jasper_lee 0:b16d94660a33 125 Multipurpose Clock Generator (MCG) in BLPI mode.
Jasper_lee 0:b16d94660a33 126 Reference clock source for MCG module: Fast internal reference clock
Jasper_lee 0:b16d94660a33 127 Core clock = 4MHz
Jasper_lee 0:b16d94660a33 128 Bus clock = 4MHz
Jasper_lee 0:b16d94660a33 129 3 ... Chip externally clocked, ready for Very Low Power Run mode.
Jasper_lee 0:b16d94660a33 130 Multipurpose Clock Generator (MCG) in BLPE mode.
Jasper_lee 0:b16d94660a33 131 Reference clock source for MCG module: System oscillator 0 reference clock
Jasper_lee 0:b16d94660a33 132 Core clock = 4MHz
Jasper_lee 0:b16d94660a33 133 Bus clock = 4MHz
Jasper_lee 0:b16d94660a33 134 4 ... USB clock setup
Jasper_lee 0:b16d94660a33 135 Multipurpose Clock Generator (MCG) in PEE mode.
Jasper_lee 0:b16d94660a33 136 Reference clock source for MCG module: System oscillator 0 reference clock
Jasper_lee 0:b16d94660a33 137 Core clock = 120MHz
Jasper_lee 0:b16d94660a33 138 Bus clock = 60MHz
Jasper_lee 0:b16d94660a33 139 5 ... Maximum achievable clock frequency configuration in RUN mode
Jasper_lee 0:b16d94660a33 140 Multipurpose Clock Generator (MCG) in PEE mode.
Jasper_lee 0:b16d94660a33 141 Reference clock source for MCG module: System oscillator 0 reference clock
Jasper_lee 0:b16d94660a33 142 Core clock = 80MHz
Jasper_lee 0:b16d94660a33 143 Bus clock = 40MHz
Jasper_lee 0:b16d94660a33 144 */
Jasper_lee 0:b16d94660a33 145
Jasper_lee 0:b16d94660a33 146 /* Define clock source values */
Jasper_lee 0:b16d94660a33 147
Jasper_lee 0:b16d94660a33 148 #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
Jasper_lee 0:b16d94660a33 149 #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
Jasper_lee 0:b16d94660a33 150 #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
Jasper_lee 0:b16d94660a33 151 #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
Jasper_lee 0:b16d94660a33 152 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
Jasper_lee 0:b16d94660a33 153
Jasper_lee 0:b16d94660a33 154 /* RTC oscillator setting */
Jasper_lee 0:b16d94660a33 155 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
Jasper_lee 0:b16d94660a33 156 #define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
Jasper_lee 0:b16d94660a33 157
Jasper_lee 0:b16d94660a33 158 /* Low power mode enable */
Jasper_lee 0:b16d94660a33 159 /* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
Jasper_lee 0:b16d94660a33 160 #define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
Jasper_lee 0:b16d94660a33 161
Jasper_lee 0:b16d94660a33 162 /* Internal reference clock trim */
Jasper_lee 0:b16d94660a33 163 /* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
Jasper_lee 0:b16d94660a33 164 /* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
Jasper_lee 0:b16d94660a33 165 /* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
Jasper_lee 0:b16d94660a33 166 /* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
Jasper_lee 0:b16d94660a33 167
Jasper_lee 0:b16d94660a33 168 #if (CLOCK_SETUP == 0)
Jasper_lee 0:b16d94660a33 169 #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
Jasper_lee 0:b16d94660a33 170 #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
Jasper_lee 0:b16d94660a33 171 /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 172 #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
Jasper_lee 0:b16d94660a33 173 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
Jasper_lee 0:b16d94660a33 174 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 175 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 176 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 177 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
Jasper_lee 0:b16d94660a33 178 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
Jasper_lee 0:b16d94660a33 179 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Jasper_lee 0:b16d94660a33 180 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 181 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Jasper_lee 0:b16d94660a33 182 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 183 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 184 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 185 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 186 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
Jasper_lee 0:b16d94660a33 187 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 188 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 189 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
Jasper_lee 0:b16d94660a33 190 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 191 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 192 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 193 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 194 #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 195 #elif (CLOCK_SETUP == 1)
Jasper_lee 0:b16d94660a33 196 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
Jasper_lee 0:b16d94660a33 197 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
Jasper_lee 0:b16d94660a33 198 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 199 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
Jasper_lee 0:b16d94660a33 200 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
Jasper_lee 0:b16d94660a33 201 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 202 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 203 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 204 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
Jasper_lee 0:b16d94660a33 205 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
Jasper_lee 0:b16d94660a33 206 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
Jasper_lee 0:b16d94660a33 207 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 208 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
Jasper_lee 0:b16d94660a33 209 #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 210 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 211 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 212 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 213 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
Jasper_lee 0:b16d94660a33 214 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 215 #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 216 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
Jasper_lee 0:b16d94660a33 217 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 218 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 219 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 220 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 221 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 222 #elif (CLOCK_SETUP == 2)
Jasper_lee 0:b16d94660a33 223 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
Jasper_lee 0:b16d94660a33 224 #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
Jasper_lee 0:b16d94660a33 225 /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 226 #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
Jasper_lee 0:b16d94660a33 227 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
Jasper_lee 0:b16d94660a33 228 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 229 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 230 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 231 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
Jasper_lee 0:b16d94660a33 232 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
Jasper_lee 0:b16d94660a33 233 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Jasper_lee 0:b16d94660a33 234 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 235 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Jasper_lee 0:b16d94660a33 236 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 237 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 238 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 239 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 240 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
Jasper_lee 0:b16d94660a33 241 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 242 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 243 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
Jasper_lee 0:b16d94660a33 244 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 245 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 246 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 247 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 248 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 249 #elif (CLOCK_SETUP == 3)
Jasper_lee 0:b16d94660a33 250 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
Jasper_lee 0:b16d94660a33 251 #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
Jasper_lee 0:b16d94660a33 252 /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 253 #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
Jasper_lee 0:b16d94660a33 254 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
Jasper_lee 0:b16d94660a33 255 #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 256 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 257 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 258 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
Jasper_lee 0:b16d94660a33 259 #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
Jasper_lee 0:b16d94660a33 260 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
Jasper_lee 0:b16d94660a33 261 #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 262 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
Jasper_lee 0:b16d94660a33 263 #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 264 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 265 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 266 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 267 #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
Jasper_lee 0:b16d94660a33 268 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 269 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 270 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
Jasper_lee 0:b16d94660a33 271 #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 272 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 273 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 274 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 275 #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 276 #elif (CLOCK_SETUP == 4)
Jasper_lee 0:b16d94660a33 277 #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
Jasper_lee 0:b16d94660a33 278 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
Jasper_lee 0:b16d94660a33 279 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 280 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
Jasper_lee 0:b16d94660a33 281 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
Jasper_lee 0:b16d94660a33 282 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 283 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 284 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 285 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
Jasper_lee 0:b16d94660a33 286 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
Jasper_lee 0:b16d94660a33 287 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
Jasper_lee 0:b16d94660a33 288 #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 289 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
Jasper_lee 0:b16d94660a33 290 #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 291 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 292 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 293 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 294 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
Jasper_lee 0:b16d94660a33 295 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 296 #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 297 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
Jasper_lee 0:b16d94660a33 298 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 299 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
Jasper_lee 0:b16d94660a33 300 #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
Jasper_lee 0:b16d94660a33 301 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 302 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 303 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 304 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 305 #elif (CLOCK_SETUP == 5)
Jasper_lee 0:b16d94660a33 306 #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
Jasper_lee 0:b16d94660a33 307 #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
Jasper_lee 0:b16d94660a33 308 /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
Jasper_lee 0:b16d94660a33 309 #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
Jasper_lee 0:b16d94660a33 310 /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
Jasper_lee 0:b16d94660a33 311 #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
Jasper_lee 0:b16d94660a33 312 /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
Jasper_lee 0:b16d94660a33 313 #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
Jasper_lee 0:b16d94660a33 314 /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
Jasper_lee 0:b16d94660a33 315 #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
Jasper_lee 0:b16d94660a33 316 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
Jasper_lee 0:b16d94660a33 317 #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
Jasper_lee 0:b16d94660a33 318 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
Jasper_lee 0:b16d94660a33 319 #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
Jasper_lee 0:b16d94660a33 320 /* MCG_C7: OSCSEL=0 */
Jasper_lee 0:b16d94660a33 321 #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
Jasper_lee 0:b16d94660a33 322 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
Jasper_lee 0:b16d94660a33 323 #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
Jasper_lee 0:b16d94660a33 324 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
Jasper_lee 0:b16d94660a33 325 #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
Jasper_lee 0:b16d94660a33 326 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
Jasper_lee 0:b16d94660a33 327 #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
Jasper_lee 0:b16d94660a33 328 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
Jasper_lee 0:b16d94660a33 329 #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
Jasper_lee 0:b16d94660a33 330 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
Jasper_lee 0:b16d94660a33 331 #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
Jasper_lee 0:b16d94660a33 332 #endif
Jasper_lee 0:b16d94660a33 333
Jasper_lee 0:b16d94660a33 334 /**
Jasper_lee 0:b16d94660a33 335 * @brief System clock frequency (core clock)
Jasper_lee 0:b16d94660a33 336 *
Jasper_lee 0:b16d94660a33 337 * The system clock frequency supplied to the SysTick timer and the processor
Jasper_lee 0:b16d94660a33 338 * core clock. This variable can be used by the user application to setup the
Jasper_lee 0:b16d94660a33 339 * SysTick timer or configure other parameters. It may also be used by debugger to
Jasper_lee 0:b16d94660a33 340 * query the frequency of the debug timer or configure the trace clock speed
Jasper_lee 0:b16d94660a33 341 * SystemCoreClock is initialized with a correct predefined value.
Jasper_lee 0:b16d94660a33 342 */
Jasper_lee 0:b16d94660a33 343 extern uint32_t SystemCoreClock;
Jasper_lee 0:b16d94660a33 344
Jasper_lee 0:b16d94660a33 345 /**
Jasper_lee 0:b16d94660a33 346 * @brief Setup the microcontroller system.
Jasper_lee 0:b16d94660a33 347 *
Jasper_lee 0:b16d94660a33 348 * Typically this function configures the oscillator (PLL) that is part of the
Jasper_lee 0:b16d94660a33 349 * microcontroller device. For systems with variable clock speed it also updates
Jasper_lee 0:b16d94660a33 350 * the variable SystemCoreClock. SystemInit is called from startup_device file.
Jasper_lee 0:b16d94660a33 351 */
Jasper_lee 0:b16d94660a33 352 void SystemInit (void);
Jasper_lee 0:b16d94660a33 353
Jasper_lee 0:b16d94660a33 354 /**
Jasper_lee 0:b16d94660a33 355 * @brief Updates the SystemCoreClock variable.
Jasper_lee 0:b16d94660a33 356 *
Jasper_lee 0:b16d94660a33 357 * It must be called whenever the core clock is changed during program
Jasper_lee 0:b16d94660a33 358 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
Jasper_lee 0:b16d94660a33 359 * the current core clock.
Jasper_lee 0:b16d94660a33 360 */
Jasper_lee 0:b16d94660a33 361 void SystemCoreClockUpdate (void);
Jasper_lee 0:b16d94660a33 362
Jasper_lee 0:b16d94660a33 363 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 364 }
Jasper_lee 0:b16d94660a33 365 #endif
Jasper_lee 0:b16d94660a33 366
Jasper_lee 0:b16d94660a33 367 #endif /* #if !defined(SYSTEM_MK22F51212_H_) */