Jasper Lee / mbed_helloworld

change some io settings for TWR-K22F-120M

Dependents:   twr_helloworld

TARGET_ARCH_BLE/nrf51.h@0:b16d94660a33, 2014-12-23 (annotated)

Committer:
Jasper_lee
Date:
Tue Dec 23 03:35:08 2014 +0000
Revision:
0:b16d94660a33
change some io setting used in TWR-K22F120M

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Jasper_lee 0:b16d94660a33 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
Jasper_lee 0:b16d94660a33 2 *
Jasper_lee 0:b16d94660a33 3 * The information contained herein is property of Nordic Semiconductor ASA.
Jasper_lee 0:b16d94660a33 4 * Terms and conditions of usage are described in detail in NORDIC
Jasper_lee 0:b16d94660a33 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
Jasper_lee 0:b16d94660a33 6 *
Jasper_lee 0:b16d94660a33 7 * Licensees are granted free, non-transferable use of the information. NO
Jasper_lee 0:b16d94660a33 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
Jasper_lee 0:b16d94660a33 9 * the file.
Jasper_lee 0:b16d94660a33 10 *
Jasper_lee 0:b16d94660a33 11 */
Jasper_lee 0:b16d94660a33 12
Jasper_lee 0:b16d94660a33 13
Jasper_lee 0:b16d94660a33 14
Jasper_lee 0:b16d94660a33 15 /** @addtogroup Nordic Semiconductor
Jasper_lee 0:b16d94660a33 16 * @{
Jasper_lee 0:b16d94660a33 17 */
Jasper_lee 0:b16d94660a33 18
Jasper_lee 0:b16d94660a33 19 /** @addtogroup nRF51
Jasper_lee 0:b16d94660a33 20 * @{
Jasper_lee 0:b16d94660a33 21 */
Jasper_lee 0:b16d94660a33 22
Jasper_lee 0:b16d94660a33 23 #ifndef NRF51_H
Jasper_lee 0:b16d94660a33 24 #define NRF51_H
Jasper_lee 0:b16d94660a33 25
Jasper_lee 0:b16d94660a33 26 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 27 extern "C" {
Jasper_lee 0:b16d94660a33 28 #endif
Jasper_lee 0:b16d94660a33 29
Jasper_lee 0:b16d94660a33 30
Jasper_lee 0:b16d94660a33 31 /* ------------------------- Interrupt Number Definition ------------------------ */
Jasper_lee 0:b16d94660a33 32
Jasper_lee 0:b16d94660a33 33 typedef enum {
Jasper_lee 0:b16d94660a33 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Jasper_lee 0:b16d94660a33 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Jasper_lee 0:b16d94660a33 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Jasper_lee 0:b16d94660a33 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Jasper_lee 0:b16d94660a33 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Jasper_lee 0:b16d94660a33 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Jasper_lee 0:b16d94660a33 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Jasper_lee 0:b16d94660a33 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Jasper_lee 0:b16d94660a33 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
Jasper_lee 0:b16d94660a33 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Jasper_lee 0:b16d94660a33 44 RADIO_IRQn = 1, /*!< 1 RADIO */
Jasper_lee 0:b16d94660a33 45 UART0_IRQn = 2, /*!< 2 UART0 */
Jasper_lee 0:b16d94660a33 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
Jasper_lee 0:b16d94660a33 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
Jasper_lee 0:b16d94660a33 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Jasper_lee 0:b16d94660a33 49 ADC_IRQn = 7, /*!< 7 ADC */
Jasper_lee 0:b16d94660a33 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Jasper_lee 0:b16d94660a33 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Jasper_lee 0:b16d94660a33 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Jasper_lee 0:b16d94660a33 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
Jasper_lee 0:b16d94660a33 54 TEMP_IRQn = 12, /*!< 12 TEMP */
Jasper_lee 0:b16d94660a33 55 RNG_IRQn = 13, /*!< 13 RNG */
Jasper_lee 0:b16d94660a33 56 ECB_IRQn = 14, /*!< 14 ECB */
Jasper_lee 0:b16d94660a33 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Jasper_lee 0:b16d94660a33 58 WDT_IRQn = 16, /*!< 16 WDT */
Jasper_lee 0:b16d94660a33 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
Jasper_lee 0:b16d94660a33 60 QDEC_IRQn = 18, /*!< 18 QDEC */
Jasper_lee 0:b16d94660a33 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
Jasper_lee 0:b16d94660a33 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
Jasper_lee 0:b16d94660a33 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
Jasper_lee 0:b16d94660a33 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
Jasper_lee 0:b16d94660a33 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
Jasper_lee 0:b16d94660a33 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
Jasper_lee 0:b16d94660a33 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
Jasper_lee 0:b16d94660a33 68 } IRQn_Type;
Jasper_lee 0:b16d94660a33 69
Jasper_lee 0:b16d94660a33 70
Jasper_lee 0:b16d94660a33 71 /** @addtogroup Configuration_of_CMSIS
Jasper_lee 0:b16d94660a33 72 * @{
Jasper_lee 0:b16d94660a33 73 */
Jasper_lee 0:b16d94660a33 74
Jasper_lee 0:b16d94660a33 75
Jasper_lee 0:b16d94660a33 76 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 77 /* ================ Processor and Core Peripheral Section ================ */
Jasper_lee 0:b16d94660a33 78 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 79
Jasper_lee 0:b16d94660a33 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
Jasper_lee 0:b16d94660a33 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
Jasper_lee 0:b16d94660a33 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
Jasper_lee 0:b16d94660a33 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Jasper_lee 0:b16d94660a33 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Jasper_lee 0:b16d94660a33 85 /** @} */ /* End of group Configuration_of_CMSIS */
Jasper_lee 0:b16d94660a33 86
Jasper_lee 0:b16d94660a33 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
Jasper_lee 0:b16d94660a33 88 #include "system_nrf51822.h" /*!< nRF51 System */
Jasper_lee 0:b16d94660a33 89
Jasper_lee 0:b16d94660a33 90
Jasper_lee 0:b16d94660a33 91 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 92 /* ================ Device Specific Peripheral Section ================ */
Jasper_lee 0:b16d94660a33 93 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 94
Jasper_lee 0:b16d94660a33 95
Jasper_lee 0:b16d94660a33 96 /** @addtogroup Device_Peripheral_Registers
Jasper_lee 0:b16d94660a33 97 * @{
Jasper_lee 0:b16d94660a33 98 */
Jasper_lee 0:b16d94660a33 99
Jasper_lee 0:b16d94660a33 100
Jasper_lee 0:b16d94660a33 101 /* ------------------- Start of section using anonymous unions ------------------ */
Jasper_lee 0:b16d94660a33 102 #if defined(__CC_ARM)
Jasper_lee 0:b16d94660a33 103 #pragma push
Jasper_lee 0:b16d94660a33 104 #pragma anon_unions
Jasper_lee 0:b16d94660a33 105 #elif defined(__ICCARM__)
Jasper_lee 0:b16d94660a33 106 #pragma language=extended
Jasper_lee 0:b16d94660a33 107 #elif defined(__GNUC__)
Jasper_lee 0:b16d94660a33 108 /* anonymous unions are enabled by default */
Jasper_lee 0:b16d94660a33 109 #elif defined(__TMS470__)
Jasper_lee 0:b16d94660a33 110 /* anonymous unions are enabled by default */
Jasper_lee 0:b16d94660a33 111 #elif defined(__TASKING__)
Jasper_lee 0:b16d94660a33 112 #pragma warning 586
Jasper_lee 0:b16d94660a33 113 #else
Jasper_lee 0:b16d94660a33 114 #warning Not supported compiler type
Jasper_lee 0:b16d94660a33 115 #endif
Jasper_lee 0:b16d94660a33 116
Jasper_lee 0:b16d94660a33 117
Jasper_lee 0:b16d94660a33 118 typedef struct {
Jasper_lee 0:b16d94660a33 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
Jasper_lee 0:b16d94660a33 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
Jasper_lee 0:b16d94660a33 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
Jasper_lee 0:b16d94660a33 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
Jasper_lee 0:b16d94660a33 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
Jasper_lee 0:b16d94660a33 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
Jasper_lee 0:b16d94660a33 125 } AMLI_RAMPRI_Type;
Jasper_lee 0:b16d94660a33 126
Jasper_lee 0:b16d94660a33 127 typedef struct {
Jasper_lee 0:b16d94660a33 128 __O uint32_t EN; /*!< Enable channel group. */
Jasper_lee 0:b16d94660a33 129 __O uint32_t DIS; /*!< Disable channel group. */
Jasper_lee 0:b16d94660a33 130 } PPI_TASKS_CHG_Type;
Jasper_lee 0:b16d94660a33 131
Jasper_lee 0:b16d94660a33 132 typedef struct {
Jasper_lee 0:b16d94660a33 133 __IO uint32_t EEP; /*!< Channel event end-point. */
Jasper_lee 0:b16d94660a33 134 __IO uint32_t TEP; /*!< Channel task end-point. */
Jasper_lee 0:b16d94660a33 135 } PPI_CH_Type;
Jasper_lee 0:b16d94660a33 136
Jasper_lee 0:b16d94660a33 137
Jasper_lee 0:b16d94660a33 138 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 139 /* ================ POWER ================ */
Jasper_lee 0:b16d94660a33 140 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 141
Jasper_lee 0:b16d94660a33 142
Jasper_lee 0:b16d94660a33 143 /**
Jasper_lee 0:b16d94660a33 144 * @brief Power Control. (POWER)
Jasper_lee 0:b16d94660a33 145 */
Jasper_lee 0:b16d94660a33 146
Jasper_lee 0:b16d94660a33 147 typedef struct { /*!< POWER Structure */
Jasper_lee 0:b16d94660a33 148 __I uint32_t RESERVED0[30];
Jasper_lee 0:b16d94660a33 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
Jasper_lee 0:b16d94660a33 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
Jasper_lee 0:b16d94660a33 151 __I uint32_t RESERVED1[34];
Jasper_lee 0:b16d94660a33 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
Jasper_lee 0:b16d94660a33 153 __I uint32_t RESERVED2[126];
Jasper_lee 0:b16d94660a33 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 156 __I uint32_t RESERVED3[61];
Jasper_lee 0:b16d94660a33 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
Jasper_lee 0:b16d94660a33 158 __I uint32_t RESERVED4[63];
Jasper_lee 0:b16d94660a33 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
Jasper_lee 0:b16d94660a33 160 __I uint32_t RESERVED5[3];
Jasper_lee 0:b16d94660a33 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
Jasper_lee 0:b16d94660a33 162 __I uint32_t RESERVED6[2];
Jasper_lee 0:b16d94660a33 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Jasper_lee 0:b16d94660a33 164 register. */
Jasper_lee 0:b16d94660a33 165 __I uint32_t RESERVED7;
Jasper_lee 0:b16d94660a33 166 __IO uint32_t RAMON; /*!< Ram on/off. */
Jasper_lee 0:b16d94660a33 167 __I uint32_t RESERVED8[7];
Jasper_lee 0:b16d94660a33 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Jasper_lee 0:b16d94660a33 169 is a retained register. */
Jasper_lee 0:b16d94660a33 170 __I uint32_t RESERVED9[12];
Jasper_lee 0:b16d94660a33 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Jasper_lee 0:b16d94660a33 172 } NRF_POWER_Type;
Jasper_lee 0:b16d94660a33 173
Jasper_lee 0:b16d94660a33 174
Jasper_lee 0:b16d94660a33 175 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 176 /* ================ CLOCK ================ */
Jasper_lee 0:b16d94660a33 177 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 178
Jasper_lee 0:b16d94660a33 179
Jasper_lee 0:b16d94660a33 180 /**
Jasper_lee 0:b16d94660a33 181 * @brief Clock control. (CLOCK)
Jasper_lee 0:b16d94660a33 182 */
Jasper_lee 0:b16d94660a33 183
Jasper_lee 0:b16d94660a33 184 typedef struct { /*!< CLOCK Structure */
Jasper_lee 0:b16d94660a33 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
Jasper_lee 0:b16d94660a33 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
Jasper_lee 0:b16d94660a33 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
Jasper_lee 0:b16d94660a33 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
Jasper_lee 0:b16d94660a33 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
Jasper_lee 0:b16d94660a33 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
Jasper_lee 0:b16d94660a33 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
Jasper_lee 0:b16d94660a33 192 __I uint32_t RESERVED0[57];
Jasper_lee 0:b16d94660a33 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
Jasper_lee 0:b16d94660a33 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
Jasper_lee 0:b16d94660a33 195 __I uint32_t RESERVED1;
Jasper_lee 0:b16d94660a33 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
Jasper_lee 0:b16d94660a33 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
Jasper_lee 0:b16d94660a33 198 __I uint32_t RESERVED2[124];
Jasper_lee 0:b16d94660a33 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 201 __I uint32_t RESERVED3[64];
Jasper_lee 0:b16d94660a33 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Jasper_lee 0:b16d94660a33 203 __I uint32_t RESERVED4[2];
Jasper_lee 0:b16d94660a33 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Jasper_lee 0:b16d94660a33 205 __I uint32_t RESERVED5[63];
Jasper_lee 0:b16d94660a33 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
Jasper_lee 0:b16d94660a33 207 __I uint32_t RESERVED6[7];
Jasper_lee 0:b16d94660a33 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
Jasper_lee 0:b16d94660a33 209 __I uint32_t RESERVED7[5];
Jasper_lee 0:b16d94660a33 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
Jasper_lee 0:b16d94660a33 211 } NRF_CLOCK_Type;
Jasper_lee 0:b16d94660a33 212
Jasper_lee 0:b16d94660a33 213
Jasper_lee 0:b16d94660a33 214 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 215 /* ================ MPU ================ */
Jasper_lee 0:b16d94660a33 216 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 217
Jasper_lee 0:b16d94660a33 218
Jasper_lee 0:b16d94660a33 219 /**
Jasper_lee 0:b16d94660a33 220 * @brief Memory Protection Unit. (MPU)
Jasper_lee 0:b16d94660a33 221 */
Jasper_lee 0:b16d94660a33 222
Jasper_lee 0:b16d94660a33 223 typedef struct { /*!< MPU Structure */
Jasper_lee 0:b16d94660a33 224 __I uint32_t RESERVED0[330];
Jasper_lee 0:b16d94660a33 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
Jasper_lee 0:b16d94660a33 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
Jasper_lee 0:b16d94660a33 227 __I uint32_t RESERVED1[52];
Jasper_lee 0:b16d94660a33 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
Jasper_lee 0:b16d94660a33 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
Jasper_lee 0:b16d94660a33 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
Jasper_lee 0:b16d94660a33 231 } NRF_MPU_Type;
Jasper_lee 0:b16d94660a33 232
Jasper_lee 0:b16d94660a33 233
Jasper_lee 0:b16d94660a33 234 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 235 /* ================ PU ================ */
Jasper_lee 0:b16d94660a33 236 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 237
Jasper_lee 0:b16d94660a33 238
Jasper_lee 0:b16d94660a33 239 /**
Jasper_lee 0:b16d94660a33 240 * @brief Patch unit. (PU)
Jasper_lee 0:b16d94660a33 241 */
Jasper_lee 0:b16d94660a33 242
Jasper_lee 0:b16d94660a33 243 typedef struct { /*!< PU Structure */
Jasper_lee 0:b16d94660a33 244 __I uint32_t RESERVED0[448];
Jasper_lee 0:b16d94660a33 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
Jasper_lee 0:b16d94660a33 246 __I uint32_t RESERVED1[24];
Jasper_lee 0:b16d94660a33 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
Jasper_lee 0:b16d94660a33 248 __I uint32_t RESERVED2[24];
Jasper_lee 0:b16d94660a33 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
Jasper_lee 0:b16d94660a33 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
Jasper_lee 0:b16d94660a33 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
Jasper_lee 0:b16d94660a33 252 } NRF_PU_Type;
Jasper_lee 0:b16d94660a33 253
Jasper_lee 0:b16d94660a33 254
Jasper_lee 0:b16d94660a33 255 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 256 /* ================ AMLI ================ */
Jasper_lee 0:b16d94660a33 257 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 258
Jasper_lee 0:b16d94660a33 259
Jasper_lee 0:b16d94660a33 260 /**
Jasper_lee 0:b16d94660a33 261 * @brief AHB Multi-Layer Interface. (AMLI)
Jasper_lee 0:b16d94660a33 262 */
Jasper_lee 0:b16d94660a33 263
Jasper_lee 0:b16d94660a33 264 typedef struct { /*!< AMLI Structure */
Jasper_lee 0:b16d94660a33 265 __I uint32_t RESERVED0[896];
Jasper_lee 0:b16d94660a33 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
Jasper_lee 0:b16d94660a33 267 } NRF_AMLI_Type;
Jasper_lee 0:b16d94660a33 268
Jasper_lee 0:b16d94660a33 269
Jasper_lee 0:b16d94660a33 270 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 271 /* ================ RADIO ================ */
Jasper_lee 0:b16d94660a33 272 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 273
Jasper_lee 0:b16d94660a33 274
Jasper_lee 0:b16d94660a33 275 /**
Jasper_lee 0:b16d94660a33 276 * @brief The radio. (RADIO)
Jasper_lee 0:b16d94660a33 277 */
Jasper_lee 0:b16d94660a33 278
Jasper_lee 0:b16d94660a33 279 typedef struct { /*!< RADIO Structure */
Jasper_lee 0:b16d94660a33 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
Jasper_lee 0:b16d94660a33 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
Jasper_lee 0:b16d94660a33 282 __O uint32_t TASKS_START; /*!< Start radio. */
Jasper_lee 0:b16d94660a33 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
Jasper_lee 0:b16d94660a33 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
Jasper_lee 0:b16d94660a33 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
Jasper_lee 0:b16d94660a33 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
Jasper_lee 0:b16d94660a33 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
Jasper_lee 0:b16d94660a33 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
Jasper_lee 0:b16d94660a33 289 __I uint32_t RESERVED0[55];
Jasper_lee 0:b16d94660a33 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
Jasper_lee 0:b16d94660a33 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
Jasper_lee 0:b16d94660a33 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
Jasper_lee 0:b16d94660a33 293 __IO uint32_t EVENTS_END; /*!< End event. */
Jasper_lee 0:b16d94660a33 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
Jasper_lee 0:b16d94660a33 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
Jasper_lee 0:b16d94660a33 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
Jasper_lee 0:b16d94660a33 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Jasper_lee 0:b16d94660a33 298 sample is ready for readout at the RSSISAMPLE register. */
Jasper_lee 0:b16d94660a33 299 __I uint32_t RESERVED1[2];
Jasper_lee 0:b16d94660a33 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
Jasper_lee 0:b16d94660a33 301 __I uint32_t RESERVED2[53];
Jasper_lee 0:b16d94660a33 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
Jasper_lee 0:b16d94660a33 303 __I uint32_t RESERVED3[64];
Jasper_lee 0:b16d94660a33 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 306 __I uint32_t RESERVED4[61];
Jasper_lee 0:b16d94660a33 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Jasper_lee 0:b16d94660a33 308 __I uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 309 __I uint32_t RXMATCH; /*!< Received address. */
Jasper_lee 0:b16d94660a33 310 __I uint32_t RXCRC; /*!< Received CRC. */
Jasper_lee 0:b16d94660a33 311 __IO uint32_t DAI; /*!< Device address match index. */
Jasper_lee 0:b16d94660a33 312 __I uint32_t RESERVED6[60];
Jasper_lee 0:b16d94660a33 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
Jasper_lee 0:b16d94660a33 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
Jasper_lee 0:b16d94660a33 315 __IO uint32_t TXPOWER; /*!< Output power. */
Jasper_lee 0:b16d94660a33 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
Jasper_lee 0:b16d94660a33 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
Jasper_lee 0:b16d94660a33 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
Jasper_lee 0:b16d94660a33 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
Jasper_lee 0:b16d94660a33 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
Jasper_lee 0:b16d94660a33 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
Jasper_lee 0:b16d94660a33 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
Jasper_lee 0:b16d94660a33 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
Jasper_lee 0:b16d94660a33 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
Jasper_lee 0:b16d94660a33 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
Jasper_lee 0:b16d94660a33 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
Jasper_lee 0:b16d94660a33 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
Jasper_lee 0:b16d94660a33 328 __IO uint32_t TEST; /*!< Test features enable register. */
Jasper_lee 0:b16d94660a33 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Jasper_lee 0:b16d94660a33 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
Jasper_lee 0:b16d94660a33 331 __I uint32_t RESERVED7;
Jasper_lee 0:b16d94660a33 332 __I uint32_t STATE; /*!< Current radio state. */
Jasper_lee 0:b16d94660a33 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Jasper_lee 0:b16d94660a33 334 __I uint32_t RESERVED8[2];
Jasper_lee 0:b16d94660a33 335 __IO uint32_t BCC; /*!< Bit counter compare. */
Jasper_lee 0:b16d94660a33 336 __I uint32_t RESERVED9[39];
Jasper_lee 0:b16d94660a33 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
Jasper_lee 0:b16d94660a33 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
Jasper_lee 0:b16d94660a33 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
Jasper_lee 0:b16d94660a33 340 __I uint32_t RESERVED10[56];
Jasper_lee 0:b16d94660a33 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
Jasper_lee 0:b16d94660a33 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
Jasper_lee 0:b16d94660a33 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
Jasper_lee 0:b16d94660a33 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
Jasper_lee 0:b16d94660a33 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Jasper_lee 0:b16d94660a33 346 __I uint32_t RESERVED11[561];
Jasper_lee 0:b16d94660a33 347 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 348 } NRF_RADIO_Type;
Jasper_lee 0:b16d94660a33 349
Jasper_lee 0:b16d94660a33 350
Jasper_lee 0:b16d94660a33 351 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 352 /* ================ UART ================ */
Jasper_lee 0:b16d94660a33 353 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 354
Jasper_lee 0:b16d94660a33 355
Jasper_lee 0:b16d94660a33 356 /**
Jasper_lee 0:b16d94660a33 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
Jasper_lee 0:b16d94660a33 358 */
Jasper_lee 0:b16d94660a33 359
Jasper_lee 0:b16d94660a33 360 typedef struct { /*!< UART Structure */
Jasper_lee 0:b16d94660a33 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
Jasper_lee 0:b16d94660a33 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
Jasper_lee 0:b16d94660a33 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
Jasper_lee 0:b16d94660a33 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
Jasper_lee 0:b16d94660a33 365 __I uint32_t RESERVED0[3];
Jasper_lee 0:b16d94660a33 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
Jasper_lee 0:b16d94660a33 367 __I uint32_t RESERVED1[56];
Jasper_lee 0:b16d94660a33 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
Jasper_lee 0:b16d94660a33 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
Jasper_lee 0:b16d94660a33 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
Jasper_lee 0:b16d94660a33 371 __I uint32_t RESERVED2[4];
Jasper_lee 0:b16d94660a33 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
Jasper_lee 0:b16d94660a33 373 __I uint32_t RESERVED3;
Jasper_lee 0:b16d94660a33 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
Jasper_lee 0:b16d94660a33 375 __I uint32_t RESERVED4[7];
Jasper_lee 0:b16d94660a33 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
Jasper_lee 0:b16d94660a33 377 __I uint32_t RESERVED5[46];
Jasper_lee 0:b16d94660a33 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Jasper_lee 0:b16d94660a33 379 __I uint32_t RESERVED6[64];
Jasper_lee 0:b16d94660a33 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 382 __I uint32_t RESERVED7[93];
Jasper_lee 0:b16d94660a33 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
Jasper_lee 0:b16d94660a33 384 __I uint32_t RESERVED8[31];
Jasper_lee 0:b16d94660a33 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
Jasper_lee 0:b16d94660a33 386 __I uint32_t RESERVED9;
Jasper_lee 0:b16d94660a33 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
Jasper_lee 0:b16d94660a33 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
Jasper_lee 0:b16d94660a33 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
Jasper_lee 0:b16d94660a33 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
Jasper_lee 0:b16d94660a33 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Jasper_lee 0:b16d94660a33 392 Once read the character is consummed. If read when no character
Jasper_lee 0:b16d94660a33 393 available, the UART will stop working. */
Jasper_lee 0:b16d94660a33 394 __O uint32_t TXD; /*!< TXD register. */
Jasper_lee 0:b16d94660a33 395 __I uint32_t RESERVED10;
Jasper_lee 0:b16d94660a33 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
Jasper_lee 0:b16d94660a33 397 __I uint32_t RESERVED11[17];
Jasper_lee 0:b16d94660a33 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
Jasper_lee 0:b16d94660a33 399 __I uint32_t RESERVED12[675];
Jasper_lee 0:b16d94660a33 400 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 401 } NRF_UART_Type;
Jasper_lee 0:b16d94660a33 402
Jasper_lee 0:b16d94660a33 403
Jasper_lee 0:b16d94660a33 404 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 405 /* ================ SPI ================ */
Jasper_lee 0:b16d94660a33 406 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 407
Jasper_lee 0:b16d94660a33 408
Jasper_lee 0:b16d94660a33 409 /**
Jasper_lee 0:b16d94660a33 410 * @brief SPI master 0. (SPI)
Jasper_lee 0:b16d94660a33 411 */
Jasper_lee 0:b16d94660a33 412
Jasper_lee 0:b16d94660a33 413 typedef struct { /*!< SPI Structure */
Jasper_lee 0:b16d94660a33 414 __I uint32_t RESERVED0[66];
Jasper_lee 0:b16d94660a33 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
Jasper_lee 0:b16d94660a33 416 __I uint32_t RESERVED1[126];
Jasper_lee 0:b16d94660a33 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 419 __I uint32_t RESERVED2[125];
Jasper_lee 0:b16d94660a33 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
Jasper_lee 0:b16d94660a33 421 __I uint32_t RESERVED3;
Jasper_lee 0:b16d94660a33 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Jasper_lee 0:b16d94660a33 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Jasper_lee 0:b16d94660a33 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Jasper_lee 0:b16d94660a33 425 __I uint32_t RESERVED4;
Jasper_lee 0:b16d94660a33 426 __IO uint32_t RXD; /*!< RX data. */
Jasper_lee 0:b16d94660a33 427 __IO uint32_t TXD; /*!< TX data. */
Jasper_lee 0:b16d94660a33 428 __I uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Jasper_lee 0:b16d94660a33 430 __I uint32_t RESERVED6[11];
Jasper_lee 0:b16d94660a33 431 __IO uint32_t CONFIG; /*!< Configuration register. */
Jasper_lee 0:b16d94660a33 432 __I uint32_t RESERVED7[681];
Jasper_lee 0:b16d94660a33 433 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 434 } NRF_SPI_Type;
Jasper_lee 0:b16d94660a33 435
Jasper_lee 0:b16d94660a33 436
Jasper_lee 0:b16d94660a33 437 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 438 /* ================ TWI ================ */
Jasper_lee 0:b16d94660a33 439 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 440
Jasper_lee 0:b16d94660a33 441
Jasper_lee 0:b16d94660a33 442 /**
Jasper_lee 0:b16d94660a33 443 * @brief Two-wire interface master 0. (TWI)
Jasper_lee 0:b16d94660a33 444 */
Jasper_lee 0:b16d94660a33 445
Jasper_lee 0:b16d94660a33 446 typedef struct { /*!< TWI Structure */
Jasper_lee 0:b16d94660a33 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
Jasper_lee 0:b16d94660a33 448 __I uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
Jasper_lee 0:b16d94660a33 450 __I uint32_t RESERVED1[2];
Jasper_lee 0:b16d94660a33 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
Jasper_lee 0:b16d94660a33 452 __I uint32_t RESERVED2;
Jasper_lee 0:b16d94660a33 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
Jasper_lee 0:b16d94660a33 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
Jasper_lee 0:b16d94660a33 455 __I uint32_t RESERVED3[56];
Jasper_lee 0:b16d94660a33 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
Jasper_lee 0:b16d94660a33 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
Jasper_lee 0:b16d94660a33 458 __I uint32_t RESERVED4[4];
Jasper_lee 0:b16d94660a33 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
Jasper_lee 0:b16d94660a33 460 __I uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
Jasper_lee 0:b16d94660a33 462 __I uint32_t RESERVED6[4];
Jasper_lee 0:b16d94660a33 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Jasper_lee 0:b16d94660a33 464 __I uint32_t RESERVED7[49];
Jasper_lee 0:b16d94660a33 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Jasper_lee 0:b16d94660a33 466 __I uint32_t RESERVED8[64];
Jasper_lee 0:b16d94660a33 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 469 __I uint32_t RESERVED9[110];
Jasper_lee 0:b16d94660a33 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Jasper_lee 0:b16d94660a33 471 __I uint32_t RESERVED10[14];
Jasper_lee 0:b16d94660a33 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Jasper_lee 0:b16d94660a33 473 __I uint32_t RESERVED11;
Jasper_lee 0:b16d94660a33 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
Jasper_lee 0:b16d94660a33 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Jasper_lee 0:b16d94660a33 476 __I uint32_t RESERVED12[2];
Jasper_lee 0:b16d94660a33 477 __IO uint32_t RXD; /*!< RX data register. */
Jasper_lee 0:b16d94660a33 478 __IO uint32_t TXD; /*!< TX data register. */
Jasper_lee 0:b16d94660a33 479 __I uint32_t RESERVED13;
Jasper_lee 0:b16d94660a33 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Jasper_lee 0:b16d94660a33 481 __I uint32_t RESERVED14[24];
Jasper_lee 0:b16d94660a33 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Jasper_lee 0:b16d94660a33 483 __I uint32_t RESERVED15[668];
Jasper_lee 0:b16d94660a33 484 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 485 } NRF_TWI_Type;
Jasper_lee 0:b16d94660a33 486
Jasper_lee 0:b16d94660a33 487
Jasper_lee 0:b16d94660a33 488 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 489 /* ================ SPIS ================ */
Jasper_lee 0:b16d94660a33 490 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 491
Jasper_lee 0:b16d94660a33 492
Jasper_lee 0:b16d94660a33 493 /**
Jasper_lee 0:b16d94660a33 494 * @brief SPI slave 1. (SPIS)
Jasper_lee 0:b16d94660a33 495 */
Jasper_lee 0:b16d94660a33 496
Jasper_lee 0:b16d94660a33 497 typedef struct { /*!< SPIS Structure */
Jasper_lee 0:b16d94660a33 498 __I uint32_t RESERVED0[9];
Jasper_lee 0:b16d94660a33 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
Jasper_lee 0:b16d94660a33 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
Jasper_lee 0:b16d94660a33 501 __I uint32_t RESERVED1[54];
Jasper_lee 0:b16d94660a33 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Jasper_lee 0:b16d94660a33 503 __I uint32_t RESERVED2[8];
Jasper_lee 0:b16d94660a33 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Jasper_lee 0:b16d94660a33 505 __I uint32_t RESERVED3[53];
Jasper_lee 0:b16d94660a33 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Jasper_lee 0:b16d94660a33 507 __I uint32_t RESERVED4[64];
Jasper_lee 0:b16d94660a33 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 510 __I uint32_t RESERVED5[61];
Jasper_lee 0:b16d94660a33 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Jasper_lee 0:b16d94660a33 512 __I uint32_t RESERVED6[15];
Jasper_lee 0:b16d94660a33 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
Jasper_lee 0:b16d94660a33 514 __I uint32_t RESERVED7[47];
Jasper_lee 0:b16d94660a33 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Jasper_lee 0:b16d94660a33 516 __I uint32_t RESERVED8;
Jasper_lee 0:b16d94660a33 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Jasper_lee 0:b16d94660a33 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Jasper_lee 0:b16d94660a33 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Jasper_lee 0:b16d94660a33 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Jasper_lee 0:b16d94660a33 521 __I uint32_t RESERVED9[7];
Jasper_lee 0:b16d94660a33 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
Jasper_lee 0:b16d94660a33 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Jasper_lee 0:b16d94660a33 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Jasper_lee 0:b16d94660a33 525 __I uint32_t RESERVED10;
Jasper_lee 0:b16d94660a33 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
Jasper_lee 0:b16d94660a33 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Jasper_lee 0:b16d94660a33 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Jasper_lee 0:b16d94660a33 529 __I uint32_t RESERVED11;
Jasper_lee 0:b16d94660a33 530 __IO uint32_t CONFIG; /*!< Configuration register. */
Jasper_lee 0:b16d94660a33 531 __I uint32_t RESERVED12;
Jasper_lee 0:b16d94660a33 532 __IO uint32_t DEF; /*!< Default character. */
Jasper_lee 0:b16d94660a33 533 __I uint32_t RESERVED13[24];
Jasper_lee 0:b16d94660a33 534 __IO uint32_t ORC; /*!< Over-read character. */
Jasper_lee 0:b16d94660a33 535 __I uint32_t RESERVED14[654];
Jasper_lee 0:b16d94660a33 536 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 537 } NRF_SPIS_Type;
Jasper_lee 0:b16d94660a33 538
Jasper_lee 0:b16d94660a33 539
Jasper_lee 0:b16d94660a33 540 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 541 /* ================ GPIOTE ================ */
Jasper_lee 0:b16d94660a33 542 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 543
Jasper_lee 0:b16d94660a33 544
Jasper_lee 0:b16d94660a33 545 /**
Jasper_lee 0:b16d94660a33 546 * @brief GPIO tasks and events. (GPIOTE)
Jasper_lee 0:b16d94660a33 547 */
Jasper_lee 0:b16d94660a33 548
Jasper_lee 0:b16d94660a33 549 typedef struct { /*!< GPIOTE Structure */
Jasper_lee 0:b16d94660a33 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
Jasper_lee 0:b16d94660a33 551 __I uint32_t RESERVED0[60];
Jasper_lee 0:b16d94660a33 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
Jasper_lee 0:b16d94660a33 553 __I uint32_t RESERVED1[27];
Jasper_lee 0:b16d94660a33 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
Jasper_lee 0:b16d94660a33 555 __I uint32_t RESERVED2[97];
Jasper_lee 0:b16d94660a33 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 558 __I uint32_t RESERVED3[129];
Jasper_lee 0:b16d94660a33 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
Jasper_lee 0:b16d94660a33 560 __I uint32_t RESERVED4[695];
Jasper_lee 0:b16d94660a33 561 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 562 } NRF_GPIOTE_Type;
Jasper_lee 0:b16d94660a33 563
Jasper_lee 0:b16d94660a33 564
Jasper_lee 0:b16d94660a33 565 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 566 /* ================ ADC ================ */
Jasper_lee 0:b16d94660a33 567 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 568
Jasper_lee 0:b16d94660a33 569
Jasper_lee 0:b16d94660a33 570 /**
Jasper_lee 0:b16d94660a33 571 * @brief Analog to digital converter. (ADC)
Jasper_lee 0:b16d94660a33 572 */
Jasper_lee 0:b16d94660a33 573
Jasper_lee 0:b16d94660a33 574 typedef struct { /*!< ADC Structure */
Jasper_lee 0:b16d94660a33 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
Jasper_lee 0:b16d94660a33 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
Jasper_lee 0:b16d94660a33 577 __I uint32_t RESERVED0[62];
Jasper_lee 0:b16d94660a33 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
Jasper_lee 0:b16d94660a33 579 __I uint32_t RESERVED1[128];
Jasper_lee 0:b16d94660a33 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 582 __I uint32_t RESERVED2[61];
Jasper_lee 0:b16d94660a33 583 __I uint32_t BUSY; /*!< ADC busy register. */
Jasper_lee 0:b16d94660a33 584 __I uint32_t RESERVED3[63];
Jasper_lee 0:b16d94660a33 585 __IO uint32_t ENABLE; /*!< ADC enable. */
Jasper_lee 0:b16d94660a33 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
Jasper_lee 0:b16d94660a33 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
Jasper_lee 0:b16d94660a33 588 __I uint32_t RESERVED4[700];
Jasper_lee 0:b16d94660a33 589 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 590 } NRF_ADC_Type;
Jasper_lee 0:b16d94660a33 591
Jasper_lee 0:b16d94660a33 592
Jasper_lee 0:b16d94660a33 593 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 594 /* ================ TIMER ================ */
Jasper_lee 0:b16d94660a33 595 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 596
Jasper_lee 0:b16d94660a33 597
Jasper_lee 0:b16d94660a33 598 /**
Jasper_lee 0:b16d94660a33 599 * @brief Timer 0. (TIMER)
Jasper_lee 0:b16d94660a33 600 */
Jasper_lee 0:b16d94660a33 601
Jasper_lee 0:b16d94660a33 602 typedef struct { /*!< TIMER Structure */
Jasper_lee 0:b16d94660a33 603 __O uint32_t TASKS_START; /*!< Start Timer. */
Jasper_lee 0:b16d94660a33 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
Jasper_lee 0:b16d94660a33 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
Jasper_lee 0:b16d94660a33 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Jasper_lee 0:b16d94660a33 607 __I uint32_t RESERVED0[12];
Jasper_lee 0:b16d94660a33 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
Jasper_lee 0:b16d94660a33 609 __I uint32_t RESERVED1[60];
Jasper_lee 0:b16d94660a33 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Jasper_lee 0:b16d94660a33 611 __I uint32_t RESERVED2[44];
Jasper_lee 0:b16d94660a33 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
Jasper_lee 0:b16d94660a33 613 __I uint32_t RESERVED3[64];
Jasper_lee 0:b16d94660a33 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 616 __I uint32_t RESERVED4[126];
Jasper_lee 0:b16d94660a33 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
Jasper_lee 0:b16d94660a33 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
Jasper_lee 0:b16d94660a33 619 __I uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Jasper_lee 0:b16d94660a33 621 clock frequency is divided by 2^SCALE. */
Jasper_lee 0:b16d94660a33 622 __I uint32_t RESERVED6[11];
Jasper_lee 0:b16d94660a33 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Jasper_lee 0:b16d94660a33 624 __I uint32_t RESERVED7[683];
Jasper_lee 0:b16d94660a33 625 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 626 } NRF_TIMER_Type;
Jasper_lee 0:b16d94660a33 627
Jasper_lee 0:b16d94660a33 628
Jasper_lee 0:b16d94660a33 629 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 630 /* ================ RTC ================ */
Jasper_lee 0:b16d94660a33 631 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 632
Jasper_lee 0:b16d94660a33 633
Jasper_lee 0:b16d94660a33 634 /**
Jasper_lee 0:b16d94660a33 635 * @brief Real time counter 0. (RTC)
Jasper_lee 0:b16d94660a33 636 */
Jasper_lee 0:b16d94660a33 637
Jasper_lee 0:b16d94660a33 638 typedef struct { /*!< RTC Structure */
Jasper_lee 0:b16d94660a33 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
Jasper_lee 0:b16d94660a33 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
Jasper_lee 0:b16d94660a33 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
Jasper_lee 0:b16d94660a33 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
Jasper_lee 0:b16d94660a33 643 __I uint32_t RESERVED0[60];
Jasper_lee 0:b16d94660a33 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
Jasper_lee 0:b16d94660a33 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
Jasper_lee 0:b16d94660a33 646 __I uint32_t RESERVED1[14];
Jasper_lee 0:b16d94660a33 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Jasper_lee 0:b16d94660a33 648 __I uint32_t RESERVED2[109];
Jasper_lee 0:b16d94660a33 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 651 __I uint32_t RESERVED3[13];
Jasper_lee 0:b16d94660a33 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
Jasper_lee 0:b16d94660a33 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Jasper_lee 0:b16d94660a33 654 the value of EVTEN. */
Jasper_lee 0:b16d94660a33 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Jasper_lee 0:b16d94660a33 656 gives the value of EVTEN. */
Jasper_lee 0:b16d94660a33 657 __I uint32_t RESERVED4[110];
Jasper_lee 0:b16d94660a33 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
Jasper_lee 0:b16d94660a33 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Jasper_lee 0:b16d94660a33 660 Must be written when RTC is STOPed. */
Jasper_lee 0:b16d94660a33 661 __I uint32_t RESERVED5[13];
Jasper_lee 0:b16d94660a33 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Jasper_lee 0:b16d94660a33 663 __I uint32_t RESERVED6[683];
Jasper_lee 0:b16d94660a33 664 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 665 } NRF_RTC_Type;
Jasper_lee 0:b16d94660a33 666
Jasper_lee 0:b16d94660a33 667
Jasper_lee 0:b16d94660a33 668 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 669 /* ================ TEMP ================ */
Jasper_lee 0:b16d94660a33 670 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 671
Jasper_lee 0:b16d94660a33 672
Jasper_lee 0:b16d94660a33 673 /**
Jasper_lee 0:b16d94660a33 674 * @brief Temperature Sensor. (TEMP)
Jasper_lee 0:b16d94660a33 675 */
Jasper_lee 0:b16d94660a33 676
Jasper_lee 0:b16d94660a33 677 typedef struct { /*!< TEMP Structure */
Jasper_lee 0:b16d94660a33 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
Jasper_lee 0:b16d94660a33 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
Jasper_lee 0:b16d94660a33 680 __I uint32_t RESERVED0[62];
Jasper_lee 0:b16d94660a33 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
Jasper_lee 0:b16d94660a33 682 __I uint32_t RESERVED1[128];
Jasper_lee 0:b16d94660a33 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 685 __I uint32_t RESERVED2[127];
Jasper_lee 0:b16d94660a33 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
Jasper_lee 0:b16d94660a33 687 __I uint32_t RESERVED3[700];
Jasper_lee 0:b16d94660a33 688 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 689 } NRF_TEMP_Type;
Jasper_lee 0:b16d94660a33 690
Jasper_lee 0:b16d94660a33 691
Jasper_lee 0:b16d94660a33 692 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 693 /* ================ RNG ================ */
Jasper_lee 0:b16d94660a33 694 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 695
Jasper_lee 0:b16d94660a33 696
Jasper_lee 0:b16d94660a33 697 /**
Jasper_lee 0:b16d94660a33 698 * @brief Random Number Generator. (RNG)
Jasper_lee 0:b16d94660a33 699 */
Jasper_lee 0:b16d94660a33 700
Jasper_lee 0:b16d94660a33 701 typedef struct { /*!< RNG Structure */
Jasper_lee 0:b16d94660a33 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
Jasper_lee 0:b16d94660a33 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
Jasper_lee 0:b16d94660a33 704 __I uint32_t RESERVED0[62];
Jasper_lee 0:b16d94660a33 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
Jasper_lee 0:b16d94660a33 706 __I uint32_t RESERVED1[63];
Jasper_lee 0:b16d94660a33 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
Jasper_lee 0:b16d94660a33 708 __I uint32_t RESERVED2[64];
Jasper_lee 0:b16d94660a33 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
Jasper_lee 0:b16d94660a33 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
Jasper_lee 0:b16d94660a33 711 __I uint32_t RESERVED3[126];
Jasper_lee 0:b16d94660a33 712 __IO uint32_t CONFIG; /*!< Configuration register. */
Jasper_lee 0:b16d94660a33 713 __I uint32_t VALUE; /*!< RNG random number. */
Jasper_lee 0:b16d94660a33 714 __I uint32_t RESERVED4[700];
Jasper_lee 0:b16d94660a33 715 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 716 } NRF_RNG_Type;
Jasper_lee 0:b16d94660a33 717
Jasper_lee 0:b16d94660a33 718
Jasper_lee 0:b16d94660a33 719 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 720 /* ================ ECB ================ */
Jasper_lee 0:b16d94660a33 721 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 722
Jasper_lee 0:b16d94660a33 723
Jasper_lee 0:b16d94660a33 724 /**
Jasper_lee 0:b16d94660a33 725 * @brief AES ECB Mode Encryption. (ECB)
Jasper_lee 0:b16d94660a33 726 */
Jasper_lee 0:b16d94660a33 727
Jasper_lee 0:b16d94660a33 728 typedef struct { /*!< ECB Structure */
Jasper_lee 0:b16d94660a33 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Jasper_lee 0:b16d94660a33 730 will not initiate a new encryption and the ERRORECB event will
Jasper_lee 0:b16d94660a33 731 be triggered. */
Jasper_lee 0:b16d94660a33 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Jasper_lee 0:b16d94660a33 733 this will will trigger the ERRORECB event. */
Jasper_lee 0:b16d94660a33 734 __I uint32_t RESERVED0[62];
Jasper_lee 0:b16d94660a33 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
Jasper_lee 0:b16d94660a33 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Jasper_lee 0:b16d94660a33 737 error. */
Jasper_lee 0:b16d94660a33 738 __I uint32_t RESERVED1[127];
Jasper_lee 0:b16d94660a33 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 741 __I uint32_t RESERVED2[126];
Jasper_lee 0:b16d94660a33 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
Jasper_lee 0:b16d94660a33 743 __I uint32_t RESERVED3[701];
Jasper_lee 0:b16d94660a33 744 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 745 } NRF_ECB_Type;
Jasper_lee 0:b16d94660a33 746
Jasper_lee 0:b16d94660a33 747
Jasper_lee 0:b16d94660a33 748 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 749 /* ================ AAR ================ */
Jasper_lee 0:b16d94660a33 750 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 751
Jasper_lee 0:b16d94660a33 752
Jasper_lee 0:b16d94660a33 753 /**
Jasper_lee 0:b16d94660a33 754 * @brief Accelerated Address Resolver. (AAR)
Jasper_lee 0:b16d94660a33 755 */
Jasper_lee 0:b16d94660a33 756
Jasper_lee 0:b16d94660a33 757 typedef struct { /*!< AAR Structure */
Jasper_lee 0:b16d94660a33 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Jasper_lee 0:b16d94660a33 759 data structure. */
Jasper_lee 0:b16d94660a33 760 __I uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
Jasper_lee 0:b16d94660a33 762 __I uint32_t RESERVED1[61];
Jasper_lee 0:b16d94660a33 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
Jasper_lee 0:b16d94660a33 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
Jasper_lee 0:b16d94660a33 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
Jasper_lee 0:b16d94660a33 766 __I uint32_t RESERVED2[126];
Jasper_lee 0:b16d94660a33 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 769 __I uint32_t RESERVED3[61];
Jasper_lee 0:b16d94660a33 770 __I uint32_t STATUS; /*!< Resolution status. */
Jasper_lee 0:b16d94660a33 771 __I uint32_t RESERVED4[63];
Jasper_lee 0:b16d94660a33 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
Jasper_lee 0:b16d94660a33 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
Jasper_lee 0:b16d94660a33 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
Jasper_lee 0:b16d94660a33 775 __I uint32_t RESERVED5;
Jasper_lee 0:b16d94660a33 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Jasper_lee 0:b16d94660a33 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
Jasper_lee 0:b16d94660a33 778 resolution. A minimum of 3 bytes must be reserved. */
Jasper_lee 0:b16d94660a33 779 __I uint32_t RESERVED6[697];
Jasper_lee 0:b16d94660a33 780 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 781 } NRF_AAR_Type;
Jasper_lee 0:b16d94660a33 782
Jasper_lee 0:b16d94660a33 783
Jasper_lee 0:b16d94660a33 784 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 785 /* ================ CCM ================ */
Jasper_lee 0:b16d94660a33 786 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 787
Jasper_lee 0:b16d94660a33 788
Jasper_lee 0:b16d94660a33 789 /**
Jasper_lee 0:b16d94660a33 790 * @brief AES CCM Mode Encryption. (CCM)
Jasper_lee 0:b16d94660a33 791 */
Jasper_lee 0:b16d94660a33 792
Jasper_lee 0:b16d94660a33 793 typedef struct { /*!< CCM Structure */
Jasper_lee 0:b16d94660a33 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Jasper_lee 0:b16d94660a33 795 itself when completed. */
Jasper_lee 0:b16d94660a33 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Jasper_lee 0:b16d94660a33 797 completed. */
Jasper_lee 0:b16d94660a33 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
Jasper_lee 0:b16d94660a33 799 __I uint32_t RESERVED0[61];
Jasper_lee 0:b16d94660a33 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
Jasper_lee 0:b16d94660a33 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
Jasper_lee 0:b16d94660a33 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
Jasper_lee 0:b16d94660a33 803 __I uint32_t RESERVED1[61];
Jasper_lee 0:b16d94660a33 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
Jasper_lee 0:b16d94660a33 805 __I uint32_t RESERVED2[64];
Jasper_lee 0:b16d94660a33 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 808 __I uint32_t RESERVED3[61];
Jasper_lee 0:b16d94660a33 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
Jasper_lee 0:b16d94660a33 810 __I uint32_t RESERVED4[63];
Jasper_lee 0:b16d94660a33 811 __IO uint32_t ENABLE; /*!< CCM enable. */
Jasper_lee 0:b16d94660a33 812 __IO uint32_t MODE; /*!< Operation mode. */
Jasper_lee 0:b16d94660a33 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
Jasper_lee 0:b16d94660a33 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
Jasper_lee 0:b16d94660a33 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
Jasper_lee 0:b16d94660a33 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
Jasper_lee 0:b16d94660a33 817 resolution. A minimum of 43 bytes must be reserved. */
Jasper_lee 0:b16d94660a33 818 __I uint32_t RESERVED5[697];
Jasper_lee 0:b16d94660a33 819 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 820 } NRF_CCM_Type;
Jasper_lee 0:b16d94660a33 821
Jasper_lee 0:b16d94660a33 822
Jasper_lee 0:b16d94660a33 823 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 824 /* ================ WDT ================ */
Jasper_lee 0:b16d94660a33 825 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 826
Jasper_lee 0:b16d94660a33 827
Jasper_lee 0:b16d94660a33 828 /**
Jasper_lee 0:b16d94660a33 829 * @brief Watchdog Timer. (WDT)
Jasper_lee 0:b16d94660a33 830 */
Jasper_lee 0:b16d94660a33 831
Jasper_lee 0:b16d94660a33 832 typedef struct { /*!< WDT Structure */
Jasper_lee 0:b16d94660a33 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
Jasper_lee 0:b16d94660a33 834 __I uint32_t RESERVED0[63];
Jasper_lee 0:b16d94660a33 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
Jasper_lee 0:b16d94660a33 836 __I uint32_t RESERVED1[128];
Jasper_lee 0:b16d94660a33 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 839 __I uint32_t RESERVED2[61];
Jasper_lee 0:b16d94660a33 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
Jasper_lee 0:b16d94660a33 841 __I uint32_t REQSTATUS; /*!< Request status. */
Jasper_lee 0:b16d94660a33 842 __I uint32_t RESERVED3[63];
Jasper_lee 0:b16d94660a33 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
Jasper_lee 0:b16d94660a33 844 __IO uint32_t RREN; /*!< Reload request enable. */
Jasper_lee 0:b16d94660a33 845 __IO uint32_t CONFIG; /*!< Configuration register. */
Jasper_lee 0:b16d94660a33 846 __I uint32_t RESERVED4[60];
Jasper_lee 0:b16d94660a33 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
Jasper_lee 0:b16d94660a33 848 __I uint32_t RESERVED5[631];
Jasper_lee 0:b16d94660a33 849 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 850 } NRF_WDT_Type;
Jasper_lee 0:b16d94660a33 851
Jasper_lee 0:b16d94660a33 852
Jasper_lee 0:b16d94660a33 853 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 854 /* ================ QDEC ================ */
Jasper_lee 0:b16d94660a33 855 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 856
Jasper_lee 0:b16d94660a33 857
Jasper_lee 0:b16d94660a33 858 /**
Jasper_lee 0:b16d94660a33 859 * @brief Rotary decoder. (QDEC)
Jasper_lee 0:b16d94660a33 860 */
Jasper_lee 0:b16d94660a33 861
Jasper_lee 0:b16d94660a33 862 typedef struct { /*!< QDEC Structure */
Jasper_lee 0:b16d94660a33 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
Jasper_lee 0:b16d94660a33 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
Jasper_lee 0:b16d94660a33 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Jasper_lee 0:b16d94660a33 866 and clears the ACC registers. */
Jasper_lee 0:b16d94660a33 867 __I uint32_t RESERVED0[61];
Jasper_lee 0:b16d94660a33 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
Jasper_lee 0:b16d94660a33 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Jasper_lee 0:b16d94660a33 870 ACC register different than zero. */
Jasper_lee 0:b16d94660a33 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
Jasper_lee 0:b16d94660a33 872 __I uint32_t RESERVED1[61];
Jasper_lee 0:b16d94660a33 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
Jasper_lee 0:b16d94660a33 874 __I uint32_t RESERVED2[64];
Jasper_lee 0:b16d94660a33 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 877 __I uint32_t RESERVED3[125];
Jasper_lee 0:b16d94660a33 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
Jasper_lee 0:b16d94660a33 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
Jasper_lee 0:b16d94660a33 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
Jasper_lee 0:b16d94660a33 881 __I int32_t SAMPLE; /*!< Motion sample value. */
Jasper_lee 0:b16d94660a33 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
Jasper_lee 0:b16d94660a33 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
Jasper_lee 0:b16d94660a33 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Jasper_lee 0:b16d94660a33 885 task. */
Jasper_lee 0:b16d94660a33 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
Jasper_lee 0:b16d94660a33 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
Jasper_lee 0:b16d94660a33 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
Jasper_lee 0:b16d94660a33 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
Jasper_lee 0:b16d94660a33 890 __I uint32_t RESERVED4[5];
Jasper_lee 0:b16d94660a33 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
Jasper_lee 0:b16d94660a33 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
Jasper_lee 0:b16d94660a33 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Jasper_lee 0:b16d94660a33 894 task. */
Jasper_lee 0:b16d94660a33 895 __I uint32_t RESERVED5[684];
Jasper_lee 0:b16d94660a33 896 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 897 } NRF_QDEC_Type;
Jasper_lee 0:b16d94660a33 898
Jasper_lee 0:b16d94660a33 899
Jasper_lee 0:b16d94660a33 900 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 901 /* ================ LPCOMP ================ */
Jasper_lee 0:b16d94660a33 902 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 903
Jasper_lee 0:b16d94660a33 904
Jasper_lee 0:b16d94660a33 905 /**
Jasper_lee 0:b16d94660a33 906 * @brief Wakeup Comparator. (LPCOMP)
Jasper_lee 0:b16d94660a33 907 */
Jasper_lee 0:b16d94660a33 908
Jasper_lee 0:b16d94660a33 909 typedef struct { /*!< LPCOMP Structure */
Jasper_lee 0:b16d94660a33 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
Jasper_lee 0:b16d94660a33 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Jasper_lee 0:b16d94660a33 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Jasper_lee 0:b16d94660a33 913 __I uint32_t RESERVED0[61];
Jasper_lee 0:b16d94660a33 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
Jasper_lee 0:b16d94660a33 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Jasper_lee 0:b16d94660a33 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Jasper_lee 0:b16d94660a33 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Jasper_lee 0:b16d94660a33 918 __I uint32_t RESERVED1[60];
Jasper_lee 0:b16d94660a33 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
Jasper_lee 0:b16d94660a33 920 __I uint32_t RESERVED2[64];
Jasper_lee 0:b16d94660a33 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 923 __I uint32_t RESERVED3[61];
Jasper_lee 0:b16d94660a33 924 __I uint32_t RESULT; /*!< Result of last compare. */
Jasper_lee 0:b16d94660a33 925 __I uint32_t RESERVED4[63];
Jasper_lee 0:b16d94660a33 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
Jasper_lee 0:b16d94660a33 927 __IO uint32_t PSEL; /*!< Input pin select. */
Jasper_lee 0:b16d94660a33 928 __IO uint32_t REFSEL; /*!< Reference select. */
Jasper_lee 0:b16d94660a33 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Jasper_lee 0:b16d94660a33 930 __I uint32_t RESERVED5[4];
Jasper_lee 0:b16d94660a33 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
Jasper_lee 0:b16d94660a33 932 __I uint32_t RESERVED6[694];
Jasper_lee 0:b16d94660a33 933 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 934 } NRF_LPCOMP_Type;
Jasper_lee 0:b16d94660a33 935
Jasper_lee 0:b16d94660a33 936
Jasper_lee 0:b16d94660a33 937 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 938 /* ================ COMP ================ */
Jasper_lee 0:b16d94660a33 939 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 940
Jasper_lee 0:b16d94660a33 941
Jasper_lee 0:b16d94660a33 942 /**
Jasper_lee 0:b16d94660a33 943 * @brief Comparator. (COMP)
Jasper_lee 0:b16d94660a33 944 */
Jasper_lee 0:b16d94660a33 945
Jasper_lee 0:b16d94660a33 946 typedef struct { /*!< COMP Structure */
Jasper_lee 0:b16d94660a33 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
Jasper_lee 0:b16d94660a33 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Jasper_lee 0:b16d94660a33 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Jasper_lee 0:b16d94660a33 950 __I uint32_t RESERVED0[61];
Jasper_lee 0:b16d94660a33 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
Jasper_lee 0:b16d94660a33 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Jasper_lee 0:b16d94660a33 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Jasper_lee 0:b16d94660a33 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Jasper_lee 0:b16d94660a33 955 __I uint32_t RESERVED1[60];
Jasper_lee 0:b16d94660a33 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
Jasper_lee 0:b16d94660a33 957 __I uint32_t RESERVED2[64];
Jasper_lee 0:b16d94660a33 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Jasper_lee 0:b16d94660a33 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Jasper_lee 0:b16d94660a33 960 __I uint32_t RESERVED3[61];
Jasper_lee 0:b16d94660a33 961 __I uint32_t RESULT; /*!< Compare result. */
Jasper_lee 0:b16d94660a33 962 __I uint32_t RESERVED4[63];
Jasper_lee 0:b16d94660a33 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
Jasper_lee 0:b16d94660a33 964 __IO uint32_t PSEL; /*!< Input pin select. */
Jasper_lee 0:b16d94660a33 965 __IO uint32_t REFSEL; /*!< Reference select. */
Jasper_lee 0:b16d94660a33 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Jasper_lee 0:b16d94660a33 967 __I uint32_t RESERVED5[8];
Jasper_lee 0:b16d94660a33 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
Jasper_lee 0:b16d94660a33 969 __IO uint32_t MODE; /*!< Mode configuration. */
Jasper_lee 0:b16d94660a33 970 __I uint32_t RESERVED6[689];
Jasper_lee 0:b16d94660a33 971 __IO uint32_t POWER; /*!< Peripheral power control. */
Jasper_lee 0:b16d94660a33 972 } NRF_COMP_Type;
Jasper_lee 0:b16d94660a33 973
Jasper_lee 0:b16d94660a33 974
Jasper_lee 0:b16d94660a33 975 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 976 /* ================ SWI ================ */
Jasper_lee 0:b16d94660a33 977 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 978
Jasper_lee 0:b16d94660a33 979
Jasper_lee 0:b16d94660a33 980 /**
Jasper_lee 0:b16d94660a33 981 * @brief SW Interrupts. (SWI)
Jasper_lee 0:b16d94660a33 982 */
Jasper_lee 0:b16d94660a33 983
Jasper_lee 0:b16d94660a33 984 typedef struct { /*!< SWI Structure */
Jasper_lee 0:b16d94660a33 985 __I uint32_t UNUSED; /*!< Unused. */
Jasper_lee 0:b16d94660a33 986 } NRF_SWI_Type;
Jasper_lee 0:b16d94660a33 987
Jasper_lee 0:b16d94660a33 988
Jasper_lee 0:b16d94660a33 989 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 990 /* ================ NVMC ================ */
Jasper_lee 0:b16d94660a33 991 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 992
Jasper_lee 0:b16d94660a33 993
Jasper_lee 0:b16d94660a33 994 /**
Jasper_lee 0:b16d94660a33 995 * @brief Non Volatile Memory Controller. (NVMC)
Jasper_lee 0:b16d94660a33 996 */
Jasper_lee 0:b16d94660a33 997
Jasper_lee 0:b16d94660a33 998 typedef struct { /*!< NVMC Structure */
Jasper_lee 0:b16d94660a33 999 __I uint32_t RESERVED0[256];
Jasper_lee 0:b16d94660a33 1000 __I uint32_t READY; /*!< Ready flag. */
Jasper_lee 0:b16d94660a33 1001 __I uint32_t RESERVED1[64];
Jasper_lee 0:b16d94660a33 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
Jasper_lee 0:b16d94660a33 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Jasper_lee 0:b16d94660a33 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Jasper_lee 0:b16d94660a33 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
Jasper_lee 0:b16d94660a33 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
Jasper_lee 0:b16d94660a33 1007 } NRF_NVMC_Type;
Jasper_lee 0:b16d94660a33 1008
Jasper_lee 0:b16d94660a33 1009
Jasper_lee 0:b16d94660a33 1010 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1011 /* ================ PPI ================ */
Jasper_lee 0:b16d94660a33 1012 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1013
Jasper_lee 0:b16d94660a33 1014
Jasper_lee 0:b16d94660a33 1015 /**
Jasper_lee 0:b16d94660a33 1016 * @brief PPI controller. (PPI)
Jasper_lee 0:b16d94660a33 1017 */
Jasper_lee 0:b16d94660a33 1018
Jasper_lee 0:b16d94660a33 1019 typedef struct { /*!< PPI Structure */
Jasper_lee 0:b16d94660a33 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
Jasper_lee 0:b16d94660a33 1021 __I uint32_t RESERVED0[312];
Jasper_lee 0:b16d94660a33 1022 __IO uint32_t CHEN; /*!< Channel enable. */
Jasper_lee 0:b16d94660a33 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
Jasper_lee 0:b16d94660a33 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
Jasper_lee 0:b16d94660a33 1025 __I uint32_t RESERVED1;
Jasper_lee 0:b16d94660a33 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
Jasper_lee 0:b16d94660a33 1027 __I uint32_t RESERVED2[156];
Jasper_lee 0:b16d94660a33 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
Jasper_lee 0:b16d94660a33 1029 } NRF_PPI_Type;
Jasper_lee 0:b16d94660a33 1030
Jasper_lee 0:b16d94660a33 1031
Jasper_lee 0:b16d94660a33 1032 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1033 /* ================ FICR ================ */
Jasper_lee 0:b16d94660a33 1034 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1035
Jasper_lee 0:b16d94660a33 1036
Jasper_lee 0:b16d94660a33 1037 /**
Jasper_lee 0:b16d94660a33 1038 * @brief Factory Information Configuration. (FICR)
Jasper_lee 0:b16d94660a33 1039 */
Jasper_lee 0:b16d94660a33 1040
Jasper_lee 0:b16d94660a33 1041 typedef struct { /*!< FICR Structure */
Jasper_lee 0:b16d94660a33 1042 __I uint32_t RESERVED0[4];
Jasper_lee 0:b16d94660a33 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
Jasper_lee 0:b16d94660a33 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
Jasper_lee 0:b16d94660a33 1045 __I uint32_t RESERVED1[4];
Jasper_lee 0:b16d94660a33 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
Jasper_lee 0:b16d94660a33 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
Jasper_lee 0:b16d94660a33 1048 __I uint32_t RESERVED2;
Jasper_lee 0:b16d94660a33 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Jasper_lee 0:b16d94660a33 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
Jasper_lee 0:b16d94660a33 1051 __I uint32_t RESERVED3[5];
Jasper_lee 0:b16d94660a33 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
Jasper_lee 0:b16d94660a33 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
Jasper_lee 0:b16d94660a33 1054 __I uint32_t RESERVED4[6];
Jasper_lee 0:b16d94660a33 1055 __I uint32_t ER[4]; /*!< Encryption root. */
Jasper_lee 0:b16d94660a33 1056 __I uint32_t IR[4]; /*!< Identity root. */
Jasper_lee 0:b16d94660a33 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
Jasper_lee 0:b16d94660a33 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
Jasper_lee 0:b16d94660a33 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Jasper_lee 0:b16d94660a33 1060 __I uint32_t RESERVED5[15];
Jasper_lee 0:b16d94660a33 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Jasper_lee 0:b16d94660a33 1062 mode. */
Jasper_lee 0:b16d94660a33 1063 } NRF_FICR_Type;
Jasper_lee 0:b16d94660a33 1064
Jasper_lee 0:b16d94660a33 1065
Jasper_lee 0:b16d94660a33 1066 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1067 /* ================ UICR ================ */
Jasper_lee 0:b16d94660a33 1068 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1069
Jasper_lee 0:b16d94660a33 1070
Jasper_lee 0:b16d94660a33 1071 /**
Jasper_lee 0:b16d94660a33 1072 * @brief User Information Configuration. (UICR)
Jasper_lee 0:b16d94660a33 1073 */
Jasper_lee 0:b16d94660a33 1074
Jasper_lee 0:b16d94660a33 1075 typedef struct { /*!< UICR Structure */
Jasper_lee 0:b16d94660a33 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
Jasper_lee 0:b16d94660a33 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
Jasper_lee 0:b16d94660a33 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
Jasper_lee 0:b16d94660a33 1079 __I uint32_t RESERVED0;
Jasper_lee 0:b16d94660a33 1080 __I uint32_t FWID; /*!< Firmware ID. */
Jasper_lee 0:b16d94660a33 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Jasper_lee 0:b16d94660a33 1082 } NRF_UICR_Type;
Jasper_lee 0:b16d94660a33 1083
Jasper_lee 0:b16d94660a33 1084
Jasper_lee 0:b16d94660a33 1085 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1086 /* ================ GPIO ================ */
Jasper_lee 0:b16d94660a33 1087 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1088
Jasper_lee 0:b16d94660a33 1089
Jasper_lee 0:b16d94660a33 1090 /**
Jasper_lee 0:b16d94660a33 1091 * @brief General purpose input and output. (GPIO)
Jasper_lee 0:b16d94660a33 1092 */
Jasper_lee 0:b16d94660a33 1093
Jasper_lee 0:b16d94660a33 1094 typedef struct { /*!< GPIO Structure */
Jasper_lee 0:b16d94660a33 1095 __I uint32_t RESERVED0[321];
Jasper_lee 0:b16d94660a33 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
Jasper_lee 0:b16d94660a33 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
Jasper_lee 0:b16d94660a33 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
Jasper_lee 0:b16d94660a33 1099 __I uint32_t IN; /*!< Read GPIO port. */
Jasper_lee 0:b16d94660a33 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
Jasper_lee 0:b16d94660a33 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
Jasper_lee 0:b16d94660a33 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
Jasper_lee 0:b16d94660a33 1103 __I uint32_t RESERVED1[120];
Jasper_lee 0:b16d94660a33 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
Jasper_lee 0:b16d94660a33 1105 } NRF_GPIO_Type;
Jasper_lee 0:b16d94660a33 1106
Jasper_lee 0:b16d94660a33 1107
Jasper_lee 0:b16d94660a33 1108 /* -------------------- End of section using anonymous unions ------------------- */
Jasper_lee 0:b16d94660a33 1109 #if defined(__CC_ARM)
Jasper_lee 0:b16d94660a33 1110 #pragma pop
Jasper_lee 0:b16d94660a33 1111 #elif defined(__ICCARM__)
Jasper_lee 0:b16d94660a33 1112 /* leave anonymous unions enabled */
Jasper_lee 0:b16d94660a33 1113 #elif defined(__GNUC__)
Jasper_lee 0:b16d94660a33 1114 /* anonymous unions are enabled by default */
Jasper_lee 0:b16d94660a33 1115 #elif defined(__TMS470__)
Jasper_lee 0:b16d94660a33 1116 /* anonymous unions are enabled by default */
Jasper_lee 0:b16d94660a33 1117 #elif defined(__TASKING__)
Jasper_lee 0:b16d94660a33 1118 #pragma warning restore
Jasper_lee 0:b16d94660a33 1119 #else
Jasper_lee 0:b16d94660a33 1120 #warning Not supported compiler type
Jasper_lee 0:b16d94660a33 1121 #endif
Jasper_lee 0:b16d94660a33 1122
Jasper_lee 0:b16d94660a33 1123
Jasper_lee 0:b16d94660a33 1124
Jasper_lee 0:b16d94660a33 1125
Jasper_lee 0:b16d94660a33 1126 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1127 /* ================ Peripheral memory map ================ */
Jasper_lee 0:b16d94660a33 1128 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1129
Jasper_lee 0:b16d94660a33 1130 #define NRF_POWER_BASE 0x40000000UL
Jasper_lee 0:b16d94660a33 1131 #define NRF_CLOCK_BASE 0x40000000UL
Jasper_lee 0:b16d94660a33 1132 #define NRF_MPU_BASE 0x40000000UL
Jasper_lee 0:b16d94660a33 1133 #define NRF_PU_BASE 0x40000000UL
Jasper_lee 0:b16d94660a33 1134 #define NRF_AMLI_BASE 0x40000000UL
Jasper_lee 0:b16d94660a33 1135 #define NRF_RADIO_BASE 0x40001000UL
Jasper_lee 0:b16d94660a33 1136 #define NRF_UART0_BASE 0x40002000UL
Jasper_lee 0:b16d94660a33 1137 #define NRF_SPI0_BASE 0x40003000UL
Jasper_lee 0:b16d94660a33 1138 #define NRF_TWI0_BASE 0x40003000UL
Jasper_lee 0:b16d94660a33 1139 #define NRF_SPI1_BASE 0x40004000UL
Jasper_lee 0:b16d94660a33 1140 #define NRF_TWI1_BASE 0x40004000UL
Jasper_lee 0:b16d94660a33 1141 #define NRF_SPIS1_BASE 0x40004000UL
Jasper_lee 0:b16d94660a33 1142 #define NRF_GPIOTE_BASE 0x40006000UL
Jasper_lee 0:b16d94660a33 1143 #define NRF_ADC_BASE 0x40007000UL
Jasper_lee 0:b16d94660a33 1144 #define NRF_TIMER0_BASE 0x40008000UL
Jasper_lee 0:b16d94660a33 1145 #define NRF_TIMER1_BASE 0x40009000UL
Jasper_lee 0:b16d94660a33 1146 #define NRF_TIMER2_BASE 0x4000A000UL
Jasper_lee 0:b16d94660a33 1147 #define NRF_RTC0_BASE 0x4000B000UL
Jasper_lee 0:b16d94660a33 1148 #define NRF_TEMP_BASE 0x4000C000UL
Jasper_lee 0:b16d94660a33 1149 #define NRF_RNG_BASE 0x4000D000UL
Jasper_lee 0:b16d94660a33 1150 #define NRF_ECB_BASE 0x4000E000UL
Jasper_lee 0:b16d94660a33 1151 #define NRF_AAR_BASE 0x4000F000UL
Jasper_lee 0:b16d94660a33 1152 #define NRF_CCM_BASE 0x4000F000UL
Jasper_lee 0:b16d94660a33 1153 #define NRF_WDT_BASE 0x40010000UL
Jasper_lee 0:b16d94660a33 1154 #define NRF_RTC1_BASE 0x40011000UL
Jasper_lee 0:b16d94660a33 1155 #define NRF_QDEC_BASE 0x40012000UL
Jasper_lee 0:b16d94660a33 1156 #define NRF_LPCOMP_BASE 0x40013000UL
Jasper_lee 0:b16d94660a33 1157 #define NRF_COMP_BASE 0x40013000UL
Jasper_lee 0:b16d94660a33 1158 #define NRF_SWI_BASE 0x40014000UL
Jasper_lee 0:b16d94660a33 1159 #define NRF_NVMC_BASE 0x4001E000UL
Jasper_lee 0:b16d94660a33 1160 #define NRF_PPI_BASE 0x4001F000UL
Jasper_lee 0:b16d94660a33 1161 #define NRF_FICR_BASE 0x10000000UL
Jasper_lee 0:b16d94660a33 1162 #define NRF_UICR_BASE 0x10001000UL
Jasper_lee 0:b16d94660a33 1163 #define NRF_GPIO_BASE 0x50000000UL
Jasper_lee 0:b16d94660a33 1164
Jasper_lee 0:b16d94660a33 1165
Jasper_lee 0:b16d94660a33 1166 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1167 /* ================ Peripheral declaration ================ */
Jasper_lee 0:b16d94660a33 1168 /* ================================================================================ */
Jasper_lee 0:b16d94660a33 1169
Jasper_lee 0:b16d94660a33 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Jasper_lee 0:b16d94660a33 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Jasper_lee 0:b16d94660a33 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Jasper_lee 0:b16d94660a33 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
Jasper_lee 0:b16d94660a33 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Jasper_lee 0:b16d94660a33 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Jasper_lee 0:b16d94660a33 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Jasper_lee 0:b16d94660a33 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Jasper_lee 0:b16d94660a33 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Jasper_lee 0:b16d94660a33 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Jasper_lee 0:b16d94660a33 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Jasper_lee 0:b16d94660a33 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Jasper_lee 0:b16d94660a33 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Jasper_lee 0:b16d94660a33 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Jasper_lee 0:b16d94660a33 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Jasper_lee 0:b16d94660a33 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Jasper_lee 0:b16d94660a33 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Jasper_lee 0:b16d94660a33 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Jasper_lee 0:b16d94660a33 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Jasper_lee 0:b16d94660a33 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Jasper_lee 0:b16d94660a33 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Jasper_lee 0:b16d94660a33 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Jasper_lee 0:b16d94660a33 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Jasper_lee 0:b16d94660a33 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Jasper_lee 0:b16d94660a33 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Jasper_lee 0:b16d94660a33 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Jasper_lee 0:b16d94660a33 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Jasper_lee 0:b16d94660a33 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
Jasper_lee 0:b16d94660a33 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Jasper_lee 0:b16d94660a33 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Jasper_lee 0:b16d94660a33 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Jasper_lee 0:b16d94660a33 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Jasper_lee 0:b16d94660a33 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Jasper_lee 0:b16d94660a33 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Jasper_lee 0:b16d94660a33 1204
Jasper_lee 0:b16d94660a33 1205
Jasper_lee 0:b16d94660a33 1206 /** @} */ /* End of group Device_Peripheral_Registers */
Jasper_lee 0:b16d94660a33 1207 /** @} */ /* End of group nRF51 */
Jasper_lee 0:b16d94660a33 1208 /** @} */ /* End of group Nordic Semiconductor */
Jasper_lee 0:b16d94660a33 1209
Jasper_lee 0:b16d94660a33 1210 #ifdef __cplusplus
Jasper_lee 0:b16d94660a33 1211 }
Jasper_lee 0:b16d94660a33 1212 #endif
Jasper_lee 0:b16d94660a33 1213
Jasper_lee 0:b16d94660a33 1214
Jasper_lee 0:b16d94660a33 1215 #endif /* nRF51_H */
Jasper_lee 0:b16d94660a33 1216