Mark Harris
/
SIEMENS_DLFEEDER_LOOP
Loop based controller for dual lane siemens siplace feeder.
partNumbers.h@1:4d3738338cf1, 2017-02-04 (annotated)
- Committer:
- Issus
- Date:
- Sat Feb 04 01:27:29 2017 +0000
- Revision:
- 1:4d3738338cf1
Minimum on time for cover tape pickup. Added IAP for getting mcu serial number and future eeprom use. Moved defs to .h file.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Issus | 1:4d3738338cf1 | 1 | // http://www.nxp.com/documents/user_manual/UM10462.pdf Page 407-408 |
Issus | 1:4d3738338cf1 | 2 | #define LPC11U12FHN33_201 { 0x09, 0x5C, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 3 | #define LPC11U12FHN33_201 { 0x29, 0x5C, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 4 | #define LPC11U12FBD48_201 { 0x09, 0x5C, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 5 | #define LPC11U12FBD48_201 { 0x29, 0x5C, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 6 | #define LPC11U13FBD48_201 { 0x09, 0x7A, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 7 | #define LPC11U13FBD48_201 { 0x29, 0x7A, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 8 | #define LPC11U14FHN33_201 { 0x09, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 9 | #define LPC11U14FHN33_201 { 0x29, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 10 | #define LPC11U14FHI33_201 { 0x29, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 11 | #define LPC11U14FBD48_201 { 0x09, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 12 | #define LPC11U14FBD48_201 { 0x29, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 13 | #define LPC11U14FET48_201 { 0x09, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 14 | #define LPC11U14FET48_201 { 0x29, 0x98, 0x80, 0x2B } |
Issus | 1:4d3738338cf1 | 15 | #define LPC11U22FBD48_301 { 0x29, 0x54, 0x40, 0x2B } |
Issus | 1:4d3738338cf1 | 16 | #define LPC11U23FBD48_301 { 0x29, 0x72, 0x40, 0x2B } |
Issus | 1:4d3738338cf1 | 17 | #define LPC11U24FHI33_301 { 0x29, 0x88, 0x40, 0x2B } |
Issus | 1:4d3738338cf1 | 18 | #define LPC11U24FBD48_301 { 0x29, 0x88, 0x40, 0x2B } |
Issus | 1:4d3738338cf1 | 19 | #define LPC11U24FET48_301 { 0x29, 0x88, 0x40, 0x2B } |
Issus | 1:4d3738338cf1 | 20 | #define LPC11U24FHN33_401 { 0x29, 0x80, 0x00, 0x2B } |
Issus | 1:4d3738338cf1 | 21 | #define LPC11U24FBD48_401 { 0x29, 0x80, 0x00, 0x2B } |
Issus | 1:4d3738338cf1 | 22 | #define LPC11U24FBD64_401 { 0x29, 0x80, 0x00, 0x2B } |
Issus | 1:4d3738338cf1 | 23 | #define LPC11U34FHN33_311 { 0x00, 0x03, 0xD4, 0x40 } |
Issus | 1:4d3738338cf1 | 24 | #define LPC11U34FBD48_311 { 0x00, 0x03, 0xD4, 0x40 } |
Issus | 1:4d3738338cf1 | 25 | #define LPC11U34FHN33_421 { 0x00, 0x01, 0xCC, 0x40 } |
Issus | 1:4d3738338cf1 | 26 | #define LPC11U34FBD48_421 { 0x00, 0x01, 0xCC, 0x40 } |
Issus | 1:4d3738338cf1 | 27 | #define LPC11U35FHN33_401 { 0x00, 0x01, 0xBC, 0x40 } |
Issus | 1:4d3738338cf1 | 28 | #define LPC11U35FBD48_401 { 0x00, 0x01, 0xBC, 0x40 } |
Issus | 1:4d3738338cf1 | 29 | #define LPC11U35FBD64_401 { 0x00, 0x01, 0xBC, 0x40 } |
Issus | 1:4d3738338cf1 | 30 | #define LPC11U35FHI33_501 { 0x00, 0x00, 0xBC, 0x40 } |
Issus | 1:4d3738338cf1 | 31 | #define LPC11U35FET48_501 { 0x00, 0x00, 0xBC, 0x40 } |
Issus | 1:4d3738338cf1 | 32 | #define LPC11U36FBD48_401 { 0x00, 0x01, 0x9C, 0x40 } |
Issus | 1:4d3738338cf1 | 33 | #define LPC11U36FBD64_401 { 0x00, 0x01, 0x9C, 0x40 } |
Issus | 1:4d3738338cf1 | 34 | #define LPC11U37FBD48_401 { 0x00, 0x01, 0x7C, 0x40 } |
Issus | 1:4d3738338cf1 | 35 | #define LPC11U37HFBD64_401 { 0x00, 0x00, 0x7C, 0x44 } |
Issus | 1:4d3738338cf1 | 36 | #define LPC11U37FBD64_501 { 0x00, 0x00, 0x7C, 0x40 } |