This Automatic mode is the most simple lib for MCU Gear with LPC1114FN28. You don't need to think about Bank.
Dependents: MCUGearALPC1114FN28
Fork of MCUGearA by
MCUGearBaseA.h@1:95255bae41c8, 2014-05-03 (annotated)
- Committer:
- Info
- Date:
- Sat May 03 16:56:16 2014 +0000
- Revision:
- 1:95255bae41c8
- Parent:
- 0:12d93184b350
sample code for MCU Gear with LPC1114FN28. This code is easier than other our sample code.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Info | 0:12d93184b350 | 1 | /* MCU Gear Library, only for testing MCUGear without any circuit you connected. |
Info | 0:12d93184b350 | 2 | * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/ |
Info | 0:12d93184b350 | 3 | * |
Info | 0:12d93184b350 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
Info | 0:12d93184b350 | 5 | * of this software and associated documentation files (the "Software"), to deal |
Info | 0:12d93184b350 | 6 | * in the Software without restriction, including without limitation the rights |
Info | 0:12d93184b350 | 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
Info | 0:12d93184b350 | 8 | * copies of the Software, and to permit persons to whom the Software is |
Info | 0:12d93184b350 | 9 | * furnished to do so, subject to the following conditions: |
Info | 0:12d93184b350 | 10 | * |
Info | 0:12d93184b350 | 11 | * The above copyright notice and this permission notice shall be included in |
Info | 0:12d93184b350 | 12 | * all copies or substantial portions of the Software. |
Info | 0:12d93184b350 | 13 | * |
Info | 0:12d93184b350 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
Info | 0:12d93184b350 | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
Info | 0:12d93184b350 | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
Info | 0:12d93184b350 | 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
Info | 0:12d93184b350 | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
Info | 0:12d93184b350 | 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
Info | 0:12d93184b350 | 20 | * THE SOFTWARE. |
Info | 0:12d93184b350 | 21 | */ |
Info | 0:12d93184b350 | 22 | |
Info | 0:12d93184b350 | 23 | #include "commonA.h" |
Info | 0:12d93184b350 | 24 | |
Info | 0:12d93184b350 | 25 | |
Info | 0:12d93184b350 | 26 | #define FPGA_SYSINFO_0 0x00 |
Info | 0:12d93184b350 | 27 | #define FPGA_SYSINFO_1 0x04 |
Info | 0:12d93184b350 | 28 | #define FPGA_ENABLE 0x08 |
Info | 0:12d93184b350 | 29 | #define FPGA_DETECT 0x14 |
Info | 0:12d93184b350 | 30 | |
Info | 0:12d93184b350 | 31 | void fpga_write(int dev_adr,unsigned char adr, unsigned char data); |
Info | 0:12d93184b350 | 32 | unsigned char fpga_read(int dev_adr,unsigned char adr); |
Info | 0:12d93184b350 | 33 | void initBase(void); |
Info | 0:12d93184b350 | 34 | //void startReg(uint8_t bank); |
Info | 0:12d93184b350 | 35 | //void endReg(uint8_t bank); |
Info | 0:12d93184b350 | 36 | void deleteBank(uint8_t bank); |
Info | 0:12d93184b350 | 37 | void changeBank(uint8_t bank); |
Info | 0:12d93184b350 | 38 | |
Info | 0:12d93184b350 | 39 | |
Info | 0:12d93184b350 | 40 | // FGPGA CPU I/O |
Info | 0:12d93184b350 | 41 | typedef enum { |
Info | 0:12d93184b350 | 42 | |
Info | 1:95255bae41c8 | 43 | IOMOSI = 0x80,//P0_9 |
Info | 1:95255bae41c8 | 44 | IOSCK,//P0_6 |
Info | 1:95255bae41c8 | 45 | IOMISO,//P0_8 |
Info | 1:95255bae41c8 | 46 | IOout4,//P1_0 |
Info | 1:95255bae41c8 | 47 | NC1,//NC1 |
Info | 1:95255bae41c8 | 48 | IOout5,//P1_1 |
Info | 1:95255bae41c8 | 49 | IOout2,//P0_7 |
Info | 1:95255bae41c8 | 50 | IORX,//P1_6 |
Info | 1:95255bae41c8 | 51 | NC2,//NC2 |
Info | 1:95255bae41c8 | 52 | IOin2,//P1_9 |
Info | 1:95255bae41c8 | 53 | IOTX,//P1_7 |
Info | 1:95255bae41c8 | 54 | IOin1,//P1_8 |
Info | 1:95255bae41c8 | 55 | IOout7,//P1_5 |
Info | 1:95255bae41c8 | 56 | IOout8,//P1_4 |
Info | 1:95255bae41c8 | 57 | IOout6,//P1_2 |
Info | 1:95255bae41c8 | 58 | IOout3,//P0_11 |
Info | 1:95255bae41c8 | 59 | IOout1,//P0_3 |
Info | 1:95255bae41c8 | 60 | IOCS,//P0_2 |
Info | 1:95255bae41c8 | 61 | IOSDA,//P0_5 |
Info | 1:95255bae41c8 | 62 | IOSCL//0_4 |
Info | 1:95255bae41c8 | 63 | |
Info | 1:95255bae41c8 | 64 | /* IOP0_9 = 0x80,//P0_9 |
Info | 1:95255bae41c8 | 65 | IOP0_6,//P0_6 |
Info | 1:95255bae41c8 | 66 | IOP0_8,//P0_8 |
Info | 1:95255bae41c8 | 67 | IOP1_0,//P1_0 |
Info | 1:95255bae41c8 | 68 | NC1,//NC1 |
Info | 1:95255bae41c8 | 69 | IOP1_1,//P1_1 |
Info | 1:95255bae41c8 | 70 | IOP0_7,//P0_7 |
Info | 1:95255bae41c8 | 71 | IOP1_6,//P1_6 |
Info | 1:95255bae41c8 | 72 | NC2,//NC2 |
Info | 1:95255bae41c8 | 73 | IOP1_9,//P1_9 |
Info | 1:95255bae41c8 | 74 | IOP1_7,//P1_7 |
Info | 1:95255bae41c8 | 75 | IOP1_8,//P1_8 |
Info | 1:95255bae41c8 | 76 | IOP1_5,//P1_5 |
Info | 1:95255bae41c8 | 77 | IOP1_4,//P1_4 |
Info | 1:95255bae41c8 | 78 | IOP1_2,//P1_2 |
Info | 1:95255bae41c8 | 79 | IOP0_11,//P0_11 |
Info | 1:95255bae41c8 | 80 | IOP0_3,//P0_3 |
Info | 1:95255bae41c8 | 81 | IOP0_2,//P0_2 |
Info | 1:95255bae41c8 | 82 | IOP0_5,//P0_5 |
Info | 1:95255bae41c8 | 83 | IO0_4//0_4 |
Info | 1:95255bae41c8 | 84 | */ |
Info | 0:12d93184b350 | 85 | } en_cpu_io; |
Info | 0:12d93184b350 | 86 | |
Info | 0:12d93184b350 | 87 | // FPGA EXT I/O |
Info | 0:12d93184b350 | 88 | typedef enum { |
Info | 0:12d93184b350 | 89 | IO_CON1_1 = 0, |
Info | 0:12d93184b350 | 90 | IO_CON1_2, |
Info | 0:12d93184b350 | 91 | IO_CON1_3, |
Info | 0:12d93184b350 | 92 | IO_CON1_4, |
Info | 0:12d93184b350 | 93 | IO_CON2_1, |
Info | 0:12d93184b350 | 94 | IO_CON2_2, |
Info | 0:12d93184b350 | 95 | IO_CON2_3, |
Info | 0:12d93184b350 | 96 | IO_CON2_4, |
Info | 0:12d93184b350 | 97 | IO_CON3_1, |
Info | 0:12d93184b350 | 98 | IO_CON3_2, |
Info | 0:12d93184b350 | 99 | IO_CON3_3, |
Info | 0:12d93184b350 | 100 | IO_CON3_4, |
Info | 0:12d93184b350 | 101 | IO_CON4_1, |
Info | 0:12d93184b350 | 102 | IO_CON4_2, |
Info | 0:12d93184b350 | 103 | IO_CON4_3, |
Info | 0:12d93184b350 | 104 | IO_CON4_4, |
Info | 0:12d93184b350 | 105 | IO_CON5_1, |
Info | 0:12d93184b350 | 106 | IO_CON5_2, |
Info | 0:12d93184b350 | 107 | IO_CON5_3, |
Info | 0:12d93184b350 | 108 | IO_CON5_4, |
Info | 0:12d93184b350 | 109 | IO_CON6_1, |
Info | 0:12d93184b350 | 110 | IO_CON6_2, |
Info | 0:12d93184b350 | 111 | IO_CON6_3, |
Info | 0:12d93184b350 | 112 | IO_CON6_4, |
Info | 0:12d93184b350 | 113 | IO_CON7_1, |
Info | 0:12d93184b350 | 114 | IO_CON7_2, |
Info | 0:12d93184b350 | 115 | IO_CON7_3, |
Info | 0:12d93184b350 | 116 | IO_CON7_4, |
Info | 0:12d93184b350 | 117 | IO_CON8_1, |
Info | 0:12d93184b350 | 118 | IO_CON8_2, |
Info | 0:12d93184b350 | 119 | IO_CON8_3, |
Info | 0:12d93184b350 | 120 | IO_CON8_4, |
Info | 0:12d93184b350 | 121 | IO_CON9_1, |
Info | 0:12d93184b350 | 122 | IO_CON9_2, |
Info | 0:12d93184b350 | 123 | IO_CON9_3, |
Info | 0:12d93184b350 | 124 | IO_CON9_4, |
Info | 0:12d93184b350 | 125 | IO_CON10_1, |
Info | 0:12d93184b350 | 126 | IO_CON10_2, |
Info | 0:12d93184b350 | 127 | IO_CON10_3, |
Info | 0:12d93184b350 | 128 | IO_CON10_4, |
Info | 0:12d93184b350 | 129 | IO_CON11_1, |
Info | 0:12d93184b350 | 130 | IO_CON11_2, |
Info | 0:12d93184b350 | 131 | IO_CON11_3, |
Info | 0:12d93184b350 | 132 | IO_CON11_4, |
Info | 0:12d93184b350 | 133 | IO_CON12_1, |
Info | 0:12d93184b350 | 134 | IO_CON12_2, |
Info | 0:12d93184b350 | 135 | IO_CON12_3, |
Info | 0:12d93184b350 | 136 | IO_CON12_4 |
Info | 0:12d93184b350 | 137 | } en_fpga_io; |
Info | 0:12d93184b350 | 138 | |
Info | 0:12d93184b350 | 139 | typedef enum { |
Info | 0:12d93184b350 | 140 | IO_REG_EN = 0x80, |
Info | 0:12d93184b350 | 141 | IO_REG_OUT_DIR = 0x40, |
Info | 0:12d93184b350 | 142 | IO_REG_IN_DIR = 0x00, |
Info | 0:12d93184b350 | 143 | IO_REG_DISABLE = 0x3f |
Info | 0:12d93184b350 | 144 | } en_fpga_io_reg; |
Info | 0:12d93184b350 | 145 | |
Info | 0:12d93184b350 | 146 |