mille feuille / MCUGear

detail : http://www.mcugear.com/

You need lib of mbed and textLCD.

mbed と textLCDのライブラリが必要です。

common.h@1:bbcba1a79e7b, 2013-10-03 (annotated)

Committer:
Info
Date:
Thu Oct 03 09:21:14 2013 +0000
Revision:
1:bbcba1a79e7b
Parent:
0:d2cb480cd5e0 
main.cpp????????

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Who changed what in which revision?

UserRevisionLine numberNew contents of line
Info 0:d2cb480cd5e0 1 /* MCU Gear Library, only for testing MCUGear without any circuit you connected.
Info 0:d2cb480cd5e0 2 * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
Info 0:d2cb480cd5e0 3 *
Info 0:d2cb480cd5e0 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
Info 0:d2cb480cd5e0 5 * of this software and associated documentation files (the "Software"), to deal
Info 0:d2cb480cd5e0 6 * in the Software without restriction, including without limitation the rights
Info 0:d2cb480cd5e0 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
Info 0:d2cb480cd5e0 8 * copies of the Software, and to permit persons to whom the Software is
Info 0:d2cb480cd5e0 9 * furnished to do so, subject to the following conditions:
Info 0:d2cb480cd5e0 10 *
Info 0:d2cb480cd5e0 11 * The above copyright notice and this permission notice shall be included in
Info 0:d2cb480cd5e0 12 * all copies or substantial portions of the Software.
Info 0:d2cb480cd5e0 13 *
Info 0:d2cb480cd5e0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Info 0:d2cb480cd5e0 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Info 0:d2cb480cd5e0 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Info 0:d2cb480cd5e0 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Info 0:d2cb480cd5e0 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Info 0:d2cb480cd5e0 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Info 0:d2cb480cd5e0 20 * THE SOFTWARE.
Info 0:d2cb480cd5e0 21 */
Info 0:d2cb480cd5e0 22
Info 0:d2cb480cd5e0 23
Info 0:d2cb480cd5e0 24 //select your mbed--------------------------------------------
Info 0:d2cb480cd5e0 25 #define LPC1768_mbed
Info 0:d2cb480cd5e0 26 //#define FS_KL25Z
Info 0:d2cb480cd5e0 27
Info 0:d2cb480cd5e0 28 //#define BOOST_MODE //if you want use BANK System, define this.
Info 0:d2cb480cd5e0 29 //------------------------------------------------------------
Info 0:d2cb480cd5e0 30
Info 0:d2cb480cd5e0 31 //For Sample Mltifunction Mofdule-----------------------------
Info 0:d2cb480cd5e0 32 //#define AD_MODE
Info 0:d2cb480cd5e0 33 //#define PWM_MODE
Info 0:d2cb480cd5e0 34 //#define I2C_MODE
Info 0:d2cb480cd5e0 35
Info 0:d2cb480cd5e0 36 //------------------------------------------------------------
Info 0:d2cb480cd5e0 37
Info 0:d2cb480cd5e0 38
Info 0:d2cb480cd5e0 39
Info 0:d2cb480cd5e0 40
Info 0:d2cb480cd5e0 41 //#define DEBUG //If you need to debug, define this.
Info 0:d2cb480cd5e0 42 #ifdef LPC1768_mbed
Info 0:d2cb480cd5e0 43
Info 0:d2cb480cd5e0 44 #define BaudRate 9600
Info 0:d2cb480cd5e0 45 #define FPGA_I2C_CLOCK 1000000
Info 0:d2cb480cd5e0 46 #define MODULE_I2C_CLOCK 1000000
Info 0:d2cb480cd5e0 47
Info 0:d2cb480cd5e0 48 #endif
Info 0:d2cb480cd5e0 49
Info 0:d2cb480cd5e0 50 #ifdef FS_KL25Z
Info 0:d2cb480cd5e0 51
Info 0:d2cb480cd5e0 52 #define BaudRate 19200
Info 0:d2cb480cd5e0 53 #define FPGA_I2C_CLOCK 2000000 //about 769kHz
Info 0:d2cb480cd5e0 54 #define MODULE_I2C_CLOCK 2000000
Info 0:d2cb480cd5e0 55
Info 0:d2cb480cd5e0 56 #endif
Info 0:d2cb480cd5e0 57
Info 0:d2cb480cd5e0 58
Info 0:d2cb480cd5e0 59 #define FPGA_I2C_ADR 0x78
Info 0:d2cb480cd5e0 60
Info 0:d2cb480cd5e0 61 #ifdef DEBUG
Info 0:d2cb480cd5e0 62 #define BankMaxNum 3 //you can set 1 to 7 BANKs for Debug Mode.
Info 0:d2cb480cd5e0 63
Info 0:d2cb480cd5e0 64 #else
Info 0:d2cb480cd5e0 65 #define BankMaxNum 7 //BANK layers
Info 0:d2cb480cd5e0 66
Info 0:d2cb480cd5e0 67 #endif
Info 0:d2cb480cd5e0 68
Info 0:d2cb480cd5e0 69 //PCA9674
Info 0:d2cb480cd5e0 70 //VSS = GND VDD = +3.3V
Info 0:d2cb480cd5e0 71 //AD2 AD1 AD0
Info 0:d2cb480cd5e0 72 #define N_VSS_SCL_VSS 0x20
Info 0:d2cb480cd5e0 73 #define N_VSS_SCL_VDD 0x22
Info 0:d2cb480cd5e0 74 #define N_VSS_SDA_VSS 0x24
Info 0:d2cb480cd5e0 75 #define N_VSS_SDA_VDD 0x26
Info 0:d2cb480cd5e0 76 #define N_VDD_SCL_VSS 0x28
Info 0:d2cb480cd5e0 77 #define N_VDD_SCL_VDD 0x2A
Info 0:d2cb480cd5e0 78 #define N_VDD_SDA_VSS 0x2C
Info 0:d2cb480cd5e0 79 #define N_VDD_SDA_VDD 0x2E
Info 0:d2cb480cd5e0 80 #define N_VSS_SCL_SCL 0x30
Info 0:d2cb480cd5e0 81 #define N_VSS_SCL_SDA 0x32
Info 0:d2cb480cd5e0 82 #define N_VSS_SDA_SCL 0x34
Info 0:d2cb480cd5e0 83 #define N_VSS_SDA_SDA 0x36
Info 0:d2cb480cd5e0 84 #define N_VDD_SCL_SCL 0x38
Info 0:d2cb480cd5e0 85 #define N_VDD_SCL_SDA 0x3A
Info 0:d2cb480cd5e0 86 #define N_VDD_SDA_SCL 0x3C
Info 0:d2cb480cd5e0 87 #define N_VDD_SDA_SDA 0x3E
Info 0:d2cb480cd5e0 88 #define N_VSS_VSS_VSS 0x40
Info 0:d2cb480cd5e0 89 #define N_VSS_VSS_VDD 0x42
Info 0:d2cb480cd5e0 90 #define N_VSS_VDD_VSS 0x44
Info 0:d2cb480cd5e0 91 #define N_VSS_VDD_VDD 0x46
Info 0:d2cb480cd5e0 92 #define N_VDD_VSS_VSS 0x48
Info 0:d2cb480cd5e0 93 #define N_VDD_VSS_VDD 0x4A
Info 0:d2cb480cd5e0 94 #define N_VDD_VDD_VSS 0x4C
Info 0:d2cb480cd5e0 95 #define N_VDD_VDD_VDD 0x4E
Info 0:d2cb480cd5e0 96 #define N_VSS_VSS_SCL 0x50
Info 0:d2cb480cd5e0 97 #define N_VSS_VSS_SDA 0x52
Info 0:d2cb480cd5e0 98 #define N_VSS_VDD_SCL 0x54
Info 0:d2cb480cd5e0 99 #define N_VSS_VDD_SDA 0x56
Info 0:d2cb480cd5e0 100 #define N_VDD_VSS_SCL 0x58
Info 0:d2cb480cd5e0 101 #define N_VDD_VSS_SDA 0x5A
Info 0:d2cb480cd5e0 102 #define N_VDD_VDD_SCL 0x5C
Info 0:d2cb480cd5e0 103 #define N_VDD_VDD_SDA 0x5E
Info 0:d2cb480cd5e0 104 #define N_SCL_SCL_VSS 0xA0
Info 0:d2cb480cd5e0 105 #define N_SCL_SCL_VDD 0xA2
Info 0:d2cb480cd5e0 106 #define N_SCL_SDA_VSS 0xA4
Info 0:d2cb480cd5e0 107 #define N_SCL_SDA_VDD 0xA6
Info 0:d2cb480cd5e0 108 #define N_SDA_SCL_VSS 0xA8
Info 0:d2cb480cd5e0 109 #define N_SDA_SCL_VDD 0xAA
Info 0:d2cb480cd5e0 110 #define N_SDA_SDA_VSS 0xAC
Info 0:d2cb480cd5e0 111 #define N_SDA_SDA_VDD 0xAE
Info 0:d2cb480cd5e0 112 #define N_SCL_SCL_SCL 0xB0
Info 0:d2cb480cd5e0 113 #define N_SCL_SCL_SDA 0xB2
Info 0:d2cb480cd5e0 114 #define N_SCL_SDA_SCL 0xB4
Info 0:d2cb480cd5e0 115 #define N_SCL_SDA_SDA 0xB6
Info 0:d2cb480cd5e0 116 #define N_SDA_SCL_SCL 0xB8
Info 0:d2cb480cd5e0 117 #define N_SDA_SCL_SDA 0xBA
Info 0:d2cb480cd5e0 118 #define N_SDA_SDA_SCL 0xBC
Info 0:d2cb480cd5e0 119 #define N_SDA_SDA_SDA 0xBE
Info 0:d2cb480cd5e0 120 #define N_SCL_VSS_VSS 0xC0
Info 0:d2cb480cd5e0 121 #define N_SCL_VSS_VDD 0xC2
Info 0:d2cb480cd5e0 122 #define N_SCL_VDD_VSS 0xC4
Info 0:d2cb480cd5e0 123 #define N_SCL_VDD_VDD 0xC6
Info 0:d2cb480cd5e0 124 #define N_SDA_VSS_VSS 0xC8
Info 0:d2cb480cd5e0 125 #define N_SDA_VSS_VDD 0xCA
Info 0:d2cb480cd5e0 126 #define N_SDA_VDD_VSS 0xCC
Info 0:d2cb480cd5e0 127 #define N_SDA_VDD_VDD 0xCE
Info 0:d2cb480cd5e0 128 #define N_SCL_VSS_SCL 0xE0
Info 0:d2cb480cd5e0 129 #define N_SCL_VSS_SDA 0xE2
Info 0:d2cb480cd5e0 130 #define N_SCL_VDD_SCL 0xE4
Info 0:d2cb480cd5e0 131 #define N_SCL_VDD_SDA 0xE6
Info 0:d2cb480cd5e0 132 #define N_SDA_VSS_SCL 0xE8
Info 0:d2cb480cd5e0 133 #define N_SDA_VSS_SDA 0xEA
Info 0:d2cb480cd5e0 134 #define N_SDA_VDD_SCL 0xEC
Info 0:d2cb480cd5e0 135 #define N_SDA_VDD_SDA 0xEE
Info 0:d2cb480cd5e0 136
Info 0:d2cb480cd5e0 137
Info 0:d2cb480cd5e0 138 //PCA9674A
Info 0:d2cb480cd5e0 139 //VSS = GND VDD = +3.3V
Info 0:d2cb480cd5e0 140 //AD2 AD1 AD0
Info 0:d2cb480cd5e0 141 #define A_VSS_SCL_VSS 0x10
Info 0:d2cb480cd5e0 142 #define A_VSS_SCL_VDD 0x12
Info 0:d2cb480cd5e0 143 #define A_VSS_SDA_VSS 0x14
Info 0:d2cb480cd5e0 144 #define A_VSS_SDA_VDD 0x16
Info 0:d2cb480cd5e0 145 #define A_VDD_SCL_VSS 0x18
Info 0:d2cb480cd5e0 146 #define A_VDD_SCL_VDD 0x1A
Info 0:d2cb480cd5e0 147 #define A_VDD_SDA_VSS 0x1C
Info 0:d2cb480cd5e0 148 #define A_VDD_SDA_VDD 0x1E
Info 0:d2cb480cd5e0 149 #define A_VSS_SCL_SCL 0x60
Info 0:d2cb480cd5e0 150 #define A_VSS_SCL_SDA 0x62
Info 0:d2cb480cd5e0 151 #define A_VSS_SDA_SCL 0x64
Info 0:d2cb480cd5e0 152 #define A_VSS_SDA_SDA 0x66
Info 0:d2cb480cd5e0 153 #define A_VDD_SCL_SCL 0x68
Info 0:d2cb480cd5e0 154 #define A_VDD_SCL_SDA 0x6A
Info 0:d2cb480cd5e0 155 #define A_VDD_SDA_SCL 0x6C
Info 0:d2cb480cd5e0 156 #define A_VDD_SDA_SDA 0x6E
Info 0:d2cb480cd5e0 157 #define A_VSS_VSS_VSS 0x70
Info 0:d2cb480cd5e0 158 #define A_VSS_VSS_VDD 0x72
Info 0:d2cb480cd5e0 159 #define A_VSS_VDD_VSS 0x74
Info 0:d2cb480cd5e0 160 #define A_VSS_VDD_VDD 0x76
Info 0:d2cb480cd5e0 161 //#define A_VDD_VSS_VSS 0x78 //This is baseboard address. It is reserved.
Info 0:d2cb480cd5e0 162 #define A_VDD_VSS_VDD 0x7A
Info 0:d2cb480cd5e0 163 #define A_VDD_VDD_VSS 0x7C
Info 0:d2cb480cd5e0 164 #define A_VDD_VDD_VDD 0x7E
Info 0:d2cb480cd5e0 165 #define A_VSS_VSS_SCL 0x80
Info 0:d2cb480cd5e0 166 #define A_VSS_VSS_SDA 0x82
Info 0:d2cb480cd5e0 167 #define A_VSS_VDD_SCL 0x84
Info 0:d2cb480cd5e0 168 #define A_VSS_VDD_SDA 0x86
Info 0:d2cb480cd5e0 169 #define A_VDD_VSS_SCL 0x88
Info 0:d2cb480cd5e0 170 #define A_VDD_VSS_SDA 0x8A
Info 0:d2cb480cd5e0 171 #define A_VDD_VDD_SCL 0x8C
Info 0:d2cb480cd5e0 172 #define A_VDD_VDD_SDA 0x8E
Info 0:d2cb480cd5e0 173 #define A_SCL_SCL_VSS 0x90
Info 0:d2cb480cd5e0 174 #define A_SCL_SCL_VDD 0x92
Info 0:d2cb480cd5e0 175 #define A_SCL_SDA_VSS 0x94
Info 0:d2cb480cd5e0 176 #define A_SCL_SDA_VDD 0x96
Info 0:d2cb480cd5e0 177 #define A_SDA_SCL_VSS 0x98
Info 0:d2cb480cd5e0 178 #define A_SDA_SCL_VDD 0x9A
Info 0:d2cb480cd5e0 179 #define A_SDA_SDA_VSS 0x9C
Info 0:d2cb480cd5e0 180 #define A_SDA_SDA_VDD 0x9E
Info 0:d2cb480cd5e0 181 #define A_SCL_SCL_SCL 0xD0
Info 0:d2cb480cd5e0 182 #define A_SCL_SCL_SDA 0xD2
Info 0:d2cb480cd5e0 183 #define A_SCL_SDA_SCL 0xD4
Info 0:d2cb480cd5e0 184 #define A_SCL_SDA_SDA 0xD6
Info 0:d2cb480cd5e0 185 #define A_SDA_SCL_SCL 0xD8
Info 0:d2cb480cd5e0 186 #define A_SDA_SCL_SDA 0xDA
Info 0:d2cb480cd5e0 187 #define A_SDA_SDA_SCL 0xDC
Info 0:d2cb480cd5e0 188 #define A_SDA_SDA_SDA 0xDE
Info 0:d2cb480cd5e0 189 #define A_SCL_VSS_VSS 0xF0
Info 0:d2cb480cd5e0 190 #define A_SCL_VSS_VDD 0xF2
Info 0:d2cb480cd5e0 191 #define A_SCL_VDD_VSS 0xF4
Info 0:d2cb480cd5e0 192 #define A_SCL_VDD_VDD 0xF6
Info 0:d2cb480cd5e0 193 #define A_SDA_VSS_VSS 0xF8
Info 0:d2cb480cd5e0 194 #define A_SDA_VSS_VDD 0xFA
Info 0:d2cb480cd5e0 195 #define A_SDA_VDD_VSS 0xFC
Info 0:d2cb480cd5e0 196 #define A_SDA_VDD_VDD 0xFE
Info 0:d2cb480cd5e0 197 #define A_SCL_VSS_SCL 0x00
Info 0:d2cb480cd5e0 198 #define A_SCL_VSS_SDA 0x02
Info 0:d2cb480cd5e0 199 #define A_SCL_VDD_SCL 0x04
Info 0:d2cb480cd5e0 200 #define A_SCL_VDD_SDA 0x06
Info 0:d2cb480cd5e0 201 #define A_SDA_VSS_SCL 0x08
Info 0:d2cb480cd5e0 202 #define A_SDA_VSS_SDA 0x0A
Info 0:d2cb480cd5e0 203 #define A_SDA_VDD_SCL 0x0C
Info 0:d2cb480cd5e0 204 #define A_SDA_VDD_SDA 0x0E
Info 0:d2cb480cd5e0 205
Info 0:d2cb480cd5e0 206