detail : http://www.mcugear.com/
You need lib of mbed and textLCD.
mbed と textLCDのライブラリが必要です。
MCUGear.cpp@1:bbcba1a79e7b, 2013-10-03 (annotated)
- Committer:
- Info
- Date:
- Thu Oct 03 09:21:14 2013 +0000
- Revision:
- 1:bbcba1a79e7b
- Parent:
- 0:d2cb480cd5e0
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Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Info | 0:d2cb480cd5e0 | 1 | /* MCU Gear Library, only for testing MCUGear without any circuit you connected. |
Info | 0:d2cb480cd5e0 | 2 | * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/ |
Info | 0:d2cb480cd5e0 | 3 | * |
Info | 0:d2cb480cd5e0 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
Info | 0:d2cb480cd5e0 | 5 | * of this software and associated documentation files (the "Software"), to deal |
Info | 0:d2cb480cd5e0 | 6 | * in the Software without restriction, including without limitation the rights |
Info | 0:d2cb480cd5e0 | 7 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
Info | 0:d2cb480cd5e0 | 8 | * copies of the Software, and to permit persons to whom the Software is |
Info | 0:d2cb480cd5e0 | 9 | * furnished to do so, subject to the following conditions: |
Info | 0:d2cb480cd5e0 | 10 | * |
Info | 0:d2cb480cd5e0 | 11 | * The above copyright notice and this permission notice shall be included in |
Info | 0:d2cb480cd5e0 | 12 | * all copies or substantial portions of the Software. |
Info | 0:d2cb480cd5e0 | 13 | * |
Info | 0:d2cb480cd5e0 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
Info | 0:d2cb480cd5e0 | 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
Info | 0:d2cb480cd5e0 | 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
Info | 0:d2cb480cd5e0 | 17 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
Info | 0:d2cb480cd5e0 | 18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
Info | 0:d2cb480cd5e0 | 19 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
Info | 0:d2cb480cd5e0 | 20 | * THE SOFTWARE. |
Info | 0:d2cb480cd5e0 | 21 | */ |
Info | 0:d2cb480cd5e0 | 22 | |
Info | 0:d2cb480cd5e0 | 23 | |
Info | 0:d2cb480cd5e0 | 24 | #include "mbed.h" |
Info | 0:d2cb480cd5e0 | 25 | #include "MCUGear.h" |
Info | 0:d2cb480cd5e0 | 26 | #include "MCUGearBase.h" |
Info | 0:d2cb480cd5e0 | 27 | |
Info | 0:d2cb480cd5e0 | 28 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 29 | Serial MCUGear_pc(USBTX, USBRX); // tx, rx |
Info | 0:d2cb480cd5e0 | 30 | #endif |
Info | 0:d2cb480cd5e0 | 31 | |
Info | 0:d2cb480cd5e0 | 32 | |
Info | 0:d2cb480cd5e0 | 33 | unsigned char Layer[12]; |
Info | 0:d2cb480cd5e0 | 34 | unsigned char BankSetting[12][32]; |
Info | 0:d2cb480cd5e0 | 35 | unsigned char BankAndInPins[7][20]; |
Info | 0:d2cb480cd5e0 | 36 | |
Info | 0:d2cb480cd5e0 | 37 | unsigned char NowBank; |
Info | 0:d2cb480cd5e0 | 38 | |
Info | 0:d2cb480cd5e0 | 39 | //init |
Info | 0:d2cb480cd5e0 | 40 | //#ifdef BANK_MODE |
Info | 0:d2cb480cd5e0 | 41 | MCUGear::MCUGear(PinName scl, PinName sda, char addr, char NumberOfPin) |
Info | 0:d2cb480cd5e0 | 42 | : _i2c(scl, sda) { |
Info | 0:d2cb480cd5e0 | 43 | _i2c.frequency(FPGA_I2C_CLOCK); |
Info | 0:d2cb480cd5e0 | 44 | _addr = addr; |
Info | 0:d2cb480cd5e0 | 45 | data = 0x00; |
Info | 0:d2cb480cd5e0 | 46 | flgReg = 0; |
Info | 0:d2cb480cd5e0 | 47 | NowBank = 0; |
Info | 0:d2cb480cd5e0 | 48 | numPin = NumberOfPin; |
Info | 0:d2cb480cd5e0 | 49 | // numCon = ConnectorNumber; |
Info | 0:d2cb480cd5e0 | 50 | if(numPin<=4){ |
Info | 0:d2cb480cd5e0 | 51 | numCon = 1; |
Info | 0:d2cb480cd5e0 | 52 | }else if((numPin > 4)&&(numPin <= 8)){ |
Info | 0:d2cb480cd5e0 | 53 | numCon = 2; |
Info | 0:d2cb480cd5e0 | 54 | }else if(numPin > 8){ |
Info | 0:d2cb480cd5e0 | 55 | numCon = 3; |
Info | 0:d2cb480cd5e0 | 56 | }else{ |
Info | 0:d2cb480cd5e0 | 57 | ;//error |
Info | 0:d2cb480cd5e0 | 58 | } |
Info | 0:d2cb480cd5e0 | 59 | |
Info | 0:d2cb480cd5e0 | 60 | write(0xff); |
Info | 0:d2cb480cd5e0 | 61 | |
Info | 0:d2cb480cd5e0 | 62 | } |
Info | 0:d2cb480cd5e0 | 63 | /* |
Info | 0:d2cb480cd5e0 | 64 | #else |
Info | 0:d2cb480cd5e0 | 65 | MCUGear::MCUGear(PinName scl, PinName sda, char a) |
Info | 0:d2cb480cd5e0 | 66 | : _i2c(scl, sda) { |
Info | 0:d2cb480cd5e0 | 67 | _i2c.frequency(FPGA_I2C_CLOCK); |
Info | 0:d2cb480cd5e0 | 68 | _addr = a; |
Info | 0:d2cb480cd5e0 | 69 | Bank = 0; |
Info | 0:d2cb480cd5e0 | 70 | data = 0x00; |
Info | 0:d2cb480cd5e0 | 71 | flgReg = 0; |
Info | 0:d2cb480cd5e0 | 72 | } |
Info | 0:d2cb480cd5e0 | 73 | |
Info | 0:d2cb480cd5e0 | 74 | #endif |
Info | 0:d2cb480cd5e0 | 75 | */ |
Info | 0:d2cb480cd5e0 | 76 | |
Info | 0:d2cb480cd5e0 | 77 | //insert data function |
Info | 0:d2cb480cd5e0 | 78 | |
Info | 0:d2cb480cd5e0 | 79 | void MCUGear::savePinSetting(uint8_t number, unsigned char CPUPin,unsigned char Direction ,unsigned char ModulePin){ |
Info | 0:d2cb480cd5e0 | 80 | ip[number] = CPUPin; |
Info | 0:d2cb480cd5e0 | 81 | op[number] = (Direction|ModulePin); |
Info | 0:d2cb480cd5e0 | 82 | |
Info | 0:d2cb480cd5e0 | 83 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 84 | MCUGear_pc.printf("ModulePin = %x :op[%d] = %x : ip[%d] = %x\n",ModulePin, number, op[number], number, ip[number]); |
Info | 0:d2cb480cd5e0 | 85 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 86 | //MCUGear_pc.printf("sizeof(ModulePin) = %ubyte\n",sizeof(ModulePin)); |
Info | 0:d2cb480cd5e0 | 87 | //wait(0.1); |
Info | 0:d2cb480cd5e0 | 88 | #endif |
Info | 0:d2cb480cd5e0 | 89 | |
Info | 0:d2cb480cd5e0 | 90 | } |
Info | 0:d2cb480cd5e0 | 91 | /* |
Info | 0:d2cb480cd5e0 | 92 | uint8_t MCUGear::disconnectModule(void){ |
Info | 0:d2cb480cd5e0 | 93 | |
Info | 0:d2cb480cd5e0 | 94 | write(0xff); //close module gate |
Info | 0:d2cb480cd5e0 | 95 | |
Info | 0:d2cb480cd5e0 | 96 | if(Bank == 0){ |
Info | 0:d2cb480cd5e0 | 97 | fpga_write(0x0c,(0|0x80));//regist - Delete all connection on Bank 0. |
Info | 0:d2cb480cd5e0 | 98 | wait(0.001); |
Info | 0:d2cb480cd5e0 | 99 | fpga_write(0x10, 0);//enable |
Info | 0:d2cb480cd5e0 | 100 | } |
Info | 0:d2cb480cd5e0 | 101 | |
Info | 0:d2cb480cd5e0 | 102 | return 1; |
Info | 0:d2cb480cd5e0 | 103 | |
Info | 0:d2cb480cd5e0 | 104 | } |
Info | 0:d2cb480cd5e0 | 105 | */ |
Info | 0:d2cb480cd5e0 | 106 | uint8_t MCUGear::disconnectModule(void){ |
Info | 0:d2cb480cd5e0 | 107 | |
Info | 0:d2cb480cd5e0 | 108 | write(0xff); //close module gate |
Info | 0:d2cb480cd5e0 | 109 | |
Info | 0:d2cb480cd5e0 | 110 | if(Bank == 0){ |
Info | 0:d2cb480cd5e0 | 111 | |
Info | 0:d2cb480cd5e0 | 112 | //#ifdef test |
Info | 0:d2cb480cd5e0 | 113 | fpga_write(0x0c,(Bank|0x80));//regist - Delete all connection on Bank 0. |
Info | 0:d2cb480cd5e0 | 114 | wait(0.001); |
Info | 0:d2cb480cd5e0 | 115 | fpga_write(0x10, Bank);//enable |
Info | 0:d2cb480cd5e0 | 116 | /*#else |
Info | 0:d2cb480cd5e0 | 117 | int i=0; |
Info | 0:d2cb480cd5e0 | 118 | |
Info | 0:d2cb480cd5e0 | 119 | fpga_write(0x0c, 0);//regist |
Info | 0:d2cb480cd5e0 | 120 | //Rest all IO connction on Bank 0. |
Info | 0:d2cb480cd5e0 | 121 | |
Info | 0:d2cb480cd5e0 | 122 | for(i=0; i<16; ++i){ |
Info | 0:d2cb480cd5e0 | 123 | fpga_write(ip[i], (IO_REG_DISABLE | op[i])); |
Info | 0:d2cb480cd5e0 | 124 | wait(0.0001); |
Info | 0:d2cb480cd5e0 | 125 | } |
Info | 0:d2cb480cd5e0 | 126 | fpga_write(0x10, (Bank|0x40));//enable |
Info | 0:d2cb480cd5e0 | 127 | |
Info | 0:d2cb480cd5e0 | 128 | #endif |
Info | 0:d2cb480cd5e0 | 129 | */ |
Info | 0:d2cb480cd5e0 | 130 | } |
Info | 0:d2cb480cd5e0 | 131 | return 1; |
Info | 0:d2cb480cd5e0 | 132 | |
Info | 0:d2cb480cd5e0 | 133 | } |
Info | 0:d2cb480cd5e0 | 134 | |
Info | 0:d2cb480cd5e0 | 135 | uint8_t MCUGear::connectModule(void){ |
Info | 0:d2cb480cd5e0 | 136 | |
Info | 0:d2cb480cd5e0 | 137 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 138 | MCUGear_pc.printf("_addr = %x, [NowBank = %d ,Bank = %d] \n",_addr, NowBank, Bank); |
Info | 0:d2cb480cd5e0 | 139 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 140 | #endif |
Info | 0:d2cb480cd5e0 | 141 | |
Info | 0:d2cb480cd5e0 | 142 | int i=0; |
Info | 0:d2cb480cd5e0 | 143 | |
Info | 0:d2cb480cd5e0 | 144 | if(flgReg==0){ |
Info | 0:d2cb480cd5e0 | 145 | fpga_write(0x0c,Bank);//init regist |
Info | 0:d2cb480cd5e0 | 146 | |
Info | 0:d2cb480cd5e0 | 147 | }else{ |
Info | 0:d2cb480cd5e0 | 148 | if(Bank == NowBank){ |
Info | 0:d2cb480cd5e0 | 149 | ; //Nothing to do |
Info | 0:d2cb480cd5e0 | 150 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 151 | MCUGear_pc.printf("_Nothing to do \n"); |
Info | 0:d2cb480cd5e0 | 152 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 153 | #endif |
Info | 0:d2cb480cd5e0 | 154 | }else{ |
Info | 0:d2cb480cd5e0 | 155 | fpga_write(0x0c,Bank);//regist |
Info | 0:d2cb480cd5e0 | 156 | } |
Info | 0:d2cb480cd5e0 | 157 | } |
Info | 0:d2cb480cd5e0 | 158 | |
Info | 0:d2cb480cd5e0 | 159 | |
Info | 0:d2cb480cd5e0 | 160 | if(Bank != 0){ //Bank is between 1-7 |
Info | 0:d2cb480cd5e0 | 161 | if(flgReg==0){ //Onetime IO connections |
Info | 0:d2cb480cd5e0 | 162 | |
Info | 0:d2cb480cd5e0 | 163 | for(i=0; i<16; ++i){ |
Info | 0:d2cb480cd5e0 | 164 | fpga_write(ip[i], (IO_REG_EN | op[i])); |
Info | 0:d2cb480cd5e0 | 165 | wait(0.0001); |
Info | 0:d2cb480cd5e0 | 166 | |
Info | 0:d2cb480cd5e0 | 167 | if((numCon==1)&&(i==3)){ |
Info | 0:d2cb480cd5e0 | 168 | write(0xfe); //1111 1110 |
Info | 0:d2cb480cd5e0 | 169 | break; |
Info | 0:d2cb480cd5e0 | 170 | |
Info | 0:d2cb480cd5e0 | 171 | }else if((numCon==2)&&(i==7)){ |
Info | 0:d2cb480cd5e0 | 172 | write(0xfc); //1111 1100 |
Info | 0:d2cb480cd5e0 | 173 | break; |
Info | 0:d2cb480cd5e0 | 174 | |
Info | 0:d2cb480cd5e0 | 175 | }else if((numCon==3)&&(i==11)){ |
Info | 0:d2cb480cd5e0 | 176 | write(0xf8); //1111 1000 |
Info | 0:d2cb480cd5e0 | 177 | break; |
Info | 0:d2cb480cd5e0 | 178 | |
Info | 0:d2cb480cd5e0 | 179 | }else if(i > 12){ |
Info | 0:d2cb480cd5e0 | 180 | return 2;//error |
Info | 0:d2cb480cd5e0 | 181 | } |
Info | 0:d2cb480cd5e0 | 182 | } |
Info | 0:d2cb480cd5e0 | 183 | |
Info | 0:d2cb480cd5e0 | 184 | fpga_write(0x10,Bank);//init regist/////// |
Info | 0:d2cb480cd5e0 | 185 | flgReg = 1; |
Info | 0:d2cb480cd5e0 | 186 | }else{ //only change module gate |
Info | 0:d2cb480cd5e0 | 187 | |
Info | 0:d2cb480cd5e0 | 188 | if(numCon==1){ |
Info | 0:d2cb480cd5e0 | 189 | write(0xfe); //1111 1110 |
Info | 0:d2cb480cd5e0 | 190 | |
Info | 0:d2cb480cd5e0 | 191 | }else if(numCon==2){ |
Info | 0:d2cb480cd5e0 | 192 | write(0xfc); //1111 1100 |
Info | 0:d2cb480cd5e0 | 193 | |
Info | 0:d2cb480cd5e0 | 194 | }else if(numCon==3){ |
Info | 0:d2cb480cd5e0 | 195 | write(0xf8); //1111 1000 |
Info | 0:d2cb480cd5e0 | 196 | |
Info | 0:d2cb480cd5e0 | 197 | }else{ |
Info | 0:d2cb480cd5e0 | 198 | return 2;//error |
Info | 0:d2cb480cd5e0 | 199 | } |
Info | 0:d2cb480cd5e0 | 200 | |
Info | 0:d2cb480cd5e0 | 201 | } |
Info | 0:d2cb480cd5e0 | 202 | //#else |
Info | 0:d2cb480cd5e0 | 203 | }else{ //You need to change IO connections evrytime on Bank 0. |
Info | 0:d2cb480cd5e0 | 204 | for(i=0; i<16; ++i){ |
Info | 0:d2cb480cd5e0 | 205 | fpga_write(ip[i], (IO_REG_EN | op[i])); |
Info | 0:d2cb480cd5e0 | 206 | wait(0.0001); |
Info | 0:d2cb480cd5e0 | 207 | |
Info | 0:d2cb480cd5e0 | 208 | if((numCon==1)&&(i==3)){ |
Info | 0:d2cb480cd5e0 | 209 | write(0xfe); //1111 1110 |
Info | 0:d2cb480cd5e0 | 210 | break; |
Info | 0:d2cb480cd5e0 | 211 | |
Info | 0:d2cb480cd5e0 | 212 | }else if((numCon==2)&&(i==7)){ |
Info | 0:d2cb480cd5e0 | 213 | write(0xfc); //1111 1100 |
Info | 0:d2cb480cd5e0 | 214 | break; |
Info | 0:d2cb480cd5e0 | 215 | |
Info | 0:d2cb480cd5e0 | 216 | }else if((numCon==3)&&(i==11)){ |
Info | 0:d2cb480cd5e0 | 217 | write(0xf8); //1111 1000 |
Info | 0:d2cb480cd5e0 | 218 | break; |
Info | 0:d2cb480cd5e0 | 219 | |
Info | 0:d2cb480cd5e0 | 220 | }else if(i > 12){ |
Info | 0:d2cb480cd5e0 | 221 | return 2;//error |
Info | 0:d2cb480cd5e0 | 222 | } |
Info | 0:d2cb480cd5e0 | 223 | } |
Info | 0:d2cb480cd5e0 | 224 | fpga_write(0x10,Bank);//init regist/////// |
Info | 0:d2cb480cd5e0 | 225 | } |
Info | 0:d2cb480cd5e0 | 226 | //#endif |
Info | 0:d2cb480cd5e0 | 227 | /* |
Info | 0:d2cb480cd5e0 | 228 | if(flgReg==0){ |
Info | 0:d2cb480cd5e0 | 229 | flgReg = 1; |
Info | 0:d2cb480cd5e0 | 230 | fpga_write(0x10,Bank);//init regist |
Info | 0:d2cb480cd5e0 | 231 | |
Info | 0:d2cb480cd5e0 | 232 | }else{ |
Info | 0:d2cb480cd5e0 | 233 | if(Bank == NowBank){ |
Info | 0:d2cb480cd5e0 | 234 | ; //Nothing to do |
Info | 0:d2cb480cd5e0 | 235 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 236 | MCUGear_pc.printf("_Nothing to do \n"); |
Info | 0:d2cb480cd5e0 | 237 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 238 | #endif |
Info | 0:d2cb480cd5e0 | 239 | }else{ |
Info | 0:d2cb480cd5e0 | 240 | fpga_write(0x10,Bank);//regist |
Info | 0:d2cb480cd5e0 | 241 | } |
Info | 0:d2cb480cd5e0 | 242 | } |
Info | 0:d2cb480cd5e0 | 243 | */ |
Info | 0:d2cb480cd5e0 | 244 | |
Info | 0:d2cb480cd5e0 | 245 | /* |
Info | 0:d2cb480cd5e0 | 246 | if((Bank != NowBank)){ |
Info | 0:d2cb480cd5e0 | 247 | fpga_write(0x10, Bank); //Bank enable |
Info | 0:d2cb480cd5e0 | 248 | } |
Info | 0:d2cb480cd5e0 | 249 | */ |
Info | 0:d2cb480cd5e0 | 250 | NowBank = Bank; //set NowBank |
Info | 0:d2cb480cd5e0 | 251 | |
Info | 0:d2cb480cd5e0 | 252 | return 1; |
Info | 0:d2cb480cd5e0 | 253 | } |
Info | 0:d2cb480cd5e0 | 254 | |
Info | 0:d2cb480cd5e0 | 255 | |
Info | 0:d2cb480cd5e0 | 256 | |
Info | 0:d2cb480cd5e0 | 257 | void MCUGear::fpga_write(unsigned char adr, unsigned char data) { |
Info | 0:d2cb480cd5e0 | 258 | char cmd[2]; |
Info | 0:d2cb480cd5e0 | 259 | cmd[0] = adr; |
Info | 0:d2cb480cd5e0 | 260 | cmd[1] = data; |
Info | 0:d2cb480cd5e0 | 261 | _i2c.write(FPGA_I2C_ADR, cmd, 2); |
Info | 0:d2cb480cd5e0 | 262 | //wait(0.01); |
Info | 0:d2cb480cd5e0 | 263 | //pc.printf("fpga write adr:%x data:%x\n", adr,data); |
Info | 0:d2cb480cd5e0 | 264 | } |
Info | 0:d2cb480cd5e0 | 265 | |
Info | 0:d2cb480cd5e0 | 266 | |
Info | 0:d2cb480cd5e0 | 267 | void MCUGear::set_addr(char s){ |
Info | 0:d2cb480cd5e0 | 268 | _addr = s; |
Info | 0:d2cb480cd5e0 | 269 | } |
Info | 0:d2cb480cd5e0 | 270 | |
Info | 0:d2cb480cd5e0 | 271 | void MCUGear::set_data(char c){ |
Info | 0:d2cb480cd5e0 | 272 | data = c; |
Info | 0:d2cb480cd5e0 | 273 | } |
Info | 0:d2cb480cd5e0 | 274 | |
Info | 0:d2cb480cd5e0 | 275 | //send I2C signal function |
Info | 0:d2cb480cd5e0 | 276 | void MCUGear::write(char c){ |
Info | 0:d2cb480cd5e0 | 277 | |
Info | 0:d2cb480cd5e0 | 278 | char cmd[1]; |
Info | 0:d2cb480cd5e0 | 279 | cmd[0] = c; |
Info | 0:d2cb480cd5e0 | 280 | _i2c.write(_addr, cmd, 1); |
Info | 0:d2cb480cd5e0 | 281 | //wait(0.01); |
Info | 0:d2cb480cd5e0 | 282 | |
Info | 0:d2cb480cd5e0 | 283 | } |
Info | 0:d2cb480cd5e0 | 284 | |
Info | 0:d2cb480cd5e0 | 285 | ////detect module |
Info | 0:d2cb480cd5e0 | 286 | void MCUGear::detect_module(uint8_t *fio) { |
Info | 0:d2cb480cd5e0 | 287 | int i; |
Info | 0:d2cb480cd5e0 | 288 | uint8_t pnum=0xff; |
Info | 0:d2cb480cd5e0 | 289 | uint8_t iio; |
Info | 0:d2cb480cd5e0 | 290 | //1pin GND |
Info | 0:d2cb480cd5e0 | 291 | |
Info | 0:d2cb480cd5e0 | 292 | write(0x7f); //0111 1111 |
Info | 0:d2cb480cd5e0 | 293 | //wait(0.1); |
Info | 0:d2cb480cd5e0 | 294 | pnum =fpga_read(FPGA_I2C_ADR,FPGA_DETECT); |
Info | 0:d2cb480cd5e0 | 295 | |
Info | 0:d2cb480cd5e0 | 296 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 297 | wait(1); |
Info | 0:d2cb480cd5e0 | 298 | MCUGear_pc.printf("detected. port %d \n",pnum); |
Info | 0:d2cb480cd5e0 | 299 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 300 | #endif |
Info | 0:d2cb480cd5e0 | 301 | write(0xff); //1111 1111 |
Info | 0:d2cb480cd5e0 | 302 | |
Info | 0:d2cb480cd5e0 | 303 | iio = pnum; |
Info | 0:d2cb480cd5e0 | 304 | if(iio != 0xff){ |
Info | 0:d2cb480cd5e0 | 305 | //Resolve boundary value problem |
Info | 0:d2cb480cd5e0 | 306 | pinArrey[0] = iio; |
Info | 0:d2cb480cd5e0 | 307 | |
Info | 0:d2cb480cd5e0 | 308 | iio = iio + 4; |
Info | 0:d2cb480cd5e0 | 309 | |
Info | 0:d2cb480cd5e0 | 310 | if((iio > 44)){ |
Info | 0:d2cb480cd5e0 | 311 | iio = 0;; |
Info | 0:d2cb480cd5e0 | 312 | } |
Info | 0:d2cb480cd5e0 | 313 | pinArrey[1] = iio; |
Info | 0:d2cb480cd5e0 | 314 | |
Info | 0:d2cb480cd5e0 | 315 | |
Info | 0:d2cb480cd5e0 | 316 | iio = iio + 4; |
Info | 0:d2cb480cd5e0 | 317 | |
Info | 0:d2cb480cd5e0 | 318 | if((iio > 44)){ |
Info | 0:d2cb480cd5e0 | 319 | iio = 0; |
Info | 0:d2cb480cd5e0 | 320 | } |
Info | 0:d2cb480cd5e0 | 321 | pinArrey[2] = iio; |
Info | 0:d2cb480cd5e0 | 322 | |
Info | 0:d2cb480cd5e0 | 323 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 324 | MCUGear_pc.printf("detected. pinArrey[0] = %d \n",pinArrey[0]); |
Info | 0:d2cb480cd5e0 | 325 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 326 | #endif |
Info | 0:d2cb480cd5e0 | 327 | |
Info | 0:d2cb480cd5e0 | 328 | //makeCircuit(); |
Info | 0:d2cb480cd5e0 | 329 | } |
Info | 0:d2cb480cd5e0 | 330 | |
Info | 0:d2cb480cd5e0 | 331 | for(i=0;i<12;++i){ |
Info | 0:d2cb480cd5e0 | 332 | if(pnum+i>47){ |
Info | 0:d2cb480cd5e0 | 333 | fio[i] = pnum+i-48; |
Info | 0:d2cb480cd5e0 | 334 | }else{ |
Info | 0:d2cb480cd5e0 | 335 | fio[i] = pnum+i; |
Info | 0:d2cb480cd5e0 | 336 | } |
Info | 0:d2cb480cd5e0 | 337 | |
Info | 0:d2cb480cd5e0 | 338 | |
Info | 0:d2cb480cd5e0 | 339 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 340 | //MCUGear_pc.printf("detected. fio[%d] = %d \n",i,fio[i]); |
Info | 0:d2cb480cd5e0 | 341 | //wait(0.1); |
Info | 0:d2cb480cd5e0 | 342 | #endif |
Info | 0:d2cb480cd5e0 | 343 | |
Info | 0:d2cb480cd5e0 | 344 | } |
Info | 0:d2cb480cd5e0 | 345 | |
Info | 0:d2cb480cd5e0 | 346 | // return pnum; |
Info | 0:d2cb480cd5e0 | 347 | } |
Info | 0:d2cb480cd5e0 | 348 | |
Info | 0:d2cb480cd5e0 | 349 | |
Info | 0:d2cb480cd5e0 | 350 | |
Info | 0:d2cb480cd5e0 | 351 | ///making onecircuit |
Info | 0:d2cb480cd5e0 | 352 | void MCUGear::makeCircuit(void){ |
Info | 0:d2cb480cd5e0 | 353 | //unsigned char i = 0; |
Info | 0:d2cb480cd5e0 | 354 | char i = 0; |
Info | 0:d2cb480cd5e0 | 355 | unsigned char j = 0; |
Info | 0:d2cb480cd5e0 | 356 | int k = 0; |
Info | 0:d2cb480cd5e0 | 357 | unsigned char con = 0; |
Info | 0:d2cb480cd5e0 | 358 | unsigned char conNum2 = 0; |
Info | 0:d2cb480cd5e0 | 359 | unsigned char MaxLayer = 0; |
Info | 0:d2cb480cd5e0 | 360 | |
Info | 0:d2cb480cd5e0 | 361 | con = (pinArrey[0]/4)+1; //creat connector number |
Info | 0:d2cb480cd5e0 | 362 | |
Info | 0:d2cb480cd5e0 | 363 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 364 | MCUGear_pc.printf("makeCircuit con = (pinArrey[%d]/4)+1 = %d \n",i,con); |
Info | 0:d2cb480cd5e0 | 365 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 366 | #endif |
Info | 0:d2cb480cd5e0 | 367 | |
Info | 0:d2cb480cd5e0 | 368 | //find MaxLayer |
Info | 0:d2cb480cd5e0 | 369 | for(i=0; i<numCon; ++i){ |
Info | 0:d2cb480cd5e0 | 370 | if((con+i) > 12){ |
Info | 0:d2cb480cd5e0 | 371 | ++Layer[con + i - 12]; |
Info | 0:d2cb480cd5e0 | 372 | |
Info | 0:d2cb480cd5e0 | 373 | if(MaxLayer < Layer[con + i - 12]){ |
Info | 0:d2cb480cd5e0 | 374 | MaxLayer = Layer[con + i - 12]; |
Info | 0:d2cb480cd5e0 | 375 | } |
Info | 0:d2cb480cd5e0 | 376 | }else{ |
Info | 0:d2cb480cd5e0 | 377 | ++Layer[con + i]; |
Info | 0:d2cb480cd5e0 | 378 | |
Info | 0:d2cb480cd5e0 | 379 | if(MaxLayer < Layer[con + i]){ |
Info | 0:d2cb480cd5e0 | 380 | MaxLayer = Layer[con + i]; |
Info | 0:d2cb480cd5e0 | 381 | } |
Info | 0:d2cb480cd5e0 | 382 | } |
Info | 0:d2cb480cd5e0 | 383 | } |
Info | 0:d2cb480cd5e0 | 384 | |
Info | 0:d2cb480cd5e0 | 385 | //Check over rap CPU pins on a Bank |
Info | 0:d2cb480cd5e0 | 386 | //If it find over rap, set other layers. |
Info | 0:d2cb480cd5e0 | 387 | conNum2 = numCon * 4; |
Info | 0:d2cb480cd5e0 | 388 | |
Info | 0:d2cb480cd5e0 | 389 | for(i=0; i<20; ++i){ |
Info | 0:d2cb480cd5e0 | 390 | for(j=0; j<numPin; ++j){ |
Info | 0:d2cb480cd5e0 | 391 | if(BankAndInPins[MaxLayer][i] == ip[j]){ |
Info | 0:d2cb480cd5e0 | 392 | ++MaxLayer; |
Info | 0:d2cb480cd5e0 | 393 | |
Info | 0:d2cb480cd5e0 | 394 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 395 | MCUGear_pc.printf("CPU IO over rap! ++MaxLayer : %d \n",MaxLayer); |
Info | 0:d2cb480cd5e0 | 396 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 397 | #endif |
Info | 0:d2cb480cd5e0 | 398 | //i = 0x20; |
Info | 0:d2cb480cd5e0 | 399 | //j = numPin; |
Info | 0:d2cb480cd5e0 | 400 | //break; |
Info | 0:d2cb480cd5e0 | 401 | i = 0; |
Info | 0:d2cb480cd5e0 | 402 | j = 0; |
Info | 0:d2cb480cd5e0 | 403 | } |
Info | 0:d2cb480cd5e0 | 404 | } |
Info | 0:d2cb480cd5e0 | 405 | } |
Info | 0:d2cb480cd5e0 | 406 | |
Info | 0:d2cb480cd5e0 | 407 | //Save Datas |
Info | 0:d2cb480cd5e0 | 408 | for(j=0; j<conNum2; ++j){ |
Info | 0:d2cb480cd5e0 | 409 | k = (int)(ip[j]-0x80); |
Info | 0:d2cb480cd5e0 | 410 | BankAndInPins[MaxLayer][k] = ip[j]; |
Info | 0:d2cb480cd5e0 | 411 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 412 | MCUGear_pc.printf("BankAndInPins[%d][%d] = %x \n",MaxLayer,k,ip[j]); |
Info | 0:d2cb480cd5e0 | 413 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 414 | #endif |
Info | 0:d2cb480cd5e0 | 415 | } |
Info | 0:d2cb480cd5e0 | 416 | |
Info | 0:d2cb480cd5e0 | 417 | |
Info | 0:d2cb480cd5e0 | 418 | //save MaxLayer to all connectors |
Info | 0:d2cb480cd5e0 | 419 | for(i=0; i<numCon; ++i){ |
Info | 0:d2cb480cd5e0 | 420 | if(MaxLayer > Layer[con + i]){ |
Info | 0:d2cb480cd5e0 | 421 | Layer[con + i] = MaxLayer; |
Info | 0:d2cb480cd5e0 | 422 | } |
Info | 0:d2cb480cd5e0 | 423 | |
Info | 0:d2cb480cd5e0 | 424 | } |
Info | 0:d2cb480cd5e0 | 425 | |
Info | 0:d2cb480cd5e0 | 426 | |
Info | 0:d2cb480cd5e0 | 427 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 428 | MCUGear_pc.printf("MaxLayer = %d \n",MaxLayer); |
Info | 0:d2cb480cd5e0 | 429 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 430 | #endif |
Info | 0:d2cb480cd5e0 | 431 | |
Info | 0:d2cb480cd5e0 | 432 | for(i=0; i<numCon; ++i){ |
Info | 0:d2cb480cd5e0 | 433 | |
Info | 0:d2cb480cd5e0 | 434 | if((con + i)>12){ |
Info | 0:d2cb480cd5e0 | 435 | BankSetting[con + i - 12][MaxLayer] = _addr; |
Info | 0:d2cb480cd5e0 | 436 | |
Info | 0:d2cb480cd5e0 | 437 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 438 | MCUGear_pc.printf("BankSetting[CON %d][Layer %d] = %x \n",(con + i - 12),MaxLayer,_addr); |
Info | 0:d2cb480cd5e0 | 439 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 440 | #endif |
Info | 0:d2cb480cd5e0 | 441 | }else{ |
Info | 0:d2cb480cd5e0 | 442 | BankSetting[con + i][MaxLayer] = _addr; |
Info | 0:d2cb480cd5e0 | 443 | |
Info | 0:d2cb480cd5e0 | 444 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 445 | MCUGear_pc.printf("BankSetting[CON %d][Layer %d] = %x \n",(con + i),MaxLayer,_addr); |
Info | 0:d2cb480cd5e0 | 446 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 447 | #endif |
Info | 0:d2cb480cd5e0 | 448 | } |
Info | 0:d2cb480cd5e0 | 449 | } |
Info | 0:d2cb480cd5e0 | 450 | |
Info | 0:d2cb480cd5e0 | 451 | |
Info | 0:d2cb480cd5e0 | 452 | //make 0-6 BANKs others are chang single pin |
Info | 0:d2cb480cd5e0 | 453 | //MaxLayer = BANK No |
Info | 0:d2cb480cd5e0 | 454 | |
Info | 0:d2cb480cd5e0 | 455 | if(MaxLayer <= BankMaxNum){ |
Info | 0:d2cb480cd5e0 | 456 | fpga_write(0x0c, MaxLayer); //regist to Bank |
Info | 0:d2cb480cd5e0 | 457 | Bank = MaxLayer; |
Info | 0:d2cb480cd5e0 | 458 | }else{ |
Info | 0:d2cb480cd5e0 | 459 | Bank = 0; |
Info | 0:d2cb480cd5e0 | 460 | #ifdef DEBUG |
Info | 0:d2cb480cd5e0 | 461 | MCUGear_pc.printf("set Bank = 0\n"); |
Info | 0:d2cb480cd5e0 | 462 | wait(0.1); |
Info | 0:d2cb480cd5e0 | 463 | #endif |
Info | 0:d2cb480cd5e0 | 464 | |
Info | 0:d2cb480cd5e0 | 465 | } |
Info | 0:d2cb480cd5e0 | 466 | |
Info | 0:d2cb480cd5e0 | 467 | } |
Info | 0:d2cb480cd5e0 | 468 | |
Info | 0:d2cb480cd5e0 | 469 | |
Info | 0:d2cb480cd5e0 | 470 | |
Info | 0:d2cb480cd5e0 | 471 |