mille feuille / MCUGear

detail : http://www.mcugear.com/

You need lib of mbed and textLCD.

mbed と textLCDのライブラリが必要です。

MCUGearBase.h@0:d2cb480cd5e0, 2013-09-29 (annotated)

Committer:
Info
Date:
Sun Sep 29 10:16:02 2013 +0000
Revision:
0:d2cb480cd5e0
Ver1.0.0 MCUGear test program for mbed

; You should change the defines in common.h.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Info 0:d2cb480cd5e0 1 /* MCU Gear Library, only for testing MCUGear without any circuit you connected.
Info 0:d2cb480cd5e0 2 * Copyright (c) 2013, NestEgg Inc., http://www.mcugear.com/
Info 0:d2cb480cd5e0 3 *
Info 0:d2cb480cd5e0 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
Info 0:d2cb480cd5e0 5 * of this software and associated documentation files (the "Software"), to deal
Info 0:d2cb480cd5e0 6 * in the Software without restriction, including without limitation the rights
Info 0:d2cb480cd5e0 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
Info 0:d2cb480cd5e0 8 * copies of the Software, and to permit persons to whom the Software is
Info 0:d2cb480cd5e0 9 * furnished to do so, subject to the following conditions:
Info 0:d2cb480cd5e0 10 *
Info 0:d2cb480cd5e0 11 * The above copyright notice and this permission notice shall be included in
Info 0:d2cb480cd5e0 12 * all copies or substantial portions of the Software.
Info 0:d2cb480cd5e0 13 *
Info 0:d2cb480cd5e0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
Info 0:d2cb480cd5e0 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
Info 0:d2cb480cd5e0 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
Info 0:d2cb480cd5e0 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
Info 0:d2cb480cd5e0 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Info 0:d2cb480cd5e0 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
Info 0:d2cb480cd5e0 20 * THE SOFTWARE.
Info 0:d2cb480cd5e0 21 */
Info 0:d2cb480cd5e0 22
Info 0:d2cb480cd5e0 23 #include "common.h"
Info 0:d2cb480cd5e0 24
Info 0:d2cb480cd5e0 25
Info 0:d2cb480cd5e0 26 #define FPGA_SYSINFO_0 0x00
Info 0:d2cb480cd5e0 27 #define FPGA_SYSINFO_1 0x04
Info 0:d2cb480cd5e0 28 #define FPGA_ENABLE 0x08
Info 0:d2cb480cd5e0 29 #define FPGA_DETECT 0x14
Info 0:d2cb480cd5e0 30
Info 0:d2cb480cd5e0 31 /*
Info 0:d2cb480cd5e0 32 // cpu port mapping
Info 0:d2cb480cd5e0 33 #define P5 0
Info 0:d2cb480cd5e0 34 //
Info 0:d2cb480cd5e0 35 #define CON1_1 0
Info 0:d2cb480cd5e0 36 #define CON1_2 0
Info 0:d2cb480cd5e0 37 #define CON1_3 0
Info 0:d2cb480cd5e0 38 #define CON1_4 0
Info 0:d2cb480cd5e0 39 */
Info 0:d2cb480cd5e0 40 void fpga_write(int dev_adr,unsigned char adr, unsigned char data);
Info 0:d2cb480cd5e0 41 unsigned char fpga_read(int dev_adr,unsigned char adr);
Info 0:d2cb480cd5e0 42 void initBase(void);
Info 0:d2cb480cd5e0 43 int detect_module(char addr);
Info 0:d2cb480cd5e0 44
Info 0:d2cb480cd5e0 45
Info 0:d2cb480cd5e0 46 // FGPGA CPU I/O
Info 0:d2cb480cd5e0 47 typedef enum {
Info 0:d2cb480cd5e0 48
Info 0:d2cb480cd5e0 49 #ifdef LPC1768_mbed
Info 0:d2cb480cd5e0 50 IO_MBED_P15 = 0x80,
Info 0:d2cb480cd5e0 51 IO_MBED_P13,
Info 0:d2cb480cd5e0 52 IO_MBED_P16,
Info 0:d2cb480cd5e0 53 IO_MBED_P12,
Info 0:d2cb480cd5e0 54 IO_MBED_P5,
Info 0:d2cb480cd5e0 55 IO_MBED_P11,
Info 0:d2cb480cd5e0 56 IO_MBED_P23,
Info 0:d2cb480cd5e0 57 IO_MBED_P22,
Info 0:d2cb480cd5e0 58 IO_MBED_P26,
Info 0:d2cb480cd5e0 59 IO_MBED_P10,
Info 0:d2cb480cd5e0 60 IO_MBED_P21,
Info 0:d2cb480cd5e0 61 IO_MBED_P9,
Info 0:d2cb480cd5e0 62 IO_MBED_P6,
Info 0:d2cb480cd5e0 63 IO_MBED_P7,
Info 0:d2cb480cd5e0 64 IO_MBED_P8,
Info 0:d2cb480cd5e0 65 IO_MBED_P14,
Info 0:d2cb480cd5e0 66 IO_MBED_P24,
Info 0:d2cb480cd5e0 67 IO_MBED_P25,
Info 0:d2cb480cd5e0 68 IO_MBED_P28,
Info 0:d2cb480cd5e0 69 IO_MBED_P27
Info 0:d2cb480cd5e0 70 #endif
Info 0:d2cb480cd5e0 71
Info 0:d2cb480cd5e0 72 #ifdef FS_KL25Z
Info 0:d2cb480cd5e0 73
Info 0:d2cb480cd5e0 74 IO_MBED_PTA5 = 0x80,
Info 0:d2cb480cd5e0 75 IO_MBED_PTC8,
Info 0:d2cb480cd5e0 76 IO_MBED_PTC9,
Info 0:d2cb480cd5e0 77 IO_MBED_PTD5,
Info 0:d2cb480cd5e0 78 IO_MBED_PTA13,
Info 0:d2cb480cd5e0 79 IO_MBED_PTD2,
Info 0:d2cb480cd5e0 80 IO_MBED_PTB1,
Info 0:d2cb480cd5e0 81 IO_MBED_PTB2,
Info 0:d2cb480cd5e0 82 IO_MBED_PTA2,
Info 0:d2cb480cd5e0 83 IO_MBED_PTD4,
Info 0:d2cb480cd5e0 84 IO_MBED_PTB3,
Info 0:d2cb480cd5e0 85 IO_MBED_PTA12,
Info 0:d2cb480cd5e0 86 IO_MBED_PTD0,
Info 0:d2cb480cd5e0 87 IO_MBED_PTD3,
Info 0:d2cb480cd5e0 88 IO_MBED_PTD1,
Info 0:d2cb480cd5e0 89 IO_MBED_PTA4,
Info 0:d2cb480cd5e0 90 IO_MBED_PTB0,
Info 0:d2cb480cd5e0 91 IO_MBED_PTA1,
Info 0:d2cb480cd5e0 92 IO_MBED_PTE0, //SDA
Info 0:d2cb480cd5e0 93 IO_MBED_PTE1 //SCL
Info 0:d2cb480cd5e0 94 #endif
Info 0:d2cb480cd5e0 95
Info 0:d2cb480cd5e0 96 } en_cpu_io;
Info 0:d2cb480cd5e0 97
Info 0:d2cb480cd5e0 98 // FPGA EXT I/O
Info 0:d2cb480cd5e0 99 typedef enum {
Info 0:d2cb480cd5e0 100 IO_CON1_1 = 0,
Info 0:d2cb480cd5e0 101 IO_CON1_2,
Info 0:d2cb480cd5e0 102 IO_CON1_3,
Info 0:d2cb480cd5e0 103 IO_CON1_4,
Info 0:d2cb480cd5e0 104 IO_CON2_1,
Info 0:d2cb480cd5e0 105 IO_CON2_2,
Info 0:d2cb480cd5e0 106 IO_CON2_3,
Info 0:d2cb480cd5e0 107 IO_CON2_4,
Info 0:d2cb480cd5e0 108 IO_CON3_1,
Info 0:d2cb480cd5e0 109 IO_CON3_2,
Info 0:d2cb480cd5e0 110 IO_CON3_3,
Info 0:d2cb480cd5e0 111 IO_CON3_4,
Info 0:d2cb480cd5e0 112 IO_CON4_1,
Info 0:d2cb480cd5e0 113 IO_CON4_2,
Info 0:d2cb480cd5e0 114 IO_CON4_3,
Info 0:d2cb480cd5e0 115 IO_CON4_4,
Info 0:d2cb480cd5e0 116 IO_CON5_1,
Info 0:d2cb480cd5e0 117 IO_CON5_2,
Info 0:d2cb480cd5e0 118 IO_CON5_3,
Info 0:d2cb480cd5e0 119 IO_CON5_4,
Info 0:d2cb480cd5e0 120 IO_CON6_1,
Info 0:d2cb480cd5e0 121 IO_CON6_2,
Info 0:d2cb480cd5e0 122 IO_CON6_3,
Info 0:d2cb480cd5e0 123 IO_CON6_4,
Info 0:d2cb480cd5e0 124 IO_CON7_1,
Info 0:d2cb480cd5e0 125 IO_CON7_2,
Info 0:d2cb480cd5e0 126 IO_CON7_3,
Info 0:d2cb480cd5e0 127 IO_CON7_4,
Info 0:d2cb480cd5e0 128 IO_CON8_1,
Info 0:d2cb480cd5e0 129 IO_CON8_2,
Info 0:d2cb480cd5e0 130 IO_CON8_3,
Info 0:d2cb480cd5e0 131 IO_CON8_4,
Info 0:d2cb480cd5e0 132 IO_CON9_1,
Info 0:d2cb480cd5e0 133 IO_CON9_2,
Info 0:d2cb480cd5e0 134 IO_CON9_3,
Info 0:d2cb480cd5e0 135 IO_CON9_4,
Info 0:d2cb480cd5e0 136 IO_CON10_1,
Info 0:d2cb480cd5e0 137 IO_CON10_2,
Info 0:d2cb480cd5e0 138 IO_CON10_3,
Info 0:d2cb480cd5e0 139 IO_CON10_4,
Info 0:d2cb480cd5e0 140 IO_CON11_1,
Info 0:d2cb480cd5e0 141 IO_CON11_2,
Info 0:d2cb480cd5e0 142 IO_CON11_3,
Info 0:d2cb480cd5e0 143 IO_CON11_4,
Info 0:d2cb480cd5e0 144 IO_CON12_1,
Info 0:d2cb480cd5e0 145 IO_CON12_2,
Info 0:d2cb480cd5e0 146 IO_CON12_3,
Info 0:d2cb480cd5e0 147 IO_CON12_4
Info 0:d2cb480cd5e0 148 } en_fpga_io;
Info 0:d2cb480cd5e0 149
Info 0:d2cb480cd5e0 150 typedef enum {
Info 0:d2cb480cd5e0 151 IO_REG_EN = 0x80,
Info 0:d2cb480cd5e0 152 IO_REG_OUT_DIR = 0x40,
Info 0:d2cb480cd5e0 153 IO_REG_IN_DIR = 0x00,
Info 0:d2cb480cd5e0 154 IO_REG_DISABLE = 0x3f
Info 0:d2cb480cd5e0 155 } en_fpga_io_reg;
Info 0:d2cb480cd5e0 156
Info 0:d2cb480cd5e0 157