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mbed/TARGET_LPC1768/core_cmSimd.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file core_cmSimd.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M SIMD Header File
IKobayashi 0:c88c3b616c00 4 * @version V4.10
IKobayashi 0:c88c3b616c00 5 * @date 18. March 2015
IKobayashi 0:c88c3b616c00 6 *
IKobayashi 0:c88c3b616c00 7 * @note
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 ******************************************************************************/
IKobayashi 0:c88c3b616c00 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
IKobayashi 0:c88c3b616c00 11
IKobayashi 0:c88c3b616c00 12 All rights reserved.
IKobayashi 0:c88c3b616c00 13 Redistribution and use in source and binary forms, with or without
IKobayashi 0:c88c3b616c00 14 modification, are permitted provided that the following conditions are met:
IKobayashi 0:c88c3b616c00 15 - Redistributions of source code must retain the above copyright
IKobayashi 0:c88c3b616c00 16 notice, this list of conditions and the following disclaimer.
IKobayashi 0:c88c3b616c00 17 - Redistributions in binary form must reproduce the above copyright
IKobayashi 0:c88c3b616c00 18 notice, this list of conditions and the following disclaimer in the
IKobayashi 0:c88c3b616c00 19 documentation and/or other materials provided with the distribution.
IKobayashi 0:c88c3b616c00 20 - Neither the name of ARM nor the names of its contributors may be used
IKobayashi 0:c88c3b616c00 21 to endorse or promote products derived from this software without
IKobayashi 0:c88c3b616c00 22 specific prior written permission.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi 0:c88c3b616c00 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi 0:c88c3b616c00 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi 0:c88c3b616c00 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi 0:c88c3b616c00 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi 0:c88c3b616c00 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi 0:c88c3b616c00 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi 0:c88c3b616c00 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi 0:c88c3b616c00 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi 0:c88c3b616c00 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi 0:c88c3b616c00 34 POSSIBILITY OF SUCH DAMAGE.
IKobayashi 0:c88c3b616c00 35 ---------------------------------------------------------------------------*/
IKobayashi 0:c88c3b616c00 36
IKobayashi 0:c88c3b616c00 37
IKobayashi 0:c88c3b616c00 38 #if defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 39 #pragma system_include /* treat file as system include file for MISRA check */
IKobayashi 0:c88c3b616c00 40 #endif
IKobayashi 0:c88c3b616c00 41
IKobayashi 0:c88c3b616c00 42 #ifndef __CORE_CMSIMD_H
IKobayashi 0:c88c3b616c00 43 #define __CORE_CMSIMD_H
IKobayashi 0:c88c3b616c00 44
IKobayashi 0:c88c3b616c00 45 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 46 extern "C" {
IKobayashi 0:c88c3b616c00 47 #endif
IKobayashi 0:c88c3b616c00 48
IKobayashi 0:c88c3b616c00 49
IKobayashi 0:c88c3b616c00 50 /*******************************************************************************
IKobayashi 0:c88c3b616c00 51 * Hardware Abstraction Layer
IKobayashi 0:c88c3b616c00 52 ******************************************************************************/
IKobayashi 0:c88c3b616c00 53
IKobayashi 0:c88c3b616c00 54
IKobayashi 0:c88c3b616c00 55 /* ################### Compiler specific Intrinsics ########################### */
IKobayashi 0:c88c3b616c00 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
IKobayashi 0:c88c3b616c00 57 Access to dedicated SIMD instructions
IKobayashi 0:c88c3b616c00 58 @{
IKobayashi 0:c88c3b616c00 59 */
IKobayashi 0:c88c3b616c00 60
IKobayashi 0:c88c3b616c00 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
IKobayashi 0:c88c3b616c00 62 /* ARM armcc specific functions */
IKobayashi 0:c88c3b616c00 63 #define __SADD8 __sadd8
IKobayashi 0:c88c3b616c00 64 #define __QADD8 __qadd8
IKobayashi 0:c88c3b616c00 65 #define __SHADD8 __shadd8
IKobayashi 0:c88c3b616c00 66 #define __UADD8 __uadd8
IKobayashi 0:c88c3b616c00 67 #define __UQADD8 __uqadd8
IKobayashi 0:c88c3b616c00 68 #define __UHADD8 __uhadd8
IKobayashi 0:c88c3b616c00 69 #define __SSUB8 __ssub8
IKobayashi 0:c88c3b616c00 70 #define __QSUB8 __qsub8
IKobayashi 0:c88c3b616c00 71 #define __SHSUB8 __shsub8
IKobayashi 0:c88c3b616c00 72 #define __USUB8 __usub8
IKobayashi 0:c88c3b616c00 73 #define __UQSUB8 __uqsub8
IKobayashi 0:c88c3b616c00 74 #define __UHSUB8 __uhsub8
IKobayashi 0:c88c3b616c00 75 #define __SADD16 __sadd16
IKobayashi 0:c88c3b616c00 76 #define __QADD16 __qadd16
IKobayashi 0:c88c3b616c00 77 #define __SHADD16 __shadd16
IKobayashi 0:c88c3b616c00 78 #define __UADD16 __uadd16
IKobayashi 0:c88c3b616c00 79 #define __UQADD16 __uqadd16
IKobayashi 0:c88c3b616c00 80 #define __UHADD16 __uhadd16
IKobayashi 0:c88c3b616c00 81 #define __SSUB16 __ssub16
IKobayashi 0:c88c3b616c00 82 #define __QSUB16 __qsub16
IKobayashi 0:c88c3b616c00 83 #define __SHSUB16 __shsub16
IKobayashi 0:c88c3b616c00 84 #define __USUB16 __usub16
IKobayashi 0:c88c3b616c00 85 #define __UQSUB16 __uqsub16
IKobayashi 0:c88c3b616c00 86 #define __UHSUB16 __uhsub16
IKobayashi 0:c88c3b616c00 87 #define __SASX __sasx
IKobayashi 0:c88c3b616c00 88 #define __QASX __qasx
IKobayashi 0:c88c3b616c00 89 #define __SHASX __shasx
IKobayashi 0:c88c3b616c00 90 #define __UASX __uasx
IKobayashi 0:c88c3b616c00 91 #define __UQASX __uqasx
IKobayashi 0:c88c3b616c00 92 #define __UHASX __uhasx
IKobayashi 0:c88c3b616c00 93 #define __SSAX __ssax
IKobayashi 0:c88c3b616c00 94 #define __QSAX __qsax
IKobayashi 0:c88c3b616c00 95 #define __SHSAX __shsax
IKobayashi 0:c88c3b616c00 96 #define __USAX __usax
IKobayashi 0:c88c3b616c00 97 #define __UQSAX __uqsax
IKobayashi 0:c88c3b616c00 98 #define __UHSAX __uhsax
IKobayashi 0:c88c3b616c00 99 #define __USAD8 __usad8
IKobayashi 0:c88c3b616c00 100 #define __USADA8 __usada8
IKobayashi 0:c88c3b616c00 101 #define __SSAT16 __ssat16
IKobayashi 0:c88c3b616c00 102 #define __USAT16 __usat16
IKobayashi 0:c88c3b616c00 103 #define __UXTB16 __uxtb16
IKobayashi 0:c88c3b616c00 104 #define __UXTAB16 __uxtab16
IKobayashi 0:c88c3b616c00 105 #define __SXTB16 __sxtb16
IKobayashi 0:c88c3b616c00 106 #define __SXTAB16 __sxtab16
IKobayashi 0:c88c3b616c00 107 #define __SMUAD __smuad
IKobayashi 0:c88c3b616c00 108 #define __SMUADX __smuadx
IKobayashi 0:c88c3b616c00 109 #define __SMLAD __smlad
IKobayashi 0:c88c3b616c00 110 #define __SMLADX __smladx
IKobayashi 0:c88c3b616c00 111 #define __SMLALD __smlald
IKobayashi 0:c88c3b616c00 112 #define __SMLALDX __smlaldx
IKobayashi 0:c88c3b616c00 113 #define __SMUSD __smusd
IKobayashi 0:c88c3b616c00 114 #define __SMUSDX __smusdx
IKobayashi 0:c88c3b616c00 115 #define __SMLSD __smlsd
IKobayashi 0:c88c3b616c00 116 #define __SMLSDX __smlsdx
IKobayashi 0:c88c3b616c00 117 #define __SMLSLD __smlsld
IKobayashi 0:c88c3b616c00 118 #define __SMLSLDX __smlsldx
IKobayashi 0:c88c3b616c00 119 #define __SEL __sel
IKobayashi 0:c88c3b616c00 120 #define __QADD __qadd
IKobayashi 0:c88c3b616c00 121 #define __QSUB __qsub
IKobayashi 0:c88c3b616c00 122
IKobayashi 0:c88c3b616c00 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
IKobayashi 0:c88c3b616c00 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
IKobayashi 0:c88c3b616c00 125
IKobayashi 0:c88c3b616c00 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
IKobayashi 0:c88c3b616c00 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
IKobayashi 0:c88c3b616c00 128
IKobayashi 0:c88c3b616c00 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
IKobayashi 0:c88c3b616c00 130 ((int64_t)(ARG3) << 32) ) >> 32))
IKobayashi 0:c88c3b616c00 131
IKobayashi 0:c88c3b616c00 132
IKobayashi 0:c88c3b616c00 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
IKobayashi 0:c88c3b616c00 134 /* GNU gcc specific functions */
IKobayashi 0:c88c3b616c00 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 136 {
IKobayashi 0:c88c3b616c00 137 uint32_t result;
IKobayashi 0:c88c3b616c00 138
IKobayashi 0:c88c3b616c00 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 140 return(result);
IKobayashi 0:c88c3b616c00 141 }
IKobayashi 0:c88c3b616c00 142
IKobayashi 0:c88c3b616c00 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 144 {
IKobayashi 0:c88c3b616c00 145 uint32_t result;
IKobayashi 0:c88c3b616c00 146
IKobayashi 0:c88c3b616c00 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 148 return(result);
IKobayashi 0:c88c3b616c00 149 }
IKobayashi 0:c88c3b616c00 150
IKobayashi 0:c88c3b616c00 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 152 {
IKobayashi 0:c88c3b616c00 153 uint32_t result;
IKobayashi 0:c88c3b616c00 154
IKobayashi 0:c88c3b616c00 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 156 return(result);
IKobayashi 0:c88c3b616c00 157 }
IKobayashi 0:c88c3b616c00 158
IKobayashi 0:c88c3b616c00 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 160 {
IKobayashi 0:c88c3b616c00 161 uint32_t result;
IKobayashi 0:c88c3b616c00 162
IKobayashi 0:c88c3b616c00 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 164 return(result);
IKobayashi 0:c88c3b616c00 165 }
IKobayashi 0:c88c3b616c00 166
IKobayashi 0:c88c3b616c00 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 168 {
IKobayashi 0:c88c3b616c00 169 uint32_t result;
IKobayashi 0:c88c3b616c00 170
IKobayashi 0:c88c3b616c00 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 172 return(result);
IKobayashi 0:c88c3b616c00 173 }
IKobayashi 0:c88c3b616c00 174
IKobayashi 0:c88c3b616c00 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 176 {
IKobayashi 0:c88c3b616c00 177 uint32_t result;
IKobayashi 0:c88c3b616c00 178
IKobayashi 0:c88c3b616c00 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 180 return(result);
IKobayashi 0:c88c3b616c00 181 }
IKobayashi 0:c88c3b616c00 182
IKobayashi 0:c88c3b616c00 183
IKobayashi 0:c88c3b616c00 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 185 {
IKobayashi 0:c88c3b616c00 186 uint32_t result;
IKobayashi 0:c88c3b616c00 187
IKobayashi 0:c88c3b616c00 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 189 return(result);
IKobayashi 0:c88c3b616c00 190 }
IKobayashi 0:c88c3b616c00 191
IKobayashi 0:c88c3b616c00 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 193 {
IKobayashi 0:c88c3b616c00 194 uint32_t result;
IKobayashi 0:c88c3b616c00 195
IKobayashi 0:c88c3b616c00 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 197 return(result);
IKobayashi 0:c88c3b616c00 198 }
IKobayashi 0:c88c3b616c00 199
IKobayashi 0:c88c3b616c00 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 201 {
IKobayashi 0:c88c3b616c00 202 uint32_t result;
IKobayashi 0:c88c3b616c00 203
IKobayashi 0:c88c3b616c00 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 205 return(result);
IKobayashi 0:c88c3b616c00 206 }
IKobayashi 0:c88c3b616c00 207
IKobayashi 0:c88c3b616c00 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 209 {
IKobayashi 0:c88c3b616c00 210 uint32_t result;
IKobayashi 0:c88c3b616c00 211
IKobayashi 0:c88c3b616c00 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 213 return(result);
IKobayashi 0:c88c3b616c00 214 }
IKobayashi 0:c88c3b616c00 215
IKobayashi 0:c88c3b616c00 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 217 {
IKobayashi 0:c88c3b616c00 218 uint32_t result;
IKobayashi 0:c88c3b616c00 219
IKobayashi 0:c88c3b616c00 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 221 return(result);
IKobayashi 0:c88c3b616c00 222 }
IKobayashi 0:c88c3b616c00 223
IKobayashi 0:c88c3b616c00 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 225 {
IKobayashi 0:c88c3b616c00 226 uint32_t result;
IKobayashi 0:c88c3b616c00 227
IKobayashi 0:c88c3b616c00 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 229 return(result);
IKobayashi 0:c88c3b616c00 230 }
IKobayashi 0:c88c3b616c00 231
IKobayashi 0:c88c3b616c00 232
IKobayashi 0:c88c3b616c00 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 234 {
IKobayashi 0:c88c3b616c00 235 uint32_t result;
IKobayashi 0:c88c3b616c00 236
IKobayashi 0:c88c3b616c00 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 238 return(result);
IKobayashi 0:c88c3b616c00 239 }
IKobayashi 0:c88c3b616c00 240
IKobayashi 0:c88c3b616c00 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 242 {
IKobayashi 0:c88c3b616c00 243 uint32_t result;
IKobayashi 0:c88c3b616c00 244
IKobayashi 0:c88c3b616c00 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 246 return(result);
IKobayashi 0:c88c3b616c00 247 }
IKobayashi 0:c88c3b616c00 248
IKobayashi 0:c88c3b616c00 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 250 {
IKobayashi 0:c88c3b616c00 251 uint32_t result;
IKobayashi 0:c88c3b616c00 252
IKobayashi 0:c88c3b616c00 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 254 return(result);
IKobayashi 0:c88c3b616c00 255 }
IKobayashi 0:c88c3b616c00 256
IKobayashi 0:c88c3b616c00 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 258 {
IKobayashi 0:c88c3b616c00 259 uint32_t result;
IKobayashi 0:c88c3b616c00 260
IKobayashi 0:c88c3b616c00 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 262 return(result);
IKobayashi 0:c88c3b616c00 263 }
IKobayashi 0:c88c3b616c00 264
IKobayashi 0:c88c3b616c00 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 266 {
IKobayashi 0:c88c3b616c00 267 uint32_t result;
IKobayashi 0:c88c3b616c00 268
IKobayashi 0:c88c3b616c00 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 270 return(result);
IKobayashi 0:c88c3b616c00 271 }
IKobayashi 0:c88c3b616c00 272
IKobayashi 0:c88c3b616c00 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 274 {
IKobayashi 0:c88c3b616c00 275 uint32_t result;
IKobayashi 0:c88c3b616c00 276
IKobayashi 0:c88c3b616c00 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 278 return(result);
IKobayashi 0:c88c3b616c00 279 }
IKobayashi 0:c88c3b616c00 280
IKobayashi 0:c88c3b616c00 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 282 {
IKobayashi 0:c88c3b616c00 283 uint32_t result;
IKobayashi 0:c88c3b616c00 284
IKobayashi 0:c88c3b616c00 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 286 return(result);
IKobayashi 0:c88c3b616c00 287 }
IKobayashi 0:c88c3b616c00 288
IKobayashi 0:c88c3b616c00 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 290 {
IKobayashi 0:c88c3b616c00 291 uint32_t result;
IKobayashi 0:c88c3b616c00 292
IKobayashi 0:c88c3b616c00 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 294 return(result);
IKobayashi 0:c88c3b616c00 295 }
IKobayashi 0:c88c3b616c00 296
IKobayashi 0:c88c3b616c00 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 298 {
IKobayashi 0:c88c3b616c00 299 uint32_t result;
IKobayashi 0:c88c3b616c00 300
IKobayashi 0:c88c3b616c00 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 302 return(result);
IKobayashi 0:c88c3b616c00 303 }
IKobayashi 0:c88c3b616c00 304
IKobayashi 0:c88c3b616c00 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 306 {
IKobayashi 0:c88c3b616c00 307 uint32_t result;
IKobayashi 0:c88c3b616c00 308
IKobayashi 0:c88c3b616c00 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 310 return(result);
IKobayashi 0:c88c3b616c00 311 }
IKobayashi 0:c88c3b616c00 312
IKobayashi 0:c88c3b616c00 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 314 {
IKobayashi 0:c88c3b616c00 315 uint32_t result;
IKobayashi 0:c88c3b616c00 316
IKobayashi 0:c88c3b616c00 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 318 return(result);
IKobayashi 0:c88c3b616c00 319 }
IKobayashi 0:c88c3b616c00 320
IKobayashi 0:c88c3b616c00 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 322 {
IKobayashi 0:c88c3b616c00 323 uint32_t result;
IKobayashi 0:c88c3b616c00 324
IKobayashi 0:c88c3b616c00 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 326 return(result);
IKobayashi 0:c88c3b616c00 327 }
IKobayashi 0:c88c3b616c00 328
IKobayashi 0:c88c3b616c00 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 330 {
IKobayashi 0:c88c3b616c00 331 uint32_t result;
IKobayashi 0:c88c3b616c00 332
IKobayashi 0:c88c3b616c00 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 334 return(result);
IKobayashi 0:c88c3b616c00 335 }
IKobayashi 0:c88c3b616c00 336
IKobayashi 0:c88c3b616c00 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 338 {
IKobayashi 0:c88c3b616c00 339 uint32_t result;
IKobayashi 0:c88c3b616c00 340
IKobayashi 0:c88c3b616c00 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 342 return(result);
IKobayashi 0:c88c3b616c00 343 }
IKobayashi 0:c88c3b616c00 344
IKobayashi 0:c88c3b616c00 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 346 {
IKobayashi 0:c88c3b616c00 347 uint32_t result;
IKobayashi 0:c88c3b616c00 348
IKobayashi 0:c88c3b616c00 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 350 return(result);
IKobayashi 0:c88c3b616c00 351 }
IKobayashi 0:c88c3b616c00 352
IKobayashi 0:c88c3b616c00 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 354 {
IKobayashi 0:c88c3b616c00 355 uint32_t result;
IKobayashi 0:c88c3b616c00 356
IKobayashi 0:c88c3b616c00 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 358 return(result);
IKobayashi 0:c88c3b616c00 359 }
IKobayashi 0:c88c3b616c00 360
IKobayashi 0:c88c3b616c00 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 362 {
IKobayashi 0:c88c3b616c00 363 uint32_t result;
IKobayashi 0:c88c3b616c00 364
IKobayashi 0:c88c3b616c00 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 366 return(result);
IKobayashi 0:c88c3b616c00 367 }
IKobayashi 0:c88c3b616c00 368
IKobayashi 0:c88c3b616c00 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 370 {
IKobayashi 0:c88c3b616c00 371 uint32_t result;
IKobayashi 0:c88c3b616c00 372
IKobayashi 0:c88c3b616c00 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 374 return(result);
IKobayashi 0:c88c3b616c00 375 }
IKobayashi 0:c88c3b616c00 376
IKobayashi 0:c88c3b616c00 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 378 {
IKobayashi 0:c88c3b616c00 379 uint32_t result;
IKobayashi 0:c88c3b616c00 380
IKobayashi 0:c88c3b616c00 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 382 return(result);
IKobayashi 0:c88c3b616c00 383 }
IKobayashi 0:c88c3b616c00 384
IKobayashi 0:c88c3b616c00 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 386 {
IKobayashi 0:c88c3b616c00 387 uint32_t result;
IKobayashi 0:c88c3b616c00 388
IKobayashi 0:c88c3b616c00 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 390 return(result);
IKobayashi 0:c88c3b616c00 391 }
IKobayashi 0:c88c3b616c00 392
IKobayashi 0:c88c3b616c00 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 394 {
IKobayashi 0:c88c3b616c00 395 uint32_t result;
IKobayashi 0:c88c3b616c00 396
IKobayashi 0:c88c3b616c00 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 398 return(result);
IKobayashi 0:c88c3b616c00 399 }
IKobayashi 0:c88c3b616c00 400
IKobayashi 0:c88c3b616c00 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 402 {
IKobayashi 0:c88c3b616c00 403 uint32_t result;
IKobayashi 0:c88c3b616c00 404
IKobayashi 0:c88c3b616c00 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 406 return(result);
IKobayashi 0:c88c3b616c00 407 }
IKobayashi 0:c88c3b616c00 408
IKobayashi 0:c88c3b616c00 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 410 {
IKobayashi 0:c88c3b616c00 411 uint32_t result;
IKobayashi 0:c88c3b616c00 412
IKobayashi 0:c88c3b616c00 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 414 return(result);
IKobayashi 0:c88c3b616c00 415 }
IKobayashi 0:c88c3b616c00 416
IKobayashi 0:c88c3b616c00 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 418 {
IKobayashi 0:c88c3b616c00 419 uint32_t result;
IKobayashi 0:c88c3b616c00 420
IKobayashi 0:c88c3b616c00 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 422 return(result);
IKobayashi 0:c88c3b616c00 423 }
IKobayashi 0:c88c3b616c00 424
IKobayashi 0:c88c3b616c00 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 426 {
IKobayashi 0:c88c3b616c00 427 uint32_t result;
IKobayashi 0:c88c3b616c00 428
IKobayashi 0:c88c3b616c00 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 430 return(result);
IKobayashi 0:c88c3b616c00 431 }
IKobayashi 0:c88c3b616c00 432
IKobayashi 0:c88c3b616c00 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
IKobayashi 0:c88c3b616c00 434 {
IKobayashi 0:c88c3b616c00 435 uint32_t result;
IKobayashi 0:c88c3b616c00 436
IKobayashi 0:c88c3b616c00 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 438 return(result);
IKobayashi 0:c88c3b616c00 439 }
IKobayashi 0:c88c3b616c00 440
IKobayashi 0:c88c3b616c00 441 #define __SSAT16(ARG1,ARG2) \
IKobayashi 0:c88c3b616c00 442 ({ \
IKobayashi 0:c88c3b616c00 443 uint32_t __RES, __ARG1 = (ARG1); \
IKobayashi 0:c88c3b616c00 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
IKobayashi 0:c88c3b616c00 445 __RES; \
IKobayashi 0:c88c3b616c00 446 })
IKobayashi 0:c88c3b616c00 447
IKobayashi 0:c88c3b616c00 448 #define __USAT16(ARG1,ARG2) \
IKobayashi 0:c88c3b616c00 449 ({ \
IKobayashi 0:c88c3b616c00 450 uint32_t __RES, __ARG1 = (ARG1); \
IKobayashi 0:c88c3b616c00 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
IKobayashi 0:c88c3b616c00 452 __RES; \
IKobayashi 0:c88c3b616c00 453 })
IKobayashi 0:c88c3b616c00 454
IKobayashi 0:c88c3b616c00 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
IKobayashi 0:c88c3b616c00 456 {
IKobayashi 0:c88c3b616c00 457 uint32_t result;
IKobayashi 0:c88c3b616c00 458
IKobayashi 0:c88c3b616c00 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
IKobayashi 0:c88c3b616c00 460 return(result);
IKobayashi 0:c88c3b616c00 461 }
IKobayashi 0:c88c3b616c00 462
IKobayashi 0:c88c3b616c00 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 464 {
IKobayashi 0:c88c3b616c00 465 uint32_t result;
IKobayashi 0:c88c3b616c00 466
IKobayashi 0:c88c3b616c00 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 468 return(result);
IKobayashi 0:c88c3b616c00 469 }
IKobayashi 0:c88c3b616c00 470
IKobayashi 0:c88c3b616c00 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
IKobayashi 0:c88c3b616c00 472 {
IKobayashi 0:c88c3b616c00 473 uint32_t result;
IKobayashi 0:c88c3b616c00 474
IKobayashi 0:c88c3b616c00 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
IKobayashi 0:c88c3b616c00 476 return(result);
IKobayashi 0:c88c3b616c00 477 }
IKobayashi 0:c88c3b616c00 478
IKobayashi 0:c88c3b616c00 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 480 {
IKobayashi 0:c88c3b616c00 481 uint32_t result;
IKobayashi 0:c88c3b616c00 482
IKobayashi 0:c88c3b616c00 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 484 return(result);
IKobayashi 0:c88c3b616c00 485 }
IKobayashi 0:c88c3b616c00 486
IKobayashi 0:c88c3b616c00 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 488 {
IKobayashi 0:c88c3b616c00 489 uint32_t result;
IKobayashi 0:c88c3b616c00 490
IKobayashi 0:c88c3b616c00 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 492 return(result);
IKobayashi 0:c88c3b616c00 493 }
IKobayashi 0:c88c3b616c00 494
IKobayashi 0:c88c3b616c00 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 496 {
IKobayashi 0:c88c3b616c00 497 uint32_t result;
IKobayashi 0:c88c3b616c00 498
IKobayashi 0:c88c3b616c00 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 500 return(result);
IKobayashi 0:c88c3b616c00 501 }
IKobayashi 0:c88c3b616c00 502
IKobayashi 0:c88c3b616c00 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
IKobayashi 0:c88c3b616c00 504 {
IKobayashi 0:c88c3b616c00 505 uint32_t result;
IKobayashi 0:c88c3b616c00 506
IKobayashi 0:c88c3b616c00 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 508 return(result);
IKobayashi 0:c88c3b616c00 509 }
IKobayashi 0:c88c3b616c00 510
IKobayashi 0:c88c3b616c00 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
IKobayashi 0:c88c3b616c00 512 {
IKobayashi 0:c88c3b616c00 513 uint32_t result;
IKobayashi 0:c88c3b616c00 514
IKobayashi 0:c88c3b616c00 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 516 return(result);
IKobayashi 0:c88c3b616c00 517 }
IKobayashi 0:c88c3b616c00 518
IKobayashi 0:c88c3b616c00 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
IKobayashi 0:c88c3b616c00 520 {
IKobayashi 0:c88c3b616c00 521 union llreg_u{
IKobayashi 0:c88c3b616c00 522 uint32_t w32[2];
IKobayashi 0:c88c3b616c00 523 uint64_t w64;
IKobayashi 0:c88c3b616c00 524 } llr;
IKobayashi 0:c88c3b616c00 525 llr.w64 = acc;
IKobayashi 0:c88c3b616c00 526
IKobayashi 0:c88c3b616c00 527 #ifndef __ARMEB__ // Little endian
IKobayashi 0:c88c3b616c00 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
IKobayashi 0:c88c3b616c00 529 #else // Big endian
IKobayashi 0:c88c3b616c00 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
IKobayashi 0:c88c3b616c00 531 #endif
IKobayashi 0:c88c3b616c00 532
IKobayashi 0:c88c3b616c00 533 return(llr.w64);
IKobayashi 0:c88c3b616c00 534 }
IKobayashi 0:c88c3b616c00 535
IKobayashi 0:c88c3b616c00 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
IKobayashi 0:c88c3b616c00 537 {
IKobayashi 0:c88c3b616c00 538 union llreg_u{
IKobayashi 0:c88c3b616c00 539 uint32_t w32[2];
IKobayashi 0:c88c3b616c00 540 uint64_t w64;
IKobayashi 0:c88c3b616c00 541 } llr;
IKobayashi 0:c88c3b616c00 542 llr.w64 = acc;
IKobayashi 0:c88c3b616c00 543
IKobayashi 0:c88c3b616c00 544 #ifndef __ARMEB__ // Little endian
IKobayashi 0:c88c3b616c00 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
IKobayashi 0:c88c3b616c00 546 #else // Big endian
IKobayashi 0:c88c3b616c00 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
IKobayashi 0:c88c3b616c00 548 #endif
IKobayashi 0:c88c3b616c00 549
IKobayashi 0:c88c3b616c00 550 return(llr.w64);
IKobayashi 0:c88c3b616c00 551 }
IKobayashi 0:c88c3b616c00 552
IKobayashi 0:c88c3b616c00 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 554 {
IKobayashi 0:c88c3b616c00 555 uint32_t result;
IKobayashi 0:c88c3b616c00 556
IKobayashi 0:c88c3b616c00 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 558 return(result);
IKobayashi 0:c88c3b616c00 559 }
IKobayashi 0:c88c3b616c00 560
IKobayashi 0:c88c3b616c00 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 562 {
IKobayashi 0:c88c3b616c00 563 uint32_t result;
IKobayashi 0:c88c3b616c00 564
IKobayashi 0:c88c3b616c00 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 566 return(result);
IKobayashi 0:c88c3b616c00 567 }
IKobayashi 0:c88c3b616c00 568
IKobayashi 0:c88c3b616c00 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
IKobayashi 0:c88c3b616c00 570 {
IKobayashi 0:c88c3b616c00 571 uint32_t result;
IKobayashi 0:c88c3b616c00 572
IKobayashi 0:c88c3b616c00 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 574 return(result);
IKobayashi 0:c88c3b616c00 575 }
IKobayashi 0:c88c3b616c00 576
IKobayashi 0:c88c3b616c00 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
IKobayashi 0:c88c3b616c00 578 {
IKobayashi 0:c88c3b616c00 579 uint32_t result;
IKobayashi 0:c88c3b616c00 580
IKobayashi 0:c88c3b616c00 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 582 return(result);
IKobayashi 0:c88c3b616c00 583 }
IKobayashi 0:c88c3b616c00 584
IKobayashi 0:c88c3b616c00 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
IKobayashi 0:c88c3b616c00 586 {
IKobayashi 0:c88c3b616c00 587 union llreg_u{
IKobayashi 0:c88c3b616c00 588 uint32_t w32[2];
IKobayashi 0:c88c3b616c00 589 uint64_t w64;
IKobayashi 0:c88c3b616c00 590 } llr;
IKobayashi 0:c88c3b616c00 591 llr.w64 = acc;
IKobayashi 0:c88c3b616c00 592
IKobayashi 0:c88c3b616c00 593 #ifndef __ARMEB__ // Little endian
IKobayashi 0:c88c3b616c00 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
IKobayashi 0:c88c3b616c00 595 #else // Big endian
IKobayashi 0:c88c3b616c00 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
IKobayashi 0:c88c3b616c00 597 #endif
IKobayashi 0:c88c3b616c00 598
IKobayashi 0:c88c3b616c00 599 return(llr.w64);
IKobayashi 0:c88c3b616c00 600 }
IKobayashi 0:c88c3b616c00 601
IKobayashi 0:c88c3b616c00 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
IKobayashi 0:c88c3b616c00 603 {
IKobayashi 0:c88c3b616c00 604 union llreg_u{
IKobayashi 0:c88c3b616c00 605 uint32_t w32[2];
IKobayashi 0:c88c3b616c00 606 uint64_t w64;
IKobayashi 0:c88c3b616c00 607 } llr;
IKobayashi 0:c88c3b616c00 608 llr.w64 = acc;
IKobayashi 0:c88c3b616c00 609
IKobayashi 0:c88c3b616c00 610 #ifndef __ARMEB__ // Little endian
IKobayashi 0:c88c3b616c00 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
IKobayashi 0:c88c3b616c00 612 #else // Big endian
IKobayashi 0:c88c3b616c00 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
IKobayashi 0:c88c3b616c00 614 #endif
IKobayashi 0:c88c3b616c00 615
IKobayashi 0:c88c3b616c00 616 return(llr.w64);
IKobayashi 0:c88c3b616c00 617 }
IKobayashi 0:c88c3b616c00 618
IKobayashi 0:c88c3b616c00 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 620 {
IKobayashi 0:c88c3b616c00 621 uint32_t result;
IKobayashi 0:c88c3b616c00 622
IKobayashi 0:c88c3b616c00 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 624 return(result);
IKobayashi 0:c88c3b616c00 625 }
IKobayashi 0:c88c3b616c00 626
IKobayashi 0:c88c3b616c00 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 628 {
IKobayashi 0:c88c3b616c00 629 uint32_t result;
IKobayashi 0:c88c3b616c00 630
IKobayashi 0:c88c3b616c00 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 632 return(result);
IKobayashi 0:c88c3b616c00 633 }
IKobayashi 0:c88c3b616c00 634
IKobayashi 0:c88c3b616c00 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 636 {
IKobayashi 0:c88c3b616c00 637 uint32_t result;
IKobayashi 0:c88c3b616c00 638
IKobayashi 0:c88c3b616c00 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
IKobayashi 0:c88c3b616c00 640 return(result);
IKobayashi 0:c88c3b616c00 641 }
IKobayashi 0:c88c3b616c00 642
IKobayashi 0:c88c3b616c00 643 #define __PKHBT(ARG1,ARG2,ARG3) \
IKobayashi 0:c88c3b616c00 644 ({ \
IKobayashi 0:c88c3b616c00 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
IKobayashi 0:c88c3b616c00 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
IKobayashi 0:c88c3b616c00 647 __RES; \
IKobayashi 0:c88c3b616c00 648 })
IKobayashi 0:c88c3b616c00 649
IKobayashi 0:c88c3b616c00 650 #define __PKHTB(ARG1,ARG2,ARG3) \
IKobayashi 0:c88c3b616c00 651 ({ \
IKobayashi 0:c88c3b616c00 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
IKobayashi 0:c88c3b616c00 653 if (ARG3 == 0) \
IKobayashi 0:c88c3b616c00 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
IKobayashi 0:c88c3b616c00 655 else \
IKobayashi 0:c88c3b616c00 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
IKobayashi 0:c88c3b616c00 657 __RES; \
IKobayashi 0:c88c3b616c00 658 })
IKobayashi 0:c88c3b616c00 659
IKobayashi 0:c88c3b616c00 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
IKobayashi 0:c88c3b616c00 661 {
IKobayashi 0:c88c3b616c00 662 int32_t result;
IKobayashi 0:c88c3b616c00 663
IKobayashi 0:c88c3b616c00 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
IKobayashi 0:c88c3b616c00 665 return(result);
IKobayashi 0:c88c3b616c00 666 }
IKobayashi 0:c88c3b616c00 667
IKobayashi 0:c88c3b616c00 668
IKobayashi 0:c88c3b616c00 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 670 /* IAR iccarm specific functions */
IKobayashi 0:c88c3b616c00 671 #include <cmsis_iar.h>
IKobayashi 0:c88c3b616c00 672
IKobayashi 0:c88c3b616c00 673
IKobayashi 0:c88c3b616c00 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
IKobayashi 0:c88c3b616c00 675 /* TI CCS specific functions */
IKobayashi 0:c88c3b616c00 676 #include <cmsis_ccs.h>
IKobayashi 0:c88c3b616c00 677
IKobayashi 0:c88c3b616c00 678
IKobayashi 0:c88c3b616c00 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
IKobayashi 0:c88c3b616c00 680 /* TASKING carm specific functions */
IKobayashi 0:c88c3b616c00 681 /* not yet supported */
IKobayashi 0:c88c3b616c00 682
IKobayashi 0:c88c3b616c00 683
IKobayashi 0:c88c3b616c00 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 685 /* Cosmic specific functions */
IKobayashi 0:c88c3b616c00 686 #include <cmsis_csm.h>
IKobayashi 0:c88c3b616c00 687
IKobayashi 0:c88c3b616c00 688 #endif
IKobayashi 0:c88c3b616c00 689
IKobayashi 0:c88c3b616c00 690 /*@} end of group CMSIS_SIMD_intrinsics */
IKobayashi 0:c88c3b616c00 691
IKobayashi 0:c88c3b616c00 692
IKobayashi 0:c88c3b616c00 693 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 694 }
IKobayashi 0:c88c3b616c00 695 #endif
IKobayashi 0:c88c3b616c00 696
IKobayashi 0:c88c3b616c00 697 #endif /* __CORE_CMSIMD_H */