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mbed/TARGET_LPC1768/core_cmInstr.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file core_cmInstr.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
IKobayashi 0:c88c3b616c00 4 * @version V4.10
IKobayashi 0:c88c3b616c00 5 * @date 18. March 2015
IKobayashi 0:c88c3b616c00 6 *
IKobayashi 0:c88c3b616c00 7 * @note
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 ******************************************************************************/
IKobayashi 0:c88c3b616c00 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
IKobayashi 0:c88c3b616c00 11
IKobayashi 0:c88c3b616c00 12 All rights reserved.
IKobayashi 0:c88c3b616c00 13 Redistribution and use in source and binary forms, with or without
IKobayashi 0:c88c3b616c00 14 modification, are permitted provided that the following conditions are met:
IKobayashi 0:c88c3b616c00 15 - Redistributions of source code must retain the above copyright
IKobayashi 0:c88c3b616c00 16 notice, this list of conditions and the following disclaimer.
IKobayashi 0:c88c3b616c00 17 - Redistributions in binary form must reproduce the above copyright
IKobayashi 0:c88c3b616c00 18 notice, this list of conditions and the following disclaimer in the
IKobayashi 0:c88c3b616c00 19 documentation and/or other materials provided with the distribution.
IKobayashi 0:c88c3b616c00 20 - Neither the name of ARM nor the names of its contributors may be used
IKobayashi 0:c88c3b616c00 21 to endorse or promote products derived from this software without
IKobayashi 0:c88c3b616c00 22 specific prior written permission.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi 0:c88c3b616c00 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi 0:c88c3b616c00 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi 0:c88c3b616c00 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi 0:c88c3b616c00 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi 0:c88c3b616c00 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi 0:c88c3b616c00 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi 0:c88c3b616c00 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi 0:c88c3b616c00 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi 0:c88c3b616c00 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi 0:c88c3b616c00 34 POSSIBILITY OF SUCH DAMAGE.
IKobayashi 0:c88c3b616c00 35 ---------------------------------------------------------------------------*/
IKobayashi 0:c88c3b616c00 36
IKobayashi 0:c88c3b616c00 37
IKobayashi 0:c88c3b616c00 38 #ifndef __CORE_CMINSTR_H
IKobayashi 0:c88c3b616c00 39 #define __CORE_CMINSTR_H
IKobayashi 0:c88c3b616c00 40
IKobayashi 0:c88c3b616c00 41
IKobayashi 0:c88c3b616c00 42 /* ########################## Core Instruction Access ######################### */
IKobayashi 0:c88c3b616c00 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
IKobayashi 0:c88c3b616c00 44 Access to dedicated instructions
IKobayashi 0:c88c3b616c00 45 @{
IKobayashi 0:c88c3b616c00 46 */
IKobayashi 0:c88c3b616c00 47
IKobayashi 0:c88c3b616c00 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
IKobayashi 0:c88c3b616c00 49 /* ARM armcc specific functions */
IKobayashi 0:c88c3b616c00 50
IKobayashi 0:c88c3b616c00 51 #if (__ARMCC_VERSION < 400677)
IKobayashi 0:c88c3b616c00 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
IKobayashi 0:c88c3b616c00 53 #endif
IKobayashi 0:c88c3b616c00 54
IKobayashi 0:c88c3b616c00 55
IKobayashi 0:c88c3b616c00 56 /** \brief No Operation
IKobayashi 0:c88c3b616c00 57
IKobayashi 0:c88c3b616c00 58 No Operation does nothing. This instruction can be used for code alignment purposes.
IKobayashi 0:c88c3b616c00 59 */
IKobayashi 0:c88c3b616c00 60 #define __NOP __nop
IKobayashi 0:c88c3b616c00 61
IKobayashi 0:c88c3b616c00 62
IKobayashi 0:c88c3b616c00 63 /** \brief Wait For Interrupt
IKobayashi 0:c88c3b616c00 64
IKobayashi 0:c88c3b616c00 65 Wait For Interrupt is a hint instruction that suspends execution
IKobayashi 0:c88c3b616c00 66 until one of a number of events occurs.
IKobayashi 0:c88c3b616c00 67 */
IKobayashi 0:c88c3b616c00 68 #define __WFI __wfi
IKobayashi 0:c88c3b616c00 69
IKobayashi 0:c88c3b616c00 70
IKobayashi 0:c88c3b616c00 71 /** \brief Wait For Event
IKobayashi 0:c88c3b616c00 72
IKobayashi 0:c88c3b616c00 73 Wait For Event is a hint instruction that permits the processor to enter
IKobayashi 0:c88c3b616c00 74 a low-power state until one of a number of events occurs.
IKobayashi 0:c88c3b616c00 75 */
IKobayashi 0:c88c3b616c00 76 #define __WFE __wfe
IKobayashi 0:c88c3b616c00 77
IKobayashi 0:c88c3b616c00 78
IKobayashi 0:c88c3b616c00 79 /** \brief Send Event
IKobayashi 0:c88c3b616c00 80
IKobayashi 0:c88c3b616c00 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
IKobayashi 0:c88c3b616c00 82 */
IKobayashi 0:c88c3b616c00 83 #define __SEV __sev
IKobayashi 0:c88c3b616c00 84
IKobayashi 0:c88c3b616c00 85
IKobayashi 0:c88c3b616c00 86 /** \brief Instruction Synchronization Barrier
IKobayashi 0:c88c3b616c00 87
IKobayashi 0:c88c3b616c00 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
IKobayashi 0:c88c3b616c00 89 so that all instructions following the ISB are fetched from cache or
IKobayashi 0:c88c3b616c00 90 memory, after the instruction has been completed.
IKobayashi 0:c88c3b616c00 91 */
IKobayashi 0:c88c3b616c00 92 #define __ISB() do {\
IKobayashi 0:c88c3b616c00 93 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 94 __isb(0xF);\
IKobayashi 0:c88c3b616c00 95 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 96 } while (0)
IKobayashi 0:c88c3b616c00 97
IKobayashi 0:c88c3b616c00 98 /** \brief Data Synchronization Barrier
IKobayashi 0:c88c3b616c00 99
IKobayashi 0:c88c3b616c00 100 This function acts as a special kind of Data Memory Barrier.
IKobayashi 0:c88c3b616c00 101 It completes when all explicit memory accesses before this instruction complete.
IKobayashi 0:c88c3b616c00 102 */
IKobayashi 0:c88c3b616c00 103 #define __DSB() do {\
IKobayashi 0:c88c3b616c00 104 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 105 __dsb(0xF);\
IKobayashi 0:c88c3b616c00 106 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 107 } while (0)
IKobayashi 0:c88c3b616c00 108
IKobayashi 0:c88c3b616c00 109 /** \brief Data Memory Barrier
IKobayashi 0:c88c3b616c00 110
IKobayashi 0:c88c3b616c00 111 This function ensures the apparent order of the explicit memory operations before
IKobayashi 0:c88c3b616c00 112 and after the instruction, without ensuring their completion.
IKobayashi 0:c88c3b616c00 113 */
IKobayashi 0:c88c3b616c00 114 #define __DMB() do {\
IKobayashi 0:c88c3b616c00 115 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 116 __dmb(0xF);\
IKobayashi 0:c88c3b616c00 117 __schedule_barrier();\
IKobayashi 0:c88c3b616c00 118 } while (0)
IKobayashi 0:c88c3b616c00 119
IKobayashi 0:c88c3b616c00 120 /** \brief Reverse byte order (32 bit)
IKobayashi 0:c88c3b616c00 121
IKobayashi 0:c88c3b616c00 122 This function reverses the byte order in integer value.
IKobayashi 0:c88c3b616c00 123
IKobayashi 0:c88c3b616c00 124 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 125 \return Reversed value
IKobayashi 0:c88c3b616c00 126 */
IKobayashi 0:c88c3b616c00 127 #define __REV __rev
IKobayashi 0:c88c3b616c00 128
IKobayashi 0:c88c3b616c00 129
IKobayashi 0:c88c3b616c00 130 /** \brief Reverse byte order (16 bit)
IKobayashi 0:c88c3b616c00 131
IKobayashi 0:c88c3b616c00 132 This function reverses the byte order in two unsigned short values.
IKobayashi 0:c88c3b616c00 133
IKobayashi 0:c88c3b616c00 134 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 135 \return Reversed value
IKobayashi 0:c88c3b616c00 136 */
IKobayashi 0:c88c3b616c00 137 #ifndef __NO_EMBEDDED_ASM
IKobayashi 0:c88c3b616c00 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
IKobayashi 0:c88c3b616c00 139 {
IKobayashi 0:c88c3b616c00 140 rev16 r0, r0
IKobayashi 0:c88c3b616c00 141 bx lr
IKobayashi 0:c88c3b616c00 142 }
IKobayashi 0:c88c3b616c00 143 #endif
IKobayashi 0:c88c3b616c00 144
IKobayashi 0:c88c3b616c00 145 /** \brief Reverse byte order in signed short value
IKobayashi 0:c88c3b616c00 146
IKobayashi 0:c88c3b616c00 147 This function reverses the byte order in a signed short value with sign extension to integer.
IKobayashi 0:c88c3b616c00 148
IKobayashi 0:c88c3b616c00 149 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 150 \return Reversed value
IKobayashi 0:c88c3b616c00 151 */
IKobayashi 0:c88c3b616c00 152 #ifndef __NO_EMBEDDED_ASM
IKobayashi 0:c88c3b616c00 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
IKobayashi 0:c88c3b616c00 154 {
IKobayashi 0:c88c3b616c00 155 revsh r0, r0
IKobayashi 0:c88c3b616c00 156 bx lr
IKobayashi 0:c88c3b616c00 157 }
IKobayashi 0:c88c3b616c00 158 #endif
IKobayashi 0:c88c3b616c00 159
IKobayashi 0:c88c3b616c00 160
IKobayashi 0:c88c3b616c00 161 /** \brief Rotate Right in unsigned value (32 bit)
IKobayashi 0:c88c3b616c00 162
IKobayashi 0:c88c3b616c00 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
IKobayashi 0:c88c3b616c00 164
IKobayashi 0:c88c3b616c00 165 \param [in] value Value to rotate
IKobayashi 0:c88c3b616c00 166 \param [in] value Number of Bits to rotate
IKobayashi 0:c88c3b616c00 167 \return Rotated value
IKobayashi 0:c88c3b616c00 168 */
IKobayashi 0:c88c3b616c00 169 #define __ROR __ror
IKobayashi 0:c88c3b616c00 170
IKobayashi 0:c88c3b616c00 171
IKobayashi 0:c88c3b616c00 172 /** \brief Breakpoint
IKobayashi 0:c88c3b616c00 173
IKobayashi 0:c88c3b616c00 174 This function causes the processor to enter Debug state.
IKobayashi 0:c88c3b616c00 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
IKobayashi 0:c88c3b616c00 176
IKobayashi 0:c88c3b616c00 177 \param [in] value is ignored by the processor.
IKobayashi 0:c88c3b616c00 178 If required, a debugger can use it to store additional information about the breakpoint.
IKobayashi 0:c88c3b616c00 179 */
IKobayashi 0:c88c3b616c00 180 #define __BKPT(value) __breakpoint(value)
IKobayashi 0:c88c3b616c00 181
IKobayashi 0:c88c3b616c00 182
IKobayashi 0:c88c3b616c00 183 /** \brief Reverse bit order of value
IKobayashi 0:c88c3b616c00 184
IKobayashi 0:c88c3b616c00 185 This function reverses the bit order of the given value.
IKobayashi 0:c88c3b616c00 186
IKobayashi 0:c88c3b616c00 187 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 188 \return Reversed value
IKobayashi 0:c88c3b616c00 189 */
IKobayashi 0:c88c3b616c00 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
IKobayashi 0:c88c3b616c00 191 #define __RBIT __rbit
IKobayashi 0:c88c3b616c00 192 #else
IKobayashi 0:c88c3b616c00 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
IKobayashi 0:c88c3b616c00 194 {
IKobayashi 0:c88c3b616c00 195 uint32_t result;
IKobayashi 0:c88c3b616c00 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
IKobayashi 0:c88c3b616c00 197
IKobayashi 0:c88c3b616c00 198 result = value; // r will be reversed bits of v; first get LSB of v
IKobayashi 0:c88c3b616c00 199 for (value >>= 1; value; value >>= 1)
IKobayashi 0:c88c3b616c00 200 {
IKobayashi 0:c88c3b616c00 201 result <<= 1;
IKobayashi 0:c88c3b616c00 202 result |= value & 1;
IKobayashi 0:c88c3b616c00 203 s--;
IKobayashi 0:c88c3b616c00 204 }
IKobayashi 0:c88c3b616c00 205 result <<= s; // shift when v's highest bits are zero
IKobayashi 0:c88c3b616c00 206 return(result);
IKobayashi 0:c88c3b616c00 207 }
IKobayashi 0:c88c3b616c00 208 #endif
IKobayashi 0:c88c3b616c00 209
IKobayashi 0:c88c3b616c00 210
IKobayashi 0:c88c3b616c00 211 /** \brief Count leading zeros
IKobayashi 0:c88c3b616c00 212
IKobayashi 0:c88c3b616c00 213 This function counts the number of leading zeros of a data value.
IKobayashi 0:c88c3b616c00 214
IKobayashi 0:c88c3b616c00 215 \param [in] value Value to count the leading zeros
IKobayashi 0:c88c3b616c00 216 \return number of leading zeros in value
IKobayashi 0:c88c3b616c00 217 */
IKobayashi 0:c88c3b616c00 218 #define __CLZ __clz
IKobayashi 0:c88c3b616c00 219
IKobayashi 0:c88c3b616c00 220
IKobayashi 0:c88c3b616c00 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
IKobayashi 0:c88c3b616c00 222
IKobayashi 0:c88c3b616c00 223 /** \brief LDR Exclusive (8 bit)
IKobayashi 0:c88c3b616c00 224
IKobayashi 0:c88c3b616c00 225 This function executes a exclusive LDR instruction for 8 bit value.
IKobayashi 0:c88c3b616c00 226
IKobayashi 0:c88c3b616c00 227 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 228 \return value of type uint8_t at (*ptr)
IKobayashi 0:c88c3b616c00 229 */
IKobayashi 0:c88c3b616c00 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
IKobayashi 0:c88c3b616c00 231
IKobayashi 0:c88c3b616c00 232
IKobayashi 0:c88c3b616c00 233 /** \brief LDR Exclusive (16 bit)
IKobayashi 0:c88c3b616c00 234
IKobayashi 0:c88c3b616c00 235 This function executes a exclusive LDR instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 236
IKobayashi 0:c88c3b616c00 237 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 238 \return value of type uint16_t at (*ptr)
IKobayashi 0:c88c3b616c00 239 */
IKobayashi 0:c88c3b616c00 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
IKobayashi 0:c88c3b616c00 241
IKobayashi 0:c88c3b616c00 242
IKobayashi 0:c88c3b616c00 243 /** \brief LDR Exclusive (32 bit)
IKobayashi 0:c88c3b616c00 244
IKobayashi 0:c88c3b616c00 245 This function executes a exclusive LDR instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 246
IKobayashi 0:c88c3b616c00 247 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 248 \return value of type uint32_t at (*ptr)
IKobayashi 0:c88c3b616c00 249 */
IKobayashi 0:c88c3b616c00 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
IKobayashi 0:c88c3b616c00 251
IKobayashi 0:c88c3b616c00 252
IKobayashi 0:c88c3b616c00 253 /** \brief STR Exclusive (8 bit)
IKobayashi 0:c88c3b616c00 254
IKobayashi 0:c88c3b616c00 255 This function executes a exclusive STR instruction for 8 bit values.
IKobayashi 0:c88c3b616c00 256
IKobayashi 0:c88c3b616c00 257 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 258 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 259 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 260 \return 1 Function failed
IKobayashi 0:c88c3b616c00 261 */
IKobayashi 0:c88c3b616c00 262 #define __STREXB(value, ptr) __strex(value, ptr)
IKobayashi 0:c88c3b616c00 263
IKobayashi 0:c88c3b616c00 264
IKobayashi 0:c88c3b616c00 265 /** \brief STR Exclusive (16 bit)
IKobayashi 0:c88c3b616c00 266
IKobayashi 0:c88c3b616c00 267 This function executes a exclusive STR instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 268
IKobayashi 0:c88c3b616c00 269 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 270 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 271 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 272 \return 1 Function failed
IKobayashi 0:c88c3b616c00 273 */
IKobayashi 0:c88c3b616c00 274 #define __STREXH(value, ptr) __strex(value, ptr)
IKobayashi 0:c88c3b616c00 275
IKobayashi 0:c88c3b616c00 276
IKobayashi 0:c88c3b616c00 277 /** \brief STR Exclusive (32 bit)
IKobayashi 0:c88c3b616c00 278
IKobayashi 0:c88c3b616c00 279 This function executes a exclusive STR instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 280
IKobayashi 0:c88c3b616c00 281 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 282 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 283 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 284 \return 1 Function failed
IKobayashi 0:c88c3b616c00 285 */
IKobayashi 0:c88c3b616c00 286 #define __STREXW(value, ptr) __strex(value, ptr)
IKobayashi 0:c88c3b616c00 287
IKobayashi 0:c88c3b616c00 288
IKobayashi 0:c88c3b616c00 289 /** \brief Remove the exclusive lock
IKobayashi 0:c88c3b616c00 290
IKobayashi 0:c88c3b616c00 291 This function removes the exclusive lock which is created by LDREX.
IKobayashi 0:c88c3b616c00 292
IKobayashi 0:c88c3b616c00 293 */
IKobayashi 0:c88c3b616c00 294 #define __CLREX __clrex
IKobayashi 0:c88c3b616c00 295
IKobayashi 0:c88c3b616c00 296
IKobayashi 0:c88c3b616c00 297 /** \brief Signed Saturate
IKobayashi 0:c88c3b616c00 298
IKobayashi 0:c88c3b616c00 299 This function saturates a signed value.
IKobayashi 0:c88c3b616c00 300
IKobayashi 0:c88c3b616c00 301 \param [in] value Value to be saturated
IKobayashi 0:c88c3b616c00 302 \param [in] sat Bit position to saturate to (1..32)
IKobayashi 0:c88c3b616c00 303 \return Saturated value
IKobayashi 0:c88c3b616c00 304 */
IKobayashi 0:c88c3b616c00 305 #define __SSAT __ssat
IKobayashi 0:c88c3b616c00 306
IKobayashi 0:c88c3b616c00 307
IKobayashi 0:c88c3b616c00 308 /** \brief Unsigned Saturate
IKobayashi 0:c88c3b616c00 309
IKobayashi 0:c88c3b616c00 310 This function saturates an unsigned value.
IKobayashi 0:c88c3b616c00 311
IKobayashi 0:c88c3b616c00 312 \param [in] value Value to be saturated
IKobayashi 0:c88c3b616c00 313 \param [in] sat Bit position to saturate to (0..31)
IKobayashi 0:c88c3b616c00 314 \return Saturated value
IKobayashi 0:c88c3b616c00 315 */
IKobayashi 0:c88c3b616c00 316 #define __USAT __usat
IKobayashi 0:c88c3b616c00 317
IKobayashi 0:c88c3b616c00 318
IKobayashi 0:c88c3b616c00 319 /** \brief Rotate Right with Extend (32 bit)
IKobayashi 0:c88c3b616c00 320
IKobayashi 0:c88c3b616c00 321 This function moves each bit of a bitstring right by one bit.
IKobayashi 0:c88c3b616c00 322 The carry input is shifted in at the left end of the bitstring.
IKobayashi 0:c88c3b616c00 323
IKobayashi 0:c88c3b616c00 324 \param [in] value Value to rotate
IKobayashi 0:c88c3b616c00 325 \return Rotated value
IKobayashi 0:c88c3b616c00 326 */
IKobayashi 0:c88c3b616c00 327 #ifndef __NO_EMBEDDED_ASM
IKobayashi 0:c88c3b616c00 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
IKobayashi 0:c88c3b616c00 329 {
IKobayashi 0:c88c3b616c00 330 rrx r0, r0
IKobayashi 0:c88c3b616c00 331 bx lr
IKobayashi 0:c88c3b616c00 332 }
IKobayashi 0:c88c3b616c00 333 #endif
IKobayashi 0:c88c3b616c00 334
IKobayashi 0:c88c3b616c00 335
IKobayashi 0:c88c3b616c00 336 /** \brief LDRT Unprivileged (8 bit)
IKobayashi 0:c88c3b616c00 337
IKobayashi 0:c88c3b616c00 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
IKobayashi 0:c88c3b616c00 339
IKobayashi 0:c88c3b616c00 340 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 341 \return value of type uint8_t at (*ptr)
IKobayashi 0:c88c3b616c00 342 */
IKobayashi 0:c88c3b616c00 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
IKobayashi 0:c88c3b616c00 344
IKobayashi 0:c88c3b616c00 345
IKobayashi 0:c88c3b616c00 346 /** \brief LDRT Unprivileged (16 bit)
IKobayashi 0:c88c3b616c00 347
IKobayashi 0:c88c3b616c00 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 349
IKobayashi 0:c88c3b616c00 350 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 351 \return value of type uint16_t at (*ptr)
IKobayashi 0:c88c3b616c00 352 */
IKobayashi 0:c88c3b616c00 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
IKobayashi 0:c88c3b616c00 354
IKobayashi 0:c88c3b616c00 355
IKobayashi 0:c88c3b616c00 356 /** \brief LDRT Unprivileged (32 bit)
IKobayashi 0:c88c3b616c00 357
IKobayashi 0:c88c3b616c00 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 359
IKobayashi 0:c88c3b616c00 360 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 361 \return value of type uint32_t at (*ptr)
IKobayashi 0:c88c3b616c00 362 */
IKobayashi 0:c88c3b616c00 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
IKobayashi 0:c88c3b616c00 364
IKobayashi 0:c88c3b616c00 365
IKobayashi 0:c88c3b616c00 366 /** \brief STRT Unprivileged (8 bit)
IKobayashi 0:c88c3b616c00 367
IKobayashi 0:c88c3b616c00 368 This function executes a Unprivileged STRT instruction for 8 bit values.
IKobayashi 0:c88c3b616c00 369
IKobayashi 0:c88c3b616c00 370 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 371 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 372 */
IKobayashi 0:c88c3b616c00 373 #define __STRBT(value, ptr) __strt(value, ptr)
IKobayashi 0:c88c3b616c00 374
IKobayashi 0:c88c3b616c00 375
IKobayashi 0:c88c3b616c00 376 /** \brief STRT Unprivileged (16 bit)
IKobayashi 0:c88c3b616c00 377
IKobayashi 0:c88c3b616c00 378 This function executes a Unprivileged STRT instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 379
IKobayashi 0:c88c3b616c00 380 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 381 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 382 */
IKobayashi 0:c88c3b616c00 383 #define __STRHT(value, ptr) __strt(value, ptr)
IKobayashi 0:c88c3b616c00 384
IKobayashi 0:c88c3b616c00 385
IKobayashi 0:c88c3b616c00 386 /** \brief STRT Unprivileged (32 bit)
IKobayashi 0:c88c3b616c00 387
IKobayashi 0:c88c3b616c00 388 This function executes a Unprivileged STRT instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 389
IKobayashi 0:c88c3b616c00 390 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 391 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 392 */
IKobayashi 0:c88c3b616c00 393 #define __STRT(value, ptr) __strt(value, ptr)
IKobayashi 0:c88c3b616c00 394
IKobayashi 0:c88c3b616c00 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
IKobayashi 0:c88c3b616c00 396
IKobayashi 0:c88c3b616c00 397
IKobayashi 0:c88c3b616c00 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
IKobayashi 0:c88c3b616c00 399 /* GNU gcc specific functions */
IKobayashi 0:c88c3b616c00 400
IKobayashi 0:c88c3b616c00 401 /* Define macros for porting to both thumb1 and thumb2.
IKobayashi 0:c88c3b616c00 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
IKobayashi 0:c88c3b616c00 403 * Otherwise, use general registers, specified by constrant "r" */
IKobayashi 0:c88c3b616c00 404 #if defined (__thumb__) && !defined (__thumb2__)
IKobayashi 0:c88c3b616c00 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
IKobayashi 0:c88c3b616c00 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
IKobayashi 0:c88c3b616c00 407 #else
IKobayashi 0:c88c3b616c00 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
IKobayashi 0:c88c3b616c00 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
IKobayashi 0:c88c3b616c00 410 #endif
IKobayashi 0:c88c3b616c00 411
IKobayashi 0:c88c3b616c00 412 /** \brief No Operation
IKobayashi 0:c88c3b616c00 413
IKobayashi 0:c88c3b616c00 414 No Operation does nothing. This instruction can be used for code alignment purposes.
IKobayashi 0:c88c3b616c00 415 */
IKobayashi 0:c88c3b616c00 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
IKobayashi 0:c88c3b616c00 417 {
IKobayashi 0:c88c3b616c00 418 __ASM volatile ("nop");
IKobayashi 0:c88c3b616c00 419 }
IKobayashi 0:c88c3b616c00 420
IKobayashi 0:c88c3b616c00 421
IKobayashi 0:c88c3b616c00 422 /** \brief Wait For Interrupt
IKobayashi 0:c88c3b616c00 423
IKobayashi 0:c88c3b616c00 424 Wait For Interrupt is a hint instruction that suspends execution
IKobayashi 0:c88c3b616c00 425 until one of a number of events occurs.
IKobayashi 0:c88c3b616c00 426 */
IKobayashi 0:c88c3b616c00 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
IKobayashi 0:c88c3b616c00 428 {
IKobayashi 0:c88c3b616c00 429 __ASM volatile ("wfi");
IKobayashi 0:c88c3b616c00 430 }
IKobayashi 0:c88c3b616c00 431
IKobayashi 0:c88c3b616c00 432
IKobayashi 0:c88c3b616c00 433 /** \brief Wait For Event
IKobayashi 0:c88c3b616c00 434
IKobayashi 0:c88c3b616c00 435 Wait For Event is a hint instruction that permits the processor to enter
IKobayashi 0:c88c3b616c00 436 a low-power state until one of a number of events occurs.
IKobayashi 0:c88c3b616c00 437 */
IKobayashi 0:c88c3b616c00 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
IKobayashi 0:c88c3b616c00 439 {
IKobayashi 0:c88c3b616c00 440 __ASM volatile ("wfe");
IKobayashi 0:c88c3b616c00 441 }
IKobayashi 0:c88c3b616c00 442
IKobayashi 0:c88c3b616c00 443
IKobayashi 0:c88c3b616c00 444 /** \brief Send Event
IKobayashi 0:c88c3b616c00 445
IKobayashi 0:c88c3b616c00 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
IKobayashi 0:c88c3b616c00 447 */
IKobayashi 0:c88c3b616c00 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
IKobayashi 0:c88c3b616c00 449 {
IKobayashi 0:c88c3b616c00 450 __ASM volatile ("sev");
IKobayashi 0:c88c3b616c00 451 }
IKobayashi 0:c88c3b616c00 452
IKobayashi 0:c88c3b616c00 453
IKobayashi 0:c88c3b616c00 454 /** \brief Instruction Synchronization Barrier
IKobayashi 0:c88c3b616c00 455
IKobayashi 0:c88c3b616c00 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
IKobayashi 0:c88c3b616c00 457 so that all instructions following the ISB are fetched from cache or
IKobayashi 0:c88c3b616c00 458 memory, after the instruction has been completed.
IKobayashi 0:c88c3b616c00 459 */
IKobayashi 0:c88c3b616c00 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
IKobayashi 0:c88c3b616c00 461 {
IKobayashi 0:c88c3b616c00 462 __ASM volatile ("isb 0xF":::"memory");
IKobayashi 0:c88c3b616c00 463 }
IKobayashi 0:c88c3b616c00 464
IKobayashi 0:c88c3b616c00 465
IKobayashi 0:c88c3b616c00 466 /** \brief Data Synchronization Barrier
IKobayashi 0:c88c3b616c00 467
IKobayashi 0:c88c3b616c00 468 This function acts as a special kind of Data Memory Barrier.
IKobayashi 0:c88c3b616c00 469 It completes when all explicit memory accesses before this instruction complete.
IKobayashi 0:c88c3b616c00 470 */
IKobayashi 0:c88c3b616c00 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
IKobayashi 0:c88c3b616c00 472 {
IKobayashi 0:c88c3b616c00 473 __ASM volatile ("dsb 0xF":::"memory");
IKobayashi 0:c88c3b616c00 474 }
IKobayashi 0:c88c3b616c00 475
IKobayashi 0:c88c3b616c00 476
IKobayashi 0:c88c3b616c00 477 /** \brief Data Memory Barrier
IKobayashi 0:c88c3b616c00 478
IKobayashi 0:c88c3b616c00 479 This function ensures the apparent order of the explicit memory operations before
IKobayashi 0:c88c3b616c00 480 and after the instruction, without ensuring their completion.
IKobayashi 0:c88c3b616c00 481 */
IKobayashi 0:c88c3b616c00 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
IKobayashi 0:c88c3b616c00 483 {
IKobayashi 0:c88c3b616c00 484 __ASM volatile ("dmb 0xF":::"memory");
IKobayashi 0:c88c3b616c00 485 }
IKobayashi 0:c88c3b616c00 486
IKobayashi 0:c88c3b616c00 487
IKobayashi 0:c88c3b616c00 488 /** \brief Reverse byte order (32 bit)
IKobayashi 0:c88c3b616c00 489
IKobayashi 0:c88c3b616c00 490 This function reverses the byte order in integer value.
IKobayashi 0:c88c3b616c00 491
IKobayashi 0:c88c3b616c00 492 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 493 \return Reversed value
IKobayashi 0:c88c3b616c00 494 */
IKobayashi 0:c88c3b616c00 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
IKobayashi 0:c88c3b616c00 496 {
IKobayashi 0:c88c3b616c00 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
IKobayashi 0:c88c3b616c00 498 return __builtin_bswap32(value);
IKobayashi 0:c88c3b616c00 499 #else
IKobayashi 0:c88c3b616c00 500 uint32_t result;
IKobayashi 0:c88c3b616c00 501
IKobayashi 0:c88c3b616c00 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
IKobayashi 0:c88c3b616c00 503 return(result);
IKobayashi 0:c88c3b616c00 504 #endif
IKobayashi 0:c88c3b616c00 505 }
IKobayashi 0:c88c3b616c00 506
IKobayashi 0:c88c3b616c00 507
IKobayashi 0:c88c3b616c00 508 /** \brief Reverse byte order (16 bit)
IKobayashi 0:c88c3b616c00 509
IKobayashi 0:c88c3b616c00 510 This function reverses the byte order in two unsigned short values.
IKobayashi 0:c88c3b616c00 511
IKobayashi 0:c88c3b616c00 512 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 513 \return Reversed value
IKobayashi 0:c88c3b616c00 514 */
IKobayashi 0:c88c3b616c00 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
IKobayashi 0:c88c3b616c00 516 {
IKobayashi 0:c88c3b616c00 517 uint32_t result;
IKobayashi 0:c88c3b616c00 518
IKobayashi 0:c88c3b616c00 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
IKobayashi 0:c88c3b616c00 520 return(result);
IKobayashi 0:c88c3b616c00 521 }
IKobayashi 0:c88c3b616c00 522
IKobayashi 0:c88c3b616c00 523
IKobayashi 0:c88c3b616c00 524 /** \brief Reverse byte order in signed short value
IKobayashi 0:c88c3b616c00 525
IKobayashi 0:c88c3b616c00 526 This function reverses the byte order in a signed short value with sign extension to integer.
IKobayashi 0:c88c3b616c00 527
IKobayashi 0:c88c3b616c00 528 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 529 \return Reversed value
IKobayashi 0:c88c3b616c00 530 */
IKobayashi 0:c88c3b616c00 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
IKobayashi 0:c88c3b616c00 532 {
IKobayashi 0:c88c3b616c00 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
IKobayashi 0:c88c3b616c00 534 return (short)__builtin_bswap16(value);
IKobayashi 0:c88c3b616c00 535 #else
IKobayashi 0:c88c3b616c00 536 uint32_t result;
IKobayashi 0:c88c3b616c00 537
IKobayashi 0:c88c3b616c00 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
IKobayashi 0:c88c3b616c00 539 return(result);
IKobayashi 0:c88c3b616c00 540 #endif
IKobayashi 0:c88c3b616c00 541 }
IKobayashi 0:c88c3b616c00 542
IKobayashi 0:c88c3b616c00 543
IKobayashi 0:c88c3b616c00 544 /** \brief Rotate Right in unsigned value (32 bit)
IKobayashi 0:c88c3b616c00 545
IKobayashi 0:c88c3b616c00 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
IKobayashi 0:c88c3b616c00 547
IKobayashi 0:c88c3b616c00 548 \param [in] value Value to rotate
IKobayashi 0:c88c3b616c00 549 \param [in] value Number of Bits to rotate
IKobayashi 0:c88c3b616c00 550 \return Rotated value
IKobayashi 0:c88c3b616c00 551 */
IKobayashi 0:c88c3b616c00 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
IKobayashi 0:c88c3b616c00 553 {
IKobayashi 0:c88c3b616c00 554 return (op1 >> op2) | (op1 << (32 - op2));
IKobayashi 0:c88c3b616c00 555 }
IKobayashi 0:c88c3b616c00 556
IKobayashi 0:c88c3b616c00 557
IKobayashi 0:c88c3b616c00 558 /** \brief Breakpoint
IKobayashi 0:c88c3b616c00 559
IKobayashi 0:c88c3b616c00 560 This function causes the processor to enter Debug state.
IKobayashi 0:c88c3b616c00 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
IKobayashi 0:c88c3b616c00 562
IKobayashi 0:c88c3b616c00 563 \param [in] value is ignored by the processor.
IKobayashi 0:c88c3b616c00 564 If required, a debugger can use it to store additional information about the breakpoint.
IKobayashi 0:c88c3b616c00 565 */
IKobayashi 0:c88c3b616c00 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
IKobayashi 0:c88c3b616c00 567
IKobayashi 0:c88c3b616c00 568
IKobayashi 0:c88c3b616c00 569 /** \brief Reverse bit order of value
IKobayashi 0:c88c3b616c00 570
IKobayashi 0:c88c3b616c00 571 This function reverses the bit order of the given value.
IKobayashi 0:c88c3b616c00 572
IKobayashi 0:c88c3b616c00 573 \param [in] value Value to reverse
IKobayashi 0:c88c3b616c00 574 \return Reversed value
IKobayashi 0:c88c3b616c00 575 */
IKobayashi 0:c88c3b616c00 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
IKobayashi 0:c88c3b616c00 577 {
IKobayashi 0:c88c3b616c00 578 uint32_t result;
IKobayashi 0:c88c3b616c00 579
IKobayashi 0:c88c3b616c00 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
IKobayashi 0:c88c3b616c00 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
IKobayashi 0:c88c3b616c00 582 #else
IKobayashi 0:c88c3b616c00 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
IKobayashi 0:c88c3b616c00 584
IKobayashi 0:c88c3b616c00 585 result = value; // r will be reversed bits of v; first get LSB of v
IKobayashi 0:c88c3b616c00 586 for (value >>= 1; value; value >>= 1)
IKobayashi 0:c88c3b616c00 587 {
IKobayashi 0:c88c3b616c00 588 result <<= 1;
IKobayashi 0:c88c3b616c00 589 result |= value & 1;
IKobayashi 0:c88c3b616c00 590 s--;
IKobayashi 0:c88c3b616c00 591 }
IKobayashi 0:c88c3b616c00 592 result <<= s; // shift when v's highest bits are zero
IKobayashi 0:c88c3b616c00 593 #endif
IKobayashi 0:c88c3b616c00 594 return(result);
IKobayashi 0:c88c3b616c00 595 }
IKobayashi 0:c88c3b616c00 596
IKobayashi 0:c88c3b616c00 597
IKobayashi 0:c88c3b616c00 598 /** \brief Count leading zeros
IKobayashi 0:c88c3b616c00 599
IKobayashi 0:c88c3b616c00 600 This function counts the number of leading zeros of a data value.
IKobayashi 0:c88c3b616c00 601
IKobayashi 0:c88c3b616c00 602 \param [in] value Value to count the leading zeros
IKobayashi 0:c88c3b616c00 603 \return number of leading zeros in value
IKobayashi 0:c88c3b616c00 604 */
IKobayashi 0:c88c3b616c00 605 #define __CLZ __builtin_clz
IKobayashi 0:c88c3b616c00 606
IKobayashi 0:c88c3b616c00 607
IKobayashi 0:c88c3b616c00 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
IKobayashi 0:c88c3b616c00 609
IKobayashi 0:c88c3b616c00 610 /** \brief LDR Exclusive (8 bit)
IKobayashi 0:c88c3b616c00 611
IKobayashi 0:c88c3b616c00 612 This function executes a exclusive LDR instruction for 8 bit value.
IKobayashi 0:c88c3b616c00 613
IKobayashi 0:c88c3b616c00 614 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 615 \return value of type uint8_t at (*ptr)
IKobayashi 0:c88c3b616c00 616 */
IKobayashi 0:c88c3b616c00 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
IKobayashi 0:c88c3b616c00 618 {
IKobayashi 0:c88c3b616c00 619 uint32_t result;
IKobayashi 0:c88c3b616c00 620
IKobayashi 0:c88c3b616c00 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
IKobayashi 0:c88c3b616c00 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 623 #else
IKobayashi 0:c88c3b616c00 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
IKobayashi 0:c88c3b616c00 625 accepted by assembler. So has to use following less efficient pattern.
IKobayashi 0:c88c3b616c00 626 */
IKobayashi 0:c88c3b616c00 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
IKobayashi 0:c88c3b616c00 628 #endif
IKobayashi 0:c88c3b616c00 629 return ((uint8_t) result); /* Add explicit type cast here */
IKobayashi 0:c88c3b616c00 630 }
IKobayashi 0:c88c3b616c00 631
IKobayashi 0:c88c3b616c00 632
IKobayashi 0:c88c3b616c00 633 /** \brief LDR Exclusive (16 bit)
IKobayashi 0:c88c3b616c00 634
IKobayashi 0:c88c3b616c00 635 This function executes a exclusive LDR instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 636
IKobayashi 0:c88c3b616c00 637 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 638 \return value of type uint16_t at (*ptr)
IKobayashi 0:c88c3b616c00 639 */
IKobayashi 0:c88c3b616c00 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
IKobayashi 0:c88c3b616c00 641 {
IKobayashi 0:c88c3b616c00 642 uint32_t result;
IKobayashi 0:c88c3b616c00 643
IKobayashi 0:c88c3b616c00 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
IKobayashi 0:c88c3b616c00 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 646 #else
IKobayashi 0:c88c3b616c00 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
IKobayashi 0:c88c3b616c00 648 accepted by assembler. So has to use following less efficient pattern.
IKobayashi 0:c88c3b616c00 649 */
IKobayashi 0:c88c3b616c00 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
IKobayashi 0:c88c3b616c00 651 #endif
IKobayashi 0:c88c3b616c00 652 return ((uint16_t) result); /* Add explicit type cast here */
IKobayashi 0:c88c3b616c00 653 }
IKobayashi 0:c88c3b616c00 654
IKobayashi 0:c88c3b616c00 655
IKobayashi 0:c88c3b616c00 656 /** \brief LDR Exclusive (32 bit)
IKobayashi 0:c88c3b616c00 657
IKobayashi 0:c88c3b616c00 658 This function executes a exclusive LDR instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 659
IKobayashi 0:c88c3b616c00 660 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 661 \return value of type uint32_t at (*ptr)
IKobayashi 0:c88c3b616c00 662 */
IKobayashi 0:c88c3b616c00 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
IKobayashi 0:c88c3b616c00 664 {
IKobayashi 0:c88c3b616c00 665 uint32_t result;
IKobayashi 0:c88c3b616c00 666
IKobayashi 0:c88c3b616c00 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 668 return(result);
IKobayashi 0:c88c3b616c00 669 }
IKobayashi 0:c88c3b616c00 670
IKobayashi 0:c88c3b616c00 671
IKobayashi 0:c88c3b616c00 672 /** \brief STR Exclusive (8 bit)
IKobayashi 0:c88c3b616c00 673
IKobayashi 0:c88c3b616c00 674 This function executes a exclusive STR instruction for 8 bit values.
IKobayashi 0:c88c3b616c00 675
IKobayashi 0:c88c3b616c00 676 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 677 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 678 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 679 \return 1 Function failed
IKobayashi 0:c88c3b616c00 680 */
IKobayashi 0:c88c3b616c00 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
IKobayashi 0:c88c3b616c00 682 {
IKobayashi 0:c88c3b616c00 683 uint32_t result;
IKobayashi 0:c88c3b616c00 684
IKobayashi 0:c88c3b616c00 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
IKobayashi 0:c88c3b616c00 686 return(result);
IKobayashi 0:c88c3b616c00 687 }
IKobayashi 0:c88c3b616c00 688
IKobayashi 0:c88c3b616c00 689
IKobayashi 0:c88c3b616c00 690 /** \brief STR Exclusive (16 bit)
IKobayashi 0:c88c3b616c00 691
IKobayashi 0:c88c3b616c00 692 This function executes a exclusive STR instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 693
IKobayashi 0:c88c3b616c00 694 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 695 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 696 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 697 \return 1 Function failed
IKobayashi 0:c88c3b616c00 698 */
IKobayashi 0:c88c3b616c00 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
IKobayashi 0:c88c3b616c00 700 {
IKobayashi 0:c88c3b616c00 701 uint32_t result;
IKobayashi 0:c88c3b616c00 702
IKobayashi 0:c88c3b616c00 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
IKobayashi 0:c88c3b616c00 704 return(result);
IKobayashi 0:c88c3b616c00 705 }
IKobayashi 0:c88c3b616c00 706
IKobayashi 0:c88c3b616c00 707
IKobayashi 0:c88c3b616c00 708 /** \brief STR Exclusive (32 bit)
IKobayashi 0:c88c3b616c00 709
IKobayashi 0:c88c3b616c00 710 This function executes a exclusive STR instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 711
IKobayashi 0:c88c3b616c00 712 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 713 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 714 \return 0 Function succeeded
IKobayashi 0:c88c3b616c00 715 \return 1 Function failed
IKobayashi 0:c88c3b616c00 716 */
IKobayashi 0:c88c3b616c00 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
IKobayashi 0:c88c3b616c00 718 {
IKobayashi 0:c88c3b616c00 719 uint32_t result;
IKobayashi 0:c88c3b616c00 720
IKobayashi 0:c88c3b616c00 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
IKobayashi 0:c88c3b616c00 722 return(result);
IKobayashi 0:c88c3b616c00 723 }
IKobayashi 0:c88c3b616c00 724
IKobayashi 0:c88c3b616c00 725
IKobayashi 0:c88c3b616c00 726 /** \brief Remove the exclusive lock
IKobayashi 0:c88c3b616c00 727
IKobayashi 0:c88c3b616c00 728 This function removes the exclusive lock which is created by LDREX.
IKobayashi 0:c88c3b616c00 729
IKobayashi 0:c88c3b616c00 730 */
IKobayashi 0:c88c3b616c00 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
IKobayashi 0:c88c3b616c00 732 {
IKobayashi 0:c88c3b616c00 733 __ASM volatile ("clrex" ::: "memory");
IKobayashi 0:c88c3b616c00 734 }
IKobayashi 0:c88c3b616c00 735
IKobayashi 0:c88c3b616c00 736
IKobayashi 0:c88c3b616c00 737 /** \brief Signed Saturate
IKobayashi 0:c88c3b616c00 738
IKobayashi 0:c88c3b616c00 739 This function saturates a signed value.
IKobayashi 0:c88c3b616c00 740
IKobayashi 0:c88c3b616c00 741 \param [in] value Value to be saturated
IKobayashi 0:c88c3b616c00 742 \param [in] sat Bit position to saturate to (1..32)
IKobayashi 0:c88c3b616c00 743 \return Saturated value
IKobayashi 0:c88c3b616c00 744 */
IKobayashi 0:c88c3b616c00 745 #define __SSAT(ARG1,ARG2) \
IKobayashi 0:c88c3b616c00 746 ({ \
IKobayashi 0:c88c3b616c00 747 uint32_t __RES, __ARG1 = (ARG1); \
IKobayashi 0:c88c3b616c00 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
IKobayashi 0:c88c3b616c00 749 __RES; \
IKobayashi 0:c88c3b616c00 750 })
IKobayashi 0:c88c3b616c00 751
IKobayashi 0:c88c3b616c00 752
IKobayashi 0:c88c3b616c00 753 /** \brief Unsigned Saturate
IKobayashi 0:c88c3b616c00 754
IKobayashi 0:c88c3b616c00 755 This function saturates an unsigned value.
IKobayashi 0:c88c3b616c00 756
IKobayashi 0:c88c3b616c00 757 \param [in] value Value to be saturated
IKobayashi 0:c88c3b616c00 758 \param [in] sat Bit position to saturate to (0..31)
IKobayashi 0:c88c3b616c00 759 \return Saturated value
IKobayashi 0:c88c3b616c00 760 */
IKobayashi 0:c88c3b616c00 761 #define __USAT(ARG1,ARG2) \
IKobayashi 0:c88c3b616c00 762 ({ \
IKobayashi 0:c88c3b616c00 763 uint32_t __RES, __ARG1 = (ARG1); \
IKobayashi 0:c88c3b616c00 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
IKobayashi 0:c88c3b616c00 765 __RES; \
IKobayashi 0:c88c3b616c00 766 })
IKobayashi 0:c88c3b616c00 767
IKobayashi 0:c88c3b616c00 768
IKobayashi 0:c88c3b616c00 769 /** \brief Rotate Right with Extend (32 bit)
IKobayashi 0:c88c3b616c00 770
IKobayashi 0:c88c3b616c00 771 This function moves each bit of a bitstring right by one bit.
IKobayashi 0:c88c3b616c00 772 The carry input is shifted in at the left end of the bitstring.
IKobayashi 0:c88c3b616c00 773
IKobayashi 0:c88c3b616c00 774 \param [in] value Value to rotate
IKobayashi 0:c88c3b616c00 775 \return Rotated value
IKobayashi 0:c88c3b616c00 776 */
IKobayashi 0:c88c3b616c00 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
IKobayashi 0:c88c3b616c00 778 {
IKobayashi 0:c88c3b616c00 779 uint32_t result;
IKobayashi 0:c88c3b616c00 780
IKobayashi 0:c88c3b616c00 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
IKobayashi 0:c88c3b616c00 782 return(result);
IKobayashi 0:c88c3b616c00 783 }
IKobayashi 0:c88c3b616c00 784
IKobayashi 0:c88c3b616c00 785
IKobayashi 0:c88c3b616c00 786 /** \brief LDRT Unprivileged (8 bit)
IKobayashi 0:c88c3b616c00 787
IKobayashi 0:c88c3b616c00 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
IKobayashi 0:c88c3b616c00 789
IKobayashi 0:c88c3b616c00 790 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 791 \return value of type uint8_t at (*ptr)
IKobayashi 0:c88c3b616c00 792 */
IKobayashi 0:c88c3b616c00 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
IKobayashi 0:c88c3b616c00 794 {
IKobayashi 0:c88c3b616c00 795 uint32_t result;
IKobayashi 0:c88c3b616c00 796
IKobayashi 0:c88c3b616c00 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
IKobayashi 0:c88c3b616c00 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 799 #else
IKobayashi 0:c88c3b616c00 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
IKobayashi 0:c88c3b616c00 801 accepted by assembler. So has to use following less efficient pattern.
IKobayashi 0:c88c3b616c00 802 */
IKobayashi 0:c88c3b616c00 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
IKobayashi 0:c88c3b616c00 804 #endif
IKobayashi 0:c88c3b616c00 805 return ((uint8_t) result); /* Add explicit type cast here */
IKobayashi 0:c88c3b616c00 806 }
IKobayashi 0:c88c3b616c00 807
IKobayashi 0:c88c3b616c00 808
IKobayashi 0:c88c3b616c00 809 /** \brief LDRT Unprivileged (16 bit)
IKobayashi 0:c88c3b616c00 810
IKobayashi 0:c88c3b616c00 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 812
IKobayashi 0:c88c3b616c00 813 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 814 \return value of type uint16_t at (*ptr)
IKobayashi 0:c88c3b616c00 815 */
IKobayashi 0:c88c3b616c00 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
IKobayashi 0:c88c3b616c00 817 {
IKobayashi 0:c88c3b616c00 818 uint32_t result;
IKobayashi 0:c88c3b616c00 819
IKobayashi 0:c88c3b616c00 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
IKobayashi 0:c88c3b616c00 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 822 #else
IKobayashi 0:c88c3b616c00 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
IKobayashi 0:c88c3b616c00 824 accepted by assembler. So has to use following less efficient pattern.
IKobayashi 0:c88c3b616c00 825 */
IKobayashi 0:c88c3b616c00 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
IKobayashi 0:c88c3b616c00 827 #endif
IKobayashi 0:c88c3b616c00 828 return ((uint16_t) result); /* Add explicit type cast here */
IKobayashi 0:c88c3b616c00 829 }
IKobayashi 0:c88c3b616c00 830
IKobayashi 0:c88c3b616c00 831
IKobayashi 0:c88c3b616c00 832 /** \brief LDRT Unprivileged (32 bit)
IKobayashi 0:c88c3b616c00 833
IKobayashi 0:c88c3b616c00 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 835
IKobayashi 0:c88c3b616c00 836 \param [in] ptr Pointer to data
IKobayashi 0:c88c3b616c00 837 \return value of type uint32_t at (*ptr)
IKobayashi 0:c88c3b616c00 838 */
IKobayashi 0:c88c3b616c00 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
IKobayashi 0:c88c3b616c00 840 {
IKobayashi 0:c88c3b616c00 841 uint32_t result;
IKobayashi 0:c88c3b616c00 842
IKobayashi 0:c88c3b616c00 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
IKobayashi 0:c88c3b616c00 844 return(result);
IKobayashi 0:c88c3b616c00 845 }
IKobayashi 0:c88c3b616c00 846
IKobayashi 0:c88c3b616c00 847
IKobayashi 0:c88c3b616c00 848 /** \brief STRT Unprivileged (8 bit)
IKobayashi 0:c88c3b616c00 849
IKobayashi 0:c88c3b616c00 850 This function executes a Unprivileged STRT instruction for 8 bit values.
IKobayashi 0:c88c3b616c00 851
IKobayashi 0:c88c3b616c00 852 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 853 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 854 */
IKobayashi 0:c88c3b616c00 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
IKobayashi 0:c88c3b616c00 856 {
IKobayashi 0:c88c3b616c00 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
IKobayashi 0:c88c3b616c00 858 }
IKobayashi 0:c88c3b616c00 859
IKobayashi 0:c88c3b616c00 860
IKobayashi 0:c88c3b616c00 861 /** \brief STRT Unprivileged (16 bit)
IKobayashi 0:c88c3b616c00 862
IKobayashi 0:c88c3b616c00 863 This function executes a Unprivileged STRT instruction for 16 bit values.
IKobayashi 0:c88c3b616c00 864
IKobayashi 0:c88c3b616c00 865 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 866 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 867 */
IKobayashi 0:c88c3b616c00 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
IKobayashi 0:c88c3b616c00 869 {
IKobayashi 0:c88c3b616c00 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
IKobayashi 0:c88c3b616c00 871 }
IKobayashi 0:c88c3b616c00 872
IKobayashi 0:c88c3b616c00 873
IKobayashi 0:c88c3b616c00 874 /** \brief STRT Unprivileged (32 bit)
IKobayashi 0:c88c3b616c00 875
IKobayashi 0:c88c3b616c00 876 This function executes a Unprivileged STRT instruction for 32 bit values.
IKobayashi 0:c88c3b616c00 877
IKobayashi 0:c88c3b616c00 878 \param [in] value Value to store
IKobayashi 0:c88c3b616c00 879 \param [in] ptr Pointer to location
IKobayashi 0:c88c3b616c00 880 */
IKobayashi 0:c88c3b616c00 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
IKobayashi 0:c88c3b616c00 882 {
IKobayashi 0:c88c3b616c00 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
IKobayashi 0:c88c3b616c00 884 }
IKobayashi 0:c88c3b616c00 885
IKobayashi 0:c88c3b616c00 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
IKobayashi 0:c88c3b616c00 887
IKobayashi 0:c88c3b616c00 888
IKobayashi 0:c88c3b616c00 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 890 /* IAR iccarm specific functions */
IKobayashi 0:c88c3b616c00 891 #include <cmsis_iar.h>
IKobayashi 0:c88c3b616c00 892
IKobayashi 0:c88c3b616c00 893
IKobayashi 0:c88c3b616c00 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
IKobayashi 0:c88c3b616c00 895 /* TI CCS specific functions */
IKobayashi 0:c88c3b616c00 896 #include <cmsis_ccs.h>
IKobayashi 0:c88c3b616c00 897
IKobayashi 0:c88c3b616c00 898
IKobayashi 0:c88c3b616c00 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
IKobayashi 0:c88c3b616c00 900 /* TASKING carm specific functions */
IKobayashi 0:c88c3b616c00 901 /*
IKobayashi 0:c88c3b616c00 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
IKobayashi 0:c88c3b616c00 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
IKobayashi 0:c88c3b616c00 904 * Including the CMSIS ones.
IKobayashi 0:c88c3b616c00 905 */
IKobayashi 0:c88c3b616c00 906
IKobayashi 0:c88c3b616c00 907
IKobayashi 0:c88c3b616c00 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 909 /* Cosmic specific functions */
IKobayashi 0:c88c3b616c00 910 #include <cmsis_csm.h>
IKobayashi 0:c88c3b616c00 911
IKobayashi 0:c88c3b616c00 912 #endif
IKobayashi 0:c88c3b616c00 913
IKobayashi 0:c88c3b616c00 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
IKobayashi 0:c88c3b616c00 915
IKobayashi 0:c88c3b616c00 916 #endif /* __CORE_CMINSTR_H */