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mbed/TARGET_LPC1768/core_cmFunc.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file core_cmFunc.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M Core Function Access Header File
IKobayashi 0:c88c3b616c00 4 * @version V4.10
IKobayashi 0:c88c3b616c00 5 * @date 18. March 2015
IKobayashi 0:c88c3b616c00 6 *
IKobayashi 0:c88c3b616c00 7 * @note
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 ******************************************************************************/
IKobayashi 0:c88c3b616c00 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
IKobayashi 0:c88c3b616c00 11
IKobayashi 0:c88c3b616c00 12 All rights reserved.
IKobayashi 0:c88c3b616c00 13 Redistribution and use in source and binary forms, with or without
IKobayashi 0:c88c3b616c00 14 modification, are permitted provided that the following conditions are met:
IKobayashi 0:c88c3b616c00 15 - Redistributions of source code must retain the above copyright
IKobayashi 0:c88c3b616c00 16 notice, this list of conditions and the following disclaimer.
IKobayashi 0:c88c3b616c00 17 - Redistributions in binary form must reproduce the above copyright
IKobayashi 0:c88c3b616c00 18 notice, this list of conditions and the following disclaimer in the
IKobayashi 0:c88c3b616c00 19 documentation and/or other materials provided with the distribution.
IKobayashi 0:c88c3b616c00 20 - Neither the name of ARM nor the names of its contributors may be used
IKobayashi 0:c88c3b616c00 21 to endorse or promote products derived from this software without
IKobayashi 0:c88c3b616c00 22 specific prior written permission.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi 0:c88c3b616c00 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi 0:c88c3b616c00 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi 0:c88c3b616c00 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi 0:c88c3b616c00 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi 0:c88c3b616c00 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi 0:c88c3b616c00 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi 0:c88c3b616c00 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi 0:c88c3b616c00 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi 0:c88c3b616c00 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi 0:c88c3b616c00 34 POSSIBILITY OF SUCH DAMAGE.
IKobayashi 0:c88c3b616c00 35 ---------------------------------------------------------------------------*/
IKobayashi 0:c88c3b616c00 36
IKobayashi 0:c88c3b616c00 37
IKobayashi 0:c88c3b616c00 38 #ifndef __CORE_CMFUNC_H
IKobayashi 0:c88c3b616c00 39 #define __CORE_CMFUNC_H
IKobayashi 0:c88c3b616c00 40
IKobayashi 0:c88c3b616c00 41
IKobayashi 0:c88c3b616c00 42 /* ########################### Core Function Access ########################### */
IKobayashi 0:c88c3b616c00 43 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
IKobayashi 0:c88c3b616c00 45 @{
IKobayashi 0:c88c3b616c00 46 */
IKobayashi 0:c88c3b616c00 47
IKobayashi 0:c88c3b616c00 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
IKobayashi 0:c88c3b616c00 49 /* ARM armcc specific functions */
IKobayashi 0:c88c3b616c00 50
IKobayashi 0:c88c3b616c00 51 #if (__ARMCC_VERSION < 400677)
IKobayashi 0:c88c3b616c00 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
IKobayashi 0:c88c3b616c00 53 #endif
IKobayashi 0:c88c3b616c00 54
IKobayashi 0:c88c3b616c00 55 /* intrinsic void __enable_irq(); */
IKobayashi 0:c88c3b616c00 56 /* intrinsic void __disable_irq(); */
IKobayashi 0:c88c3b616c00 57
IKobayashi 0:c88c3b616c00 58 /** \brief Get Control Register
IKobayashi 0:c88c3b616c00 59
IKobayashi 0:c88c3b616c00 60 This function returns the content of the Control Register.
IKobayashi 0:c88c3b616c00 61
IKobayashi 0:c88c3b616c00 62 \return Control Register value
IKobayashi 0:c88c3b616c00 63 */
IKobayashi 0:c88c3b616c00 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
IKobayashi 0:c88c3b616c00 65 {
IKobayashi 0:c88c3b616c00 66 register uint32_t __regControl __ASM("control");
IKobayashi 0:c88c3b616c00 67 return(__regControl);
IKobayashi 0:c88c3b616c00 68 }
IKobayashi 0:c88c3b616c00 69
IKobayashi 0:c88c3b616c00 70
IKobayashi 0:c88c3b616c00 71 /** \brief Set Control Register
IKobayashi 0:c88c3b616c00 72
IKobayashi 0:c88c3b616c00 73 This function writes the given value to the Control Register.
IKobayashi 0:c88c3b616c00 74
IKobayashi 0:c88c3b616c00 75 \param [in] control Control Register value to set
IKobayashi 0:c88c3b616c00 76 */
IKobayashi 0:c88c3b616c00 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
IKobayashi 0:c88c3b616c00 78 {
IKobayashi 0:c88c3b616c00 79 register uint32_t __regControl __ASM("control");
IKobayashi 0:c88c3b616c00 80 __regControl = control;
IKobayashi 0:c88c3b616c00 81 }
IKobayashi 0:c88c3b616c00 82
IKobayashi 0:c88c3b616c00 83
IKobayashi 0:c88c3b616c00 84 /** \brief Get IPSR Register
IKobayashi 0:c88c3b616c00 85
IKobayashi 0:c88c3b616c00 86 This function returns the content of the IPSR Register.
IKobayashi 0:c88c3b616c00 87
IKobayashi 0:c88c3b616c00 88 \return IPSR Register value
IKobayashi 0:c88c3b616c00 89 */
IKobayashi 0:c88c3b616c00 90 __STATIC_INLINE uint32_t __get_IPSR(void)
IKobayashi 0:c88c3b616c00 91 {
IKobayashi 0:c88c3b616c00 92 register uint32_t __regIPSR __ASM("ipsr");
IKobayashi 0:c88c3b616c00 93 return(__regIPSR);
IKobayashi 0:c88c3b616c00 94 }
IKobayashi 0:c88c3b616c00 95
IKobayashi 0:c88c3b616c00 96
IKobayashi 0:c88c3b616c00 97 /** \brief Get APSR Register
IKobayashi 0:c88c3b616c00 98
IKobayashi 0:c88c3b616c00 99 This function returns the content of the APSR Register.
IKobayashi 0:c88c3b616c00 100
IKobayashi 0:c88c3b616c00 101 \return APSR Register value
IKobayashi 0:c88c3b616c00 102 */
IKobayashi 0:c88c3b616c00 103 __STATIC_INLINE uint32_t __get_APSR(void)
IKobayashi 0:c88c3b616c00 104 {
IKobayashi 0:c88c3b616c00 105 register uint32_t __regAPSR __ASM("apsr");
IKobayashi 0:c88c3b616c00 106 return(__regAPSR);
IKobayashi 0:c88c3b616c00 107 }
IKobayashi 0:c88c3b616c00 108
IKobayashi 0:c88c3b616c00 109
IKobayashi 0:c88c3b616c00 110 /** \brief Get xPSR Register
IKobayashi 0:c88c3b616c00 111
IKobayashi 0:c88c3b616c00 112 This function returns the content of the xPSR Register.
IKobayashi 0:c88c3b616c00 113
IKobayashi 0:c88c3b616c00 114 \return xPSR Register value
IKobayashi 0:c88c3b616c00 115 */
IKobayashi 0:c88c3b616c00 116 __STATIC_INLINE uint32_t __get_xPSR(void)
IKobayashi 0:c88c3b616c00 117 {
IKobayashi 0:c88c3b616c00 118 register uint32_t __regXPSR __ASM("xpsr");
IKobayashi 0:c88c3b616c00 119 return(__regXPSR);
IKobayashi 0:c88c3b616c00 120 }
IKobayashi 0:c88c3b616c00 121
IKobayashi 0:c88c3b616c00 122
IKobayashi 0:c88c3b616c00 123 /** \brief Get Process Stack Pointer
IKobayashi 0:c88c3b616c00 124
IKobayashi 0:c88c3b616c00 125 This function returns the current value of the Process Stack Pointer (PSP).
IKobayashi 0:c88c3b616c00 126
IKobayashi 0:c88c3b616c00 127 \return PSP Register value
IKobayashi 0:c88c3b616c00 128 */
IKobayashi 0:c88c3b616c00 129 __STATIC_INLINE uint32_t __get_PSP(void)
IKobayashi 0:c88c3b616c00 130 {
IKobayashi 0:c88c3b616c00 131 register uint32_t __regProcessStackPointer __ASM("psp");
IKobayashi 0:c88c3b616c00 132 return(__regProcessStackPointer);
IKobayashi 0:c88c3b616c00 133 }
IKobayashi 0:c88c3b616c00 134
IKobayashi 0:c88c3b616c00 135
IKobayashi 0:c88c3b616c00 136 /** \brief Set Process Stack Pointer
IKobayashi 0:c88c3b616c00 137
IKobayashi 0:c88c3b616c00 138 This function assigns the given value to the Process Stack Pointer (PSP).
IKobayashi 0:c88c3b616c00 139
IKobayashi 0:c88c3b616c00 140 \param [in] topOfProcStack Process Stack Pointer value to set
IKobayashi 0:c88c3b616c00 141 */
IKobayashi 0:c88c3b616c00 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
IKobayashi 0:c88c3b616c00 143 {
IKobayashi 0:c88c3b616c00 144 register uint32_t __regProcessStackPointer __ASM("psp");
IKobayashi 0:c88c3b616c00 145 __regProcessStackPointer = topOfProcStack;
IKobayashi 0:c88c3b616c00 146 }
IKobayashi 0:c88c3b616c00 147
IKobayashi 0:c88c3b616c00 148
IKobayashi 0:c88c3b616c00 149 /** \brief Get Main Stack Pointer
IKobayashi 0:c88c3b616c00 150
IKobayashi 0:c88c3b616c00 151 This function returns the current value of the Main Stack Pointer (MSP).
IKobayashi 0:c88c3b616c00 152
IKobayashi 0:c88c3b616c00 153 \return MSP Register value
IKobayashi 0:c88c3b616c00 154 */
IKobayashi 0:c88c3b616c00 155 __STATIC_INLINE uint32_t __get_MSP(void)
IKobayashi 0:c88c3b616c00 156 {
IKobayashi 0:c88c3b616c00 157 register uint32_t __regMainStackPointer __ASM("msp");
IKobayashi 0:c88c3b616c00 158 return(__regMainStackPointer);
IKobayashi 0:c88c3b616c00 159 }
IKobayashi 0:c88c3b616c00 160
IKobayashi 0:c88c3b616c00 161
IKobayashi 0:c88c3b616c00 162 /** \brief Set Main Stack Pointer
IKobayashi 0:c88c3b616c00 163
IKobayashi 0:c88c3b616c00 164 This function assigns the given value to the Main Stack Pointer (MSP).
IKobayashi 0:c88c3b616c00 165
IKobayashi 0:c88c3b616c00 166 \param [in] topOfMainStack Main Stack Pointer value to set
IKobayashi 0:c88c3b616c00 167 */
IKobayashi 0:c88c3b616c00 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
IKobayashi 0:c88c3b616c00 169 {
IKobayashi 0:c88c3b616c00 170 register uint32_t __regMainStackPointer __ASM("msp");
IKobayashi 0:c88c3b616c00 171 __regMainStackPointer = topOfMainStack;
IKobayashi 0:c88c3b616c00 172 }
IKobayashi 0:c88c3b616c00 173
IKobayashi 0:c88c3b616c00 174
IKobayashi 0:c88c3b616c00 175 /** \brief Get Priority Mask
IKobayashi 0:c88c3b616c00 176
IKobayashi 0:c88c3b616c00 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
IKobayashi 0:c88c3b616c00 178
IKobayashi 0:c88c3b616c00 179 \return Priority Mask value
IKobayashi 0:c88c3b616c00 180 */
IKobayashi 0:c88c3b616c00 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
IKobayashi 0:c88c3b616c00 182 {
IKobayashi 0:c88c3b616c00 183 register uint32_t __regPriMask __ASM("primask");
IKobayashi 0:c88c3b616c00 184 return(__regPriMask);
IKobayashi 0:c88c3b616c00 185 }
IKobayashi 0:c88c3b616c00 186
IKobayashi 0:c88c3b616c00 187
IKobayashi 0:c88c3b616c00 188 /** \brief Set Priority Mask
IKobayashi 0:c88c3b616c00 189
IKobayashi 0:c88c3b616c00 190 This function assigns the given value to the Priority Mask Register.
IKobayashi 0:c88c3b616c00 191
IKobayashi 0:c88c3b616c00 192 \param [in] priMask Priority Mask
IKobayashi 0:c88c3b616c00 193 */
IKobayashi 0:c88c3b616c00 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
IKobayashi 0:c88c3b616c00 195 {
IKobayashi 0:c88c3b616c00 196 register uint32_t __regPriMask __ASM("primask");
IKobayashi 0:c88c3b616c00 197 __regPriMask = (priMask);
IKobayashi 0:c88c3b616c00 198 }
IKobayashi 0:c88c3b616c00 199
IKobayashi 0:c88c3b616c00 200
IKobayashi 0:c88c3b616c00 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
IKobayashi 0:c88c3b616c00 202
IKobayashi 0:c88c3b616c00 203 /** \brief Enable FIQ
IKobayashi 0:c88c3b616c00 204
IKobayashi 0:c88c3b616c00 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
IKobayashi 0:c88c3b616c00 206 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 207 */
IKobayashi 0:c88c3b616c00 208 #define __enable_fault_irq __enable_fiq
IKobayashi 0:c88c3b616c00 209
IKobayashi 0:c88c3b616c00 210
IKobayashi 0:c88c3b616c00 211 /** \brief Disable FIQ
IKobayashi 0:c88c3b616c00 212
IKobayashi 0:c88c3b616c00 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
IKobayashi 0:c88c3b616c00 214 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 215 */
IKobayashi 0:c88c3b616c00 216 #define __disable_fault_irq __disable_fiq
IKobayashi 0:c88c3b616c00 217
IKobayashi 0:c88c3b616c00 218
IKobayashi 0:c88c3b616c00 219 /** \brief Get Base Priority
IKobayashi 0:c88c3b616c00 220
IKobayashi 0:c88c3b616c00 221 This function returns the current value of the Base Priority register.
IKobayashi 0:c88c3b616c00 222
IKobayashi 0:c88c3b616c00 223 \return Base Priority register value
IKobayashi 0:c88c3b616c00 224 */
IKobayashi 0:c88c3b616c00 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
IKobayashi 0:c88c3b616c00 226 {
IKobayashi 0:c88c3b616c00 227 register uint32_t __regBasePri __ASM("basepri");
IKobayashi 0:c88c3b616c00 228 return(__regBasePri);
IKobayashi 0:c88c3b616c00 229 }
IKobayashi 0:c88c3b616c00 230
IKobayashi 0:c88c3b616c00 231
IKobayashi 0:c88c3b616c00 232 /** \brief Set Base Priority
IKobayashi 0:c88c3b616c00 233
IKobayashi 0:c88c3b616c00 234 This function assigns the given value to the Base Priority register.
IKobayashi 0:c88c3b616c00 235
IKobayashi 0:c88c3b616c00 236 \param [in] basePri Base Priority value to set
IKobayashi 0:c88c3b616c00 237 */
IKobayashi 0:c88c3b616c00 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
IKobayashi 0:c88c3b616c00 239 {
IKobayashi 0:c88c3b616c00 240 register uint32_t __regBasePri __ASM("basepri");
IKobayashi 0:c88c3b616c00 241 __regBasePri = (basePri & 0xff);
IKobayashi 0:c88c3b616c00 242 }
IKobayashi 0:c88c3b616c00 243
IKobayashi 0:c88c3b616c00 244
IKobayashi 0:c88c3b616c00 245 /** \brief Set Base Priority with condition
IKobayashi 0:c88c3b616c00 246
IKobayashi 0:c88c3b616c00 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
IKobayashi 0:c88c3b616c00 248 or the new value increases the BASEPRI priority level.
IKobayashi 0:c88c3b616c00 249
IKobayashi 0:c88c3b616c00 250 \param [in] basePri Base Priority value to set
IKobayashi 0:c88c3b616c00 251 */
IKobayashi 0:c88c3b616c00 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
IKobayashi 0:c88c3b616c00 253 {
IKobayashi 0:c88c3b616c00 254 register uint32_t __regBasePriMax __ASM("basepri_max");
IKobayashi 0:c88c3b616c00 255 __regBasePriMax = (basePri & 0xff);
IKobayashi 0:c88c3b616c00 256 }
IKobayashi 0:c88c3b616c00 257
IKobayashi 0:c88c3b616c00 258
IKobayashi 0:c88c3b616c00 259 /** \brief Get Fault Mask
IKobayashi 0:c88c3b616c00 260
IKobayashi 0:c88c3b616c00 261 This function returns the current value of the Fault Mask register.
IKobayashi 0:c88c3b616c00 262
IKobayashi 0:c88c3b616c00 263 \return Fault Mask register value
IKobayashi 0:c88c3b616c00 264 */
IKobayashi 0:c88c3b616c00 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
IKobayashi 0:c88c3b616c00 266 {
IKobayashi 0:c88c3b616c00 267 register uint32_t __regFaultMask __ASM("faultmask");
IKobayashi 0:c88c3b616c00 268 return(__regFaultMask);
IKobayashi 0:c88c3b616c00 269 }
IKobayashi 0:c88c3b616c00 270
IKobayashi 0:c88c3b616c00 271
IKobayashi 0:c88c3b616c00 272 /** \brief Set Fault Mask
IKobayashi 0:c88c3b616c00 273
IKobayashi 0:c88c3b616c00 274 This function assigns the given value to the Fault Mask register.
IKobayashi 0:c88c3b616c00 275
IKobayashi 0:c88c3b616c00 276 \param [in] faultMask Fault Mask value to set
IKobayashi 0:c88c3b616c00 277 */
IKobayashi 0:c88c3b616c00 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
IKobayashi 0:c88c3b616c00 279 {
IKobayashi 0:c88c3b616c00 280 register uint32_t __regFaultMask __ASM("faultmask");
IKobayashi 0:c88c3b616c00 281 __regFaultMask = (faultMask & (uint32_t)1);
IKobayashi 0:c88c3b616c00 282 }
IKobayashi 0:c88c3b616c00 283
IKobayashi 0:c88c3b616c00 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
IKobayashi 0:c88c3b616c00 285
IKobayashi 0:c88c3b616c00 286
IKobayashi 0:c88c3b616c00 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
IKobayashi 0:c88c3b616c00 288
IKobayashi 0:c88c3b616c00 289 /** \brief Get FPSCR
IKobayashi 0:c88c3b616c00 290
IKobayashi 0:c88c3b616c00 291 This function returns the current value of the Floating Point Status/Control register.
IKobayashi 0:c88c3b616c00 292
IKobayashi 0:c88c3b616c00 293 \return Floating Point Status/Control register value
IKobayashi 0:c88c3b616c00 294 */
IKobayashi 0:c88c3b616c00 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
IKobayashi 0:c88c3b616c00 296 {
IKobayashi 0:c88c3b616c00 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
IKobayashi 0:c88c3b616c00 298 register uint32_t __regfpscr __ASM("fpscr");
IKobayashi 0:c88c3b616c00 299 return(__regfpscr);
IKobayashi 0:c88c3b616c00 300 #else
IKobayashi 0:c88c3b616c00 301 return(0);
IKobayashi 0:c88c3b616c00 302 #endif
IKobayashi 0:c88c3b616c00 303 }
IKobayashi 0:c88c3b616c00 304
IKobayashi 0:c88c3b616c00 305
IKobayashi 0:c88c3b616c00 306 /** \brief Set FPSCR
IKobayashi 0:c88c3b616c00 307
IKobayashi 0:c88c3b616c00 308 This function assigns the given value to the Floating Point Status/Control register.
IKobayashi 0:c88c3b616c00 309
IKobayashi 0:c88c3b616c00 310 \param [in] fpscr Floating Point Status/Control value to set
IKobayashi 0:c88c3b616c00 311 */
IKobayashi 0:c88c3b616c00 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
IKobayashi 0:c88c3b616c00 313 {
IKobayashi 0:c88c3b616c00 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
IKobayashi 0:c88c3b616c00 315 register uint32_t __regfpscr __ASM("fpscr");
IKobayashi 0:c88c3b616c00 316 __regfpscr = (fpscr);
IKobayashi 0:c88c3b616c00 317 #endif
IKobayashi 0:c88c3b616c00 318 }
IKobayashi 0:c88c3b616c00 319
IKobayashi 0:c88c3b616c00 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
IKobayashi 0:c88c3b616c00 321
IKobayashi 0:c88c3b616c00 322
IKobayashi 0:c88c3b616c00 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
IKobayashi 0:c88c3b616c00 324 /* GNU gcc specific functions */
IKobayashi 0:c88c3b616c00 325
IKobayashi 0:c88c3b616c00 326 /** \brief Enable IRQ Interrupts
IKobayashi 0:c88c3b616c00 327
IKobayashi 0:c88c3b616c00 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
IKobayashi 0:c88c3b616c00 329 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 330 */
IKobayashi 0:c88c3b616c00 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
IKobayashi 0:c88c3b616c00 332 {
IKobayashi 0:c88c3b616c00 333 __ASM volatile ("cpsie i" : : : "memory");
IKobayashi 0:c88c3b616c00 334 }
IKobayashi 0:c88c3b616c00 335
IKobayashi 0:c88c3b616c00 336
IKobayashi 0:c88c3b616c00 337 /** \brief Disable IRQ Interrupts
IKobayashi 0:c88c3b616c00 338
IKobayashi 0:c88c3b616c00 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
IKobayashi 0:c88c3b616c00 340 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 341 */
IKobayashi 0:c88c3b616c00 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
IKobayashi 0:c88c3b616c00 343 {
IKobayashi 0:c88c3b616c00 344 __ASM volatile ("cpsid i" : : : "memory");
IKobayashi 0:c88c3b616c00 345 }
IKobayashi 0:c88c3b616c00 346
IKobayashi 0:c88c3b616c00 347
IKobayashi 0:c88c3b616c00 348 /** \brief Get Control Register
IKobayashi 0:c88c3b616c00 349
IKobayashi 0:c88c3b616c00 350 This function returns the content of the Control Register.
IKobayashi 0:c88c3b616c00 351
IKobayashi 0:c88c3b616c00 352 \return Control Register value
IKobayashi 0:c88c3b616c00 353 */
IKobayashi 0:c88c3b616c00 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
IKobayashi 0:c88c3b616c00 355 {
IKobayashi 0:c88c3b616c00 356 uint32_t result;
IKobayashi 0:c88c3b616c00 357
IKobayashi 0:c88c3b616c00 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
IKobayashi 0:c88c3b616c00 359 return(result);
IKobayashi 0:c88c3b616c00 360 }
IKobayashi 0:c88c3b616c00 361
IKobayashi 0:c88c3b616c00 362
IKobayashi 0:c88c3b616c00 363 /** \brief Set Control Register
IKobayashi 0:c88c3b616c00 364
IKobayashi 0:c88c3b616c00 365 This function writes the given value to the Control Register.
IKobayashi 0:c88c3b616c00 366
IKobayashi 0:c88c3b616c00 367 \param [in] control Control Register value to set
IKobayashi 0:c88c3b616c00 368 */
IKobayashi 0:c88c3b616c00 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
IKobayashi 0:c88c3b616c00 370 {
IKobayashi 0:c88c3b616c00 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
IKobayashi 0:c88c3b616c00 372 }
IKobayashi 0:c88c3b616c00 373
IKobayashi 0:c88c3b616c00 374
IKobayashi 0:c88c3b616c00 375 /** \brief Get IPSR Register
IKobayashi 0:c88c3b616c00 376
IKobayashi 0:c88c3b616c00 377 This function returns the content of the IPSR Register.
IKobayashi 0:c88c3b616c00 378
IKobayashi 0:c88c3b616c00 379 \return IPSR Register value
IKobayashi 0:c88c3b616c00 380 */
IKobayashi 0:c88c3b616c00 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
IKobayashi 0:c88c3b616c00 382 {
IKobayashi 0:c88c3b616c00 383 uint32_t result;
IKobayashi 0:c88c3b616c00 384
IKobayashi 0:c88c3b616c00 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
IKobayashi 0:c88c3b616c00 386 return(result);
IKobayashi 0:c88c3b616c00 387 }
IKobayashi 0:c88c3b616c00 388
IKobayashi 0:c88c3b616c00 389
IKobayashi 0:c88c3b616c00 390 /** \brief Get APSR Register
IKobayashi 0:c88c3b616c00 391
IKobayashi 0:c88c3b616c00 392 This function returns the content of the APSR Register.
IKobayashi 0:c88c3b616c00 393
IKobayashi 0:c88c3b616c00 394 \return APSR Register value
IKobayashi 0:c88c3b616c00 395 */
IKobayashi 0:c88c3b616c00 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
IKobayashi 0:c88c3b616c00 397 {
IKobayashi 0:c88c3b616c00 398 uint32_t result;
IKobayashi 0:c88c3b616c00 399
IKobayashi 0:c88c3b616c00 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
IKobayashi 0:c88c3b616c00 401 return(result);
IKobayashi 0:c88c3b616c00 402 }
IKobayashi 0:c88c3b616c00 403
IKobayashi 0:c88c3b616c00 404
IKobayashi 0:c88c3b616c00 405 /** \brief Get xPSR Register
IKobayashi 0:c88c3b616c00 406
IKobayashi 0:c88c3b616c00 407 This function returns the content of the xPSR Register.
IKobayashi 0:c88c3b616c00 408
IKobayashi 0:c88c3b616c00 409 \return xPSR Register value
IKobayashi 0:c88c3b616c00 410 */
IKobayashi 0:c88c3b616c00 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
IKobayashi 0:c88c3b616c00 412 {
IKobayashi 0:c88c3b616c00 413 uint32_t result;
IKobayashi 0:c88c3b616c00 414
IKobayashi 0:c88c3b616c00 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
IKobayashi 0:c88c3b616c00 416 return(result);
IKobayashi 0:c88c3b616c00 417 }
IKobayashi 0:c88c3b616c00 418
IKobayashi 0:c88c3b616c00 419
IKobayashi 0:c88c3b616c00 420 /** \brief Get Process Stack Pointer
IKobayashi 0:c88c3b616c00 421
IKobayashi 0:c88c3b616c00 422 This function returns the current value of the Process Stack Pointer (PSP).
IKobayashi 0:c88c3b616c00 423
IKobayashi 0:c88c3b616c00 424 \return PSP Register value
IKobayashi 0:c88c3b616c00 425 */
IKobayashi 0:c88c3b616c00 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
IKobayashi 0:c88c3b616c00 427 {
IKobayashi 0:c88c3b616c00 428 register uint32_t result;
IKobayashi 0:c88c3b616c00 429
IKobayashi 0:c88c3b616c00 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
IKobayashi 0:c88c3b616c00 431 return(result);
IKobayashi 0:c88c3b616c00 432 }
IKobayashi 0:c88c3b616c00 433
IKobayashi 0:c88c3b616c00 434
IKobayashi 0:c88c3b616c00 435 /** \brief Set Process Stack Pointer
IKobayashi 0:c88c3b616c00 436
IKobayashi 0:c88c3b616c00 437 This function assigns the given value to the Process Stack Pointer (PSP).
IKobayashi 0:c88c3b616c00 438
IKobayashi 0:c88c3b616c00 439 \param [in] topOfProcStack Process Stack Pointer value to set
IKobayashi 0:c88c3b616c00 440 */
IKobayashi 0:c88c3b616c00 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
IKobayashi 0:c88c3b616c00 442 {
IKobayashi 0:c88c3b616c00 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
IKobayashi 0:c88c3b616c00 444 }
IKobayashi 0:c88c3b616c00 445
IKobayashi 0:c88c3b616c00 446
IKobayashi 0:c88c3b616c00 447 /** \brief Get Main Stack Pointer
IKobayashi 0:c88c3b616c00 448
IKobayashi 0:c88c3b616c00 449 This function returns the current value of the Main Stack Pointer (MSP).
IKobayashi 0:c88c3b616c00 450
IKobayashi 0:c88c3b616c00 451 \return MSP Register value
IKobayashi 0:c88c3b616c00 452 */
IKobayashi 0:c88c3b616c00 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
IKobayashi 0:c88c3b616c00 454 {
IKobayashi 0:c88c3b616c00 455 register uint32_t result;
IKobayashi 0:c88c3b616c00 456
IKobayashi 0:c88c3b616c00 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
IKobayashi 0:c88c3b616c00 458 return(result);
IKobayashi 0:c88c3b616c00 459 }
IKobayashi 0:c88c3b616c00 460
IKobayashi 0:c88c3b616c00 461
IKobayashi 0:c88c3b616c00 462 /** \brief Set Main Stack Pointer
IKobayashi 0:c88c3b616c00 463
IKobayashi 0:c88c3b616c00 464 This function assigns the given value to the Main Stack Pointer (MSP).
IKobayashi 0:c88c3b616c00 465
IKobayashi 0:c88c3b616c00 466 \param [in] topOfMainStack Main Stack Pointer value to set
IKobayashi 0:c88c3b616c00 467 */
IKobayashi 0:c88c3b616c00 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
IKobayashi 0:c88c3b616c00 469 {
IKobayashi 0:c88c3b616c00 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
IKobayashi 0:c88c3b616c00 471 }
IKobayashi 0:c88c3b616c00 472
IKobayashi 0:c88c3b616c00 473
IKobayashi 0:c88c3b616c00 474 /** \brief Get Priority Mask
IKobayashi 0:c88c3b616c00 475
IKobayashi 0:c88c3b616c00 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
IKobayashi 0:c88c3b616c00 477
IKobayashi 0:c88c3b616c00 478 \return Priority Mask value
IKobayashi 0:c88c3b616c00 479 */
IKobayashi 0:c88c3b616c00 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
IKobayashi 0:c88c3b616c00 481 {
IKobayashi 0:c88c3b616c00 482 uint32_t result;
IKobayashi 0:c88c3b616c00 483
IKobayashi 0:c88c3b616c00 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
IKobayashi 0:c88c3b616c00 485 return(result);
IKobayashi 0:c88c3b616c00 486 }
IKobayashi 0:c88c3b616c00 487
IKobayashi 0:c88c3b616c00 488
IKobayashi 0:c88c3b616c00 489 /** \brief Set Priority Mask
IKobayashi 0:c88c3b616c00 490
IKobayashi 0:c88c3b616c00 491 This function assigns the given value to the Priority Mask Register.
IKobayashi 0:c88c3b616c00 492
IKobayashi 0:c88c3b616c00 493 \param [in] priMask Priority Mask
IKobayashi 0:c88c3b616c00 494 */
IKobayashi 0:c88c3b616c00 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
IKobayashi 0:c88c3b616c00 496 {
IKobayashi 0:c88c3b616c00 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
IKobayashi 0:c88c3b616c00 498 }
IKobayashi 0:c88c3b616c00 499
IKobayashi 0:c88c3b616c00 500
IKobayashi 0:c88c3b616c00 501 #if (__CORTEX_M >= 0x03)
IKobayashi 0:c88c3b616c00 502
IKobayashi 0:c88c3b616c00 503 /** \brief Enable FIQ
IKobayashi 0:c88c3b616c00 504
IKobayashi 0:c88c3b616c00 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
IKobayashi 0:c88c3b616c00 506 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 507 */
IKobayashi 0:c88c3b616c00 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
IKobayashi 0:c88c3b616c00 509 {
IKobayashi 0:c88c3b616c00 510 __ASM volatile ("cpsie f" : : : "memory");
IKobayashi 0:c88c3b616c00 511 }
IKobayashi 0:c88c3b616c00 512
IKobayashi 0:c88c3b616c00 513
IKobayashi 0:c88c3b616c00 514 /** \brief Disable FIQ
IKobayashi 0:c88c3b616c00 515
IKobayashi 0:c88c3b616c00 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
IKobayashi 0:c88c3b616c00 517 Can only be executed in Privileged modes.
IKobayashi 0:c88c3b616c00 518 */
IKobayashi 0:c88c3b616c00 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
IKobayashi 0:c88c3b616c00 520 {
IKobayashi 0:c88c3b616c00 521 __ASM volatile ("cpsid f" : : : "memory");
IKobayashi 0:c88c3b616c00 522 }
IKobayashi 0:c88c3b616c00 523
IKobayashi 0:c88c3b616c00 524
IKobayashi 0:c88c3b616c00 525 /** \brief Get Base Priority
IKobayashi 0:c88c3b616c00 526
IKobayashi 0:c88c3b616c00 527 This function returns the current value of the Base Priority register.
IKobayashi 0:c88c3b616c00 528
IKobayashi 0:c88c3b616c00 529 \return Base Priority register value
IKobayashi 0:c88c3b616c00 530 */
IKobayashi 0:c88c3b616c00 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
IKobayashi 0:c88c3b616c00 532 {
IKobayashi 0:c88c3b616c00 533 uint32_t result;
IKobayashi 0:c88c3b616c00 534
IKobayashi 0:c88c3b616c00 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
IKobayashi 0:c88c3b616c00 536 return(result);
IKobayashi 0:c88c3b616c00 537 }
IKobayashi 0:c88c3b616c00 538
IKobayashi 0:c88c3b616c00 539
IKobayashi 0:c88c3b616c00 540 /** \brief Set Base Priority
IKobayashi 0:c88c3b616c00 541
IKobayashi 0:c88c3b616c00 542 This function assigns the given value to the Base Priority register.
IKobayashi 0:c88c3b616c00 543
IKobayashi 0:c88c3b616c00 544 \param [in] basePri Base Priority value to set
IKobayashi 0:c88c3b616c00 545 */
IKobayashi 0:c88c3b616c00 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
IKobayashi 0:c88c3b616c00 547 {
IKobayashi 0:c88c3b616c00 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
IKobayashi 0:c88c3b616c00 549 }
IKobayashi 0:c88c3b616c00 550
IKobayashi 0:c88c3b616c00 551
IKobayashi 0:c88c3b616c00 552 /** \brief Set Base Priority with condition
IKobayashi 0:c88c3b616c00 553
IKobayashi 0:c88c3b616c00 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
IKobayashi 0:c88c3b616c00 555 or the new value increases the BASEPRI priority level.
IKobayashi 0:c88c3b616c00 556
IKobayashi 0:c88c3b616c00 557 \param [in] basePri Base Priority value to set
IKobayashi 0:c88c3b616c00 558 */
IKobayashi 0:c88c3b616c00 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
IKobayashi 0:c88c3b616c00 560 {
IKobayashi 0:c88c3b616c00 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
IKobayashi 0:c88c3b616c00 562 }
IKobayashi 0:c88c3b616c00 563
IKobayashi 0:c88c3b616c00 564
IKobayashi 0:c88c3b616c00 565 /** \brief Get Fault Mask
IKobayashi 0:c88c3b616c00 566
IKobayashi 0:c88c3b616c00 567 This function returns the current value of the Fault Mask register.
IKobayashi 0:c88c3b616c00 568
IKobayashi 0:c88c3b616c00 569 \return Fault Mask register value
IKobayashi 0:c88c3b616c00 570 */
IKobayashi 0:c88c3b616c00 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
IKobayashi 0:c88c3b616c00 572 {
IKobayashi 0:c88c3b616c00 573 uint32_t result;
IKobayashi 0:c88c3b616c00 574
IKobayashi 0:c88c3b616c00 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
IKobayashi 0:c88c3b616c00 576 return(result);
IKobayashi 0:c88c3b616c00 577 }
IKobayashi 0:c88c3b616c00 578
IKobayashi 0:c88c3b616c00 579
IKobayashi 0:c88c3b616c00 580 /** \brief Set Fault Mask
IKobayashi 0:c88c3b616c00 581
IKobayashi 0:c88c3b616c00 582 This function assigns the given value to the Fault Mask register.
IKobayashi 0:c88c3b616c00 583
IKobayashi 0:c88c3b616c00 584 \param [in] faultMask Fault Mask value to set
IKobayashi 0:c88c3b616c00 585 */
IKobayashi 0:c88c3b616c00 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
IKobayashi 0:c88c3b616c00 587 {
IKobayashi 0:c88c3b616c00 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
IKobayashi 0:c88c3b616c00 589 }
IKobayashi 0:c88c3b616c00 590
IKobayashi 0:c88c3b616c00 591 #endif /* (__CORTEX_M >= 0x03) */
IKobayashi 0:c88c3b616c00 592
IKobayashi 0:c88c3b616c00 593
IKobayashi 0:c88c3b616c00 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
IKobayashi 0:c88c3b616c00 595
IKobayashi 0:c88c3b616c00 596 /** \brief Get FPSCR
IKobayashi 0:c88c3b616c00 597
IKobayashi 0:c88c3b616c00 598 This function returns the current value of the Floating Point Status/Control register.
IKobayashi 0:c88c3b616c00 599
IKobayashi 0:c88c3b616c00 600 \return Floating Point Status/Control register value
IKobayashi 0:c88c3b616c00 601 */
IKobayashi 0:c88c3b616c00 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
IKobayashi 0:c88c3b616c00 603 {
IKobayashi 0:c88c3b616c00 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
IKobayashi 0:c88c3b616c00 605 uint32_t result;
IKobayashi 0:c88c3b616c00 606
IKobayashi 0:c88c3b616c00 607 /* Empty asm statement works as a scheduling barrier */
IKobayashi 0:c88c3b616c00 608 __ASM volatile ("");
IKobayashi 0:c88c3b616c00 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
IKobayashi 0:c88c3b616c00 610 __ASM volatile ("");
IKobayashi 0:c88c3b616c00 611 return(result);
IKobayashi 0:c88c3b616c00 612 #else
IKobayashi 0:c88c3b616c00 613 return(0);
IKobayashi 0:c88c3b616c00 614 #endif
IKobayashi 0:c88c3b616c00 615 }
IKobayashi 0:c88c3b616c00 616
IKobayashi 0:c88c3b616c00 617
IKobayashi 0:c88c3b616c00 618 /** \brief Set FPSCR
IKobayashi 0:c88c3b616c00 619
IKobayashi 0:c88c3b616c00 620 This function assigns the given value to the Floating Point Status/Control register.
IKobayashi 0:c88c3b616c00 621
IKobayashi 0:c88c3b616c00 622 \param [in] fpscr Floating Point Status/Control value to set
IKobayashi 0:c88c3b616c00 623 */
IKobayashi 0:c88c3b616c00 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
IKobayashi 0:c88c3b616c00 625 {
IKobayashi 0:c88c3b616c00 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
IKobayashi 0:c88c3b616c00 627 /* Empty asm statement works as a scheduling barrier */
IKobayashi 0:c88c3b616c00 628 __ASM volatile ("");
IKobayashi 0:c88c3b616c00 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
IKobayashi 0:c88c3b616c00 630 __ASM volatile ("");
IKobayashi 0:c88c3b616c00 631 #endif
IKobayashi 0:c88c3b616c00 632 }
IKobayashi 0:c88c3b616c00 633
IKobayashi 0:c88c3b616c00 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
IKobayashi 0:c88c3b616c00 635
IKobayashi 0:c88c3b616c00 636
IKobayashi 0:c88c3b616c00 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 638 /* IAR iccarm specific functions */
IKobayashi 0:c88c3b616c00 639 #include <cmsis_iar.h>
IKobayashi 0:c88c3b616c00 640
IKobayashi 0:c88c3b616c00 641
IKobayashi 0:c88c3b616c00 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
IKobayashi 0:c88c3b616c00 643 /* TI CCS specific functions */
IKobayashi 0:c88c3b616c00 644 #include <cmsis_ccs.h>
IKobayashi 0:c88c3b616c00 645
IKobayashi 0:c88c3b616c00 646
IKobayashi 0:c88c3b616c00 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
IKobayashi 0:c88c3b616c00 648 /* TASKING carm specific functions */
IKobayashi 0:c88c3b616c00 649 /*
IKobayashi 0:c88c3b616c00 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
IKobayashi 0:c88c3b616c00 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
IKobayashi 0:c88c3b616c00 652 * Including the CMSIS ones.
IKobayashi 0:c88c3b616c00 653 */
IKobayashi 0:c88c3b616c00 654
IKobayashi 0:c88c3b616c00 655
IKobayashi 0:c88c3b616c00 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
IKobayashi 0:c88c3b616c00 657 /* Cosmic specific functions */
IKobayashi 0:c88c3b616c00 658 #include <cmsis_csm.h>
IKobayashi 0:c88c3b616c00 659
IKobayashi 0:c88c3b616c00 660 #endif
IKobayashi 0:c88c3b616c00 661
IKobayashi 0:c88c3b616c00 662 /*@} end of CMSIS_Core_RegAccFunctions */
IKobayashi 0:c88c3b616c00 663
IKobayashi 0:c88c3b616c00 664 #endif /* __CORE_CMFUNC_H */