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mbed/TARGET_LPC1768/core_cm7.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file core_cm7.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
IKobayashi 0:c88c3b616c00 4 * @version V4.10
IKobayashi 0:c88c3b616c00 5 * @date 18. March 2015
IKobayashi 0:c88c3b616c00 6 *
IKobayashi 0:c88c3b616c00 7 * @note
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 ******************************************************************************/
IKobayashi 0:c88c3b616c00 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
IKobayashi 0:c88c3b616c00 11
IKobayashi 0:c88c3b616c00 12 All rights reserved.
IKobayashi 0:c88c3b616c00 13 Redistribution and use in source and binary forms, with or without
IKobayashi 0:c88c3b616c00 14 modification, are permitted provided that the following conditions are met:
IKobayashi 0:c88c3b616c00 15 - Redistributions of source code must retain the above copyright
IKobayashi 0:c88c3b616c00 16 notice, this list of conditions and the following disclaimer.
IKobayashi 0:c88c3b616c00 17 - Redistributions in binary form must reproduce the above copyright
IKobayashi 0:c88c3b616c00 18 notice, this list of conditions and the following disclaimer in the
IKobayashi 0:c88c3b616c00 19 documentation and/or other materials provided with the distribution.
IKobayashi 0:c88c3b616c00 20 - Neither the name of ARM nor the names of its contributors may be used
IKobayashi 0:c88c3b616c00 21 to endorse or promote products derived from this software without
IKobayashi 0:c88c3b616c00 22 specific prior written permission.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi 0:c88c3b616c00 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi 0:c88c3b616c00 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi 0:c88c3b616c00 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi 0:c88c3b616c00 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi 0:c88c3b616c00 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi 0:c88c3b616c00 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi 0:c88c3b616c00 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi 0:c88c3b616c00 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi 0:c88c3b616c00 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi 0:c88c3b616c00 34 POSSIBILITY OF SUCH DAMAGE.
IKobayashi 0:c88c3b616c00 35 ---------------------------------------------------------------------------*/
IKobayashi 0:c88c3b616c00 36
IKobayashi 0:c88c3b616c00 37
IKobayashi 0:c88c3b616c00 38 #if defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 39 #pragma system_include /* treat file as system include file for MISRA check */
IKobayashi 0:c88c3b616c00 40 #endif
IKobayashi 0:c88c3b616c00 41
IKobayashi 0:c88c3b616c00 42 #ifndef __CORE_CM7_H_GENERIC
IKobayashi 0:c88c3b616c00 43 #define __CORE_CM7_H_GENERIC
IKobayashi 0:c88c3b616c00 44
IKobayashi 0:c88c3b616c00 45 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 46 extern "C" {
IKobayashi 0:c88c3b616c00 47 #endif
IKobayashi 0:c88c3b616c00 48
IKobayashi 0:c88c3b616c00 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
IKobayashi 0:c88c3b616c00 50 CMSIS violates the following MISRA-C:2004 rules:
IKobayashi 0:c88c3b616c00 51
IKobayashi 0:c88c3b616c00 52 \li Required Rule 8.5, object/function definition in header file.<br>
IKobayashi 0:c88c3b616c00 53 Function definitions in header files are used to allow 'inlining'.
IKobayashi 0:c88c3b616c00 54
IKobayashi 0:c88c3b616c00 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
IKobayashi 0:c88c3b616c00 56 Unions are used for effective representation of core registers.
IKobayashi 0:c88c3b616c00 57
IKobayashi 0:c88c3b616c00 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
IKobayashi 0:c88c3b616c00 59 Function-like macros are used to allow more efficient code.
IKobayashi 0:c88c3b616c00 60 */
IKobayashi 0:c88c3b616c00 61
IKobayashi 0:c88c3b616c00 62
IKobayashi 0:c88c3b616c00 63 /*******************************************************************************
IKobayashi 0:c88c3b616c00 64 * CMSIS definitions
IKobayashi 0:c88c3b616c00 65 ******************************************************************************/
IKobayashi 0:c88c3b616c00 66 /** \ingroup Cortex_M7
IKobayashi 0:c88c3b616c00 67 @{
IKobayashi 0:c88c3b616c00 68 */
IKobayashi 0:c88c3b616c00 69
IKobayashi 0:c88c3b616c00 70 /* CMSIS CM7 definitions */
IKobayashi 0:c88c3b616c00 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
IKobayashi 0:c88c3b616c00 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
IKobayashi 0:c88c3b616c00 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
IKobayashi 0:c88c3b616c00 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
IKobayashi 0:c88c3b616c00 75
IKobayashi 0:c88c3b616c00 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
IKobayashi 0:c88c3b616c00 77
IKobayashi 0:c88c3b616c00 78
IKobayashi 0:c88c3b616c00 79 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
IKobayashi 0:c88c3b616c00 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
IKobayashi 0:c88c3b616c00 82 #define __STATIC_INLINE static __inline
IKobayashi 0:c88c3b616c00 83
IKobayashi 0:c88c3b616c00 84 #elif defined ( __GNUC__ )
IKobayashi 0:c88c3b616c00 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
IKobayashi 0:c88c3b616c00 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
IKobayashi 0:c88c3b616c00 87 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 88
IKobayashi 0:c88c3b616c00 89 #elif defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
IKobayashi 0:c88c3b616c00 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
IKobayashi 0:c88c3b616c00 92 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 93
IKobayashi 0:c88c3b616c00 94 #elif defined ( __TMS470__ )
IKobayashi 0:c88c3b616c00 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
IKobayashi 0:c88c3b616c00 96 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 97
IKobayashi 0:c88c3b616c00 98 #elif defined ( __TASKING__ )
IKobayashi 0:c88c3b616c00 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
IKobayashi 0:c88c3b616c00 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
IKobayashi 0:c88c3b616c00 101 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 102
IKobayashi 0:c88c3b616c00 103 #elif defined ( __CSMC__ )
IKobayashi 0:c88c3b616c00 104 #define __packed
IKobayashi 0:c88c3b616c00 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
IKobayashi 0:c88c3b616c00 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
IKobayashi 0:c88c3b616c00 107 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 108
IKobayashi 0:c88c3b616c00 109 #endif
IKobayashi 0:c88c3b616c00 110
IKobayashi 0:c88c3b616c00 111 /** __FPU_USED indicates whether an FPU is used or not.
IKobayashi 0:c88c3b616c00 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
IKobayashi 0:c88c3b616c00 113 */
IKobayashi 0:c88c3b616c00 114 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 115 #if defined __TARGET_FPU_VFP
IKobayashi 0:c88c3b616c00 116 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 117 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 118 #else
IKobayashi 0:c88c3b616c00 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 120 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 121 #endif
IKobayashi 0:c88c3b616c00 122 #else
IKobayashi 0:c88c3b616c00 123 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 124 #endif
IKobayashi 0:c88c3b616c00 125
IKobayashi 0:c88c3b616c00 126 #elif defined ( __GNUC__ )
IKobayashi 0:c88c3b616c00 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
IKobayashi 0:c88c3b616c00 128 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 129 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 130 #else
IKobayashi 0:c88c3b616c00 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 132 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 133 #endif
IKobayashi 0:c88c3b616c00 134 #else
IKobayashi 0:c88c3b616c00 135 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 136 #endif
IKobayashi 0:c88c3b616c00 137
IKobayashi 0:c88c3b616c00 138 #elif defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 139 #if defined __ARMVFP__
IKobayashi 0:c88c3b616c00 140 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 141 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 142 #else
IKobayashi 0:c88c3b616c00 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 144 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 145 #endif
IKobayashi 0:c88c3b616c00 146 #else
IKobayashi 0:c88c3b616c00 147 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 148 #endif
IKobayashi 0:c88c3b616c00 149
IKobayashi 0:c88c3b616c00 150 #elif defined ( __TMS470__ )
IKobayashi 0:c88c3b616c00 151 #if defined __TI_VFP_SUPPORT__
IKobayashi 0:c88c3b616c00 152 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 153 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 154 #else
IKobayashi 0:c88c3b616c00 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 156 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 157 #endif
IKobayashi 0:c88c3b616c00 158 #else
IKobayashi 0:c88c3b616c00 159 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 160 #endif
IKobayashi 0:c88c3b616c00 161
IKobayashi 0:c88c3b616c00 162 #elif defined ( __TASKING__ )
IKobayashi 0:c88c3b616c00 163 #if defined __FPU_VFP__
IKobayashi 0:c88c3b616c00 164 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 165 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 166 #else
IKobayashi 0:c88c3b616c00 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 168 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 169 #endif
IKobayashi 0:c88c3b616c00 170 #else
IKobayashi 0:c88c3b616c00 171 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 172 #endif
IKobayashi 0:c88c3b616c00 173
IKobayashi 0:c88c3b616c00 174 #elif defined ( __CSMC__ ) /* Cosmic */
IKobayashi 0:c88c3b616c00 175 #if ( __CSMC__ & 0x400) // FPU present for parser
IKobayashi 0:c88c3b616c00 176 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 177 #define __FPU_USED 1
IKobayashi 0:c88c3b616c00 178 #else
IKobayashi 0:c88c3b616c00 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 180 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 181 #endif
IKobayashi 0:c88c3b616c00 182 #else
IKobayashi 0:c88c3b616c00 183 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 184 #endif
IKobayashi 0:c88c3b616c00 185 #endif
IKobayashi 0:c88c3b616c00 186
IKobayashi 0:c88c3b616c00 187 #include <stdint.h> /* standard types definitions */
IKobayashi 0:c88c3b616c00 188 #include <core_cmInstr.h> /* Core Instruction Access */
IKobayashi 0:c88c3b616c00 189 #include <core_cmFunc.h> /* Core Function Access */
IKobayashi 0:c88c3b616c00 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
IKobayashi 0:c88c3b616c00 191
IKobayashi 0:c88c3b616c00 192 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 193 }
IKobayashi 0:c88c3b616c00 194 #endif
IKobayashi 0:c88c3b616c00 195
IKobayashi 0:c88c3b616c00 196 #endif /* __CORE_CM7_H_GENERIC */
IKobayashi 0:c88c3b616c00 197
IKobayashi 0:c88c3b616c00 198 #ifndef __CMSIS_GENERIC
IKobayashi 0:c88c3b616c00 199
IKobayashi 0:c88c3b616c00 200 #ifndef __CORE_CM7_H_DEPENDANT
IKobayashi 0:c88c3b616c00 201 #define __CORE_CM7_H_DEPENDANT
IKobayashi 0:c88c3b616c00 202
IKobayashi 0:c88c3b616c00 203 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 204 extern "C" {
IKobayashi 0:c88c3b616c00 205 #endif
IKobayashi 0:c88c3b616c00 206
IKobayashi 0:c88c3b616c00 207 /* check device defines and use defaults */
IKobayashi 0:c88c3b616c00 208 #if defined __CHECK_DEVICE_DEFINES
IKobayashi 0:c88c3b616c00 209 #ifndef __CM7_REV
IKobayashi 0:c88c3b616c00 210 #define __CM7_REV 0x0000
IKobayashi 0:c88c3b616c00 211 #warning "__CM7_REV not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 212 #endif
IKobayashi 0:c88c3b616c00 213
IKobayashi 0:c88c3b616c00 214 #ifndef __FPU_PRESENT
IKobayashi 0:c88c3b616c00 215 #define __FPU_PRESENT 0
IKobayashi 0:c88c3b616c00 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 217 #endif
IKobayashi 0:c88c3b616c00 218
IKobayashi 0:c88c3b616c00 219 #ifndef __MPU_PRESENT
IKobayashi 0:c88c3b616c00 220 #define __MPU_PRESENT 0
IKobayashi 0:c88c3b616c00 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 222 #endif
IKobayashi 0:c88c3b616c00 223
IKobayashi 0:c88c3b616c00 224 #ifndef __ICACHE_PRESENT
IKobayashi 0:c88c3b616c00 225 #define __ICACHE_PRESENT 0
IKobayashi 0:c88c3b616c00 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 227 #endif
IKobayashi 0:c88c3b616c00 228
IKobayashi 0:c88c3b616c00 229 #ifndef __DCACHE_PRESENT
IKobayashi 0:c88c3b616c00 230 #define __DCACHE_PRESENT 0
IKobayashi 0:c88c3b616c00 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 232 #endif
IKobayashi 0:c88c3b616c00 233
IKobayashi 0:c88c3b616c00 234 #ifndef __DTCM_PRESENT
IKobayashi 0:c88c3b616c00 235 #define __DTCM_PRESENT 0
IKobayashi 0:c88c3b616c00 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 237 #endif
IKobayashi 0:c88c3b616c00 238
IKobayashi 0:c88c3b616c00 239 #ifndef __NVIC_PRIO_BITS
IKobayashi 0:c88c3b616c00 240 #define __NVIC_PRIO_BITS 3
IKobayashi 0:c88c3b616c00 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 242 #endif
IKobayashi 0:c88c3b616c00 243
IKobayashi 0:c88c3b616c00 244 #ifndef __Vendor_SysTickConfig
IKobayashi 0:c88c3b616c00 245 #define __Vendor_SysTickConfig 0
IKobayashi 0:c88c3b616c00 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 247 #endif
IKobayashi 0:c88c3b616c00 248 #endif
IKobayashi 0:c88c3b616c00 249
IKobayashi 0:c88c3b616c00 250 /* IO definitions (access restrictions to peripheral registers) */
IKobayashi 0:c88c3b616c00 251 /**
IKobayashi 0:c88c3b616c00 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
IKobayashi 0:c88c3b616c00 253
IKobayashi 0:c88c3b616c00 254 <strong>IO Type Qualifiers</strong> are used
IKobayashi 0:c88c3b616c00 255 \li to specify the access to peripheral variables.
IKobayashi 0:c88c3b616c00 256 \li for automatic generation of peripheral register debug information.
IKobayashi 0:c88c3b616c00 257 */
IKobayashi 0:c88c3b616c00 258 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 259 #define __I volatile /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 260 #else
IKobayashi 0:c88c3b616c00 261 #define __I volatile const /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 262 #endif
IKobayashi 0:c88c3b616c00 263 #define __O volatile /*!< Defines 'write only' permissions */
IKobayashi 0:c88c3b616c00 264 #define __IO volatile /*!< Defines 'read / write' permissions */
IKobayashi 0:c88c3b616c00 265
IKobayashi 0:c88c3b616c00 266 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 267 #define __IM volatile /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 268 #else
IKobayashi 0:c88c3b616c00 269 #define __IM volatile const /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 270 #endif
IKobayashi 0:c88c3b616c00 271 #define __OM volatile /*!< Defines 'write only' permissions */
IKobayashi 0:c88c3b616c00 272 #define __IOM volatile /*!< Defines 'read / write' permissions */
IKobayashi 0:c88c3b616c00 273
IKobayashi 0:c88c3b616c00 274 /*@} end of group Cortex_M7 */
IKobayashi 0:c88c3b616c00 275
IKobayashi 0:c88c3b616c00 276
IKobayashi 0:c88c3b616c00 277
IKobayashi 0:c88c3b616c00 278 /*******************************************************************************
IKobayashi 0:c88c3b616c00 279 * Register Abstraction
IKobayashi 0:c88c3b616c00 280 Core Register contain:
IKobayashi 0:c88c3b616c00 281 - Core Register
IKobayashi 0:c88c3b616c00 282 - Core NVIC Register
IKobayashi 0:c88c3b616c00 283 - Core SCB Register
IKobayashi 0:c88c3b616c00 284 - Core SysTick Register
IKobayashi 0:c88c3b616c00 285 - Core Debug Register
IKobayashi 0:c88c3b616c00 286 - Core MPU Register
IKobayashi 0:c88c3b616c00 287 - Core FPU Register
IKobayashi 0:c88c3b616c00 288 ******************************************************************************/
IKobayashi 0:c88c3b616c00 289 /** \defgroup CMSIS_core_register Defines and Type Definitions
IKobayashi 0:c88c3b616c00 290 \brief Type definitions and defines for Cortex-M processor based devices.
IKobayashi 0:c88c3b616c00 291 */
IKobayashi 0:c88c3b616c00 292
IKobayashi 0:c88c3b616c00 293 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 294 \defgroup CMSIS_CORE Status and Control Registers
IKobayashi 0:c88c3b616c00 295 \brief Core Register type definitions.
IKobayashi 0:c88c3b616c00 296 @{
IKobayashi 0:c88c3b616c00 297 */
IKobayashi 0:c88c3b616c00 298
IKobayashi 0:c88c3b616c00 299 /** \brief Union type to access the Application Program Status Register (APSR).
IKobayashi 0:c88c3b616c00 300 */
IKobayashi 0:c88c3b616c00 301 typedef union
IKobayashi 0:c88c3b616c00 302 {
IKobayashi 0:c88c3b616c00 303 struct
IKobayashi 0:c88c3b616c00 304 {
IKobayashi 0:c88c3b616c00 305 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
IKobayashi 0:c88c3b616c00 306 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
IKobayashi 0:c88c3b616c00 307 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
IKobayashi 0:c88c3b616c00 308 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
IKobayashi 0:c88c3b616c00 309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
IKobayashi 0:c88c3b616c00 310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
IKobayashi 0:c88c3b616c00 311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
IKobayashi 0:c88c3b616c00 312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
IKobayashi 0:c88c3b616c00 313 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 314 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 315 } APSR_Type;
IKobayashi 0:c88c3b616c00 316
IKobayashi 0:c88c3b616c00 317 /* APSR Register Definitions */
IKobayashi 0:c88c3b616c00 318 #define APSR_N_Pos 31 /*!< APSR: N Position */
IKobayashi 0:c88c3b616c00 319 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
IKobayashi 0:c88c3b616c00 320
IKobayashi 0:c88c3b616c00 321 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
IKobayashi 0:c88c3b616c00 322 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
IKobayashi 0:c88c3b616c00 323
IKobayashi 0:c88c3b616c00 324 #define APSR_C_Pos 29 /*!< APSR: C Position */
IKobayashi 0:c88c3b616c00 325 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
IKobayashi 0:c88c3b616c00 326
IKobayashi 0:c88c3b616c00 327 #define APSR_V_Pos 28 /*!< APSR: V Position */
IKobayashi 0:c88c3b616c00 328 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
IKobayashi 0:c88c3b616c00 329
IKobayashi 0:c88c3b616c00 330 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
IKobayashi 0:c88c3b616c00 331 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
IKobayashi 0:c88c3b616c00 332
IKobayashi 0:c88c3b616c00 333 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
IKobayashi 0:c88c3b616c00 334 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
IKobayashi 0:c88c3b616c00 335
IKobayashi 0:c88c3b616c00 336
IKobayashi 0:c88c3b616c00 337 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
IKobayashi 0:c88c3b616c00 338 */
IKobayashi 0:c88c3b616c00 339 typedef union
IKobayashi 0:c88c3b616c00 340 {
IKobayashi 0:c88c3b616c00 341 struct
IKobayashi 0:c88c3b616c00 342 {
IKobayashi 0:c88c3b616c00 343 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
IKobayashi 0:c88c3b616c00 344 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
IKobayashi 0:c88c3b616c00 345 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 346 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 347 } IPSR_Type;
IKobayashi 0:c88c3b616c00 348
IKobayashi 0:c88c3b616c00 349 /* IPSR Register Definitions */
IKobayashi 0:c88c3b616c00 350 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
IKobayashi 0:c88c3b616c00 351 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
IKobayashi 0:c88c3b616c00 352
IKobayashi 0:c88c3b616c00 353
IKobayashi 0:c88c3b616c00 354 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
IKobayashi 0:c88c3b616c00 355 */
IKobayashi 0:c88c3b616c00 356 typedef union
IKobayashi 0:c88c3b616c00 357 {
IKobayashi 0:c88c3b616c00 358 struct
IKobayashi 0:c88c3b616c00 359 {
IKobayashi 0:c88c3b616c00 360 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
IKobayashi 0:c88c3b616c00 361 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
IKobayashi 0:c88c3b616c00 362 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
IKobayashi 0:c88c3b616c00 363 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
IKobayashi 0:c88c3b616c00 364 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
IKobayashi 0:c88c3b616c00 365 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
IKobayashi 0:c88c3b616c00 366 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
IKobayashi 0:c88c3b616c00 367 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
IKobayashi 0:c88c3b616c00 368 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
IKobayashi 0:c88c3b616c00 369 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
IKobayashi 0:c88c3b616c00 370 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
IKobayashi 0:c88c3b616c00 371 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 372 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 373 } xPSR_Type;
IKobayashi 0:c88c3b616c00 374
IKobayashi 0:c88c3b616c00 375 /* xPSR Register Definitions */
IKobayashi 0:c88c3b616c00 376 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
IKobayashi 0:c88c3b616c00 377 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
IKobayashi 0:c88c3b616c00 378
IKobayashi 0:c88c3b616c00 379 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
IKobayashi 0:c88c3b616c00 380 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
IKobayashi 0:c88c3b616c00 381
IKobayashi 0:c88c3b616c00 382 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
IKobayashi 0:c88c3b616c00 383 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
IKobayashi 0:c88c3b616c00 384
IKobayashi 0:c88c3b616c00 385 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
IKobayashi 0:c88c3b616c00 386 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
IKobayashi 0:c88c3b616c00 387
IKobayashi 0:c88c3b616c00 388 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
IKobayashi 0:c88c3b616c00 389 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
IKobayashi 0:c88c3b616c00 390
IKobayashi 0:c88c3b616c00 391 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
IKobayashi 0:c88c3b616c00 392 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
IKobayashi 0:c88c3b616c00 393
IKobayashi 0:c88c3b616c00 394 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
IKobayashi 0:c88c3b616c00 395 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
IKobayashi 0:c88c3b616c00 396
IKobayashi 0:c88c3b616c00 397 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
IKobayashi 0:c88c3b616c00 398 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
IKobayashi 0:c88c3b616c00 399
IKobayashi 0:c88c3b616c00 400 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
IKobayashi 0:c88c3b616c00 401 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
IKobayashi 0:c88c3b616c00 402
IKobayashi 0:c88c3b616c00 403
IKobayashi 0:c88c3b616c00 404 /** \brief Union type to access the Control Registers (CONTROL).
IKobayashi 0:c88c3b616c00 405 */
IKobayashi 0:c88c3b616c00 406 typedef union
IKobayashi 0:c88c3b616c00 407 {
IKobayashi 0:c88c3b616c00 408 struct
IKobayashi 0:c88c3b616c00 409 {
IKobayashi 0:c88c3b616c00 410 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
IKobayashi 0:c88c3b616c00 411 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
IKobayashi 0:c88c3b616c00 412 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
IKobayashi 0:c88c3b616c00 413 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
IKobayashi 0:c88c3b616c00 414 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 415 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 416 } CONTROL_Type;
IKobayashi 0:c88c3b616c00 417
IKobayashi 0:c88c3b616c00 418 /* CONTROL Register Definitions */
IKobayashi 0:c88c3b616c00 419 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
IKobayashi 0:c88c3b616c00 420 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
IKobayashi 0:c88c3b616c00 421
IKobayashi 0:c88c3b616c00 422 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
IKobayashi 0:c88c3b616c00 423 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
IKobayashi 0:c88c3b616c00 424
IKobayashi 0:c88c3b616c00 425 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
IKobayashi 0:c88c3b616c00 426 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
IKobayashi 0:c88c3b616c00 427
IKobayashi 0:c88c3b616c00 428 /*@} end of group CMSIS_CORE */
IKobayashi 0:c88c3b616c00 429
IKobayashi 0:c88c3b616c00 430
IKobayashi 0:c88c3b616c00 431 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 432 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
IKobayashi 0:c88c3b616c00 433 \brief Type definitions for the NVIC Registers
IKobayashi 0:c88c3b616c00 434 @{
IKobayashi 0:c88c3b616c00 435 */
IKobayashi 0:c88c3b616c00 436
IKobayashi 0:c88c3b616c00 437 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
IKobayashi 0:c88c3b616c00 438 */
IKobayashi 0:c88c3b616c00 439 typedef struct
IKobayashi 0:c88c3b616c00 440 {
IKobayashi 0:c88c3b616c00 441 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
IKobayashi 0:c88c3b616c00 442 uint32_t RESERVED0[24];
IKobayashi 0:c88c3b616c00 443 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
IKobayashi 0:c88c3b616c00 444 uint32_t RSERVED1[24];
IKobayashi 0:c88c3b616c00 445 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
IKobayashi 0:c88c3b616c00 446 uint32_t RESERVED2[24];
IKobayashi 0:c88c3b616c00 447 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
IKobayashi 0:c88c3b616c00 448 uint32_t RESERVED3[24];
IKobayashi 0:c88c3b616c00 449 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
IKobayashi 0:c88c3b616c00 450 uint32_t RESERVED4[56];
IKobayashi 0:c88c3b616c00 451 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
IKobayashi 0:c88c3b616c00 452 uint32_t RESERVED5[644];
IKobayashi 0:c88c3b616c00 453 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
IKobayashi 0:c88c3b616c00 454 } NVIC_Type;
IKobayashi 0:c88c3b616c00 455
IKobayashi 0:c88c3b616c00 456 /* Software Triggered Interrupt Register Definitions */
IKobayashi 0:c88c3b616c00 457 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
IKobayashi 0:c88c3b616c00 458 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
IKobayashi 0:c88c3b616c00 459
IKobayashi 0:c88c3b616c00 460 /*@} end of group CMSIS_NVIC */
IKobayashi 0:c88c3b616c00 461
IKobayashi 0:c88c3b616c00 462
IKobayashi 0:c88c3b616c00 463 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 464 \defgroup CMSIS_SCB System Control Block (SCB)
IKobayashi 0:c88c3b616c00 465 \brief Type definitions for the System Control Block Registers
IKobayashi 0:c88c3b616c00 466 @{
IKobayashi 0:c88c3b616c00 467 */
IKobayashi 0:c88c3b616c00 468
IKobayashi 0:c88c3b616c00 469 /** \brief Structure type to access the System Control Block (SCB).
IKobayashi 0:c88c3b616c00 470 */
IKobayashi 0:c88c3b616c00 471 typedef struct
IKobayashi 0:c88c3b616c00 472 {
IKobayashi 0:c88c3b616c00 473 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
IKobayashi 0:c88c3b616c00 474 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
IKobayashi 0:c88c3b616c00 475 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
IKobayashi 0:c88c3b616c00 476 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
IKobayashi 0:c88c3b616c00 477 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
IKobayashi 0:c88c3b616c00 478 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
IKobayashi 0:c88c3b616c00 479 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
IKobayashi 0:c88c3b616c00 480 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
IKobayashi 0:c88c3b616c00 481 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
IKobayashi 0:c88c3b616c00 482 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
IKobayashi 0:c88c3b616c00 483 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
IKobayashi 0:c88c3b616c00 484 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
IKobayashi 0:c88c3b616c00 485 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
IKobayashi 0:c88c3b616c00 486 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
IKobayashi 0:c88c3b616c00 487 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
IKobayashi 0:c88c3b616c00 488 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
IKobayashi 0:c88c3b616c00 489 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
IKobayashi 0:c88c3b616c00 490 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
IKobayashi 0:c88c3b616c00 491 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
IKobayashi 0:c88c3b616c00 492 uint32_t RESERVED0[1];
IKobayashi 0:c88c3b616c00 493 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
IKobayashi 0:c88c3b616c00 494 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
IKobayashi 0:c88c3b616c00 495 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
IKobayashi 0:c88c3b616c00 496 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
IKobayashi 0:c88c3b616c00 497 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
IKobayashi 0:c88c3b616c00 498 uint32_t RESERVED3[93];
IKobayashi 0:c88c3b616c00 499 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
IKobayashi 0:c88c3b616c00 500 uint32_t RESERVED4[15];
IKobayashi 0:c88c3b616c00 501 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
IKobayashi 0:c88c3b616c00 502 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
IKobayashi 0:c88c3b616c00 503 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
IKobayashi 0:c88c3b616c00 504 uint32_t RESERVED5[1];
IKobayashi 0:c88c3b616c00 505 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
IKobayashi 0:c88c3b616c00 506 uint32_t RESERVED6[1];
IKobayashi 0:c88c3b616c00 507 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
IKobayashi 0:c88c3b616c00 508 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
IKobayashi 0:c88c3b616c00 509 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
IKobayashi 0:c88c3b616c00 510 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
IKobayashi 0:c88c3b616c00 511 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
IKobayashi 0:c88c3b616c00 512 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
IKobayashi 0:c88c3b616c00 513 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
IKobayashi 0:c88c3b616c00 514 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
IKobayashi 0:c88c3b616c00 515 uint32_t RESERVED7[6];
IKobayashi 0:c88c3b616c00 516 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
IKobayashi 0:c88c3b616c00 517 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
IKobayashi 0:c88c3b616c00 518 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
IKobayashi 0:c88c3b616c00 519 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
IKobayashi 0:c88c3b616c00 520 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
IKobayashi 0:c88c3b616c00 521 uint32_t RESERVED8[1];
IKobayashi 0:c88c3b616c00 522 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
IKobayashi 0:c88c3b616c00 523 } SCB_Type;
IKobayashi 0:c88c3b616c00 524
IKobayashi 0:c88c3b616c00 525 /* SCB CPUID Register Definitions */
IKobayashi 0:c88c3b616c00 526 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
IKobayashi 0:c88c3b616c00 527 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
IKobayashi 0:c88c3b616c00 528
IKobayashi 0:c88c3b616c00 529 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
IKobayashi 0:c88c3b616c00 530 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
IKobayashi 0:c88c3b616c00 531
IKobayashi 0:c88c3b616c00 532 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
IKobayashi 0:c88c3b616c00 533 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
IKobayashi 0:c88c3b616c00 534
IKobayashi 0:c88c3b616c00 535 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
IKobayashi 0:c88c3b616c00 536 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
IKobayashi 0:c88c3b616c00 537
IKobayashi 0:c88c3b616c00 538 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
IKobayashi 0:c88c3b616c00 539 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
IKobayashi 0:c88c3b616c00 540
IKobayashi 0:c88c3b616c00 541 /* SCB Interrupt Control State Register Definitions */
IKobayashi 0:c88c3b616c00 542 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
IKobayashi 0:c88c3b616c00 543 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
IKobayashi 0:c88c3b616c00 544
IKobayashi 0:c88c3b616c00 545 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
IKobayashi 0:c88c3b616c00 546 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
IKobayashi 0:c88c3b616c00 547
IKobayashi 0:c88c3b616c00 548 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
IKobayashi 0:c88c3b616c00 549 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
IKobayashi 0:c88c3b616c00 550
IKobayashi 0:c88c3b616c00 551 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
IKobayashi 0:c88c3b616c00 552 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
IKobayashi 0:c88c3b616c00 553
IKobayashi 0:c88c3b616c00 554 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
IKobayashi 0:c88c3b616c00 555 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
IKobayashi 0:c88c3b616c00 556
IKobayashi 0:c88c3b616c00 557 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
IKobayashi 0:c88c3b616c00 558 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
IKobayashi 0:c88c3b616c00 559
IKobayashi 0:c88c3b616c00 560 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
IKobayashi 0:c88c3b616c00 561 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
IKobayashi 0:c88c3b616c00 562
IKobayashi 0:c88c3b616c00 563 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
IKobayashi 0:c88c3b616c00 564 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
IKobayashi 0:c88c3b616c00 565
IKobayashi 0:c88c3b616c00 566 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
IKobayashi 0:c88c3b616c00 567 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
IKobayashi 0:c88c3b616c00 568
IKobayashi 0:c88c3b616c00 569 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
IKobayashi 0:c88c3b616c00 570 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
IKobayashi 0:c88c3b616c00 571
IKobayashi 0:c88c3b616c00 572 /* SCB Vector Table Offset Register Definitions */
IKobayashi 0:c88c3b616c00 573 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
IKobayashi 0:c88c3b616c00 574 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
IKobayashi 0:c88c3b616c00 575
IKobayashi 0:c88c3b616c00 576 /* SCB Application Interrupt and Reset Control Register Definitions */
IKobayashi 0:c88c3b616c00 577 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
IKobayashi 0:c88c3b616c00 578 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
IKobayashi 0:c88c3b616c00 579
IKobayashi 0:c88c3b616c00 580 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
IKobayashi 0:c88c3b616c00 581 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
IKobayashi 0:c88c3b616c00 582
IKobayashi 0:c88c3b616c00 583 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
IKobayashi 0:c88c3b616c00 584 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
IKobayashi 0:c88c3b616c00 585
IKobayashi 0:c88c3b616c00 586 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
IKobayashi 0:c88c3b616c00 587 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
IKobayashi 0:c88c3b616c00 588
IKobayashi 0:c88c3b616c00 589 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
IKobayashi 0:c88c3b616c00 590 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
IKobayashi 0:c88c3b616c00 591
IKobayashi 0:c88c3b616c00 592 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
IKobayashi 0:c88c3b616c00 593 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
IKobayashi 0:c88c3b616c00 594
IKobayashi 0:c88c3b616c00 595 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
IKobayashi 0:c88c3b616c00 596 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
IKobayashi 0:c88c3b616c00 597
IKobayashi 0:c88c3b616c00 598 /* SCB System Control Register Definitions */
IKobayashi 0:c88c3b616c00 599 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
IKobayashi 0:c88c3b616c00 600 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
IKobayashi 0:c88c3b616c00 601
IKobayashi 0:c88c3b616c00 602 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
IKobayashi 0:c88c3b616c00 603 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
IKobayashi 0:c88c3b616c00 604
IKobayashi 0:c88c3b616c00 605 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
IKobayashi 0:c88c3b616c00 606 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
IKobayashi 0:c88c3b616c00 607
IKobayashi 0:c88c3b616c00 608 /* SCB Configuration Control Register Definitions */
IKobayashi 0:c88c3b616c00 609 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
IKobayashi 0:c88c3b616c00 610 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
IKobayashi 0:c88c3b616c00 611
IKobayashi 0:c88c3b616c00 612 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
IKobayashi 0:c88c3b616c00 613 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
IKobayashi 0:c88c3b616c00 614
IKobayashi 0:c88c3b616c00 615 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
IKobayashi 0:c88c3b616c00 616 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
IKobayashi 0:c88c3b616c00 617
IKobayashi 0:c88c3b616c00 618 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
IKobayashi 0:c88c3b616c00 619 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
IKobayashi 0:c88c3b616c00 620
IKobayashi 0:c88c3b616c00 621 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
IKobayashi 0:c88c3b616c00 622 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
IKobayashi 0:c88c3b616c00 623
IKobayashi 0:c88c3b616c00 624 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
IKobayashi 0:c88c3b616c00 625 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
IKobayashi 0:c88c3b616c00 626
IKobayashi 0:c88c3b616c00 627 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
IKobayashi 0:c88c3b616c00 628 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
IKobayashi 0:c88c3b616c00 629
IKobayashi 0:c88c3b616c00 630 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
IKobayashi 0:c88c3b616c00 631 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
IKobayashi 0:c88c3b616c00 632
IKobayashi 0:c88c3b616c00 633 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
IKobayashi 0:c88c3b616c00 634 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
IKobayashi 0:c88c3b616c00 635
IKobayashi 0:c88c3b616c00 636 /* SCB System Handler Control and State Register Definitions */
IKobayashi 0:c88c3b616c00 637 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
IKobayashi 0:c88c3b616c00 638 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
IKobayashi 0:c88c3b616c00 639
IKobayashi 0:c88c3b616c00 640 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
IKobayashi 0:c88c3b616c00 641 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
IKobayashi 0:c88c3b616c00 642
IKobayashi 0:c88c3b616c00 643 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
IKobayashi 0:c88c3b616c00 644 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
IKobayashi 0:c88c3b616c00 645
IKobayashi 0:c88c3b616c00 646 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
IKobayashi 0:c88c3b616c00 647 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
IKobayashi 0:c88c3b616c00 648
IKobayashi 0:c88c3b616c00 649 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
IKobayashi 0:c88c3b616c00 650 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
IKobayashi 0:c88c3b616c00 651
IKobayashi 0:c88c3b616c00 652 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
IKobayashi 0:c88c3b616c00 653 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
IKobayashi 0:c88c3b616c00 654
IKobayashi 0:c88c3b616c00 655 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
IKobayashi 0:c88c3b616c00 656 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
IKobayashi 0:c88c3b616c00 657
IKobayashi 0:c88c3b616c00 658 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
IKobayashi 0:c88c3b616c00 659 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
IKobayashi 0:c88c3b616c00 660
IKobayashi 0:c88c3b616c00 661 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
IKobayashi 0:c88c3b616c00 662 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
IKobayashi 0:c88c3b616c00 663
IKobayashi 0:c88c3b616c00 664 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
IKobayashi 0:c88c3b616c00 665 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
IKobayashi 0:c88c3b616c00 666
IKobayashi 0:c88c3b616c00 667 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
IKobayashi 0:c88c3b616c00 668 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
IKobayashi 0:c88c3b616c00 669
IKobayashi 0:c88c3b616c00 670 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
IKobayashi 0:c88c3b616c00 671 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
IKobayashi 0:c88c3b616c00 672
IKobayashi 0:c88c3b616c00 673 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
IKobayashi 0:c88c3b616c00 674 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
IKobayashi 0:c88c3b616c00 675
IKobayashi 0:c88c3b616c00 676 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
IKobayashi 0:c88c3b616c00 677 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
IKobayashi 0:c88c3b616c00 678
IKobayashi 0:c88c3b616c00 679 /* SCB Configurable Fault Status Registers Definitions */
IKobayashi 0:c88c3b616c00 680 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
IKobayashi 0:c88c3b616c00 681 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
IKobayashi 0:c88c3b616c00 682
IKobayashi 0:c88c3b616c00 683 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
IKobayashi 0:c88c3b616c00 684 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
IKobayashi 0:c88c3b616c00 685
IKobayashi 0:c88c3b616c00 686 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
IKobayashi 0:c88c3b616c00 687 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
IKobayashi 0:c88c3b616c00 688
IKobayashi 0:c88c3b616c00 689 /* SCB Hard Fault Status Registers Definitions */
IKobayashi 0:c88c3b616c00 690 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
IKobayashi 0:c88c3b616c00 691 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
IKobayashi 0:c88c3b616c00 692
IKobayashi 0:c88c3b616c00 693 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
IKobayashi 0:c88c3b616c00 694 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
IKobayashi 0:c88c3b616c00 695
IKobayashi 0:c88c3b616c00 696 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
IKobayashi 0:c88c3b616c00 697 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
IKobayashi 0:c88c3b616c00 698
IKobayashi 0:c88c3b616c00 699 /* SCB Debug Fault Status Register Definitions */
IKobayashi 0:c88c3b616c00 700 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
IKobayashi 0:c88c3b616c00 701 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
IKobayashi 0:c88c3b616c00 702
IKobayashi 0:c88c3b616c00 703 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
IKobayashi 0:c88c3b616c00 704 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
IKobayashi 0:c88c3b616c00 705
IKobayashi 0:c88c3b616c00 706 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
IKobayashi 0:c88c3b616c00 707 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
IKobayashi 0:c88c3b616c00 708
IKobayashi 0:c88c3b616c00 709 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
IKobayashi 0:c88c3b616c00 710 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
IKobayashi 0:c88c3b616c00 711
IKobayashi 0:c88c3b616c00 712 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
IKobayashi 0:c88c3b616c00 713 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
IKobayashi 0:c88c3b616c00 714
IKobayashi 0:c88c3b616c00 715 /* Cache Level ID register */
IKobayashi 0:c88c3b616c00 716 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
IKobayashi 0:c88c3b616c00 717 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
IKobayashi 0:c88c3b616c00 718
IKobayashi 0:c88c3b616c00 719 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
IKobayashi 0:c88c3b616c00 720 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
IKobayashi 0:c88c3b616c00 721
IKobayashi 0:c88c3b616c00 722 /* Cache Type register */
IKobayashi 0:c88c3b616c00 723 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
IKobayashi 0:c88c3b616c00 724 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
IKobayashi 0:c88c3b616c00 725
IKobayashi 0:c88c3b616c00 726 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
IKobayashi 0:c88c3b616c00 727 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
IKobayashi 0:c88c3b616c00 728
IKobayashi 0:c88c3b616c00 729 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
IKobayashi 0:c88c3b616c00 730 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
IKobayashi 0:c88c3b616c00 731
IKobayashi 0:c88c3b616c00 732 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
IKobayashi 0:c88c3b616c00 733 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
IKobayashi 0:c88c3b616c00 734
IKobayashi 0:c88c3b616c00 735 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
IKobayashi 0:c88c3b616c00 736 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
IKobayashi 0:c88c3b616c00 737
IKobayashi 0:c88c3b616c00 738 /* Cache Size ID Register */
IKobayashi 0:c88c3b616c00 739 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
IKobayashi 0:c88c3b616c00 740 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
IKobayashi 0:c88c3b616c00 741
IKobayashi 0:c88c3b616c00 742 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
IKobayashi 0:c88c3b616c00 743 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
IKobayashi 0:c88c3b616c00 744
IKobayashi 0:c88c3b616c00 745 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
IKobayashi 0:c88c3b616c00 746 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
IKobayashi 0:c88c3b616c00 747
IKobayashi 0:c88c3b616c00 748 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
IKobayashi 0:c88c3b616c00 749 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
IKobayashi 0:c88c3b616c00 750
IKobayashi 0:c88c3b616c00 751 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
IKobayashi 0:c88c3b616c00 752 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
IKobayashi 0:c88c3b616c00 753
IKobayashi 0:c88c3b616c00 754 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
IKobayashi 0:c88c3b616c00 755 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
IKobayashi 0:c88c3b616c00 756
IKobayashi 0:c88c3b616c00 757 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
IKobayashi 0:c88c3b616c00 758 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
IKobayashi 0:c88c3b616c00 759
IKobayashi 0:c88c3b616c00 760 /* Cache Size Selection Register */
IKobayashi 0:c88c3b616c00 761 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
IKobayashi 0:c88c3b616c00 762 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
IKobayashi 0:c88c3b616c00 763
IKobayashi 0:c88c3b616c00 764 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
IKobayashi 0:c88c3b616c00 765 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
IKobayashi 0:c88c3b616c00 766
IKobayashi 0:c88c3b616c00 767 /* SCB Software Triggered Interrupt Register */
IKobayashi 0:c88c3b616c00 768 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
IKobayashi 0:c88c3b616c00 769 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
IKobayashi 0:c88c3b616c00 770
IKobayashi 0:c88c3b616c00 771 /* Instruction Tightly-Coupled Memory Control Register*/
IKobayashi 0:c88c3b616c00 772 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
IKobayashi 0:c88c3b616c00 773 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
IKobayashi 0:c88c3b616c00 774
IKobayashi 0:c88c3b616c00 775 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
IKobayashi 0:c88c3b616c00 776 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
IKobayashi 0:c88c3b616c00 777
IKobayashi 0:c88c3b616c00 778 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
IKobayashi 0:c88c3b616c00 779 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
IKobayashi 0:c88c3b616c00 780
IKobayashi 0:c88c3b616c00 781 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
IKobayashi 0:c88c3b616c00 782 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
IKobayashi 0:c88c3b616c00 783
IKobayashi 0:c88c3b616c00 784 /* Data Tightly-Coupled Memory Control Registers */
IKobayashi 0:c88c3b616c00 785 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
IKobayashi 0:c88c3b616c00 786 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
IKobayashi 0:c88c3b616c00 787
IKobayashi 0:c88c3b616c00 788 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
IKobayashi 0:c88c3b616c00 789 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
IKobayashi 0:c88c3b616c00 790
IKobayashi 0:c88c3b616c00 791 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
IKobayashi 0:c88c3b616c00 792 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
IKobayashi 0:c88c3b616c00 793
IKobayashi 0:c88c3b616c00 794 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
IKobayashi 0:c88c3b616c00 795 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
IKobayashi 0:c88c3b616c00 796
IKobayashi 0:c88c3b616c00 797 /* AHBP Control Register */
IKobayashi 0:c88c3b616c00 798 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
IKobayashi 0:c88c3b616c00 799 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
IKobayashi 0:c88c3b616c00 800
IKobayashi 0:c88c3b616c00 801 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
IKobayashi 0:c88c3b616c00 802 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
IKobayashi 0:c88c3b616c00 803
IKobayashi 0:c88c3b616c00 804 /* L1 Cache Control Register */
IKobayashi 0:c88c3b616c00 805 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
IKobayashi 0:c88c3b616c00 806 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
IKobayashi 0:c88c3b616c00 807
IKobayashi 0:c88c3b616c00 808 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
IKobayashi 0:c88c3b616c00 809 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
IKobayashi 0:c88c3b616c00 810
IKobayashi 0:c88c3b616c00 811 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
IKobayashi 0:c88c3b616c00 812 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
IKobayashi 0:c88c3b616c00 813
IKobayashi 0:c88c3b616c00 814 /* AHBS control register */
IKobayashi 0:c88c3b616c00 815 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
IKobayashi 0:c88c3b616c00 816 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
IKobayashi 0:c88c3b616c00 817
IKobayashi 0:c88c3b616c00 818 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
IKobayashi 0:c88c3b616c00 819 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
IKobayashi 0:c88c3b616c00 820
IKobayashi 0:c88c3b616c00 821 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
IKobayashi 0:c88c3b616c00 822 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
IKobayashi 0:c88c3b616c00 823
IKobayashi 0:c88c3b616c00 824 /* Auxiliary Bus Fault Status Register */
IKobayashi 0:c88c3b616c00 825 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
IKobayashi 0:c88c3b616c00 826 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
IKobayashi 0:c88c3b616c00 827
IKobayashi 0:c88c3b616c00 828 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
IKobayashi 0:c88c3b616c00 829 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
IKobayashi 0:c88c3b616c00 830
IKobayashi 0:c88c3b616c00 831 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
IKobayashi 0:c88c3b616c00 832 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
IKobayashi 0:c88c3b616c00 833
IKobayashi 0:c88c3b616c00 834 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
IKobayashi 0:c88c3b616c00 835 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
IKobayashi 0:c88c3b616c00 836
IKobayashi 0:c88c3b616c00 837 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
IKobayashi 0:c88c3b616c00 838 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
IKobayashi 0:c88c3b616c00 839
IKobayashi 0:c88c3b616c00 840 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
IKobayashi 0:c88c3b616c00 841 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
IKobayashi 0:c88c3b616c00 842
IKobayashi 0:c88c3b616c00 843 /*@} end of group CMSIS_SCB */
IKobayashi 0:c88c3b616c00 844
IKobayashi 0:c88c3b616c00 845
IKobayashi 0:c88c3b616c00 846 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 847 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
IKobayashi 0:c88c3b616c00 848 \brief Type definitions for the System Control and ID Register not in the SCB
IKobayashi 0:c88c3b616c00 849 @{
IKobayashi 0:c88c3b616c00 850 */
IKobayashi 0:c88c3b616c00 851
IKobayashi 0:c88c3b616c00 852 /** \brief Structure type to access the System Control and ID Register not in the SCB.
IKobayashi 0:c88c3b616c00 853 */
IKobayashi 0:c88c3b616c00 854 typedef struct
IKobayashi 0:c88c3b616c00 855 {
IKobayashi 0:c88c3b616c00 856 uint32_t RESERVED0[1];
IKobayashi 0:c88c3b616c00 857 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
IKobayashi 0:c88c3b616c00 858 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
IKobayashi 0:c88c3b616c00 859 } SCnSCB_Type;
IKobayashi 0:c88c3b616c00 860
IKobayashi 0:c88c3b616c00 861 /* Interrupt Controller Type Register Definitions */
IKobayashi 0:c88c3b616c00 862 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
IKobayashi 0:c88c3b616c00 863 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
IKobayashi 0:c88c3b616c00 864
IKobayashi 0:c88c3b616c00 865 /* Auxiliary Control Register Definitions */
IKobayashi 0:c88c3b616c00 866 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
IKobayashi 0:c88c3b616c00 867 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
IKobayashi 0:c88c3b616c00 868
IKobayashi 0:c88c3b616c00 869 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
IKobayashi 0:c88c3b616c00 870 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
IKobayashi 0:c88c3b616c00 871
IKobayashi 0:c88c3b616c00 872 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
IKobayashi 0:c88c3b616c00 873 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
IKobayashi 0:c88c3b616c00 874
IKobayashi 0:c88c3b616c00 875 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
IKobayashi 0:c88c3b616c00 876 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
IKobayashi 0:c88c3b616c00 877
IKobayashi 0:c88c3b616c00 878 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
IKobayashi 0:c88c3b616c00 879 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
IKobayashi 0:c88c3b616c00 880
IKobayashi 0:c88c3b616c00 881 /*@} end of group CMSIS_SCnotSCB */
IKobayashi 0:c88c3b616c00 882
IKobayashi 0:c88c3b616c00 883
IKobayashi 0:c88c3b616c00 884 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 885 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
IKobayashi 0:c88c3b616c00 886 \brief Type definitions for the System Timer Registers.
IKobayashi 0:c88c3b616c00 887 @{
IKobayashi 0:c88c3b616c00 888 */
IKobayashi 0:c88c3b616c00 889
IKobayashi 0:c88c3b616c00 890 /** \brief Structure type to access the System Timer (SysTick).
IKobayashi 0:c88c3b616c00 891 */
IKobayashi 0:c88c3b616c00 892 typedef struct
IKobayashi 0:c88c3b616c00 893 {
IKobayashi 0:c88c3b616c00 894 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
IKobayashi 0:c88c3b616c00 895 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
IKobayashi 0:c88c3b616c00 896 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
IKobayashi 0:c88c3b616c00 897 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
IKobayashi 0:c88c3b616c00 898 } SysTick_Type;
IKobayashi 0:c88c3b616c00 899
IKobayashi 0:c88c3b616c00 900 /* SysTick Control / Status Register Definitions */
IKobayashi 0:c88c3b616c00 901 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
IKobayashi 0:c88c3b616c00 902 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
IKobayashi 0:c88c3b616c00 903
IKobayashi 0:c88c3b616c00 904 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
IKobayashi 0:c88c3b616c00 905 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
IKobayashi 0:c88c3b616c00 906
IKobayashi 0:c88c3b616c00 907 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
IKobayashi 0:c88c3b616c00 908 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
IKobayashi 0:c88c3b616c00 909
IKobayashi 0:c88c3b616c00 910 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
IKobayashi 0:c88c3b616c00 911 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
IKobayashi 0:c88c3b616c00 912
IKobayashi 0:c88c3b616c00 913 /* SysTick Reload Register Definitions */
IKobayashi 0:c88c3b616c00 914 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
IKobayashi 0:c88c3b616c00 915 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
IKobayashi 0:c88c3b616c00 916
IKobayashi 0:c88c3b616c00 917 /* SysTick Current Register Definitions */
IKobayashi 0:c88c3b616c00 918 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
IKobayashi 0:c88c3b616c00 919 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
IKobayashi 0:c88c3b616c00 920
IKobayashi 0:c88c3b616c00 921 /* SysTick Calibration Register Definitions */
IKobayashi 0:c88c3b616c00 922 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
IKobayashi 0:c88c3b616c00 923 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
IKobayashi 0:c88c3b616c00 924
IKobayashi 0:c88c3b616c00 925 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
IKobayashi 0:c88c3b616c00 926 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
IKobayashi 0:c88c3b616c00 927
IKobayashi 0:c88c3b616c00 928 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
IKobayashi 0:c88c3b616c00 929 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
IKobayashi 0:c88c3b616c00 930
IKobayashi 0:c88c3b616c00 931 /*@} end of group CMSIS_SysTick */
IKobayashi 0:c88c3b616c00 932
IKobayashi 0:c88c3b616c00 933
IKobayashi 0:c88c3b616c00 934 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 935 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
IKobayashi 0:c88c3b616c00 936 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
IKobayashi 0:c88c3b616c00 937 @{
IKobayashi 0:c88c3b616c00 938 */
IKobayashi 0:c88c3b616c00 939
IKobayashi 0:c88c3b616c00 940 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
IKobayashi 0:c88c3b616c00 941 */
IKobayashi 0:c88c3b616c00 942 typedef struct
IKobayashi 0:c88c3b616c00 943 {
IKobayashi 0:c88c3b616c00 944 __O union
IKobayashi 0:c88c3b616c00 945 {
IKobayashi 0:c88c3b616c00 946 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
IKobayashi 0:c88c3b616c00 947 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
IKobayashi 0:c88c3b616c00 948 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
IKobayashi 0:c88c3b616c00 949 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
IKobayashi 0:c88c3b616c00 950 uint32_t RESERVED0[864];
IKobayashi 0:c88c3b616c00 951 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
IKobayashi 0:c88c3b616c00 952 uint32_t RESERVED1[15];
IKobayashi 0:c88c3b616c00 953 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
IKobayashi 0:c88c3b616c00 954 uint32_t RESERVED2[15];
IKobayashi 0:c88c3b616c00 955 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
IKobayashi 0:c88c3b616c00 956 uint32_t RESERVED3[29];
IKobayashi 0:c88c3b616c00 957 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
IKobayashi 0:c88c3b616c00 958 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
IKobayashi 0:c88c3b616c00 959 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
IKobayashi 0:c88c3b616c00 960 uint32_t RESERVED4[43];
IKobayashi 0:c88c3b616c00 961 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
IKobayashi 0:c88c3b616c00 962 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
IKobayashi 0:c88c3b616c00 963 uint32_t RESERVED5[6];
IKobayashi 0:c88c3b616c00 964 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
IKobayashi 0:c88c3b616c00 965 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
IKobayashi 0:c88c3b616c00 966 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
IKobayashi 0:c88c3b616c00 967 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
IKobayashi 0:c88c3b616c00 968 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
IKobayashi 0:c88c3b616c00 969 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
IKobayashi 0:c88c3b616c00 970 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
IKobayashi 0:c88c3b616c00 971 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
IKobayashi 0:c88c3b616c00 972 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
IKobayashi 0:c88c3b616c00 973 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
IKobayashi 0:c88c3b616c00 974 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
IKobayashi 0:c88c3b616c00 975 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
IKobayashi 0:c88c3b616c00 976 } ITM_Type;
IKobayashi 0:c88c3b616c00 977
IKobayashi 0:c88c3b616c00 978 /* ITM Trace Privilege Register Definitions */
IKobayashi 0:c88c3b616c00 979 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
IKobayashi 0:c88c3b616c00 980 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
IKobayashi 0:c88c3b616c00 981
IKobayashi 0:c88c3b616c00 982 /* ITM Trace Control Register Definitions */
IKobayashi 0:c88c3b616c00 983 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
IKobayashi 0:c88c3b616c00 984 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
IKobayashi 0:c88c3b616c00 985
IKobayashi 0:c88c3b616c00 986 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
IKobayashi 0:c88c3b616c00 987 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
IKobayashi 0:c88c3b616c00 988
IKobayashi 0:c88c3b616c00 989 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
IKobayashi 0:c88c3b616c00 990 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
IKobayashi 0:c88c3b616c00 991
IKobayashi 0:c88c3b616c00 992 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
IKobayashi 0:c88c3b616c00 993 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
IKobayashi 0:c88c3b616c00 994
IKobayashi 0:c88c3b616c00 995 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
IKobayashi 0:c88c3b616c00 996 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
IKobayashi 0:c88c3b616c00 997
IKobayashi 0:c88c3b616c00 998 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
IKobayashi 0:c88c3b616c00 999 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
IKobayashi 0:c88c3b616c00 1000
IKobayashi 0:c88c3b616c00 1001 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
IKobayashi 0:c88c3b616c00 1002 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
IKobayashi 0:c88c3b616c00 1003
IKobayashi 0:c88c3b616c00 1004 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
IKobayashi 0:c88c3b616c00 1005 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
IKobayashi 0:c88c3b616c00 1006
IKobayashi 0:c88c3b616c00 1007 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
IKobayashi 0:c88c3b616c00 1008 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
IKobayashi 0:c88c3b616c00 1009
IKobayashi 0:c88c3b616c00 1010 /* ITM Integration Write Register Definitions */
IKobayashi 0:c88c3b616c00 1011 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
IKobayashi 0:c88c3b616c00 1012 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
IKobayashi 0:c88c3b616c00 1013
IKobayashi 0:c88c3b616c00 1014 /* ITM Integration Read Register Definitions */
IKobayashi 0:c88c3b616c00 1015 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
IKobayashi 0:c88c3b616c00 1016 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
IKobayashi 0:c88c3b616c00 1017
IKobayashi 0:c88c3b616c00 1018 /* ITM Integration Mode Control Register Definitions */
IKobayashi 0:c88c3b616c00 1019 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
IKobayashi 0:c88c3b616c00 1020 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
IKobayashi 0:c88c3b616c00 1021
IKobayashi 0:c88c3b616c00 1022 /* ITM Lock Status Register Definitions */
IKobayashi 0:c88c3b616c00 1023 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
IKobayashi 0:c88c3b616c00 1024 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
IKobayashi 0:c88c3b616c00 1025
IKobayashi 0:c88c3b616c00 1026 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
IKobayashi 0:c88c3b616c00 1027 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
IKobayashi 0:c88c3b616c00 1028
IKobayashi 0:c88c3b616c00 1029 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
IKobayashi 0:c88c3b616c00 1030 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
IKobayashi 0:c88c3b616c00 1031
IKobayashi 0:c88c3b616c00 1032 /*@}*/ /* end of group CMSIS_ITM */
IKobayashi 0:c88c3b616c00 1033
IKobayashi 0:c88c3b616c00 1034
IKobayashi 0:c88c3b616c00 1035 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1036 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
IKobayashi 0:c88c3b616c00 1037 \brief Type definitions for the Data Watchpoint and Trace (DWT)
IKobayashi 0:c88c3b616c00 1038 @{
IKobayashi 0:c88c3b616c00 1039 */
IKobayashi 0:c88c3b616c00 1040
IKobayashi 0:c88c3b616c00 1041 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
IKobayashi 0:c88c3b616c00 1042 */
IKobayashi 0:c88c3b616c00 1043 typedef struct
IKobayashi 0:c88c3b616c00 1044 {
IKobayashi 0:c88c3b616c00 1045 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
IKobayashi 0:c88c3b616c00 1046 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
IKobayashi 0:c88c3b616c00 1047 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
IKobayashi 0:c88c3b616c00 1048 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
IKobayashi 0:c88c3b616c00 1049 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
IKobayashi 0:c88c3b616c00 1050 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
IKobayashi 0:c88c3b616c00 1051 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
IKobayashi 0:c88c3b616c00 1052 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
IKobayashi 0:c88c3b616c00 1053 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
IKobayashi 0:c88c3b616c00 1054 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
IKobayashi 0:c88c3b616c00 1055 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
IKobayashi 0:c88c3b616c00 1056 uint32_t RESERVED0[1];
IKobayashi 0:c88c3b616c00 1057 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
IKobayashi 0:c88c3b616c00 1058 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
IKobayashi 0:c88c3b616c00 1059 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
IKobayashi 0:c88c3b616c00 1060 uint32_t RESERVED1[1];
IKobayashi 0:c88c3b616c00 1061 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
IKobayashi 0:c88c3b616c00 1062 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
IKobayashi 0:c88c3b616c00 1063 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
IKobayashi 0:c88c3b616c00 1064 uint32_t RESERVED2[1];
IKobayashi 0:c88c3b616c00 1065 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
IKobayashi 0:c88c3b616c00 1066 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
IKobayashi 0:c88c3b616c00 1067 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
IKobayashi 0:c88c3b616c00 1068 uint32_t RESERVED3[981];
IKobayashi 0:c88c3b616c00 1069 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
IKobayashi 0:c88c3b616c00 1070 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
IKobayashi 0:c88c3b616c00 1071 } DWT_Type;
IKobayashi 0:c88c3b616c00 1072
IKobayashi 0:c88c3b616c00 1073 /* DWT Control Register Definitions */
IKobayashi 0:c88c3b616c00 1074 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
IKobayashi 0:c88c3b616c00 1075 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
IKobayashi 0:c88c3b616c00 1076
IKobayashi 0:c88c3b616c00 1077 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
IKobayashi 0:c88c3b616c00 1078 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
IKobayashi 0:c88c3b616c00 1079
IKobayashi 0:c88c3b616c00 1080 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
IKobayashi 0:c88c3b616c00 1081 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
IKobayashi 0:c88c3b616c00 1082
IKobayashi 0:c88c3b616c00 1083 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
IKobayashi 0:c88c3b616c00 1084 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
IKobayashi 0:c88c3b616c00 1085
IKobayashi 0:c88c3b616c00 1086 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
IKobayashi 0:c88c3b616c00 1087 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
IKobayashi 0:c88c3b616c00 1088
IKobayashi 0:c88c3b616c00 1089 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
IKobayashi 0:c88c3b616c00 1090 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
IKobayashi 0:c88c3b616c00 1091
IKobayashi 0:c88c3b616c00 1092 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
IKobayashi 0:c88c3b616c00 1093 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
IKobayashi 0:c88c3b616c00 1094
IKobayashi 0:c88c3b616c00 1095 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
IKobayashi 0:c88c3b616c00 1096 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
IKobayashi 0:c88c3b616c00 1097
IKobayashi 0:c88c3b616c00 1098 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
IKobayashi 0:c88c3b616c00 1099 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
IKobayashi 0:c88c3b616c00 1100
IKobayashi 0:c88c3b616c00 1101 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
IKobayashi 0:c88c3b616c00 1102 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
IKobayashi 0:c88c3b616c00 1103
IKobayashi 0:c88c3b616c00 1104 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
IKobayashi 0:c88c3b616c00 1105 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
IKobayashi 0:c88c3b616c00 1106
IKobayashi 0:c88c3b616c00 1107 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
IKobayashi 0:c88c3b616c00 1108 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
IKobayashi 0:c88c3b616c00 1109
IKobayashi 0:c88c3b616c00 1110 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
IKobayashi 0:c88c3b616c00 1111 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
IKobayashi 0:c88c3b616c00 1112
IKobayashi 0:c88c3b616c00 1113 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
IKobayashi 0:c88c3b616c00 1114 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
IKobayashi 0:c88c3b616c00 1115
IKobayashi 0:c88c3b616c00 1116 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
IKobayashi 0:c88c3b616c00 1117 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
IKobayashi 0:c88c3b616c00 1118
IKobayashi 0:c88c3b616c00 1119 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
IKobayashi 0:c88c3b616c00 1120 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
IKobayashi 0:c88c3b616c00 1121
IKobayashi 0:c88c3b616c00 1122 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
IKobayashi 0:c88c3b616c00 1123 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
IKobayashi 0:c88c3b616c00 1124
IKobayashi 0:c88c3b616c00 1125 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
IKobayashi 0:c88c3b616c00 1126 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
IKobayashi 0:c88c3b616c00 1127
IKobayashi 0:c88c3b616c00 1128 /* DWT CPI Count Register Definitions */
IKobayashi 0:c88c3b616c00 1129 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
IKobayashi 0:c88c3b616c00 1130 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
IKobayashi 0:c88c3b616c00 1131
IKobayashi 0:c88c3b616c00 1132 /* DWT Exception Overhead Count Register Definitions */
IKobayashi 0:c88c3b616c00 1133 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
IKobayashi 0:c88c3b616c00 1134 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
IKobayashi 0:c88c3b616c00 1135
IKobayashi 0:c88c3b616c00 1136 /* DWT Sleep Count Register Definitions */
IKobayashi 0:c88c3b616c00 1137 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
IKobayashi 0:c88c3b616c00 1138 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
IKobayashi 0:c88c3b616c00 1139
IKobayashi 0:c88c3b616c00 1140 /* DWT LSU Count Register Definitions */
IKobayashi 0:c88c3b616c00 1141 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
IKobayashi 0:c88c3b616c00 1142 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
IKobayashi 0:c88c3b616c00 1143
IKobayashi 0:c88c3b616c00 1144 /* DWT Folded-instruction Count Register Definitions */
IKobayashi 0:c88c3b616c00 1145 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
IKobayashi 0:c88c3b616c00 1146 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
IKobayashi 0:c88c3b616c00 1147
IKobayashi 0:c88c3b616c00 1148 /* DWT Comparator Mask Register Definitions */
IKobayashi 0:c88c3b616c00 1149 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
IKobayashi 0:c88c3b616c00 1150 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
IKobayashi 0:c88c3b616c00 1151
IKobayashi 0:c88c3b616c00 1152 /* DWT Comparator Function Register Definitions */
IKobayashi 0:c88c3b616c00 1153 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
IKobayashi 0:c88c3b616c00 1154 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
IKobayashi 0:c88c3b616c00 1155
IKobayashi 0:c88c3b616c00 1156 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
IKobayashi 0:c88c3b616c00 1157 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
IKobayashi 0:c88c3b616c00 1158
IKobayashi 0:c88c3b616c00 1159 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
IKobayashi 0:c88c3b616c00 1160 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
IKobayashi 0:c88c3b616c00 1161
IKobayashi 0:c88c3b616c00 1162 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
IKobayashi 0:c88c3b616c00 1163 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
IKobayashi 0:c88c3b616c00 1164
IKobayashi 0:c88c3b616c00 1165 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
IKobayashi 0:c88c3b616c00 1166 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
IKobayashi 0:c88c3b616c00 1167
IKobayashi 0:c88c3b616c00 1168 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
IKobayashi 0:c88c3b616c00 1169 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
IKobayashi 0:c88c3b616c00 1170
IKobayashi 0:c88c3b616c00 1171 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
IKobayashi 0:c88c3b616c00 1172 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
IKobayashi 0:c88c3b616c00 1173
IKobayashi 0:c88c3b616c00 1174 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
IKobayashi 0:c88c3b616c00 1175 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
IKobayashi 0:c88c3b616c00 1176
IKobayashi 0:c88c3b616c00 1177 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
IKobayashi 0:c88c3b616c00 1178 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
IKobayashi 0:c88c3b616c00 1179
IKobayashi 0:c88c3b616c00 1180 /*@}*/ /* end of group CMSIS_DWT */
IKobayashi 0:c88c3b616c00 1181
IKobayashi 0:c88c3b616c00 1182
IKobayashi 0:c88c3b616c00 1183 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1184 \defgroup CMSIS_TPI Trace Port Interface (TPI)
IKobayashi 0:c88c3b616c00 1185 \brief Type definitions for the Trace Port Interface (TPI)
IKobayashi 0:c88c3b616c00 1186 @{
IKobayashi 0:c88c3b616c00 1187 */
IKobayashi 0:c88c3b616c00 1188
IKobayashi 0:c88c3b616c00 1189 /** \brief Structure type to access the Trace Port Interface Register (TPI).
IKobayashi 0:c88c3b616c00 1190 */
IKobayashi 0:c88c3b616c00 1191 typedef struct
IKobayashi 0:c88c3b616c00 1192 {
IKobayashi 0:c88c3b616c00 1193 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
IKobayashi 0:c88c3b616c00 1194 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
IKobayashi 0:c88c3b616c00 1195 uint32_t RESERVED0[2];
IKobayashi 0:c88c3b616c00 1196 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
IKobayashi 0:c88c3b616c00 1197 uint32_t RESERVED1[55];
IKobayashi 0:c88c3b616c00 1198 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
IKobayashi 0:c88c3b616c00 1199 uint32_t RESERVED2[131];
IKobayashi 0:c88c3b616c00 1200 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
IKobayashi 0:c88c3b616c00 1201 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
IKobayashi 0:c88c3b616c00 1202 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
IKobayashi 0:c88c3b616c00 1203 uint32_t RESERVED3[759];
IKobayashi 0:c88c3b616c00 1204 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
IKobayashi 0:c88c3b616c00 1205 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
IKobayashi 0:c88c3b616c00 1206 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
IKobayashi 0:c88c3b616c00 1207 uint32_t RESERVED4[1];
IKobayashi 0:c88c3b616c00 1208 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
IKobayashi 0:c88c3b616c00 1209 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
IKobayashi 0:c88c3b616c00 1210 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
IKobayashi 0:c88c3b616c00 1211 uint32_t RESERVED5[39];
IKobayashi 0:c88c3b616c00 1212 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
IKobayashi 0:c88c3b616c00 1213 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
IKobayashi 0:c88c3b616c00 1214 uint32_t RESERVED7[8];
IKobayashi 0:c88c3b616c00 1215 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
IKobayashi 0:c88c3b616c00 1216 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
IKobayashi 0:c88c3b616c00 1217 } TPI_Type;
IKobayashi 0:c88c3b616c00 1218
IKobayashi 0:c88c3b616c00 1219 /* TPI Asynchronous Clock Prescaler Register Definitions */
IKobayashi 0:c88c3b616c00 1220 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
IKobayashi 0:c88c3b616c00 1221 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
IKobayashi 0:c88c3b616c00 1222
IKobayashi 0:c88c3b616c00 1223 /* TPI Selected Pin Protocol Register Definitions */
IKobayashi 0:c88c3b616c00 1224 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
IKobayashi 0:c88c3b616c00 1225 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
IKobayashi 0:c88c3b616c00 1226
IKobayashi 0:c88c3b616c00 1227 /* TPI Formatter and Flush Status Register Definitions */
IKobayashi 0:c88c3b616c00 1228 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
IKobayashi 0:c88c3b616c00 1229 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
IKobayashi 0:c88c3b616c00 1230
IKobayashi 0:c88c3b616c00 1231 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
IKobayashi 0:c88c3b616c00 1232 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
IKobayashi 0:c88c3b616c00 1233
IKobayashi 0:c88c3b616c00 1234 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
IKobayashi 0:c88c3b616c00 1235 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
IKobayashi 0:c88c3b616c00 1236
IKobayashi 0:c88c3b616c00 1237 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
IKobayashi 0:c88c3b616c00 1238 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
IKobayashi 0:c88c3b616c00 1239
IKobayashi 0:c88c3b616c00 1240 /* TPI Formatter and Flush Control Register Definitions */
IKobayashi 0:c88c3b616c00 1241 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
IKobayashi 0:c88c3b616c00 1242 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
IKobayashi 0:c88c3b616c00 1243
IKobayashi 0:c88c3b616c00 1244 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
IKobayashi 0:c88c3b616c00 1245 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
IKobayashi 0:c88c3b616c00 1246
IKobayashi 0:c88c3b616c00 1247 /* TPI TRIGGER Register Definitions */
IKobayashi 0:c88c3b616c00 1248 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
IKobayashi 0:c88c3b616c00 1249 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
IKobayashi 0:c88c3b616c00 1250
IKobayashi 0:c88c3b616c00 1251 /* TPI Integration ETM Data Register Definitions (FIFO0) */
IKobayashi 0:c88c3b616c00 1252 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
IKobayashi 0:c88c3b616c00 1253 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
IKobayashi 0:c88c3b616c00 1254
IKobayashi 0:c88c3b616c00 1255 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
IKobayashi 0:c88c3b616c00 1256 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
IKobayashi 0:c88c3b616c00 1257
IKobayashi 0:c88c3b616c00 1258 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
IKobayashi 0:c88c3b616c00 1259 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
IKobayashi 0:c88c3b616c00 1260
IKobayashi 0:c88c3b616c00 1261 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
IKobayashi 0:c88c3b616c00 1262 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
IKobayashi 0:c88c3b616c00 1263
IKobayashi 0:c88c3b616c00 1264 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
IKobayashi 0:c88c3b616c00 1265 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
IKobayashi 0:c88c3b616c00 1266
IKobayashi 0:c88c3b616c00 1267 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
IKobayashi 0:c88c3b616c00 1268 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
IKobayashi 0:c88c3b616c00 1269
IKobayashi 0:c88c3b616c00 1270 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
IKobayashi 0:c88c3b616c00 1271 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
IKobayashi 0:c88c3b616c00 1272
IKobayashi 0:c88c3b616c00 1273 /* TPI ITATBCTR2 Register Definitions */
IKobayashi 0:c88c3b616c00 1274 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
IKobayashi 0:c88c3b616c00 1275 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
IKobayashi 0:c88c3b616c00 1276
IKobayashi 0:c88c3b616c00 1277 /* TPI Integration ITM Data Register Definitions (FIFO1) */
IKobayashi 0:c88c3b616c00 1278 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
IKobayashi 0:c88c3b616c00 1279 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
IKobayashi 0:c88c3b616c00 1280
IKobayashi 0:c88c3b616c00 1281 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
IKobayashi 0:c88c3b616c00 1282 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
IKobayashi 0:c88c3b616c00 1283
IKobayashi 0:c88c3b616c00 1284 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
IKobayashi 0:c88c3b616c00 1285 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
IKobayashi 0:c88c3b616c00 1286
IKobayashi 0:c88c3b616c00 1287 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
IKobayashi 0:c88c3b616c00 1288 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
IKobayashi 0:c88c3b616c00 1289
IKobayashi 0:c88c3b616c00 1290 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
IKobayashi 0:c88c3b616c00 1291 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
IKobayashi 0:c88c3b616c00 1292
IKobayashi 0:c88c3b616c00 1293 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
IKobayashi 0:c88c3b616c00 1294 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
IKobayashi 0:c88c3b616c00 1295
IKobayashi 0:c88c3b616c00 1296 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
IKobayashi 0:c88c3b616c00 1297 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
IKobayashi 0:c88c3b616c00 1298
IKobayashi 0:c88c3b616c00 1299 /* TPI ITATBCTR0 Register Definitions */
IKobayashi 0:c88c3b616c00 1300 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
IKobayashi 0:c88c3b616c00 1301 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
IKobayashi 0:c88c3b616c00 1302
IKobayashi 0:c88c3b616c00 1303 /* TPI Integration Mode Control Register Definitions */
IKobayashi 0:c88c3b616c00 1304 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
IKobayashi 0:c88c3b616c00 1305 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
IKobayashi 0:c88c3b616c00 1306
IKobayashi 0:c88c3b616c00 1307 /* TPI DEVID Register Definitions */
IKobayashi 0:c88c3b616c00 1308 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
IKobayashi 0:c88c3b616c00 1309 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
IKobayashi 0:c88c3b616c00 1310
IKobayashi 0:c88c3b616c00 1311 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
IKobayashi 0:c88c3b616c00 1312 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
IKobayashi 0:c88c3b616c00 1313
IKobayashi 0:c88c3b616c00 1314 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
IKobayashi 0:c88c3b616c00 1315 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
IKobayashi 0:c88c3b616c00 1316
IKobayashi 0:c88c3b616c00 1317 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
IKobayashi 0:c88c3b616c00 1318 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
IKobayashi 0:c88c3b616c00 1319
IKobayashi 0:c88c3b616c00 1320 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
IKobayashi 0:c88c3b616c00 1321 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
IKobayashi 0:c88c3b616c00 1322
IKobayashi 0:c88c3b616c00 1323 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
IKobayashi 0:c88c3b616c00 1324 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
IKobayashi 0:c88c3b616c00 1325
IKobayashi 0:c88c3b616c00 1326 /* TPI DEVTYPE Register Definitions */
IKobayashi 0:c88c3b616c00 1327 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
IKobayashi 0:c88c3b616c00 1328 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
IKobayashi 0:c88c3b616c00 1329
IKobayashi 0:c88c3b616c00 1330 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
IKobayashi 0:c88c3b616c00 1331 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
IKobayashi 0:c88c3b616c00 1332
IKobayashi 0:c88c3b616c00 1333 /*@}*/ /* end of group CMSIS_TPI */
IKobayashi 0:c88c3b616c00 1334
IKobayashi 0:c88c3b616c00 1335
IKobayashi 0:c88c3b616c00 1336 #if (__MPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 1337 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1338 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
IKobayashi 0:c88c3b616c00 1339 \brief Type definitions for the Memory Protection Unit (MPU)
IKobayashi 0:c88c3b616c00 1340 @{
IKobayashi 0:c88c3b616c00 1341 */
IKobayashi 0:c88c3b616c00 1342
IKobayashi 0:c88c3b616c00 1343 /** \brief Structure type to access the Memory Protection Unit (MPU).
IKobayashi 0:c88c3b616c00 1344 */
IKobayashi 0:c88c3b616c00 1345 typedef struct
IKobayashi 0:c88c3b616c00 1346 {
IKobayashi 0:c88c3b616c00 1347 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
IKobayashi 0:c88c3b616c00 1348 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
IKobayashi 0:c88c3b616c00 1349 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
IKobayashi 0:c88c3b616c00 1350 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
IKobayashi 0:c88c3b616c00 1351 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 1352 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
IKobayashi 0:c88c3b616c00 1353 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 1354 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
IKobayashi 0:c88c3b616c00 1355 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 1356 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
IKobayashi 0:c88c3b616c00 1357 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 1358 } MPU_Type;
IKobayashi 0:c88c3b616c00 1359
IKobayashi 0:c88c3b616c00 1360 /* MPU Type Register */
IKobayashi 0:c88c3b616c00 1361 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
IKobayashi 0:c88c3b616c00 1362 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
IKobayashi 0:c88c3b616c00 1363
IKobayashi 0:c88c3b616c00 1364 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
IKobayashi 0:c88c3b616c00 1365 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
IKobayashi 0:c88c3b616c00 1366
IKobayashi 0:c88c3b616c00 1367 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
IKobayashi 0:c88c3b616c00 1368 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
IKobayashi 0:c88c3b616c00 1369
IKobayashi 0:c88c3b616c00 1370 /* MPU Control Register */
IKobayashi 0:c88c3b616c00 1371 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
IKobayashi 0:c88c3b616c00 1372 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
IKobayashi 0:c88c3b616c00 1373
IKobayashi 0:c88c3b616c00 1374 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
IKobayashi 0:c88c3b616c00 1375 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
IKobayashi 0:c88c3b616c00 1376
IKobayashi 0:c88c3b616c00 1377 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
IKobayashi 0:c88c3b616c00 1378 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
IKobayashi 0:c88c3b616c00 1379
IKobayashi 0:c88c3b616c00 1380 /* MPU Region Number Register */
IKobayashi 0:c88c3b616c00 1381 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
IKobayashi 0:c88c3b616c00 1382 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
IKobayashi 0:c88c3b616c00 1383
IKobayashi 0:c88c3b616c00 1384 /* MPU Region Base Address Register */
IKobayashi 0:c88c3b616c00 1385 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
IKobayashi 0:c88c3b616c00 1386 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
IKobayashi 0:c88c3b616c00 1387
IKobayashi 0:c88c3b616c00 1388 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
IKobayashi 0:c88c3b616c00 1389 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
IKobayashi 0:c88c3b616c00 1390
IKobayashi 0:c88c3b616c00 1391 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
IKobayashi 0:c88c3b616c00 1392 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
IKobayashi 0:c88c3b616c00 1393
IKobayashi 0:c88c3b616c00 1394 /* MPU Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 1395 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
IKobayashi 0:c88c3b616c00 1396 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
IKobayashi 0:c88c3b616c00 1397
IKobayashi 0:c88c3b616c00 1398 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
IKobayashi 0:c88c3b616c00 1399 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
IKobayashi 0:c88c3b616c00 1400
IKobayashi 0:c88c3b616c00 1401 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
IKobayashi 0:c88c3b616c00 1402 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
IKobayashi 0:c88c3b616c00 1403
IKobayashi 0:c88c3b616c00 1404 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
IKobayashi 0:c88c3b616c00 1405 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
IKobayashi 0:c88c3b616c00 1406
IKobayashi 0:c88c3b616c00 1407 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
IKobayashi 0:c88c3b616c00 1408 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
IKobayashi 0:c88c3b616c00 1409
IKobayashi 0:c88c3b616c00 1410 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
IKobayashi 0:c88c3b616c00 1411 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
IKobayashi 0:c88c3b616c00 1412
IKobayashi 0:c88c3b616c00 1413 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
IKobayashi 0:c88c3b616c00 1414 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
IKobayashi 0:c88c3b616c00 1415
IKobayashi 0:c88c3b616c00 1416 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
IKobayashi 0:c88c3b616c00 1417 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
IKobayashi 0:c88c3b616c00 1418
IKobayashi 0:c88c3b616c00 1419 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
IKobayashi 0:c88c3b616c00 1420 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
IKobayashi 0:c88c3b616c00 1421
IKobayashi 0:c88c3b616c00 1422 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
IKobayashi 0:c88c3b616c00 1423 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
IKobayashi 0:c88c3b616c00 1424
IKobayashi 0:c88c3b616c00 1425 /*@} end of group CMSIS_MPU */
IKobayashi 0:c88c3b616c00 1426 #endif
IKobayashi 0:c88c3b616c00 1427
IKobayashi 0:c88c3b616c00 1428
IKobayashi 0:c88c3b616c00 1429 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 1430 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1431 \defgroup CMSIS_FPU Floating Point Unit (FPU)
IKobayashi 0:c88c3b616c00 1432 \brief Type definitions for the Floating Point Unit (FPU)
IKobayashi 0:c88c3b616c00 1433 @{
IKobayashi 0:c88c3b616c00 1434 */
IKobayashi 0:c88c3b616c00 1435
IKobayashi 0:c88c3b616c00 1436 /** \brief Structure type to access the Floating Point Unit (FPU).
IKobayashi 0:c88c3b616c00 1437 */
IKobayashi 0:c88c3b616c00 1438 typedef struct
IKobayashi 0:c88c3b616c00 1439 {
IKobayashi 0:c88c3b616c00 1440 uint32_t RESERVED0[1];
IKobayashi 0:c88c3b616c00 1441 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
IKobayashi 0:c88c3b616c00 1442 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
IKobayashi 0:c88c3b616c00 1443 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
IKobayashi 0:c88c3b616c00 1444 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
IKobayashi 0:c88c3b616c00 1445 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
IKobayashi 0:c88c3b616c00 1446 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
IKobayashi 0:c88c3b616c00 1447 } FPU_Type;
IKobayashi 0:c88c3b616c00 1448
IKobayashi 0:c88c3b616c00 1449 /* Floating-Point Context Control Register */
IKobayashi 0:c88c3b616c00 1450 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
IKobayashi 0:c88c3b616c00 1451 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
IKobayashi 0:c88c3b616c00 1452
IKobayashi 0:c88c3b616c00 1453 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
IKobayashi 0:c88c3b616c00 1454 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
IKobayashi 0:c88c3b616c00 1455
IKobayashi 0:c88c3b616c00 1456 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
IKobayashi 0:c88c3b616c00 1457 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
IKobayashi 0:c88c3b616c00 1458
IKobayashi 0:c88c3b616c00 1459 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
IKobayashi 0:c88c3b616c00 1460 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
IKobayashi 0:c88c3b616c00 1461
IKobayashi 0:c88c3b616c00 1462 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
IKobayashi 0:c88c3b616c00 1463 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
IKobayashi 0:c88c3b616c00 1464
IKobayashi 0:c88c3b616c00 1465 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
IKobayashi 0:c88c3b616c00 1466 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
IKobayashi 0:c88c3b616c00 1467
IKobayashi 0:c88c3b616c00 1468 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
IKobayashi 0:c88c3b616c00 1469 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
IKobayashi 0:c88c3b616c00 1470
IKobayashi 0:c88c3b616c00 1471 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
IKobayashi 0:c88c3b616c00 1472 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
IKobayashi 0:c88c3b616c00 1473
IKobayashi 0:c88c3b616c00 1474 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
IKobayashi 0:c88c3b616c00 1475 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
IKobayashi 0:c88c3b616c00 1476
IKobayashi 0:c88c3b616c00 1477 /* Floating-Point Context Address Register */
IKobayashi 0:c88c3b616c00 1478 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
IKobayashi 0:c88c3b616c00 1479 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
IKobayashi 0:c88c3b616c00 1480
IKobayashi 0:c88c3b616c00 1481 /* Floating-Point Default Status Control Register */
IKobayashi 0:c88c3b616c00 1482 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
IKobayashi 0:c88c3b616c00 1483 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
IKobayashi 0:c88c3b616c00 1484
IKobayashi 0:c88c3b616c00 1485 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
IKobayashi 0:c88c3b616c00 1486 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
IKobayashi 0:c88c3b616c00 1487
IKobayashi 0:c88c3b616c00 1488 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
IKobayashi 0:c88c3b616c00 1489 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
IKobayashi 0:c88c3b616c00 1490
IKobayashi 0:c88c3b616c00 1491 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
IKobayashi 0:c88c3b616c00 1492 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
IKobayashi 0:c88c3b616c00 1493
IKobayashi 0:c88c3b616c00 1494 /* Media and FP Feature Register 0 */
IKobayashi 0:c88c3b616c00 1495 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
IKobayashi 0:c88c3b616c00 1496 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
IKobayashi 0:c88c3b616c00 1497
IKobayashi 0:c88c3b616c00 1498 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
IKobayashi 0:c88c3b616c00 1499 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
IKobayashi 0:c88c3b616c00 1500
IKobayashi 0:c88c3b616c00 1501 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
IKobayashi 0:c88c3b616c00 1502 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
IKobayashi 0:c88c3b616c00 1503
IKobayashi 0:c88c3b616c00 1504 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
IKobayashi 0:c88c3b616c00 1505 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
IKobayashi 0:c88c3b616c00 1506
IKobayashi 0:c88c3b616c00 1507 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
IKobayashi 0:c88c3b616c00 1508 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
IKobayashi 0:c88c3b616c00 1509
IKobayashi 0:c88c3b616c00 1510 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
IKobayashi 0:c88c3b616c00 1511 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
IKobayashi 0:c88c3b616c00 1512
IKobayashi 0:c88c3b616c00 1513 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
IKobayashi 0:c88c3b616c00 1514 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
IKobayashi 0:c88c3b616c00 1515
IKobayashi 0:c88c3b616c00 1516 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
IKobayashi 0:c88c3b616c00 1517 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
IKobayashi 0:c88c3b616c00 1518
IKobayashi 0:c88c3b616c00 1519 /* Media and FP Feature Register 1 */
IKobayashi 0:c88c3b616c00 1520 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
IKobayashi 0:c88c3b616c00 1521 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
IKobayashi 0:c88c3b616c00 1522
IKobayashi 0:c88c3b616c00 1523 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
IKobayashi 0:c88c3b616c00 1524 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
IKobayashi 0:c88c3b616c00 1525
IKobayashi 0:c88c3b616c00 1526 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
IKobayashi 0:c88c3b616c00 1527 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
IKobayashi 0:c88c3b616c00 1528
IKobayashi 0:c88c3b616c00 1529 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
IKobayashi 0:c88c3b616c00 1530 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
IKobayashi 0:c88c3b616c00 1531
IKobayashi 0:c88c3b616c00 1532 /* Media and FP Feature Register 2 */
IKobayashi 0:c88c3b616c00 1533
IKobayashi 0:c88c3b616c00 1534 /*@} end of group CMSIS_FPU */
IKobayashi 0:c88c3b616c00 1535 #endif
IKobayashi 0:c88c3b616c00 1536
IKobayashi 0:c88c3b616c00 1537
IKobayashi 0:c88c3b616c00 1538 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1539 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
IKobayashi 0:c88c3b616c00 1540 \brief Type definitions for the Core Debug Registers
IKobayashi 0:c88c3b616c00 1541 @{
IKobayashi 0:c88c3b616c00 1542 */
IKobayashi 0:c88c3b616c00 1543
IKobayashi 0:c88c3b616c00 1544 /** \brief Structure type to access the Core Debug Register (CoreDebug).
IKobayashi 0:c88c3b616c00 1545 */
IKobayashi 0:c88c3b616c00 1546 typedef struct
IKobayashi 0:c88c3b616c00 1547 {
IKobayashi 0:c88c3b616c00 1548 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
IKobayashi 0:c88c3b616c00 1549 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
IKobayashi 0:c88c3b616c00 1550 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
IKobayashi 0:c88c3b616c00 1551 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
IKobayashi 0:c88c3b616c00 1552 } CoreDebug_Type;
IKobayashi 0:c88c3b616c00 1553
IKobayashi 0:c88c3b616c00 1554 /* Debug Halting Control and Status Register */
IKobayashi 0:c88c3b616c00 1555 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
IKobayashi 0:c88c3b616c00 1556 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
IKobayashi 0:c88c3b616c00 1557
IKobayashi 0:c88c3b616c00 1558 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
IKobayashi 0:c88c3b616c00 1559 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
IKobayashi 0:c88c3b616c00 1560
IKobayashi 0:c88c3b616c00 1561 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
IKobayashi 0:c88c3b616c00 1562 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
IKobayashi 0:c88c3b616c00 1563
IKobayashi 0:c88c3b616c00 1564 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
IKobayashi 0:c88c3b616c00 1565 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
IKobayashi 0:c88c3b616c00 1566
IKobayashi 0:c88c3b616c00 1567 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
IKobayashi 0:c88c3b616c00 1568 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
IKobayashi 0:c88c3b616c00 1569
IKobayashi 0:c88c3b616c00 1570 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
IKobayashi 0:c88c3b616c00 1571 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
IKobayashi 0:c88c3b616c00 1572
IKobayashi 0:c88c3b616c00 1573 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
IKobayashi 0:c88c3b616c00 1574 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
IKobayashi 0:c88c3b616c00 1575
IKobayashi 0:c88c3b616c00 1576 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
IKobayashi 0:c88c3b616c00 1577 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
IKobayashi 0:c88c3b616c00 1578
IKobayashi 0:c88c3b616c00 1579 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
IKobayashi 0:c88c3b616c00 1580 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
IKobayashi 0:c88c3b616c00 1581
IKobayashi 0:c88c3b616c00 1582 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
IKobayashi 0:c88c3b616c00 1583 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
IKobayashi 0:c88c3b616c00 1584
IKobayashi 0:c88c3b616c00 1585 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
IKobayashi 0:c88c3b616c00 1586 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
IKobayashi 0:c88c3b616c00 1587
IKobayashi 0:c88c3b616c00 1588 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
IKobayashi 0:c88c3b616c00 1589 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
IKobayashi 0:c88c3b616c00 1590
IKobayashi 0:c88c3b616c00 1591 /* Debug Core Register Selector Register */
IKobayashi 0:c88c3b616c00 1592 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
IKobayashi 0:c88c3b616c00 1593 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
IKobayashi 0:c88c3b616c00 1594
IKobayashi 0:c88c3b616c00 1595 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
IKobayashi 0:c88c3b616c00 1596 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
IKobayashi 0:c88c3b616c00 1597
IKobayashi 0:c88c3b616c00 1598 /* Debug Exception and Monitor Control Register */
IKobayashi 0:c88c3b616c00 1599 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
IKobayashi 0:c88c3b616c00 1600 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
IKobayashi 0:c88c3b616c00 1601
IKobayashi 0:c88c3b616c00 1602 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
IKobayashi 0:c88c3b616c00 1603 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
IKobayashi 0:c88c3b616c00 1604
IKobayashi 0:c88c3b616c00 1605 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
IKobayashi 0:c88c3b616c00 1606 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
IKobayashi 0:c88c3b616c00 1607
IKobayashi 0:c88c3b616c00 1608 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
IKobayashi 0:c88c3b616c00 1609 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
IKobayashi 0:c88c3b616c00 1610
IKobayashi 0:c88c3b616c00 1611 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
IKobayashi 0:c88c3b616c00 1612 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
IKobayashi 0:c88c3b616c00 1613
IKobayashi 0:c88c3b616c00 1614 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
IKobayashi 0:c88c3b616c00 1615 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
IKobayashi 0:c88c3b616c00 1616
IKobayashi 0:c88c3b616c00 1617 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
IKobayashi 0:c88c3b616c00 1618 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
IKobayashi 0:c88c3b616c00 1619
IKobayashi 0:c88c3b616c00 1620 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
IKobayashi 0:c88c3b616c00 1621 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
IKobayashi 0:c88c3b616c00 1622
IKobayashi 0:c88c3b616c00 1623 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
IKobayashi 0:c88c3b616c00 1624 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
IKobayashi 0:c88c3b616c00 1625
IKobayashi 0:c88c3b616c00 1626 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
IKobayashi 0:c88c3b616c00 1627 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
IKobayashi 0:c88c3b616c00 1628
IKobayashi 0:c88c3b616c00 1629 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
IKobayashi 0:c88c3b616c00 1630 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
IKobayashi 0:c88c3b616c00 1631
IKobayashi 0:c88c3b616c00 1632 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
IKobayashi 0:c88c3b616c00 1633 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
IKobayashi 0:c88c3b616c00 1634
IKobayashi 0:c88c3b616c00 1635 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
IKobayashi 0:c88c3b616c00 1636 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
IKobayashi 0:c88c3b616c00 1637
IKobayashi 0:c88c3b616c00 1638 /*@} end of group CMSIS_CoreDebug */
IKobayashi 0:c88c3b616c00 1639
IKobayashi 0:c88c3b616c00 1640
IKobayashi 0:c88c3b616c00 1641 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 1642 \defgroup CMSIS_core_base Core Definitions
IKobayashi 0:c88c3b616c00 1643 \brief Definitions for base addresses, unions, and structures.
IKobayashi 0:c88c3b616c00 1644 @{
IKobayashi 0:c88c3b616c00 1645 */
IKobayashi 0:c88c3b616c00 1646
IKobayashi 0:c88c3b616c00 1647 /* Memory mapping of Cortex-M4 Hardware */
IKobayashi 0:c88c3b616c00 1648 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
IKobayashi 0:c88c3b616c00 1649 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
IKobayashi 0:c88c3b616c00 1650 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
IKobayashi 0:c88c3b616c00 1651 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
IKobayashi 0:c88c3b616c00 1652 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
IKobayashi 0:c88c3b616c00 1653 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
IKobayashi 0:c88c3b616c00 1654 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
IKobayashi 0:c88c3b616c00 1655 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
IKobayashi 0:c88c3b616c00 1656
IKobayashi 0:c88c3b616c00 1657 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
IKobayashi 0:c88c3b616c00 1658 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
IKobayashi 0:c88c3b616c00 1659 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
IKobayashi 0:c88c3b616c00 1660 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
IKobayashi 0:c88c3b616c00 1661 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
IKobayashi 0:c88c3b616c00 1662 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
IKobayashi 0:c88c3b616c00 1663 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
IKobayashi 0:c88c3b616c00 1664 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
IKobayashi 0:c88c3b616c00 1665
IKobayashi 0:c88c3b616c00 1666 #if (__MPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 1667 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
IKobayashi 0:c88c3b616c00 1668 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
IKobayashi 0:c88c3b616c00 1669 #endif
IKobayashi 0:c88c3b616c00 1670
IKobayashi 0:c88c3b616c00 1671 #if (__FPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 1672 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
IKobayashi 0:c88c3b616c00 1673 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
IKobayashi 0:c88c3b616c00 1674 #endif
IKobayashi 0:c88c3b616c00 1675
IKobayashi 0:c88c3b616c00 1676 /*@} */
IKobayashi 0:c88c3b616c00 1677
IKobayashi 0:c88c3b616c00 1678
IKobayashi 0:c88c3b616c00 1679
IKobayashi 0:c88c3b616c00 1680 /*******************************************************************************
IKobayashi 0:c88c3b616c00 1681 * Hardware Abstraction Layer
IKobayashi 0:c88c3b616c00 1682 Core Function Interface contains:
IKobayashi 0:c88c3b616c00 1683 - Core NVIC Functions
IKobayashi 0:c88c3b616c00 1684 - Core SysTick Functions
IKobayashi 0:c88c3b616c00 1685 - Core Debug Functions
IKobayashi 0:c88c3b616c00 1686 - Core Register Access Functions
IKobayashi 0:c88c3b616c00 1687 ******************************************************************************/
IKobayashi 0:c88c3b616c00 1688 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
IKobayashi 0:c88c3b616c00 1689 */
IKobayashi 0:c88c3b616c00 1690
IKobayashi 0:c88c3b616c00 1691
IKobayashi 0:c88c3b616c00 1692
IKobayashi 0:c88c3b616c00 1693 /* ########################## NVIC functions #################################### */
IKobayashi 0:c88c3b616c00 1694 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 1695 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
IKobayashi 0:c88c3b616c00 1696 \brief Functions that manage interrupts and exceptions via the NVIC.
IKobayashi 0:c88c3b616c00 1697 @{
IKobayashi 0:c88c3b616c00 1698 */
IKobayashi 0:c88c3b616c00 1699
IKobayashi 0:c88c3b616c00 1700 /** \brief Set Priority Grouping
IKobayashi 0:c88c3b616c00 1701
IKobayashi 0:c88c3b616c00 1702 The function sets the priority grouping field using the required unlock sequence.
IKobayashi 0:c88c3b616c00 1703 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
IKobayashi 0:c88c3b616c00 1704 Only values from 0..7 are used.
IKobayashi 0:c88c3b616c00 1705 In case of a conflict between priority grouping and available
IKobayashi 0:c88c3b616c00 1706 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
IKobayashi 0:c88c3b616c00 1707
IKobayashi 0:c88c3b616c00 1708 \param [in] PriorityGroup Priority grouping field.
IKobayashi 0:c88c3b616c00 1709 */
IKobayashi 0:c88c3b616c00 1710 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
IKobayashi 0:c88c3b616c00 1711 {
IKobayashi 0:c88c3b616c00 1712 uint32_t reg_value;
IKobayashi 0:c88c3b616c00 1713 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi 0:c88c3b616c00 1714
IKobayashi 0:c88c3b616c00 1715 reg_value = SCB->AIRCR; /* read old register configuration */
IKobayashi 0:c88c3b616c00 1716 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
IKobayashi 0:c88c3b616c00 1717 reg_value = (reg_value |
IKobayashi 0:c88c3b616c00 1718 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
IKobayashi 0:c88c3b616c00 1719 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
IKobayashi 0:c88c3b616c00 1720 SCB->AIRCR = reg_value;
IKobayashi 0:c88c3b616c00 1721 }
IKobayashi 0:c88c3b616c00 1722
IKobayashi 0:c88c3b616c00 1723
IKobayashi 0:c88c3b616c00 1724 /** \brief Get Priority Grouping
IKobayashi 0:c88c3b616c00 1725
IKobayashi 0:c88c3b616c00 1726 The function reads the priority grouping field from the NVIC Interrupt Controller.
IKobayashi 0:c88c3b616c00 1727
IKobayashi 0:c88c3b616c00 1728 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
IKobayashi 0:c88c3b616c00 1729 */
IKobayashi 0:c88c3b616c00 1730 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
IKobayashi 0:c88c3b616c00 1731 {
IKobayashi 0:c88c3b616c00 1732 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
IKobayashi 0:c88c3b616c00 1733 }
IKobayashi 0:c88c3b616c00 1734
IKobayashi 0:c88c3b616c00 1735
IKobayashi 0:c88c3b616c00 1736 /** \brief Enable External Interrupt
IKobayashi 0:c88c3b616c00 1737
IKobayashi 0:c88c3b616c00 1738 The function enables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi 0:c88c3b616c00 1739
IKobayashi 0:c88c3b616c00 1740 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 1741 */
IKobayashi 0:c88c3b616c00 1742 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1743 {
IKobayashi 0:c88c3b616c00 1744 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 1745 }
IKobayashi 0:c88c3b616c00 1746
IKobayashi 0:c88c3b616c00 1747
IKobayashi 0:c88c3b616c00 1748 /** \brief Disable External Interrupt
IKobayashi 0:c88c3b616c00 1749
IKobayashi 0:c88c3b616c00 1750 The function disables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi 0:c88c3b616c00 1751
IKobayashi 0:c88c3b616c00 1752 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 1753 */
IKobayashi 0:c88c3b616c00 1754 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1755 {
IKobayashi 0:c88c3b616c00 1756 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 1757 __DSB();
IKobayashi 0:c88c3b616c00 1758 __ISB();
IKobayashi 0:c88c3b616c00 1759 }
IKobayashi 0:c88c3b616c00 1760
IKobayashi 0:c88c3b616c00 1761
IKobayashi 0:c88c3b616c00 1762 /** \brief Get Pending Interrupt
IKobayashi 0:c88c3b616c00 1763
IKobayashi 0:c88c3b616c00 1764 The function reads the pending register in the NVIC and returns the pending bit
IKobayashi 0:c88c3b616c00 1765 for the specified interrupt.
IKobayashi 0:c88c3b616c00 1766
IKobayashi 0:c88c3b616c00 1767 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 1768
IKobayashi 0:c88c3b616c00 1769 \return 0 Interrupt status is not pending.
IKobayashi 0:c88c3b616c00 1770 \return 1 Interrupt status is pending.
IKobayashi 0:c88c3b616c00 1771 */
IKobayashi 0:c88c3b616c00 1772 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1773 {
IKobayashi 0:c88c3b616c00 1774 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
IKobayashi 0:c88c3b616c00 1775 }
IKobayashi 0:c88c3b616c00 1776
IKobayashi 0:c88c3b616c00 1777
IKobayashi 0:c88c3b616c00 1778 /** \brief Set Pending Interrupt
IKobayashi 0:c88c3b616c00 1779
IKobayashi 0:c88c3b616c00 1780 The function sets the pending bit of an external interrupt.
IKobayashi 0:c88c3b616c00 1781
IKobayashi 0:c88c3b616c00 1782 \param [in] IRQn Interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 1783 */
IKobayashi 0:c88c3b616c00 1784 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1785 {
IKobayashi 0:c88c3b616c00 1786 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 1787 }
IKobayashi 0:c88c3b616c00 1788
IKobayashi 0:c88c3b616c00 1789
IKobayashi 0:c88c3b616c00 1790 /** \brief Clear Pending Interrupt
IKobayashi 0:c88c3b616c00 1791
IKobayashi 0:c88c3b616c00 1792 The function clears the pending bit of an external interrupt.
IKobayashi 0:c88c3b616c00 1793
IKobayashi 0:c88c3b616c00 1794 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 1795 */
IKobayashi 0:c88c3b616c00 1796 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1797 {
IKobayashi 0:c88c3b616c00 1798 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 1799 }
IKobayashi 0:c88c3b616c00 1800
IKobayashi 0:c88c3b616c00 1801
IKobayashi 0:c88c3b616c00 1802 /** \brief Get Active Interrupt
IKobayashi 0:c88c3b616c00 1803
IKobayashi 0:c88c3b616c00 1804 The function reads the active register in NVIC and returns the active bit.
IKobayashi 0:c88c3b616c00 1805
IKobayashi 0:c88c3b616c00 1806 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 1807
IKobayashi 0:c88c3b616c00 1808 \return 0 Interrupt status is not active.
IKobayashi 0:c88c3b616c00 1809 \return 1 Interrupt status is active.
IKobayashi 0:c88c3b616c00 1810 */
IKobayashi 0:c88c3b616c00 1811 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1812 {
IKobayashi 0:c88c3b616c00 1813 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
IKobayashi 0:c88c3b616c00 1814 }
IKobayashi 0:c88c3b616c00 1815
IKobayashi 0:c88c3b616c00 1816
IKobayashi 0:c88c3b616c00 1817 /** \brief Set Interrupt Priority
IKobayashi 0:c88c3b616c00 1818
IKobayashi 0:c88c3b616c00 1819 The function sets the priority of an interrupt.
IKobayashi 0:c88c3b616c00 1820
IKobayashi 0:c88c3b616c00 1821 \note The priority cannot be set for every core interrupt.
IKobayashi 0:c88c3b616c00 1822
IKobayashi 0:c88c3b616c00 1823 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 1824 \param [in] priority Priority to set.
IKobayashi 0:c88c3b616c00 1825 */
IKobayashi 0:c88c3b616c00 1826 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
IKobayashi 0:c88c3b616c00 1827 {
IKobayashi 0:c88c3b616c00 1828 if((int32_t)IRQn < 0) {
IKobayashi 0:c88c3b616c00 1829 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
IKobayashi 0:c88c3b616c00 1830 }
IKobayashi 0:c88c3b616c00 1831 else {
IKobayashi 0:c88c3b616c00 1832 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
IKobayashi 0:c88c3b616c00 1833 }
IKobayashi 0:c88c3b616c00 1834 }
IKobayashi 0:c88c3b616c00 1835
IKobayashi 0:c88c3b616c00 1836
IKobayashi 0:c88c3b616c00 1837 /** \brief Get Interrupt Priority
IKobayashi 0:c88c3b616c00 1838
IKobayashi 0:c88c3b616c00 1839 The function reads the priority of an interrupt. The interrupt
IKobayashi 0:c88c3b616c00 1840 number can be positive to specify an external (device specific)
IKobayashi 0:c88c3b616c00 1841 interrupt, or negative to specify an internal (core) interrupt.
IKobayashi 0:c88c3b616c00 1842
IKobayashi 0:c88c3b616c00 1843
IKobayashi 0:c88c3b616c00 1844 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 1845 \return Interrupt Priority. Value is aligned automatically to the implemented
IKobayashi 0:c88c3b616c00 1846 priority bits of the microcontroller.
IKobayashi 0:c88c3b616c00 1847 */
IKobayashi 0:c88c3b616c00 1848 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 1849 {
IKobayashi 0:c88c3b616c00 1850
IKobayashi 0:c88c3b616c00 1851 if((int32_t)IRQn < 0) {
IKobayashi 0:c88c3b616c00 1852 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
IKobayashi 0:c88c3b616c00 1853 }
IKobayashi 0:c88c3b616c00 1854 else {
IKobayashi 0:c88c3b616c00 1855 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
IKobayashi 0:c88c3b616c00 1856 }
IKobayashi 0:c88c3b616c00 1857 }
IKobayashi 0:c88c3b616c00 1858
IKobayashi 0:c88c3b616c00 1859
IKobayashi 0:c88c3b616c00 1860 /** \brief Encode Priority
IKobayashi 0:c88c3b616c00 1861
IKobayashi 0:c88c3b616c00 1862 The function encodes the priority for an interrupt with the given priority group,
IKobayashi 0:c88c3b616c00 1863 preemptive priority value, and subpriority value.
IKobayashi 0:c88c3b616c00 1864 In case of a conflict between priority grouping and available
IKobayashi 0:c88c3b616c00 1865 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
IKobayashi 0:c88c3b616c00 1866
IKobayashi 0:c88c3b616c00 1867 \param [in] PriorityGroup Used priority group.
IKobayashi 0:c88c3b616c00 1868 \param [in] PreemptPriority Preemptive priority value (starting from 0).
IKobayashi 0:c88c3b616c00 1869 \param [in] SubPriority Subpriority value (starting from 0).
IKobayashi 0:c88c3b616c00 1870 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
IKobayashi 0:c88c3b616c00 1871 */
IKobayashi 0:c88c3b616c00 1872 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
IKobayashi 0:c88c3b616c00 1873 {
IKobayashi 0:c88c3b616c00 1874 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi 0:c88c3b616c00 1875 uint32_t PreemptPriorityBits;
IKobayashi 0:c88c3b616c00 1876 uint32_t SubPriorityBits;
IKobayashi 0:c88c3b616c00 1877
IKobayashi 0:c88c3b616c00 1878 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
IKobayashi 0:c88c3b616c00 1879 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
IKobayashi 0:c88c3b616c00 1880
IKobayashi 0:c88c3b616c00 1881 return (
IKobayashi 0:c88c3b616c00 1882 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
IKobayashi 0:c88c3b616c00 1883 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
IKobayashi 0:c88c3b616c00 1884 );
IKobayashi 0:c88c3b616c00 1885 }
IKobayashi 0:c88c3b616c00 1886
IKobayashi 0:c88c3b616c00 1887
IKobayashi 0:c88c3b616c00 1888 /** \brief Decode Priority
IKobayashi 0:c88c3b616c00 1889
IKobayashi 0:c88c3b616c00 1890 The function decodes an interrupt priority value with a given priority group to
IKobayashi 0:c88c3b616c00 1891 preemptive priority value and subpriority value.
IKobayashi 0:c88c3b616c00 1892 In case of a conflict between priority grouping and available
IKobayashi 0:c88c3b616c00 1893 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
IKobayashi 0:c88c3b616c00 1894
IKobayashi 0:c88c3b616c00 1895 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
IKobayashi 0:c88c3b616c00 1896 \param [in] PriorityGroup Used priority group.
IKobayashi 0:c88c3b616c00 1897 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
IKobayashi 0:c88c3b616c00 1898 \param [out] pSubPriority Subpriority value (starting from 0).
IKobayashi 0:c88c3b616c00 1899 */
IKobayashi 0:c88c3b616c00 1900 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
IKobayashi 0:c88c3b616c00 1901 {
IKobayashi 0:c88c3b616c00 1902 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi 0:c88c3b616c00 1903 uint32_t PreemptPriorityBits;
IKobayashi 0:c88c3b616c00 1904 uint32_t SubPriorityBits;
IKobayashi 0:c88c3b616c00 1905
IKobayashi 0:c88c3b616c00 1906 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
IKobayashi 0:c88c3b616c00 1907 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
IKobayashi 0:c88c3b616c00 1908
IKobayashi 0:c88c3b616c00 1909 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
IKobayashi 0:c88c3b616c00 1910 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
IKobayashi 0:c88c3b616c00 1911 }
IKobayashi 0:c88c3b616c00 1912
IKobayashi 0:c88c3b616c00 1913
IKobayashi 0:c88c3b616c00 1914 /** \brief System Reset
IKobayashi 0:c88c3b616c00 1915
IKobayashi 0:c88c3b616c00 1916 The function initiates a system reset request to reset the MCU.
IKobayashi 0:c88c3b616c00 1917 */
IKobayashi 0:c88c3b616c00 1918 __STATIC_INLINE void NVIC_SystemReset(void)
IKobayashi 0:c88c3b616c00 1919 {
IKobayashi 0:c88c3b616c00 1920 __DSB(); /* Ensure all outstanding memory accesses included
IKobayashi 0:c88c3b616c00 1921 buffered write are completed before reset */
IKobayashi 0:c88c3b616c00 1922 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
IKobayashi 0:c88c3b616c00 1923 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
IKobayashi 0:c88c3b616c00 1924 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
IKobayashi 0:c88c3b616c00 1925 __DSB(); /* Ensure completion of memory access */
IKobayashi 0:c88c3b616c00 1926 while(1) { __NOP(); } /* wait until reset */
IKobayashi 0:c88c3b616c00 1927 }
IKobayashi 0:c88c3b616c00 1928
IKobayashi 0:c88c3b616c00 1929 /*@} end of CMSIS_Core_NVICFunctions */
IKobayashi 0:c88c3b616c00 1930
IKobayashi 0:c88c3b616c00 1931
IKobayashi 0:c88c3b616c00 1932 /* ########################## FPU functions #################################### */
IKobayashi 0:c88c3b616c00 1933 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 1934 \defgroup CMSIS_Core_FpuFunctions FPU Functions
IKobayashi 0:c88c3b616c00 1935 \brief Function that provides FPU type.
IKobayashi 0:c88c3b616c00 1936 @{
IKobayashi 0:c88c3b616c00 1937 */
IKobayashi 0:c88c3b616c00 1938
IKobayashi 0:c88c3b616c00 1939 /**
IKobayashi 0:c88c3b616c00 1940 \fn uint32_t SCB_GetFPUType(void)
IKobayashi 0:c88c3b616c00 1941 \brief get FPU type
IKobayashi 0:c88c3b616c00 1942 \returns
IKobayashi 0:c88c3b616c00 1943 - \b 0: No FPU
IKobayashi 0:c88c3b616c00 1944 - \b 1: Single precision FPU
IKobayashi 0:c88c3b616c00 1945 - \b 2: Double + Single precision FPU
IKobayashi 0:c88c3b616c00 1946 */
IKobayashi 0:c88c3b616c00 1947 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
IKobayashi 0:c88c3b616c00 1948 {
IKobayashi 0:c88c3b616c00 1949 uint32_t mvfr0;
IKobayashi 0:c88c3b616c00 1950
IKobayashi 0:c88c3b616c00 1951 mvfr0 = SCB->MVFR0;
IKobayashi 0:c88c3b616c00 1952 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
IKobayashi 0:c88c3b616c00 1953 return 2UL; // Double + Single precision FPU
IKobayashi 0:c88c3b616c00 1954 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
IKobayashi 0:c88c3b616c00 1955 return 1UL; // Single precision FPU
IKobayashi 0:c88c3b616c00 1956 } else {
IKobayashi 0:c88c3b616c00 1957 return 0UL; // No FPU
IKobayashi 0:c88c3b616c00 1958 }
IKobayashi 0:c88c3b616c00 1959 }
IKobayashi 0:c88c3b616c00 1960
IKobayashi 0:c88c3b616c00 1961
IKobayashi 0:c88c3b616c00 1962 /*@} end of CMSIS_Core_FpuFunctions */
IKobayashi 0:c88c3b616c00 1963
IKobayashi 0:c88c3b616c00 1964
IKobayashi 0:c88c3b616c00 1965
IKobayashi 0:c88c3b616c00 1966 /* ########################## Cache functions #################################### */
IKobayashi 0:c88c3b616c00 1967 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 1968 \defgroup CMSIS_Core_CacheFunctions Cache Functions
IKobayashi 0:c88c3b616c00 1969 \brief Functions that configure Instruction and Data cache.
IKobayashi 0:c88c3b616c00 1970 @{
IKobayashi 0:c88c3b616c00 1971 */
IKobayashi 0:c88c3b616c00 1972
IKobayashi 0:c88c3b616c00 1973 /* Cache Size ID Register Macros */
IKobayashi 0:c88c3b616c00 1974 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
IKobayashi 0:c88c3b616c00 1975 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
IKobayashi 0:c88c3b616c00 1976 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
IKobayashi 0:c88c3b616c00 1977
IKobayashi 0:c88c3b616c00 1978
IKobayashi 0:c88c3b616c00 1979 /** \brief Enable I-Cache
IKobayashi 0:c88c3b616c00 1980
IKobayashi 0:c88c3b616c00 1981 The function turns on I-Cache
IKobayashi 0:c88c3b616c00 1982 */
IKobayashi 0:c88c3b616c00 1983 __STATIC_INLINE void SCB_EnableICache (void)
IKobayashi 0:c88c3b616c00 1984 {
IKobayashi 0:c88c3b616c00 1985 #if (__ICACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 1986 __DSB();
IKobayashi 0:c88c3b616c00 1987 __ISB();
IKobayashi 0:c88c3b616c00 1988 SCB->ICIALLU = 0UL; // invalidate I-Cache
IKobayashi 0:c88c3b616c00 1989 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
IKobayashi 0:c88c3b616c00 1990 __DSB();
IKobayashi 0:c88c3b616c00 1991 __ISB();
IKobayashi 0:c88c3b616c00 1992 #endif
IKobayashi 0:c88c3b616c00 1993 }
IKobayashi 0:c88c3b616c00 1994
IKobayashi 0:c88c3b616c00 1995
IKobayashi 0:c88c3b616c00 1996 /** \brief Disable I-Cache
IKobayashi 0:c88c3b616c00 1997
IKobayashi 0:c88c3b616c00 1998 The function turns off I-Cache
IKobayashi 0:c88c3b616c00 1999 */
IKobayashi 0:c88c3b616c00 2000 __STATIC_INLINE void SCB_DisableICache (void)
IKobayashi 0:c88c3b616c00 2001 {
IKobayashi 0:c88c3b616c00 2002 #if (__ICACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2003 __DSB();
IKobayashi 0:c88c3b616c00 2004 __ISB();
IKobayashi 0:c88c3b616c00 2005 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
IKobayashi 0:c88c3b616c00 2006 SCB->ICIALLU = 0UL; // invalidate I-Cache
IKobayashi 0:c88c3b616c00 2007 __DSB();
IKobayashi 0:c88c3b616c00 2008 __ISB();
IKobayashi 0:c88c3b616c00 2009 #endif
IKobayashi 0:c88c3b616c00 2010 }
IKobayashi 0:c88c3b616c00 2011
IKobayashi 0:c88c3b616c00 2012
IKobayashi 0:c88c3b616c00 2013 /** \brief Invalidate I-Cache
IKobayashi 0:c88c3b616c00 2014
IKobayashi 0:c88c3b616c00 2015 The function invalidates I-Cache
IKobayashi 0:c88c3b616c00 2016 */
IKobayashi 0:c88c3b616c00 2017 __STATIC_INLINE void SCB_InvalidateICache (void)
IKobayashi 0:c88c3b616c00 2018 {
IKobayashi 0:c88c3b616c00 2019 #if (__ICACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2020 __DSB();
IKobayashi 0:c88c3b616c00 2021 __ISB();
IKobayashi 0:c88c3b616c00 2022 SCB->ICIALLU = 0UL;
IKobayashi 0:c88c3b616c00 2023 __DSB();
IKobayashi 0:c88c3b616c00 2024 __ISB();
IKobayashi 0:c88c3b616c00 2025 #endif
IKobayashi 0:c88c3b616c00 2026 }
IKobayashi 0:c88c3b616c00 2027
IKobayashi 0:c88c3b616c00 2028
IKobayashi 0:c88c3b616c00 2029 /** \brief Enable D-Cache
IKobayashi 0:c88c3b616c00 2030
IKobayashi 0:c88c3b616c00 2031 The function turns on D-Cache
IKobayashi 0:c88c3b616c00 2032 */
IKobayashi 0:c88c3b616c00 2033 __STATIC_INLINE void SCB_EnableDCache (void)
IKobayashi 0:c88c3b616c00 2034 {
IKobayashi 0:c88c3b616c00 2035 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2036 uint32_t ccsidr, sshift, wshift, sw;
IKobayashi 0:c88c3b616c00 2037 uint32_t sets, ways;
IKobayashi 0:c88c3b616c00 2038
IKobayashi 0:c88c3b616c00 2039 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
IKobayashi 0:c88c3b616c00 2040 ccsidr = SCB->CCSIDR;
IKobayashi 0:c88c3b616c00 2041 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
IKobayashi 0:c88c3b616c00 2042 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
IKobayashi 0:c88c3b616c00 2043 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
IKobayashi 0:c88c3b616c00 2044 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
IKobayashi 0:c88c3b616c00 2045
IKobayashi 0:c88c3b616c00 2046 __DSB();
IKobayashi 0:c88c3b616c00 2047
IKobayashi 0:c88c3b616c00 2048 do { // invalidate D-Cache
IKobayashi 0:c88c3b616c00 2049 uint32_t tmpways = ways;
IKobayashi 0:c88c3b616c00 2050 do {
IKobayashi 0:c88c3b616c00 2051 sw = ((tmpways << wshift) | (sets << sshift));
IKobayashi 0:c88c3b616c00 2052 SCB->DCISW = sw;
IKobayashi 0:c88c3b616c00 2053 } while(tmpways--);
IKobayashi 0:c88c3b616c00 2054 } while(sets--);
IKobayashi 0:c88c3b616c00 2055 __DSB();
IKobayashi 0:c88c3b616c00 2056
IKobayashi 0:c88c3b616c00 2057 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
IKobayashi 0:c88c3b616c00 2058
IKobayashi 0:c88c3b616c00 2059 __DSB();
IKobayashi 0:c88c3b616c00 2060 __ISB();
IKobayashi 0:c88c3b616c00 2061 #endif
IKobayashi 0:c88c3b616c00 2062 }
IKobayashi 0:c88c3b616c00 2063
IKobayashi 0:c88c3b616c00 2064
IKobayashi 0:c88c3b616c00 2065 /** \brief Disable D-Cache
IKobayashi 0:c88c3b616c00 2066
IKobayashi 0:c88c3b616c00 2067 The function turns off D-Cache
IKobayashi 0:c88c3b616c00 2068 */
IKobayashi 0:c88c3b616c00 2069 __STATIC_INLINE void SCB_DisableDCache (void)
IKobayashi 0:c88c3b616c00 2070 {
IKobayashi 0:c88c3b616c00 2071 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2072 uint32_t ccsidr, sshift, wshift, sw;
IKobayashi 0:c88c3b616c00 2073 uint32_t sets, ways;
IKobayashi 0:c88c3b616c00 2074
IKobayashi 0:c88c3b616c00 2075 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
IKobayashi 0:c88c3b616c00 2076 ccsidr = SCB->CCSIDR;
IKobayashi 0:c88c3b616c00 2077 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
IKobayashi 0:c88c3b616c00 2078 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
IKobayashi 0:c88c3b616c00 2079 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
IKobayashi 0:c88c3b616c00 2080 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
IKobayashi 0:c88c3b616c00 2081
IKobayashi 0:c88c3b616c00 2082 __DSB();
IKobayashi 0:c88c3b616c00 2083
IKobayashi 0:c88c3b616c00 2084 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
IKobayashi 0:c88c3b616c00 2085
IKobayashi 0:c88c3b616c00 2086 do { // clean & invalidate D-Cache
IKobayashi 0:c88c3b616c00 2087 uint32_t tmpways = ways;
IKobayashi 0:c88c3b616c00 2088 do {
IKobayashi 0:c88c3b616c00 2089 sw = ((tmpways << wshift) | (sets << sshift));
IKobayashi 0:c88c3b616c00 2090 SCB->DCCISW = sw;
IKobayashi 0:c88c3b616c00 2091 } while(tmpways--);
IKobayashi 0:c88c3b616c00 2092 } while(sets--);
IKobayashi 0:c88c3b616c00 2093
IKobayashi 0:c88c3b616c00 2094
IKobayashi 0:c88c3b616c00 2095 __DSB();
IKobayashi 0:c88c3b616c00 2096 __ISB();
IKobayashi 0:c88c3b616c00 2097 #endif
IKobayashi 0:c88c3b616c00 2098 }
IKobayashi 0:c88c3b616c00 2099
IKobayashi 0:c88c3b616c00 2100
IKobayashi 0:c88c3b616c00 2101 /** \brief Invalidate D-Cache
IKobayashi 0:c88c3b616c00 2102
IKobayashi 0:c88c3b616c00 2103 The function invalidates D-Cache
IKobayashi 0:c88c3b616c00 2104 */
IKobayashi 0:c88c3b616c00 2105 __STATIC_INLINE void SCB_InvalidateDCache (void)
IKobayashi 0:c88c3b616c00 2106 {
IKobayashi 0:c88c3b616c00 2107 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2108 uint32_t ccsidr, sshift, wshift, sw;
IKobayashi 0:c88c3b616c00 2109 uint32_t sets, ways;
IKobayashi 0:c88c3b616c00 2110
IKobayashi 0:c88c3b616c00 2111 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
IKobayashi 0:c88c3b616c00 2112 ccsidr = SCB->CCSIDR;
IKobayashi 0:c88c3b616c00 2113 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
IKobayashi 0:c88c3b616c00 2114 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
IKobayashi 0:c88c3b616c00 2115 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
IKobayashi 0:c88c3b616c00 2116 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
IKobayashi 0:c88c3b616c00 2117
IKobayashi 0:c88c3b616c00 2118 __DSB();
IKobayashi 0:c88c3b616c00 2119
IKobayashi 0:c88c3b616c00 2120 do { // invalidate D-Cache
IKobayashi 0:c88c3b616c00 2121 uint32_t tmpways = ways;
IKobayashi 0:c88c3b616c00 2122 do {
IKobayashi 0:c88c3b616c00 2123 sw = ((tmpways << wshift) | (sets << sshift));
IKobayashi 0:c88c3b616c00 2124 SCB->DCISW = sw;
IKobayashi 0:c88c3b616c00 2125 } while(tmpways--);
IKobayashi 0:c88c3b616c00 2126 } while(sets--);
IKobayashi 0:c88c3b616c00 2127
IKobayashi 0:c88c3b616c00 2128 __DSB();
IKobayashi 0:c88c3b616c00 2129 __ISB();
IKobayashi 0:c88c3b616c00 2130 #endif
IKobayashi 0:c88c3b616c00 2131 }
IKobayashi 0:c88c3b616c00 2132
IKobayashi 0:c88c3b616c00 2133
IKobayashi 0:c88c3b616c00 2134 /** \brief Clean D-Cache
IKobayashi 0:c88c3b616c00 2135
IKobayashi 0:c88c3b616c00 2136 The function cleans D-Cache
IKobayashi 0:c88c3b616c00 2137 */
IKobayashi 0:c88c3b616c00 2138 __STATIC_INLINE void SCB_CleanDCache (void)
IKobayashi 0:c88c3b616c00 2139 {
IKobayashi 0:c88c3b616c00 2140 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2141 uint32_t ccsidr, sshift, wshift, sw;
IKobayashi 0:c88c3b616c00 2142 uint32_t sets, ways;
IKobayashi 0:c88c3b616c00 2143
IKobayashi 0:c88c3b616c00 2144 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
IKobayashi 0:c88c3b616c00 2145 ccsidr = SCB->CCSIDR;
IKobayashi 0:c88c3b616c00 2146 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
IKobayashi 0:c88c3b616c00 2147 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
IKobayashi 0:c88c3b616c00 2148 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
IKobayashi 0:c88c3b616c00 2149 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
IKobayashi 0:c88c3b616c00 2150
IKobayashi 0:c88c3b616c00 2151 __DSB();
IKobayashi 0:c88c3b616c00 2152
IKobayashi 0:c88c3b616c00 2153 do { // clean D-Cache
IKobayashi 0:c88c3b616c00 2154 uint32_t tmpways = ways;
IKobayashi 0:c88c3b616c00 2155 do {
IKobayashi 0:c88c3b616c00 2156 sw = ((tmpways << wshift) | (sets << sshift));
IKobayashi 0:c88c3b616c00 2157 SCB->DCCSW = sw;
IKobayashi 0:c88c3b616c00 2158 } while(tmpways--);
IKobayashi 0:c88c3b616c00 2159 } while(sets--);
IKobayashi 0:c88c3b616c00 2160
IKobayashi 0:c88c3b616c00 2161 __DSB();
IKobayashi 0:c88c3b616c00 2162 __ISB();
IKobayashi 0:c88c3b616c00 2163 #endif
IKobayashi 0:c88c3b616c00 2164 }
IKobayashi 0:c88c3b616c00 2165
IKobayashi 0:c88c3b616c00 2166
IKobayashi 0:c88c3b616c00 2167 /** \brief Clean & Invalidate D-Cache
IKobayashi 0:c88c3b616c00 2168
IKobayashi 0:c88c3b616c00 2169 The function cleans and Invalidates D-Cache
IKobayashi 0:c88c3b616c00 2170 */
IKobayashi 0:c88c3b616c00 2171 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
IKobayashi 0:c88c3b616c00 2172 {
IKobayashi 0:c88c3b616c00 2173 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2174 uint32_t ccsidr, sshift, wshift, sw;
IKobayashi 0:c88c3b616c00 2175 uint32_t sets, ways;
IKobayashi 0:c88c3b616c00 2176
IKobayashi 0:c88c3b616c00 2177 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
IKobayashi 0:c88c3b616c00 2178 ccsidr = SCB->CCSIDR;
IKobayashi 0:c88c3b616c00 2179 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
IKobayashi 0:c88c3b616c00 2180 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
IKobayashi 0:c88c3b616c00 2181 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
IKobayashi 0:c88c3b616c00 2182 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
IKobayashi 0:c88c3b616c00 2183
IKobayashi 0:c88c3b616c00 2184 __DSB();
IKobayashi 0:c88c3b616c00 2185
IKobayashi 0:c88c3b616c00 2186 do { // clean & invalidate D-Cache
IKobayashi 0:c88c3b616c00 2187 uint32_t tmpways = ways;
IKobayashi 0:c88c3b616c00 2188 do {
IKobayashi 0:c88c3b616c00 2189 sw = ((tmpways << wshift) | (sets << sshift));
IKobayashi 0:c88c3b616c00 2190 SCB->DCCISW = sw;
IKobayashi 0:c88c3b616c00 2191 } while(tmpways--);
IKobayashi 0:c88c3b616c00 2192 } while(sets--);
IKobayashi 0:c88c3b616c00 2193
IKobayashi 0:c88c3b616c00 2194 __DSB();
IKobayashi 0:c88c3b616c00 2195 __ISB();
IKobayashi 0:c88c3b616c00 2196 #endif
IKobayashi 0:c88c3b616c00 2197 }
IKobayashi 0:c88c3b616c00 2198
IKobayashi 0:c88c3b616c00 2199
IKobayashi 0:c88c3b616c00 2200 /**
IKobayashi 0:c88c3b616c00 2201 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2202 \brief D-Cache Invalidate by address
IKobayashi 0:c88c3b616c00 2203 \param[in] addr address (aligned to 32-byte boundary)
IKobayashi 0:c88c3b616c00 2204 \param[in] dsize size of memory block (in number of bytes)
IKobayashi 0:c88c3b616c00 2205 */
IKobayashi 0:c88c3b616c00 2206 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2207 {
IKobayashi 0:c88c3b616c00 2208 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2209 int32_t op_size = dsize;
IKobayashi 0:c88c3b616c00 2210 uint32_t op_addr = (uint32_t)addr;
IKobayashi 0:c88c3b616c00 2211 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
IKobayashi 0:c88c3b616c00 2212
IKobayashi 0:c88c3b616c00 2213 __DSB();
IKobayashi 0:c88c3b616c00 2214
IKobayashi 0:c88c3b616c00 2215 while (op_size > 0) {
IKobayashi 0:c88c3b616c00 2216 SCB->DCIMVAC = op_addr;
IKobayashi 0:c88c3b616c00 2217 op_addr += linesize;
IKobayashi 0:c88c3b616c00 2218 op_size -= (int32_t)linesize;
IKobayashi 0:c88c3b616c00 2219 }
IKobayashi 0:c88c3b616c00 2220
IKobayashi 0:c88c3b616c00 2221 __DSB();
IKobayashi 0:c88c3b616c00 2222 __ISB();
IKobayashi 0:c88c3b616c00 2223 #endif
IKobayashi 0:c88c3b616c00 2224 }
IKobayashi 0:c88c3b616c00 2225
IKobayashi 0:c88c3b616c00 2226
IKobayashi 0:c88c3b616c00 2227 /**
IKobayashi 0:c88c3b616c00 2228 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2229 \brief D-Cache Clean by address
IKobayashi 0:c88c3b616c00 2230 \param[in] addr address (aligned to 32-byte boundary)
IKobayashi 0:c88c3b616c00 2231 \param[in] dsize size of memory block (in number of bytes)
IKobayashi 0:c88c3b616c00 2232 */
IKobayashi 0:c88c3b616c00 2233 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2234 {
IKobayashi 0:c88c3b616c00 2235 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2236 int32_t op_size = dsize;
IKobayashi 0:c88c3b616c00 2237 uint32_t op_addr = (uint32_t) addr;
IKobayashi 0:c88c3b616c00 2238 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
IKobayashi 0:c88c3b616c00 2239
IKobayashi 0:c88c3b616c00 2240 __DSB();
IKobayashi 0:c88c3b616c00 2241
IKobayashi 0:c88c3b616c00 2242 while (op_size > 0) {
IKobayashi 0:c88c3b616c00 2243 SCB->DCCMVAC = op_addr;
IKobayashi 0:c88c3b616c00 2244 op_addr += linesize;
IKobayashi 0:c88c3b616c00 2245 op_size -= (int32_t)linesize;
IKobayashi 0:c88c3b616c00 2246 }
IKobayashi 0:c88c3b616c00 2247
IKobayashi 0:c88c3b616c00 2248 __DSB();
IKobayashi 0:c88c3b616c00 2249 __ISB();
IKobayashi 0:c88c3b616c00 2250 #endif
IKobayashi 0:c88c3b616c00 2251 }
IKobayashi 0:c88c3b616c00 2252
IKobayashi 0:c88c3b616c00 2253
IKobayashi 0:c88c3b616c00 2254 /**
IKobayashi 0:c88c3b616c00 2255 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2256 \brief D-Cache Clean and Invalidate by address
IKobayashi 0:c88c3b616c00 2257 \param[in] addr address (aligned to 32-byte boundary)
IKobayashi 0:c88c3b616c00 2258 \param[in] dsize size of memory block (in number of bytes)
IKobayashi 0:c88c3b616c00 2259 */
IKobayashi 0:c88c3b616c00 2260 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
IKobayashi 0:c88c3b616c00 2261 {
IKobayashi 0:c88c3b616c00 2262 #if (__DCACHE_PRESENT == 1)
IKobayashi 0:c88c3b616c00 2263 int32_t op_size = dsize;
IKobayashi 0:c88c3b616c00 2264 uint32_t op_addr = (uint32_t) addr;
IKobayashi 0:c88c3b616c00 2265 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
IKobayashi 0:c88c3b616c00 2266
IKobayashi 0:c88c3b616c00 2267 __DSB();
IKobayashi 0:c88c3b616c00 2268
IKobayashi 0:c88c3b616c00 2269 while (op_size > 0) {
IKobayashi 0:c88c3b616c00 2270 SCB->DCCIMVAC = op_addr;
IKobayashi 0:c88c3b616c00 2271 op_addr += linesize;
IKobayashi 0:c88c3b616c00 2272 op_size -= (int32_t)linesize;
IKobayashi 0:c88c3b616c00 2273 }
IKobayashi 0:c88c3b616c00 2274
IKobayashi 0:c88c3b616c00 2275 __DSB();
IKobayashi 0:c88c3b616c00 2276 __ISB();
IKobayashi 0:c88c3b616c00 2277 #endif
IKobayashi 0:c88c3b616c00 2278 }
IKobayashi 0:c88c3b616c00 2279
IKobayashi 0:c88c3b616c00 2280
IKobayashi 0:c88c3b616c00 2281 /*@} end of CMSIS_Core_CacheFunctions */
IKobayashi 0:c88c3b616c00 2282
IKobayashi 0:c88c3b616c00 2283
IKobayashi 0:c88c3b616c00 2284
IKobayashi 0:c88c3b616c00 2285 /* ################################## SysTick function ############################################ */
IKobayashi 0:c88c3b616c00 2286 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 2287 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
IKobayashi 0:c88c3b616c00 2288 \brief Functions that configure the System.
IKobayashi 0:c88c3b616c00 2289 @{
IKobayashi 0:c88c3b616c00 2290 */
IKobayashi 0:c88c3b616c00 2291
IKobayashi 0:c88c3b616c00 2292 #if (__Vendor_SysTickConfig == 0)
IKobayashi 0:c88c3b616c00 2293
IKobayashi 0:c88c3b616c00 2294 /** \brief System Tick Configuration
IKobayashi 0:c88c3b616c00 2295
IKobayashi 0:c88c3b616c00 2296 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
IKobayashi 0:c88c3b616c00 2297 Counter is in free running mode to generate periodic interrupts.
IKobayashi 0:c88c3b616c00 2298
IKobayashi 0:c88c3b616c00 2299 \param [in] ticks Number of ticks between two interrupts.
IKobayashi 0:c88c3b616c00 2300
IKobayashi 0:c88c3b616c00 2301 \return 0 Function succeeded.
IKobayashi 0:c88c3b616c00 2302 \return 1 Function failed.
IKobayashi 0:c88c3b616c00 2303
IKobayashi 0:c88c3b616c00 2304 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
IKobayashi 0:c88c3b616c00 2305 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
IKobayashi 0:c88c3b616c00 2306 must contain a vendor-specific implementation of this function.
IKobayashi 0:c88c3b616c00 2307
IKobayashi 0:c88c3b616c00 2308 */
IKobayashi 0:c88c3b616c00 2309 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
IKobayashi 0:c88c3b616c00 2310 {
IKobayashi 0:c88c3b616c00 2311 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
IKobayashi 0:c88c3b616c00 2312
IKobayashi 0:c88c3b616c00 2313 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
IKobayashi 0:c88c3b616c00 2314 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
IKobayashi 0:c88c3b616c00 2315 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
IKobayashi 0:c88c3b616c00 2316 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
IKobayashi 0:c88c3b616c00 2317 SysTick_CTRL_TICKINT_Msk |
IKobayashi 0:c88c3b616c00 2318 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
IKobayashi 0:c88c3b616c00 2319 return (0UL); /* Function successful */
IKobayashi 0:c88c3b616c00 2320 }
IKobayashi 0:c88c3b616c00 2321
IKobayashi 0:c88c3b616c00 2322 #endif
IKobayashi 0:c88c3b616c00 2323
IKobayashi 0:c88c3b616c00 2324 /*@} end of CMSIS_Core_SysTickFunctions */
IKobayashi 0:c88c3b616c00 2325
IKobayashi 0:c88c3b616c00 2326
IKobayashi 0:c88c3b616c00 2327
IKobayashi 0:c88c3b616c00 2328 /* ##################################### Debug In/Output function ########################################### */
IKobayashi 0:c88c3b616c00 2329 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 2330 \defgroup CMSIS_core_DebugFunctions ITM Functions
IKobayashi 0:c88c3b616c00 2331 \brief Functions that access the ITM debug interface.
IKobayashi 0:c88c3b616c00 2332 @{
IKobayashi 0:c88c3b616c00 2333 */
IKobayashi 0:c88c3b616c00 2334
IKobayashi 0:c88c3b616c00 2335 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
IKobayashi 0:c88c3b616c00 2336 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
IKobayashi 0:c88c3b616c00 2337
IKobayashi 0:c88c3b616c00 2338
IKobayashi 0:c88c3b616c00 2339 /** \brief ITM Send Character
IKobayashi 0:c88c3b616c00 2340
IKobayashi 0:c88c3b616c00 2341 The function transmits a character via the ITM channel 0, and
IKobayashi 0:c88c3b616c00 2342 \li Just returns when no debugger is connected that has booked the output.
IKobayashi 0:c88c3b616c00 2343 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
IKobayashi 0:c88c3b616c00 2344
IKobayashi 0:c88c3b616c00 2345 \param [in] ch Character to transmit.
IKobayashi 0:c88c3b616c00 2346
IKobayashi 0:c88c3b616c00 2347 \returns Character to transmit.
IKobayashi 0:c88c3b616c00 2348 */
IKobayashi 0:c88c3b616c00 2349 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
IKobayashi 0:c88c3b616c00 2350 {
IKobayashi 0:c88c3b616c00 2351 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
IKobayashi 0:c88c3b616c00 2352 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
IKobayashi 0:c88c3b616c00 2353 {
IKobayashi 0:c88c3b616c00 2354 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
IKobayashi 0:c88c3b616c00 2355 ITM->PORT[0].u8 = (uint8_t)ch;
IKobayashi 0:c88c3b616c00 2356 }
IKobayashi 0:c88c3b616c00 2357 return (ch);
IKobayashi 0:c88c3b616c00 2358 }
IKobayashi 0:c88c3b616c00 2359
IKobayashi 0:c88c3b616c00 2360
IKobayashi 0:c88c3b616c00 2361 /** \brief ITM Receive Character
IKobayashi 0:c88c3b616c00 2362
IKobayashi 0:c88c3b616c00 2363 The function inputs a character via the external variable \ref ITM_RxBuffer.
IKobayashi 0:c88c3b616c00 2364
IKobayashi 0:c88c3b616c00 2365 \return Received character.
IKobayashi 0:c88c3b616c00 2366 \return -1 No character pending.
IKobayashi 0:c88c3b616c00 2367 */
IKobayashi 0:c88c3b616c00 2368 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
IKobayashi 0:c88c3b616c00 2369 int32_t ch = -1; /* no character available */
IKobayashi 0:c88c3b616c00 2370
IKobayashi 0:c88c3b616c00 2371 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
IKobayashi 0:c88c3b616c00 2372 ch = ITM_RxBuffer;
IKobayashi 0:c88c3b616c00 2373 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
IKobayashi 0:c88c3b616c00 2374 }
IKobayashi 0:c88c3b616c00 2375
IKobayashi 0:c88c3b616c00 2376 return (ch);
IKobayashi 0:c88c3b616c00 2377 }
IKobayashi 0:c88c3b616c00 2378
IKobayashi 0:c88c3b616c00 2379
IKobayashi 0:c88c3b616c00 2380 /** \brief ITM Check Character
IKobayashi 0:c88c3b616c00 2381
IKobayashi 0:c88c3b616c00 2382 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
IKobayashi 0:c88c3b616c00 2383
IKobayashi 0:c88c3b616c00 2384 \return 0 No character available.
IKobayashi 0:c88c3b616c00 2385 \return 1 Character available.
IKobayashi 0:c88c3b616c00 2386 */
IKobayashi 0:c88c3b616c00 2387 __STATIC_INLINE int32_t ITM_CheckChar (void) {
IKobayashi 0:c88c3b616c00 2388
IKobayashi 0:c88c3b616c00 2389 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
IKobayashi 0:c88c3b616c00 2390 return (0); /* no character available */
IKobayashi 0:c88c3b616c00 2391 } else {
IKobayashi 0:c88c3b616c00 2392 return (1); /* character available */
IKobayashi 0:c88c3b616c00 2393 }
IKobayashi 0:c88c3b616c00 2394 }
IKobayashi 0:c88c3b616c00 2395
IKobayashi 0:c88c3b616c00 2396 /*@} end of CMSIS_core_DebugFunctions */
IKobayashi 0:c88c3b616c00 2397
IKobayashi 0:c88c3b616c00 2398
IKobayashi 0:c88c3b616c00 2399
IKobayashi 0:c88c3b616c00 2400
IKobayashi 0:c88c3b616c00 2401 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 2402 }
IKobayashi 0:c88c3b616c00 2403 #endif
IKobayashi 0:c88c3b616c00 2404
IKobayashi 0:c88c3b616c00 2405 #endif /* __CORE_CM7_H_DEPENDANT */
IKobayashi 0:c88c3b616c00 2406
IKobayashi 0:c88c3b616c00 2407 #endif /* __CMSIS_GENERIC */