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mbed/TARGET_LPC1768/core_cm3.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:: IKobayashi
Date:: Mon Mar 16 23:37:42 2020 +0900
Revision:: 0:c88c3b616c00

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User	Revision	Line number	New contents of line
IKobayashi	0:c88c3b616c00	1	/************************************************************************//
IKobayashi	0:c88c3b616c00	2	* @file core_cm3.h
IKobayashi	0:c88c3b616c00	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
IKobayashi	0:c88c3b616c00	4	* @version V4.10
IKobayashi	0:c88c3b616c00	5	* @date 18. March 2015
IKobayashi	0:c88c3b616c00	6	*
IKobayashi	0:c88c3b616c00	7	* @note
IKobayashi	0:c88c3b616c00	8	*
IKobayashi	0:c88c3b616c00	9	******************************************************************************/
IKobayashi	0:c88c3b616c00	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
IKobayashi	0:c88c3b616c00	11
IKobayashi	0:c88c3b616c00	12	All rights reserved.
IKobayashi	0:c88c3b616c00	13	Redistribution and use in source and binary forms, with or without
IKobayashi	0:c88c3b616c00	14	modification, are permitted provided that the following conditions are met:
IKobayashi	0:c88c3b616c00	15	- Redistributions of source code must retain the above copyright
IKobayashi	0:c88c3b616c00	16	notice, this list of conditions and the following disclaimer.
IKobayashi	0:c88c3b616c00	17	- Redistributions in binary form must reproduce the above copyright
IKobayashi	0:c88c3b616c00	18	notice, this list of conditions and the following disclaimer in the
IKobayashi	0:c88c3b616c00	19	documentation and/or other materials provided with the distribution.
IKobayashi	0:c88c3b616c00	20	- Neither the name of ARM nor the names of its contributors may be used
IKobayashi	0:c88c3b616c00	21	to endorse or promote products derived from this software without
IKobayashi	0:c88c3b616c00	22	specific prior written permission.
IKobayashi	0:c88c3b616c00	23	*
IKobayashi	0:c88c3b616c00	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi	0:c88c3b616c00	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi	0:c88c3b616c00	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi	0:c88c3b616c00	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi	0:c88c3b616c00	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi	0:c88c3b616c00	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi	0:c88c3b616c00	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi	0:c88c3b616c00	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi	0:c88c3b616c00	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi	0:c88c3b616c00	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi	0:c88c3b616c00	34	POSSIBILITY OF SUCH DAMAGE.
IKobayashi	0:c88c3b616c00	35	---------------------------------------------------------------------------*/
IKobayashi	0:c88c3b616c00	36
IKobayashi	0:c88c3b616c00	37
IKobayashi	0:c88c3b616c00	38	#if defined ( __ICCARM__ )
IKobayashi	0:c88c3b616c00	39	#pragma system_include /* treat file as system include file for MISRA check */
IKobayashi	0:c88c3b616c00	40	#endif
IKobayashi	0:c88c3b616c00	41
IKobayashi	0:c88c3b616c00	42	#ifndef __CORE_CM3_H_GENERIC
IKobayashi	0:c88c3b616c00	43	#define __CORE_CM3_H_GENERIC
IKobayashi	0:c88c3b616c00	44
IKobayashi	0:c88c3b616c00	45	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	46	extern "C" {
IKobayashi	0:c88c3b616c00	47	#endif
IKobayashi	0:c88c3b616c00	48
IKobayashi	0:c88c3b616c00	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
IKobayashi	0:c88c3b616c00	50	CMSIS violates the following MISRA-C:2004 rules:
IKobayashi	0:c88c3b616c00	51
IKobayashi	0:c88c3b616c00	52	\li Required Rule 8.5, object/function definition in header file.<br>
IKobayashi	0:c88c3b616c00	53	Function definitions in header files are used to allow 'inlining'.
IKobayashi	0:c88c3b616c00	54
IKobayashi	0:c88c3b616c00	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
IKobayashi	0:c88c3b616c00	56	Unions are used for effective representation of core registers.
IKobayashi	0:c88c3b616c00	57
IKobayashi	0:c88c3b616c00	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
IKobayashi	0:c88c3b616c00	59	Function-like macros are used to allow more efficient code.
IKobayashi	0:c88c3b616c00	60	*/
IKobayashi	0:c88c3b616c00	61
IKobayashi	0:c88c3b616c00	62
IKobayashi	0:c88c3b616c00	63	/*******************************************************************************
IKobayashi	0:c88c3b616c00	64	* CMSIS definitions
IKobayashi	0:c88c3b616c00	65	******************************************************************************/
IKobayashi	0:c88c3b616c00	66	/** \ingroup Cortex_M3
IKobayashi	0:c88c3b616c00	67	@{
IKobayashi	0:c88c3b616c00	68	*/
IKobayashi	0:c88c3b616c00	69
IKobayashi	0:c88c3b616c00	70	/* CMSIS CM3 definitions */
IKobayashi	0:c88c3b616c00	71	#define __CM3_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
IKobayashi	0:c88c3b616c00	72	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
IKobayashi	0:c88c3b616c00	73	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
IKobayashi	0:c88c3b616c00	74	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
IKobayashi	0:c88c3b616c00	75
IKobayashi	0:c88c3b616c00	76	#define __CORTEX_M (0x03) /!< Cortex-M Core /
IKobayashi	0:c88c3b616c00	77
IKobayashi	0:c88c3b616c00	78
IKobayashi	0:c88c3b616c00	79	#if defined ( __CC_ARM )
IKobayashi	0:c88c3b616c00	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
IKobayashi	0:c88c3b616c00	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
IKobayashi	0:c88c3b616c00	82	#define __STATIC_INLINE static __inline
IKobayashi	0:c88c3b616c00	83
IKobayashi	0:c88c3b616c00	84	#elif defined ( __GNUC__ )
IKobayashi	0:c88c3b616c00	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
IKobayashi	0:c88c3b616c00	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
IKobayashi	0:c88c3b616c00	87	#define __STATIC_INLINE static inline
IKobayashi	0:c88c3b616c00	88
IKobayashi	0:c88c3b616c00	89	#elif defined ( __ICCARM__ )
IKobayashi	0:c88c3b616c00	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
IKobayashi	0:c88c3b616c00	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
IKobayashi	0:c88c3b616c00	92	#define __STATIC_INLINE static inline
IKobayashi	0:c88c3b616c00	93
IKobayashi	0:c88c3b616c00	94	#elif defined ( __TMS470__ )
IKobayashi	0:c88c3b616c00	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
IKobayashi	0:c88c3b616c00	96	#define __STATIC_INLINE static inline
IKobayashi	0:c88c3b616c00	97
IKobayashi	0:c88c3b616c00	98	#elif defined ( __TASKING__ )
IKobayashi	0:c88c3b616c00	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
IKobayashi	0:c88c3b616c00	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
IKobayashi	0:c88c3b616c00	101	#define __STATIC_INLINE static inline
IKobayashi	0:c88c3b616c00	102
IKobayashi	0:c88c3b616c00	103	#elif defined ( __CSMC__ )
IKobayashi	0:c88c3b616c00	104	#define __packed
IKobayashi	0:c88c3b616c00	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
IKobayashi	0:c88c3b616c00	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
IKobayashi	0:c88c3b616c00	107	#define __STATIC_INLINE static inline
IKobayashi	0:c88c3b616c00	108
IKobayashi	0:c88c3b616c00	109	#endif
IKobayashi	0:c88c3b616c00	110
IKobayashi	0:c88c3b616c00	111	/** __FPU_USED indicates whether an FPU is used or not.
IKobayashi	0:c88c3b616c00	112	This core does not support an FPU at all
IKobayashi	0:c88c3b616c00	113	*/
IKobayashi	0:c88c3b616c00	114	#define __FPU_USED 0
IKobayashi	0:c88c3b616c00	115
IKobayashi	0:c88c3b616c00	116	#if defined ( __CC_ARM )
IKobayashi	0:c88c3b616c00	117	#if defined __TARGET_FPU_VFP
IKobayashi	0:c88c3b616c00	118	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	119	#endif
IKobayashi	0:c88c3b616c00	120
IKobayashi	0:c88c3b616c00	121	#elif defined ( __GNUC__ )
IKobayashi	0:c88c3b616c00	122	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
IKobayashi	0:c88c3b616c00	123	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	124	#endif
IKobayashi	0:c88c3b616c00	125
IKobayashi	0:c88c3b616c00	126	#elif defined ( __ICCARM__ )
IKobayashi	0:c88c3b616c00	127	#if defined __ARMVFP__
IKobayashi	0:c88c3b616c00	128	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	129	#endif
IKobayashi	0:c88c3b616c00	130
IKobayashi	0:c88c3b616c00	131	#elif defined ( __TMS470__ )
IKobayashi	0:c88c3b616c00	132	#if defined __TI__VFP_SUPPORT____
IKobayashi	0:c88c3b616c00	133	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	134	#endif
IKobayashi	0:c88c3b616c00	135
IKobayashi	0:c88c3b616c00	136	#elif defined ( __TASKING__ )
IKobayashi	0:c88c3b616c00	137	#if defined __FPU_VFP__
IKobayashi	0:c88c3b616c00	138	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	139	#endif
IKobayashi	0:c88c3b616c00	140
IKobayashi	0:c88c3b616c00	141	#elif defined ( __CSMC__ ) /* Cosmic */
IKobayashi	0:c88c3b616c00	142	#if ( __CSMC__ & 0x400) // FPU present for parser
IKobayashi	0:c88c3b616c00	143	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi	0:c88c3b616c00	144	#endif
IKobayashi	0:c88c3b616c00	145	#endif
IKobayashi	0:c88c3b616c00	146
IKobayashi	0:c88c3b616c00	147	#include <stdint.h> /* standard types definitions */
IKobayashi	0:c88c3b616c00	148	#include <core_cmInstr.h> /* Core Instruction Access */
IKobayashi	0:c88c3b616c00	149	#include <core_cmFunc.h> /* Core Function Access */
IKobayashi	0:c88c3b616c00	150
IKobayashi	0:c88c3b616c00	151	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	152	}
IKobayashi	0:c88c3b616c00	153	#endif
IKobayashi	0:c88c3b616c00	154
IKobayashi	0:c88c3b616c00	155	#endif /* __CORE_CM3_H_GENERIC */
IKobayashi	0:c88c3b616c00	156
IKobayashi	0:c88c3b616c00	157	#ifndef __CMSIS_GENERIC
IKobayashi	0:c88c3b616c00	158
IKobayashi	0:c88c3b616c00	159	#ifndef __CORE_CM3_H_DEPENDANT
IKobayashi	0:c88c3b616c00	160	#define __CORE_CM3_H_DEPENDANT
IKobayashi	0:c88c3b616c00	161
IKobayashi	0:c88c3b616c00	162	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	163	extern "C" {
IKobayashi	0:c88c3b616c00	164	#endif
IKobayashi	0:c88c3b616c00	165
IKobayashi	0:c88c3b616c00	166	/* check device defines and use defaults */
IKobayashi	0:c88c3b616c00	167	#if defined __CHECK_DEVICE_DEFINES
IKobayashi	0:c88c3b616c00	168	#ifndef __CM3_REV
IKobayashi	0:c88c3b616c00	169	#define __CM3_REV 0x0200
IKobayashi	0:c88c3b616c00	170	#warning "__CM3_REV not defined in device header file; using default!"
IKobayashi	0:c88c3b616c00	171	#endif
IKobayashi	0:c88c3b616c00	172
IKobayashi	0:c88c3b616c00	173	#ifndef __MPU_PRESENT
IKobayashi	0:c88c3b616c00	174	#define __MPU_PRESENT 0
IKobayashi	0:c88c3b616c00	175	#warning "__MPU_PRESENT not defined in device header file; using default!"
IKobayashi	0:c88c3b616c00	176	#endif
IKobayashi	0:c88c3b616c00	177
IKobayashi	0:c88c3b616c00	178	#ifndef __NVIC_PRIO_BITS
IKobayashi	0:c88c3b616c00	179	#define __NVIC_PRIO_BITS 4
IKobayashi	0:c88c3b616c00	180	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
IKobayashi	0:c88c3b616c00	181	#endif
IKobayashi	0:c88c3b616c00	182
IKobayashi	0:c88c3b616c00	183	#ifndef __Vendor_SysTickConfig
IKobayashi	0:c88c3b616c00	184	#define __Vendor_SysTickConfig 0
IKobayashi	0:c88c3b616c00	185	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
IKobayashi	0:c88c3b616c00	186	#endif
IKobayashi	0:c88c3b616c00	187	#endif
IKobayashi	0:c88c3b616c00	188
IKobayashi	0:c88c3b616c00	189	/* IO definitions (access restrictions to peripheral registers) */
IKobayashi	0:c88c3b616c00	190	/**
IKobayashi	0:c88c3b616c00	191	\defgroup CMSIS_glob_defs CMSIS Global Defines
IKobayashi	0:c88c3b616c00	192
IKobayashi	0:c88c3b616c00	193	<strong>IO Type Qualifiers</strong> are used
IKobayashi	0:c88c3b616c00	194	\li to specify the access to peripheral variables.
IKobayashi	0:c88c3b616c00	195	\li for automatic generation of peripheral register debug information.
IKobayashi	0:c88c3b616c00	196	*/
IKobayashi	0:c88c3b616c00	197	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	198	#define __I volatile /!< Defines 'read only' permissions /
IKobayashi	0:c88c3b616c00	199	#else
IKobayashi	0:c88c3b616c00	200	#define __I volatile const /!< Defines 'read only' permissions /
IKobayashi	0:c88c3b616c00	201	#endif
IKobayashi	0:c88c3b616c00	202	#define __O volatile /!< Defines 'write only' permissions /
IKobayashi	0:c88c3b616c00	203	#define __IO volatile /!< Defines 'read / write' permissions /
IKobayashi	0:c88c3b616c00	204
IKobayashi	0:c88c3b616c00	205	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	206	#define __IM volatile /!< Defines 'read only' permissions /
IKobayashi	0:c88c3b616c00	207	#else
IKobayashi	0:c88c3b616c00	208	#define __IM volatile const /!< Defines 'read only' permissions /
IKobayashi	0:c88c3b616c00	209	#endif
IKobayashi	0:c88c3b616c00	210	#define __OM volatile /!< Defines 'write only' permissions /
IKobayashi	0:c88c3b616c00	211	#define __IOM volatile /!< Defines 'read / write' permissions /
IKobayashi	0:c88c3b616c00	212
IKobayashi	0:c88c3b616c00	213	/@} end of group Cortex_M3 /
IKobayashi	0:c88c3b616c00	214
IKobayashi	0:c88c3b616c00	215
IKobayashi	0:c88c3b616c00	216
IKobayashi	0:c88c3b616c00	217	/*******************************************************************************
IKobayashi	0:c88c3b616c00	218	* Register Abstraction
IKobayashi	0:c88c3b616c00	219	Core Register contain:
IKobayashi	0:c88c3b616c00	220	- Core Register
IKobayashi	0:c88c3b616c00	221	- Core NVIC Register
IKobayashi	0:c88c3b616c00	222	- Core SCB Register
IKobayashi	0:c88c3b616c00	223	- Core SysTick Register
IKobayashi	0:c88c3b616c00	224	- Core Debug Register
IKobayashi	0:c88c3b616c00	225	- Core MPU Register
IKobayashi	0:c88c3b616c00	226	******************************************************************************/
IKobayashi	0:c88c3b616c00	227	/** \defgroup CMSIS_core_register Defines and Type Definitions
IKobayashi	0:c88c3b616c00	228	\brief Type definitions and defines for Cortex-M processor based devices.
IKobayashi	0:c88c3b616c00	229	*/
IKobayashi	0:c88c3b616c00	230
IKobayashi	0:c88c3b616c00	231	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	232	\defgroup CMSIS_CORE Status and Control Registers
IKobayashi	0:c88c3b616c00	233	\brief Core Register type definitions.
IKobayashi	0:c88c3b616c00	234	@{
IKobayashi	0:c88c3b616c00	235	*/
IKobayashi	0:c88c3b616c00	236
IKobayashi	0:c88c3b616c00	237	/** \brief Union type to access the Application Program Status Register (APSR).
IKobayashi	0:c88c3b616c00	238	*/
IKobayashi	0:c88c3b616c00	239	typedef union
IKobayashi	0:c88c3b616c00	240	{
IKobayashi	0:c88c3b616c00	241	struct
IKobayashi	0:c88c3b616c00	242	{
IKobayashi	0:c88c3b616c00	243	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
IKobayashi	0:c88c3b616c00	244	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
IKobayashi	0:c88c3b616c00	245	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
IKobayashi	0:c88c3b616c00	246	uint32_t C:1; /!< bit: 29 Carry condition code flag /
IKobayashi	0:c88c3b616c00	247	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
IKobayashi	0:c88c3b616c00	248	uint32_t N:1; /!< bit: 31 Negative condition code flag /
IKobayashi	0:c88c3b616c00	249	} b; /!< Structure used for bit access /
IKobayashi	0:c88c3b616c00	250	uint32_t w; /!< Type used for word access /
IKobayashi	0:c88c3b616c00	251	} APSR_Type;
IKobayashi	0:c88c3b616c00	252
IKobayashi	0:c88c3b616c00	253	/* APSR Register Definitions */
IKobayashi	0:c88c3b616c00	254	#define APSR_N_Pos 31 /!< APSR: N Position /
IKobayashi	0:c88c3b616c00	255	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
IKobayashi	0:c88c3b616c00	256
IKobayashi	0:c88c3b616c00	257	#define APSR_Z_Pos 30 /!< APSR: Z Position /
IKobayashi	0:c88c3b616c00	258	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
IKobayashi	0:c88c3b616c00	259
IKobayashi	0:c88c3b616c00	260	#define APSR_C_Pos 29 /!< APSR: C Position /
IKobayashi	0:c88c3b616c00	261	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
IKobayashi	0:c88c3b616c00	262
IKobayashi	0:c88c3b616c00	263	#define APSR_V_Pos 28 /!< APSR: V Position /
IKobayashi	0:c88c3b616c00	264	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
IKobayashi	0:c88c3b616c00	265
IKobayashi	0:c88c3b616c00	266	#define APSR_Q_Pos 27 /!< APSR: Q Position /
IKobayashi	0:c88c3b616c00	267	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
IKobayashi	0:c88c3b616c00	268
IKobayashi	0:c88c3b616c00	269
IKobayashi	0:c88c3b616c00	270	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
IKobayashi	0:c88c3b616c00	271	*/
IKobayashi	0:c88c3b616c00	272	typedef union
IKobayashi	0:c88c3b616c00	273	{
IKobayashi	0:c88c3b616c00	274	struct
IKobayashi	0:c88c3b616c00	275	{
IKobayashi	0:c88c3b616c00	276	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
IKobayashi	0:c88c3b616c00	277	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
IKobayashi	0:c88c3b616c00	278	} b; /!< Structure used for bit access /
IKobayashi	0:c88c3b616c00	279	uint32_t w; /!< Type used for word access /
IKobayashi	0:c88c3b616c00	280	} IPSR_Type;
IKobayashi	0:c88c3b616c00	281
IKobayashi	0:c88c3b616c00	282	/* IPSR Register Definitions */
IKobayashi	0:c88c3b616c00	283	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
IKobayashi	0:c88c3b616c00	284	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
IKobayashi	0:c88c3b616c00	285
IKobayashi	0:c88c3b616c00	286
IKobayashi	0:c88c3b616c00	287	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
IKobayashi	0:c88c3b616c00	288	*/
IKobayashi	0:c88c3b616c00	289	typedef union
IKobayashi	0:c88c3b616c00	290	{
IKobayashi	0:c88c3b616c00	291	struct
IKobayashi	0:c88c3b616c00	292	{
IKobayashi	0:c88c3b616c00	293	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
IKobayashi	0:c88c3b616c00	294	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
IKobayashi	0:c88c3b616c00	295	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
IKobayashi	0:c88c3b616c00	296	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
IKobayashi	0:c88c3b616c00	297	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
IKobayashi	0:c88c3b616c00	298	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
IKobayashi	0:c88c3b616c00	299	uint32_t C:1; /!< bit: 29 Carry condition code flag /
IKobayashi	0:c88c3b616c00	300	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
IKobayashi	0:c88c3b616c00	301	uint32_t N:1; /!< bit: 31 Negative condition code flag /
IKobayashi	0:c88c3b616c00	302	} b; /!< Structure used for bit access /
IKobayashi	0:c88c3b616c00	303	uint32_t w; /!< Type used for word access /
IKobayashi	0:c88c3b616c00	304	} xPSR_Type;
IKobayashi	0:c88c3b616c00	305
IKobayashi	0:c88c3b616c00	306	/* xPSR Register Definitions */
IKobayashi	0:c88c3b616c00	307	#define xPSR_N_Pos 31 /!< xPSR: N Position /
IKobayashi	0:c88c3b616c00	308	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
IKobayashi	0:c88c3b616c00	309
IKobayashi	0:c88c3b616c00	310	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
IKobayashi	0:c88c3b616c00	311	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
IKobayashi	0:c88c3b616c00	312
IKobayashi	0:c88c3b616c00	313	#define xPSR_C_Pos 29 /!< xPSR: C Position /
IKobayashi	0:c88c3b616c00	314	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
IKobayashi	0:c88c3b616c00	315
IKobayashi	0:c88c3b616c00	316	#define xPSR_V_Pos 28 /!< xPSR: V Position /
IKobayashi	0:c88c3b616c00	317	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
IKobayashi	0:c88c3b616c00	318
IKobayashi	0:c88c3b616c00	319	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
IKobayashi	0:c88c3b616c00	320	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
IKobayashi	0:c88c3b616c00	321
IKobayashi	0:c88c3b616c00	322	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
IKobayashi	0:c88c3b616c00	323	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
IKobayashi	0:c88c3b616c00	324
IKobayashi	0:c88c3b616c00	325	#define xPSR_T_Pos 24 /!< xPSR: T Position /
IKobayashi	0:c88c3b616c00	326	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
IKobayashi	0:c88c3b616c00	327
IKobayashi	0:c88c3b616c00	328	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
IKobayashi	0:c88c3b616c00	329	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
IKobayashi	0:c88c3b616c00	330
IKobayashi	0:c88c3b616c00	331
IKobayashi	0:c88c3b616c00	332	/** \brief Union type to access the Control Registers (CONTROL).
IKobayashi	0:c88c3b616c00	333	*/
IKobayashi	0:c88c3b616c00	334	typedef union
IKobayashi	0:c88c3b616c00	335	{
IKobayashi	0:c88c3b616c00	336	struct
IKobayashi	0:c88c3b616c00	337	{
IKobayashi	0:c88c3b616c00	338	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
IKobayashi	0:c88c3b616c00	339	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
IKobayashi	0:c88c3b616c00	340	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
IKobayashi	0:c88c3b616c00	341	} b; /!< Structure used for bit access /
IKobayashi	0:c88c3b616c00	342	uint32_t w; /!< Type used for word access /
IKobayashi	0:c88c3b616c00	343	} CONTROL_Type;
IKobayashi	0:c88c3b616c00	344
IKobayashi	0:c88c3b616c00	345	/* CONTROL Register Definitions */
IKobayashi	0:c88c3b616c00	346	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
IKobayashi	0:c88c3b616c00	347	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
IKobayashi	0:c88c3b616c00	348
IKobayashi	0:c88c3b616c00	349	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
IKobayashi	0:c88c3b616c00	350	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
IKobayashi	0:c88c3b616c00	351
IKobayashi	0:c88c3b616c00	352	/@} end of group CMSIS_CORE /
IKobayashi	0:c88c3b616c00	353
IKobayashi	0:c88c3b616c00	354
IKobayashi	0:c88c3b616c00	355	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	356	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
IKobayashi	0:c88c3b616c00	357	\brief Type definitions for the NVIC Registers
IKobayashi	0:c88c3b616c00	358	@{
IKobayashi	0:c88c3b616c00	359	*/
IKobayashi	0:c88c3b616c00	360
IKobayashi	0:c88c3b616c00	361	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
IKobayashi	0:c88c3b616c00	362	*/
IKobayashi	0:c88c3b616c00	363	typedef struct
IKobayashi	0:c88c3b616c00	364	{
IKobayashi	0:c88c3b616c00	365	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
IKobayashi	0:c88c3b616c00	366	uint32_t RESERVED0[24];
IKobayashi	0:c88c3b616c00	367	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
IKobayashi	0:c88c3b616c00	368	uint32_t RSERVED1[24];
IKobayashi	0:c88c3b616c00	369	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
IKobayashi	0:c88c3b616c00	370	uint32_t RESERVED2[24];
IKobayashi	0:c88c3b616c00	371	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
IKobayashi	0:c88c3b616c00	372	uint32_t RESERVED3[24];
IKobayashi	0:c88c3b616c00	373	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
IKobayashi	0:c88c3b616c00	374	uint32_t RESERVED4[56];
IKobayashi	0:c88c3b616c00	375	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
IKobayashi	0:c88c3b616c00	376	uint32_t RESERVED5[644];
IKobayashi	0:c88c3b616c00	377	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
IKobayashi	0:c88c3b616c00	378	} NVIC_Type;
IKobayashi	0:c88c3b616c00	379
IKobayashi	0:c88c3b616c00	380	/* Software Triggered Interrupt Register Definitions */
IKobayashi	0:c88c3b616c00	381	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
IKobayashi	0:c88c3b616c00	382	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
IKobayashi	0:c88c3b616c00	383
IKobayashi	0:c88c3b616c00	384	/@} end of group CMSIS_NVIC /
IKobayashi	0:c88c3b616c00	385
IKobayashi	0:c88c3b616c00	386
IKobayashi	0:c88c3b616c00	387	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	388	\defgroup CMSIS_SCB System Control Block (SCB)
IKobayashi	0:c88c3b616c00	389	\brief Type definitions for the System Control Block Registers
IKobayashi	0:c88c3b616c00	390	@{
IKobayashi	0:c88c3b616c00	391	*/
IKobayashi	0:c88c3b616c00	392
IKobayashi	0:c88c3b616c00	393	/** \brief Structure type to access the System Control Block (SCB).
IKobayashi	0:c88c3b616c00	394	*/
IKobayashi	0:c88c3b616c00	395	typedef struct
IKobayashi	0:c88c3b616c00	396	{
IKobayashi	0:c88c3b616c00	397	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
IKobayashi	0:c88c3b616c00	398	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
IKobayashi	0:c88c3b616c00	399	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
IKobayashi	0:c88c3b616c00	400	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
IKobayashi	0:c88c3b616c00	401	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
IKobayashi	0:c88c3b616c00	402	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
IKobayashi	0:c88c3b616c00	403	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
IKobayashi	0:c88c3b616c00	404	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
IKobayashi	0:c88c3b616c00	405	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
IKobayashi	0:c88c3b616c00	406	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
IKobayashi	0:c88c3b616c00	407	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
IKobayashi	0:c88c3b616c00	408	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
IKobayashi	0:c88c3b616c00	409	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
IKobayashi	0:c88c3b616c00	410	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
IKobayashi	0:c88c3b616c00	411	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
IKobayashi	0:c88c3b616c00	412	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
IKobayashi	0:c88c3b616c00	413	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
IKobayashi	0:c88c3b616c00	414	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
IKobayashi	0:c88c3b616c00	415	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
IKobayashi	0:c88c3b616c00	416	uint32_t RESERVED0[5];
IKobayashi	0:c88c3b616c00	417	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
IKobayashi	0:c88c3b616c00	418	} SCB_Type;
IKobayashi	0:c88c3b616c00	419
IKobayashi	0:c88c3b616c00	420	/* SCB CPUID Register Definitions */
IKobayashi	0:c88c3b616c00	421	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
IKobayashi	0:c88c3b616c00	422	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
IKobayashi	0:c88c3b616c00	423
IKobayashi	0:c88c3b616c00	424	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
IKobayashi	0:c88c3b616c00	425	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
IKobayashi	0:c88c3b616c00	426
IKobayashi	0:c88c3b616c00	427	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
IKobayashi	0:c88c3b616c00	428	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
IKobayashi	0:c88c3b616c00	429
IKobayashi	0:c88c3b616c00	430	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
IKobayashi	0:c88c3b616c00	431	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
IKobayashi	0:c88c3b616c00	432
IKobayashi	0:c88c3b616c00	433	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
IKobayashi	0:c88c3b616c00	434	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
IKobayashi	0:c88c3b616c00	435
IKobayashi	0:c88c3b616c00	436	/* SCB Interrupt Control State Register Definitions */
IKobayashi	0:c88c3b616c00	437	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
IKobayashi	0:c88c3b616c00	438	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
IKobayashi	0:c88c3b616c00	439
IKobayashi	0:c88c3b616c00	440	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
IKobayashi	0:c88c3b616c00	441	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
IKobayashi	0:c88c3b616c00	442
IKobayashi	0:c88c3b616c00	443	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
IKobayashi	0:c88c3b616c00	444	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
IKobayashi	0:c88c3b616c00	445
IKobayashi	0:c88c3b616c00	446	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
IKobayashi	0:c88c3b616c00	447	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
IKobayashi	0:c88c3b616c00	448
IKobayashi	0:c88c3b616c00	449	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
IKobayashi	0:c88c3b616c00	450	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
IKobayashi	0:c88c3b616c00	451
IKobayashi	0:c88c3b616c00	452	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
IKobayashi	0:c88c3b616c00	453	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
IKobayashi	0:c88c3b616c00	454
IKobayashi	0:c88c3b616c00	455	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
IKobayashi	0:c88c3b616c00	456	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
IKobayashi	0:c88c3b616c00	457
IKobayashi	0:c88c3b616c00	458	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
IKobayashi	0:c88c3b616c00	459	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
IKobayashi	0:c88c3b616c00	460
IKobayashi	0:c88c3b616c00	461	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
IKobayashi	0:c88c3b616c00	462	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
IKobayashi	0:c88c3b616c00	463
IKobayashi	0:c88c3b616c00	464	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
IKobayashi	0:c88c3b616c00	465	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
IKobayashi	0:c88c3b616c00	466
IKobayashi	0:c88c3b616c00	467	/* SCB Vector Table Offset Register Definitions */
IKobayashi	0:c88c3b616c00	468	#if (__CM3_REV < 0x0201) /* core r2p1 */
IKobayashi	0:c88c3b616c00	469	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
IKobayashi	0:c88c3b616c00	470	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
IKobayashi	0:c88c3b616c00	471
IKobayashi	0:c88c3b616c00	472	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
IKobayashi	0:c88c3b616c00	473	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
IKobayashi	0:c88c3b616c00	474	#else
IKobayashi	0:c88c3b616c00	475	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
IKobayashi	0:c88c3b616c00	476	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
IKobayashi	0:c88c3b616c00	477	#endif
IKobayashi	0:c88c3b616c00	478
IKobayashi	0:c88c3b616c00	479	/* SCB Application Interrupt and Reset Control Register Definitions */
IKobayashi	0:c88c3b616c00	480	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
IKobayashi	0:c88c3b616c00	481	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
IKobayashi	0:c88c3b616c00	482
IKobayashi	0:c88c3b616c00	483	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
IKobayashi	0:c88c3b616c00	484	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
IKobayashi	0:c88c3b616c00	485
IKobayashi	0:c88c3b616c00	486	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
IKobayashi	0:c88c3b616c00	487	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
IKobayashi	0:c88c3b616c00	488
IKobayashi	0:c88c3b616c00	489	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
IKobayashi	0:c88c3b616c00	490	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
IKobayashi	0:c88c3b616c00	491
IKobayashi	0:c88c3b616c00	492	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
IKobayashi	0:c88c3b616c00	493	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
IKobayashi	0:c88c3b616c00	494
IKobayashi	0:c88c3b616c00	495	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
IKobayashi	0:c88c3b616c00	496	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
IKobayashi	0:c88c3b616c00	497
IKobayashi	0:c88c3b616c00	498	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
IKobayashi	0:c88c3b616c00	499	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
IKobayashi	0:c88c3b616c00	500
IKobayashi	0:c88c3b616c00	501	/* SCB System Control Register Definitions */
IKobayashi	0:c88c3b616c00	502	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
IKobayashi	0:c88c3b616c00	503	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
IKobayashi	0:c88c3b616c00	504
IKobayashi	0:c88c3b616c00	505	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
IKobayashi	0:c88c3b616c00	506	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
IKobayashi	0:c88c3b616c00	507
IKobayashi	0:c88c3b616c00	508	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
IKobayashi	0:c88c3b616c00	509	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
IKobayashi	0:c88c3b616c00	510
IKobayashi	0:c88c3b616c00	511	/* SCB Configuration Control Register Definitions */
IKobayashi	0:c88c3b616c00	512	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
IKobayashi	0:c88c3b616c00	513	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
IKobayashi	0:c88c3b616c00	514
IKobayashi	0:c88c3b616c00	515	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
IKobayashi	0:c88c3b616c00	516	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
IKobayashi	0:c88c3b616c00	517
IKobayashi	0:c88c3b616c00	518	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
IKobayashi	0:c88c3b616c00	519	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
IKobayashi	0:c88c3b616c00	520
IKobayashi	0:c88c3b616c00	521	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
IKobayashi	0:c88c3b616c00	522	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
IKobayashi	0:c88c3b616c00	523
IKobayashi	0:c88c3b616c00	524	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
IKobayashi	0:c88c3b616c00	525	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
IKobayashi	0:c88c3b616c00	526
IKobayashi	0:c88c3b616c00	527	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
IKobayashi	0:c88c3b616c00	528	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
IKobayashi	0:c88c3b616c00	529
IKobayashi	0:c88c3b616c00	530	/* SCB System Handler Control and State Register Definitions */
IKobayashi	0:c88c3b616c00	531	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
IKobayashi	0:c88c3b616c00	532	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
IKobayashi	0:c88c3b616c00	533
IKobayashi	0:c88c3b616c00	534	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
IKobayashi	0:c88c3b616c00	535	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
IKobayashi	0:c88c3b616c00	536
IKobayashi	0:c88c3b616c00	537	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
IKobayashi	0:c88c3b616c00	538	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
IKobayashi	0:c88c3b616c00	539
IKobayashi	0:c88c3b616c00	540	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
IKobayashi	0:c88c3b616c00	541	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
IKobayashi	0:c88c3b616c00	542
IKobayashi	0:c88c3b616c00	543	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
IKobayashi	0:c88c3b616c00	544	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
IKobayashi	0:c88c3b616c00	545
IKobayashi	0:c88c3b616c00	546	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
IKobayashi	0:c88c3b616c00	547	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
IKobayashi	0:c88c3b616c00	548
IKobayashi	0:c88c3b616c00	549	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
IKobayashi	0:c88c3b616c00	550	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
IKobayashi	0:c88c3b616c00	551
IKobayashi	0:c88c3b616c00	552	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
IKobayashi	0:c88c3b616c00	553	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
IKobayashi	0:c88c3b616c00	554
IKobayashi	0:c88c3b616c00	555	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
IKobayashi	0:c88c3b616c00	556	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
IKobayashi	0:c88c3b616c00	557
IKobayashi	0:c88c3b616c00	558	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
IKobayashi	0:c88c3b616c00	559	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
IKobayashi	0:c88c3b616c00	560
IKobayashi	0:c88c3b616c00	561	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
IKobayashi	0:c88c3b616c00	562	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
IKobayashi	0:c88c3b616c00	563
IKobayashi	0:c88c3b616c00	564	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
IKobayashi	0:c88c3b616c00	565	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
IKobayashi	0:c88c3b616c00	566
IKobayashi	0:c88c3b616c00	567	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
IKobayashi	0:c88c3b616c00	568	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
IKobayashi	0:c88c3b616c00	569
IKobayashi	0:c88c3b616c00	570	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
IKobayashi	0:c88c3b616c00	571	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
IKobayashi	0:c88c3b616c00	572
IKobayashi	0:c88c3b616c00	573	/* SCB Configurable Fault Status Registers Definitions */
IKobayashi	0:c88c3b616c00	574	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
IKobayashi	0:c88c3b616c00	575	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
IKobayashi	0:c88c3b616c00	576
IKobayashi	0:c88c3b616c00	577	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
IKobayashi	0:c88c3b616c00	578	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
IKobayashi	0:c88c3b616c00	579
IKobayashi	0:c88c3b616c00	580	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
IKobayashi	0:c88c3b616c00	581	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
IKobayashi	0:c88c3b616c00	582
IKobayashi	0:c88c3b616c00	583	/* SCB Hard Fault Status Registers Definitions */
IKobayashi	0:c88c3b616c00	584	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
IKobayashi	0:c88c3b616c00	585	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
IKobayashi	0:c88c3b616c00	586
IKobayashi	0:c88c3b616c00	587	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
IKobayashi	0:c88c3b616c00	588	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
IKobayashi	0:c88c3b616c00	589
IKobayashi	0:c88c3b616c00	590	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
IKobayashi	0:c88c3b616c00	591	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
IKobayashi	0:c88c3b616c00	592
IKobayashi	0:c88c3b616c00	593	/* SCB Debug Fault Status Register Definitions */
IKobayashi	0:c88c3b616c00	594	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
IKobayashi	0:c88c3b616c00	595	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
IKobayashi	0:c88c3b616c00	596
IKobayashi	0:c88c3b616c00	597	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
IKobayashi	0:c88c3b616c00	598	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
IKobayashi	0:c88c3b616c00	599
IKobayashi	0:c88c3b616c00	600	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
IKobayashi	0:c88c3b616c00	601	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
IKobayashi	0:c88c3b616c00	602
IKobayashi	0:c88c3b616c00	603	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
IKobayashi	0:c88c3b616c00	604	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
IKobayashi	0:c88c3b616c00	605
IKobayashi	0:c88c3b616c00	606	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
IKobayashi	0:c88c3b616c00	607	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
IKobayashi	0:c88c3b616c00	608
IKobayashi	0:c88c3b616c00	609	/@} end of group CMSIS_SCB /
IKobayashi	0:c88c3b616c00	610
IKobayashi	0:c88c3b616c00	611
IKobayashi	0:c88c3b616c00	612	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	613	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
IKobayashi	0:c88c3b616c00	614	\brief Type definitions for the System Control and ID Register not in the SCB
IKobayashi	0:c88c3b616c00	615	@{
IKobayashi	0:c88c3b616c00	616	*/
IKobayashi	0:c88c3b616c00	617
IKobayashi	0:c88c3b616c00	618	/** \brief Structure type to access the System Control and ID Register not in the SCB.
IKobayashi	0:c88c3b616c00	619	*/
IKobayashi	0:c88c3b616c00	620	typedef struct
IKobayashi	0:c88c3b616c00	621	{
IKobayashi	0:c88c3b616c00	622	uint32_t RESERVED0[1];
IKobayashi	0:c88c3b616c00	623	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
IKobayashi	0:c88c3b616c00	624	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
IKobayashi	0:c88c3b616c00	625	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
IKobayashi	0:c88c3b616c00	626	#else
IKobayashi	0:c88c3b616c00	627	uint32_t RESERVED1[1];
IKobayashi	0:c88c3b616c00	628	#endif
IKobayashi	0:c88c3b616c00	629	} SCnSCB_Type;
IKobayashi	0:c88c3b616c00	630
IKobayashi	0:c88c3b616c00	631	/* Interrupt Controller Type Register Definitions */
IKobayashi	0:c88c3b616c00	632	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
IKobayashi	0:c88c3b616c00	633	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
IKobayashi	0:c88c3b616c00	634
IKobayashi	0:c88c3b616c00	635	/* Auxiliary Control Register Definitions */
IKobayashi	0:c88c3b616c00	636
IKobayashi	0:c88c3b616c00	637	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
IKobayashi	0:c88c3b616c00	638	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
IKobayashi	0:c88c3b616c00	639
IKobayashi	0:c88c3b616c00	640	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
IKobayashi	0:c88c3b616c00	641	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
IKobayashi	0:c88c3b616c00	642
IKobayashi	0:c88c3b616c00	643	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
IKobayashi	0:c88c3b616c00	644	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
IKobayashi	0:c88c3b616c00	645
IKobayashi	0:c88c3b616c00	646	/@} end of group CMSIS_SCnotSCB /
IKobayashi	0:c88c3b616c00	647
IKobayashi	0:c88c3b616c00	648
IKobayashi	0:c88c3b616c00	649	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	650	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
IKobayashi	0:c88c3b616c00	651	\brief Type definitions for the System Timer Registers.
IKobayashi	0:c88c3b616c00	652	@{
IKobayashi	0:c88c3b616c00	653	*/
IKobayashi	0:c88c3b616c00	654
IKobayashi	0:c88c3b616c00	655	/** \brief Structure type to access the System Timer (SysTick).
IKobayashi	0:c88c3b616c00	656	*/
IKobayashi	0:c88c3b616c00	657	typedef struct
IKobayashi	0:c88c3b616c00	658	{
IKobayashi	0:c88c3b616c00	659	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
IKobayashi	0:c88c3b616c00	660	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
IKobayashi	0:c88c3b616c00	661	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
IKobayashi	0:c88c3b616c00	662	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
IKobayashi	0:c88c3b616c00	663	} SysTick_Type;
IKobayashi	0:c88c3b616c00	664
IKobayashi	0:c88c3b616c00	665	/* SysTick Control / Status Register Definitions */
IKobayashi	0:c88c3b616c00	666	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
IKobayashi	0:c88c3b616c00	667	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
IKobayashi	0:c88c3b616c00	668
IKobayashi	0:c88c3b616c00	669	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
IKobayashi	0:c88c3b616c00	670	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
IKobayashi	0:c88c3b616c00	671
IKobayashi	0:c88c3b616c00	672	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
IKobayashi	0:c88c3b616c00	673	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
IKobayashi	0:c88c3b616c00	674
IKobayashi	0:c88c3b616c00	675	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
IKobayashi	0:c88c3b616c00	676	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
IKobayashi	0:c88c3b616c00	677
IKobayashi	0:c88c3b616c00	678	/* SysTick Reload Register Definitions */
IKobayashi	0:c88c3b616c00	679	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
IKobayashi	0:c88c3b616c00	680	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
IKobayashi	0:c88c3b616c00	681
IKobayashi	0:c88c3b616c00	682	/* SysTick Current Register Definitions */
IKobayashi	0:c88c3b616c00	683	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
IKobayashi	0:c88c3b616c00	684	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
IKobayashi	0:c88c3b616c00	685
IKobayashi	0:c88c3b616c00	686	/* SysTick Calibration Register Definitions */
IKobayashi	0:c88c3b616c00	687	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
IKobayashi	0:c88c3b616c00	688	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
IKobayashi	0:c88c3b616c00	689
IKobayashi	0:c88c3b616c00	690	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
IKobayashi	0:c88c3b616c00	691	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
IKobayashi	0:c88c3b616c00	692
IKobayashi	0:c88c3b616c00	693	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
IKobayashi	0:c88c3b616c00	694	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
IKobayashi	0:c88c3b616c00	695
IKobayashi	0:c88c3b616c00	696	/@} end of group CMSIS_SysTick /
IKobayashi	0:c88c3b616c00	697
IKobayashi	0:c88c3b616c00	698
IKobayashi	0:c88c3b616c00	699	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	700	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
IKobayashi	0:c88c3b616c00	701	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
IKobayashi	0:c88c3b616c00	702	@{
IKobayashi	0:c88c3b616c00	703	*/
IKobayashi	0:c88c3b616c00	704
IKobayashi	0:c88c3b616c00	705	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
IKobayashi	0:c88c3b616c00	706	*/
IKobayashi	0:c88c3b616c00	707	typedef struct
IKobayashi	0:c88c3b616c00	708	{
IKobayashi	0:c88c3b616c00	709	__O union
IKobayashi	0:c88c3b616c00	710	{
IKobayashi	0:c88c3b616c00	711	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
IKobayashi	0:c88c3b616c00	712	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
IKobayashi	0:c88c3b616c00	713	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
IKobayashi	0:c88c3b616c00	714	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
IKobayashi	0:c88c3b616c00	715	uint32_t RESERVED0[864];
IKobayashi	0:c88c3b616c00	716	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
IKobayashi	0:c88c3b616c00	717	uint32_t RESERVED1[15];
IKobayashi	0:c88c3b616c00	718	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
IKobayashi	0:c88c3b616c00	719	uint32_t RESERVED2[15];
IKobayashi	0:c88c3b616c00	720	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
IKobayashi	0:c88c3b616c00	721	uint32_t RESERVED3[29];
IKobayashi	0:c88c3b616c00	722	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
IKobayashi	0:c88c3b616c00	723	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
IKobayashi	0:c88c3b616c00	724	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
IKobayashi	0:c88c3b616c00	725	uint32_t RESERVED4[43];
IKobayashi	0:c88c3b616c00	726	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
IKobayashi	0:c88c3b616c00	727	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
IKobayashi	0:c88c3b616c00	728	uint32_t RESERVED5[6];
IKobayashi	0:c88c3b616c00	729	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
IKobayashi	0:c88c3b616c00	730	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
IKobayashi	0:c88c3b616c00	731	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
IKobayashi	0:c88c3b616c00	732	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
IKobayashi	0:c88c3b616c00	733	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
IKobayashi	0:c88c3b616c00	734	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
IKobayashi	0:c88c3b616c00	735	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
IKobayashi	0:c88c3b616c00	736	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
IKobayashi	0:c88c3b616c00	737	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
IKobayashi	0:c88c3b616c00	738	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
IKobayashi	0:c88c3b616c00	739	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
IKobayashi	0:c88c3b616c00	740	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
IKobayashi	0:c88c3b616c00	741	} ITM_Type;
IKobayashi	0:c88c3b616c00	742
IKobayashi	0:c88c3b616c00	743	/* ITM Trace Privilege Register Definitions */
IKobayashi	0:c88c3b616c00	744	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
IKobayashi	0:c88c3b616c00	745	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
IKobayashi	0:c88c3b616c00	746
IKobayashi	0:c88c3b616c00	747	/* ITM Trace Control Register Definitions */
IKobayashi	0:c88c3b616c00	748	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
IKobayashi	0:c88c3b616c00	749	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
IKobayashi	0:c88c3b616c00	750
IKobayashi	0:c88c3b616c00	751	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
IKobayashi	0:c88c3b616c00	752	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
IKobayashi	0:c88c3b616c00	753
IKobayashi	0:c88c3b616c00	754	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
IKobayashi	0:c88c3b616c00	755	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
IKobayashi	0:c88c3b616c00	756
IKobayashi	0:c88c3b616c00	757	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
IKobayashi	0:c88c3b616c00	758	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
IKobayashi	0:c88c3b616c00	759
IKobayashi	0:c88c3b616c00	760	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
IKobayashi	0:c88c3b616c00	761	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
IKobayashi	0:c88c3b616c00	762
IKobayashi	0:c88c3b616c00	763	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
IKobayashi	0:c88c3b616c00	764	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
IKobayashi	0:c88c3b616c00	765
IKobayashi	0:c88c3b616c00	766	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
IKobayashi	0:c88c3b616c00	767	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
IKobayashi	0:c88c3b616c00	768
IKobayashi	0:c88c3b616c00	769	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
IKobayashi	0:c88c3b616c00	770	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
IKobayashi	0:c88c3b616c00	771
IKobayashi	0:c88c3b616c00	772	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
IKobayashi	0:c88c3b616c00	773	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
IKobayashi	0:c88c3b616c00	774
IKobayashi	0:c88c3b616c00	775	/* ITM Integration Write Register Definitions */
IKobayashi	0:c88c3b616c00	776	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
IKobayashi	0:c88c3b616c00	777	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
IKobayashi	0:c88c3b616c00	778
IKobayashi	0:c88c3b616c00	779	/* ITM Integration Read Register Definitions */
IKobayashi	0:c88c3b616c00	780	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
IKobayashi	0:c88c3b616c00	781	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
IKobayashi	0:c88c3b616c00	782
IKobayashi	0:c88c3b616c00	783	/* ITM Integration Mode Control Register Definitions */
IKobayashi	0:c88c3b616c00	784	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
IKobayashi	0:c88c3b616c00	785	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
IKobayashi	0:c88c3b616c00	786
IKobayashi	0:c88c3b616c00	787	/* ITM Lock Status Register Definitions */
IKobayashi	0:c88c3b616c00	788	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
IKobayashi	0:c88c3b616c00	789	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
IKobayashi	0:c88c3b616c00	790
IKobayashi	0:c88c3b616c00	791	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
IKobayashi	0:c88c3b616c00	792	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
IKobayashi	0:c88c3b616c00	793
IKobayashi	0:c88c3b616c00	794	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
IKobayashi	0:c88c3b616c00	795	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
IKobayashi	0:c88c3b616c00	796
IKobayashi	0:c88c3b616c00	797	/@}/ /* end of group CMSIS_ITM */
IKobayashi	0:c88c3b616c00	798
IKobayashi	0:c88c3b616c00	799
IKobayashi	0:c88c3b616c00	800	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	801	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
IKobayashi	0:c88c3b616c00	802	\brief Type definitions for the Data Watchpoint and Trace (DWT)
IKobayashi	0:c88c3b616c00	803	@{
IKobayashi	0:c88c3b616c00	804	*/
IKobayashi	0:c88c3b616c00	805
IKobayashi	0:c88c3b616c00	806	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
IKobayashi	0:c88c3b616c00	807	*/
IKobayashi	0:c88c3b616c00	808	typedef struct
IKobayashi	0:c88c3b616c00	809	{
IKobayashi	0:c88c3b616c00	810	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
IKobayashi	0:c88c3b616c00	811	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
IKobayashi	0:c88c3b616c00	812	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
IKobayashi	0:c88c3b616c00	813	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
IKobayashi	0:c88c3b616c00	814	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
IKobayashi	0:c88c3b616c00	815	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
IKobayashi	0:c88c3b616c00	816	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
IKobayashi	0:c88c3b616c00	817	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
IKobayashi	0:c88c3b616c00	818	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
IKobayashi	0:c88c3b616c00	819	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
IKobayashi	0:c88c3b616c00	820	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
IKobayashi	0:c88c3b616c00	821	uint32_t RESERVED0[1];
IKobayashi	0:c88c3b616c00	822	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
IKobayashi	0:c88c3b616c00	823	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
IKobayashi	0:c88c3b616c00	824	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
IKobayashi	0:c88c3b616c00	825	uint32_t RESERVED1[1];
IKobayashi	0:c88c3b616c00	826	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
IKobayashi	0:c88c3b616c00	827	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
IKobayashi	0:c88c3b616c00	828	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
IKobayashi	0:c88c3b616c00	829	uint32_t RESERVED2[1];
IKobayashi	0:c88c3b616c00	830	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
IKobayashi	0:c88c3b616c00	831	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
IKobayashi	0:c88c3b616c00	832	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
IKobayashi	0:c88c3b616c00	833	} DWT_Type;
IKobayashi	0:c88c3b616c00	834
IKobayashi	0:c88c3b616c00	835	/* DWT Control Register Definitions */
IKobayashi	0:c88c3b616c00	836	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
IKobayashi	0:c88c3b616c00	837	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
IKobayashi	0:c88c3b616c00	838
IKobayashi	0:c88c3b616c00	839	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
IKobayashi	0:c88c3b616c00	840	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
IKobayashi	0:c88c3b616c00	841
IKobayashi	0:c88c3b616c00	842	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
IKobayashi	0:c88c3b616c00	843	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
IKobayashi	0:c88c3b616c00	844
IKobayashi	0:c88c3b616c00	845	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
IKobayashi	0:c88c3b616c00	846	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
IKobayashi	0:c88c3b616c00	847
IKobayashi	0:c88c3b616c00	848	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
IKobayashi	0:c88c3b616c00	849	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
IKobayashi	0:c88c3b616c00	850
IKobayashi	0:c88c3b616c00	851	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
IKobayashi	0:c88c3b616c00	852	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
IKobayashi	0:c88c3b616c00	853
IKobayashi	0:c88c3b616c00	854	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
IKobayashi	0:c88c3b616c00	855	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
IKobayashi	0:c88c3b616c00	856
IKobayashi	0:c88c3b616c00	857	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
IKobayashi	0:c88c3b616c00	858	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
IKobayashi	0:c88c3b616c00	859
IKobayashi	0:c88c3b616c00	860	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
IKobayashi	0:c88c3b616c00	861	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
IKobayashi	0:c88c3b616c00	862
IKobayashi	0:c88c3b616c00	863	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
IKobayashi	0:c88c3b616c00	864	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
IKobayashi	0:c88c3b616c00	865
IKobayashi	0:c88c3b616c00	866	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
IKobayashi	0:c88c3b616c00	867	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
IKobayashi	0:c88c3b616c00	868
IKobayashi	0:c88c3b616c00	869	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
IKobayashi	0:c88c3b616c00	870	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
IKobayashi	0:c88c3b616c00	871
IKobayashi	0:c88c3b616c00	872	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
IKobayashi	0:c88c3b616c00	873	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
IKobayashi	0:c88c3b616c00	874
IKobayashi	0:c88c3b616c00	875	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
IKobayashi	0:c88c3b616c00	876	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
IKobayashi	0:c88c3b616c00	877
IKobayashi	0:c88c3b616c00	878	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
IKobayashi	0:c88c3b616c00	879	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
IKobayashi	0:c88c3b616c00	880
IKobayashi	0:c88c3b616c00	881	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
IKobayashi	0:c88c3b616c00	882	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
IKobayashi	0:c88c3b616c00	883
IKobayashi	0:c88c3b616c00	884	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
IKobayashi	0:c88c3b616c00	885	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
IKobayashi	0:c88c3b616c00	886
IKobayashi	0:c88c3b616c00	887	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
IKobayashi	0:c88c3b616c00	888	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
IKobayashi	0:c88c3b616c00	889
IKobayashi	0:c88c3b616c00	890	/* DWT CPI Count Register Definitions */
IKobayashi	0:c88c3b616c00	891	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
IKobayashi	0:c88c3b616c00	892	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
IKobayashi	0:c88c3b616c00	893
IKobayashi	0:c88c3b616c00	894	/* DWT Exception Overhead Count Register Definitions */
IKobayashi	0:c88c3b616c00	895	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
IKobayashi	0:c88c3b616c00	896	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
IKobayashi	0:c88c3b616c00	897
IKobayashi	0:c88c3b616c00	898	/* DWT Sleep Count Register Definitions */
IKobayashi	0:c88c3b616c00	899	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
IKobayashi	0:c88c3b616c00	900	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
IKobayashi	0:c88c3b616c00	901
IKobayashi	0:c88c3b616c00	902	/* DWT LSU Count Register Definitions */
IKobayashi	0:c88c3b616c00	903	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
IKobayashi	0:c88c3b616c00	904	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
IKobayashi	0:c88c3b616c00	905
IKobayashi	0:c88c3b616c00	906	/* DWT Folded-instruction Count Register Definitions */
IKobayashi	0:c88c3b616c00	907	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
IKobayashi	0:c88c3b616c00	908	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
IKobayashi	0:c88c3b616c00	909
IKobayashi	0:c88c3b616c00	910	/* DWT Comparator Mask Register Definitions */
IKobayashi	0:c88c3b616c00	911	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
IKobayashi	0:c88c3b616c00	912	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
IKobayashi	0:c88c3b616c00	913
IKobayashi	0:c88c3b616c00	914	/* DWT Comparator Function Register Definitions */
IKobayashi	0:c88c3b616c00	915	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
IKobayashi	0:c88c3b616c00	916	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
IKobayashi	0:c88c3b616c00	917
IKobayashi	0:c88c3b616c00	918	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
IKobayashi	0:c88c3b616c00	919	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
IKobayashi	0:c88c3b616c00	920
IKobayashi	0:c88c3b616c00	921	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
IKobayashi	0:c88c3b616c00	922	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
IKobayashi	0:c88c3b616c00	923
IKobayashi	0:c88c3b616c00	924	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
IKobayashi	0:c88c3b616c00	925	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
IKobayashi	0:c88c3b616c00	926
IKobayashi	0:c88c3b616c00	927	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
IKobayashi	0:c88c3b616c00	928	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
IKobayashi	0:c88c3b616c00	929
IKobayashi	0:c88c3b616c00	930	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
IKobayashi	0:c88c3b616c00	931	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
IKobayashi	0:c88c3b616c00	932
IKobayashi	0:c88c3b616c00	933	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
IKobayashi	0:c88c3b616c00	934	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
IKobayashi	0:c88c3b616c00	935
IKobayashi	0:c88c3b616c00	936	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
IKobayashi	0:c88c3b616c00	937	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
IKobayashi	0:c88c3b616c00	938
IKobayashi	0:c88c3b616c00	939	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
IKobayashi	0:c88c3b616c00	940	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
IKobayashi	0:c88c3b616c00	941
IKobayashi	0:c88c3b616c00	942	/@}/ /* end of group CMSIS_DWT */
IKobayashi	0:c88c3b616c00	943
IKobayashi	0:c88c3b616c00	944
IKobayashi	0:c88c3b616c00	945	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	946	\defgroup CMSIS_TPI Trace Port Interface (TPI)
IKobayashi	0:c88c3b616c00	947	\brief Type definitions for the Trace Port Interface (TPI)
IKobayashi	0:c88c3b616c00	948	@{
IKobayashi	0:c88c3b616c00	949	*/
IKobayashi	0:c88c3b616c00	950
IKobayashi	0:c88c3b616c00	951	/** \brief Structure type to access the Trace Port Interface Register (TPI).
IKobayashi	0:c88c3b616c00	952	*/
IKobayashi	0:c88c3b616c00	953	typedef struct
IKobayashi	0:c88c3b616c00	954	{
IKobayashi	0:c88c3b616c00	955	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
IKobayashi	0:c88c3b616c00	956	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
IKobayashi	0:c88c3b616c00	957	uint32_t RESERVED0[2];
IKobayashi	0:c88c3b616c00	958	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
IKobayashi	0:c88c3b616c00	959	uint32_t RESERVED1[55];
IKobayashi	0:c88c3b616c00	960	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
IKobayashi	0:c88c3b616c00	961	uint32_t RESERVED2[131];
IKobayashi	0:c88c3b616c00	962	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
IKobayashi	0:c88c3b616c00	963	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
IKobayashi	0:c88c3b616c00	964	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
IKobayashi	0:c88c3b616c00	965	uint32_t RESERVED3[759];
IKobayashi	0:c88c3b616c00	966	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
IKobayashi	0:c88c3b616c00	967	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
IKobayashi	0:c88c3b616c00	968	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
IKobayashi	0:c88c3b616c00	969	uint32_t RESERVED4[1];
IKobayashi	0:c88c3b616c00	970	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
IKobayashi	0:c88c3b616c00	971	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
IKobayashi	0:c88c3b616c00	972	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
IKobayashi	0:c88c3b616c00	973	uint32_t RESERVED5[39];
IKobayashi	0:c88c3b616c00	974	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
IKobayashi	0:c88c3b616c00	975	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
IKobayashi	0:c88c3b616c00	976	uint32_t RESERVED7[8];
IKobayashi	0:c88c3b616c00	977	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
IKobayashi	0:c88c3b616c00	978	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
IKobayashi	0:c88c3b616c00	979	} TPI_Type;
IKobayashi	0:c88c3b616c00	980
IKobayashi	0:c88c3b616c00	981	/* TPI Asynchronous Clock Prescaler Register Definitions */
IKobayashi	0:c88c3b616c00	982	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
IKobayashi	0:c88c3b616c00	983	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
IKobayashi	0:c88c3b616c00	984
IKobayashi	0:c88c3b616c00	985	/* TPI Selected Pin Protocol Register Definitions */
IKobayashi	0:c88c3b616c00	986	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
IKobayashi	0:c88c3b616c00	987	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
IKobayashi	0:c88c3b616c00	988
IKobayashi	0:c88c3b616c00	989	/* TPI Formatter and Flush Status Register Definitions */
IKobayashi	0:c88c3b616c00	990	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
IKobayashi	0:c88c3b616c00	991	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
IKobayashi	0:c88c3b616c00	992
IKobayashi	0:c88c3b616c00	993	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
IKobayashi	0:c88c3b616c00	994	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
IKobayashi	0:c88c3b616c00	995
IKobayashi	0:c88c3b616c00	996	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
IKobayashi	0:c88c3b616c00	997	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
IKobayashi	0:c88c3b616c00	998
IKobayashi	0:c88c3b616c00	999	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
IKobayashi	0:c88c3b616c00	1000	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
IKobayashi	0:c88c3b616c00	1001
IKobayashi	0:c88c3b616c00	1002	/* TPI Formatter and Flush Control Register Definitions */
IKobayashi	0:c88c3b616c00	1003	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
IKobayashi	0:c88c3b616c00	1004	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
IKobayashi	0:c88c3b616c00	1005
IKobayashi	0:c88c3b616c00	1006	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
IKobayashi	0:c88c3b616c00	1007	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
IKobayashi	0:c88c3b616c00	1008
IKobayashi	0:c88c3b616c00	1009	/* TPI TRIGGER Register Definitions */
IKobayashi	0:c88c3b616c00	1010	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
IKobayashi	0:c88c3b616c00	1011	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
IKobayashi	0:c88c3b616c00	1012
IKobayashi	0:c88c3b616c00	1013	/* TPI Integration ETM Data Register Definitions (FIFO0) */
IKobayashi	0:c88c3b616c00	1014	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
IKobayashi	0:c88c3b616c00	1015	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
IKobayashi	0:c88c3b616c00	1016
IKobayashi	0:c88c3b616c00	1017	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
IKobayashi	0:c88c3b616c00	1018	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
IKobayashi	0:c88c3b616c00	1019
IKobayashi	0:c88c3b616c00	1020	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
IKobayashi	0:c88c3b616c00	1021	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
IKobayashi	0:c88c3b616c00	1022
IKobayashi	0:c88c3b616c00	1023	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
IKobayashi	0:c88c3b616c00	1024	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
IKobayashi	0:c88c3b616c00	1025
IKobayashi	0:c88c3b616c00	1026	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
IKobayashi	0:c88c3b616c00	1027	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
IKobayashi	0:c88c3b616c00	1028
IKobayashi	0:c88c3b616c00	1029	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
IKobayashi	0:c88c3b616c00	1030	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
IKobayashi	0:c88c3b616c00	1031
IKobayashi	0:c88c3b616c00	1032	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
IKobayashi	0:c88c3b616c00	1033	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
IKobayashi	0:c88c3b616c00	1034
IKobayashi	0:c88c3b616c00	1035	/* TPI ITATBCTR2 Register Definitions */
IKobayashi	0:c88c3b616c00	1036	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
IKobayashi	0:c88c3b616c00	1037	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
IKobayashi	0:c88c3b616c00	1038
IKobayashi	0:c88c3b616c00	1039	/* TPI Integration ITM Data Register Definitions (FIFO1) */
IKobayashi	0:c88c3b616c00	1040	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
IKobayashi	0:c88c3b616c00	1041	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
IKobayashi	0:c88c3b616c00	1042
IKobayashi	0:c88c3b616c00	1043	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
IKobayashi	0:c88c3b616c00	1044	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
IKobayashi	0:c88c3b616c00	1045
IKobayashi	0:c88c3b616c00	1046	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
IKobayashi	0:c88c3b616c00	1047	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
IKobayashi	0:c88c3b616c00	1048
IKobayashi	0:c88c3b616c00	1049	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
IKobayashi	0:c88c3b616c00	1050	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
IKobayashi	0:c88c3b616c00	1051
IKobayashi	0:c88c3b616c00	1052	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
IKobayashi	0:c88c3b616c00	1053	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
IKobayashi	0:c88c3b616c00	1054
IKobayashi	0:c88c3b616c00	1055	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
IKobayashi	0:c88c3b616c00	1056	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
IKobayashi	0:c88c3b616c00	1057
IKobayashi	0:c88c3b616c00	1058	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
IKobayashi	0:c88c3b616c00	1059	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
IKobayashi	0:c88c3b616c00	1060
IKobayashi	0:c88c3b616c00	1061	/* TPI ITATBCTR0 Register Definitions */
IKobayashi	0:c88c3b616c00	1062	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
IKobayashi	0:c88c3b616c00	1063	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
IKobayashi	0:c88c3b616c00	1064
IKobayashi	0:c88c3b616c00	1065	/* TPI Integration Mode Control Register Definitions */
IKobayashi	0:c88c3b616c00	1066	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
IKobayashi	0:c88c3b616c00	1067	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
IKobayashi	0:c88c3b616c00	1068
IKobayashi	0:c88c3b616c00	1069	/* TPI DEVID Register Definitions */
IKobayashi	0:c88c3b616c00	1070	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
IKobayashi	0:c88c3b616c00	1071	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
IKobayashi	0:c88c3b616c00	1072
IKobayashi	0:c88c3b616c00	1073	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
IKobayashi	0:c88c3b616c00	1074	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
IKobayashi	0:c88c3b616c00	1075
IKobayashi	0:c88c3b616c00	1076	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
IKobayashi	0:c88c3b616c00	1077	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
IKobayashi	0:c88c3b616c00	1078
IKobayashi	0:c88c3b616c00	1079	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
IKobayashi	0:c88c3b616c00	1080	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
IKobayashi	0:c88c3b616c00	1081
IKobayashi	0:c88c3b616c00	1082	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
IKobayashi	0:c88c3b616c00	1083	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
IKobayashi	0:c88c3b616c00	1084
IKobayashi	0:c88c3b616c00	1085	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
IKobayashi	0:c88c3b616c00	1086	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
IKobayashi	0:c88c3b616c00	1087
IKobayashi	0:c88c3b616c00	1088	/* TPI DEVTYPE Register Definitions */
IKobayashi	0:c88c3b616c00	1089	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
IKobayashi	0:c88c3b616c00	1090	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
IKobayashi	0:c88c3b616c00	1091
IKobayashi	0:c88c3b616c00	1092	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
IKobayashi	0:c88c3b616c00	1093	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
IKobayashi	0:c88c3b616c00	1094
IKobayashi	0:c88c3b616c00	1095	/@}/ /* end of group CMSIS_TPI */
IKobayashi	0:c88c3b616c00	1096
IKobayashi	0:c88c3b616c00	1097
IKobayashi	0:c88c3b616c00	1098	#if (__MPU_PRESENT == 1)
IKobayashi	0:c88c3b616c00	1099	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	1100	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
IKobayashi	0:c88c3b616c00	1101	\brief Type definitions for the Memory Protection Unit (MPU)
IKobayashi	0:c88c3b616c00	1102	@{
IKobayashi	0:c88c3b616c00	1103	*/
IKobayashi	0:c88c3b616c00	1104
IKobayashi	0:c88c3b616c00	1105	/** \brief Structure type to access the Memory Protection Unit (MPU).
IKobayashi	0:c88c3b616c00	1106	*/
IKobayashi	0:c88c3b616c00	1107	typedef struct
IKobayashi	0:c88c3b616c00	1108	{
IKobayashi	0:c88c3b616c00	1109	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
IKobayashi	0:c88c3b616c00	1110	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
IKobayashi	0:c88c3b616c00	1111	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
IKobayashi	0:c88c3b616c00	1112	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
IKobayashi	0:c88c3b616c00	1113	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
IKobayashi	0:c88c3b616c00	1114	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
IKobayashi	0:c88c3b616c00	1115	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
IKobayashi	0:c88c3b616c00	1116	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
IKobayashi	0:c88c3b616c00	1117	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
IKobayashi	0:c88c3b616c00	1118	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
IKobayashi	0:c88c3b616c00	1119	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
IKobayashi	0:c88c3b616c00	1120	} MPU_Type;
IKobayashi	0:c88c3b616c00	1121
IKobayashi	0:c88c3b616c00	1122	/* MPU Type Register */
IKobayashi	0:c88c3b616c00	1123	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
IKobayashi	0:c88c3b616c00	1124	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
IKobayashi	0:c88c3b616c00	1125
IKobayashi	0:c88c3b616c00	1126	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
IKobayashi	0:c88c3b616c00	1127	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
IKobayashi	0:c88c3b616c00	1128
IKobayashi	0:c88c3b616c00	1129	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
IKobayashi	0:c88c3b616c00	1130	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
IKobayashi	0:c88c3b616c00	1131
IKobayashi	0:c88c3b616c00	1132	/* MPU Control Register */
IKobayashi	0:c88c3b616c00	1133	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
IKobayashi	0:c88c3b616c00	1134	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
IKobayashi	0:c88c3b616c00	1135
IKobayashi	0:c88c3b616c00	1136	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
IKobayashi	0:c88c3b616c00	1137	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
IKobayashi	0:c88c3b616c00	1138
IKobayashi	0:c88c3b616c00	1139	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
IKobayashi	0:c88c3b616c00	1140	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
IKobayashi	0:c88c3b616c00	1141
IKobayashi	0:c88c3b616c00	1142	/* MPU Region Number Register */
IKobayashi	0:c88c3b616c00	1143	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
IKobayashi	0:c88c3b616c00	1144	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
IKobayashi	0:c88c3b616c00	1145
IKobayashi	0:c88c3b616c00	1146	/* MPU Region Base Address Register */
IKobayashi	0:c88c3b616c00	1147	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
IKobayashi	0:c88c3b616c00	1148	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
IKobayashi	0:c88c3b616c00	1149
IKobayashi	0:c88c3b616c00	1150	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
IKobayashi	0:c88c3b616c00	1151	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
IKobayashi	0:c88c3b616c00	1152
IKobayashi	0:c88c3b616c00	1153	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
IKobayashi	0:c88c3b616c00	1154	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
IKobayashi	0:c88c3b616c00	1155
IKobayashi	0:c88c3b616c00	1156	/* MPU Region Attribute and Size Register */
IKobayashi	0:c88c3b616c00	1157	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
IKobayashi	0:c88c3b616c00	1158	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
IKobayashi	0:c88c3b616c00	1159
IKobayashi	0:c88c3b616c00	1160	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
IKobayashi	0:c88c3b616c00	1161	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
IKobayashi	0:c88c3b616c00	1162
IKobayashi	0:c88c3b616c00	1163	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
IKobayashi	0:c88c3b616c00	1164	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
IKobayashi	0:c88c3b616c00	1165
IKobayashi	0:c88c3b616c00	1166	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
IKobayashi	0:c88c3b616c00	1167	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
IKobayashi	0:c88c3b616c00	1168
IKobayashi	0:c88c3b616c00	1169	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
IKobayashi	0:c88c3b616c00	1170	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
IKobayashi	0:c88c3b616c00	1171
IKobayashi	0:c88c3b616c00	1172	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
IKobayashi	0:c88c3b616c00	1173	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
IKobayashi	0:c88c3b616c00	1174
IKobayashi	0:c88c3b616c00	1175	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
IKobayashi	0:c88c3b616c00	1176	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
IKobayashi	0:c88c3b616c00	1177
IKobayashi	0:c88c3b616c00	1178	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
IKobayashi	0:c88c3b616c00	1179	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
IKobayashi	0:c88c3b616c00	1180
IKobayashi	0:c88c3b616c00	1181	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
IKobayashi	0:c88c3b616c00	1182	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
IKobayashi	0:c88c3b616c00	1183
IKobayashi	0:c88c3b616c00	1184	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
IKobayashi	0:c88c3b616c00	1185	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
IKobayashi	0:c88c3b616c00	1186
IKobayashi	0:c88c3b616c00	1187	/@} end of group CMSIS_MPU /
IKobayashi	0:c88c3b616c00	1188	#endif
IKobayashi	0:c88c3b616c00	1189
IKobayashi	0:c88c3b616c00	1190
IKobayashi	0:c88c3b616c00	1191	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	1192	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
IKobayashi	0:c88c3b616c00	1193	\brief Type definitions for the Core Debug Registers
IKobayashi	0:c88c3b616c00	1194	@{
IKobayashi	0:c88c3b616c00	1195	*/
IKobayashi	0:c88c3b616c00	1196
IKobayashi	0:c88c3b616c00	1197	/** \brief Structure type to access the Core Debug Register (CoreDebug).
IKobayashi	0:c88c3b616c00	1198	*/
IKobayashi	0:c88c3b616c00	1199	typedef struct
IKobayashi	0:c88c3b616c00	1200	{
IKobayashi	0:c88c3b616c00	1201	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
IKobayashi	0:c88c3b616c00	1202	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
IKobayashi	0:c88c3b616c00	1203	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
IKobayashi	0:c88c3b616c00	1204	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
IKobayashi	0:c88c3b616c00	1205	} CoreDebug_Type;
IKobayashi	0:c88c3b616c00	1206
IKobayashi	0:c88c3b616c00	1207	/* Debug Halting Control and Status Register */
IKobayashi	0:c88c3b616c00	1208	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
IKobayashi	0:c88c3b616c00	1209	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
IKobayashi	0:c88c3b616c00	1210
IKobayashi	0:c88c3b616c00	1211	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
IKobayashi	0:c88c3b616c00	1212	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
IKobayashi	0:c88c3b616c00	1213
IKobayashi	0:c88c3b616c00	1214	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
IKobayashi	0:c88c3b616c00	1215	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
IKobayashi	0:c88c3b616c00	1216
IKobayashi	0:c88c3b616c00	1217	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
IKobayashi	0:c88c3b616c00	1218	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
IKobayashi	0:c88c3b616c00	1219
IKobayashi	0:c88c3b616c00	1220	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
IKobayashi	0:c88c3b616c00	1221	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
IKobayashi	0:c88c3b616c00	1222
IKobayashi	0:c88c3b616c00	1223	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
IKobayashi	0:c88c3b616c00	1224	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
IKobayashi	0:c88c3b616c00	1225
IKobayashi	0:c88c3b616c00	1226	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
IKobayashi	0:c88c3b616c00	1227	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
IKobayashi	0:c88c3b616c00	1228
IKobayashi	0:c88c3b616c00	1229	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
IKobayashi	0:c88c3b616c00	1230	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
IKobayashi	0:c88c3b616c00	1231
IKobayashi	0:c88c3b616c00	1232	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
IKobayashi	0:c88c3b616c00	1233	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
IKobayashi	0:c88c3b616c00	1234
IKobayashi	0:c88c3b616c00	1235	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
IKobayashi	0:c88c3b616c00	1236	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
IKobayashi	0:c88c3b616c00	1237
IKobayashi	0:c88c3b616c00	1238	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
IKobayashi	0:c88c3b616c00	1239	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
IKobayashi	0:c88c3b616c00	1240
IKobayashi	0:c88c3b616c00	1241	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
IKobayashi	0:c88c3b616c00	1242	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
IKobayashi	0:c88c3b616c00	1243
IKobayashi	0:c88c3b616c00	1244	/* Debug Core Register Selector Register */
IKobayashi	0:c88c3b616c00	1245	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
IKobayashi	0:c88c3b616c00	1246	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
IKobayashi	0:c88c3b616c00	1247
IKobayashi	0:c88c3b616c00	1248	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
IKobayashi	0:c88c3b616c00	1249	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
IKobayashi	0:c88c3b616c00	1250
IKobayashi	0:c88c3b616c00	1251	/* Debug Exception and Monitor Control Register */
IKobayashi	0:c88c3b616c00	1252	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
IKobayashi	0:c88c3b616c00	1253	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
IKobayashi	0:c88c3b616c00	1254
IKobayashi	0:c88c3b616c00	1255	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
IKobayashi	0:c88c3b616c00	1256	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
IKobayashi	0:c88c3b616c00	1257
IKobayashi	0:c88c3b616c00	1258	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
IKobayashi	0:c88c3b616c00	1259	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
IKobayashi	0:c88c3b616c00	1260
IKobayashi	0:c88c3b616c00	1261	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
IKobayashi	0:c88c3b616c00	1262	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
IKobayashi	0:c88c3b616c00	1263
IKobayashi	0:c88c3b616c00	1264	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
IKobayashi	0:c88c3b616c00	1265	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
IKobayashi	0:c88c3b616c00	1266
IKobayashi	0:c88c3b616c00	1267	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
IKobayashi	0:c88c3b616c00	1268	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
IKobayashi	0:c88c3b616c00	1269
IKobayashi	0:c88c3b616c00	1270	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
IKobayashi	0:c88c3b616c00	1271	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
IKobayashi	0:c88c3b616c00	1272
IKobayashi	0:c88c3b616c00	1273	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
IKobayashi	0:c88c3b616c00	1274	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
IKobayashi	0:c88c3b616c00	1275
IKobayashi	0:c88c3b616c00	1276	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
IKobayashi	0:c88c3b616c00	1277	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
IKobayashi	0:c88c3b616c00	1278
IKobayashi	0:c88c3b616c00	1279	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
IKobayashi	0:c88c3b616c00	1280	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
IKobayashi	0:c88c3b616c00	1281
IKobayashi	0:c88c3b616c00	1282	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
IKobayashi	0:c88c3b616c00	1283	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
IKobayashi	0:c88c3b616c00	1284
IKobayashi	0:c88c3b616c00	1285	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
IKobayashi	0:c88c3b616c00	1286	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
IKobayashi	0:c88c3b616c00	1287
IKobayashi	0:c88c3b616c00	1288	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
IKobayashi	0:c88c3b616c00	1289	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
IKobayashi	0:c88c3b616c00	1290
IKobayashi	0:c88c3b616c00	1291	/@} end of group CMSIS_CoreDebug /
IKobayashi	0:c88c3b616c00	1292
IKobayashi	0:c88c3b616c00	1293
IKobayashi	0:c88c3b616c00	1294	/** \ingroup CMSIS_core_register
IKobayashi	0:c88c3b616c00	1295	\defgroup CMSIS_core_base Core Definitions
IKobayashi	0:c88c3b616c00	1296	\brief Definitions for base addresses, unions, and structures.
IKobayashi	0:c88c3b616c00	1297	@{
IKobayashi	0:c88c3b616c00	1298	*/
IKobayashi	0:c88c3b616c00	1299
IKobayashi	0:c88c3b616c00	1300	/* Memory mapping of Cortex-M3 Hardware */
IKobayashi	0:c88c3b616c00	1301	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
IKobayashi	0:c88c3b616c00	1302	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
IKobayashi	0:c88c3b616c00	1303	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
IKobayashi	0:c88c3b616c00	1304	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
IKobayashi	0:c88c3b616c00	1305	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
IKobayashi	0:c88c3b616c00	1306	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
IKobayashi	0:c88c3b616c00	1307	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
IKobayashi	0:c88c3b616c00	1308	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
IKobayashi	0:c88c3b616c00	1309
IKobayashi	0:c88c3b616c00	1310	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
IKobayashi	0:c88c3b616c00	1311	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
IKobayashi	0:c88c3b616c00	1312	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
IKobayashi	0:c88c3b616c00	1313	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
IKobayashi	0:c88c3b616c00	1314	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
IKobayashi	0:c88c3b616c00	1315	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
IKobayashi	0:c88c3b616c00	1316	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
IKobayashi	0:c88c3b616c00	1317	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
IKobayashi	0:c88c3b616c00	1318
IKobayashi	0:c88c3b616c00	1319	#if (__MPU_PRESENT == 1)
IKobayashi	0:c88c3b616c00	1320	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
IKobayashi	0:c88c3b616c00	1321	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
IKobayashi	0:c88c3b616c00	1322	#endif
IKobayashi	0:c88c3b616c00	1323
IKobayashi	0:c88c3b616c00	1324	/@} /
IKobayashi	0:c88c3b616c00	1325
IKobayashi	0:c88c3b616c00	1326
IKobayashi	0:c88c3b616c00	1327
IKobayashi	0:c88c3b616c00	1328	/*******************************************************************************
IKobayashi	0:c88c3b616c00	1329	* Hardware Abstraction Layer
IKobayashi	0:c88c3b616c00	1330	Core Function Interface contains:
IKobayashi	0:c88c3b616c00	1331	- Core NVIC Functions
IKobayashi	0:c88c3b616c00	1332	- Core SysTick Functions
IKobayashi	0:c88c3b616c00	1333	- Core Debug Functions
IKobayashi	0:c88c3b616c00	1334	- Core Register Access Functions
IKobayashi	0:c88c3b616c00	1335	******************************************************************************/
IKobayashi	0:c88c3b616c00	1336	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
IKobayashi	0:c88c3b616c00	1337	*/
IKobayashi	0:c88c3b616c00	1338
IKobayashi	0:c88c3b616c00	1339
IKobayashi	0:c88c3b616c00	1340
IKobayashi	0:c88c3b616c00	1341	/* ########################## NVIC functions #################################### */
IKobayashi	0:c88c3b616c00	1342	/** \ingroup CMSIS_Core_FunctionInterface
IKobayashi	0:c88c3b616c00	1343	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
IKobayashi	0:c88c3b616c00	1344	\brief Functions that manage interrupts and exceptions via the NVIC.
IKobayashi	0:c88c3b616c00	1345	@{
IKobayashi	0:c88c3b616c00	1346	*/
IKobayashi	0:c88c3b616c00	1347
IKobayashi	0:c88c3b616c00	1348	#ifdef CMSIS_NVIC_VIRTUAL
IKobayashi	0:c88c3b616c00	1349	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
IKobayashi	0:c88c3b616c00	1350	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
IKobayashi	0:c88c3b616c00	1351	#endif
IKobayashi	0:c88c3b616c00	1352	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
IKobayashi	0:c88c3b616c00	1353	#else
IKobayashi	0:c88c3b616c00	1354	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
IKobayashi	0:c88c3b616c00	1355	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
IKobayashi	0:c88c3b616c00	1356	#define NVIC_EnableIRQ __NVIC_EnableIRQ
IKobayashi	0:c88c3b616c00	1357	#define NVIC_DisableIRQ __NVIC_DisableIRQ
IKobayashi	0:c88c3b616c00	1358	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
IKobayashi	0:c88c3b616c00	1359	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
IKobayashi	0:c88c3b616c00	1360	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
IKobayashi	0:c88c3b616c00	1361	#define NVIC_GetActive __NVIC_GetActive
IKobayashi	0:c88c3b616c00	1362	#define NVIC_SetPriority __NVIC_SetPriority
IKobayashi	0:c88c3b616c00	1363	#define NVIC_GetPriority __NVIC_GetPriority
IKobayashi	0:c88c3b616c00	1364	#define NVIC_SystemReset __NVIC_SystemReset
IKobayashi	0:c88c3b616c00	1365	#endif /* CMSIS_NVIC_VIRTUAL */
IKobayashi	0:c88c3b616c00	1366
IKobayashi	0:c88c3b616c00	1367	#ifdef CMSIS_VECTAB_VIRTUAL
IKobayashi	0:c88c3b616c00	1368	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
IKobayashi	0:c88c3b616c00	1369	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
IKobayashi	0:c88c3b616c00	1370	#endif
IKobayashi	0:c88c3b616c00	1371	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
IKobayashi	0:c88c3b616c00	1372	#else
IKobayashi	0:c88c3b616c00	1373	#define NVIC_SetVector __NVIC_SetVector
IKobayashi	0:c88c3b616c00	1374	#define NVIC_GetVector __NVIC_GetVector
IKobayashi	0:c88c3b616c00	1375	#endif /* CMSIS_VECTAB_VIRTUAL */
IKobayashi	0:c88c3b616c00	1376
IKobayashi	0:c88c3b616c00	1377	/** \brief Set Priority Grouping
IKobayashi	0:c88c3b616c00	1378
IKobayashi	0:c88c3b616c00	1379	The function sets the priority grouping field using the required unlock sequence.
IKobayashi	0:c88c3b616c00	1380	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
IKobayashi	0:c88c3b616c00	1381	Only values from 0..7 are used.
IKobayashi	0:c88c3b616c00	1382	In case of a conflict between priority grouping and available
IKobayashi	0:c88c3b616c00	1383	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
IKobayashi	0:c88c3b616c00	1384
IKobayashi	0:c88c3b616c00	1385	\param [in] PriorityGroup Priority grouping field.
IKobayashi	0:c88c3b616c00	1386	*/
IKobayashi	0:c88c3b616c00	1387	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
IKobayashi	0:c88c3b616c00	1388	{
IKobayashi	0:c88c3b616c00	1389	uint32_t reg_value;
IKobayashi	0:c88c3b616c00	1390	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi	0:c88c3b616c00	1391
IKobayashi	0:c88c3b616c00	1392	reg_value = SCB->AIRCR; /* read old register configuration */
IKobayashi	0:c88c3b616c00	1393	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
IKobayashi	0:c88c3b616c00	1394	reg_value = (reg_value \|
IKobayashi	0:c88c3b616c00	1395	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
IKobayashi	0:c88c3b616c00	1396	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
IKobayashi	0:c88c3b616c00	1397	SCB->AIRCR = reg_value;
IKobayashi	0:c88c3b616c00	1398	}
IKobayashi	0:c88c3b616c00	1399
IKobayashi	0:c88c3b616c00	1400
IKobayashi	0:c88c3b616c00	1401	/** \brief Get Priority Grouping
IKobayashi	0:c88c3b616c00	1402
IKobayashi	0:c88c3b616c00	1403	The function reads the priority grouping field from the NVIC Interrupt Controller.
IKobayashi	0:c88c3b616c00	1404
IKobayashi	0:c88c3b616c00	1405	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
IKobayashi	0:c88c3b616c00	1406	*/
IKobayashi	0:c88c3b616c00	1407	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
IKobayashi	0:c88c3b616c00	1408	{
IKobayashi	0:c88c3b616c00	1409	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
IKobayashi	0:c88c3b616c00	1410	}
IKobayashi	0:c88c3b616c00	1411
IKobayashi	0:c88c3b616c00	1412
IKobayashi	0:c88c3b616c00	1413	/** \brief Enable External Interrupt
IKobayashi	0:c88c3b616c00	1414
IKobayashi	0:c88c3b616c00	1415	The function enables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi	0:c88c3b616c00	1416
IKobayashi	0:c88c3b616c00	1417	\param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi	0:c88c3b616c00	1418	*/
IKobayashi	0:c88c3b616c00	1419	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1420	{
IKobayashi	0:c88c3b616c00	1421	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi	0:c88c3b616c00	1422	}
IKobayashi	0:c88c3b616c00	1423
IKobayashi	0:c88c3b616c00	1424
IKobayashi	0:c88c3b616c00	1425	/** \brief Disable External Interrupt
IKobayashi	0:c88c3b616c00	1426
IKobayashi	0:c88c3b616c00	1427	The function disables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi	0:c88c3b616c00	1428
IKobayashi	0:c88c3b616c00	1429	\param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi	0:c88c3b616c00	1430	*/
IKobayashi	0:c88c3b616c00	1431	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1432	{
IKobayashi	0:c88c3b616c00	1433	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi	0:c88c3b616c00	1434	__DSB();
IKobayashi	0:c88c3b616c00	1435	__ISB();
IKobayashi	0:c88c3b616c00	1436	}
IKobayashi	0:c88c3b616c00	1437
IKobayashi	0:c88c3b616c00	1438
IKobayashi	0:c88c3b616c00	1439	/** \brief Get Pending Interrupt
IKobayashi	0:c88c3b616c00	1440
IKobayashi	0:c88c3b616c00	1441	The function reads the pending register in the NVIC and returns the pending bit
IKobayashi	0:c88c3b616c00	1442	for the specified interrupt.
IKobayashi	0:c88c3b616c00	1443
IKobayashi	0:c88c3b616c00	1444	\param [in] IRQn Interrupt number.
IKobayashi	0:c88c3b616c00	1445
IKobayashi	0:c88c3b616c00	1446	\return 0 Interrupt status is not pending.
IKobayashi	0:c88c3b616c00	1447	\return 1 Interrupt status is pending.
IKobayashi	0:c88c3b616c00	1448	*/
IKobayashi	0:c88c3b616c00	1449	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1450	{
IKobayashi	0:c88c3b616c00	1451	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
IKobayashi	0:c88c3b616c00	1452	}
IKobayashi	0:c88c3b616c00	1453
IKobayashi	0:c88c3b616c00	1454
IKobayashi	0:c88c3b616c00	1455	/** \brief Set Pending Interrupt
IKobayashi	0:c88c3b616c00	1456
IKobayashi	0:c88c3b616c00	1457	The function sets the pending bit of an external interrupt.
IKobayashi	0:c88c3b616c00	1458
IKobayashi	0:c88c3b616c00	1459	\param [in] IRQn Interrupt number. Value cannot be negative.
IKobayashi	0:c88c3b616c00	1460	*/
IKobayashi	0:c88c3b616c00	1461	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1462	{
IKobayashi	0:c88c3b616c00	1463	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi	0:c88c3b616c00	1464	}
IKobayashi	0:c88c3b616c00	1465
IKobayashi	0:c88c3b616c00	1466
IKobayashi	0:c88c3b616c00	1467	/** \brief Clear Pending Interrupt
IKobayashi	0:c88c3b616c00	1468
IKobayashi	0:c88c3b616c00	1469	The function clears the pending bit of an external interrupt.
IKobayashi	0:c88c3b616c00	1470
IKobayashi	0:c88c3b616c00	1471	\param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi	0:c88c3b616c00	1472	*/
IKobayashi	0:c88c3b616c00	1473	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1474	{
IKobayashi	0:c88c3b616c00	1475	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi	0:c88c3b616c00	1476	}
IKobayashi	0:c88c3b616c00	1477
IKobayashi	0:c88c3b616c00	1478
IKobayashi	0:c88c3b616c00	1479	/** \brief Get Active Interrupt
IKobayashi	0:c88c3b616c00	1480
IKobayashi	0:c88c3b616c00	1481	The function reads the active register in NVIC and returns the active bit.
IKobayashi	0:c88c3b616c00	1482
IKobayashi	0:c88c3b616c00	1483	\param [in] IRQn Interrupt number.
IKobayashi	0:c88c3b616c00	1484
IKobayashi	0:c88c3b616c00	1485	\return 0 Interrupt status is not active.
IKobayashi	0:c88c3b616c00	1486	\return 1 Interrupt status is active.
IKobayashi	0:c88c3b616c00	1487	*/
IKobayashi	0:c88c3b616c00	1488	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1489	{
IKobayashi	0:c88c3b616c00	1490	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
IKobayashi	0:c88c3b616c00	1491	}
IKobayashi	0:c88c3b616c00	1492
IKobayashi	0:c88c3b616c00	1493
IKobayashi	0:c88c3b616c00	1494	/** \brief Set Interrupt Priority
IKobayashi	0:c88c3b616c00	1495
IKobayashi	0:c88c3b616c00	1496	The function sets the priority of an interrupt.
IKobayashi	0:c88c3b616c00	1497
IKobayashi	0:c88c3b616c00	1498	\note The priority cannot be set for every core interrupt.
IKobayashi	0:c88c3b616c00	1499
IKobayashi	0:c88c3b616c00	1500	\param [in] IRQn Interrupt number.
IKobayashi	0:c88c3b616c00	1501	\param [in] priority Priority to set.
IKobayashi	0:c88c3b616c00	1502	*/
IKobayashi	0:c88c3b616c00	1503	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
IKobayashi	0:c88c3b616c00	1504	{
IKobayashi	0:c88c3b616c00	1505	if((int32_t)IRQn < 0) {
IKobayashi	0:c88c3b616c00	1506	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
IKobayashi	0:c88c3b616c00	1507	}
IKobayashi	0:c88c3b616c00	1508	else {
IKobayashi	0:c88c3b616c00	1509	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
IKobayashi	0:c88c3b616c00	1510	}
IKobayashi	0:c88c3b616c00	1511	}
IKobayashi	0:c88c3b616c00	1512
IKobayashi	0:c88c3b616c00	1513
IKobayashi	0:c88c3b616c00	1514	/** \brief Get Interrupt Priority
IKobayashi	0:c88c3b616c00	1515
IKobayashi	0:c88c3b616c00	1516	The function reads the priority of an interrupt. The interrupt
IKobayashi	0:c88c3b616c00	1517	number can be positive to specify an external (device specific)
IKobayashi	0:c88c3b616c00	1518	interrupt, or negative to specify an internal (core) interrupt.
IKobayashi	0:c88c3b616c00	1519
IKobayashi	0:c88c3b616c00	1520
IKobayashi	0:c88c3b616c00	1521	\param [in] IRQn Interrupt number.
IKobayashi	0:c88c3b616c00	1522	\return Interrupt Priority. Value is aligned automatically to the implemented
IKobayashi	0:c88c3b616c00	1523	priority bits of the microcontroller.
IKobayashi	0:c88c3b616c00	1524	*/
IKobayashi	0:c88c3b616c00	1525	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
IKobayashi	0:c88c3b616c00	1526	{
IKobayashi	0:c88c3b616c00	1527
IKobayashi	0:c88c3b616c00	1528	if((int32_t)IRQn < 0) {
IKobayashi	0:c88c3b616c00	1529	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
IKobayashi	0:c88c3b616c00	1530	}
IKobayashi	0:c88c3b616c00	1531	else {
IKobayashi	0:c88c3b616c00	1532	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
IKobayashi	0:c88c3b616c00	1533	}
IKobayashi	0:c88c3b616c00	1534	}
IKobayashi	0:c88c3b616c00	1535
IKobayashi	0:c88c3b616c00	1536
IKobayashi	0:c88c3b616c00	1537	/** \brief Encode Priority
IKobayashi	0:c88c3b616c00	1538
IKobayashi	0:c88c3b616c00	1539	The function encodes the priority for an interrupt with the given priority group,
IKobayashi	0:c88c3b616c00	1540	preemptive priority value, and subpriority value.
IKobayashi	0:c88c3b616c00	1541	In case of a conflict between priority grouping and available
IKobayashi	0:c88c3b616c00	1542	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
IKobayashi	0:c88c3b616c00	1543
IKobayashi	0:c88c3b616c00	1544	\param [in] PriorityGroup Used priority group.
IKobayashi	0:c88c3b616c00	1545	\param [in] PreemptPriority Preemptive priority value (starting from 0).
IKobayashi	0:c88c3b616c00	1546	\param [in] SubPriority Subpriority value (starting from 0).
IKobayashi	0:c88c3b616c00	1547	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
IKobayashi	0:c88c3b616c00	1548	*/
IKobayashi	0:c88c3b616c00	1549	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
IKobayashi	0:c88c3b616c00	1550	{
IKobayashi	0:c88c3b616c00	1551	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi	0:c88c3b616c00	1552	uint32_t PreemptPriorityBits;
IKobayashi	0:c88c3b616c00	1553	uint32_t SubPriorityBits;
IKobayashi	0:c88c3b616c00	1554
IKobayashi	0:c88c3b616c00	1555	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
IKobayashi	0:c88c3b616c00	1556	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
IKobayashi	0:c88c3b616c00	1557
IKobayashi	0:c88c3b616c00	1558	return (
IKobayashi	0:c88c3b616c00	1559	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
IKobayashi	0:c88c3b616c00	1560	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
IKobayashi	0:c88c3b616c00	1561	);
IKobayashi	0:c88c3b616c00	1562	}
IKobayashi	0:c88c3b616c00	1563
IKobayashi	0:c88c3b616c00	1564
IKobayashi	0:c88c3b616c00	1565	/** \brief Decode Priority
IKobayashi	0:c88c3b616c00	1566
IKobayashi	0:c88c3b616c00	1567	The function decodes an interrupt priority value with a given priority group to
IKobayashi	0:c88c3b616c00	1568	preemptive priority value and subpriority value.
IKobayashi	0:c88c3b616c00	1569	In case of a conflict between priority grouping and available
IKobayashi	0:c88c3b616c00	1570	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
IKobayashi	0:c88c3b616c00	1571
IKobayashi	0:c88c3b616c00	1572	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
IKobayashi	0:c88c3b616c00	1573	\param [in] PriorityGroup Used priority group.
IKobayashi	0:c88c3b616c00	1574	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
IKobayashi	0:c88c3b616c00	1575	\param [out] pSubPriority Subpriority value (starting from 0).
IKobayashi	0:c88c3b616c00	1576	*/
IKobayashi	0:c88c3b616c00	1577	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
IKobayashi	0:c88c3b616c00	1578	{
IKobayashi	0:c88c3b616c00	1579	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
IKobayashi	0:c88c3b616c00	1580	uint32_t PreemptPriorityBits;
IKobayashi	0:c88c3b616c00	1581	uint32_t SubPriorityBits;
IKobayashi	0:c88c3b616c00	1582
IKobayashi	0:c88c3b616c00	1583	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
IKobayashi	0:c88c3b616c00	1584	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
IKobayashi	0:c88c3b616c00	1585
IKobayashi	0:c88c3b616c00	1586	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
IKobayashi	0:c88c3b616c00	1587	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
IKobayashi	0:c88c3b616c00	1588	}
IKobayashi	0:c88c3b616c00	1589
IKobayashi	0:c88c3b616c00	1590
IKobayashi	0:c88c3b616c00	1591	/** \brief System Reset
IKobayashi	0:c88c3b616c00	1592
IKobayashi	0:c88c3b616c00	1593	The function initiates a system reset request to reset the MCU.
IKobayashi	0:c88c3b616c00	1594	*/
IKobayashi	0:c88c3b616c00	1595	__STATIC_INLINE void __NVIC_SystemReset(void)
IKobayashi	0:c88c3b616c00	1596	{
IKobayashi	0:c88c3b616c00	1597	__DSB(); /* Ensure all outstanding memory accesses included
IKobayashi	0:c88c3b616c00	1598	buffered write are completed before reset */
IKobayashi	0:c88c3b616c00	1599	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
IKobayashi	0:c88c3b616c00	1600	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
IKobayashi	0:c88c3b616c00	1601	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
IKobayashi	0:c88c3b616c00	1602	__DSB(); /* Ensure completion of memory access */
IKobayashi	0:c88c3b616c00	1603	while(1) { __NOP(); } /* wait until reset */
IKobayashi	0:c88c3b616c00	1604	}
IKobayashi	0:c88c3b616c00	1605
IKobayashi	0:c88c3b616c00	1606	/@} end of CMSIS_Core_NVICFunctions /
IKobayashi	0:c88c3b616c00	1607
IKobayashi	0:c88c3b616c00	1608
IKobayashi	0:c88c3b616c00	1609
IKobayashi	0:c88c3b616c00	1610	/* ################################## SysTick function ############################################ */
IKobayashi	0:c88c3b616c00	1611	/** \ingroup CMSIS_Core_FunctionInterface
IKobayashi	0:c88c3b616c00	1612	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
IKobayashi	0:c88c3b616c00	1613	\brief Functions that configure the System.
IKobayashi	0:c88c3b616c00	1614	@{
IKobayashi	0:c88c3b616c00	1615	*/
IKobayashi	0:c88c3b616c00	1616
IKobayashi	0:c88c3b616c00	1617	#if (__Vendor_SysTickConfig == 0)
IKobayashi	0:c88c3b616c00	1618
IKobayashi	0:c88c3b616c00	1619	/** \brief System Tick Configuration
IKobayashi	0:c88c3b616c00	1620
IKobayashi	0:c88c3b616c00	1621	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
IKobayashi	0:c88c3b616c00	1622	Counter is in free running mode to generate periodic interrupts.
IKobayashi	0:c88c3b616c00	1623
IKobayashi	0:c88c3b616c00	1624	\param [in] ticks Number of ticks between two interrupts.
IKobayashi	0:c88c3b616c00	1625
IKobayashi	0:c88c3b616c00	1626	\return 0 Function succeeded.
IKobayashi	0:c88c3b616c00	1627	\return 1 Function failed.
IKobayashi	0:c88c3b616c00	1628
IKobayashi	0:c88c3b616c00	1629	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
IKobayashi	0:c88c3b616c00	1630	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
IKobayashi	0:c88c3b616c00	1631	must contain a vendor-specific implementation of this function.
IKobayashi	0:c88c3b616c00	1632
IKobayashi	0:c88c3b616c00	1633	*/
IKobayashi	0:c88c3b616c00	1634	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
IKobayashi	0:c88c3b616c00	1635	{
IKobayashi	0:c88c3b616c00	1636	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
IKobayashi	0:c88c3b616c00	1637
IKobayashi	0:c88c3b616c00	1638	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
IKobayashi	0:c88c3b616c00	1639	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
IKobayashi	0:c88c3b616c00	1640	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
IKobayashi	0:c88c3b616c00	1641	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
IKobayashi	0:c88c3b616c00	1642	SysTick_CTRL_TICKINT_Msk \|
IKobayashi	0:c88c3b616c00	1643	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
IKobayashi	0:c88c3b616c00	1644	return (0UL); /* Function successful */
IKobayashi	0:c88c3b616c00	1645	}
IKobayashi	0:c88c3b616c00	1646
IKobayashi	0:c88c3b616c00	1647	#endif
IKobayashi	0:c88c3b616c00	1648
IKobayashi	0:c88c3b616c00	1649	/@} end of CMSIS_Core_SysTickFunctions /
IKobayashi	0:c88c3b616c00	1650
IKobayashi	0:c88c3b616c00	1651
IKobayashi	0:c88c3b616c00	1652
IKobayashi	0:c88c3b616c00	1653	/* ##################################### Debug In/Output function ########################################### */
IKobayashi	0:c88c3b616c00	1654	/** \ingroup CMSIS_Core_FunctionInterface
IKobayashi	0:c88c3b616c00	1655	\defgroup CMSIS_core_DebugFunctions ITM Functions
IKobayashi	0:c88c3b616c00	1656	\brief Functions that access the ITM debug interface.
IKobayashi	0:c88c3b616c00	1657	@{
IKobayashi	0:c88c3b616c00	1658	*/
IKobayashi	0:c88c3b616c00	1659
IKobayashi	0:c88c3b616c00	1660	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
IKobayashi	0:c88c3b616c00	1661	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
IKobayashi	0:c88c3b616c00	1662
IKobayashi	0:c88c3b616c00	1663
IKobayashi	0:c88c3b616c00	1664	/** \brief ITM Send Character
IKobayashi	0:c88c3b616c00	1665
IKobayashi	0:c88c3b616c00	1666	The function transmits a character via the ITM channel 0, and
IKobayashi	0:c88c3b616c00	1667	\li Just returns when no debugger is connected that has booked the output.
IKobayashi	0:c88c3b616c00	1668	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
IKobayashi	0:c88c3b616c00	1669
IKobayashi	0:c88c3b616c00	1670	\param [in] ch Character to transmit.
IKobayashi	0:c88c3b616c00	1671
IKobayashi	0:c88c3b616c00	1672	\returns Character to transmit.
IKobayashi	0:c88c3b616c00	1673	*/
IKobayashi	0:c88c3b616c00	1674	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
IKobayashi	0:c88c3b616c00	1675	{
IKobayashi	0:c88c3b616c00	1676	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
IKobayashi	0:c88c3b616c00	1677	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
IKobayashi	0:c88c3b616c00	1678	{
IKobayashi	0:c88c3b616c00	1679	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
IKobayashi	0:c88c3b616c00	1680	ITM->PORT[0].u8 = (uint8_t)ch;
IKobayashi	0:c88c3b616c00	1681	}
IKobayashi	0:c88c3b616c00	1682	return (ch);
IKobayashi	0:c88c3b616c00	1683	}
IKobayashi	0:c88c3b616c00	1684
IKobayashi	0:c88c3b616c00	1685
IKobayashi	0:c88c3b616c00	1686	/** \brief ITM Receive Character
IKobayashi	0:c88c3b616c00	1687
IKobayashi	0:c88c3b616c00	1688	The function inputs a character via the external variable \ref ITM_RxBuffer.
IKobayashi	0:c88c3b616c00	1689
IKobayashi	0:c88c3b616c00	1690	\return Received character.
IKobayashi	0:c88c3b616c00	1691	\return -1 No character pending.
IKobayashi	0:c88c3b616c00	1692	*/
IKobayashi	0:c88c3b616c00	1693	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
IKobayashi	0:c88c3b616c00	1694	int32_t ch = -1; /* no character available */
IKobayashi	0:c88c3b616c00	1695
IKobayashi	0:c88c3b616c00	1696	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
IKobayashi	0:c88c3b616c00	1697	ch = ITM_RxBuffer;
IKobayashi	0:c88c3b616c00	1698	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
IKobayashi	0:c88c3b616c00	1699	}
IKobayashi	0:c88c3b616c00	1700
IKobayashi	0:c88c3b616c00	1701	return (ch);
IKobayashi	0:c88c3b616c00	1702	}
IKobayashi	0:c88c3b616c00	1703
IKobayashi	0:c88c3b616c00	1704
IKobayashi	0:c88c3b616c00	1705	/** \brief ITM Check Character
IKobayashi	0:c88c3b616c00	1706
IKobayashi	0:c88c3b616c00	1707	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
IKobayashi	0:c88c3b616c00	1708
IKobayashi	0:c88c3b616c00	1709	\return 0 No character available.
IKobayashi	0:c88c3b616c00	1710	\return 1 Character available.
IKobayashi	0:c88c3b616c00	1711	*/
IKobayashi	0:c88c3b616c00	1712	__STATIC_INLINE int32_t ITM_CheckChar (void) {
IKobayashi	0:c88c3b616c00	1713
IKobayashi	0:c88c3b616c00	1714	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
IKobayashi	0:c88c3b616c00	1715	return (0); /* no character available */
IKobayashi	0:c88c3b616c00	1716	} else {
IKobayashi	0:c88c3b616c00	1717	return (1); /* character available */
IKobayashi	0:c88c3b616c00	1718	}
IKobayashi	0:c88c3b616c00	1719	}
IKobayashi	0:c88c3b616c00	1720
IKobayashi	0:c88c3b616c00	1721	/@} end of CMSIS_core_DebugFunctions /
IKobayashi	0:c88c3b616c00	1722
IKobayashi	0:c88c3b616c00	1723
IKobayashi	0:c88c3b616c00	1724
IKobayashi	0:c88c3b616c00	1725
IKobayashi	0:c88c3b616c00	1726	#ifdef __cplusplus
IKobayashi	0:c88c3b616c00	1727	}
IKobayashi	0:c88c3b616c00	1728	#endif
IKobayashi	0:c88c3b616c00	1729
IKobayashi	0:c88c3b616c00	1730	#endif /* __CORE_CM3_H_DEPENDANT */
IKobayashi	0:c88c3b616c00	1731
IKobayashi	0:c88c3b616c00	1732	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	16 Mar 2020
Imports:	3
Forks:	0
Commits:	1
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mbed/TARGET_LPC1768/core_cm3.h@0:c88c3b616c00, 2020-03-16 (annotated)

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