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mbed/TARGET_LPC1768/core_cm0plus.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file core_cm0plus.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
IKobayashi 0:c88c3b616c00 4 * @version V4.10
IKobayashi 0:c88c3b616c00 5 * @date 18. March 2015
IKobayashi 0:c88c3b616c00 6 *
IKobayashi 0:c88c3b616c00 7 * @note
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 ******************************************************************************/
IKobayashi 0:c88c3b616c00 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
IKobayashi 0:c88c3b616c00 11
IKobayashi 0:c88c3b616c00 12 All rights reserved.
IKobayashi 0:c88c3b616c00 13 Redistribution and use in source and binary forms, with or without
IKobayashi 0:c88c3b616c00 14 modification, are permitted provided that the following conditions are met:
IKobayashi 0:c88c3b616c00 15 - Redistributions of source code must retain the above copyright
IKobayashi 0:c88c3b616c00 16 notice, this list of conditions and the following disclaimer.
IKobayashi 0:c88c3b616c00 17 - Redistributions in binary form must reproduce the above copyright
IKobayashi 0:c88c3b616c00 18 notice, this list of conditions and the following disclaimer in the
IKobayashi 0:c88c3b616c00 19 documentation and/or other materials provided with the distribution.
IKobayashi 0:c88c3b616c00 20 - Neither the name of ARM nor the names of its contributors may be used
IKobayashi 0:c88c3b616c00 21 to endorse or promote products derived from this software without
IKobayashi 0:c88c3b616c00 22 specific prior written permission.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
IKobayashi 0:c88c3b616c00 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IKobayashi 0:c88c3b616c00 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
IKobayashi 0:c88c3b616c00 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
IKobayashi 0:c88c3b616c00 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
IKobayashi 0:c88c3b616c00 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
IKobayashi 0:c88c3b616c00 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
IKobayashi 0:c88c3b616c00 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
IKobayashi 0:c88c3b616c00 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
IKobayashi 0:c88c3b616c00 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
IKobayashi 0:c88c3b616c00 34 POSSIBILITY OF SUCH DAMAGE.
IKobayashi 0:c88c3b616c00 35 ---------------------------------------------------------------------------*/
IKobayashi 0:c88c3b616c00 36
IKobayashi 0:c88c3b616c00 37
IKobayashi 0:c88c3b616c00 38 #if defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 39 #pragma system_include /* treat file as system include file for MISRA check */
IKobayashi 0:c88c3b616c00 40 #endif
IKobayashi 0:c88c3b616c00 41
IKobayashi 0:c88c3b616c00 42 #ifndef __CORE_CM0PLUS_H_GENERIC
IKobayashi 0:c88c3b616c00 43 #define __CORE_CM0PLUS_H_GENERIC
IKobayashi 0:c88c3b616c00 44
IKobayashi 0:c88c3b616c00 45 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 46 extern "C" {
IKobayashi 0:c88c3b616c00 47 #endif
IKobayashi 0:c88c3b616c00 48
IKobayashi 0:c88c3b616c00 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
IKobayashi 0:c88c3b616c00 50 CMSIS violates the following MISRA-C:2004 rules:
IKobayashi 0:c88c3b616c00 51
IKobayashi 0:c88c3b616c00 52 \li Required Rule 8.5, object/function definition in header file.<br>
IKobayashi 0:c88c3b616c00 53 Function definitions in header files are used to allow 'inlining'.
IKobayashi 0:c88c3b616c00 54
IKobayashi 0:c88c3b616c00 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
IKobayashi 0:c88c3b616c00 56 Unions are used for effective representation of core registers.
IKobayashi 0:c88c3b616c00 57
IKobayashi 0:c88c3b616c00 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
IKobayashi 0:c88c3b616c00 59 Function-like macros are used to allow more efficient code.
IKobayashi 0:c88c3b616c00 60 */
IKobayashi 0:c88c3b616c00 61
IKobayashi 0:c88c3b616c00 62
IKobayashi 0:c88c3b616c00 63 /*******************************************************************************
IKobayashi 0:c88c3b616c00 64 * CMSIS definitions
IKobayashi 0:c88c3b616c00 65 ******************************************************************************/
IKobayashi 0:c88c3b616c00 66 /** \ingroup Cortex-M0+
IKobayashi 0:c88c3b616c00 67 @{
IKobayashi 0:c88c3b616c00 68 */
IKobayashi 0:c88c3b616c00 69
IKobayashi 0:c88c3b616c00 70 /* CMSIS CM0P definitions */
IKobayashi 0:c88c3b616c00 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
IKobayashi 0:c88c3b616c00 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
IKobayashi 0:c88c3b616c00 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
IKobayashi 0:c88c3b616c00 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
IKobayashi 0:c88c3b616c00 75
IKobayashi 0:c88c3b616c00 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
IKobayashi 0:c88c3b616c00 77
IKobayashi 0:c88c3b616c00 78
IKobayashi 0:c88c3b616c00 79 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
IKobayashi 0:c88c3b616c00 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
IKobayashi 0:c88c3b616c00 82 #define __STATIC_INLINE static __inline
IKobayashi 0:c88c3b616c00 83
IKobayashi 0:c88c3b616c00 84 #elif defined ( __GNUC__ )
IKobayashi 0:c88c3b616c00 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
IKobayashi 0:c88c3b616c00 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
IKobayashi 0:c88c3b616c00 87 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 88
IKobayashi 0:c88c3b616c00 89 #elif defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
IKobayashi 0:c88c3b616c00 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
IKobayashi 0:c88c3b616c00 92 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 93
IKobayashi 0:c88c3b616c00 94 #elif defined ( __TMS470__ )
IKobayashi 0:c88c3b616c00 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
IKobayashi 0:c88c3b616c00 96 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 97
IKobayashi 0:c88c3b616c00 98 #elif defined ( __TASKING__ )
IKobayashi 0:c88c3b616c00 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
IKobayashi 0:c88c3b616c00 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
IKobayashi 0:c88c3b616c00 101 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 102
IKobayashi 0:c88c3b616c00 103 #elif defined ( __CSMC__ )
IKobayashi 0:c88c3b616c00 104 #define __packed
IKobayashi 0:c88c3b616c00 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
IKobayashi 0:c88c3b616c00 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
IKobayashi 0:c88c3b616c00 107 #define __STATIC_INLINE static inline
IKobayashi 0:c88c3b616c00 108
IKobayashi 0:c88c3b616c00 109 #endif
IKobayashi 0:c88c3b616c00 110
IKobayashi 0:c88c3b616c00 111 /** __FPU_USED indicates whether an FPU is used or not.
IKobayashi 0:c88c3b616c00 112 This core does not support an FPU at all
IKobayashi 0:c88c3b616c00 113 */
IKobayashi 0:c88c3b616c00 114 #define __FPU_USED 0
IKobayashi 0:c88c3b616c00 115
IKobayashi 0:c88c3b616c00 116 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 117 #if defined __TARGET_FPU_VFP
IKobayashi 0:c88c3b616c00 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 119 #endif
IKobayashi 0:c88c3b616c00 120
IKobayashi 0:c88c3b616c00 121 #elif defined ( __GNUC__ )
IKobayashi 0:c88c3b616c00 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
IKobayashi 0:c88c3b616c00 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 124 #endif
IKobayashi 0:c88c3b616c00 125
IKobayashi 0:c88c3b616c00 126 #elif defined ( __ICCARM__ )
IKobayashi 0:c88c3b616c00 127 #if defined __ARMVFP__
IKobayashi 0:c88c3b616c00 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 129 #endif
IKobayashi 0:c88c3b616c00 130
IKobayashi 0:c88c3b616c00 131 #elif defined ( __TMS470__ )
IKobayashi 0:c88c3b616c00 132 #if defined __TI__VFP_SUPPORT____
IKobayashi 0:c88c3b616c00 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 134 #endif
IKobayashi 0:c88c3b616c00 135
IKobayashi 0:c88c3b616c00 136 #elif defined ( __TASKING__ )
IKobayashi 0:c88c3b616c00 137 #if defined __FPU_VFP__
IKobayashi 0:c88c3b616c00 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 139 #endif
IKobayashi 0:c88c3b616c00 140
IKobayashi 0:c88c3b616c00 141 #elif defined ( __CSMC__ ) /* Cosmic */
IKobayashi 0:c88c3b616c00 142 #if ( __CSMC__ & 0x400) // FPU present for parser
IKobayashi 0:c88c3b616c00 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
IKobayashi 0:c88c3b616c00 144 #endif
IKobayashi 0:c88c3b616c00 145 #endif
IKobayashi 0:c88c3b616c00 146
IKobayashi 0:c88c3b616c00 147 #include <stdint.h> /* standard types definitions */
IKobayashi 0:c88c3b616c00 148 #include <core_cmInstr.h> /* Core Instruction Access */
IKobayashi 0:c88c3b616c00 149 #include <core_cmFunc.h> /* Core Function Access */
IKobayashi 0:c88c3b616c00 150
IKobayashi 0:c88c3b616c00 151 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 152 }
IKobayashi 0:c88c3b616c00 153 #endif
IKobayashi 0:c88c3b616c00 154
IKobayashi 0:c88c3b616c00 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
IKobayashi 0:c88c3b616c00 156
IKobayashi 0:c88c3b616c00 157 #ifndef __CMSIS_GENERIC
IKobayashi 0:c88c3b616c00 158
IKobayashi 0:c88c3b616c00 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
IKobayashi 0:c88c3b616c00 160 #define __CORE_CM0PLUS_H_DEPENDANT
IKobayashi 0:c88c3b616c00 161
IKobayashi 0:c88c3b616c00 162 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 163 extern "C" {
IKobayashi 0:c88c3b616c00 164 #endif
IKobayashi 0:c88c3b616c00 165
IKobayashi 0:c88c3b616c00 166 /* check device defines and use defaults */
IKobayashi 0:c88c3b616c00 167 #if defined __CHECK_DEVICE_DEFINES
IKobayashi 0:c88c3b616c00 168 #ifndef __CM0PLUS_REV
IKobayashi 0:c88c3b616c00 169 #define __CM0PLUS_REV 0x0000
IKobayashi 0:c88c3b616c00 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 171 #endif
IKobayashi 0:c88c3b616c00 172
IKobayashi 0:c88c3b616c00 173 #ifndef __MPU_PRESENT
IKobayashi 0:c88c3b616c00 174 #define __MPU_PRESENT 0
IKobayashi 0:c88c3b616c00 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 176 #endif
IKobayashi 0:c88c3b616c00 177
IKobayashi 0:c88c3b616c00 178 #ifndef __VTOR_PRESENT
IKobayashi 0:c88c3b616c00 179 #define __VTOR_PRESENT 0
IKobayashi 0:c88c3b616c00 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 181 #endif
IKobayashi 0:c88c3b616c00 182
IKobayashi 0:c88c3b616c00 183 #ifndef __NVIC_PRIO_BITS
IKobayashi 0:c88c3b616c00 184 #define __NVIC_PRIO_BITS 2
IKobayashi 0:c88c3b616c00 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 186 #endif
IKobayashi 0:c88c3b616c00 187
IKobayashi 0:c88c3b616c00 188 #ifndef __Vendor_SysTickConfig
IKobayashi 0:c88c3b616c00 189 #define __Vendor_SysTickConfig 0
IKobayashi 0:c88c3b616c00 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
IKobayashi 0:c88c3b616c00 191 #endif
IKobayashi 0:c88c3b616c00 192 #endif
IKobayashi 0:c88c3b616c00 193
IKobayashi 0:c88c3b616c00 194 /* IO definitions (access restrictions to peripheral registers) */
IKobayashi 0:c88c3b616c00 195 /**
IKobayashi 0:c88c3b616c00 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
IKobayashi 0:c88c3b616c00 197
IKobayashi 0:c88c3b616c00 198 <strong>IO Type Qualifiers</strong> are used
IKobayashi 0:c88c3b616c00 199 \li to specify the access to peripheral variables.
IKobayashi 0:c88c3b616c00 200 \li for automatic generation of peripheral register debug information.
IKobayashi 0:c88c3b616c00 201 */
IKobayashi 0:c88c3b616c00 202 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 203 #define __I volatile /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 204 #else
IKobayashi 0:c88c3b616c00 205 #define __I volatile const /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 206 #endif
IKobayashi 0:c88c3b616c00 207 #define __O volatile /*!< Defines 'write only' permissions */
IKobayashi 0:c88c3b616c00 208 #define __IO volatile /*!< Defines 'read / write' permissions */
IKobayashi 0:c88c3b616c00 209
IKobayashi 0:c88c3b616c00 210 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 211 #define __IM volatile /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 212 #else
IKobayashi 0:c88c3b616c00 213 #define __IM volatile const /*!< Defines 'read only' permissions */
IKobayashi 0:c88c3b616c00 214 #endif
IKobayashi 0:c88c3b616c00 215 #define __OM volatile /*!< Defines 'write only' permissions */
IKobayashi 0:c88c3b616c00 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
IKobayashi 0:c88c3b616c00 217
IKobayashi 0:c88c3b616c00 218 /*@} end of group Cortex-M0+ */
IKobayashi 0:c88c3b616c00 219
IKobayashi 0:c88c3b616c00 220
IKobayashi 0:c88c3b616c00 221
IKobayashi 0:c88c3b616c00 222 /*******************************************************************************
IKobayashi 0:c88c3b616c00 223 * Register Abstraction
IKobayashi 0:c88c3b616c00 224 Core Register contain:
IKobayashi 0:c88c3b616c00 225 - Core Register
IKobayashi 0:c88c3b616c00 226 - Core NVIC Register
IKobayashi 0:c88c3b616c00 227 - Core SCB Register
IKobayashi 0:c88c3b616c00 228 - Core SysTick Register
IKobayashi 0:c88c3b616c00 229 - Core MPU Register
IKobayashi 0:c88c3b616c00 230 ******************************************************************************/
IKobayashi 0:c88c3b616c00 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
IKobayashi 0:c88c3b616c00 232 \brief Type definitions and defines for Cortex-M processor based devices.
IKobayashi 0:c88c3b616c00 233 */
IKobayashi 0:c88c3b616c00 234
IKobayashi 0:c88c3b616c00 235 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 236 \defgroup CMSIS_CORE Status and Control Registers
IKobayashi 0:c88c3b616c00 237 \brief Core Register type definitions.
IKobayashi 0:c88c3b616c00 238 @{
IKobayashi 0:c88c3b616c00 239 */
IKobayashi 0:c88c3b616c00 240
IKobayashi 0:c88c3b616c00 241 /** \brief Union type to access the Application Program Status Register (APSR).
IKobayashi 0:c88c3b616c00 242 */
IKobayashi 0:c88c3b616c00 243 typedef union
IKobayashi 0:c88c3b616c00 244 {
IKobayashi 0:c88c3b616c00 245 struct
IKobayashi 0:c88c3b616c00 246 {
IKobayashi 0:c88c3b616c00 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
IKobayashi 0:c88c3b616c00 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
IKobayashi 0:c88c3b616c00 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
IKobayashi 0:c88c3b616c00 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
IKobayashi 0:c88c3b616c00 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
IKobayashi 0:c88c3b616c00 252 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 253 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 254 } APSR_Type;
IKobayashi 0:c88c3b616c00 255
IKobayashi 0:c88c3b616c00 256 /* APSR Register Definitions */
IKobayashi 0:c88c3b616c00 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
IKobayashi 0:c88c3b616c00 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
IKobayashi 0:c88c3b616c00 259
IKobayashi 0:c88c3b616c00 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
IKobayashi 0:c88c3b616c00 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
IKobayashi 0:c88c3b616c00 262
IKobayashi 0:c88c3b616c00 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
IKobayashi 0:c88c3b616c00 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
IKobayashi 0:c88c3b616c00 265
IKobayashi 0:c88c3b616c00 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
IKobayashi 0:c88c3b616c00 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
IKobayashi 0:c88c3b616c00 268
IKobayashi 0:c88c3b616c00 269
IKobayashi 0:c88c3b616c00 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
IKobayashi 0:c88c3b616c00 271 */
IKobayashi 0:c88c3b616c00 272 typedef union
IKobayashi 0:c88c3b616c00 273 {
IKobayashi 0:c88c3b616c00 274 struct
IKobayashi 0:c88c3b616c00 275 {
IKobayashi 0:c88c3b616c00 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
IKobayashi 0:c88c3b616c00 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
IKobayashi 0:c88c3b616c00 278 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 279 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 280 } IPSR_Type;
IKobayashi 0:c88c3b616c00 281
IKobayashi 0:c88c3b616c00 282 /* IPSR Register Definitions */
IKobayashi 0:c88c3b616c00 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
IKobayashi 0:c88c3b616c00 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
IKobayashi 0:c88c3b616c00 285
IKobayashi 0:c88c3b616c00 286
IKobayashi 0:c88c3b616c00 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
IKobayashi 0:c88c3b616c00 288 */
IKobayashi 0:c88c3b616c00 289 typedef union
IKobayashi 0:c88c3b616c00 290 {
IKobayashi 0:c88c3b616c00 291 struct
IKobayashi 0:c88c3b616c00 292 {
IKobayashi 0:c88c3b616c00 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
IKobayashi 0:c88c3b616c00 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
IKobayashi 0:c88c3b616c00 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
IKobayashi 0:c88c3b616c00 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
IKobayashi 0:c88c3b616c00 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
IKobayashi 0:c88c3b616c00 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
IKobayashi 0:c88c3b616c00 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
IKobayashi 0:c88c3b616c00 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
IKobayashi 0:c88c3b616c00 301 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 302 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 303 } xPSR_Type;
IKobayashi 0:c88c3b616c00 304
IKobayashi 0:c88c3b616c00 305 /* xPSR Register Definitions */
IKobayashi 0:c88c3b616c00 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
IKobayashi 0:c88c3b616c00 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
IKobayashi 0:c88c3b616c00 308
IKobayashi 0:c88c3b616c00 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
IKobayashi 0:c88c3b616c00 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
IKobayashi 0:c88c3b616c00 311
IKobayashi 0:c88c3b616c00 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
IKobayashi 0:c88c3b616c00 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
IKobayashi 0:c88c3b616c00 314
IKobayashi 0:c88c3b616c00 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
IKobayashi 0:c88c3b616c00 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
IKobayashi 0:c88c3b616c00 317
IKobayashi 0:c88c3b616c00 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
IKobayashi 0:c88c3b616c00 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
IKobayashi 0:c88c3b616c00 320
IKobayashi 0:c88c3b616c00 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
IKobayashi 0:c88c3b616c00 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
IKobayashi 0:c88c3b616c00 323
IKobayashi 0:c88c3b616c00 324
IKobayashi 0:c88c3b616c00 325 /** \brief Union type to access the Control Registers (CONTROL).
IKobayashi 0:c88c3b616c00 326 */
IKobayashi 0:c88c3b616c00 327 typedef union
IKobayashi 0:c88c3b616c00 328 {
IKobayashi 0:c88c3b616c00 329 struct
IKobayashi 0:c88c3b616c00 330 {
IKobayashi 0:c88c3b616c00 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
IKobayashi 0:c88c3b616c00 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
IKobayashi 0:c88c3b616c00 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
IKobayashi 0:c88c3b616c00 334 } b; /*!< Structure used for bit access */
IKobayashi 0:c88c3b616c00 335 uint32_t w; /*!< Type used for word access */
IKobayashi 0:c88c3b616c00 336 } CONTROL_Type;
IKobayashi 0:c88c3b616c00 337
IKobayashi 0:c88c3b616c00 338 /* CONTROL Register Definitions */
IKobayashi 0:c88c3b616c00 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
IKobayashi 0:c88c3b616c00 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
IKobayashi 0:c88c3b616c00 341
IKobayashi 0:c88c3b616c00 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
IKobayashi 0:c88c3b616c00 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
IKobayashi 0:c88c3b616c00 344
IKobayashi 0:c88c3b616c00 345 /*@} end of group CMSIS_CORE */
IKobayashi 0:c88c3b616c00 346
IKobayashi 0:c88c3b616c00 347
IKobayashi 0:c88c3b616c00 348 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
IKobayashi 0:c88c3b616c00 350 \brief Type definitions for the NVIC Registers
IKobayashi 0:c88c3b616c00 351 @{
IKobayashi 0:c88c3b616c00 352 */
IKobayashi 0:c88c3b616c00 353
IKobayashi 0:c88c3b616c00 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
IKobayashi 0:c88c3b616c00 355 */
IKobayashi 0:c88c3b616c00 356 typedef struct
IKobayashi 0:c88c3b616c00 357 {
IKobayashi 0:c88c3b616c00 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
IKobayashi 0:c88c3b616c00 359 uint32_t RESERVED0[31];
IKobayashi 0:c88c3b616c00 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
IKobayashi 0:c88c3b616c00 361 uint32_t RSERVED1[31];
IKobayashi 0:c88c3b616c00 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
IKobayashi 0:c88c3b616c00 363 uint32_t RESERVED2[31];
IKobayashi 0:c88c3b616c00 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
IKobayashi 0:c88c3b616c00 365 uint32_t RESERVED3[31];
IKobayashi 0:c88c3b616c00 366 uint32_t RESERVED4[64];
IKobayashi 0:c88c3b616c00 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
IKobayashi 0:c88c3b616c00 368 } NVIC_Type;
IKobayashi 0:c88c3b616c00 369
IKobayashi 0:c88c3b616c00 370 /*@} end of group CMSIS_NVIC */
IKobayashi 0:c88c3b616c00 371
IKobayashi 0:c88c3b616c00 372
IKobayashi 0:c88c3b616c00 373 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 374 \defgroup CMSIS_SCB System Control Block (SCB)
IKobayashi 0:c88c3b616c00 375 \brief Type definitions for the System Control Block Registers
IKobayashi 0:c88c3b616c00 376 @{
IKobayashi 0:c88c3b616c00 377 */
IKobayashi 0:c88c3b616c00 378
IKobayashi 0:c88c3b616c00 379 /** \brief Structure type to access the System Control Block (SCB).
IKobayashi 0:c88c3b616c00 380 */
IKobayashi 0:c88c3b616c00 381 typedef struct
IKobayashi 0:c88c3b616c00 382 {
IKobayashi 0:c88c3b616c00 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
IKobayashi 0:c88c3b616c00 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
IKobayashi 0:c88c3b616c00 385 #if (__VTOR_PRESENT == 1)
IKobayashi 0:c88c3b616c00 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
IKobayashi 0:c88c3b616c00 387 #else
IKobayashi 0:c88c3b616c00 388 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 389 #endif
IKobayashi 0:c88c3b616c00 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
IKobayashi 0:c88c3b616c00 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
IKobayashi 0:c88c3b616c00 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
IKobayashi 0:c88c3b616c00 393 uint32_t RESERVED1;
IKobayashi 0:c88c3b616c00 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
IKobayashi 0:c88c3b616c00 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
IKobayashi 0:c88c3b616c00 396 } SCB_Type;
IKobayashi 0:c88c3b616c00 397
IKobayashi 0:c88c3b616c00 398 /* SCB CPUID Register Definitions */
IKobayashi 0:c88c3b616c00 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
IKobayashi 0:c88c3b616c00 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
IKobayashi 0:c88c3b616c00 401
IKobayashi 0:c88c3b616c00 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
IKobayashi 0:c88c3b616c00 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
IKobayashi 0:c88c3b616c00 404
IKobayashi 0:c88c3b616c00 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
IKobayashi 0:c88c3b616c00 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
IKobayashi 0:c88c3b616c00 407
IKobayashi 0:c88c3b616c00 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
IKobayashi 0:c88c3b616c00 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
IKobayashi 0:c88c3b616c00 410
IKobayashi 0:c88c3b616c00 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
IKobayashi 0:c88c3b616c00 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
IKobayashi 0:c88c3b616c00 413
IKobayashi 0:c88c3b616c00 414 /* SCB Interrupt Control State Register Definitions */
IKobayashi 0:c88c3b616c00 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
IKobayashi 0:c88c3b616c00 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
IKobayashi 0:c88c3b616c00 417
IKobayashi 0:c88c3b616c00 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
IKobayashi 0:c88c3b616c00 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
IKobayashi 0:c88c3b616c00 420
IKobayashi 0:c88c3b616c00 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
IKobayashi 0:c88c3b616c00 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
IKobayashi 0:c88c3b616c00 423
IKobayashi 0:c88c3b616c00 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
IKobayashi 0:c88c3b616c00 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
IKobayashi 0:c88c3b616c00 426
IKobayashi 0:c88c3b616c00 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
IKobayashi 0:c88c3b616c00 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
IKobayashi 0:c88c3b616c00 429
IKobayashi 0:c88c3b616c00 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
IKobayashi 0:c88c3b616c00 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
IKobayashi 0:c88c3b616c00 432
IKobayashi 0:c88c3b616c00 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
IKobayashi 0:c88c3b616c00 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
IKobayashi 0:c88c3b616c00 435
IKobayashi 0:c88c3b616c00 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
IKobayashi 0:c88c3b616c00 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
IKobayashi 0:c88c3b616c00 438
IKobayashi 0:c88c3b616c00 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
IKobayashi 0:c88c3b616c00 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
IKobayashi 0:c88c3b616c00 441
IKobayashi 0:c88c3b616c00 442 #if (__VTOR_PRESENT == 1)
IKobayashi 0:c88c3b616c00 443 /* SCB Interrupt Control State Register Definitions */
IKobayashi 0:c88c3b616c00 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
IKobayashi 0:c88c3b616c00 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
IKobayashi 0:c88c3b616c00 446 #endif
IKobayashi 0:c88c3b616c00 447
IKobayashi 0:c88c3b616c00 448 /* SCB Application Interrupt and Reset Control Register Definitions */
IKobayashi 0:c88c3b616c00 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
IKobayashi 0:c88c3b616c00 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
IKobayashi 0:c88c3b616c00 451
IKobayashi 0:c88c3b616c00 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
IKobayashi 0:c88c3b616c00 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
IKobayashi 0:c88c3b616c00 454
IKobayashi 0:c88c3b616c00 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
IKobayashi 0:c88c3b616c00 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
IKobayashi 0:c88c3b616c00 457
IKobayashi 0:c88c3b616c00 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
IKobayashi 0:c88c3b616c00 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
IKobayashi 0:c88c3b616c00 460
IKobayashi 0:c88c3b616c00 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
IKobayashi 0:c88c3b616c00 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
IKobayashi 0:c88c3b616c00 463
IKobayashi 0:c88c3b616c00 464 /* SCB System Control Register Definitions */
IKobayashi 0:c88c3b616c00 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
IKobayashi 0:c88c3b616c00 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
IKobayashi 0:c88c3b616c00 467
IKobayashi 0:c88c3b616c00 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
IKobayashi 0:c88c3b616c00 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
IKobayashi 0:c88c3b616c00 470
IKobayashi 0:c88c3b616c00 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
IKobayashi 0:c88c3b616c00 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
IKobayashi 0:c88c3b616c00 473
IKobayashi 0:c88c3b616c00 474 /* SCB Configuration Control Register Definitions */
IKobayashi 0:c88c3b616c00 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
IKobayashi 0:c88c3b616c00 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
IKobayashi 0:c88c3b616c00 477
IKobayashi 0:c88c3b616c00 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
IKobayashi 0:c88c3b616c00 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
IKobayashi 0:c88c3b616c00 480
IKobayashi 0:c88c3b616c00 481 /* SCB System Handler Control and State Register Definitions */
IKobayashi 0:c88c3b616c00 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
IKobayashi 0:c88c3b616c00 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
IKobayashi 0:c88c3b616c00 484
IKobayashi 0:c88c3b616c00 485 /*@} end of group CMSIS_SCB */
IKobayashi 0:c88c3b616c00 486
IKobayashi 0:c88c3b616c00 487
IKobayashi 0:c88c3b616c00 488 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
IKobayashi 0:c88c3b616c00 490 \brief Type definitions for the System Timer Registers.
IKobayashi 0:c88c3b616c00 491 @{
IKobayashi 0:c88c3b616c00 492 */
IKobayashi 0:c88c3b616c00 493
IKobayashi 0:c88c3b616c00 494 /** \brief Structure type to access the System Timer (SysTick).
IKobayashi 0:c88c3b616c00 495 */
IKobayashi 0:c88c3b616c00 496 typedef struct
IKobayashi 0:c88c3b616c00 497 {
IKobayashi 0:c88c3b616c00 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
IKobayashi 0:c88c3b616c00 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
IKobayashi 0:c88c3b616c00 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
IKobayashi 0:c88c3b616c00 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
IKobayashi 0:c88c3b616c00 502 } SysTick_Type;
IKobayashi 0:c88c3b616c00 503
IKobayashi 0:c88c3b616c00 504 /* SysTick Control / Status Register Definitions */
IKobayashi 0:c88c3b616c00 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
IKobayashi 0:c88c3b616c00 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
IKobayashi 0:c88c3b616c00 507
IKobayashi 0:c88c3b616c00 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
IKobayashi 0:c88c3b616c00 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
IKobayashi 0:c88c3b616c00 510
IKobayashi 0:c88c3b616c00 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
IKobayashi 0:c88c3b616c00 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
IKobayashi 0:c88c3b616c00 513
IKobayashi 0:c88c3b616c00 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
IKobayashi 0:c88c3b616c00 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
IKobayashi 0:c88c3b616c00 516
IKobayashi 0:c88c3b616c00 517 /* SysTick Reload Register Definitions */
IKobayashi 0:c88c3b616c00 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
IKobayashi 0:c88c3b616c00 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
IKobayashi 0:c88c3b616c00 520
IKobayashi 0:c88c3b616c00 521 /* SysTick Current Register Definitions */
IKobayashi 0:c88c3b616c00 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
IKobayashi 0:c88c3b616c00 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
IKobayashi 0:c88c3b616c00 524
IKobayashi 0:c88c3b616c00 525 /* SysTick Calibration Register Definitions */
IKobayashi 0:c88c3b616c00 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
IKobayashi 0:c88c3b616c00 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
IKobayashi 0:c88c3b616c00 528
IKobayashi 0:c88c3b616c00 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
IKobayashi 0:c88c3b616c00 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
IKobayashi 0:c88c3b616c00 531
IKobayashi 0:c88c3b616c00 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
IKobayashi 0:c88c3b616c00 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
IKobayashi 0:c88c3b616c00 534
IKobayashi 0:c88c3b616c00 535 /*@} end of group CMSIS_SysTick */
IKobayashi 0:c88c3b616c00 536
IKobayashi 0:c88c3b616c00 537 #if (__MPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 538 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
IKobayashi 0:c88c3b616c00 540 \brief Type definitions for the Memory Protection Unit (MPU)
IKobayashi 0:c88c3b616c00 541 @{
IKobayashi 0:c88c3b616c00 542 */
IKobayashi 0:c88c3b616c00 543
IKobayashi 0:c88c3b616c00 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
IKobayashi 0:c88c3b616c00 545 */
IKobayashi 0:c88c3b616c00 546 typedef struct
IKobayashi 0:c88c3b616c00 547 {
IKobayashi 0:c88c3b616c00 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
IKobayashi 0:c88c3b616c00 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
IKobayashi 0:c88c3b616c00 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
IKobayashi 0:c88c3b616c00 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
IKobayashi 0:c88c3b616c00 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 553 } MPU_Type;
IKobayashi 0:c88c3b616c00 554
IKobayashi 0:c88c3b616c00 555 /* MPU Type Register */
IKobayashi 0:c88c3b616c00 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
IKobayashi 0:c88c3b616c00 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
IKobayashi 0:c88c3b616c00 558
IKobayashi 0:c88c3b616c00 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
IKobayashi 0:c88c3b616c00 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
IKobayashi 0:c88c3b616c00 561
IKobayashi 0:c88c3b616c00 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
IKobayashi 0:c88c3b616c00 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
IKobayashi 0:c88c3b616c00 564
IKobayashi 0:c88c3b616c00 565 /* MPU Control Register */
IKobayashi 0:c88c3b616c00 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
IKobayashi 0:c88c3b616c00 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
IKobayashi 0:c88c3b616c00 568
IKobayashi 0:c88c3b616c00 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
IKobayashi 0:c88c3b616c00 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
IKobayashi 0:c88c3b616c00 571
IKobayashi 0:c88c3b616c00 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
IKobayashi 0:c88c3b616c00 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
IKobayashi 0:c88c3b616c00 574
IKobayashi 0:c88c3b616c00 575 /* MPU Region Number Register */
IKobayashi 0:c88c3b616c00 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
IKobayashi 0:c88c3b616c00 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
IKobayashi 0:c88c3b616c00 578
IKobayashi 0:c88c3b616c00 579 /* MPU Region Base Address Register */
IKobayashi 0:c88c3b616c00 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
IKobayashi 0:c88c3b616c00 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
IKobayashi 0:c88c3b616c00 582
IKobayashi 0:c88c3b616c00 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
IKobayashi 0:c88c3b616c00 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
IKobayashi 0:c88c3b616c00 585
IKobayashi 0:c88c3b616c00 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
IKobayashi 0:c88c3b616c00 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
IKobayashi 0:c88c3b616c00 588
IKobayashi 0:c88c3b616c00 589 /* MPU Region Attribute and Size Register */
IKobayashi 0:c88c3b616c00 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
IKobayashi 0:c88c3b616c00 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
IKobayashi 0:c88c3b616c00 592
IKobayashi 0:c88c3b616c00 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
IKobayashi 0:c88c3b616c00 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
IKobayashi 0:c88c3b616c00 595
IKobayashi 0:c88c3b616c00 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
IKobayashi 0:c88c3b616c00 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
IKobayashi 0:c88c3b616c00 598
IKobayashi 0:c88c3b616c00 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
IKobayashi 0:c88c3b616c00 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
IKobayashi 0:c88c3b616c00 601
IKobayashi 0:c88c3b616c00 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
IKobayashi 0:c88c3b616c00 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
IKobayashi 0:c88c3b616c00 604
IKobayashi 0:c88c3b616c00 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
IKobayashi 0:c88c3b616c00 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
IKobayashi 0:c88c3b616c00 607
IKobayashi 0:c88c3b616c00 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
IKobayashi 0:c88c3b616c00 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
IKobayashi 0:c88c3b616c00 610
IKobayashi 0:c88c3b616c00 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
IKobayashi 0:c88c3b616c00 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
IKobayashi 0:c88c3b616c00 613
IKobayashi 0:c88c3b616c00 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
IKobayashi 0:c88c3b616c00 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
IKobayashi 0:c88c3b616c00 616
IKobayashi 0:c88c3b616c00 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
IKobayashi 0:c88c3b616c00 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
IKobayashi 0:c88c3b616c00 619
IKobayashi 0:c88c3b616c00 620 /*@} end of group CMSIS_MPU */
IKobayashi 0:c88c3b616c00 621 #endif
IKobayashi 0:c88c3b616c00 622
IKobayashi 0:c88c3b616c00 623
IKobayashi 0:c88c3b616c00 624 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
IKobayashi 0:c88c3b616c00 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
IKobayashi 0:c88c3b616c00 627 are only accessible over DAP and not via processor. Therefore
IKobayashi 0:c88c3b616c00 628 they are not covered by the Cortex-M0 header file.
IKobayashi 0:c88c3b616c00 629 @{
IKobayashi 0:c88c3b616c00 630 */
IKobayashi 0:c88c3b616c00 631 /*@} end of group CMSIS_CoreDebug */
IKobayashi 0:c88c3b616c00 632
IKobayashi 0:c88c3b616c00 633
IKobayashi 0:c88c3b616c00 634 /** \ingroup CMSIS_core_register
IKobayashi 0:c88c3b616c00 635 \defgroup CMSIS_core_base Core Definitions
IKobayashi 0:c88c3b616c00 636 \brief Definitions for base addresses, unions, and structures.
IKobayashi 0:c88c3b616c00 637 @{
IKobayashi 0:c88c3b616c00 638 */
IKobayashi 0:c88c3b616c00 639
IKobayashi 0:c88c3b616c00 640 /* Memory mapping of Cortex-M0+ Hardware */
IKobayashi 0:c88c3b616c00 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
IKobayashi 0:c88c3b616c00 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
IKobayashi 0:c88c3b616c00 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
IKobayashi 0:c88c3b616c00 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
IKobayashi 0:c88c3b616c00 645
IKobayashi 0:c88c3b616c00 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
IKobayashi 0:c88c3b616c00 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
IKobayashi 0:c88c3b616c00 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
IKobayashi 0:c88c3b616c00 649
IKobayashi 0:c88c3b616c00 650 #if (__MPU_PRESENT == 1)
IKobayashi 0:c88c3b616c00 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
IKobayashi 0:c88c3b616c00 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
IKobayashi 0:c88c3b616c00 653 #endif
IKobayashi 0:c88c3b616c00 654
IKobayashi 0:c88c3b616c00 655 /*@} */
IKobayashi 0:c88c3b616c00 656
IKobayashi 0:c88c3b616c00 657
IKobayashi 0:c88c3b616c00 658
IKobayashi 0:c88c3b616c00 659 /*******************************************************************************
IKobayashi 0:c88c3b616c00 660 * Hardware Abstraction Layer
IKobayashi 0:c88c3b616c00 661 Core Function Interface contains:
IKobayashi 0:c88c3b616c00 662 - Core NVIC Functions
IKobayashi 0:c88c3b616c00 663 - Core SysTick Functions
IKobayashi 0:c88c3b616c00 664 - Core Register Access Functions
IKobayashi 0:c88c3b616c00 665 ******************************************************************************/
IKobayashi 0:c88c3b616c00 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
IKobayashi 0:c88c3b616c00 667 */
IKobayashi 0:c88c3b616c00 668
IKobayashi 0:c88c3b616c00 669
IKobayashi 0:c88c3b616c00 670
IKobayashi 0:c88c3b616c00 671 /* ########################## NVIC functions #################################### */
IKobayashi 0:c88c3b616c00 672 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
IKobayashi 0:c88c3b616c00 674 \brief Functions that manage interrupts and exceptions via the NVIC.
IKobayashi 0:c88c3b616c00 675 @{
IKobayashi 0:c88c3b616c00 676 */
IKobayashi 0:c88c3b616c00 677
IKobayashi 0:c88c3b616c00 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
IKobayashi 0:c88c3b616c00 679 /* The following MACROS handle generation of the register offset and byte masks */
IKobayashi 0:c88c3b616c00 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
IKobayashi 0:c88c3b616c00 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
IKobayashi 0:c88c3b616c00 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
IKobayashi 0:c88c3b616c00 683
IKobayashi 0:c88c3b616c00 684
IKobayashi 0:c88c3b616c00 685 /** \brief Enable External Interrupt
IKobayashi 0:c88c3b616c00 686
IKobayashi 0:c88c3b616c00 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi 0:c88c3b616c00 688
IKobayashi 0:c88c3b616c00 689 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 690 */
IKobayashi 0:c88c3b616c00 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 692 {
IKobayashi 0:c88c3b616c00 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 694 }
IKobayashi 0:c88c3b616c00 695
IKobayashi 0:c88c3b616c00 696
IKobayashi 0:c88c3b616c00 697 /** \brief Disable External Interrupt
IKobayashi 0:c88c3b616c00 698
IKobayashi 0:c88c3b616c00 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
IKobayashi 0:c88c3b616c00 700
IKobayashi 0:c88c3b616c00 701 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 702 */
IKobayashi 0:c88c3b616c00 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 704 {
IKobayashi 0:c88c3b616c00 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 706 __DSB();
IKobayashi 0:c88c3b616c00 707 __ISB();
IKobayashi 0:c88c3b616c00 708 }
IKobayashi 0:c88c3b616c00 709
IKobayashi 0:c88c3b616c00 710
IKobayashi 0:c88c3b616c00 711 /** \brief Get Pending Interrupt
IKobayashi 0:c88c3b616c00 712
IKobayashi 0:c88c3b616c00 713 The function reads the pending register in the NVIC and returns the pending bit
IKobayashi 0:c88c3b616c00 714 for the specified interrupt.
IKobayashi 0:c88c3b616c00 715
IKobayashi 0:c88c3b616c00 716 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 717
IKobayashi 0:c88c3b616c00 718 \return 0 Interrupt status is not pending.
IKobayashi 0:c88c3b616c00 719 \return 1 Interrupt status is pending.
IKobayashi 0:c88c3b616c00 720 */
IKobayashi 0:c88c3b616c00 721 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 722 {
IKobayashi 0:c88c3b616c00 723 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
IKobayashi 0:c88c3b616c00 724 }
IKobayashi 0:c88c3b616c00 725
IKobayashi 0:c88c3b616c00 726
IKobayashi 0:c88c3b616c00 727 /** \brief Set Pending Interrupt
IKobayashi 0:c88c3b616c00 728
IKobayashi 0:c88c3b616c00 729 The function sets the pending bit of an external interrupt.
IKobayashi 0:c88c3b616c00 730
IKobayashi 0:c88c3b616c00 731 \param [in] IRQn Interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 732 */
IKobayashi 0:c88c3b616c00 733 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 734 {
IKobayashi 0:c88c3b616c00 735 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 736 }
IKobayashi 0:c88c3b616c00 737
IKobayashi 0:c88c3b616c00 738
IKobayashi 0:c88c3b616c00 739 /** \brief Clear Pending Interrupt
IKobayashi 0:c88c3b616c00 740
IKobayashi 0:c88c3b616c00 741 The function clears the pending bit of an external interrupt.
IKobayashi 0:c88c3b616c00 742
IKobayashi 0:c88c3b616c00 743 \param [in] IRQn External interrupt number. Value cannot be negative.
IKobayashi 0:c88c3b616c00 744 */
IKobayashi 0:c88c3b616c00 745 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 746 {
IKobayashi 0:c88c3b616c00 747 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
IKobayashi 0:c88c3b616c00 748 }
IKobayashi 0:c88c3b616c00 749
IKobayashi 0:c88c3b616c00 750
IKobayashi 0:c88c3b616c00 751 /** \brief Set Interrupt Priority
IKobayashi 0:c88c3b616c00 752
IKobayashi 0:c88c3b616c00 753 The function sets the priority of an interrupt.
IKobayashi 0:c88c3b616c00 754
IKobayashi 0:c88c3b616c00 755 \note The priority cannot be set for every core interrupt.
IKobayashi 0:c88c3b616c00 756
IKobayashi 0:c88c3b616c00 757 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 758 \param [in] priority Priority to set.
IKobayashi 0:c88c3b616c00 759 */
IKobayashi 0:c88c3b616c00 760 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
IKobayashi 0:c88c3b616c00 761 {
IKobayashi 0:c88c3b616c00 762 if((int32_t)(IRQn) < 0) {
IKobayashi 0:c88c3b616c00 763 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
IKobayashi 0:c88c3b616c00 764 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
IKobayashi 0:c88c3b616c00 765 }
IKobayashi 0:c88c3b616c00 766 else {
IKobayashi 0:c88c3b616c00 767 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
IKobayashi 0:c88c3b616c00 768 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
IKobayashi 0:c88c3b616c00 769 }
IKobayashi 0:c88c3b616c00 770 }
IKobayashi 0:c88c3b616c00 771
IKobayashi 0:c88c3b616c00 772
IKobayashi 0:c88c3b616c00 773 /** \brief Get Interrupt Priority
IKobayashi 0:c88c3b616c00 774
IKobayashi 0:c88c3b616c00 775 The function reads the priority of an interrupt. The interrupt
IKobayashi 0:c88c3b616c00 776 number can be positive to specify an external (device specific)
IKobayashi 0:c88c3b616c00 777 interrupt, or negative to specify an internal (core) interrupt.
IKobayashi 0:c88c3b616c00 778
IKobayashi 0:c88c3b616c00 779
IKobayashi 0:c88c3b616c00 780 \param [in] IRQn Interrupt number.
IKobayashi 0:c88c3b616c00 781 \return Interrupt Priority. Value is aligned automatically to the implemented
IKobayashi 0:c88c3b616c00 782 priority bits of the microcontroller.
IKobayashi 0:c88c3b616c00 783 */
IKobayashi 0:c88c3b616c00 784 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
IKobayashi 0:c88c3b616c00 785 {
IKobayashi 0:c88c3b616c00 786
IKobayashi 0:c88c3b616c00 787 if((int32_t)(IRQn) < 0) {
IKobayashi 0:c88c3b616c00 788 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
IKobayashi 0:c88c3b616c00 789 }
IKobayashi 0:c88c3b616c00 790 else {
IKobayashi 0:c88c3b616c00 791 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
IKobayashi 0:c88c3b616c00 792 }
IKobayashi 0:c88c3b616c00 793 }
IKobayashi 0:c88c3b616c00 794
IKobayashi 0:c88c3b616c00 795
IKobayashi 0:c88c3b616c00 796 /** \brief System Reset
IKobayashi 0:c88c3b616c00 797
IKobayashi 0:c88c3b616c00 798 The function initiates a system reset request to reset the MCU.
IKobayashi 0:c88c3b616c00 799 */
IKobayashi 0:c88c3b616c00 800 __STATIC_INLINE void NVIC_SystemReset(void)
IKobayashi 0:c88c3b616c00 801 {
IKobayashi 0:c88c3b616c00 802 __DSB(); /* Ensure all outstanding memory accesses included
IKobayashi 0:c88c3b616c00 803 buffered write are completed before reset */
IKobayashi 0:c88c3b616c00 804 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
IKobayashi 0:c88c3b616c00 805 SCB_AIRCR_SYSRESETREQ_Msk);
IKobayashi 0:c88c3b616c00 806 __DSB(); /* Ensure completion of memory access */
IKobayashi 0:c88c3b616c00 807 while(1) { __NOP(); } /* wait until reset */
IKobayashi 0:c88c3b616c00 808 }
IKobayashi 0:c88c3b616c00 809
IKobayashi 0:c88c3b616c00 810 /*@} end of CMSIS_Core_NVICFunctions */
IKobayashi 0:c88c3b616c00 811
IKobayashi 0:c88c3b616c00 812
IKobayashi 0:c88c3b616c00 813
IKobayashi 0:c88c3b616c00 814 /* ################################## SysTick function ############################################ */
IKobayashi 0:c88c3b616c00 815 /** \ingroup CMSIS_Core_FunctionInterface
IKobayashi 0:c88c3b616c00 816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
IKobayashi 0:c88c3b616c00 817 \brief Functions that configure the System.
IKobayashi 0:c88c3b616c00 818 @{
IKobayashi 0:c88c3b616c00 819 */
IKobayashi 0:c88c3b616c00 820
IKobayashi 0:c88c3b616c00 821 #if (__Vendor_SysTickConfig == 0)
IKobayashi 0:c88c3b616c00 822
IKobayashi 0:c88c3b616c00 823 /** \brief System Tick Configuration
IKobayashi 0:c88c3b616c00 824
IKobayashi 0:c88c3b616c00 825 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
IKobayashi 0:c88c3b616c00 826 Counter is in free running mode to generate periodic interrupts.
IKobayashi 0:c88c3b616c00 827
IKobayashi 0:c88c3b616c00 828 \param [in] ticks Number of ticks between two interrupts.
IKobayashi 0:c88c3b616c00 829
IKobayashi 0:c88c3b616c00 830 \return 0 Function succeeded.
IKobayashi 0:c88c3b616c00 831 \return 1 Function failed.
IKobayashi 0:c88c3b616c00 832
IKobayashi 0:c88c3b616c00 833 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
IKobayashi 0:c88c3b616c00 834 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
IKobayashi 0:c88c3b616c00 835 must contain a vendor-specific implementation of this function.
IKobayashi 0:c88c3b616c00 836
IKobayashi 0:c88c3b616c00 837 */
IKobayashi 0:c88c3b616c00 838 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
IKobayashi 0:c88c3b616c00 839 {
IKobayashi 0:c88c3b616c00 840 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
IKobayashi 0:c88c3b616c00 841
IKobayashi 0:c88c3b616c00 842 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
IKobayashi 0:c88c3b616c00 843 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
IKobayashi 0:c88c3b616c00 844 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
IKobayashi 0:c88c3b616c00 845 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
IKobayashi 0:c88c3b616c00 846 SysTick_CTRL_TICKINT_Msk |
IKobayashi 0:c88c3b616c00 847 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
IKobayashi 0:c88c3b616c00 848 return (0UL); /* Function successful */
IKobayashi 0:c88c3b616c00 849 }
IKobayashi 0:c88c3b616c00 850
IKobayashi 0:c88c3b616c00 851 #endif
IKobayashi 0:c88c3b616c00 852
IKobayashi 0:c88c3b616c00 853 /*@} end of CMSIS_Core_SysTickFunctions */
IKobayashi 0:c88c3b616c00 854
IKobayashi 0:c88c3b616c00 855
IKobayashi 0:c88c3b616c00 856
IKobayashi 0:c88c3b616c00 857
IKobayashi 0:c88c3b616c00 858 #ifdef __cplusplus
IKobayashi 0:c88c3b616c00 859 }
IKobayashi 0:c88c3b616c00 860 #endif
IKobayashi 0:c88c3b616c00 861
IKobayashi 0:c88c3b616c00 862 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
IKobayashi 0:c88c3b616c00 863
IKobayashi 0:c88c3b616c00 864 #endif /* __CMSIS_GENERIC */