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mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/device/LPC17xx.h@0:c88c3b616c00, 2020-03-16 (annotated)

Committer:
IKobayashi
Date:
Mon Mar 16 23:37:42 2020 +0900
Revision:
0:c88c3b616c00
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IKobayashi 0:c88c3b616c00 1 /**************************************************************************//**
IKobayashi 0:c88c3b616c00 2 * @file LPC17xx.h
IKobayashi 0:c88c3b616c00 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
IKobayashi 0:c88c3b616c00 4 * NXP LPC17xx Device Series
IKobayashi 0:c88c3b616c00 5 * @version: V1.09
IKobayashi 0:c88c3b616c00 6 * @date: 17. March 2010
IKobayashi 0:c88c3b616c00 7
IKobayashi 0:c88c3b616c00 8 *
IKobayashi 0:c88c3b616c00 9 * @note
IKobayashi 0:c88c3b616c00 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
IKobayashi 0:c88c3b616c00 11 *
IKobayashi 0:c88c3b616c00 12 * @par
IKobayashi 0:c88c3b616c00 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
IKobayashi 0:c88c3b616c00 14 * processor based microcontrollers. This file can be freely distributed
IKobayashi 0:c88c3b616c00 15 * within development tools that are supporting such ARM based processors.
IKobayashi 0:c88c3b616c00 16 *
IKobayashi 0:c88c3b616c00 17 * @par
IKobayashi 0:c88c3b616c00 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
IKobayashi 0:c88c3b616c00 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
IKobayashi 0:c88c3b616c00 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
IKobayashi 0:c88c3b616c00 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
IKobayashi 0:c88c3b616c00 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
IKobayashi 0:c88c3b616c00 23 *
IKobayashi 0:c88c3b616c00 24 ******************************************************************************/
IKobayashi 0:c88c3b616c00 25
IKobayashi 0:c88c3b616c00 26
IKobayashi 0:c88c3b616c00 27 #ifndef __LPC17xx_H__
IKobayashi 0:c88c3b616c00 28 #define __LPC17xx_H__
IKobayashi 0:c88c3b616c00 29
IKobayashi 0:c88c3b616c00 30 /*
IKobayashi 0:c88c3b616c00 31 * ==========================================================================
IKobayashi 0:c88c3b616c00 32 * ---------- Interrupt Number Definition -----------------------------------
IKobayashi 0:c88c3b616c00 33 * ==========================================================================
IKobayashi 0:c88c3b616c00 34 */
IKobayashi 0:c88c3b616c00 35
IKobayashi 0:c88c3b616c00 36 typedef enum IRQn
IKobayashi 0:c88c3b616c00 37 {
IKobayashi 0:c88c3b616c00 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
IKobayashi 0:c88c3b616c00 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
IKobayashi 0:c88c3b616c00 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
IKobayashi 0:c88c3b616c00 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
IKobayashi 0:c88c3b616c00 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
IKobayashi 0:c88c3b616c00 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
IKobayashi 0:c88c3b616c00 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
IKobayashi 0:c88c3b616c00 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
IKobayashi 0:c88c3b616c00 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
IKobayashi 0:c88c3b616c00 47
IKobayashi 0:c88c3b616c00 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
IKobayashi 0:c88c3b616c00 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
IKobayashi 0:c88c3b616c00 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
IKobayashi 0:c88c3b616c00 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
IKobayashi 0:c88c3b616c00 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
IKobayashi 0:c88c3b616c00 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
IKobayashi 0:c88c3b616c00 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
IKobayashi 0:c88c3b616c00 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
IKobayashi 0:c88c3b616c00 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
IKobayashi 0:c88c3b616c00 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
IKobayashi 0:c88c3b616c00 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
IKobayashi 0:c88c3b616c00 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
IKobayashi 0:c88c3b616c00 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
IKobayashi 0:c88c3b616c00 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
IKobayashi 0:c88c3b616c00 62 SPI_IRQn = 13, /*!< SPI Interrupt */
IKobayashi 0:c88c3b616c00 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
IKobayashi 0:c88c3b616c00 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
IKobayashi 0:c88c3b616c00 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
IKobayashi 0:c88c3b616c00 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
IKobayashi 0:c88c3b616c00 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
IKobayashi 0:c88c3b616c00 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
IKobayashi 0:c88c3b616c00 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
IKobayashi 0:c88c3b616c00 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
IKobayashi 0:c88c3b616c00 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
IKobayashi 0:c88c3b616c00 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
IKobayashi 0:c88c3b616c00 73 USB_IRQn = 24, /*!< USB Interrupt */
IKobayashi 0:c88c3b616c00 74 CAN_IRQn = 25, /*!< CAN Interrupt */
IKobayashi 0:c88c3b616c00 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
IKobayashi 0:c88c3b616c00 76 I2S_IRQn = 27, /*!< I2S Interrupt */
IKobayashi 0:c88c3b616c00 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
IKobayashi 0:c88c3b616c00 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
IKobayashi 0:c88c3b616c00 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
IKobayashi 0:c88c3b616c00 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
IKobayashi 0:c88c3b616c00 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
IKobayashi 0:c88c3b616c00 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
IKobayashi 0:c88c3b616c00 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
IKobayashi 0:c88c3b616c00 84 } IRQn_Type;
IKobayashi 0:c88c3b616c00 85
IKobayashi 0:c88c3b616c00 86
IKobayashi 0:c88c3b616c00 87 /*
IKobayashi 0:c88c3b616c00 88 * ==========================================================================
IKobayashi 0:c88c3b616c00 89 * ----------- Processor and Core Peripheral Section ------------------------
IKobayashi 0:c88c3b616c00 90 * ==========================================================================
IKobayashi 0:c88c3b616c00 91 */
IKobayashi 0:c88c3b616c00 92
IKobayashi 0:c88c3b616c00 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
IKobayashi 0:c88c3b616c00 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
IKobayashi 0:c88c3b616c00 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
IKobayashi 0:c88c3b616c00 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
IKobayashi 0:c88c3b616c00 97
IKobayashi 0:c88c3b616c00 98
IKobayashi 0:c88c3b616c00 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
IKobayashi 0:c88c3b616c00 100 #include "system_LPC17xx.h" /* System Header */
IKobayashi 0:c88c3b616c00 101
IKobayashi 0:c88c3b616c00 102
IKobayashi 0:c88c3b616c00 103 /******************************************************************************/
IKobayashi 0:c88c3b616c00 104 /* Device Specific Peripheral registers structures */
IKobayashi 0:c88c3b616c00 105 /******************************************************************************/
IKobayashi 0:c88c3b616c00 106
IKobayashi 0:c88c3b616c00 107 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 108 #pragma anon_unions
IKobayashi 0:c88c3b616c00 109 #endif
IKobayashi 0:c88c3b616c00 110
IKobayashi 0:c88c3b616c00 111 /*------------- System Control (SC) ------------------------------------------*/
IKobayashi 0:c88c3b616c00 112 typedef struct
IKobayashi 0:c88c3b616c00 113 {
IKobayashi 0:c88c3b616c00 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
IKobayashi 0:c88c3b616c00 115 uint32_t RESERVED0[31];
IKobayashi 0:c88c3b616c00 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
IKobayashi 0:c88c3b616c00 117 __IO uint32_t PLL0CFG;
IKobayashi 0:c88c3b616c00 118 __I uint32_t PLL0STAT;
IKobayashi 0:c88c3b616c00 119 __O uint32_t PLL0FEED;
IKobayashi 0:c88c3b616c00 120 uint32_t RESERVED1[4];
IKobayashi 0:c88c3b616c00 121 __IO uint32_t PLL1CON;
IKobayashi 0:c88c3b616c00 122 __IO uint32_t PLL1CFG;
IKobayashi 0:c88c3b616c00 123 __I uint32_t PLL1STAT;
IKobayashi 0:c88c3b616c00 124 __O uint32_t PLL1FEED;
IKobayashi 0:c88c3b616c00 125 uint32_t RESERVED2[4];
IKobayashi 0:c88c3b616c00 126 __IO uint32_t PCON;
IKobayashi 0:c88c3b616c00 127 __IO uint32_t PCONP;
IKobayashi 0:c88c3b616c00 128 uint32_t RESERVED3[15];
IKobayashi 0:c88c3b616c00 129 __IO uint32_t CCLKCFG;
IKobayashi 0:c88c3b616c00 130 __IO uint32_t USBCLKCFG;
IKobayashi 0:c88c3b616c00 131 __IO uint32_t CLKSRCSEL;
IKobayashi 0:c88c3b616c00 132 __IO uint32_t CANSLEEPCLR;
IKobayashi 0:c88c3b616c00 133 __IO uint32_t CANWAKEFLAGS;
IKobayashi 0:c88c3b616c00 134 uint32_t RESERVED4[10];
IKobayashi 0:c88c3b616c00 135 __IO uint32_t EXTINT; /* External Interrupts */
IKobayashi 0:c88c3b616c00 136 uint32_t RESERVED5;
IKobayashi 0:c88c3b616c00 137 __IO uint32_t EXTMODE;
IKobayashi 0:c88c3b616c00 138 __IO uint32_t EXTPOLAR;
IKobayashi 0:c88c3b616c00 139 uint32_t RESERVED6[12];
IKobayashi 0:c88c3b616c00 140 __IO uint32_t RSID; /* Reset */
IKobayashi 0:c88c3b616c00 141 uint32_t RESERVED7[7];
IKobayashi 0:c88c3b616c00 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
IKobayashi 0:c88c3b616c00 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
IKobayashi 0:c88c3b616c00 144 __IO uint32_t PCLKSEL0;
IKobayashi 0:c88c3b616c00 145 __IO uint32_t PCLKSEL1;
IKobayashi 0:c88c3b616c00 146 uint32_t RESERVED8[4];
IKobayashi 0:c88c3b616c00 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
IKobayashi 0:c88c3b616c00 148 __IO uint32_t DMAREQSEL;
IKobayashi 0:c88c3b616c00 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
IKobayashi 0:c88c3b616c00 150 } LPC_SC_TypeDef;
IKobayashi 0:c88c3b616c00 151
IKobayashi 0:c88c3b616c00 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
IKobayashi 0:c88c3b616c00 153 typedef struct
IKobayashi 0:c88c3b616c00 154 {
IKobayashi 0:c88c3b616c00 155 __IO uint32_t PINSEL0;
IKobayashi 0:c88c3b616c00 156 __IO uint32_t PINSEL1;
IKobayashi 0:c88c3b616c00 157 __IO uint32_t PINSEL2;
IKobayashi 0:c88c3b616c00 158 __IO uint32_t PINSEL3;
IKobayashi 0:c88c3b616c00 159 __IO uint32_t PINSEL4;
IKobayashi 0:c88c3b616c00 160 __IO uint32_t PINSEL5;
IKobayashi 0:c88c3b616c00 161 __IO uint32_t PINSEL6;
IKobayashi 0:c88c3b616c00 162 __IO uint32_t PINSEL7;
IKobayashi 0:c88c3b616c00 163 __IO uint32_t PINSEL8;
IKobayashi 0:c88c3b616c00 164 __IO uint32_t PINSEL9;
IKobayashi 0:c88c3b616c00 165 __IO uint32_t PINSEL10;
IKobayashi 0:c88c3b616c00 166 uint32_t RESERVED0[5];
IKobayashi 0:c88c3b616c00 167 __IO uint32_t PINMODE0;
IKobayashi 0:c88c3b616c00 168 __IO uint32_t PINMODE1;
IKobayashi 0:c88c3b616c00 169 __IO uint32_t PINMODE2;
IKobayashi 0:c88c3b616c00 170 __IO uint32_t PINMODE3;
IKobayashi 0:c88c3b616c00 171 __IO uint32_t PINMODE4;
IKobayashi 0:c88c3b616c00 172 __IO uint32_t PINMODE5;
IKobayashi 0:c88c3b616c00 173 __IO uint32_t PINMODE6;
IKobayashi 0:c88c3b616c00 174 __IO uint32_t PINMODE7;
IKobayashi 0:c88c3b616c00 175 __IO uint32_t PINMODE8;
IKobayashi 0:c88c3b616c00 176 __IO uint32_t PINMODE9;
IKobayashi 0:c88c3b616c00 177 __IO uint32_t PINMODE_OD0;
IKobayashi 0:c88c3b616c00 178 __IO uint32_t PINMODE_OD1;
IKobayashi 0:c88c3b616c00 179 __IO uint32_t PINMODE_OD2;
IKobayashi 0:c88c3b616c00 180 __IO uint32_t PINMODE_OD3;
IKobayashi 0:c88c3b616c00 181 __IO uint32_t PINMODE_OD4;
IKobayashi 0:c88c3b616c00 182 __IO uint32_t I2CPADCFG;
IKobayashi 0:c88c3b616c00 183 } LPC_PINCON_TypeDef;
IKobayashi 0:c88c3b616c00 184
IKobayashi 0:c88c3b616c00 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
IKobayashi 0:c88c3b616c00 186 typedef struct
IKobayashi 0:c88c3b616c00 187 {
IKobayashi 0:c88c3b616c00 188 union {
IKobayashi 0:c88c3b616c00 189 __IO uint32_t FIODIR;
IKobayashi 0:c88c3b616c00 190 struct {
IKobayashi 0:c88c3b616c00 191 __IO uint16_t FIODIRL;
IKobayashi 0:c88c3b616c00 192 __IO uint16_t FIODIRH;
IKobayashi 0:c88c3b616c00 193 };
IKobayashi 0:c88c3b616c00 194 struct {
IKobayashi 0:c88c3b616c00 195 __IO uint8_t FIODIR0;
IKobayashi 0:c88c3b616c00 196 __IO uint8_t FIODIR1;
IKobayashi 0:c88c3b616c00 197 __IO uint8_t FIODIR2;
IKobayashi 0:c88c3b616c00 198 __IO uint8_t FIODIR3;
IKobayashi 0:c88c3b616c00 199 };
IKobayashi 0:c88c3b616c00 200 };
IKobayashi 0:c88c3b616c00 201 uint32_t RESERVED0[3];
IKobayashi 0:c88c3b616c00 202 union {
IKobayashi 0:c88c3b616c00 203 __IO uint32_t FIOMASK;
IKobayashi 0:c88c3b616c00 204 struct {
IKobayashi 0:c88c3b616c00 205 __IO uint16_t FIOMASKL;
IKobayashi 0:c88c3b616c00 206 __IO uint16_t FIOMASKH;
IKobayashi 0:c88c3b616c00 207 };
IKobayashi 0:c88c3b616c00 208 struct {
IKobayashi 0:c88c3b616c00 209 __IO uint8_t FIOMASK0;
IKobayashi 0:c88c3b616c00 210 __IO uint8_t FIOMASK1;
IKobayashi 0:c88c3b616c00 211 __IO uint8_t FIOMASK2;
IKobayashi 0:c88c3b616c00 212 __IO uint8_t FIOMASK3;
IKobayashi 0:c88c3b616c00 213 };
IKobayashi 0:c88c3b616c00 214 };
IKobayashi 0:c88c3b616c00 215 union {
IKobayashi 0:c88c3b616c00 216 __IO uint32_t FIOPIN;
IKobayashi 0:c88c3b616c00 217 struct {
IKobayashi 0:c88c3b616c00 218 __IO uint16_t FIOPINL;
IKobayashi 0:c88c3b616c00 219 __IO uint16_t FIOPINH;
IKobayashi 0:c88c3b616c00 220 };
IKobayashi 0:c88c3b616c00 221 struct {
IKobayashi 0:c88c3b616c00 222 __IO uint8_t FIOPIN0;
IKobayashi 0:c88c3b616c00 223 __IO uint8_t FIOPIN1;
IKobayashi 0:c88c3b616c00 224 __IO uint8_t FIOPIN2;
IKobayashi 0:c88c3b616c00 225 __IO uint8_t FIOPIN3;
IKobayashi 0:c88c3b616c00 226 };
IKobayashi 0:c88c3b616c00 227 };
IKobayashi 0:c88c3b616c00 228 union {
IKobayashi 0:c88c3b616c00 229 __IO uint32_t FIOSET;
IKobayashi 0:c88c3b616c00 230 struct {
IKobayashi 0:c88c3b616c00 231 __IO uint16_t FIOSETL;
IKobayashi 0:c88c3b616c00 232 __IO uint16_t FIOSETH;
IKobayashi 0:c88c3b616c00 233 };
IKobayashi 0:c88c3b616c00 234 struct {
IKobayashi 0:c88c3b616c00 235 __IO uint8_t FIOSET0;
IKobayashi 0:c88c3b616c00 236 __IO uint8_t FIOSET1;
IKobayashi 0:c88c3b616c00 237 __IO uint8_t FIOSET2;
IKobayashi 0:c88c3b616c00 238 __IO uint8_t FIOSET3;
IKobayashi 0:c88c3b616c00 239 };
IKobayashi 0:c88c3b616c00 240 };
IKobayashi 0:c88c3b616c00 241 union {
IKobayashi 0:c88c3b616c00 242 __O uint32_t FIOCLR;
IKobayashi 0:c88c3b616c00 243 struct {
IKobayashi 0:c88c3b616c00 244 __O uint16_t FIOCLRL;
IKobayashi 0:c88c3b616c00 245 __O uint16_t FIOCLRH;
IKobayashi 0:c88c3b616c00 246 };
IKobayashi 0:c88c3b616c00 247 struct {
IKobayashi 0:c88c3b616c00 248 __O uint8_t FIOCLR0;
IKobayashi 0:c88c3b616c00 249 __O uint8_t FIOCLR1;
IKobayashi 0:c88c3b616c00 250 __O uint8_t FIOCLR2;
IKobayashi 0:c88c3b616c00 251 __O uint8_t FIOCLR3;
IKobayashi 0:c88c3b616c00 252 };
IKobayashi 0:c88c3b616c00 253 };
IKobayashi 0:c88c3b616c00 254 } LPC_GPIO_TypeDef;
IKobayashi 0:c88c3b616c00 255
IKobayashi 0:c88c3b616c00 256 typedef struct
IKobayashi 0:c88c3b616c00 257 {
IKobayashi 0:c88c3b616c00 258 __I uint32_t IntStatus;
IKobayashi 0:c88c3b616c00 259 __I uint32_t IO0IntStatR;
IKobayashi 0:c88c3b616c00 260 __I uint32_t IO0IntStatF;
IKobayashi 0:c88c3b616c00 261 __O uint32_t IO0IntClr;
IKobayashi 0:c88c3b616c00 262 __IO uint32_t IO0IntEnR;
IKobayashi 0:c88c3b616c00 263 __IO uint32_t IO0IntEnF;
IKobayashi 0:c88c3b616c00 264 uint32_t RESERVED0[3];
IKobayashi 0:c88c3b616c00 265 __I uint32_t IO2IntStatR;
IKobayashi 0:c88c3b616c00 266 __I uint32_t IO2IntStatF;
IKobayashi 0:c88c3b616c00 267 __O uint32_t IO2IntClr;
IKobayashi 0:c88c3b616c00 268 __IO uint32_t IO2IntEnR;
IKobayashi 0:c88c3b616c00 269 __IO uint32_t IO2IntEnF;
IKobayashi 0:c88c3b616c00 270 } LPC_GPIOINT_TypeDef;
IKobayashi 0:c88c3b616c00 271
IKobayashi 0:c88c3b616c00 272 /*------------- Timer (TIM) --------------------------------------------------*/
IKobayashi 0:c88c3b616c00 273 typedef struct
IKobayashi 0:c88c3b616c00 274 {
IKobayashi 0:c88c3b616c00 275 __IO uint32_t IR;
IKobayashi 0:c88c3b616c00 276 __IO uint32_t TCR;
IKobayashi 0:c88c3b616c00 277 __IO uint32_t TC;
IKobayashi 0:c88c3b616c00 278 __IO uint32_t PR;
IKobayashi 0:c88c3b616c00 279 __IO uint32_t PC;
IKobayashi 0:c88c3b616c00 280 __IO uint32_t MCR;
IKobayashi 0:c88c3b616c00 281 __IO uint32_t MR0;
IKobayashi 0:c88c3b616c00 282 __IO uint32_t MR1;
IKobayashi 0:c88c3b616c00 283 __IO uint32_t MR2;
IKobayashi 0:c88c3b616c00 284 __IO uint32_t MR3;
IKobayashi 0:c88c3b616c00 285 __IO uint32_t CCR;
IKobayashi 0:c88c3b616c00 286 __I uint32_t CR0;
IKobayashi 0:c88c3b616c00 287 __I uint32_t CR1;
IKobayashi 0:c88c3b616c00 288 uint32_t RESERVED0[2];
IKobayashi 0:c88c3b616c00 289 __IO uint32_t EMR;
IKobayashi 0:c88c3b616c00 290 uint32_t RESERVED1[12];
IKobayashi 0:c88c3b616c00 291 __IO uint32_t CTCR;
IKobayashi 0:c88c3b616c00 292 } LPC_TIM_TypeDef;
IKobayashi 0:c88c3b616c00 293
IKobayashi 0:c88c3b616c00 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
IKobayashi 0:c88c3b616c00 295 typedef struct
IKobayashi 0:c88c3b616c00 296 {
IKobayashi 0:c88c3b616c00 297 __IO uint32_t IR;
IKobayashi 0:c88c3b616c00 298 __IO uint32_t TCR;
IKobayashi 0:c88c3b616c00 299 __IO uint32_t TC;
IKobayashi 0:c88c3b616c00 300 __IO uint32_t PR;
IKobayashi 0:c88c3b616c00 301 __IO uint32_t PC;
IKobayashi 0:c88c3b616c00 302 __IO uint32_t MCR;
IKobayashi 0:c88c3b616c00 303 __IO uint32_t MR0;
IKobayashi 0:c88c3b616c00 304 __IO uint32_t MR1;
IKobayashi 0:c88c3b616c00 305 __IO uint32_t MR2;
IKobayashi 0:c88c3b616c00 306 __IO uint32_t MR3;
IKobayashi 0:c88c3b616c00 307 __IO uint32_t CCR;
IKobayashi 0:c88c3b616c00 308 __I uint32_t CR0;
IKobayashi 0:c88c3b616c00 309 __I uint32_t CR1;
IKobayashi 0:c88c3b616c00 310 __I uint32_t CR2;
IKobayashi 0:c88c3b616c00 311 __I uint32_t CR3;
IKobayashi 0:c88c3b616c00 312 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 313 __IO uint32_t MR4;
IKobayashi 0:c88c3b616c00 314 __IO uint32_t MR5;
IKobayashi 0:c88c3b616c00 315 __IO uint32_t MR6;
IKobayashi 0:c88c3b616c00 316 __IO uint32_t PCR;
IKobayashi 0:c88c3b616c00 317 __IO uint32_t LER;
IKobayashi 0:c88c3b616c00 318 uint32_t RESERVED1[7];
IKobayashi 0:c88c3b616c00 319 __IO uint32_t CTCR;
IKobayashi 0:c88c3b616c00 320 } LPC_PWM_TypeDef;
IKobayashi 0:c88c3b616c00 321
IKobayashi 0:c88c3b616c00 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
IKobayashi 0:c88c3b616c00 323 typedef struct
IKobayashi 0:c88c3b616c00 324 {
IKobayashi 0:c88c3b616c00 325 union {
IKobayashi 0:c88c3b616c00 326 __I uint8_t RBR;
IKobayashi 0:c88c3b616c00 327 __O uint8_t THR;
IKobayashi 0:c88c3b616c00 328 __IO uint8_t DLL;
IKobayashi 0:c88c3b616c00 329 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 330 };
IKobayashi 0:c88c3b616c00 331 union {
IKobayashi 0:c88c3b616c00 332 __IO uint8_t DLM;
IKobayashi 0:c88c3b616c00 333 __IO uint32_t IER;
IKobayashi 0:c88c3b616c00 334 };
IKobayashi 0:c88c3b616c00 335 union {
IKobayashi 0:c88c3b616c00 336 __I uint32_t IIR;
IKobayashi 0:c88c3b616c00 337 __O uint8_t FCR;
IKobayashi 0:c88c3b616c00 338 };
IKobayashi 0:c88c3b616c00 339 __IO uint8_t LCR;
IKobayashi 0:c88c3b616c00 340 uint8_t RESERVED1[7];
IKobayashi 0:c88c3b616c00 341 __I uint8_t LSR;
IKobayashi 0:c88c3b616c00 342 uint8_t RESERVED2[7];
IKobayashi 0:c88c3b616c00 343 __IO uint8_t SCR;
IKobayashi 0:c88c3b616c00 344 uint8_t RESERVED3[3];
IKobayashi 0:c88c3b616c00 345 __IO uint32_t ACR;
IKobayashi 0:c88c3b616c00 346 __IO uint8_t ICR;
IKobayashi 0:c88c3b616c00 347 uint8_t RESERVED4[3];
IKobayashi 0:c88c3b616c00 348 __IO uint8_t FDR;
IKobayashi 0:c88c3b616c00 349 uint8_t RESERVED5[7];
IKobayashi 0:c88c3b616c00 350 __IO uint8_t TER;
IKobayashi 0:c88c3b616c00 351 uint8_t RESERVED6[39];
IKobayashi 0:c88c3b616c00 352 __IO uint32_t FIFOLVL;
IKobayashi 0:c88c3b616c00 353 } LPC_UART_TypeDef;
IKobayashi 0:c88c3b616c00 354
IKobayashi 0:c88c3b616c00 355 typedef struct
IKobayashi 0:c88c3b616c00 356 {
IKobayashi 0:c88c3b616c00 357 union {
IKobayashi 0:c88c3b616c00 358 __I uint8_t RBR;
IKobayashi 0:c88c3b616c00 359 __O uint8_t THR;
IKobayashi 0:c88c3b616c00 360 __IO uint8_t DLL;
IKobayashi 0:c88c3b616c00 361 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 362 };
IKobayashi 0:c88c3b616c00 363 union {
IKobayashi 0:c88c3b616c00 364 __IO uint8_t DLM;
IKobayashi 0:c88c3b616c00 365 __IO uint32_t IER;
IKobayashi 0:c88c3b616c00 366 };
IKobayashi 0:c88c3b616c00 367 union {
IKobayashi 0:c88c3b616c00 368 __I uint32_t IIR;
IKobayashi 0:c88c3b616c00 369 __O uint8_t FCR;
IKobayashi 0:c88c3b616c00 370 };
IKobayashi 0:c88c3b616c00 371 __IO uint8_t LCR;
IKobayashi 0:c88c3b616c00 372 uint8_t RESERVED1[7];
IKobayashi 0:c88c3b616c00 373 __I uint8_t LSR;
IKobayashi 0:c88c3b616c00 374 uint8_t RESERVED2[7];
IKobayashi 0:c88c3b616c00 375 __IO uint8_t SCR;
IKobayashi 0:c88c3b616c00 376 uint8_t RESERVED3[3];
IKobayashi 0:c88c3b616c00 377 __IO uint32_t ACR;
IKobayashi 0:c88c3b616c00 378 __IO uint8_t ICR;
IKobayashi 0:c88c3b616c00 379 uint8_t RESERVED4[3];
IKobayashi 0:c88c3b616c00 380 __IO uint8_t FDR;
IKobayashi 0:c88c3b616c00 381 uint8_t RESERVED5[7];
IKobayashi 0:c88c3b616c00 382 __IO uint8_t TER;
IKobayashi 0:c88c3b616c00 383 uint8_t RESERVED6[39];
IKobayashi 0:c88c3b616c00 384 __IO uint32_t FIFOLVL;
IKobayashi 0:c88c3b616c00 385 } LPC_UART0_TypeDef;
IKobayashi 0:c88c3b616c00 386
IKobayashi 0:c88c3b616c00 387 typedef struct
IKobayashi 0:c88c3b616c00 388 {
IKobayashi 0:c88c3b616c00 389 union {
IKobayashi 0:c88c3b616c00 390 __I uint8_t RBR;
IKobayashi 0:c88c3b616c00 391 __O uint8_t THR;
IKobayashi 0:c88c3b616c00 392 __IO uint8_t DLL;
IKobayashi 0:c88c3b616c00 393 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 394 };
IKobayashi 0:c88c3b616c00 395 union {
IKobayashi 0:c88c3b616c00 396 __IO uint8_t DLM;
IKobayashi 0:c88c3b616c00 397 __IO uint32_t IER;
IKobayashi 0:c88c3b616c00 398 };
IKobayashi 0:c88c3b616c00 399 union {
IKobayashi 0:c88c3b616c00 400 __I uint32_t IIR;
IKobayashi 0:c88c3b616c00 401 __O uint8_t FCR;
IKobayashi 0:c88c3b616c00 402 };
IKobayashi 0:c88c3b616c00 403 __IO uint8_t LCR;
IKobayashi 0:c88c3b616c00 404 uint8_t RESERVED1[3];
IKobayashi 0:c88c3b616c00 405 __IO uint8_t MCR;
IKobayashi 0:c88c3b616c00 406 uint8_t RESERVED2[3];
IKobayashi 0:c88c3b616c00 407 __I uint8_t LSR;
IKobayashi 0:c88c3b616c00 408 uint8_t RESERVED3[3];
IKobayashi 0:c88c3b616c00 409 __I uint8_t MSR;
IKobayashi 0:c88c3b616c00 410 uint8_t RESERVED4[3];
IKobayashi 0:c88c3b616c00 411 __IO uint8_t SCR;
IKobayashi 0:c88c3b616c00 412 uint8_t RESERVED5[3];
IKobayashi 0:c88c3b616c00 413 __IO uint32_t ACR;
IKobayashi 0:c88c3b616c00 414 uint32_t RESERVED6;
IKobayashi 0:c88c3b616c00 415 __IO uint32_t FDR;
IKobayashi 0:c88c3b616c00 416 uint32_t RESERVED7;
IKobayashi 0:c88c3b616c00 417 __IO uint8_t TER;
IKobayashi 0:c88c3b616c00 418 uint8_t RESERVED8[27];
IKobayashi 0:c88c3b616c00 419 __IO uint8_t RS485CTRL;
IKobayashi 0:c88c3b616c00 420 uint8_t RESERVED9[3];
IKobayashi 0:c88c3b616c00 421 __IO uint8_t ADRMATCH;
IKobayashi 0:c88c3b616c00 422 uint8_t RESERVED10[3];
IKobayashi 0:c88c3b616c00 423 __IO uint8_t RS485DLY;
IKobayashi 0:c88c3b616c00 424 uint8_t RESERVED11[3];
IKobayashi 0:c88c3b616c00 425 __IO uint32_t FIFOLVL;
IKobayashi 0:c88c3b616c00 426 } LPC_UART1_TypeDef;
IKobayashi 0:c88c3b616c00 427
IKobayashi 0:c88c3b616c00 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
IKobayashi 0:c88c3b616c00 429 typedef struct
IKobayashi 0:c88c3b616c00 430 {
IKobayashi 0:c88c3b616c00 431 __IO uint32_t SPCR;
IKobayashi 0:c88c3b616c00 432 __I uint32_t SPSR;
IKobayashi 0:c88c3b616c00 433 __IO uint32_t SPDR;
IKobayashi 0:c88c3b616c00 434 __IO uint32_t SPCCR;
IKobayashi 0:c88c3b616c00 435 uint32_t RESERVED0[3];
IKobayashi 0:c88c3b616c00 436 __IO uint32_t SPINT;
IKobayashi 0:c88c3b616c00 437 } LPC_SPI_TypeDef;
IKobayashi 0:c88c3b616c00 438
IKobayashi 0:c88c3b616c00 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
IKobayashi 0:c88c3b616c00 440 typedef struct
IKobayashi 0:c88c3b616c00 441 {
IKobayashi 0:c88c3b616c00 442 __IO uint32_t CR0;
IKobayashi 0:c88c3b616c00 443 __IO uint32_t CR1;
IKobayashi 0:c88c3b616c00 444 __IO uint32_t DR;
IKobayashi 0:c88c3b616c00 445 __I uint32_t SR;
IKobayashi 0:c88c3b616c00 446 __IO uint32_t CPSR;
IKobayashi 0:c88c3b616c00 447 __IO uint32_t IMSC;
IKobayashi 0:c88c3b616c00 448 __IO uint32_t RIS;
IKobayashi 0:c88c3b616c00 449 __IO uint32_t MIS;
IKobayashi 0:c88c3b616c00 450 __IO uint32_t ICR;
IKobayashi 0:c88c3b616c00 451 __IO uint32_t DMACR;
IKobayashi 0:c88c3b616c00 452 } LPC_SSP_TypeDef;
IKobayashi 0:c88c3b616c00 453
IKobayashi 0:c88c3b616c00 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
IKobayashi 0:c88c3b616c00 455 typedef struct
IKobayashi 0:c88c3b616c00 456 {
IKobayashi 0:c88c3b616c00 457 __IO uint32_t I2CONSET;
IKobayashi 0:c88c3b616c00 458 __I uint32_t I2STAT;
IKobayashi 0:c88c3b616c00 459 __IO uint32_t I2DAT;
IKobayashi 0:c88c3b616c00 460 __IO uint32_t I2ADR0;
IKobayashi 0:c88c3b616c00 461 __IO uint32_t I2SCLH;
IKobayashi 0:c88c3b616c00 462 __IO uint32_t I2SCLL;
IKobayashi 0:c88c3b616c00 463 __O uint32_t I2CONCLR;
IKobayashi 0:c88c3b616c00 464 __IO uint32_t MMCTRL;
IKobayashi 0:c88c3b616c00 465 __IO uint32_t I2ADR1;
IKobayashi 0:c88c3b616c00 466 __IO uint32_t I2ADR2;
IKobayashi 0:c88c3b616c00 467 __IO uint32_t I2ADR3;
IKobayashi 0:c88c3b616c00 468 __I uint32_t I2DATA_BUFFER;
IKobayashi 0:c88c3b616c00 469 __IO uint32_t I2MASK0;
IKobayashi 0:c88c3b616c00 470 __IO uint32_t I2MASK1;
IKobayashi 0:c88c3b616c00 471 __IO uint32_t I2MASK2;
IKobayashi 0:c88c3b616c00 472 __IO uint32_t I2MASK3;
IKobayashi 0:c88c3b616c00 473 } LPC_I2C_TypeDef;
IKobayashi 0:c88c3b616c00 474
IKobayashi 0:c88c3b616c00 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
IKobayashi 0:c88c3b616c00 476 typedef struct
IKobayashi 0:c88c3b616c00 477 {
IKobayashi 0:c88c3b616c00 478 __IO uint32_t I2SDAO;
IKobayashi 0:c88c3b616c00 479 __IO uint32_t I2SDAI;
IKobayashi 0:c88c3b616c00 480 __O uint32_t I2STXFIFO;
IKobayashi 0:c88c3b616c00 481 __I uint32_t I2SRXFIFO;
IKobayashi 0:c88c3b616c00 482 __I uint32_t I2SSTATE;
IKobayashi 0:c88c3b616c00 483 __IO uint32_t I2SDMA1;
IKobayashi 0:c88c3b616c00 484 __IO uint32_t I2SDMA2;
IKobayashi 0:c88c3b616c00 485 __IO uint32_t I2SIRQ;
IKobayashi 0:c88c3b616c00 486 __IO uint32_t I2STXRATE;
IKobayashi 0:c88c3b616c00 487 __IO uint32_t I2SRXRATE;
IKobayashi 0:c88c3b616c00 488 __IO uint32_t I2STXBITRATE;
IKobayashi 0:c88c3b616c00 489 __IO uint32_t I2SRXBITRATE;
IKobayashi 0:c88c3b616c00 490 __IO uint32_t I2STXMODE;
IKobayashi 0:c88c3b616c00 491 __IO uint32_t I2SRXMODE;
IKobayashi 0:c88c3b616c00 492 } LPC_I2S_TypeDef;
IKobayashi 0:c88c3b616c00 493
IKobayashi 0:c88c3b616c00 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
IKobayashi 0:c88c3b616c00 495 typedef struct
IKobayashi 0:c88c3b616c00 496 {
IKobayashi 0:c88c3b616c00 497 __IO uint32_t RICOMPVAL;
IKobayashi 0:c88c3b616c00 498 __IO uint32_t RIMASK;
IKobayashi 0:c88c3b616c00 499 __IO uint8_t RICTRL;
IKobayashi 0:c88c3b616c00 500 uint8_t RESERVED0[3];
IKobayashi 0:c88c3b616c00 501 __IO uint32_t RICOUNTER;
IKobayashi 0:c88c3b616c00 502 } LPC_RIT_TypeDef;
IKobayashi 0:c88c3b616c00 503
IKobayashi 0:c88c3b616c00 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
IKobayashi 0:c88c3b616c00 505 typedef struct
IKobayashi 0:c88c3b616c00 506 {
IKobayashi 0:c88c3b616c00 507 __IO uint8_t ILR;
IKobayashi 0:c88c3b616c00 508 uint8_t RESERVED0[7];
IKobayashi 0:c88c3b616c00 509 __IO uint8_t CCR;
IKobayashi 0:c88c3b616c00 510 uint8_t RESERVED1[3];
IKobayashi 0:c88c3b616c00 511 __IO uint8_t CIIR;
IKobayashi 0:c88c3b616c00 512 uint8_t RESERVED2[3];
IKobayashi 0:c88c3b616c00 513 __IO uint8_t AMR;
IKobayashi 0:c88c3b616c00 514 uint8_t RESERVED3[3];
IKobayashi 0:c88c3b616c00 515 __I uint32_t CTIME0;
IKobayashi 0:c88c3b616c00 516 __I uint32_t CTIME1;
IKobayashi 0:c88c3b616c00 517 __I uint32_t CTIME2;
IKobayashi 0:c88c3b616c00 518 __IO uint8_t SEC;
IKobayashi 0:c88c3b616c00 519 uint8_t RESERVED4[3];
IKobayashi 0:c88c3b616c00 520 __IO uint8_t MIN;
IKobayashi 0:c88c3b616c00 521 uint8_t RESERVED5[3];
IKobayashi 0:c88c3b616c00 522 __IO uint8_t HOUR;
IKobayashi 0:c88c3b616c00 523 uint8_t RESERVED6[3];
IKobayashi 0:c88c3b616c00 524 __IO uint8_t DOM;
IKobayashi 0:c88c3b616c00 525 uint8_t RESERVED7[3];
IKobayashi 0:c88c3b616c00 526 __IO uint8_t DOW;
IKobayashi 0:c88c3b616c00 527 uint8_t RESERVED8[3];
IKobayashi 0:c88c3b616c00 528 __IO uint16_t DOY;
IKobayashi 0:c88c3b616c00 529 uint16_t RESERVED9;
IKobayashi 0:c88c3b616c00 530 __IO uint8_t MONTH;
IKobayashi 0:c88c3b616c00 531 uint8_t RESERVED10[3];
IKobayashi 0:c88c3b616c00 532 __IO uint16_t YEAR;
IKobayashi 0:c88c3b616c00 533 uint16_t RESERVED11;
IKobayashi 0:c88c3b616c00 534 __IO uint32_t CALIBRATION;
IKobayashi 0:c88c3b616c00 535 __IO uint32_t GPREG0;
IKobayashi 0:c88c3b616c00 536 __IO uint32_t GPREG1;
IKobayashi 0:c88c3b616c00 537 __IO uint32_t GPREG2;
IKobayashi 0:c88c3b616c00 538 __IO uint32_t GPREG3;
IKobayashi 0:c88c3b616c00 539 __IO uint32_t GPREG4;
IKobayashi 0:c88c3b616c00 540 __IO uint8_t RTC_AUXEN;
IKobayashi 0:c88c3b616c00 541 uint8_t RESERVED12[3];
IKobayashi 0:c88c3b616c00 542 __IO uint8_t RTC_AUX;
IKobayashi 0:c88c3b616c00 543 uint8_t RESERVED13[3];
IKobayashi 0:c88c3b616c00 544 __IO uint8_t ALSEC;
IKobayashi 0:c88c3b616c00 545 uint8_t RESERVED14[3];
IKobayashi 0:c88c3b616c00 546 __IO uint8_t ALMIN;
IKobayashi 0:c88c3b616c00 547 uint8_t RESERVED15[3];
IKobayashi 0:c88c3b616c00 548 __IO uint8_t ALHOUR;
IKobayashi 0:c88c3b616c00 549 uint8_t RESERVED16[3];
IKobayashi 0:c88c3b616c00 550 __IO uint8_t ALDOM;
IKobayashi 0:c88c3b616c00 551 uint8_t RESERVED17[3];
IKobayashi 0:c88c3b616c00 552 __IO uint8_t ALDOW;
IKobayashi 0:c88c3b616c00 553 uint8_t RESERVED18[3];
IKobayashi 0:c88c3b616c00 554 __IO uint16_t ALDOY;
IKobayashi 0:c88c3b616c00 555 uint16_t RESERVED19;
IKobayashi 0:c88c3b616c00 556 __IO uint8_t ALMON;
IKobayashi 0:c88c3b616c00 557 uint8_t RESERVED20[3];
IKobayashi 0:c88c3b616c00 558 __IO uint16_t ALYEAR;
IKobayashi 0:c88c3b616c00 559 uint16_t RESERVED21;
IKobayashi 0:c88c3b616c00 560 } LPC_RTC_TypeDef;
IKobayashi 0:c88c3b616c00 561
IKobayashi 0:c88c3b616c00 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
IKobayashi 0:c88c3b616c00 563 typedef struct
IKobayashi 0:c88c3b616c00 564 {
IKobayashi 0:c88c3b616c00 565 __IO uint8_t WDMOD;
IKobayashi 0:c88c3b616c00 566 uint8_t RESERVED0[3];
IKobayashi 0:c88c3b616c00 567 __IO uint32_t WDTC;
IKobayashi 0:c88c3b616c00 568 __O uint8_t WDFEED;
IKobayashi 0:c88c3b616c00 569 uint8_t RESERVED1[3];
IKobayashi 0:c88c3b616c00 570 __I uint32_t WDTV;
IKobayashi 0:c88c3b616c00 571 __IO uint32_t WDCLKSEL;
IKobayashi 0:c88c3b616c00 572 } LPC_WDT_TypeDef;
IKobayashi 0:c88c3b616c00 573
IKobayashi 0:c88c3b616c00 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
IKobayashi 0:c88c3b616c00 575 typedef struct
IKobayashi 0:c88c3b616c00 576 {
IKobayashi 0:c88c3b616c00 577 __IO uint32_t ADCR;
IKobayashi 0:c88c3b616c00 578 __IO uint32_t ADGDR;
IKobayashi 0:c88c3b616c00 579 uint32_t RESERVED0;
IKobayashi 0:c88c3b616c00 580 __IO uint32_t ADINTEN;
IKobayashi 0:c88c3b616c00 581 __I uint32_t ADDR0;
IKobayashi 0:c88c3b616c00 582 __I uint32_t ADDR1;
IKobayashi 0:c88c3b616c00 583 __I uint32_t ADDR2;
IKobayashi 0:c88c3b616c00 584 __I uint32_t ADDR3;
IKobayashi 0:c88c3b616c00 585 __I uint32_t ADDR4;
IKobayashi 0:c88c3b616c00 586 __I uint32_t ADDR5;
IKobayashi 0:c88c3b616c00 587 __I uint32_t ADDR6;
IKobayashi 0:c88c3b616c00 588 __I uint32_t ADDR7;
IKobayashi 0:c88c3b616c00 589 __I uint32_t ADSTAT;
IKobayashi 0:c88c3b616c00 590 __IO uint32_t ADTRM;
IKobayashi 0:c88c3b616c00 591 } LPC_ADC_TypeDef;
IKobayashi 0:c88c3b616c00 592
IKobayashi 0:c88c3b616c00 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
IKobayashi 0:c88c3b616c00 594 typedef struct
IKobayashi 0:c88c3b616c00 595 {
IKobayashi 0:c88c3b616c00 596 __IO uint32_t DACR;
IKobayashi 0:c88c3b616c00 597 __IO uint32_t DACCTRL;
IKobayashi 0:c88c3b616c00 598 __IO uint16_t DACCNTVAL;
IKobayashi 0:c88c3b616c00 599 } LPC_DAC_TypeDef;
IKobayashi 0:c88c3b616c00 600
IKobayashi 0:c88c3b616c00 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
IKobayashi 0:c88c3b616c00 602 typedef struct
IKobayashi 0:c88c3b616c00 603 {
IKobayashi 0:c88c3b616c00 604 __I uint32_t MCCON;
IKobayashi 0:c88c3b616c00 605 __O uint32_t MCCON_SET;
IKobayashi 0:c88c3b616c00 606 __O uint32_t MCCON_CLR;
IKobayashi 0:c88c3b616c00 607 __I uint32_t MCCAPCON;
IKobayashi 0:c88c3b616c00 608 __O uint32_t MCCAPCON_SET;
IKobayashi 0:c88c3b616c00 609 __O uint32_t MCCAPCON_CLR;
IKobayashi 0:c88c3b616c00 610 __IO uint32_t MCTIM0;
IKobayashi 0:c88c3b616c00 611 __IO uint32_t MCTIM1;
IKobayashi 0:c88c3b616c00 612 __IO uint32_t MCTIM2;
IKobayashi 0:c88c3b616c00 613 __IO uint32_t MCPER0;
IKobayashi 0:c88c3b616c00 614 __IO uint32_t MCPER1;
IKobayashi 0:c88c3b616c00 615 __IO uint32_t MCPER2;
IKobayashi 0:c88c3b616c00 616 __IO uint32_t MCPW0;
IKobayashi 0:c88c3b616c00 617 __IO uint32_t MCPW1;
IKobayashi 0:c88c3b616c00 618 __IO uint32_t MCPW2;
IKobayashi 0:c88c3b616c00 619 __IO uint32_t MCDEADTIME;
IKobayashi 0:c88c3b616c00 620 __IO uint32_t MCCCP;
IKobayashi 0:c88c3b616c00 621 __IO uint32_t MCCR0;
IKobayashi 0:c88c3b616c00 622 __IO uint32_t MCCR1;
IKobayashi 0:c88c3b616c00 623 __IO uint32_t MCCR2;
IKobayashi 0:c88c3b616c00 624 __I uint32_t MCINTEN;
IKobayashi 0:c88c3b616c00 625 __O uint32_t MCINTEN_SET;
IKobayashi 0:c88c3b616c00 626 __O uint32_t MCINTEN_CLR;
IKobayashi 0:c88c3b616c00 627 __I uint32_t MCCNTCON;
IKobayashi 0:c88c3b616c00 628 __O uint32_t MCCNTCON_SET;
IKobayashi 0:c88c3b616c00 629 __O uint32_t MCCNTCON_CLR;
IKobayashi 0:c88c3b616c00 630 __I uint32_t MCINTFLAG;
IKobayashi 0:c88c3b616c00 631 __O uint32_t MCINTFLAG_SET;
IKobayashi 0:c88c3b616c00 632 __O uint32_t MCINTFLAG_CLR;
IKobayashi 0:c88c3b616c00 633 __O uint32_t MCCAP_CLR;
IKobayashi 0:c88c3b616c00 634 } LPC_MCPWM_TypeDef;
IKobayashi 0:c88c3b616c00 635
IKobayashi 0:c88c3b616c00 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
IKobayashi 0:c88c3b616c00 637 typedef struct
IKobayashi 0:c88c3b616c00 638 {
IKobayashi 0:c88c3b616c00 639 __O uint32_t QEICON;
IKobayashi 0:c88c3b616c00 640 __I uint32_t QEISTAT;
IKobayashi 0:c88c3b616c00 641 __IO uint32_t QEICONF;
IKobayashi 0:c88c3b616c00 642 __I uint32_t QEIPOS;
IKobayashi 0:c88c3b616c00 643 __IO uint32_t QEIMAXPOS;
IKobayashi 0:c88c3b616c00 644 __IO uint32_t CMPOS0;
IKobayashi 0:c88c3b616c00 645 __IO uint32_t CMPOS1;
IKobayashi 0:c88c3b616c00 646 __IO uint32_t CMPOS2;
IKobayashi 0:c88c3b616c00 647 __I uint32_t INXCNT;
IKobayashi 0:c88c3b616c00 648 __IO uint32_t INXCMP;
IKobayashi 0:c88c3b616c00 649 __IO uint32_t QEILOAD;
IKobayashi 0:c88c3b616c00 650 __I uint32_t QEITIME;
IKobayashi 0:c88c3b616c00 651 __I uint32_t QEIVEL;
IKobayashi 0:c88c3b616c00 652 __I uint32_t QEICAP;
IKobayashi 0:c88c3b616c00 653 __IO uint32_t VELCOMP;
IKobayashi 0:c88c3b616c00 654 __IO uint32_t FILTER;
IKobayashi 0:c88c3b616c00 655 uint32_t RESERVED0[998];
IKobayashi 0:c88c3b616c00 656 __O uint32_t QEIIEC;
IKobayashi 0:c88c3b616c00 657 __O uint32_t QEIIES;
IKobayashi 0:c88c3b616c00 658 __I uint32_t QEIINTSTAT;
IKobayashi 0:c88c3b616c00 659 __I uint32_t QEIIE;
IKobayashi 0:c88c3b616c00 660 __O uint32_t QEICLR;
IKobayashi 0:c88c3b616c00 661 __O uint32_t QEISET;
IKobayashi 0:c88c3b616c00 662 } LPC_QEI_TypeDef;
IKobayashi 0:c88c3b616c00 663
IKobayashi 0:c88c3b616c00 664 /*------------- Controller Area Network (CAN) --------------------------------*/
IKobayashi 0:c88c3b616c00 665 typedef struct
IKobayashi 0:c88c3b616c00 666 {
IKobayashi 0:c88c3b616c00 667 __IO uint32_t mask[512]; /* ID Masks */
IKobayashi 0:c88c3b616c00 668 } LPC_CANAF_RAM_TypeDef;
IKobayashi 0:c88c3b616c00 669
IKobayashi 0:c88c3b616c00 670 typedef struct /* Acceptance Filter Registers */
IKobayashi 0:c88c3b616c00 671 {
IKobayashi 0:c88c3b616c00 672 __IO uint32_t AFMR;
IKobayashi 0:c88c3b616c00 673 __IO uint32_t SFF_sa;
IKobayashi 0:c88c3b616c00 674 __IO uint32_t SFF_GRP_sa;
IKobayashi 0:c88c3b616c00 675 __IO uint32_t EFF_sa;
IKobayashi 0:c88c3b616c00 676 __IO uint32_t EFF_GRP_sa;
IKobayashi 0:c88c3b616c00 677 __IO uint32_t ENDofTable;
IKobayashi 0:c88c3b616c00 678 __I uint32_t LUTerrAd;
IKobayashi 0:c88c3b616c00 679 __I uint32_t LUTerr;
IKobayashi 0:c88c3b616c00 680 __IO uint32_t FCANIE;
IKobayashi 0:c88c3b616c00 681 __IO uint32_t FCANIC0;
IKobayashi 0:c88c3b616c00 682 __IO uint32_t FCANIC1;
IKobayashi 0:c88c3b616c00 683 } LPC_CANAF_TypeDef;
IKobayashi 0:c88c3b616c00 684
IKobayashi 0:c88c3b616c00 685 typedef struct /* Central Registers */
IKobayashi 0:c88c3b616c00 686 {
IKobayashi 0:c88c3b616c00 687 __I uint32_t CANTxSR;
IKobayashi 0:c88c3b616c00 688 __I uint32_t CANRxSR;
IKobayashi 0:c88c3b616c00 689 __I uint32_t CANMSR;
IKobayashi 0:c88c3b616c00 690 } LPC_CANCR_TypeDef;
IKobayashi 0:c88c3b616c00 691
IKobayashi 0:c88c3b616c00 692 typedef struct /* Controller Registers */
IKobayashi 0:c88c3b616c00 693 {
IKobayashi 0:c88c3b616c00 694 __IO uint32_t MOD;
IKobayashi 0:c88c3b616c00 695 __O uint32_t CMR;
IKobayashi 0:c88c3b616c00 696 __IO uint32_t GSR;
IKobayashi 0:c88c3b616c00 697 __I uint32_t ICR;
IKobayashi 0:c88c3b616c00 698 __IO uint32_t IER;
IKobayashi 0:c88c3b616c00 699 __IO uint32_t BTR;
IKobayashi 0:c88c3b616c00 700 __IO uint32_t EWL;
IKobayashi 0:c88c3b616c00 701 __I uint32_t SR;
IKobayashi 0:c88c3b616c00 702 __IO uint32_t RFS;
IKobayashi 0:c88c3b616c00 703 __IO uint32_t RID;
IKobayashi 0:c88c3b616c00 704 __IO uint32_t RDA;
IKobayashi 0:c88c3b616c00 705 __IO uint32_t RDB;
IKobayashi 0:c88c3b616c00 706 __IO uint32_t TFI1;
IKobayashi 0:c88c3b616c00 707 __IO uint32_t TID1;
IKobayashi 0:c88c3b616c00 708 __IO uint32_t TDA1;
IKobayashi 0:c88c3b616c00 709 __IO uint32_t TDB1;
IKobayashi 0:c88c3b616c00 710 __IO uint32_t TFI2;
IKobayashi 0:c88c3b616c00 711 __IO uint32_t TID2;
IKobayashi 0:c88c3b616c00 712 __IO uint32_t TDA2;
IKobayashi 0:c88c3b616c00 713 __IO uint32_t TDB2;
IKobayashi 0:c88c3b616c00 714 __IO uint32_t TFI3;
IKobayashi 0:c88c3b616c00 715 __IO uint32_t TID3;
IKobayashi 0:c88c3b616c00 716 __IO uint32_t TDA3;
IKobayashi 0:c88c3b616c00 717 __IO uint32_t TDB3;
IKobayashi 0:c88c3b616c00 718 } LPC_CAN_TypeDef;
IKobayashi 0:c88c3b616c00 719
IKobayashi 0:c88c3b616c00 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
IKobayashi 0:c88c3b616c00 721 typedef struct /* Common Registers */
IKobayashi 0:c88c3b616c00 722 {
IKobayashi 0:c88c3b616c00 723 __I uint32_t DMACIntStat;
IKobayashi 0:c88c3b616c00 724 __I uint32_t DMACIntTCStat;
IKobayashi 0:c88c3b616c00 725 __O uint32_t DMACIntTCClear;
IKobayashi 0:c88c3b616c00 726 __I uint32_t DMACIntErrStat;
IKobayashi 0:c88c3b616c00 727 __O uint32_t DMACIntErrClr;
IKobayashi 0:c88c3b616c00 728 __I uint32_t DMACRawIntTCStat;
IKobayashi 0:c88c3b616c00 729 __I uint32_t DMACRawIntErrStat;
IKobayashi 0:c88c3b616c00 730 __I uint32_t DMACEnbldChns;
IKobayashi 0:c88c3b616c00 731 __IO uint32_t DMACSoftBReq;
IKobayashi 0:c88c3b616c00 732 __IO uint32_t DMACSoftSReq;
IKobayashi 0:c88c3b616c00 733 __IO uint32_t DMACSoftLBReq;
IKobayashi 0:c88c3b616c00 734 __IO uint32_t DMACSoftLSReq;
IKobayashi 0:c88c3b616c00 735 __IO uint32_t DMACConfig;
IKobayashi 0:c88c3b616c00 736 __IO uint32_t DMACSync;
IKobayashi 0:c88c3b616c00 737 } LPC_GPDMA_TypeDef;
IKobayashi 0:c88c3b616c00 738
IKobayashi 0:c88c3b616c00 739 typedef struct /* Channel Registers */
IKobayashi 0:c88c3b616c00 740 {
IKobayashi 0:c88c3b616c00 741 __IO uint32_t DMACCSrcAddr;
IKobayashi 0:c88c3b616c00 742 __IO uint32_t DMACCDestAddr;
IKobayashi 0:c88c3b616c00 743 __IO uint32_t DMACCLLI;
IKobayashi 0:c88c3b616c00 744 __IO uint32_t DMACCControl;
IKobayashi 0:c88c3b616c00 745 __IO uint32_t DMACCConfig;
IKobayashi 0:c88c3b616c00 746 } LPC_GPDMACH_TypeDef;
IKobayashi 0:c88c3b616c00 747
IKobayashi 0:c88c3b616c00 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
IKobayashi 0:c88c3b616c00 749 typedef struct
IKobayashi 0:c88c3b616c00 750 {
IKobayashi 0:c88c3b616c00 751 __I uint32_t HcRevision; /* USB Host Registers */
IKobayashi 0:c88c3b616c00 752 __IO uint32_t HcControl;
IKobayashi 0:c88c3b616c00 753 __IO uint32_t HcCommandStatus;
IKobayashi 0:c88c3b616c00 754 __IO uint32_t HcInterruptStatus;
IKobayashi 0:c88c3b616c00 755 __IO uint32_t HcInterruptEnable;
IKobayashi 0:c88c3b616c00 756 __IO uint32_t HcInterruptDisable;
IKobayashi 0:c88c3b616c00 757 __IO uint32_t HcHCCA;
IKobayashi 0:c88c3b616c00 758 __I uint32_t HcPeriodCurrentED;
IKobayashi 0:c88c3b616c00 759 __IO uint32_t HcControlHeadED;
IKobayashi 0:c88c3b616c00 760 __IO uint32_t HcControlCurrentED;
IKobayashi 0:c88c3b616c00 761 __IO uint32_t HcBulkHeadED;
IKobayashi 0:c88c3b616c00 762 __IO uint32_t HcBulkCurrentED;
IKobayashi 0:c88c3b616c00 763 __I uint32_t HcDoneHead;
IKobayashi 0:c88c3b616c00 764 __IO uint32_t HcFmInterval;
IKobayashi 0:c88c3b616c00 765 __I uint32_t HcFmRemaining;
IKobayashi 0:c88c3b616c00 766 __I uint32_t HcFmNumber;
IKobayashi 0:c88c3b616c00 767 __IO uint32_t HcPeriodicStart;
IKobayashi 0:c88c3b616c00 768 __IO uint32_t HcLSTreshold;
IKobayashi 0:c88c3b616c00 769 __IO uint32_t HcRhDescriptorA;
IKobayashi 0:c88c3b616c00 770 __IO uint32_t HcRhDescriptorB;
IKobayashi 0:c88c3b616c00 771 __IO uint32_t HcRhStatus;
IKobayashi 0:c88c3b616c00 772 __IO uint32_t HcRhPortStatus1;
IKobayashi 0:c88c3b616c00 773 __IO uint32_t HcRhPortStatus2;
IKobayashi 0:c88c3b616c00 774 uint32_t RESERVED0[40];
IKobayashi 0:c88c3b616c00 775 __I uint32_t Module_ID;
IKobayashi 0:c88c3b616c00 776
IKobayashi 0:c88c3b616c00 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
IKobayashi 0:c88c3b616c00 778 __IO uint32_t OTGIntEn;
IKobayashi 0:c88c3b616c00 779 __O uint32_t OTGIntSet;
IKobayashi 0:c88c3b616c00 780 __O uint32_t OTGIntClr;
IKobayashi 0:c88c3b616c00 781 __IO uint32_t OTGStCtrl;
IKobayashi 0:c88c3b616c00 782 __IO uint32_t OTGTmr;
IKobayashi 0:c88c3b616c00 783 uint32_t RESERVED1[58];
IKobayashi 0:c88c3b616c00 784
IKobayashi 0:c88c3b616c00 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
IKobayashi 0:c88c3b616c00 786 __IO uint32_t USBDevIntEn;
IKobayashi 0:c88c3b616c00 787 __O uint32_t USBDevIntClr;
IKobayashi 0:c88c3b616c00 788 __O uint32_t USBDevIntSet;
IKobayashi 0:c88c3b616c00 789
IKobayashi 0:c88c3b616c00 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
IKobayashi 0:c88c3b616c00 791 __I uint32_t USBCmdData;
IKobayashi 0:c88c3b616c00 792
IKobayashi 0:c88c3b616c00 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
IKobayashi 0:c88c3b616c00 794 __O uint32_t USBTxData;
IKobayashi 0:c88c3b616c00 795 __I uint32_t USBRxPLen;
IKobayashi 0:c88c3b616c00 796 __O uint32_t USBTxPLen;
IKobayashi 0:c88c3b616c00 797 __IO uint32_t USBCtrl;
IKobayashi 0:c88c3b616c00 798 __O uint32_t USBDevIntPri;
IKobayashi 0:c88c3b616c00 799
IKobayashi 0:c88c3b616c00 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
IKobayashi 0:c88c3b616c00 801 __IO uint32_t USBEpIntEn;
IKobayashi 0:c88c3b616c00 802 __O uint32_t USBEpIntClr;
IKobayashi 0:c88c3b616c00 803 __O uint32_t USBEpIntSet;
IKobayashi 0:c88c3b616c00 804 __O uint32_t USBEpIntPri;
IKobayashi 0:c88c3b616c00 805
IKobayashi 0:c88c3b616c00 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
IKobayashi 0:c88c3b616c00 807 __O uint32_t USBEpInd;
IKobayashi 0:c88c3b616c00 808 __IO uint32_t USBMaxPSize;
IKobayashi 0:c88c3b616c00 809
IKobayashi 0:c88c3b616c00 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
IKobayashi 0:c88c3b616c00 811 __O uint32_t USBDMARClr;
IKobayashi 0:c88c3b616c00 812 __O uint32_t USBDMARSet;
IKobayashi 0:c88c3b616c00 813 uint32_t RESERVED2[9];
IKobayashi 0:c88c3b616c00 814 __IO uint32_t USBUDCAH;
IKobayashi 0:c88c3b616c00 815 __I uint32_t USBEpDMASt;
IKobayashi 0:c88c3b616c00 816 __O uint32_t USBEpDMAEn;
IKobayashi 0:c88c3b616c00 817 __O uint32_t USBEpDMADis;
IKobayashi 0:c88c3b616c00 818 __I uint32_t USBDMAIntSt;
IKobayashi 0:c88c3b616c00 819 __IO uint32_t USBDMAIntEn;
IKobayashi 0:c88c3b616c00 820 uint32_t RESERVED3[2];
IKobayashi 0:c88c3b616c00 821 __I uint32_t USBEoTIntSt;
IKobayashi 0:c88c3b616c00 822 __O uint32_t USBEoTIntClr;
IKobayashi 0:c88c3b616c00 823 __O uint32_t USBEoTIntSet;
IKobayashi 0:c88c3b616c00 824 __I uint32_t USBNDDRIntSt;
IKobayashi 0:c88c3b616c00 825 __O uint32_t USBNDDRIntClr;
IKobayashi 0:c88c3b616c00 826 __O uint32_t USBNDDRIntSet;
IKobayashi 0:c88c3b616c00 827 __I uint32_t USBSysErrIntSt;
IKobayashi 0:c88c3b616c00 828 __O uint32_t USBSysErrIntClr;
IKobayashi 0:c88c3b616c00 829 __O uint32_t USBSysErrIntSet;
IKobayashi 0:c88c3b616c00 830 uint32_t RESERVED4[15];
IKobayashi 0:c88c3b616c00 831
IKobayashi 0:c88c3b616c00 832 union {
IKobayashi 0:c88c3b616c00 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
IKobayashi 0:c88c3b616c00 834 __O uint32_t I2C_TX;
IKobayashi 0:c88c3b616c00 835 };
IKobayashi 0:c88c3b616c00 836 __I uint32_t I2C_STS;
IKobayashi 0:c88c3b616c00 837 __IO uint32_t I2C_CTL;
IKobayashi 0:c88c3b616c00 838 __IO uint32_t I2C_CLKHI;
IKobayashi 0:c88c3b616c00 839 __O uint32_t I2C_CLKLO;
IKobayashi 0:c88c3b616c00 840 uint32_t RESERVED5[824];
IKobayashi 0:c88c3b616c00 841
IKobayashi 0:c88c3b616c00 842 union {
IKobayashi 0:c88c3b616c00 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
IKobayashi 0:c88c3b616c00 844 __IO uint32_t OTGClkCtrl;
IKobayashi 0:c88c3b616c00 845 };
IKobayashi 0:c88c3b616c00 846 union {
IKobayashi 0:c88c3b616c00 847 __I uint32_t USBClkSt;
IKobayashi 0:c88c3b616c00 848 __I uint32_t OTGClkSt;
IKobayashi 0:c88c3b616c00 849 };
IKobayashi 0:c88c3b616c00 850 } LPC_USB_TypeDef;
IKobayashi 0:c88c3b616c00 851
IKobayashi 0:c88c3b616c00 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
IKobayashi 0:c88c3b616c00 853 typedef struct
IKobayashi 0:c88c3b616c00 854 {
IKobayashi 0:c88c3b616c00 855 __IO uint32_t MAC1; /* MAC Registers */
IKobayashi 0:c88c3b616c00 856 __IO uint32_t MAC2;
IKobayashi 0:c88c3b616c00 857 __IO uint32_t IPGT;
IKobayashi 0:c88c3b616c00 858 __IO uint32_t IPGR;
IKobayashi 0:c88c3b616c00 859 __IO uint32_t CLRT;
IKobayashi 0:c88c3b616c00 860 __IO uint32_t MAXF;
IKobayashi 0:c88c3b616c00 861 __IO uint32_t SUPP;
IKobayashi 0:c88c3b616c00 862 __IO uint32_t TEST;
IKobayashi 0:c88c3b616c00 863 __IO uint32_t MCFG;
IKobayashi 0:c88c3b616c00 864 __IO uint32_t MCMD;
IKobayashi 0:c88c3b616c00 865 __IO uint32_t MADR;
IKobayashi 0:c88c3b616c00 866 __O uint32_t MWTD;
IKobayashi 0:c88c3b616c00 867 __I uint32_t MRDD;
IKobayashi 0:c88c3b616c00 868 __I uint32_t MIND;
IKobayashi 0:c88c3b616c00 869 uint32_t RESERVED0[2];
IKobayashi 0:c88c3b616c00 870 __IO uint32_t SA0;
IKobayashi 0:c88c3b616c00 871 __IO uint32_t SA1;
IKobayashi 0:c88c3b616c00 872 __IO uint32_t SA2;
IKobayashi 0:c88c3b616c00 873 uint32_t RESERVED1[45];
IKobayashi 0:c88c3b616c00 874 __IO uint32_t Command; /* Control Registers */
IKobayashi 0:c88c3b616c00 875 __I uint32_t Status;
IKobayashi 0:c88c3b616c00 876 __IO uint32_t RxDescriptor;
IKobayashi 0:c88c3b616c00 877 __IO uint32_t RxStatus;
IKobayashi 0:c88c3b616c00 878 __IO uint32_t RxDescriptorNumber;
IKobayashi 0:c88c3b616c00 879 __I uint32_t RxProduceIndex;
IKobayashi 0:c88c3b616c00 880 __IO uint32_t RxConsumeIndex;
IKobayashi 0:c88c3b616c00 881 __IO uint32_t TxDescriptor;
IKobayashi 0:c88c3b616c00 882 __IO uint32_t TxStatus;
IKobayashi 0:c88c3b616c00 883 __IO uint32_t TxDescriptorNumber;
IKobayashi 0:c88c3b616c00 884 __IO uint32_t TxProduceIndex;
IKobayashi 0:c88c3b616c00 885 __I uint32_t TxConsumeIndex;
IKobayashi 0:c88c3b616c00 886 uint32_t RESERVED2[10];
IKobayashi 0:c88c3b616c00 887 __I uint32_t TSV0;
IKobayashi 0:c88c3b616c00 888 __I uint32_t TSV1;
IKobayashi 0:c88c3b616c00 889 __I uint32_t RSV;
IKobayashi 0:c88c3b616c00 890 uint32_t RESERVED3[3];
IKobayashi 0:c88c3b616c00 891 __IO uint32_t FlowControlCounter;
IKobayashi 0:c88c3b616c00 892 __I uint32_t FlowControlStatus;
IKobayashi 0:c88c3b616c00 893 uint32_t RESERVED4[34];
IKobayashi 0:c88c3b616c00 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
IKobayashi 0:c88c3b616c00 895 __IO uint32_t RxFilterWoLStatus;
IKobayashi 0:c88c3b616c00 896 __IO uint32_t RxFilterWoLClear;
IKobayashi 0:c88c3b616c00 897 uint32_t RESERVED5;
IKobayashi 0:c88c3b616c00 898 __IO uint32_t HashFilterL;
IKobayashi 0:c88c3b616c00 899 __IO uint32_t HashFilterH;
IKobayashi 0:c88c3b616c00 900 uint32_t RESERVED6[882];
IKobayashi 0:c88c3b616c00 901 __I uint32_t IntStatus; /* Module Control Registers */
IKobayashi 0:c88c3b616c00 902 __IO uint32_t IntEnable;
IKobayashi 0:c88c3b616c00 903 __O uint32_t IntClear;
IKobayashi 0:c88c3b616c00 904 __O uint32_t IntSet;
IKobayashi 0:c88c3b616c00 905 uint32_t RESERVED7;
IKobayashi 0:c88c3b616c00 906 __IO uint32_t PowerDown;
IKobayashi 0:c88c3b616c00 907 uint32_t RESERVED8;
IKobayashi 0:c88c3b616c00 908 __IO uint32_t Module_ID;
IKobayashi 0:c88c3b616c00 909 } LPC_EMAC_TypeDef;
IKobayashi 0:c88c3b616c00 910
IKobayashi 0:c88c3b616c00 911 #if defined ( __CC_ARM )
IKobayashi 0:c88c3b616c00 912 #pragma no_anon_unions
IKobayashi 0:c88c3b616c00 913 #endif
IKobayashi 0:c88c3b616c00 914
IKobayashi 0:c88c3b616c00 915
IKobayashi 0:c88c3b616c00 916 /******************************************************************************/
IKobayashi 0:c88c3b616c00 917 /* Peripheral memory map */
IKobayashi 0:c88c3b616c00 918 /******************************************************************************/
IKobayashi 0:c88c3b616c00 919 /* Base addresses */
IKobayashi 0:c88c3b616c00 920 #define LPC_FLASH_BASE (0x00000000UL)
IKobayashi 0:c88c3b616c00 921 #define LPC_RAM_BASE (0x10000000UL)
IKobayashi 0:c88c3b616c00 922 #define LPC_GPIO_BASE (0x2009C000UL)
IKobayashi 0:c88c3b616c00 923 #define LPC_APB0_BASE (0x40000000UL)
IKobayashi 0:c88c3b616c00 924 #define LPC_APB1_BASE (0x40080000UL)
IKobayashi 0:c88c3b616c00 925 #define LPC_AHB_BASE (0x50000000UL)
IKobayashi 0:c88c3b616c00 926 #define LPC_CM3_BASE (0xE0000000UL)
IKobayashi 0:c88c3b616c00 927
IKobayashi 0:c88c3b616c00 928 /* APB0 peripherals */
IKobayashi 0:c88c3b616c00 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
IKobayashi 0:c88c3b616c00 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
IKobayashi 0:c88c3b616c00 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
IKobayashi 0:c88c3b616c00 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
IKobayashi 0:c88c3b616c00 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
IKobayashi 0:c88c3b616c00 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
IKobayashi 0:c88c3b616c00 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
IKobayashi 0:c88c3b616c00 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
IKobayashi 0:c88c3b616c00 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
IKobayashi 0:c88c3b616c00 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
IKobayashi 0:c88c3b616c00 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
IKobayashi 0:c88c3b616c00 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
IKobayashi 0:c88c3b616c00 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
IKobayashi 0:c88c3b616c00 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
IKobayashi 0:c88c3b616c00 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
IKobayashi 0:c88c3b616c00 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
IKobayashi 0:c88c3b616c00 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
IKobayashi 0:c88c3b616c00 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
IKobayashi 0:c88c3b616c00 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
IKobayashi 0:c88c3b616c00 948
IKobayashi 0:c88c3b616c00 949 /* APB1 peripherals */
IKobayashi 0:c88c3b616c00 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
IKobayashi 0:c88c3b616c00 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
IKobayashi 0:c88c3b616c00 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
IKobayashi 0:c88c3b616c00 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
IKobayashi 0:c88c3b616c00 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
IKobayashi 0:c88c3b616c00 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
IKobayashi 0:c88c3b616c00 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
IKobayashi 0:c88c3b616c00 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
IKobayashi 0:c88c3b616c00 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
IKobayashi 0:c88c3b616c00 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
IKobayashi 0:c88c3b616c00 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
IKobayashi 0:c88c3b616c00 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
IKobayashi 0:c88c3b616c00 962
IKobayashi 0:c88c3b616c00 963 /* AHB peripherals */
IKobayashi 0:c88c3b616c00 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
IKobayashi 0:c88c3b616c00 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
IKobayashi 0:c88c3b616c00 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
IKobayashi 0:c88c3b616c00 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
IKobayashi 0:c88c3b616c00 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
IKobayashi 0:c88c3b616c00 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
IKobayashi 0:c88c3b616c00 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
IKobayashi 0:c88c3b616c00 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
IKobayashi 0:c88c3b616c00 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
IKobayashi 0:c88c3b616c00 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
IKobayashi 0:c88c3b616c00 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
IKobayashi 0:c88c3b616c00 975
IKobayashi 0:c88c3b616c00 976 /* GPIOs */
IKobayashi 0:c88c3b616c00 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
IKobayashi 0:c88c3b616c00 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
IKobayashi 0:c88c3b616c00 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
IKobayashi 0:c88c3b616c00 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
IKobayashi 0:c88c3b616c00 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
IKobayashi 0:c88c3b616c00 982
IKobayashi 0:c88c3b616c00 983
IKobayashi 0:c88c3b616c00 984 /******************************************************************************/
IKobayashi 0:c88c3b616c00 985 /* Peripheral declaration */
IKobayashi 0:c88c3b616c00 986 /******************************************************************************/
IKobayashi 0:c88c3b616c00 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
IKobayashi 0:c88c3b616c00 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
IKobayashi 0:c88c3b616c00 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
IKobayashi 0:c88c3b616c00 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
IKobayashi 0:c88c3b616c00 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
IKobayashi 0:c88c3b616c00 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
IKobayashi 0:c88c3b616c00 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
IKobayashi 0:c88c3b616c00 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
IKobayashi 0:c88c3b616c00 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
IKobayashi 0:c88c3b616c00 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
IKobayashi 0:c88c3b616c00 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
IKobayashi 0:c88c3b616c00 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
IKobayashi 0:c88c3b616c00 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
IKobayashi 0:c88c3b616c00 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
IKobayashi 0:c88c3b616c00 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
IKobayashi 0:c88c3b616c00 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
IKobayashi 0:c88c3b616c00 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
IKobayashi 0:c88c3b616c00 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
IKobayashi 0:c88c3b616c00 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
IKobayashi 0:c88c3b616c00 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
IKobayashi 0:c88c3b616c00 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
IKobayashi 0:c88c3b616c00 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
IKobayashi 0:c88c3b616c00 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
IKobayashi 0:c88c3b616c00 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
IKobayashi 0:c88c3b616c00 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
IKobayashi 0:c88c3b616c00 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
IKobayashi 0:c88c3b616c00 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
IKobayashi 0:c88c3b616c00 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
IKobayashi 0:c88c3b616c00 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
IKobayashi 0:c88c3b616c00 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
IKobayashi 0:c88c3b616c00 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
IKobayashi 0:c88c3b616c00 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
IKobayashi 0:c88c3b616c00 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
IKobayashi 0:c88c3b616c00 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
IKobayashi 0:c88c3b616c00 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
IKobayashi 0:c88c3b616c00 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
IKobayashi 0:c88c3b616c00 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
IKobayashi 0:c88c3b616c00 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
IKobayashi 0:c88c3b616c00 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
IKobayashi 0:c88c3b616c00 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
IKobayashi 0:c88c3b616c00 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
IKobayashi 0:c88c3b616c00 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
IKobayashi 0:c88c3b616c00 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
IKobayashi 0:c88c3b616c00 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
IKobayashi 0:c88c3b616c00 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
IKobayashi 0:c88c3b616c00 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
IKobayashi 0:c88c3b616c00 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
IKobayashi 0:c88c3b616c00 1034
IKobayashi 0:c88c3b616c00 1035 #endif // __LPC17xx_H__