Diff: arch/int/W7500x_toe.cpp

Revision:

14:2101ab5ee40f

Parent:

8:4c02de1dbf3a

Child:

15:24a9f2df2145

diff -r ec1c34e9ec45 -r 2101ab5ee40f arch/int/W7500x_toe.cpp
--- a/arch/int/W7500x_toe.cpp	Tue Jun 16 13:03:28 2015 +0900
+++ b/arch/int/W7500x_toe.cpp	Wed Jun 17 00:24:45 2015 +0000
@@ -481,11 +481,11 @@
 	idle_MDIO(GPIOx);
 }
 
-int ethernet_link(void) {
+int WIZnet_Chip::ethernet_link(void) {
 	return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01); 
 }
 
-void ethernet_set_link(int speed, int duplex) {
+void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
 	uint32_t val=0;
 	if((speed < 0) || (speed > 1)) {
 		val = CNTL_AUTONEGO; 
@@ -494,5 +494,37 @@
 	}
 	mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
 }
+
+   void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data) 
+   {
+       	data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
+       	data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
+       	data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
+       	data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
+       	data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
+       	data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
+    }
+
+    void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
+    {
+        uint8_t buf[4]={0,};
+		uint32_t wr_ip = 0;
+        char* p = (char*)ip;
+        
+        for(int i = 0; i < 4; i++) {
+            wr_ip = (wr_ip<<8);
+            buf[i] = atoi(p);
+            wr_ip |= buf[i];
+            p = strchr(p, '.');
+            if (p == NULL) break;
+            p++;
+        }
+       	*(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
+    }
+
+    void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
+        reg_wr_ip(addr,  (uint8_t)(0x01+(socket<<2)), ip);
+    }
+
 #endif