Helmut Tschemernjak / USBDeviceHT

A copy of the mbed USBDevice with USBSerial library

Dependents:   STM32L0_LoRa Smartage STM32L0_LoRa Turtle_RadioShuttle

targets/TARGET_STM/USBRegs_STM32.h@7:8a5cc0d9bfa2, 2019-01-31 (annotated)

Committer:
Helmut Tschemernjak
Date:
Thu Jan 31 20:56:55 2019 +0100
Revision:
7:8a5cc0d9bfa2
Parent:
0:a3ea811f80f2 
fixed compiler warnings

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Helmut64 0:a3ea811f80f2 1 /**
Helmut64 0:a3ea811f80f2 2 ******************************************************************************
Helmut64 0:a3ea811f80f2 3 * @file usb_regs.h
Helmut64 0:a3ea811f80f2 4 * @author MCD Application Team
Helmut64 0:a3ea811f80f2 5 * @version V2.1.0
Helmut64 0:a3ea811f80f2 6 * @date 19-March-2012
Helmut64 0:a3ea811f80f2 7 * @brief hardware registers
Helmut64 0:a3ea811f80f2 8 ******************************************************************************
Helmut64 0:a3ea811f80f2 9 * @attention
Helmut64 0:a3ea811f80f2 10 *
Helmut64 0:a3ea811f80f2 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
Helmut64 0:a3ea811f80f2 12 *
Helmut64 0:a3ea811f80f2 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
Helmut64 0:a3ea811f80f2 14 * You may not use this file except in compliance with the License.
Helmut64 0:a3ea811f80f2 15 * You may obtain a copy of the License at:
Helmut64 0:a3ea811f80f2 16 *
Helmut64 0:a3ea811f80f2 17 * http://www.st.com/software_license_agreement_liberty_v2
Helmut64 0:a3ea811f80f2 18 *
Helmut64 0:a3ea811f80f2 19 * Unless required by applicable law or agreed to in writing, software
Helmut64 0:a3ea811f80f2 20 * distributed under the License is distributed on an "AS IS" BASIS,
Helmut64 0:a3ea811f80f2 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Helmut64 0:a3ea811f80f2 22 * See the License for the specific language governing permissions and
Helmut64 0:a3ea811f80f2 23 * limitations under the License.
Helmut64 0:a3ea811f80f2 24 *
Helmut64 0:a3ea811f80f2 25 ******************************************************************************
Helmut64 0:a3ea811f80f2 26 */
Helmut64 0:a3ea811f80f2 27
Helmut64 0:a3ea811f80f2 28 #ifndef __USB_OTG_REGS_H__
Helmut64 0:a3ea811f80f2 29 #define __USB_OTG_REGS_H__
Helmut64 0:a3ea811f80f2 30
Helmut64 0:a3ea811f80f2 31 typedef struct //000h
Helmut64 0:a3ea811f80f2 32 {
Helmut64 0:a3ea811f80f2 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
Helmut64 0:a3ea811f80f2 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
Helmut64 0:a3ea811f80f2 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
Helmut64 0:a3ea811f80f2 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
Helmut64 0:a3ea811f80f2 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
Helmut64 0:a3ea811f80f2 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
Helmut64 0:a3ea811f80f2 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
Helmut64 0:a3ea811f80f2 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
Helmut64 0:a3ea811f80f2 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
Helmut64 0:a3ea811f80f2 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
Helmut64 0:a3ea811f80f2 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
Helmut64 0:a3ea811f80f2 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
Helmut64 0:a3ea811f80f2 45 uint32_t Reserved30[2]; /* Reserved 030h*/
Helmut64 0:a3ea811f80f2 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
Helmut64 0:a3ea811f80f2 47 __IO uint32_t CID; /* User ID Register 03Ch*/
Helmut64 0:a3ea811f80f2 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
Helmut64 0:a3ea811f80f2 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
Helmut64 0:a3ea811f80f2 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
Helmut64 0:a3ea811f80f2 51 }
Helmut64 0:a3ea811f80f2 52 USB_OTG_GREGS;
Helmut64 0:a3ea811f80f2 53
Helmut64 0:a3ea811f80f2 54 typedef struct // 800h
Helmut64 0:a3ea811f80f2 55 {
Helmut64 0:a3ea811f80f2 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
Helmut64 0:a3ea811f80f2 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
Helmut64 0:a3ea811f80f2 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
Helmut64 0:a3ea811f80f2 59 uint32_t Reserved0C; /* Reserved 80Ch*/
Helmut64 0:a3ea811f80f2 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
Helmut64 0:a3ea811f80f2 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
Helmut64 0:a3ea811f80f2 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
Helmut64 0:a3ea811f80f2 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
Helmut64 0:a3ea811f80f2 64 uint32_t Reserved20; /* Reserved 820h*/
Helmut64 0:a3ea811f80f2 65 uint32_t Reserved9; /* Reserved 824h*/
Helmut64 0:a3ea811f80f2 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
Helmut64 0:a3ea811f80f2 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
Helmut64 0:a3ea811f80f2 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
Helmut64 0:a3ea811f80f2 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
Helmut64 0:a3ea811f80f2 70 }
Helmut64 0:a3ea811f80f2 71 USB_OTG_DREGS;
Helmut64 0:a3ea811f80f2 72
Helmut64 0:a3ea811f80f2 73 typedef struct
Helmut64 0:a3ea811f80f2 74 {
Helmut64 0:a3ea811f80f2 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
Helmut64 0:a3ea811f80f2 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
Helmut64 0:a3ea811f80f2 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
Helmut64 0:a3ea811f80f2 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
Helmut64 0:a3ea811f80f2 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
Helmut64 0:a3ea811f80f2 80 uint32_t Reserved14;
Helmut64 0:a3ea811f80f2 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
Helmut64 0:a3ea811f80f2 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
Helmut64 0:a3ea811f80f2 83 }
Helmut64 0:a3ea811f80f2 84 USB_OTG_INEPREGS;
Helmut64 0:a3ea811f80f2 85
Helmut64 0:a3ea811f80f2 86 typedef struct
Helmut64 0:a3ea811f80f2 87 {
Helmut64 0:a3ea811f80f2 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
Helmut64 0:a3ea811f80f2 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
Helmut64 0:a3ea811f80f2 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
Helmut64 0:a3ea811f80f2 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
Helmut64 0:a3ea811f80f2 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
Helmut64 0:a3ea811f80f2 93 uint32_t Reserved14[3];
Helmut64 0:a3ea811f80f2 94 }
Helmut64 0:a3ea811f80f2 95 USB_OTG_OUTEPREGS;
Helmut64 0:a3ea811f80f2 96
Helmut64 0:a3ea811f80f2 97 typedef struct
Helmut64 0:a3ea811f80f2 98 {
Helmut64 0:a3ea811f80f2 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
Helmut64 0:a3ea811f80f2 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
Helmut64 0:a3ea811f80f2 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
Helmut64 0:a3ea811f80f2 102 uint32_t Reserved40C; /* Reserved 40Ch*/
Helmut64 0:a3ea811f80f2 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
Helmut64 0:a3ea811f80f2 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
Helmut64 0:a3ea811f80f2 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
Helmut64 0:a3ea811f80f2 106 }
Helmut64 0:a3ea811f80f2 107 USB_OTG_HREGS;
Helmut64 0:a3ea811f80f2 108
Helmut64 0:a3ea811f80f2 109 typedef struct
Helmut64 0:a3ea811f80f2 110 {
Helmut64 0:a3ea811f80f2 111 __IO uint32_t HCCHAR;
Helmut64 0:a3ea811f80f2 112 __IO uint32_t HCSPLT;
Helmut64 0:a3ea811f80f2 113 __IO uint32_t HCINT;
Helmut64 0:a3ea811f80f2 114 __IO uint32_t HCINTMSK;
Helmut64 0:a3ea811f80f2 115 __IO uint32_t HCTSIZ;
Helmut64 0:a3ea811f80f2 116 uint32_t Reserved[3];
Helmut64 0:a3ea811f80f2 117 }
Helmut64 0:a3ea811f80f2 118 USB_OTG_HC_REGS;
Helmut64 0:a3ea811f80f2 119
Helmut64 0:a3ea811f80f2 120 typedef struct
Helmut64 0:a3ea811f80f2 121 {
Helmut64 0:a3ea811f80f2 122 USB_OTG_GREGS GREGS;
Helmut64 0:a3ea811f80f2 123 uint32_t RESERVED0[188];
Helmut64 0:a3ea811f80f2 124 USB_OTG_HREGS HREGS;
Helmut64 0:a3ea811f80f2 125 uint32_t RESERVED1[9];
Helmut64 0:a3ea811f80f2 126 __IO uint32_t HPRT;
Helmut64 0:a3ea811f80f2 127 uint32_t RESERVED2[47];
Helmut64 0:a3ea811f80f2 128 USB_OTG_HC_REGS HC_REGS[8];
Helmut64 0:a3ea811f80f2 129 uint32_t RESERVED3[128];
Helmut64 0:a3ea811f80f2 130 USB_OTG_DREGS DREGS;
Helmut64 0:a3ea811f80f2 131 uint32_t RESERVED4[50];
Helmut64 0:a3ea811f80f2 132 USB_OTG_INEPREGS INEP_REGS[4];
Helmut64 0:a3ea811f80f2 133 uint32_t RESERVED5[96];
Helmut64 0:a3ea811f80f2 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
Helmut64 0:a3ea811f80f2 135 uint32_t RESERVED6[160];
Helmut64 0:a3ea811f80f2 136 __IO uint32_t PCGCCTL;
Helmut64 0:a3ea811f80f2 137 uint32_t RESERVED7[127];
Helmut64 0:a3ea811f80f2 138 __IO uint32_t FIFO[4][1024];
Helmut64 0:a3ea811f80f2 139 }
Helmut64 0:a3ea811f80f2 140 USB_OTG_CORE_REGS;
Helmut64 0:a3ea811f80f2 141
Helmut64 0:a3ea811f80f2 142
Helmut64 0:a3ea811f80f2 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
Helmut64 0:a3ea811f80f2 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
Helmut64 0:a3ea811f80f2 145
Helmut64 0:a3ea811f80f2 146 #endif //__USB_OTG_REGS_H__
Helmut64 0:a3ea811f80f2 147
Helmut64 0:a3ea811f80f2 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Helmut64 0:a3ea811f80f2 149