Guillaume Mourozeau / Mbed 2 deprecated Lab4_BluetoothRobot

Bluetooth-controlled Robot with RFID switching mode

Dependencies:   Motor mbed-rtos mbed

MFRC522.h@0:64f17142aa89, 2016-03-13 (annotated)

Committer:
GuillaumeMrzo
Date:
Sun Mar 13 03:51:00 2016 +0000
Revision:
0:64f17142aa89
Bluetooth-controlled Robot with RFID switching mode

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GuillaumeMrzo 0:64f17142aa89 1 /**
GuillaumeMrzo 0:64f17142aa89 2 * MFRC522.h - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
GuillaumeMrzo 0:64f17142aa89 3 * Based on code Dr.Leong ( WWW.B2CQSHOP.COM )
GuillaumeMrzo 0:64f17142aa89 4 * Created by Miguel Balboa (circuitito.com), Jan, 2012.
GuillaumeMrzo 0:64f17142aa89 5 * Rewritten by Soren Thing Andersen (access.thing.dk), fall of 2013 (Translation to English, refactored, comments, anti collision, cascade levels.)
GuillaumeMrzo 0:64f17142aa89 6 * Ported to mbed by Martin Olejar, Dec, 2013
GuillaumeMrzo 0:64f17142aa89 7 *
GuillaumeMrzo 0:64f17142aa89 8 * Please read this file for an overview and then MFRC522.cpp for comments on the specific functions.
GuillaumeMrzo 0:64f17142aa89 9 * Search for "mf-rc522" on ebay.com to purchase the MF-RC522 board.
GuillaumeMrzo 0:64f17142aa89 10 *
GuillaumeMrzo 0:64f17142aa89 11 * There are three hardware components involved:
GuillaumeMrzo 0:64f17142aa89 12 * 1) The micro controller: An Arduino
GuillaumeMrzo 0:64f17142aa89 13 * 2) The PCD (short for Proximity Coupling Device): NXP MFRC522 Contactless Reader IC
GuillaumeMrzo 0:64f17142aa89 14 * 3) The PICC (short for Proximity Integrated Circuit Card): A card or tag using the ISO 14443A interface, eg Mifare or NTAG203.
GuillaumeMrzo 0:64f17142aa89 15 *
GuillaumeMrzo 0:64f17142aa89 16 * The microcontroller and card reader uses SPI for communication.
GuillaumeMrzo 0:64f17142aa89 17 * The protocol is described in the MFRC522 datasheet: http://www.nxp.com/documents/data_sheet/MFRC522.pdf
GuillaumeMrzo 0:64f17142aa89 18 *
GuillaumeMrzo 0:64f17142aa89 19 * The card reader and the tags communicate using a 13.56MHz electromagnetic field.
GuillaumeMrzo 0:64f17142aa89 20 * The protocol is defined in ISO/IEC 14443-3 Identification cards -- Contactless integrated circuit cards -- Proximity cards -- Part 3: Initialization and anticollision".
GuillaumeMrzo 0:64f17142aa89 21 * A free version of the final draft can be found at http://wg8.de/wg8n1496_17n3613_Ballot_FCD14443-3.pdf
GuillaumeMrzo 0:64f17142aa89 22 * Details are found in chapter 6, Type A: Initialization and anticollision.
GuillaumeMrzo 0:64f17142aa89 23 *
GuillaumeMrzo 0:64f17142aa89 24 * If only the PICC UID is wanted, the above documents has all the needed information.
GuillaumeMrzo 0:64f17142aa89 25 * To read and write from MIFARE PICCs, the MIFARE protocol is used after the PICC has been selected.
GuillaumeMrzo 0:64f17142aa89 26 * The MIFARE Classic chips and protocol is described in the datasheets:
GuillaumeMrzo 0:64f17142aa89 27 * 1K: http://www.nxp.com/documents/data_sheet/MF1S503x.pdf
GuillaumeMrzo 0:64f17142aa89 28 * 4K: http://www.nxp.com/documents/data_sheet/MF1S703x.pdf
GuillaumeMrzo 0:64f17142aa89 29 * Mini: http://www.idcardmarket.com/download/mifare_S20_datasheet.pdf
GuillaumeMrzo 0:64f17142aa89 30 * The MIFARE Ultralight chip and protocol is described in the datasheets:
GuillaumeMrzo 0:64f17142aa89 31 * Ultralight: http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf
GuillaumeMrzo 0:64f17142aa89 32 * Ultralight C: http://www.nxp.com/documents/short_data_sheet/MF0ICU2_SDS.pdf
GuillaumeMrzo 0:64f17142aa89 33 *
GuillaumeMrzo 0:64f17142aa89 34 * MIFARE Classic 1K (MF1S503x):
GuillaumeMrzo 0:64f17142aa89 35 * Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
GuillaumeMrzo 0:64f17142aa89 36 * The blocks are numbered 0-63.
GuillaumeMrzo 0:64f17142aa89 37 * Block 3 in each sector is the Sector Trailer. See http://www.nxp.com/documents/data_sheet/MF1S503x.pdf sections 8.6 and 8.7:
GuillaumeMrzo 0:64f17142aa89 38 * Bytes 0-5: Key A
GuillaumeMrzo 0:64f17142aa89 39 * Bytes 6-8: Access Bits
GuillaumeMrzo 0:64f17142aa89 40 * Bytes 9: User data
GuillaumeMrzo 0:64f17142aa89 41 * Bytes 10-15: Key B (or user data)
GuillaumeMrzo 0:64f17142aa89 42 * Block 0 is read only manufacturer data.
GuillaumeMrzo 0:64f17142aa89 43 * To access a block, an authentication using a key from the block's sector must be performed first.
GuillaumeMrzo 0:64f17142aa89 44 * Example: To read from block 10, first authenticate using a key from sector 3 (blocks 8-11).
GuillaumeMrzo 0:64f17142aa89 45 * All keys are set to FFFFFFFFFFFFh at chip delivery.
GuillaumeMrzo 0:64f17142aa89 46 * Warning: Please read section 8.7 "Memory Access". It includes this text: if the PICC detects a format violation the whole sector is irreversibly blocked.
GuillaumeMrzo 0:64f17142aa89 47 * To use a block in "value block" mode (for Increment/Decrement operations) you need to change the sector trailer. Use PICC_SetAccessBits() to calculate the bit patterns.
GuillaumeMrzo 0:64f17142aa89 48 * MIFARE Classic 4K (MF1S703x):
GuillaumeMrzo 0:64f17142aa89 49 * Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
GuillaumeMrzo 0:64f17142aa89 50 * The blocks are numbered 0-255.
GuillaumeMrzo 0:64f17142aa89 51 * The last block in each sector is the Sector Trailer like above.
GuillaumeMrzo 0:64f17142aa89 52 * MIFARE Classic Mini (MF1 IC S20):
GuillaumeMrzo 0:64f17142aa89 53 * Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
GuillaumeMrzo 0:64f17142aa89 54 * The blocks are numbered 0-19.
GuillaumeMrzo 0:64f17142aa89 55 * The last block in each sector is the Sector Trailer like above.
GuillaumeMrzo 0:64f17142aa89 56 *
GuillaumeMrzo 0:64f17142aa89 57 * MIFARE Ultralight (MF0ICU1):
GuillaumeMrzo 0:64f17142aa89 58 * Has 16 pages of 4 bytes = 64 bytes.
GuillaumeMrzo 0:64f17142aa89 59 * Pages 0 + 1 is used for the 7-byte UID.
GuillaumeMrzo 0:64f17142aa89 60 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
GuillaumeMrzo 0:64f17142aa89 61 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
GuillaumeMrzo 0:64f17142aa89 62 * Pages 4-15 are read/write unless blocked by the lock bytes in page 2.
GuillaumeMrzo 0:64f17142aa89 63 * MIFARE Ultralight C (MF0ICU2):
GuillaumeMrzo 0:64f17142aa89 64 * Has 48 pages of 4 bytes = 64 bytes.
GuillaumeMrzo 0:64f17142aa89 65 * Pages 0 + 1 is used for the 7-byte UID.
GuillaumeMrzo 0:64f17142aa89 66 * Page 2 contains the last chech digit for the UID, one byte manufacturer internal data, and the lock bytes (see http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf section 8.5.2)
GuillaumeMrzo 0:64f17142aa89 67 * Page 3 is OTP, One Time Programmable bits. Once set to 1 they cannot revert to 0.
GuillaumeMrzo 0:64f17142aa89 68 * Pages 4-39 are read/write unless blocked by the lock bytes in page 2.
GuillaumeMrzo 0:64f17142aa89 69 * Page 40 Lock bytes
GuillaumeMrzo 0:64f17142aa89 70 * Page 41 16 bit one way counter
GuillaumeMrzo 0:64f17142aa89 71 * Pages 42-43 Authentication configuration
GuillaumeMrzo 0:64f17142aa89 72 * Pages 44-47 Authentication key
GuillaumeMrzo 0:64f17142aa89 73 */
GuillaumeMrzo 0:64f17142aa89 74 #ifndef MFRC522_h
GuillaumeMrzo 0:64f17142aa89 75 #define MFRC522_h
GuillaumeMrzo 0:64f17142aa89 76
GuillaumeMrzo 0:64f17142aa89 77 #include "mbed.h"
GuillaumeMrzo 0:64f17142aa89 78
GuillaumeMrzo 0:64f17142aa89 79 /**
GuillaumeMrzo 0:64f17142aa89 80 * MFRC522 example
GuillaumeMrzo 0:64f17142aa89 81 *
GuillaumeMrzo 0:64f17142aa89 82 * @code
GuillaumeMrzo 0:64f17142aa89 83 * #include "mbed.h"
GuillaumeMrzo 0:64f17142aa89 84 * #include "MFRC522.h"
GuillaumeMrzo 0:64f17142aa89 85 *
GuillaumeMrzo 0:64f17142aa89 86 * //KL25Z Pins for MFRC522 SPI interface
GuillaumeMrzo 0:64f17142aa89 87 * #define SPI_MOSI PTC6
GuillaumeMrzo 0:64f17142aa89 88 * #define SPI_MISO PTC7
GuillaumeMrzo 0:64f17142aa89 89 * #define SPI_SCLK PTC5
GuillaumeMrzo 0:64f17142aa89 90 * #define SPI_CS PTC4
GuillaumeMrzo 0:64f17142aa89 91 * // KL25Z Pin for MFRC522 reset
GuillaumeMrzo 0:64f17142aa89 92 * #define MF_RESET PTC3
GuillaumeMrzo 0:64f17142aa89 93 * // KL25Z Pins for Debug UART port
GuillaumeMrzo 0:64f17142aa89 94 * #define UART_RX PTA1
GuillaumeMrzo 0:64f17142aa89 95 * #define UART_TX PTA2
GuillaumeMrzo 0:64f17142aa89 96 *
GuillaumeMrzo 0:64f17142aa89 97 * DigitalOut LedRed (LED_RED);
GuillaumeMrzo 0:64f17142aa89 98 * DigitalOut LedGreen (LED_GREEN);
GuillaumeMrzo 0:64f17142aa89 99 *
GuillaumeMrzo 0:64f17142aa89 100 * Serial DebugUART(UART_TX, UART_RX);
GuillaumeMrzo 0:64f17142aa89 101 * MFRC522 RfChip (SPI_MOSI, SPI_MISO, SPI_SCLK, SPI_CS, MF_RESET);
GuillaumeMrzo 0:64f17142aa89 102 *
GuillaumeMrzo 0:64f17142aa89 103 * int main(void) {
GuillaumeMrzo 0:64f17142aa89 104 * // Set debug UART speed
GuillaumeMrzo 0:64f17142aa89 105 * DebugUART.baud(115200);
GuillaumeMrzo 0:64f17142aa89 106 *
GuillaumeMrzo 0:64f17142aa89 107 * // Init. RC522 Chip
GuillaumeMrzo 0:64f17142aa89 108 * RfChip.PCD_Init();
GuillaumeMrzo 0:64f17142aa89 109 *
GuillaumeMrzo 0:64f17142aa89 110 * while (true) {
GuillaumeMrzo 0:64f17142aa89 111 * LedRed = 1;
GuillaumeMrzo 0:64f17142aa89 112 * LedGreen = 1;
GuillaumeMrzo 0:64f17142aa89 113 *
GuillaumeMrzo 0:64f17142aa89 114 * // Look for new cards
GuillaumeMrzo 0:64f17142aa89 115 * if ( ! RfChip.PICC_IsNewCardPresent())
GuillaumeMrzo 0:64f17142aa89 116 * {
GuillaumeMrzo 0:64f17142aa89 117 * wait_ms(500);
GuillaumeMrzo 0:64f17142aa89 118 * continue;
GuillaumeMrzo 0:64f17142aa89 119 * }
GuillaumeMrzo 0:64f17142aa89 120 *
GuillaumeMrzo 0:64f17142aa89 121 * LedRed = 0;
GuillaumeMrzo 0:64f17142aa89 122 *
GuillaumeMrzo 0:64f17142aa89 123 * // Select one of the cards
GuillaumeMrzo 0:64f17142aa89 124 * if ( ! RfChip.PICC_ReadCardSerial())
GuillaumeMrzo 0:64f17142aa89 125 * {
GuillaumeMrzo 0:64f17142aa89 126 * wait_ms(500);
GuillaumeMrzo 0:64f17142aa89 127 * continue;
GuillaumeMrzo 0:64f17142aa89 128 * }
GuillaumeMrzo 0:64f17142aa89 129 *
GuillaumeMrzo 0:64f17142aa89 130 * LedRed = 1;
GuillaumeMrzo 0:64f17142aa89 131 * LedGreen = 0;
GuillaumeMrzo 0:64f17142aa89 132 *
GuillaumeMrzo 0:64f17142aa89 133 * // Print Card UID
GuillaumeMrzo 0:64f17142aa89 134 * printf("Card UID: ");
GuillaumeMrzo 0:64f17142aa89 135 * for (uint8_t i = 0; i < RfChip.uid.size; i++)
GuillaumeMrzo 0:64f17142aa89 136 * {
GuillaumeMrzo 0:64f17142aa89 137 * printf(" %X02", RfChip.uid.uidByte[i]);
GuillaumeMrzo 0:64f17142aa89 138 * }
GuillaumeMrzo 0:64f17142aa89 139 * printf("\n\r");
GuillaumeMrzo 0:64f17142aa89 140 *
GuillaumeMrzo 0:64f17142aa89 141 * // Print Card type
GuillaumeMrzo 0:64f17142aa89 142 * uint8_t piccType = RfChip.PICC_GetType(RfChip.uid.sak);
GuillaumeMrzo 0:64f17142aa89 143 * printf("PICC Type: %s \n\r", RfChip.PICC_GetTypeName(piccType));
GuillaumeMrzo 0:64f17142aa89 144 * wait_ms(1000);
GuillaumeMrzo 0:64f17142aa89 145 * }
GuillaumeMrzo 0:64f17142aa89 146 * }
GuillaumeMrzo 0:64f17142aa89 147 * @endcode
GuillaumeMrzo 0:64f17142aa89 148 */
GuillaumeMrzo 0:64f17142aa89 149
GuillaumeMrzo 0:64f17142aa89 150 class MFRC522 {
GuillaumeMrzo 0:64f17142aa89 151 public:
GuillaumeMrzo 0:64f17142aa89 152
GuillaumeMrzo 0:64f17142aa89 153 /**
GuillaumeMrzo 0:64f17142aa89 154 * MFRC522 registers (described in chapter 9 of the datasheet).
GuillaumeMrzo 0:64f17142aa89 155 * When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
GuillaumeMrzo 0:64f17142aa89 156 */
GuillaumeMrzo 0:64f17142aa89 157 enum PCD_Register {
GuillaumeMrzo 0:64f17142aa89 158 // Page 0: Command and status
GuillaumeMrzo 0:64f17142aa89 159 // 0x00 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 160 CommandReg = 0x01 << 1, // starts and stops command execution
GuillaumeMrzo 0:64f17142aa89 161 ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
GuillaumeMrzo 0:64f17142aa89 162 DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
GuillaumeMrzo 0:64f17142aa89 163 ComIrqReg = 0x04 << 1, // interrupt request bits
GuillaumeMrzo 0:64f17142aa89 164 DivIrqReg = 0x05 << 1, // interrupt request bits
GuillaumeMrzo 0:64f17142aa89 165 ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
GuillaumeMrzo 0:64f17142aa89 166 Status1Reg = 0x07 << 1, // communication status bits
GuillaumeMrzo 0:64f17142aa89 167 Status2Reg = 0x08 << 1, // receiver and transmitter status bits
GuillaumeMrzo 0:64f17142aa89 168 FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
GuillaumeMrzo 0:64f17142aa89 169 FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
GuillaumeMrzo 0:64f17142aa89 170 WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
GuillaumeMrzo 0:64f17142aa89 171 ControlReg = 0x0C << 1, // miscellaneous control registers
GuillaumeMrzo 0:64f17142aa89 172 BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
GuillaumeMrzo 0:64f17142aa89 173 CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
GuillaumeMrzo 0:64f17142aa89 174 // 0x0F // reserved for future use
GuillaumeMrzo 0:64f17142aa89 175
GuillaumeMrzo 0:64f17142aa89 176 // Page 1:Command
GuillaumeMrzo 0:64f17142aa89 177 // 0x10 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 178 ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
GuillaumeMrzo 0:64f17142aa89 179 TxModeReg = 0x12 << 1, // defines transmission data rate and framing
GuillaumeMrzo 0:64f17142aa89 180 RxModeReg = 0x13 << 1, // defines reception data rate and framing
GuillaumeMrzo 0:64f17142aa89 181 TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
GuillaumeMrzo 0:64f17142aa89 182 TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
GuillaumeMrzo 0:64f17142aa89 183 TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
GuillaumeMrzo 0:64f17142aa89 184 RxSelReg = 0x17 << 1, // selects internal receiver settings
GuillaumeMrzo 0:64f17142aa89 185 RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
GuillaumeMrzo 0:64f17142aa89 186 DemodReg = 0x19 << 1, // defines demodulator settings
GuillaumeMrzo 0:64f17142aa89 187 // 0x1A // reserved for future use
GuillaumeMrzo 0:64f17142aa89 188 // 0x1B // reserved for future use
GuillaumeMrzo 0:64f17142aa89 189 MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
GuillaumeMrzo 0:64f17142aa89 190 MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
GuillaumeMrzo 0:64f17142aa89 191 // 0x1E // reserved for future use
GuillaumeMrzo 0:64f17142aa89 192 SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
GuillaumeMrzo 0:64f17142aa89 193
GuillaumeMrzo 0:64f17142aa89 194 // Page 2: Configuration
GuillaumeMrzo 0:64f17142aa89 195 // 0x20 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 196 CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
GuillaumeMrzo 0:64f17142aa89 197 CRCResultRegL = 0x22 << 1,
GuillaumeMrzo 0:64f17142aa89 198 // 0x23 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 199 ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
GuillaumeMrzo 0:64f17142aa89 200 // 0x25 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 201 RFCfgReg = 0x26 << 1, // configures the receiver gain
GuillaumeMrzo 0:64f17142aa89 202 GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
GuillaumeMrzo 0:64f17142aa89 203 CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
GuillaumeMrzo 0:64f17142aa89 204 ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
GuillaumeMrzo 0:64f17142aa89 205 TModeReg = 0x2A << 1, // defines settings for the internal timer
GuillaumeMrzo 0:64f17142aa89 206 TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
GuillaumeMrzo 0:64f17142aa89 207 TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
GuillaumeMrzo 0:64f17142aa89 208 TReloadRegL = 0x2D << 1,
GuillaumeMrzo 0:64f17142aa89 209 TCntValueRegH = 0x2E << 1, // shows the 16-bit timer value
GuillaumeMrzo 0:64f17142aa89 210 TCntValueRegL = 0x2F << 1,
GuillaumeMrzo 0:64f17142aa89 211
GuillaumeMrzo 0:64f17142aa89 212 // Page 3:Test Registers
GuillaumeMrzo 0:64f17142aa89 213 // 0x30 // reserved for future use
GuillaumeMrzo 0:64f17142aa89 214 TestSel1Reg = 0x31 << 1, // general test signal configuration
GuillaumeMrzo 0:64f17142aa89 215 TestSel2Reg = 0x32 << 1, // general test signal configuration
GuillaumeMrzo 0:64f17142aa89 216 TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
GuillaumeMrzo 0:64f17142aa89 217 TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
GuillaumeMrzo 0:64f17142aa89 218 TestBusReg = 0x35 << 1, // shows the status of the internal test bus
GuillaumeMrzo 0:64f17142aa89 219 AutoTestReg = 0x36 << 1, // controls the digital self test
GuillaumeMrzo 0:64f17142aa89 220 VersionReg = 0x37 << 1, // shows the software version
GuillaumeMrzo 0:64f17142aa89 221 AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
GuillaumeMrzo 0:64f17142aa89 222 TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
GuillaumeMrzo 0:64f17142aa89 223 TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
GuillaumeMrzo 0:64f17142aa89 224 TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
GuillaumeMrzo 0:64f17142aa89 225 // 0x3C // reserved for production tests
GuillaumeMrzo 0:64f17142aa89 226 // 0x3D // reserved for production tests
GuillaumeMrzo 0:64f17142aa89 227 // 0x3E // reserved for production tests
GuillaumeMrzo 0:64f17142aa89 228 // 0x3F // reserved for production tests
GuillaumeMrzo 0:64f17142aa89 229 };
GuillaumeMrzo 0:64f17142aa89 230
GuillaumeMrzo 0:64f17142aa89 231 // MFRC522 commands Described in chapter 10 of the datasheet.
GuillaumeMrzo 0:64f17142aa89 232 enum PCD_Command {
GuillaumeMrzo 0:64f17142aa89 233 PCD_Idle = 0x00, // no action, cancels current command execution
GuillaumeMrzo 0:64f17142aa89 234 PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
GuillaumeMrzo 0:64f17142aa89 235 PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
GuillaumeMrzo 0:64f17142aa89 236 PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
GuillaumeMrzo 0:64f17142aa89 237 PCD_Transmit = 0x04, // transmits data from the FIFO buffer
GuillaumeMrzo 0:64f17142aa89 238 PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
GuillaumeMrzo 0:64f17142aa89 239 PCD_Receive = 0x08, // activates the receiver circuits
GuillaumeMrzo 0:64f17142aa89 240 PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
GuillaumeMrzo 0:64f17142aa89 241 PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
GuillaumeMrzo 0:64f17142aa89 242 PCD_SoftReset = 0x0F // resets the MFRC522
GuillaumeMrzo 0:64f17142aa89 243 };
GuillaumeMrzo 0:64f17142aa89 244
GuillaumeMrzo 0:64f17142aa89 245 // Commands sent to the PICC.
GuillaumeMrzo 0:64f17142aa89 246 enum PICC_Command {
GuillaumeMrzo 0:64f17142aa89 247 // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
GuillaumeMrzo 0:64f17142aa89 248 PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
GuillaumeMrzo 0:64f17142aa89 249 PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
GuillaumeMrzo 0:64f17142aa89 250 PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
GuillaumeMrzo 0:64f17142aa89 251 PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
GuillaumeMrzo 0:64f17142aa89 252 PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
GuillaumeMrzo 0:64f17142aa89 253 PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
GuillaumeMrzo 0:64f17142aa89 254 PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
GuillaumeMrzo 0:64f17142aa89 255
GuillaumeMrzo 0:64f17142aa89 256 // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
GuillaumeMrzo 0:64f17142aa89 257 // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
GuillaumeMrzo 0:64f17142aa89 258 // The read/write commands can also be used for MIFARE Ultralight.
GuillaumeMrzo 0:64f17142aa89 259 PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
GuillaumeMrzo 0:64f17142aa89 260 PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
GuillaumeMrzo 0:64f17142aa89 261 PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
GuillaumeMrzo 0:64f17142aa89 262 PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
GuillaumeMrzo 0:64f17142aa89 263 PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
GuillaumeMrzo 0:64f17142aa89 264 PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
GuillaumeMrzo 0:64f17142aa89 265 PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
GuillaumeMrzo 0:64f17142aa89 266 PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
GuillaumeMrzo 0:64f17142aa89 267
GuillaumeMrzo 0:64f17142aa89 268 // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
GuillaumeMrzo 0:64f17142aa89 269 // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
GuillaumeMrzo 0:64f17142aa89 270 PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
GuillaumeMrzo 0:64f17142aa89 271 };
GuillaumeMrzo 0:64f17142aa89 272
GuillaumeMrzo 0:64f17142aa89 273 // MIFARE constants that does not fit anywhere else
GuillaumeMrzo 0:64f17142aa89 274 enum MIFARE_Misc {
GuillaumeMrzo 0:64f17142aa89 275 MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
GuillaumeMrzo 0:64f17142aa89 276 MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
GuillaumeMrzo 0:64f17142aa89 277 };
GuillaumeMrzo 0:64f17142aa89 278
GuillaumeMrzo 0:64f17142aa89 279 // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
GuillaumeMrzo 0:64f17142aa89 280 enum PICC_Type {
GuillaumeMrzo 0:64f17142aa89 281 PICC_TYPE_UNKNOWN = 0,
GuillaumeMrzo 0:64f17142aa89 282 PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
GuillaumeMrzo 0:64f17142aa89 283 PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
GuillaumeMrzo 0:64f17142aa89 284 PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
GuillaumeMrzo 0:64f17142aa89 285 PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
GuillaumeMrzo 0:64f17142aa89 286 PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
GuillaumeMrzo 0:64f17142aa89 287 PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
GuillaumeMrzo 0:64f17142aa89 288 PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
GuillaumeMrzo 0:64f17142aa89 289 PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
GuillaumeMrzo 0:64f17142aa89 290 PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
GuillaumeMrzo 0:64f17142aa89 291 };
GuillaumeMrzo 0:64f17142aa89 292
GuillaumeMrzo 0:64f17142aa89 293 // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
GuillaumeMrzo 0:64f17142aa89 294 enum StatusCode {
GuillaumeMrzo 0:64f17142aa89 295 STATUS_OK = 1, // Success
GuillaumeMrzo 0:64f17142aa89 296 STATUS_ERROR = 2, // Error in communication
GuillaumeMrzo 0:64f17142aa89 297 STATUS_COLLISION = 3, // Collision detected
GuillaumeMrzo 0:64f17142aa89 298 STATUS_TIMEOUT = 4, // Timeout in communication.
GuillaumeMrzo 0:64f17142aa89 299 STATUS_NO_ROOM = 5, // A buffer is not big enough.
GuillaumeMrzo 0:64f17142aa89 300 STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
GuillaumeMrzo 0:64f17142aa89 301 STATUS_INVALID = 7, // Invalid argument.
GuillaumeMrzo 0:64f17142aa89 302 STATUS_CRC_WRONG = 8, // The CRC_A does not match
GuillaumeMrzo 0:64f17142aa89 303 STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
GuillaumeMrzo 0:64f17142aa89 304 };
GuillaumeMrzo 0:64f17142aa89 305
GuillaumeMrzo 0:64f17142aa89 306 // A struct used for passing the UID of a PICC.
GuillaumeMrzo 0:64f17142aa89 307 typedef struct {
GuillaumeMrzo 0:64f17142aa89 308 uint8_t size; // Number of bytes in the UID. 4, 7 or 10.
GuillaumeMrzo 0:64f17142aa89 309 uint8_t uidByte[10];
GuillaumeMrzo 0:64f17142aa89 310 uint8_t sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
GuillaumeMrzo 0:64f17142aa89 311 } Uid;
GuillaumeMrzo 0:64f17142aa89 312
GuillaumeMrzo 0:64f17142aa89 313 // A struct used for passing a MIFARE Crypto1 key
GuillaumeMrzo 0:64f17142aa89 314 typedef struct {
GuillaumeMrzo 0:64f17142aa89 315 uint8_t keyByte[MF_KEY_SIZE];
GuillaumeMrzo 0:64f17142aa89 316 } MIFARE_Key;
GuillaumeMrzo 0:64f17142aa89 317
GuillaumeMrzo 0:64f17142aa89 318 // Member variables
GuillaumeMrzo 0:64f17142aa89 319 Uid uid; // Used by PICC_ReadCardSerial().
GuillaumeMrzo 0:64f17142aa89 320
GuillaumeMrzo 0:64f17142aa89 321 // Size of the MFRC522 FIFO
GuillaumeMrzo 0:64f17142aa89 322 static const uint8_t FIFO_SIZE = 64; // The FIFO is 64 bytes.
GuillaumeMrzo 0:64f17142aa89 323
GuillaumeMrzo 0:64f17142aa89 324 /**
GuillaumeMrzo 0:64f17142aa89 325 * MFRC522 constructor
GuillaumeMrzo 0:64f17142aa89 326 *
GuillaumeMrzo 0:64f17142aa89 327 * @param mosi SPI MOSI pin
GuillaumeMrzo 0:64f17142aa89 328 * @param miso SPI MISO pin
GuillaumeMrzo 0:64f17142aa89 329 * @param sclk SPI SCLK pin
GuillaumeMrzo 0:64f17142aa89 330 * @param cs SPI CS pin
GuillaumeMrzo 0:64f17142aa89 331 * @param reset Reset pin
GuillaumeMrzo 0:64f17142aa89 332 */
GuillaumeMrzo 0:64f17142aa89 333 MFRC522(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset);
GuillaumeMrzo 0:64f17142aa89 334
GuillaumeMrzo 0:64f17142aa89 335 /**
GuillaumeMrzo 0:64f17142aa89 336 * MFRC522 destructor
GuillaumeMrzo 0:64f17142aa89 337 */
GuillaumeMrzo 0:64f17142aa89 338 ~MFRC522();
GuillaumeMrzo 0:64f17142aa89 339
GuillaumeMrzo 0:64f17142aa89 340
GuillaumeMrzo 0:64f17142aa89 341 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 342 //! @name Functions for manipulating the MFRC522
GuillaumeMrzo 0:64f17142aa89 343 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 344 //@{
GuillaumeMrzo 0:64f17142aa89 345
GuillaumeMrzo 0:64f17142aa89 346 /**
GuillaumeMrzo 0:64f17142aa89 347 * Initializes the MFRC522 chip.
GuillaumeMrzo 0:64f17142aa89 348 */
GuillaumeMrzo 0:64f17142aa89 349 void PCD_Init (void);
GuillaumeMrzo 0:64f17142aa89 350
GuillaumeMrzo 0:64f17142aa89 351 /**
GuillaumeMrzo 0:64f17142aa89 352 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
GuillaumeMrzo 0:64f17142aa89 353 */
GuillaumeMrzo 0:64f17142aa89 354 void PCD_Reset (void);
GuillaumeMrzo 0:64f17142aa89 355
GuillaumeMrzo 0:64f17142aa89 356 /**
GuillaumeMrzo 0:64f17142aa89 357 * Turns the antenna on by enabling pins TX1 and TX2.
GuillaumeMrzo 0:64f17142aa89 358 * After a reset these pins disabled.
GuillaumeMrzo 0:64f17142aa89 359 */
GuillaumeMrzo 0:64f17142aa89 360 void PCD_AntennaOn (void);
GuillaumeMrzo 0:64f17142aa89 361
GuillaumeMrzo 0:64f17142aa89 362 /**
GuillaumeMrzo 0:64f17142aa89 363 * Writes a byte to the specified register in the MFRC522 chip.
GuillaumeMrzo 0:64f17142aa89 364 * The interface is described in the datasheet section 8.1.2.
GuillaumeMrzo 0:64f17142aa89 365 *
GuillaumeMrzo 0:64f17142aa89 366 * @param reg The register to write to. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 367 * @param value The value to write.
GuillaumeMrzo 0:64f17142aa89 368 */
GuillaumeMrzo 0:64f17142aa89 369 void PCD_WriteRegister (uint8_t reg, uint8_t value);
GuillaumeMrzo 0:64f17142aa89 370
GuillaumeMrzo 0:64f17142aa89 371 /**
GuillaumeMrzo 0:64f17142aa89 372 * Writes a number of bytes to the specified register in the MFRC522 chip.
GuillaumeMrzo 0:64f17142aa89 373 * The interface is described in the datasheet section 8.1.2.
GuillaumeMrzo 0:64f17142aa89 374 *
GuillaumeMrzo 0:64f17142aa89 375 * @param reg The register to write to. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 376 * @param count The number of bytes to write to the register
GuillaumeMrzo 0:64f17142aa89 377 * @param values The values to write. Byte array.
GuillaumeMrzo 0:64f17142aa89 378 */
GuillaumeMrzo 0:64f17142aa89 379 void PCD_WriteRegister (uint8_t reg, uint8_t count, uint8_t *values);
GuillaumeMrzo 0:64f17142aa89 380
GuillaumeMrzo 0:64f17142aa89 381 /**
GuillaumeMrzo 0:64f17142aa89 382 * Reads a byte from the specified register in the MFRC522 chip.
GuillaumeMrzo 0:64f17142aa89 383 * The interface is described in the datasheet section 8.1.2.
GuillaumeMrzo 0:64f17142aa89 384 *
GuillaumeMrzo 0:64f17142aa89 385 * @param reg The register to read from. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 386 * @returns Register value
GuillaumeMrzo 0:64f17142aa89 387 */
GuillaumeMrzo 0:64f17142aa89 388 uint8_t PCD_ReadRegister (uint8_t reg);
GuillaumeMrzo 0:64f17142aa89 389
GuillaumeMrzo 0:64f17142aa89 390 /**
GuillaumeMrzo 0:64f17142aa89 391 * Reads a number of bytes from the specified register in the MFRC522 chip.
GuillaumeMrzo 0:64f17142aa89 392 * The interface is described in the datasheet section 8.1.2.
GuillaumeMrzo 0:64f17142aa89 393 *
GuillaumeMrzo 0:64f17142aa89 394 * @param reg The register to read from. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 395 * @param count The number of bytes to read.
GuillaumeMrzo 0:64f17142aa89 396 * @param values Byte array to store the values in.
GuillaumeMrzo 0:64f17142aa89 397 * @param rxAlign Only bit positions rxAlign..7 in values[0] are updated.
GuillaumeMrzo 0:64f17142aa89 398 */
GuillaumeMrzo 0:64f17142aa89 399 void PCD_ReadRegister (uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign = 0);
GuillaumeMrzo 0:64f17142aa89 400
GuillaumeMrzo 0:64f17142aa89 401 /**
GuillaumeMrzo 0:64f17142aa89 402 * Sets the bits given in mask in register reg.
GuillaumeMrzo 0:64f17142aa89 403 *
GuillaumeMrzo 0:64f17142aa89 404 * @param reg The register to update. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 405 * @param mask The bits to set.
GuillaumeMrzo 0:64f17142aa89 406 */
GuillaumeMrzo 0:64f17142aa89 407 void PCD_SetRegisterBits(uint8_t reg, uint8_t mask);
GuillaumeMrzo 0:64f17142aa89 408
GuillaumeMrzo 0:64f17142aa89 409 /**
GuillaumeMrzo 0:64f17142aa89 410 * Clears the bits given in mask from register reg.
GuillaumeMrzo 0:64f17142aa89 411 *
GuillaumeMrzo 0:64f17142aa89 412 * @param reg The register to update. One of the PCD_Register enums.
GuillaumeMrzo 0:64f17142aa89 413 * @param mask The bits to clear.
GuillaumeMrzo 0:64f17142aa89 414 */
GuillaumeMrzo 0:64f17142aa89 415 void PCD_ClrRegisterBits(uint8_t reg, uint8_t mask);
GuillaumeMrzo 0:64f17142aa89 416
GuillaumeMrzo 0:64f17142aa89 417 /**
GuillaumeMrzo 0:64f17142aa89 418 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
GuillaumeMrzo 0:64f17142aa89 419 *
GuillaumeMrzo 0:64f17142aa89 420 * @param data Pointer to the data to transfer to the FIFO for CRC calculation.
GuillaumeMrzo 0:64f17142aa89 421 * @param length The number of bytes to transfer.
GuillaumeMrzo 0:64f17142aa89 422 * @param result Pointer to result buffer. Result is written to result[0..1], low byte first.
GuillaumeMrzo 0:64f17142aa89 423 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 424 */
GuillaumeMrzo 0:64f17142aa89 425 uint8_t PCD_CalculateCRC (uint8_t *data, uint8_t length, uint8_t *result);
GuillaumeMrzo 0:64f17142aa89 426
GuillaumeMrzo 0:64f17142aa89 427 /**
GuillaumeMrzo 0:64f17142aa89 428 * Executes the Transceive command.
GuillaumeMrzo 0:64f17142aa89 429 * CRC validation can only be done if backData and backLen are specified.
GuillaumeMrzo 0:64f17142aa89 430 *
GuillaumeMrzo 0:64f17142aa89 431 * @param sendData Pointer to the data to transfer to the FIFO.
GuillaumeMrzo 0:64f17142aa89 432 * @param sendLen Number of bytes to transfer to the FIFO.
GuillaumeMrzo 0:64f17142aa89 433 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
GuillaumeMrzo 0:64f17142aa89 434 * @param backLen Max number of bytes to write to *backData. Out: The number of bytes returned.
GuillaumeMrzo 0:64f17142aa89 435 * @param validBits The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
GuillaumeMrzo 0:64f17142aa89 436 * @param rxAlign Defines the bit position in backData[0] for the first bit received. Default 0.
GuillaumeMrzo 0:64f17142aa89 437 * @param checkCRC True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
GuillaumeMrzo 0:64f17142aa89 438 *
GuillaumeMrzo 0:64f17142aa89 439 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 440 */
GuillaumeMrzo 0:64f17142aa89 441 uint8_t PCD_TransceiveData (uint8_t *sendData,
GuillaumeMrzo 0:64f17142aa89 442 uint8_t sendLen,
GuillaumeMrzo 0:64f17142aa89 443 uint8_t *backData,
GuillaumeMrzo 0:64f17142aa89 444 uint8_t *backLen,
GuillaumeMrzo 0:64f17142aa89 445 uint8_t *validBits = NULL,
GuillaumeMrzo 0:64f17142aa89 446 uint8_t rxAlign = 0,
GuillaumeMrzo 0:64f17142aa89 447 bool checkCRC = false);
GuillaumeMrzo 0:64f17142aa89 448
GuillaumeMrzo 0:64f17142aa89 449
GuillaumeMrzo 0:64f17142aa89 450 /**
GuillaumeMrzo 0:64f17142aa89 451 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
GuillaumeMrzo 0:64f17142aa89 452 * CRC validation can only be done if backData and backLen are specified.
GuillaumeMrzo 0:64f17142aa89 453 *
GuillaumeMrzo 0:64f17142aa89 454 * @param command The command to execute. One of the PCD_Command enums.
GuillaumeMrzo 0:64f17142aa89 455 * @param waitIRq The bits in the ComIrqReg register that signals successful completion of the command.
GuillaumeMrzo 0:64f17142aa89 456 * @param sendData Pointer to the data to transfer to the FIFO.
GuillaumeMrzo 0:64f17142aa89 457 * @param sendLen Number of bytes to transfer to the FIFO.
GuillaumeMrzo 0:64f17142aa89 458 * @param backData NULL or pointer to buffer if data should be read back after executing the command.
GuillaumeMrzo 0:64f17142aa89 459 * @param backLen In: Max number of bytes to write to *backData. Out: The number of bytes returned.
GuillaumeMrzo 0:64f17142aa89 460 * @param validBits In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
GuillaumeMrzo 0:64f17142aa89 461 * @param rxAlign In: Defines the bit position in backData[0] for the first bit received. Default 0.
GuillaumeMrzo 0:64f17142aa89 462 * @param checkCRC In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
GuillaumeMrzo 0:64f17142aa89 463 *
GuillaumeMrzo 0:64f17142aa89 464 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 465 */
GuillaumeMrzo 0:64f17142aa89 466 uint8_t PCD_CommunicateWithPICC(uint8_t command,
GuillaumeMrzo 0:64f17142aa89 467 uint8_t waitIRq,
GuillaumeMrzo 0:64f17142aa89 468 uint8_t *sendData,
GuillaumeMrzo 0:64f17142aa89 469 uint8_t sendLen,
GuillaumeMrzo 0:64f17142aa89 470 uint8_t *backData = NULL,
GuillaumeMrzo 0:64f17142aa89 471 uint8_t *backLen = NULL,
GuillaumeMrzo 0:64f17142aa89 472 uint8_t *validBits = NULL,
GuillaumeMrzo 0:64f17142aa89 473 uint8_t rxAlign = 0,
GuillaumeMrzo 0:64f17142aa89 474 bool checkCRC = false);
GuillaumeMrzo 0:64f17142aa89 475
GuillaumeMrzo 0:64f17142aa89 476 /**
GuillaumeMrzo 0:64f17142aa89 477 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
GuillaumeMrzo 0:64f17142aa89 478 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
GuillaumeMrzo 0:64f17142aa89 479 *
GuillaumeMrzo 0:64f17142aa89 480 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
GuillaumeMrzo 0:64f17142aa89 481 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
GuillaumeMrzo 0:64f17142aa89 482 *
GuillaumeMrzo 0:64f17142aa89 483 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 484 */
GuillaumeMrzo 0:64f17142aa89 485 uint8_t PICC_RequestA (uint8_t *bufferATQA, uint8_t *bufferSize);
GuillaumeMrzo 0:64f17142aa89 486
GuillaumeMrzo 0:64f17142aa89 487 /**
GuillaumeMrzo 0:64f17142aa89 488 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
GuillaumeMrzo 0:64f17142aa89 489 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
GuillaumeMrzo 0:64f17142aa89 490 *
GuillaumeMrzo 0:64f17142aa89 491 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
GuillaumeMrzo 0:64f17142aa89 492 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
GuillaumeMrzo 0:64f17142aa89 493 *
GuillaumeMrzo 0:64f17142aa89 494 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 495 */
GuillaumeMrzo 0:64f17142aa89 496 uint8_t PICC_WakeupA (uint8_t *bufferATQA, uint8_t *bufferSize);
GuillaumeMrzo 0:64f17142aa89 497
GuillaumeMrzo 0:64f17142aa89 498 /**
GuillaumeMrzo 0:64f17142aa89 499 * Transmits REQA or WUPA commands.
GuillaumeMrzo 0:64f17142aa89 500 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
GuillaumeMrzo 0:64f17142aa89 501 *
GuillaumeMrzo 0:64f17142aa89 502 * @param command The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
GuillaumeMrzo 0:64f17142aa89 503 * @param bufferATQA The buffer to store the ATQA (Answer to request) in
GuillaumeMrzo 0:64f17142aa89 504 * @param bufferSize Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
GuillaumeMrzo 0:64f17142aa89 505 *
GuillaumeMrzo 0:64f17142aa89 506 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 507 */
GuillaumeMrzo 0:64f17142aa89 508 uint8_t PICC_REQA_or_WUPA (uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize);
GuillaumeMrzo 0:64f17142aa89 509
GuillaumeMrzo 0:64f17142aa89 510 /**
GuillaumeMrzo 0:64f17142aa89 511 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
GuillaumeMrzo 0:64f17142aa89 512 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
GuillaumeMrzo 0:64f17142aa89 513 * On success:
GuillaumeMrzo 0:64f17142aa89 514 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
GuillaumeMrzo 0:64f17142aa89 515 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
GuillaumeMrzo 0:64f17142aa89 516 *
GuillaumeMrzo 0:64f17142aa89 517 * A PICC UID consists of 4, 7 or 10 bytes.
GuillaumeMrzo 0:64f17142aa89 518 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
GuillaumeMrzo 0:64f17142aa89 519 *
GuillaumeMrzo 0:64f17142aa89 520 * UID size Number of UID bytes Cascade levels Example of PICC
GuillaumeMrzo 0:64f17142aa89 521 * ======== =================== ============== ===============
GuillaumeMrzo 0:64f17142aa89 522 * single 4 1 MIFARE Classic
GuillaumeMrzo 0:64f17142aa89 523 * double 7 2 MIFARE Ultralight
GuillaumeMrzo 0:64f17142aa89 524 * triple 10 3 Not currently in use?
GuillaumeMrzo 0:64f17142aa89 525 *
GuillaumeMrzo 0:64f17142aa89 526 *
GuillaumeMrzo 0:64f17142aa89 527 * @param uid Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
GuillaumeMrzo 0:64f17142aa89 528 * @param validBits The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
GuillaumeMrzo 0:64f17142aa89 529 *
GuillaumeMrzo 0:64f17142aa89 530 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 531 */
GuillaumeMrzo 0:64f17142aa89 532 uint8_t PICC_Select (Uid *uid, uint8_t validBits = 0);
GuillaumeMrzo 0:64f17142aa89 533
GuillaumeMrzo 0:64f17142aa89 534 /**
GuillaumeMrzo 0:64f17142aa89 535 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
GuillaumeMrzo 0:64f17142aa89 536 *
GuillaumeMrzo 0:64f17142aa89 537 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 538 */
GuillaumeMrzo 0:64f17142aa89 539 uint8_t PICC_HaltA (void);
GuillaumeMrzo 0:64f17142aa89 540
GuillaumeMrzo 0:64f17142aa89 541 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 542 //@}
GuillaumeMrzo 0:64f17142aa89 543
GuillaumeMrzo 0:64f17142aa89 544
GuillaumeMrzo 0:64f17142aa89 545 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 546 //! @name Functions for communicating with MIFARE PICCs
GuillaumeMrzo 0:64f17142aa89 547 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 548 //@{
GuillaumeMrzo 0:64f17142aa89 549
GuillaumeMrzo 0:64f17142aa89 550 /**
GuillaumeMrzo 0:64f17142aa89 551 * Executes the MFRC522 MFAuthent command.
GuillaumeMrzo 0:64f17142aa89 552 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
GuillaumeMrzo 0:64f17142aa89 553 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
GuillaumeMrzo 0:64f17142aa89 554 * For use with MIFARE Classic PICCs.
GuillaumeMrzo 0:64f17142aa89 555 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
GuillaumeMrzo 0:64f17142aa89 556 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
GuillaumeMrzo 0:64f17142aa89 557 *
GuillaumeMrzo 0:64f17142aa89 558 * All keys are set to FFFFFFFFFFFFh at chip delivery.
GuillaumeMrzo 0:64f17142aa89 559 *
GuillaumeMrzo 0:64f17142aa89 560 * @param command PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
GuillaumeMrzo 0:64f17142aa89 561 * @param blockAddr The block number. See numbering in the comments in the .h file.
GuillaumeMrzo 0:64f17142aa89 562 * @param key Pointer to the Crypteo1 key to use (6 bytes)
GuillaumeMrzo 0:64f17142aa89 563 * @param uid Pointer to Uid struct. The first 4 bytes of the UID is used.
GuillaumeMrzo 0:64f17142aa89 564 *
GuillaumeMrzo 0:64f17142aa89 565 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
GuillaumeMrzo 0:64f17142aa89 566 */
GuillaumeMrzo 0:64f17142aa89 567 uint8_t PCD_Authenticate (uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid);
GuillaumeMrzo 0:64f17142aa89 568
GuillaumeMrzo 0:64f17142aa89 569 /**
GuillaumeMrzo 0:64f17142aa89 570 * Used to exit the PCD from its authenticated state.
GuillaumeMrzo 0:64f17142aa89 571 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
GuillaumeMrzo 0:64f17142aa89 572 */
GuillaumeMrzo 0:64f17142aa89 573 void PCD_StopCrypto1 (void);
GuillaumeMrzo 0:64f17142aa89 574
GuillaumeMrzo 0:64f17142aa89 575 /**
GuillaumeMrzo 0:64f17142aa89 576 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
GuillaumeMrzo 0:64f17142aa89 577 *
GuillaumeMrzo 0:64f17142aa89 578 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 579 *
GuillaumeMrzo 0:64f17142aa89 580 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
GuillaumeMrzo 0:64f17142aa89 581 * The MF0ICU1 returns a NAK for higher addresses.
GuillaumeMrzo 0:64f17142aa89 582 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
GuillaumeMrzo 0:64f17142aa89 583 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
GuillaumeMrzo 0:64f17142aa89 584 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
GuillaumeMrzo 0:64f17142aa89 585 *
GuillaumeMrzo 0:64f17142aa89 586 * The buffer must be at least 18 bytes because a CRC_A is also returned.
GuillaumeMrzo 0:64f17142aa89 587 * Checks the CRC_A before returning STATUS_OK.
GuillaumeMrzo 0:64f17142aa89 588 *
GuillaumeMrzo 0:64f17142aa89 589 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
GuillaumeMrzo 0:64f17142aa89 590 * @param buffer The buffer to store the data in
GuillaumeMrzo 0:64f17142aa89 591 * @param bufferSize Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
GuillaumeMrzo 0:64f17142aa89 592 *
GuillaumeMrzo 0:64f17142aa89 593 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 594 */
GuillaumeMrzo 0:64f17142aa89 595 uint8_t MIFARE_Read (uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize);
GuillaumeMrzo 0:64f17142aa89 596
GuillaumeMrzo 0:64f17142aa89 597 /**
GuillaumeMrzo 0:64f17142aa89 598 * Writes 16 bytes to the active PICC.
GuillaumeMrzo 0:64f17142aa89 599 *
GuillaumeMrzo 0:64f17142aa89 600 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 601 *
GuillaumeMrzo 0:64f17142aa89 602 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
GuillaumeMrzo 0:64f17142aa89 603 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
GuillaumeMrzo 0:64f17142aa89 604 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
GuillaumeMrzo 0:64f17142aa89 605 *
GuillaumeMrzo 0:64f17142aa89 606 * @param blockAddr MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
GuillaumeMrzo 0:64f17142aa89 607 * @param buffer The 16 bytes to write to the PICC
GuillaumeMrzo 0:64f17142aa89 608 * @param bufferSize Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
GuillaumeMrzo 0:64f17142aa89 609 *
GuillaumeMrzo 0:64f17142aa89 610 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 611 */
GuillaumeMrzo 0:64f17142aa89 612 uint8_t MIFARE_Write (uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize);
GuillaumeMrzo 0:64f17142aa89 613
GuillaumeMrzo 0:64f17142aa89 614 /**
GuillaumeMrzo 0:64f17142aa89 615 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
GuillaumeMrzo 0:64f17142aa89 616 *
GuillaumeMrzo 0:64f17142aa89 617 * @param page The page (2-15) to write to.
GuillaumeMrzo 0:64f17142aa89 618 * @param buffer The 4 bytes to write to the PICC
GuillaumeMrzo 0:64f17142aa89 619 * @param bufferSize Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
GuillaumeMrzo 0:64f17142aa89 620 *
GuillaumeMrzo 0:64f17142aa89 621 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 622 */
GuillaumeMrzo 0:64f17142aa89 623 uint8_t MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize);
GuillaumeMrzo 0:64f17142aa89 624
GuillaumeMrzo 0:64f17142aa89 625 /**
GuillaumeMrzo 0:64f17142aa89 626 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
GuillaumeMrzo 0:64f17142aa89 627 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 628 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
GuillaumeMrzo 0:64f17142aa89 629 * Use MIFARE_Transfer() to store the result in a block.
GuillaumeMrzo 0:64f17142aa89 630 *
GuillaumeMrzo 0:64f17142aa89 631 * @param blockAddr The block (0-0xff) number.
GuillaumeMrzo 0:64f17142aa89 632 * @param delta This number is subtracted from the value of block blockAddr.
GuillaumeMrzo 0:64f17142aa89 633 *
GuillaumeMrzo 0:64f17142aa89 634 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 635 */
GuillaumeMrzo 0:64f17142aa89 636 uint8_t MIFARE_Decrement (uint8_t blockAddr, uint32_t delta);
GuillaumeMrzo 0:64f17142aa89 637
GuillaumeMrzo 0:64f17142aa89 638 /**
GuillaumeMrzo 0:64f17142aa89 639 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
GuillaumeMrzo 0:64f17142aa89 640 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 641 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
GuillaumeMrzo 0:64f17142aa89 642 * Use MIFARE_Transfer() to store the result in a block.
GuillaumeMrzo 0:64f17142aa89 643 *
GuillaumeMrzo 0:64f17142aa89 644 * @param blockAddr The block (0-0xff) number.
GuillaumeMrzo 0:64f17142aa89 645 * @param delta This number is added to the value of block blockAddr.
GuillaumeMrzo 0:64f17142aa89 646 *
GuillaumeMrzo 0:64f17142aa89 647 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 648 */
GuillaumeMrzo 0:64f17142aa89 649 uint8_t MIFARE_Increment (uint8_t blockAddr, uint32_t delta);
GuillaumeMrzo 0:64f17142aa89 650
GuillaumeMrzo 0:64f17142aa89 651 /**
GuillaumeMrzo 0:64f17142aa89 652 * MIFARE Restore copies the value of the addressed block into a volatile memory.
GuillaumeMrzo 0:64f17142aa89 653 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 654 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
GuillaumeMrzo 0:64f17142aa89 655 * Use MIFARE_Transfer() to store the result in a block.
GuillaumeMrzo 0:64f17142aa89 656 *
GuillaumeMrzo 0:64f17142aa89 657 * @param blockAddr The block (0-0xff) number.
GuillaumeMrzo 0:64f17142aa89 658 *
GuillaumeMrzo 0:64f17142aa89 659 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 660 */
GuillaumeMrzo 0:64f17142aa89 661 uint8_t MIFARE_Restore (uint8_t blockAddr);
GuillaumeMrzo 0:64f17142aa89 662
GuillaumeMrzo 0:64f17142aa89 663 /**
GuillaumeMrzo 0:64f17142aa89 664 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
GuillaumeMrzo 0:64f17142aa89 665 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
GuillaumeMrzo 0:64f17142aa89 666 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
GuillaumeMrzo 0:64f17142aa89 667 *
GuillaumeMrzo 0:64f17142aa89 668 * @param blockAddr The block (0-0xff) number.
GuillaumeMrzo 0:64f17142aa89 669 *
GuillaumeMrzo 0:64f17142aa89 670 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 671 */
GuillaumeMrzo 0:64f17142aa89 672 uint8_t MIFARE_Transfer (uint8_t blockAddr);
GuillaumeMrzo 0:64f17142aa89 673
GuillaumeMrzo 0:64f17142aa89 674 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 675 //@}
GuillaumeMrzo 0:64f17142aa89 676
GuillaumeMrzo 0:64f17142aa89 677
GuillaumeMrzo 0:64f17142aa89 678 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 679 //! @name Support functions
GuillaumeMrzo 0:64f17142aa89 680 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 681 //@{
GuillaumeMrzo 0:64f17142aa89 682
GuillaumeMrzo 0:64f17142aa89 683 /**
GuillaumeMrzo 0:64f17142aa89 684 * Wrapper for MIFARE protocol communication.
GuillaumeMrzo 0:64f17142aa89 685 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
GuillaumeMrzo 0:64f17142aa89 686 *
GuillaumeMrzo 0:64f17142aa89 687 * @param sendData Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
GuillaumeMrzo 0:64f17142aa89 688 * @param sendLen Number of bytes in sendData.
GuillaumeMrzo 0:64f17142aa89 689 * @param acceptTimeout True => A timeout is also success
GuillaumeMrzo 0:64f17142aa89 690 *
GuillaumeMrzo 0:64f17142aa89 691 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 692 */
GuillaumeMrzo 0:64f17142aa89 693 uint8_t PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout = false);
GuillaumeMrzo 0:64f17142aa89 694
GuillaumeMrzo 0:64f17142aa89 695 /**
GuillaumeMrzo 0:64f17142aa89 696 * Translates the SAK (Select Acknowledge) to a PICC type.
GuillaumeMrzo 0:64f17142aa89 697 *
GuillaumeMrzo 0:64f17142aa89 698 * @param sak The SAK byte returned from PICC_Select().
GuillaumeMrzo 0:64f17142aa89 699 *
GuillaumeMrzo 0:64f17142aa89 700 * @return PICC_Type
GuillaumeMrzo 0:64f17142aa89 701 */
GuillaumeMrzo 0:64f17142aa89 702 uint8_t PICC_GetType (uint8_t sak);
GuillaumeMrzo 0:64f17142aa89 703
GuillaumeMrzo 0:64f17142aa89 704 /**
GuillaumeMrzo 0:64f17142aa89 705 * Returns a string pointer to the PICC type name.
GuillaumeMrzo 0:64f17142aa89 706 *
GuillaumeMrzo 0:64f17142aa89 707 * @param type One of the PICC_Type enums.
GuillaumeMrzo 0:64f17142aa89 708 *
GuillaumeMrzo 0:64f17142aa89 709 * @return A string pointer to the PICC type name.
GuillaumeMrzo 0:64f17142aa89 710 */
GuillaumeMrzo 0:64f17142aa89 711 char* PICC_GetTypeName (uint8_t type);
GuillaumeMrzo 0:64f17142aa89 712
GuillaumeMrzo 0:64f17142aa89 713 /**
GuillaumeMrzo 0:64f17142aa89 714 * Returns a string pointer to a status code name.
GuillaumeMrzo 0:64f17142aa89 715 *
GuillaumeMrzo 0:64f17142aa89 716 * @param code One of the StatusCode enums.
GuillaumeMrzo 0:64f17142aa89 717 *
GuillaumeMrzo 0:64f17142aa89 718 * @return A string pointer to a status code name.
GuillaumeMrzo 0:64f17142aa89 719 */
GuillaumeMrzo 0:64f17142aa89 720 char* GetStatusCodeName (uint8_t code);
GuillaumeMrzo 0:64f17142aa89 721
GuillaumeMrzo 0:64f17142aa89 722 /**
GuillaumeMrzo 0:64f17142aa89 723 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
GuillaumeMrzo 0:64f17142aa89 724 *
GuillaumeMrzo 0:64f17142aa89 725 * @param accessBitBuffer Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
GuillaumeMrzo 0:64f17142aa89 726 * @param g0 Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
GuillaumeMrzo 0:64f17142aa89 727 * @param g1 Access bits [C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
GuillaumeMrzo 0:64f17142aa89 728 * @param g2 Access bits [C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
GuillaumeMrzo 0:64f17142aa89 729 * @param g3 Access bits [C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
GuillaumeMrzo 0:64f17142aa89 730 */
GuillaumeMrzo 0:64f17142aa89 731 void MIFARE_SetAccessBits (uint8_t *accessBitBuffer,
GuillaumeMrzo 0:64f17142aa89 732 uint8_t g0,
GuillaumeMrzo 0:64f17142aa89 733 uint8_t g1,
GuillaumeMrzo 0:64f17142aa89 734 uint8_t g2,
GuillaumeMrzo 0:64f17142aa89 735 uint8_t g3);
GuillaumeMrzo 0:64f17142aa89 736
GuillaumeMrzo 0:64f17142aa89 737 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 738 //@}
GuillaumeMrzo 0:64f17142aa89 739
GuillaumeMrzo 0:64f17142aa89 740
GuillaumeMrzo 0:64f17142aa89 741 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 742 //! @name Convenience functions - does not add extra functionality
GuillaumeMrzo 0:64f17142aa89 743 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 744 //@{
GuillaumeMrzo 0:64f17142aa89 745
GuillaumeMrzo 0:64f17142aa89 746 /**
GuillaumeMrzo 0:64f17142aa89 747 * Returns true if a PICC responds to PICC_CMD_REQA.
GuillaumeMrzo 0:64f17142aa89 748 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
GuillaumeMrzo 0:64f17142aa89 749 *
GuillaumeMrzo 0:64f17142aa89 750 * @return bool
GuillaumeMrzo 0:64f17142aa89 751 */
GuillaumeMrzo 0:64f17142aa89 752 bool PICC_IsNewCardPresent(void);
GuillaumeMrzo 0:64f17142aa89 753
GuillaumeMrzo 0:64f17142aa89 754 /**
GuillaumeMrzo 0:64f17142aa89 755 * Simple wrapper around PICC_Select.
GuillaumeMrzo 0:64f17142aa89 756 * Returns true if a UID could be read.
GuillaumeMrzo 0:64f17142aa89 757 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
GuillaumeMrzo 0:64f17142aa89 758 * The read UID is available in the class variable uid.
GuillaumeMrzo 0:64f17142aa89 759 *
GuillaumeMrzo 0:64f17142aa89 760 * @return bool
GuillaumeMrzo 0:64f17142aa89 761 */
GuillaumeMrzo 0:64f17142aa89 762 bool PICC_ReadCardSerial (void);
GuillaumeMrzo 0:64f17142aa89 763
GuillaumeMrzo 0:64f17142aa89 764 // ************************************************************************************
GuillaumeMrzo 0:64f17142aa89 765 //@}
GuillaumeMrzo 0:64f17142aa89 766
GuillaumeMrzo 0:64f17142aa89 767
GuillaumeMrzo 0:64f17142aa89 768 private:
GuillaumeMrzo 0:64f17142aa89 769 SPI m_SPI;
GuillaumeMrzo 0:64f17142aa89 770 DigitalOut m_CS;
GuillaumeMrzo 0:64f17142aa89 771 DigitalOut m_RESET;
GuillaumeMrzo 0:64f17142aa89 772
GuillaumeMrzo 0:64f17142aa89 773 /**
GuillaumeMrzo 0:64f17142aa89 774 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
GuillaumeMrzo 0:64f17142aa89 775 *
GuillaumeMrzo 0:64f17142aa89 776 * @param command The command to use
GuillaumeMrzo 0:64f17142aa89 777 * @param blockAddr The block (0-0xff) number.
GuillaumeMrzo 0:64f17142aa89 778 * @param data The data to transfer in step 2
GuillaumeMrzo 0:64f17142aa89 779 *
GuillaumeMrzo 0:64f17142aa89 780 * @return STATUS_OK on success, STATUS_??? otherwise.
GuillaumeMrzo 0:64f17142aa89 781 */
GuillaumeMrzo 0:64f17142aa89 782 uint8_t MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data);
GuillaumeMrzo 0:64f17142aa89 783 };
GuillaumeMrzo 0:64f17142aa89 784
GuillaumeMrzo 0:64f17142aa89 785 #endif