nrf51_bitfields.h

00001 /*
00002  * Copyright (c) Nordic Semiconductor ASA
00003  * All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without modification,
00006  * are permitted provided that the following conditions are met:
00007  *
00008  *   1. Redistributions of source code must retain the above copyright notice, this
00009  *   list of conditions and the following disclaimer.
00010  *
00011  *   2. Redistributions in binary form must reproduce the above copyright notice, this
00012  *   list of conditions and the following disclaimer in the documentation and/or
00013  *   other materials provided with the distribution.
00014  *
00015  *   3. Neither the name of Nordic Semiconductor ASA nor the names of other
00016  *   contributors to this software may be used to endorse or promote products
00017  *   derived from this software without specific prior written permission.
00018  *
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00021  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00022  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00023  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00024  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00025  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00026  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00027  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00028  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00029  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00030  *
00031  */
00032 #ifndef __NRF51_BITS_H
00033 #define __NRF51_BITS_H
00034 
00035 /*lint ++flb "Enter library region */
00036 
00037 #include <core_cm0.h>
00038 
00039 /* Peripheral: AAR */
00040 /* Description: Accelerated Address Resolver. */
00041 
00042 /* Register: AAR_INTENSET */
00043 /* Description: Interrupt enable set register. */
00044 
00045 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
00046 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
00047 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
00048 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
00049 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
00050 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
00051 
00052 /* Bit 1 : Enable interrupt on RESOLVED event. */
00053 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
00054 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
00055 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
00056 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
00057 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
00058 
00059 /* Bit 0 : Enable interrupt on END event. */
00060 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
00061 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
00062 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
00063 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
00064 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
00065 
00066 /* Register: AAR_INTENCLR */
00067 /* Description: Interrupt enable clear register. */
00068 
00069 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
00070 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
00071 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
00072 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
00073 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
00074 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
00075 
00076 /* Bit 1 : Disable interrupt on RESOLVED event. */
00077 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
00078 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
00079 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
00080 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
00081 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
00082 
00083 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
00084 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
00085 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
00086 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
00087 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
00088 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
00089 
00090 /* Register: AAR_STATUS */
00091 /* Description: Resolution status. */
00092 
00093 /* Bits 3..0 : The IRK used last time an address was resolved. */
00094 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
00095 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
00096 
00097 /* Register: AAR_ENABLE */
00098 /* Description: Enable AAR. */
00099 
00100 /* Bits 1..0 : Enable AAR. */
00101 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
00102 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
00103 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
00104 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
00105 
00106 /* Register: AAR_NIRK */
00107 /* Description: Number of Identity root Keys in the IRK data structure. */
00108 
00109 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
00110 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
00111 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
00112 
00113 /* Register: AAR_POWER */
00114 /* Description: Peripheral power control. */
00115 
00116 /* Bit 0 : Peripheral power control. */
00117 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
00118 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
00119 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
00120 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
00121 
00122 
00123 /* Peripheral: ADC */
00124 /* Description: Analog to digital converter. */
00125 
00126 /* Register: ADC_INTENSET */
00127 /* Description: Interrupt enable set register. */
00128 
00129 /* Bit 0 : Enable interrupt on END event. */
00130 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
00131 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
00132 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
00133 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
00134 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
00135 
00136 /* Register: ADC_INTENCLR */
00137 /* Description: Interrupt enable clear register. */
00138 
00139 /* Bit 0 : Disable interrupt on END event. */
00140 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
00141 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
00142 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
00143 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
00144 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
00145 
00146 /* Register: ADC_BUSY */
00147 /* Description: ADC busy register. */
00148 
00149 /* Bit 0 : ADC busy register. */
00150 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
00151 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
00152 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
00153 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
00154 
00155 /* Register: ADC_ENABLE */
00156 /* Description: ADC enable. */
00157 
00158 /* Bits 1..0 : ADC enable. */
00159 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
00160 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
00161 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
00162 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
00163 
00164 /* Register: ADC_CONFIG */
00165 /* Description: ADC configuration register. */
00166 
00167 /* Bits 17..16 : ADC external reference pin selection. */
00168 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
00169 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
00170 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
00171 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
00172 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
00173 
00174 /* Bits 15..8 : ADC analog pin selection. */
00175 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
00176 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
00177 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
00178 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
00179 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
00180 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
00181 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
00182 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
00183 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
00184 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
00185 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
00186 
00187 /* Bits 6..5 : ADC reference selection. */
00188 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
00189 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
00190 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
00191 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
00192 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
00193 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
00194 
00195 /* Bits 4..2 : ADC input selection. */
00196 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
00197 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
00198 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
00199 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
00200 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
00201 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
00202 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
00203 
00204 /* Bits 1..0 : ADC resolution. */
00205 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
00206 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
00207 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
00208 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
00209 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
00210 
00211 /* Register: ADC_RESULT */
00212 /* Description: Result of ADC conversion. */
00213 
00214 /* Bits 9..0 : Result of ADC conversion. */
00215 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
00216 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
00217 
00218 /* Register: ADC_POWER */
00219 /* Description: Peripheral power control. */
00220 
00221 /* Bit 0 : Peripheral power control. */
00222 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
00223 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
00224 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
00225 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
00226 
00227 
00228 /* Peripheral: AMLI */
00229 /* Description: AHB Multi-Layer Interface. */
00230 
00231 /* Register: AMLI_RAMPRI_CPU0 */
00232 /* Description: Configurable priority configuration register for CPU0. */
00233 
00234 /* Bits 31..28 : Configuration field for RAM block 7. */
00235 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00236 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00237 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00238 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00239 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00240 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00241 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00242 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00243 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00244 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00245 
00246 /* Bits 27..24 : Configuration field for RAM block 6. */
00247 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00248 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00249 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00250 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00251 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00252 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00253 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00254 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00255 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00256 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00257 
00258 /* Bits 23..20 : Configuration field for RAM block 5. */
00259 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00260 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00261 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00262 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00263 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00264 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00265 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00266 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00267 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00268 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00269 
00270 /* Bits 19..16 : Configuration field for RAM block 4. */
00271 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00272 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00273 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00274 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00275 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00276 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00277 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00278 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00279 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00280 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00281 
00282 /* Bits 15..12 : Configuration field for RAM block 3. */
00283 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00284 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00285 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00286 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00287 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00288 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00289 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00290 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00291 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00292 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00293 
00294 /* Bits 11..8 : Configuration field for RAM block 2. */
00295 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00296 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00297 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00298 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00299 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00300 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00301 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00302 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00303 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00304 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00305 
00306 /* Bits 7..4 : Configuration field for RAM block 1. */
00307 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00308 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00309 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00310 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00311 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00312 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00313 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00314 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00315 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00316 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00317 
00318 /* Bits 3..0 : Configuration field for RAM block 0. */
00319 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00320 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00321 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00322 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00323 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00324 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00325 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00326 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00327 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00328 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00329 
00330 /* Register: AMLI_RAMPRI_SPIS1 */
00331 /* Description: Configurable priority configuration register for SPIS1. */
00332 
00333 /* Bits 31..28 : Configuration field for RAM block 7. */
00334 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00335 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00342 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00343 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00344 
00345 /* Bits 27..24 : Configuration field for RAM block 6. */
00346 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00347 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00354 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00355 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00356 
00357 /* Bits 23..20 : Configuration field for RAM block 5. */
00358 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00359 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00368 
00369 /* Bits 19..16 : Configuration field for RAM block 4. */
00370 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00371 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00380 
00381 /* Bits 15..12 : Configuration field for RAM block 3. */
00382 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00383 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00392 
00393 /* Bits 11..8 : Configuration field for RAM block 2. */
00394 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00395 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00402 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00404 
00405 /* Bits 7..4 : Configuration field for RAM block 1. */
00406 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00407 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00414 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00415 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00416 
00417 /* Bits 3..0 : Configuration field for RAM block 0. */
00418 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00419 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00426 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00427 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00428 
00429 /* Register: AMLI_RAMPRI_RADIO */
00430 /* Description: Configurable priority configuration register for RADIO. */
00431 
00432 /* Bits 31..28 : Configuration field for RAM block 7. */
00433 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00434 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00435 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00436 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00437 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00438 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00439 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00440 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00441 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00442 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00443 
00444 /* Bits 27..24 : Configuration field for RAM block 6. */
00445 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00446 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00447 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00448 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00449 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00450 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00451 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00452 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00453 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00454 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00455 
00456 /* Bits 23..20 : Configuration field for RAM block 5. */
00457 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00458 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00459 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00460 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00461 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00462 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00463 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00464 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00465 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00466 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00467 
00468 /* Bits 19..16 : Configuration field for RAM block 4. */
00469 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00470 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00471 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00472 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00473 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00474 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00475 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00476 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00477 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00478 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00479 
00480 /* Bits 15..12 : Configuration field for RAM block 3. */
00481 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00482 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00483 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00484 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00485 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00486 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00487 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00488 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00489 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00490 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00491 
00492 /* Bits 11..8 : Configuration field for RAM block 2. */
00493 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00494 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00495 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00496 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00497 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00498 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00499 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00500 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00501 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00502 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00503 
00504 /* Bits 7..4 : Configuration field for RAM block 1. */
00505 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00506 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00507 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00508 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00509 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00510 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00511 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00512 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00513 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00514 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00515 
00516 /* Bits 3..0 : Configuration field for RAM block 0. */
00517 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00518 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00519 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00520 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00521 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00522 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00523 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00524 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00525 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00526 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00527 
00528 /* Register: AMLI_RAMPRI_ECB */
00529 /* Description: Configurable priority configuration register for ECB. */
00530 
00531 /* Bits 31..28 : Configuration field for RAM block 7. */
00532 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00533 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00534 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00535 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00536 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00537 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00538 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00539 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00540 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00541 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00542 
00543 /* Bits 27..24 : Configuration field for RAM block 6. */
00544 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00545 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00546 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00547 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00548 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00549 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00550 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00551 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00552 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00553 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00554 
00555 /* Bits 23..20 : Configuration field for RAM block 5. */
00556 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00557 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00558 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00559 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00560 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00561 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00562 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00563 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00564 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00565 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00566 
00567 /* Bits 19..16 : Configuration field for RAM block 4. */
00568 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00569 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00570 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00571 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00572 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00573 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00574 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00575 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00576 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00577 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00578 
00579 /* Bits 15..12 : Configuration field for RAM block 3. */
00580 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00581 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00582 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00583 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00584 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00585 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00586 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00587 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00588 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00589 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00590 
00591 /* Bits 11..8 : Configuration field for RAM block 2. */
00592 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00593 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00594 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00595 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00596 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00597 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00598 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00599 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00600 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00601 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00602 
00603 /* Bits 7..4 : Configuration field for RAM block 1. */
00604 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00605 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00606 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00607 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00608 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00609 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00610 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00611 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00612 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00613 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00614 
00615 /* Bits 3..0 : Configuration field for RAM block 0. */
00616 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00617 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00618 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00619 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00620 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00621 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00622 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00623 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00624 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00625 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00626 
00627 /* Register: AMLI_RAMPRI_CCM */
00628 /* Description: Configurable priority configuration register for CCM. */
00629 
00630 /* Bits 31..28 : Configuration field for RAM block 7. */
00631 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00632 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00633 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00634 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00635 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00636 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00637 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00638 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00639 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00640 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00641 
00642 /* Bits 27..24 : Configuration field for RAM block 6. */
00643 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00644 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00645 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00646 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00647 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00648 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00649 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00650 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00651 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00652 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00653 
00654 /* Bits 23..20 : Configuration field for RAM block 5. */
00655 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00656 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00657 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00658 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00659 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00660 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00661 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00662 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00663 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00664 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00665 
00666 /* Bits 19..16 : Configuration field for RAM block 4. */
00667 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00668 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00669 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00670 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00671 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00672 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00673 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00674 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00675 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00676 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00677 
00678 /* Bits 15..12 : Configuration field for RAM block 3. */
00679 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00680 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00681 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00682 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00683 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00684 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00685 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00686 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00687 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00688 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00689 
00690 /* Bits 11..8 : Configuration field for RAM block 2. */
00691 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00692 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00693 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00694 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00695 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00696 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00697 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00698 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00699 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00700 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00701 
00702 /* Bits 7..4 : Configuration field for RAM block 1. */
00703 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00704 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00705 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00706 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00707 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00708 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00709 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00710 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00711 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00712 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00713 
00714 /* Bits 3..0 : Configuration field for RAM block 0. */
00715 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00716 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00717 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00718 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00719 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00720 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00721 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00722 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00723 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00724 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00725 
00726 /* Register: AMLI_RAMPRI_AAR */
00727 /* Description: Configurable priority configuration register for AAR. */
00728 
00729 /* Bits 31..28 : Configuration field for RAM block 7. */
00730 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
00731 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
00732 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
00733 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
00734 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
00735 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
00736 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
00737 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
00738 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
00739 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
00740 
00741 /* Bits 27..24 : Configuration field for RAM block 6. */
00742 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
00743 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
00744 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
00745 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
00746 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
00747 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
00748 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
00749 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
00750 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
00751 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
00752 
00753 /* Bits 23..20 : Configuration field for RAM block 5. */
00754 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
00755 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
00756 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
00757 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
00758 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
00759 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
00760 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
00761 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
00762 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
00763 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
00764 
00765 /* Bits 19..16 : Configuration field for RAM block 4. */
00766 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
00767 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
00768 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
00769 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
00770 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
00771 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
00772 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
00773 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
00774 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
00775 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
00776 
00777 /* Bits 15..12 : Configuration field for RAM block 3. */
00778 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
00779 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
00780 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
00781 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
00782 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
00783 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
00784 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
00785 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
00786 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
00787 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
00788 
00789 /* Bits 11..8 : Configuration field for RAM block 2. */
00790 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
00791 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
00792 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
00793 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
00794 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
00795 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
00796 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
00797 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
00798 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
00799 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
00800 
00801 /* Bits 7..4 : Configuration field for RAM block 1. */
00802 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
00803 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
00804 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
00805 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
00806 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
00807 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
00808 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
00809 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
00810 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
00811 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
00812 
00813 /* Bits 3..0 : Configuration field for RAM block 0. */
00814 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
00815 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
00816 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
00817 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
00818 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
00819 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
00820 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
00821 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
00822 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
00823 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
00824 
00825 /* Peripheral: CCM */
00826 /* Description: AES CCM Mode Encryption. */
00827 
00828 /* Register: CCM_SHORTS */
00829 /* Description: Shortcuts for the CCM. */
00830 
00831 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
00832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
00833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
00834 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
00835 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
00836 
00837 /* Register: CCM_INTENSET */
00838 /* Description: Interrupt enable set register. */
00839 
00840 /* Bit 2 : Enable interrupt on ERROR event. */
00841 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
00842 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
00843 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
00844 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
00845 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
00846 
00847 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
00848 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
00849 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
00850 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
00851 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
00852 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
00853 
00854 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
00855 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
00856 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
00857 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
00858 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
00859 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
00860 
00861 /* Register: CCM_INTENCLR */
00862 /* Description: Interrupt enable clear register. */
00863 
00864 /* Bit 2 : Disable interrupt on ERROR event. */
00865 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
00866 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
00867 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
00868 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
00869 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
00870 
00871 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
00872 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
00873 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
00874 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
00875 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
00876 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
00877 
00878 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
00879 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
00880 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
00881 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
00882 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
00883 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
00884 
00885 /* Register: CCM_MICSTATUS */
00886 /* Description: CCM RX MIC check result. */
00887 
00888 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
00889 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
00890 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
00891 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
00892 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
00893 
00894 /* Register: CCM_ENABLE */
00895 /* Description: CCM enable. */
00896 
00897 /* Bits 1..0 : CCM enable. */
00898 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
00899 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
00900 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
00901 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
00902 
00903 /* Register: CCM_MODE */
00904 /* Description: Operation mode. */
00905 
00906 /* Bit 0 : CCM mode operation. */
00907 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
00908 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
00909 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
00910 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
00911 
00912 /* Register: CCM_POWER */
00913 /* Description: Peripheral power control. */
00914 
00915 /* Bit 0 : Peripheral power control. */
00916 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
00917 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
00918 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
00919 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
00920 
00921 
00922 /* Peripheral: CLOCK */
00923 /* Description: Clock control. */
00924 
00925 /* Register: CLOCK_INTENSET */
00926 /* Description: Interrupt enable set register. */
00927 
00928 /* Bit 4 : Enable interrupt on CTTO event. */
00929 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
00930 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
00931 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
00932 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
00933 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
00934 
00935 /* Bit 3 : Enable interrupt on DONE event. */
00936 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
00937 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
00938 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
00939 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
00940 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
00941 
00942 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
00943 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
00944 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
00945 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
00946 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
00947 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
00948 
00949 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
00950 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
00951 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
00952 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
00953 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
00954 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
00955 
00956 /* Register: CLOCK_INTENCLR */
00957 /* Description: Interrupt enable clear register. */
00958 
00959 /* Bit 4 : Disable interrupt on CTTO event. */
00960 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
00961 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
00962 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
00963 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
00964 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
00965 
00966 /* Bit 3 : Disable interrupt on DONE event. */
00967 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
00968 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
00969 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
00970 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
00971 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
00972 
00973 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
00974 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
00975 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
00976 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
00977 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
00978 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
00979 
00980 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
00981 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
00982 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
00983 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
00984 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
00985 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
00986 
00987 /* Register: CLOCK_HFCLKRUN */
00988 /* Description: Task HFCLKSTART trigger status. */
00989 
00990 /* Bit 0 : Task HFCLKSTART trigger status. */
00991 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
00992 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
00993 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
00994 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
00995 
00996 /* Register: CLOCK_HFCLKSTAT */
00997 /* Description: High frequency clock status. */
00998 
00999 /* Bit 16 : State for the HFCLK. */
01000 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
01001 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
01002 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
01003 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
01004 
01005 /* Bit 0 : Active clock source for the HF clock. */
01006 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
01007 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
01008 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
01009 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
01010 
01011 /* Register: CLOCK_LFCLKRUN */
01012 /* Description: Task LFCLKSTART triggered status. */
01013 
01014 /* Bit 0 : Task LFCLKSTART triggered status. */
01015 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
01016 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
01017 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
01018 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
01019 
01020 /* Register: CLOCK_LFCLKSTAT */
01021 /* Description: Low frequency clock status. */
01022 
01023 /* Bit 16 : State for the LF clock. */
01024 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
01025 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
01026 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
01027 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
01028 
01029 /* Bits 1..0 : Active clock source for the LF clock. */
01030 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
01031 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
01032 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
01033 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
01034 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
01035 
01036 /* Register: CLOCK_LFCLKSRCCOPY */
01037 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
01038 
01039 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
01040 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
01041 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
01042 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
01043 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
01044 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
01045 
01046 /* Register: CLOCK_LFCLKSRC */
01047 /* Description: Clock source for the LFCLK clock. */
01048 
01049 /* Bits 1..0 : Clock source. */
01050 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
01051 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
01052 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
01053 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
01054 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
01055 
01056 /* Register: CLOCK_CTIV */
01057 /* Description: Calibration timer interval. */
01058 
01059 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
01060 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
01061 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
01062 
01063 /* Register: CLOCK_XTALFREQ */
01064 /* Description: Crystal frequency. */
01065 
01066 /* Bits 7..0 : External Xtal frequency selection. */
01067 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
01068 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
01069 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
01070 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
01071 
01072 
01073 /* Peripheral: ECB */
01074 /* Description: AES ECB Mode Encryption. */
01075 
01076 /* Register: ECB_INTENSET */
01077 /* Description: Interrupt enable set register. */
01078 
01079 /* Bit 1 : Enable interrupt on ERRORECB event. */
01080 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
01081 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
01082 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
01083 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
01084 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
01085 
01086 /* Bit 0 : Enable interrupt on ENDECB event. */
01087 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
01088 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
01089 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
01090 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
01091 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
01092 
01093 /* Register: ECB_INTENCLR */
01094 /* Description: Interrupt enable clear register. */
01095 
01096 /* Bit 1 : Disable interrupt on ERRORECB event. */
01097 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
01098 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
01099 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
01100 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
01101 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
01102 
01103 /* Bit 0 : Disable interrupt on ENDECB event. */
01104 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
01105 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
01106 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
01107 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
01108 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
01109 
01110 /* Register: ECB_POWER */
01111 /* Description: Peripheral power control. */
01112 
01113 /* Bit 0 : Peripheral power control. */
01114 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
01115 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
01116 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
01117 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
01118 
01119 
01120 /* Peripheral: FICR */
01121 /* Description: Factory Information Configuration. */
01122 
01123 /* Register: FICR_PPFC */
01124 /* Description: Pre-programmed factory code present. */
01125 
01126 /* Bits 7..0 : Pre-programmed factory code present. */
01127 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
01128 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
01129 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
01130 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
01131 
01132 /* Register: FICR_CONFIGID */
01133 /* Description: Configuration identifier. */
01134 
01135 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
01136 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
01137 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
01138 
01139 /* Bits 15..0 : Hardware Identification Number. */
01140 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
01141 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
01142 
01143 /* Register: FICR_DEVICEADDRTYPE */
01144 /* Description: Device address type. */
01145 
01146 /* Bit 0 : Device address type. */
01147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
01148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
01149 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
01150 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
01151 
01152 /* Register: FICR_OVERRIDEEN */
01153 /* Description: Radio calibration override enable. */
01154 
01155 /* Bit 3 : Override default values for BLE_1Mbit mode. */
01156 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
01157 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
01158 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
01159 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
01160 
01161 /* Bit 0 : Override default values for NRF_1Mbit mode. */
01162 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
01163 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
01164 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
01165 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
01166 
01167 /* Register: FICR_INFO_PART */
01168 /* Description: Part code */
01169 
01170 /* Bits 31..0 : Part code */
01171 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
01172 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
01173 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */
01174 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */
01175 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
01176 
01177 /* Register: FICR_INFO_VARIANT */
01178 /* Description: Part variant */
01179 
01180 /* Bits 31..0 : Part variant */
01181 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
01182 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
01183 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */
01184 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */
01185 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */
01186 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
01187 
01188 /* Register: FICR_INFO_PACKAGE */
01189 /* Description: Package option */
01190 
01191 /* Bits 31..0 : Package option */
01192 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
01193 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
01194 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */
01195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */
01196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */
01197 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */
01198 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */
01199 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
01200 
01201 /* Register: FICR_INFO_RAM */
01202 /* Description: RAM variant */
01203 
01204 /* Bits 31..0 : RAM variant */
01205 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
01206 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
01207 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
01208 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */
01209 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */
01210 
01211 /* Register: FICR_INFO_FLASH */
01212 /* Description: Flash variant */
01213 
01214 /* Bits 31..0 : Flash variant */
01215 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
01216 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
01217 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
01218 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */
01219 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */
01220 
01221 
01222 /* Peripheral: GPIO */
01223 /* Description: General purpose input and output. */
01224 
01225 /* Register: GPIO_OUT */
01226 /* Description: Write GPIO port. */
01227 
01228 /* Bit 31 : Pin 31. */
01229 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
01230 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
01231 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
01232 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
01233 
01234 /* Bit 30 : Pin 30. */
01235 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
01236 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
01237 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
01238 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
01239 
01240 /* Bit 29 : Pin 29. */
01241 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
01242 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
01243 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
01244 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
01245 
01246 /* Bit 28 : Pin 28. */
01247 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
01248 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
01249 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
01250 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
01251 
01252 /* Bit 27 : Pin 27. */
01253 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
01254 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
01255 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
01256 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
01257 
01258 /* Bit 26 : Pin 26. */
01259 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
01260 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
01261 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
01262 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
01263 
01264 /* Bit 25 : Pin 25. */
01265 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
01266 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
01267 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
01268 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
01269 
01270 /* Bit 24 : Pin 24. */
01271 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
01272 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
01273 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
01274 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
01275 
01276 /* Bit 23 : Pin 23. */
01277 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
01278 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
01279 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
01280 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
01281 
01282 /* Bit 22 : Pin 22. */
01283 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
01284 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
01285 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
01286 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
01287 
01288 /* Bit 21 : Pin 21. */
01289 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
01290 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
01291 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
01292 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
01293 
01294 /* Bit 20 : Pin 20. */
01295 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
01296 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
01297 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
01298 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
01299 
01300 /* Bit 19 : Pin 19. */
01301 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
01302 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
01303 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
01304 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
01305 
01306 /* Bit 18 : Pin 18. */
01307 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
01308 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
01309 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
01310 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
01311 
01312 /* Bit 17 : Pin 17. */
01313 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
01314 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
01315 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
01316 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
01317 
01318 /* Bit 16 : Pin 16. */
01319 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
01320 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
01321 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
01322 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
01323 
01324 /* Bit 15 : Pin 15. */
01325 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
01326 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
01327 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
01328 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
01329 
01330 /* Bit 14 : Pin 14. */
01331 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
01332 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
01333 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
01334 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
01335 
01336 /* Bit 13 : Pin 13. */
01337 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
01338 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
01339 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
01340 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
01341 
01342 /* Bit 12 : Pin 12. */
01343 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
01344 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
01345 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
01346 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
01347 
01348 /* Bit 11 : Pin 11. */
01349 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
01350 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
01351 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
01352 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
01353 
01354 /* Bit 10 : Pin 10. */
01355 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
01356 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
01357 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
01358 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
01359 
01360 /* Bit 9 : Pin 9. */
01361 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
01362 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
01363 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
01364 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
01365 
01366 /* Bit 8 : Pin 8. */
01367 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
01368 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
01369 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
01370 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
01371 
01372 /* Bit 7 : Pin 7. */
01373 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
01374 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
01375 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
01376 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
01377 
01378 /* Bit 6 : Pin 6. */
01379 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
01380 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
01381 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
01382 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
01383 
01384 /* Bit 5 : Pin 5. */
01385 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
01386 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
01387 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
01388 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
01389 
01390 /* Bit 4 : Pin 4. */
01391 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
01392 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
01393 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
01394 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
01395 
01396 /* Bit 3 : Pin 3. */
01397 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
01398 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
01399 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
01400 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
01401 
01402 /* Bit 2 : Pin 2. */
01403 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
01404 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
01405 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
01406 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
01407 
01408 /* Bit 1 : Pin 1. */
01409 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
01410 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
01411 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
01412 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
01413 
01414 /* Bit 0 : Pin 0. */
01415 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
01416 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
01417 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
01418 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
01419 
01420 /* Register: GPIO_OUTSET */
01421 /* Description: Set individual bits in GPIO port. */
01422 
01423 /* Bit 31 : Pin 31. */
01424 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
01425 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
01426 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
01427 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
01428 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
01429 
01430 /* Bit 30 : Pin 30. */
01431 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
01432 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
01433 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
01434 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
01435 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
01436 
01437 /* Bit 29 : Pin 29. */
01438 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
01439 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
01440 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
01441 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
01442 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
01443 
01444 /* Bit 28 : Pin 28. */
01445 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
01446 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
01447 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
01448 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
01449 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
01450 
01451 /* Bit 27 : Pin 27. */
01452 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
01453 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
01454 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
01455 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
01456 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
01457 
01458 /* Bit 26 : Pin 26. */
01459 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
01460 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
01461 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
01462 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
01463 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
01464 
01465 /* Bit 25 : Pin 25. */
01466 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
01467 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
01468 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
01469 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
01470 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
01471 
01472 /* Bit 24 : Pin 24. */
01473 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
01474 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
01475 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
01476 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
01477 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
01478 
01479 /* Bit 23 : Pin 23. */
01480 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
01481 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
01482 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
01483 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
01484 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
01485 
01486 /* Bit 22 : Pin 22. */
01487 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
01488 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
01489 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
01490 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
01491 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
01492 
01493 /* Bit 21 : Pin 21. */
01494 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
01495 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
01496 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
01497 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
01498 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
01499 
01500 /* Bit 20 : Pin 20. */
01501 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
01502 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
01503 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
01504 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
01505 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
01506 
01507 /* Bit 19 : Pin 19. */
01508 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
01509 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
01510 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
01511 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
01512 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
01513 
01514 /* Bit 18 : Pin 18. */
01515 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
01516 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
01517 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
01518 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
01519 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
01520 
01521 /* Bit 17 : Pin 17. */
01522 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
01523 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
01524 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
01525 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
01526 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
01527 
01528 /* Bit 16 : Pin 16. */
01529 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
01530 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
01531 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
01532 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
01533 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
01534 
01535 /* Bit 15 : Pin 15. */
01536 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
01537 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
01538 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
01539 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
01540 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
01541 
01542 /* Bit 14 : Pin 14. */
01543 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
01544 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
01545 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
01546 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
01547 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
01548 
01549 /* Bit 13 : Pin 13. */
01550 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
01551 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
01552 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
01553 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
01554 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
01555 
01556 /* Bit 12 : Pin 12. */
01557 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
01558 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
01559 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
01560 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
01561 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
01562 
01563 /* Bit 11 : Pin 11. */
01564 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
01565 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
01566 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
01567 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
01568 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
01569 
01570 /* Bit 10 : Pin 10. */
01571 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
01572 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
01573 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
01574 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
01575 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
01576 
01577 /* Bit 9 : Pin 9. */
01578 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
01579 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
01580 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
01581 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
01582 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
01583 
01584 /* Bit 8 : Pin 8. */
01585 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
01586 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
01587 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
01588 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
01589 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
01590 
01591 /* Bit 7 : Pin 7. */
01592 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
01593 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
01594 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
01595 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
01596 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
01597 
01598 /* Bit 6 : Pin 6. */
01599 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
01600 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
01601 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
01602 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
01603 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
01604 
01605 /* Bit 5 : Pin 5. */
01606 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
01607 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
01608 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
01609 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
01610 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
01611 
01612 /* Bit 4 : Pin 4. */
01613 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
01614 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
01615 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
01616 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
01617 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
01618 
01619 /* Bit 3 : Pin 3. */
01620 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
01621 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
01622 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
01623 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
01624 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
01625 
01626 /* Bit 2 : Pin 2. */
01627 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
01628 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
01629 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
01630 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
01631 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
01632 
01633 /* Bit 1 : Pin 1. */
01634 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
01635 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
01636 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
01637 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
01638 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
01639 
01640 /* Bit 0 : Pin 0. */
01641 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
01642 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
01643 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
01644 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
01645 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
01646 
01647 /* Register: GPIO_OUTCLR */
01648 /* Description: Clear individual bits in GPIO port. */
01649 
01650 /* Bit 31 : Pin 31. */
01651 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
01652 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
01653 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
01654 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
01655 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
01656 
01657 /* Bit 30 : Pin 30. */
01658 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
01659 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
01660 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
01661 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
01662 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
01663 
01664 /* Bit 29 : Pin 29. */
01665 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
01666 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
01667 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
01668 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
01669 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
01670 
01671 /* Bit 28 : Pin 28. */
01672 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
01673 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
01674 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
01675 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
01676 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
01677 
01678 /* Bit 27 : Pin 27. */
01679 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
01680 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
01681 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
01682 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
01683 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
01684 
01685 /* Bit 26 : Pin 26. */
01686 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
01687 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
01688 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
01689 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
01690 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
01691 
01692 /* Bit 25 : Pin 25. */
01693 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
01694 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
01695 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
01696 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
01697 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
01698 
01699 /* Bit 24 : Pin 24. */
01700 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
01701 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
01702 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
01703 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
01704 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
01705 
01706 /* Bit 23 : Pin 23. */
01707 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
01708 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
01709 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
01710 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
01711 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
01712 
01713 /* Bit 22 : Pin 22. */
01714 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
01715 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
01716 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
01717 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
01718 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
01719 
01720 /* Bit 21 : Pin 21. */
01721 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
01722 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
01723 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
01724 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
01725 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
01726 
01727 /* Bit 20 : Pin 20. */
01728 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
01729 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
01730 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
01731 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
01732 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
01733 
01734 /* Bit 19 : Pin 19. */
01735 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
01736 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
01737 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
01738 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
01739 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
01740 
01741 /* Bit 18 : Pin 18. */
01742 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
01743 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
01744 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
01745 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
01746 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
01747 
01748 /* Bit 17 : Pin 17. */
01749 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
01750 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
01751 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
01752 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
01753 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
01754 
01755 /* Bit 16 : Pin 16. */
01756 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
01757 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
01758 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
01759 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
01760 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
01761 
01762 /* Bit 15 : Pin 15. */
01763 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
01764 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
01765 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
01766 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
01767 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
01768 
01769 /* Bit 14 : Pin 14. */
01770 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
01771 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
01772 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
01773 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
01774 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
01775 
01776 /* Bit 13 : Pin 13. */
01777 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
01778 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
01779 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
01780 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
01781 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
01782 
01783 /* Bit 12 : Pin 12. */
01784 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
01785 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
01786 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
01787 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
01788 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
01789 
01790 /* Bit 11 : Pin 11. */
01791 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
01792 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
01793 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
01794 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
01795 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
01796 
01797 /* Bit 10 : Pin 10. */
01798 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
01799 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
01800 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
01801 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
01802 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
01803 
01804 /* Bit 9 : Pin 9. */
01805 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
01806 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
01807 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
01808 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
01809 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
01810 
01811 /* Bit 8 : Pin 8. */
01812 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
01813 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
01814 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
01815 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
01816 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
01817 
01818 /* Bit 7 : Pin 7. */
01819 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
01820 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
01821 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
01822 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
01823 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
01824 
01825 /* Bit 6 : Pin 6. */
01826 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
01827 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
01828 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
01829 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
01830 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
01831 
01832 /* Bit 5 : Pin 5. */
01833 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
01834 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
01835 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
01836 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
01837 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
01838 
01839 /* Bit 4 : Pin 4. */
01840 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
01841 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
01842 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
01843 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
01844 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
01845 
01846 /* Bit 3 : Pin 3. */
01847 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
01848 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
01849 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
01850 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
01851 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
01852 
01853 /* Bit 2 : Pin 2. */
01854 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
01855 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
01856 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
01857 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
01858 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
01859 
01860 /* Bit 1 : Pin 1. */
01861 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
01862 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
01863 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
01864 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
01865 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
01866 
01867 /* Bit 0 : Pin 0. */
01868 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
01869 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
01870 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
01871 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
01872 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
01873 
01874 /* Register: GPIO_IN */
01875 /* Description: Read GPIO port. */
01876 
01877 /* Bit 31 : Pin 31. */
01878 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
01879 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
01880 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
01881 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
01882 
01883 /* Bit 30 : Pin 30. */
01884 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
01885 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
01886 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
01887 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
01888 
01889 /* Bit 29 : Pin 29. */
01890 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
01891 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
01892 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
01893 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
01894 
01895 /* Bit 28 : Pin 28. */
01896 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
01897 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
01898 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
01899 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
01900 
01901 /* Bit 27 : Pin 27. */
01902 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
01903 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
01904 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
01905 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
01906 
01907 /* Bit 26 : Pin 26. */
01908 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
01909 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
01910 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
01911 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
01912 
01913 /* Bit 25 : Pin 25. */
01914 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
01915 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
01916 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
01917 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
01918 
01919 /* Bit 24 : Pin 24. */
01920 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
01921 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
01922 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
01923 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
01924 
01925 /* Bit 23 : Pin 23. */
01926 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
01927 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
01928 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
01929 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
01930 
01931 /* Bit 22 : Pin 22. */
01932 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
01933 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
01934 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
01935 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
01936 
01937 /* Bit 21 : Pin 21. */
01938 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
01939 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
01940 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
01941 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
01942 
01943 /* Bit 20 : Pin 20. */
01944 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
01945 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
01946 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
01947 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
01948 
01949 /* Bit 19 : Pin 19. */
01950 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
01951 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
01952 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
01953 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
01954 
01955 /* Bit 18 : Pin 18. */
01956 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
01957 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
01958 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
01959 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
01960 
01961 /* Bit 17 : Pin 17. */
01962 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
01963 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
01964 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
01965 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
01966 
01967 /* Bit 16 : Pin 16. */
01968 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
01969 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
01970 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
01971 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
01972 
01973 /* Bit 15 : Pin 15. */
01974 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
01975 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
01976 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
01977 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
01978 
01979 /* Bit 14 : Pin 14. */
01980 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
01981 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
01982 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
01983 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
01984 
01985 /* Bit 13 : Pin 13. */
01986 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
01987 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
01988 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
01989 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
01990 
01991 /* Bit 12 : Pin 12. */
01992 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
01993 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
01994 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
01995 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
01996 
01997 /* Bit 11 : Pin 11. */
01998 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
01999 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
02000 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
02001 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
02002 
02003 /* Bit 10 : Pin 10. */
02004 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
02005 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
02006 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
02007 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
02008 
02009 /* Bit 9 : Pin 9. */
02010 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
02011 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
02012 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
02013 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
02014 
02015 /* Bit 8 : Pin 8. */
02016 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
02017 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
02018 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
02019 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
02020 
02021 /* Bit 7 : Pin 7. */
02022 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
02023 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
02024 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
02025 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
02026 
02027 /* Bit 6 : Pin 6. */
02028 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
02029 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
02030 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
02031 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
02032 
02033 /* Bit 5 : Pin 5. */
02034 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
02035 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
02036 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
02037 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
02038 
02039 /* Bit 4 : Pin 4. */
02040 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
02041 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
02042 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
02043 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
02044 
02045 /* Bit 3 : Pin 3. */
02046 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
02047 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
02048 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
02049 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
02050 
02051 /* Bit 2 : Pin 2. */
02052 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
02053 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
02054 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
02055 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
02056 
02057 /* Bit 1 : Pin 1. */
02058 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
02059 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
02060 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
02061 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
02062 
02063 /* Bit 0 : Pin 0. */
02064 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
02065 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
02066 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
02067 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
02068 
02069 /* Register: GPIO_DIR */
02070 /* Description: Direction of GPIO pins. */
02071 
02072 /* Bit 31 : Pin 31. */
02073 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
02074 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
02075 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
02076 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
02077 
02078 /* Bit 30 : Pin 30. */
02079 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
02080 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
02081 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
02082 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
02083 
02084 /* Bit 29 : Pin 29. */
02085 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
02086 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
02087 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
02088 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
02089 
02090 /* Bit 28 : Pin 28. */
02091 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
02092 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
02093 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
02094 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
02095 
02096 /* Bit 27 : Pin 27. */
02097 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
02098 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
02099 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
02100 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
02101 
02102 /* Bit 26 : Pin 26. */
02103 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
02104 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
02105 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
02106 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
02107 
02108 /* Bit 25 : Pin 25. */
02109 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
02110 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
02111 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
02112 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
02113 
02114 /* Bit 24 : Pin 24. */
02115 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
02116 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
02117 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
02118 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
02119 
02120 /* Bit 23 : Pin 23. */
02121 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
02122 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
02123 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
02124 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
02125 
02126 /* Bit 22 : Pin 22. */
02127 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
02128 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
02129 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
02130 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
02131 
02132 /* Bit 21 : Pin 21. */
02133 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
02134 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
02135 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
02136 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
02137 
02138 /* Bit 20 : Pin 20. */
02139 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
02140 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
02141 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
02142 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
02143 
02144 /* Bit 19 : Pin 19. */
02145 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
02146 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
02147 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
02148 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
02149 
02150 /* Bit 18 : Pin 18. */
02151 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
02152 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
02153 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
02154 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
02155 
02156 /* Bit 17 : Pin 17. */
02157 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
02158 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
02159 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
02160 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
02161 
02162 /* Bit 16 : Pin 16. */
02163 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
02164 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
02165 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
02166 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
02167 
02168 /* Bit 15 : Pin 15. */
02169 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
02170 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
02171 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
02172 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
02173 
02174 /* Bit 14 : Pin 14. */
02175 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
02176 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
02177 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
02178 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
02179 
02180 /* Bit 13 : Pin 13. */
02181 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
02182 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
02183 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
02184 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
02185 
02186 /* Bit 12 : Pin 12. */
02187 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
02188 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
02189 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
02190 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
02191 
02192 /* Bit 11 : Pin 11. */
02193 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
02194 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
02195 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
02196 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
02197 
02198 /* Bit 10 : Pin 10. */
02199 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
02200 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
02201 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
02202 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
02203 
02204 /* Bit 9 : Pin 9. */
02205 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
02206 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
02207 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
02208 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
02209 
02210 /* Bit 8 : Pin 8. */
02211 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
02212 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
02213 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
02214 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
02215 
02216 /* Bit 7 : Pin 7. */
02217 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
02218 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
02219 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
02220 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
02221 
02222 /* Bit 6 : Pin 6. */
02223 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
02224 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
02225 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
02226 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
02227 
02228 /* Bit 5 : Pin 5. */
02229 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
02230 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
02231 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
02232 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
02233 
02234 /* Bit 4 : Pin 4. */
02235 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
02236 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
02237 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
02238 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
02239 
02240 /* Bit 3 : Pin 3. */
02241 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
02242 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
02243 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
02244 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
02245 
02246 /* Bit 2 : Pin 2. */
02247 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
02248 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
02249 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
02250 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
02251 
02252 /* Bit 1 : Pin 1. */
02253 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
02254 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
02255 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
02256 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
02257 
02258 /* Bit 0 : Pin 0. */
02259 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
02260 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
02261 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
02262 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
02263 
02264 /* Register: GPIO_DIRSET */
02265 /* Description: DIR set register. */
02266 
02267 /* Bit 31 : Set as output pin 31. */
02268 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
02269 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
02270 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
02271 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
02272 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
02273 
02274 /* Bit 30 : Set as output pin 30. */
02275 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
02276 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
02277 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
02278 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
02279 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
02280 
02281 /* Bit 29 : Set as output pin 29. */
02282 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
02283 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
02284 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
02285 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
02286 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
02287 
02288 /* Bit 28 : Set as output pin 28. */
02289 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
02290 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
02291 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
02292 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
02293 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
02294 
02295 /* Bit 27 : Set as output pin 27. */
02296 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
02297 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
02298 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
02299 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
02300 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
02301 
02302 /* Bit 26 : Set as output pin 26. */
02303 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
02304 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
02305 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
02306 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
02307 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
02308 
02309 /* Bit 25 : Set as output pin 25. */
02310 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
02311 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
02312 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
02313 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
02314 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
02315 
02316 /* Bit 24 : Set as output pin 24. */
02317 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
02318 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
02319 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
02320 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
02321 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
02322 
02323 /* Bit 23 : Set as output pin 23. */
02324 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
02325 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
02326 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
02327 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
02328 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
02329 
02330 /* Bit 22 : Set as output pin 22. */
02331 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
02332 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
02333 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
02334 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
02335 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
02336 
02337 /* Bit 21 : Set as output pin 21. */
02338 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
02339 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
02340 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
02341 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
02342 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
02343 
02344 /* Bit 20 : Set as output pin 20. */
02345 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
02346 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
02347 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
02348 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
02349 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
02350 
02351 /* Bit 19 : Set as output pin 19. */
02352 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
02353 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
02354 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
02355 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
02356 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
02357 
02358 /* Bit 18 : Set as output pin 18. */
02359 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
02360 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
02361 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
02362 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
02363 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
02364 
02365 /* Bit 17 : Set as output pin 17. */
02366 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
02367 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
02368 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
02369 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
02370 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
02371 
02372 /* Bit 16 : Set as output pin 16. */
02373 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
02374 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
02375 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
02376 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
02377 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
02378 
02379 /* Bit 15 : Set as output pin 15. */
02380 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
02381 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
02382 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
02383 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
02384 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
02385 
02386 /* Bit 14 : Set as output pin 14. */
02387 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
02388 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
02389 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
02390 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
02391 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
02392 
02393 /* Bit 13 : Set as output pin 13. */
02394 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
02395 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
02396 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
02397 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
02398 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
02399 
02400 /* Bit 12 : Set as output pin 12. */
02401 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
02402 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
02403 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
02404 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
02405 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
02406 
02407 /* Bit 11 : Set as output pin 11. */
02408 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
02409 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
02410 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
02411 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
02412 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
02413 
02414 /* Bit 10 : Set as output pin 10. */
02415 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
02416 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
02417 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
02418 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
02419 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
02420 
02421 /* Bit 9 : Set as output pin 9. */
02422 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
02423 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
02424 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
02425 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
02426 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
02427 
02428 /* Bit 8 : Set as output pin 8. */
02429 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
02430 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
02431 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
02432 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
02433 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
02434 
02435 /* Bit 7 : Set as output pin 7. */
02436 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
02437 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
02438 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
02439 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
02440 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
02441 
02442 /* Bit 6 : Set as output pin 6. */
02443 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
02444 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
02445 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
02446 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
02447 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
02448 
02449 /* Bit 5 : Set as output pin 5. */
02450 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
02451 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
02452 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
02453 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
02454 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
02455 
02456 /* Bit 4 : Set as output pin 4. */
02457 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
02458 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
02459 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
02460 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
02461 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
02462 
02463 /* Bit 3 : Set as output pin 3. */
02464 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
02465 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
02466 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
02467 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
02468 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
02469 
02470 /* Bit 2 : Set as output pin 2. */
02471 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
02472 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
02473 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
02474 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
02475 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
02476 
02477 /* Bit 1 : Set as output pin 1. */
02478 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
02479 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
02480 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
02481 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
02482 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
02483 
02484 /* Bit 0 : Set as output pin 0. */
02485 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
02486 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
02487 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
02488 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
02489 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
02490 
02491 /* Register: GPIO_DIRCLR */
02492 /* Description: DIR clear register. */
02493 
02494 /* Bit 31 : Set as input pin 31. */
02495 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
02496 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
02497 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
02498 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
02499 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
02500 
02501 /* Bit 30 : Set as input pin 30. */
02502 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
02503 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
02504 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
02505 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
02506 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
02507 
02508 /* Bit 29 : Set as input pin 29. */
02509 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
02510 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
02511 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
02512 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
02513 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
02514 
02515 /* Bit 28 : Set as input pin 28. */
02516 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
02517 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
02518 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
02519 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
02520 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
02521 
02522 /* Bit 27 : Set as input pin 27. */
02523 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
02524 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
02525 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
02526 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
02527 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
02528 
02529 /* Bit 26 : Set as input pin 26. */
02530 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
02531 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
02532 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
02533 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
02534 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
02535 
02536 /* Bit 25 : Set as input pin 25. */
02537 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
02538 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
02539 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
02540 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
02541 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
02542 
02543 /* Bit 24 : Set as input pin 24. */
02544 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
02545 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
02546 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
02547 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
02548 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
02549 
02550 /* Bit 23 : Set as input pin 23. */
02551 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
02552 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
02553 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
02554 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
02555 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
02556 
02557 /* Bit 22 : Set as input pin 22. */
02558 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
02559 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
02560 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
02561 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
02562 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
02563 
02564 /* Bit 21 : Set as input pin 21. */
02565 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
02566 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
02567 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
02568 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
02569 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
02570 
02571 /* Bit 20 : Set as input pin 20. */
02572 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
02573 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
02574 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
02575 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
02576 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
02577 
02578 /* Bit 19 : Set as input pin 19. */
02579 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
02580 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
02581 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
02582 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
02583 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
02584 
02585 /* Bit 18 : Set as input pin 18. */
02586 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
02587 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
02588 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
02589 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
02590 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
02591 
02592 /* Bit 17 : Set as input pin 17. */
02593 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
02594 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
02595 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
02596 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
02597 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
02598 
02599 /* Bit 16 : Set as input pin 16. */
02600 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
02601 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
02602 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
02603 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
02604 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
02605 
02606 /* Bit 15 : Set as input pin 15. */
02607 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
02608 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
02609 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
02610 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
02611 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
02612 
02613 /* Bit 14 : Set as input pin 14. */
02614 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
02615 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
02616 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
02617 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
02618 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
02619 
02620 /* Bit 13 : Set as input pin 13. */
02621 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
02622 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
02623 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
02624 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
02625 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
02626 
02627 /* Bit 12 : Set as input pin 12. */
02628 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
02629 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
02630 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
02631 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
02632 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
02633 
02634 /* Bit 11 : Set as input pin 11. */
02635 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
02636 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
02637 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
02638 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
02639 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
02640 
02641 /* Bit 10 : Set as input pin 10. */
02642 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
02643 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
02644 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
02645 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
02646 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
02647 
02648 /* Bit 9 : Set as input pin 9. */
02649 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
02650 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
02651 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
02652 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
02653 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
02654 
02655 /* Bit 8 : Set as input pin 8. */
02656 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
02657 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
02658 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
02659 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
02660 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
02661 
02662 /* Bit 7 : Set as input pin 7. */
02663 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
02664 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
02665 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
02666 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
02667 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
02668 
02669 /* Bit 6 : Set as input pin 6. */
02670 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
02671 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
02672 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
02673 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
02674 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
02675 
02676 /* Bit 5 : Set as input pin 5. */
02677 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
02678 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
02679 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
02680 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
02681 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
02682 
02683 /* Bit 4 : Set as input pin 4. */
02684 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
02685 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
02686 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
02687 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
02688 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
02689 
02690 /* Bit 3 : Set as input pin 3. */
02691 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
02692 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
02693 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
02694 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
02695 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
02696 
02697 /* Bit 2 : Set as input pin 2. */
02698 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
02699 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
02700 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
02701 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
02702 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
02703 
02704 /* Bit 1 : Set as input pin 1. */
02705 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
02706 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
02707 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
02708 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
02709 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
02710 
02711 /* Bit 0 : Set as input pin 0. */
02712 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
02713 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
02714 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
02715 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
02716 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
02717 
02718 /* Register: GPIO_PIN_CNF */
02719 /* Description: Configuration of GPIO pins. */
02720 
02721 /* Bits 17..16 : Pin sensing mechanism. */
02722 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
02723 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
02724 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
02725 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
02726 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
02727 
02728 /* Bits 10..8 : Drive configuration. */
02729 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
02730 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
02731 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
02732 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
02733 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
02734 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
02735 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
02736 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
02737 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
02738 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
02739 
02740 /* Bits 3..2 : Pull-up or -down configuration. */
02741 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
02742 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
02743 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
02744 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
02745 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
02746 
02747 /* Bit 1 : Connect or disconnect input path. */
02748 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
02749 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
02750 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
02751 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
02752 
02753 /* Bit 0 : Pin direction. */
02754 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
02755 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
02756 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
02757 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
02758 
02759 
02760 /* Peripheral: GPIOTE */
02761 /* Description: GPIO tasks and events. */
02762 
02763 /* Register: GPIOTE_INTENSET */
02764 /* Description: Interrupt enable set register. */
02765 
02766 /* Bit 31 : Enable interrupt on PORT event. */
02767 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
02768 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
02769 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
02770 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
02771 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
02772 
02773 /* Bit 3 : Enable interrupt on IN[3] event. */
02774 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
02775 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
02776 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
02777 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
02778 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
02779 
02780 /* Bit 2 : Enable interrupt on IN[2] event. */
02781 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
02782 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
02783 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
02784 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
02785 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
02786 
02787 /* Bit 1 : Enable interrupt on IN[1] event. */
02788 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
02789 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
02790 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
02791 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
02792 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
02793 
02794 /* Bit 0 : Enable interrupt on IN[0] event. */
02795 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
02796 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
02797 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
02798 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
02799 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
02800 
02801 /* Register: GPIOTE_INTENCLR */
02802 /* Description: Interrupt enable clear register. */
02803 
02804 /* Bit 31 : Disable interrupt on PORT event. */
02805 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
02806 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
02807 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
02808 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
02809 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
02810 
02811 /* Bit 3 : Disable interrupt on IN[3] event. */
02812 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
02813 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
02814 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
02815 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
02816 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
02817 
02818 /* Bit 2 : Disable interrupt on IN[2] event. */
02819 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
02820 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
02821 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
02822 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
02823 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
02824 
02825 /* Bit 1 : Disable interrupt on IN[1] event. */
02826 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
02827 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
02828 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
02829 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
02830 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
02831 
02832 /* Bit 0 : Disable interrupt on IN[0] event. */
02833 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
02834 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
02835 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
02836 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
02837 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
02838 
02839 /* Register: GPIOTE_CONFIG */
02840 /* Description: Channel configuration registers. */
02841 
02842 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
02843 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
02844 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
02845 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
02846 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
02847 
02848 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
02849 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
02850 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
02851 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
02852 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
02853 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
02854 
02855 /* Bits 12..8 : Pin select. */
02856 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
02857 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
02858 
02859 /* Bits 1..0 : Mode */
02860 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
02861 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
02862 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
02863 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
02864 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
02865 
02866 /* Register: GPIOTE_POWER */
02867 /* Description: Peripheral power control. */
02868 
02869 /* Bit 0 : Peripheral power control. */
02870 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
02871 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
02872 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
02873 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
02874 
02875 
02876 /* Peripheral: LPCOMP */
02877 /* Description: Low power comparator. */
02878 
02879 /* Register: LPCOMP_SHORTS */
02880 /* Description: Shortcuts for the LPCOMP. */
02881 
02882 /* Bit 4 : Shortcut between CROSS event and STOP task. */
02883 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
02884 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
02885 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
02886 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
02887 
02888 /* Bit 3 : Shortcut between UP event and STOP task. */
02889 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
02890 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
02891 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
02892 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
02893 
02894 /* Bit 2 : Shortcut between DOWN event and STOP task. */
02895 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
02896 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
02897 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
02898 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
02899 
02900 /* Bit 1 : Shortcut between RADY event and STOP task. */
02901 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
02902 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
02903 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
02904 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
02905 
02906 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
02907 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
02908 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
02909 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
02910 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
02911 
02912 /* Register: LPCOMP_INTENSET */
02913 /* Description: Interrupt enable set register. */
02914 
02915 /* Bit 3 : Enable interrupt on CROSS event. */
02916 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
02917 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
02918 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
02919 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
02920 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
02921 
02922 /* Bit 2 : Enable interrupt on UP event. */
02923 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
02924 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
02925 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
02926 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
02927 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
02928 
02929 /* Bit 1 : Enable interrupt on DOWN event. */
02930 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
02931 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
02932 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
02933 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
02934 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
02935 
02936 /* Bit 0 : Enable interrupt on READY event. */
02937 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
02938 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
02939 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
02940 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
02941 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
02942 
02943 /* Register: LPCOMP_INTENCLR */
02944 /* Description: Interrupt enable clear register. */
02945 
02946 /* Bit 3 : Disable interrupt on CROSS event. */
02947 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
02948 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
02949 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
02950 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
02951 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
02952 
02953 /* Bit 2 : Disable interrupt on UP event. */
02954 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
02955 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
02956 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
02957 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
02958 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
02959 
02960 /* Bit 1 : Disable interrupt on DOWN event. */
02961 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
02962 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
02963 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
02964 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
02965 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
02966 
02967 /* Bit 0 : Disable interrupt on READY event. */
02968 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
02969 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
02970 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
02971 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
02972 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
02973 
02974 /* Register: LPCOMP_RESULT */
02975 /* Description: Result of last compare. */
02976 
02977 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
02978 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
02979 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
02980 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
02981 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
02982 
02983 /* Register: LPCOMP_ENABLE */
02984 /* Description: Enable the LPCOMP. */
02985 
02986 /* Bits 1..0 : Enable or disable LPCOMP. */
02987 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
02988 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
02989 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
02990 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
02991 
02992 /* Register: LPCOMP_PSEL */
02993 /* Description: Input pin select. */
02994 
02995 /* Bits 2..0 : Analog input pin select. */
02996 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
02997 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
02998 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
02999 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
03000 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
03001 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
03002 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
03003 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
03004 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
03005 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
03006 
03007 /* Register: LPCOMP_REFSEL */
03008 /* Description: Reference select. */
03009 
03010 /* Bits 2..0 : Reference select. */
03011 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
03012 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
03013 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
03014 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
03015 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
03016 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
03017 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
03018 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
03019 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
03020 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
03021 
03022 /* Register: LPCOMP_EXTREFSEL */
03023 /* Description: External reference select. */
03024 
03025 /* Bit 0 : External analog reference pin selection. */
03026 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
03027 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
03028 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
03029 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
03030 
03031 /* Register: LPCOMP_ANADETECT */
03032 /* Description: Analog detect configuration. */
03033 
03034 /* Bits 1..0 : Analog detect configuration. */
03035 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
03036 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
03037 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
03038 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
03039 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
03040 
03041 /* Register: LPCOMP_POWER */
03042 /* Description: Peripheral power control. */
03043 
03044 /* Bit 0 : Peripheral power control. */
03045 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
03046 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
03047 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
03048 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
03049 
03050 
03051 /* Peripheral: MPU */
03052 /* Description: Memory Protection Unit. */
03053 
03054 /* Register: MPU_PERR0 */
03055 /* Description: Configuration of peripherals in mpu regions. */
03056 
03057 /* Bit 31 : PPI region configuration. */
03058 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
03059 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
03060 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03061 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03062 
03063 /* Bit 30 : NVMC region configuration. */
03064 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
03065 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
03066 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03067 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03068 
03069 /* Bit 19 : LPCOMP region configuration. */
03070 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
03071 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
03072 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03073 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03074 
03075 /* Bit 18 : QDEC region configuration. */
03076 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
03077 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
03078 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03079 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03080 
03081 /* Bit 17 : RTC1 region configuration. */
03082 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
03083 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
03084 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03085 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03086 
03087 /* Bit 16 : WDT region configuration. */
03088 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
03089 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
03090 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03091 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03092 
03093 /* Bit 15 : CCM and AAR region configuration. */
03094 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
03095 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
03096 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03097 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03098 
03099 /* Bit 14 : ECB region configuration. */
03100 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
03101 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
03102 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03103 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03104 
03105 /* Bit 13 : RNG region configuration. */
03106 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
03107 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
03108 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03109 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03110 
03111 /* Bit 12 : TEMP region configuration. */
03112 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
03113 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
03114 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03115 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03116 
03117 /* Bit 11 : RTC0 region configuration. */
03118 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
03119 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
03120 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03121 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03122 
03123 /* Bit 10 : TIMER2 region configuration. */
03124 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
03125 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
03126 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03127 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03128 
03129 /* Bit 9 : TIMER1 region configuration. */
03130 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
03131 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
03132 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03133 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03134 
03135 /* Bit 8 : TIMER0 region configuration. */
03136 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
03137 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
03138 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03139 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03140 
03141 /* Bit 7 : ADC region configuration. */
03142 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
03143 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
03144 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03145 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03146 
03147 /* Bit 6 : GPIOTE region configuration. */
03148 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
03149 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
03150 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03151 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03152 
03153 /* Bit 4 : SPI1 and TWI1 region configuration. */
03154 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
03155 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
03156 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03157 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03158 
03159 /* Bit 3 : SPI0 and TWI0 region configuration. */
03160 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
03161 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
03162 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03163 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03164 
03165 /* Bit 2 : UART0 region configuration. */
03166 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
03167 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
03168 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03169 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03170 
03171 /* Bit 1 : RADIO region configuration. */
03172 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
03173 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
03174 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03175 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03176 
03177 /* Bit 0 : POWER_CLOCK region configuration. */
03178 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
03179 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
03180 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
03181 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
03182 
03183 /* Register: MPU_PROTENSET0 */
03184 /* Description: Erase and write protection bit enable set register. */
03185 
03186 /* Bit 31 : Protection enable for region 31. */
03187 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
03188 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
03189 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
03190 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
03191 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
03192 
03193 /* Bit 30 : Protection enable for region 30. */
03194 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
03195 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
03196 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
03197 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
03198 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
03199 
03200 /* Bit 29 : Protection enable for region 29. */
03201 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
03202 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
03203 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
03204 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
03205 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
03206 
03207 /* Bit 28 : Protection enable for region 28. */
03208 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
03209 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
03210 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
03211 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
03212 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
03213 
03214 /* Bit 27 : Protection enable for region 27. */
03215 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
03216 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
03217 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
03218 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
03219 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
03220 
03221 /* Bit 26 : Protection enable for region 26. */
03222 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
03223 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
03224 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
03225 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
03226 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
03227 
03228 /* Bit 25 : Protection enable for region 25. */
03229 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
03230 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
03231 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
03232 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
03233 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
03234 
03235 /* Bit 24 : Protection enable for region 24. */
03236 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
03237 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
03238 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
03239 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
03240 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
03241 
03242 /* Bit 23 : Protection enable for region 23. */
03243 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
03244 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
03245 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
03246 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
03247 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
03248 
03249 /* Bit 22 : Protection enable for region 22. */
03250 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
03251 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
03252 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
03253 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
03254 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
03255 
03256 /* Bit 21 : Protection enable for region 21. */
03257 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
03258 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
03259 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
03260 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
03261 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
03262 
03263 /* Bit 20 : Protection enable for region 20. */
03264 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
03265 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
03266 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
03267 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
03268 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
03269 
03270 /* Bit 19 : Protection enable for region 19. */
03271 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
03272 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
03273 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
03274 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
03275 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
03276 
03277 /* Bit 18 : Protection enable for region 18. */
03278 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
03279 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
03280 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
03281 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
03282 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
03283 
03284 /* Bit 17 : Protection enable for region 17. */
03285 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
03286 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
03287 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
03288 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
03289 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
03290 
03291 /* Bit 16 : Protection enable for region 16. */
03292 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
03293 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
03294 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
03295 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
03296 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
03297 
03298 /* Bit 15 : Protection enable for region 15. */
03299 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
03300 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
03301 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
03302 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
03303 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
03304 
03305 /* Bit 14 : Protection enable for region 14. */
03306 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
03307 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
03308 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
03309 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
03310 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
03311 
03312 /* Bit 13 : Protection enable for region 13. */
03313 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
03314 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
03315 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
03316 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
03317 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
03318 
03319 /* Bit 12 : Protection enable for region 12. */
03320 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
03321 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
03322 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
03323 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
03324 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
03325 
03326 /* Bit 11 : Protection enable for region 11. */
03327 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
03328 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
03329 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
03330 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
03331 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
03332 
03333 /* Bit 10 : Protection enable for region 10. */
03334 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
03335 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
03336 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
03337 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
03338 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
03339 
03340 /* Bit 9 : Protection enable for region 9. */
03341 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
03342 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
03343 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
03344 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
03345 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
03346 
03347 /* Bit 8 : Protection enable for region 8. */
03348 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
03349 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
03350 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
03351 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
03352 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
03353 
03354 /* Bit 7 : Protection enable for region 7. */
03355 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
03356 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
03357 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
03358 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
03359 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
03360 
03361 /* Bit 6 : Protection enable for region 6. */
03362 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
03363 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
03364 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
03365 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
03366 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
03367 
03368 /* Bit 5 : Protection enable for region 5. */
03369 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
03370 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
03371 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
03372 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
03373 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
03374 
03375 /* Bit 4 : Protection enable for region 4. */
03376 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
03377 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
03378 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
03379 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
03380 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
03381 
03382 /* Bit 3 : Protection enable for region 3. */
03383 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
03384 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
03385 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
03386 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
03387 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
03388 
03389 /* Bit 2 : Protection enable for region 2. */
03390 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
03391 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
03392 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
03393 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
03394 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
03395 
03396 /* Bit 1 : Protection enable for region 1. */
03397 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
03398 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
03399 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
03400 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
03401 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
03402 
03403 /* Bit 0 : Protection enable for region 0. */
03404 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
03405 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
03406 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
03407 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
03408 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
03409 
03410 /* Register: MPU_PROTENSET1 */
03411 /* Description: Erase and write protection bit enable set register. */
03412 
03413 /* Bit 31 : Protection enable for region 63. */
03414 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
03415 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
03416 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
03417 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
03418 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
03419 
03420 /* Bit 30 : Protection enable for region 62. */
03421 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
03422 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
03423 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
03424 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
03425 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
03426 
03427 /* Bit 29 : Protection enable for region 61. */
03428 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
03429 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
03430 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
03431 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
03432 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
03433 
03434 /* Bit 28 : Protection enable for region 60. */
03435 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
03436 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
03437 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
03438 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
03439 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
03440 
03441 /* Bit 27 : Protection enable for region 59. */
03442 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
03443 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
03444 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
03445 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
03446 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
03447 
03448 /* Bit 26 : Protection enable for region 58. */
03449 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
03450 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
03451 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
03452 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
03453 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
03454 
03455 /* Bit 25 : Protection enable for region 57. */
03456 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
03457 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
03458 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
03459 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
03460 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
03461 
03462 /* Bit 24 : Protection enable for region 56. */
03463 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
03464 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
03465 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
03466 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
03467 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
03468 
03469 /* Bit 23 : Protection enable for region 55. */
03470 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
03471 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
03472 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
03473 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
03474 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
03475 
03476 /* Bit 22 : Protection enable for region 54. */
03477 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
03478 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
03479 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
03480 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
03481 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
03482 
03483 /* Bit 21 : Protection enable for region 53. */
03484 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
03485 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
03486 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
03487 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
03488 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
03489 
03490 /* Bit 20 : Protection enable for region 52. */
03491 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
03492 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
03493 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
03494 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
03495 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
03496 
03497 /* Bit 19 : Protection enable for region 51. */
03498 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
03499 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
03500 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
03501 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
03502 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
03503 
03504 /* Bit 18 : Protection enable for region 50. */
03505 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
03506 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
03507 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
03508 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
03509 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
03510 
03511 /* Bit 17 : Protection enable for region 49. */
03512 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
03513 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
03514 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
03515 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
03516 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
03517 
03518 /* Bit 16 : Protection enable for region 48. */
03519 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
03520 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
03521 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
03522 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
03523 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
03524 
03525 /* Bit 15 : Protection enable for region 47. */
03526 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
03527 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
03528 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
03529 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
03530 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
03531 
03532 /* Bit 14 : Protection enable for region 46. */
03533 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
03534 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
03535 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
03536 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
03537 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
03538 
03539 /* Bit 13 : Protection enable for region 45. */
03540 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
03541 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
03542 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
03543 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
03544 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
03545 
03546 /* Bit 12 : Protection enable for region 44. */
03547 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
03548 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
03549 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
03550 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
03551 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
03552 
03553 /* Bit 11 : Protection enable for region 43. */
03554 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
03555 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
03556 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
03557 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
03558 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
03559 
03560 /* Bit 10 : Protection enable for region 42. */
03561 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
03562 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
03563 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
03564 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
03565 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
03566 
03567 /* Bit 9 : Protection enable for region 41. */
03568 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
03569 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
03570 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
03571 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
03572 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
03573 
03574 /* Bit 8 : Protection enable for region 40. */
03575 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
03576 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
03577 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
03578 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
03579 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
03580 
03581 /* Bit 7 : Protection enable for region 39. */
03582 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
03583 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
03584 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
03585 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
03586 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
03587 
03588 /* Bit 6 : Protection enable for region 38. */
03589 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
03590 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
03591 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
03592 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
03593 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
03594 
03595 /* Bit 5 : Protection enable for region 37. */
03596 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
03597 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
03598 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
03599 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
03600 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
03601 
03602 /* Bit 4 : Protection enable for region 36. */
03603 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
03604 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
03605 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
03606 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
03607 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
03608 
03609 /* Bit 3 : Protection enable for region 35. */
03610 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
03611 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
03612 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
03613 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
03614 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
03615 
03616 /* Bit 2 : Protection enable for region 34. */
03617 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
03618 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
03619 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
03620 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
03621 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
03622 
03623 /* Bit 1 : Protection enable for region 33. */
03624 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
03625 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
03626 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
03627 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
03628 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
03629 
03630 /* Bit 0 : Protection enable for region 32. */
03631 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
03632 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
03633 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
03634 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
03635 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
03636 
03637 /* Register: MPU_DISABLEINDEBUG */
03638 /* Description: Disable erase and write protection mechanism in debug mode. */
03639 
03640 /* Bit 0 : Disable protection mechanism in debug mode. */
03641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
03642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
03643 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
03644 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
03645 
03646 /* Register: MPU_PROTBLOCKSIZE */
03647 /* Description: Erase and write protection block size. */
03648 
03649 /* Bits 1..0 : Erase and write protection block size. */
03650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
03651 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
03652 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
03653 
03654 
03655 /* Peripheral: NVMC */
03656 /* Description: Non Volatile Memory Controller. */
03657 
03658 /* Register: NVMC_READY */
03659 /* Description: Ready flag. */
03660 
03661 /* Bit 0 : NVMC ready. */
03662 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
03663 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
03664 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
03665 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
03666 
03667 /* Register: NVMC_CONFIG */
03668 /* Description: Configuration register. */
03669 
03670 /* Bits 1..0 : Program write enable. */
03671 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
03672 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
03673 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
03674 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
03675 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
03676 
03677 /* Register: NVMC_ERASEALL */
03678 /* Description: Register for erasing all non-volatile user memory. */
03679 
03680 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
03681 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
03682 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
03683 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
03684 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
03685 
03686 /* Register: NVMC_ERASEUICR */
03687 /* Description: Register for start erasing User Information Congfiguration Registers. */
03688 
03689 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
03690 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
03691 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
03692 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
03693 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
03694 
03695 
03696 /* Peripheral: POWER */
03697 /* Description: Power Control. */
03698 
03699 /* Register: POWER_INTENSET */
03700 /* Description: Interrupt enable set register. */
03701 
03702 /* Bit 2 : Enable interrupt on POFWARN event. */
03703 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
03704 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
03705 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
03706 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
03707 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
03708 
03709 /* Register: POWER_INTENCLR */
03710 /* Description: Interrupt enable clear register. */
03711 
03712 /* Bit 2 : Disable interrupt on POFWARN event. */
03713 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
03714 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
03715 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
03716 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
03717 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
03718 
03719 /* Register: POWER_RESETREAS */
03720 /* Description: Reset reason. */
03721 
03722 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
03723 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
03724 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
03725 
03726 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
03727 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
03728 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
03729 
03730 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
03731 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
03732 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
03733 
03734 /* Bit 3 : Reset from CPU lock-up detected. */
03735 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
03736 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
03737 
03738 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
03739 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
03740 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
03741 
03742 /* Bit 1 : Reset from watchdog detected. */
03743 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
03744 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
03745 
03746 /* Bit 0 : Reset from pin-reset detected. */
03747 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
03748 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
03749 
03750 /* Register: POWER_RAMSTATUS */
03751 /* Description: Ram status register. */
03752 
03753 /* Bit 3 : RAM block 3 status. */
03754 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
03755 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
03756 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
03757 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
03758 
03759 /* Bit 2 : RAM block 2 status. */
03760 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
03761 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
03762 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
03763 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
03764 
03765 /* Bit 1 : RAM block 1 status. */
03766 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
03767 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
03768 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
03769 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
03770 
03771 /* Bit 0 : RAM block 0 status. */
03772 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
03773 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
03774 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
03775 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
03776 
03777 /* Register: POWER_SYSTEMOFF */
03778 /* Description: System off register. */
03779 
03780 /* Bit 0 : Enter system off mode. */
03781 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
03782 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
03783 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
03784 
03785 /* Register: POWER_POFCON */
03786 /* Description: Power failure configuration. */
03787 
03788 /* Bits 2..1 : Set threshold level. */
03789 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
03790 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
03791 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
03792 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
03793 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
03794 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
03795 
03796 /* Bit 0 : Power failure comparator enable. */
03797 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
03798 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
03799 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
03800 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
03801 
03802 /* Register: POWER_GPREGRET */
03803 /* Description: General purpose retention register. This register is a retained register. */
03804 
03805 /* Bits 7..0 : General purpose retention register. */
03806 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
03807 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
03808 
03809 /* Register: POWER_RAMON */
03810 /* Description: Ram on/off. */
03811 
03812 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
03813 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
03814 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
03815 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
03816 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
03817 
03818 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
03819 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
03820 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
03821 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
03822 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
03823 
03824 /* Bit 1 : RAM block 1 behaviour in ON mode. */
03825 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
03826 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
03827 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
03828 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
03829 
03830 /* Bit 0 : RAM block 0 behaviour in ON mode. */
03831 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
03832 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
03833 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
03834 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
03835 
03836 /* Register: POWER_RESET */
03837 /* Description: Pin reset functionality configuration register. This register is a retained register. */
03838 
03839 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
03840 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
03841 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
03842 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
03843 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
03844 
03845 /* Register: POWER_RAMONB */
03846 /* Description: Ram on/off. */
03847 
03848 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
03849 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
03850 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
03851 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
03852 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
03853 
03854 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
03855 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
03856 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
03857 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
03858 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
03859 
03860 /* Bit 1 : RAM block 3 behaviour in ON mode. */
03861 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
03862 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
03863 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
03864 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
03865 
03866 /* Bit 0 : RAM block 2 behaviour in ON mode. */
03867 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
03868 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
03869 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
03870 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
03871 
03872 /* Register: POWER_DCDCEN */
03873 /* Description: DCDC converter enable configuration register. */
03874 
03875 /* Bit 0 : Enable DCDC converter. */
03876 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
03877 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
03878 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
03879 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
03880 
03881 /* Register: POWER_DCDCFORCE */
03882 /* Description: DCDC power-up force register. */
03883 
03884 /* Bit 1 : DCDC power-up force on. */
03885 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
03886 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
03887 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
03888 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
03889 
03890 /* Bit 0 : DCDC power-up force off. */
03891 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
03892 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
03893 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
03894 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
03895 
03896 
03897 /* Peripheral: PPI */
03898 /* Description: PPI controller. */
03899 
03900 /* Register: PPI_CHEN */
03901 /* Description: Channel enable. */
03902 
03903 /* Bit 31 : Enable PPI channel 31. */
03904 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
03905 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
03906 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
03907 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
03908 
03909 /* Bit 30 : Enable PPI channel 30. */
03910 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
03911 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
03912 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
03913 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
03914 
03915 /* Bit 29 : Enable PPI channel 29. */
03916 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
03917 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
03918 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
03919 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
03920 
03921 /* Bit 28 : Enable PPI channel 28. */
03922 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
03923 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
03924 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
03925 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
03926 
03927 /* Bit 27 : Enable PPI channel 27. */
03928 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
03929 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
03930 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
03931 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
03932 
03933 /* Bit 26 : Enable PPI channel 26. */
03934 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
03935 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
03936 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
03937 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
03938 
03939 /* Bit 25 : Enable PPI channel 25. */
03940 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
03941 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
03942 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
03943 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
03944 
03945 /* Bit 24 : Enable PPI channel 24. */
03946 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
03947 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
03948 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
03949 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
03950 
03951 /* Bit 23 : Enable PPI channel 23. */
03952 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
03953 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
03954 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
03955 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
03956 
03957 /* Bit 22 : Enable PPI channel 22. */
03958 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
03959 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
03960 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
03961 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
03962 
03963 /* Bit 21 : Enable PPI channel 21. */
03964 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
03965 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
03966 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
03967 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
03968 
03969 /* Bit 20 : Enable PPI channel 20. */
03970 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
03971 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
03972 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
03973 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
03974 
03975 /* Bit 15 : Enable PPI channel 15. */
03976 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
03977 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
03978 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
03979 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
03980 
03981 /* Bit 14 : Enable PPI channel 14. */
03982 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
03983 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
03984 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
03985 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
03986 
03987 /* Bit 13 : Enable PPI channel 13. */
03988 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
03989 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
03990 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
03991 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
03992 
03993 /* Bit 12 : Enable PPI channel 12. */
03994 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
03995 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
03996 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
03997 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
03998 
03999 /* Bit 11 : Enable PPI channel 11. */
04000 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
04001 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
04002 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
04003 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
04004 
04005 /* Bit 10 : Enable PPI channel 10. */
04006 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
04007 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
04008 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
04009 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
04010 
04011 /* Bit 9 : Enable PPI channel 9. */
04012 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
04013 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
04014 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
04015 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
04016 
04017 /* Bit 8 : Enable PPI channel 8. */
04018 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
04019 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
04020 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
04021 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
04022 
04023 /* Bit 7 : Enable PPI channel 7. */
04024 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
04025 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
04026 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
04027 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
04028 
04029 /* Bit 6 : Enable PPI channel 6. */
04030 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
04031 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
04032 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
04033 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
04034 
04035 /* Bit 5 : Enable PPI channel 5. */
04036 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
04037 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
04038 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
04039 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
04040 
04041 /* Bit 4 : Enable PPI channel 4. */
04042 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
04043 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
04044 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
04045 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
04046 
04047 /* Bit 3 : Enable PPI channel 3. */
04048 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
04049 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
04050 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
04051 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
04052 
04053 /* Bit 2 : Enable PPI channel 2. */
04054 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
04055 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
04056 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
04057 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
04058 
04059 /* Bit 1 : Enable PPI channel 1. */
04060 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
04061 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
04062 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
04063 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
04064 
04065 /* Bit 0 : Enable PPI channel 0. */
04066 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
04067 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
04068 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
04069 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
04070 
04071 /* Register: PPI_CHENSET */
04072 /* Description: Channel enable set. */
04073 
04074 /* Bit 31 : Enable PPI channel 31. */
04075 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
04076 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
04077 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
04078 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
04079 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
04080 
04081 /* Bit 30 : Enable PPI channel 30. */
04082 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
04083 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
04084 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
04085 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
04086 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
04087 
04088 /* Bit 29 : Enable PPI channel 29. */
04089 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
04090 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
04091 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
04092 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
04093 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
04094 
04095 /* Bit 28 : Enable PPI channel 28. */
04096 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
04097 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
04098 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
04099 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
04100 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
04101 
04102 /* Bit 27 : Enable PPI channel 27. */
04103 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
04104 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
04105 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
04106 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
04107 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
04108 
04109 /* Bit 26 : Enable PPI channel 26. */
04110 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
04111 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
04112 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
04113 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
04114 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
04115 
04116 /* Bit 25 : Enable PPI channel 25. */
04117 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
04118 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
04119 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
04120 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
04121 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
04122 
04123 /* Bit 24 : Enable PPI channel 24. */
04124 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
04125 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
04126 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
04127 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
04128 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
04129 
04130 /* Bit 23 : Enable PPI channel 23. */
04131 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
04132 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
04133 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
04134 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
04135 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
04136 
04137 /* Bit 22 : Enable PPI channel 22. */
04138 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
04139 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
04140 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
04141 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
04142 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
04143 
04144 /* Bit 21 : Enable PPI channel 21. */
04145 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
04146 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
04147 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
04148 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
04149 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
04150 
04151 /* Bit 20 : Enable PPI channel 20. */
04152 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
04153 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
04154 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
04155 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
04156 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
04157 
04158 /* Bit 15 : Enable PPI channel 15. */
04159 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
04160 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
04161 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
04162 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
04163 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
04164 
04165 /* Bit 14 : Enable PPI channel 14. */
04166 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
04167 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
04168 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
04169 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
04170 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
04171 
04172 /* Bit 13 : Enable PPI channel 13. */
04173 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
04174 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
04175 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
04176 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
04177 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
04178 
04179 /* Bit 12 : Enable PPI channel 12. */
04180 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
04181 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
04182 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
04183 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
04184 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
04185 
04186 /* Bit 11 : Enable PPI channel 11. */
04187 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
04188 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
04189 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
04190 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
04191 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
04192 
04193 /* Bit 10 : Enable PPI channel 10. */
04194 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
04195 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
04196 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
04197 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
04198 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
04199 
04200 /* Bit 9 : Enable PPI channel 9. */
04201 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
04202 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
04203 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
04204 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
04205 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
04206 
04207 /* Bit 8 : Enable PPI channel 8. */
04208 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
04209 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
04210 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
04211 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
04212 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
04213 
04214 /* Bit 7 : Enable PPI channel 7. */
04215 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
04216 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
04217 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
04218 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
04219 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
04220 
04221 /* Bit 6 : Enable PPI channel 6. */
04222 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
04223 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
04224 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
04225 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
04226 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
04227 
04228 /* Bit 5 : Enable PPI channel 5. */
04229 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
04230 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
04231 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
04232 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
04233 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
04234 
04235 /* Bit 4 : Enable PPI channel 4. */
04236 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
04237 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
04238 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
04239 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
04240 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
04241 
04242 /* Bit 3 : Enable PPI channel 3. */
04243 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
04244 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
04245 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
04246 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
04247 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
04248 
04249 /* Bit 2 : Enable PPI channel 2. */
04250 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
04251 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
04252 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
04253 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
04254 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
04255 
04256 /* Bit 1 : Enable PPI channel 1. */
04257 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
04258 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
04259 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
04260 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
04261 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
04262 
04263 /* Bit 0 : Enable PPI channel 0. */
04264 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
04265 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
04266 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
04267 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
04268 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
04269 
04270 /* Register: PPI_CHENCLR */
04271 /* Description: Channel enable clear. */
04272 
04273 /* Bit 31 : Disable PPI channel 31. */
04274 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
04275 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
04276 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
04277 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
04278 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
04279 
04280 /* Bit 30 : Disable PPI channel 30. */
04281 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
04282 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
04283 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
04284 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
04285 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
04286 
04287 /* Bit 29 : Disable PPI channel 29. */
04288 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
04289 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
04290 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
04291 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
04292 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
04293 
04294 /* Bit 28 : Disable PPI channel 28. */
04295 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
04296 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
04297 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
04298 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
04299 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
04300 
04301 /* Bit 27 : Disable PPI channel 27. */
04302 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
04303 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
04304 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
04305 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
04306 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
04307 
04308 /* Bit 26 : Disable PPI channel 26. */
04309 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
04310 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
04311 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
04312 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
04313 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
04314 
04315 /* Bit 25 : Disable PPI channel 25. */
04316 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
04317 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
04318 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
04319 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
04320 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
04321 
04322 /* Bit 24 : Disable PPI channel 24. */
04323 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
04324 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
04325 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
04326 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
04327 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
04328 
04329 /* Bit 23 : Disable PPI channel 23. */
04330 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
04331 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
04332 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
04333 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
04334 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
04335 
04336 /* Bit 22 : Disable PPI channel 22. */
04337 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
04338 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
04339 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
04340 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
04341 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
04342 
04343 /* Bit 21 : Disable PPI channel 21. */
04344 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
04345 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
04346 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
04347 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
04348 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
04349 
04350 /* Bit 20 : Disable PPI channel 20. */
04351 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
04352 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
04353 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
04354 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
04355 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
04356 
04357 /* Bit 15 : Disable PPI channel 15. */
04358 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
04359 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
04360 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
04361 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
04362 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
04363 
04364 /* Bit 14 : Disable PPI channel 14. */
04365 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
04366 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
04367 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
04368 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
04369 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
04370 
04371 /* Bit 13 : Disable PPI channel 13. */
04372 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
04373 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
04374 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
04375 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
04376 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
04377 
04378 /* Bit 12 : Disable PPI channel 12. */
04379 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
04380 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
04381 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
04382 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
04383 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
04384 
04385 /* Bit 11 : Disable PPI channel 11. */
04386 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
04387 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
04388 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
04389 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
04390 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
04391 
04392 /* Bit 10 : Disable PPI channel 10. */
04393 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
04394 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
04395 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
04396 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
04397 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
04398 
04399 /* Bit 9 : Disable PPI channel 9. */
04400 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
04401 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
04402 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
04403 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
04404 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
04405 
04406 /* Bit 8 : Disable PPI channel 8. */
04407 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
04408 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
04409 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
04410 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
04411 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
04412 
04413 /* Bit 7 : Disable PPI channel 7. */
04414 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
04415 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
04416 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
04417 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
04418 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
04419 
04420 /* Bit 6 : Disable PPI channel 6. */
04421 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
04422 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
04423 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
04424 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
04425 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
04426 
04427 /* Bit 5 : Disable PPI channel 5. */
04428 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
04429 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
04430 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
04431 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
04432 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
04433 
04434 /* Bit 4 : Disable PPI channel 4. */
04435 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
04436 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
04437 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
04438 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
04439 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
04440 
04441 /* Bit 3 : Disable PPI channel 3. */
04442 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
04443 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
04444 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
04445 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
04446 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
04447 
04448 /* Bit 2 : Disable PPI channel 2. */
04449 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
04450 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
04451 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
04452 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
04453 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
04454 
04455 /* Bit 1 : Disable PPI channel 1. */
04456 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
04457 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
04458 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
04459 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
04460 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
04461 
04462 /* Bit 0 : Disable PPI channel 0. */
04463 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
04464 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
04465 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
04466 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
04467 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
04468 
04469 /* Register: PPI_CHG */
04470 /* Description: Channel group configuration. */
04471 
04472 /* Bit 31 : Include CH31 in channel group. */
04473 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
04474 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
04475 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
04476 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
04477 
04478 /* Bit 30 : Include CH30 in channel group. */
04479 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
04480 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
04481 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
04482 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
04483 
04484 /* Bit 29 : Include CH29 in channel group. */
04485 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
04486 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
04487 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
04488 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
04489 
04490 /* Bit 28 : Include CH28 in channel group. */
04491 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
04492 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
04493 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
04494 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
04495 
04496 /* Bit 27 : Include CH27 in channel group. */
04497 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
04498 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
04499 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
04500 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
04501 
04502 /* Bit 26 : Include CH26 in channel group. */
04503 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
04504 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
04505 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
04506 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
04507 
04508 /* Bit 25 : Include CH25 in channel group. */
04509 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
04510 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
04511 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
04512 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
04513 
04514 /* Bit 24 : Include CH24 in channel group. */
04515 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
04516 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
04517 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
04518 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
04519 
04520 /* Bit 23 : Include CH23 in channel group. */
04521 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
04522 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
04523 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
04524 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
04525 
04526 /* Bit 22 : Include CH22 in channel group. */
04527 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
04528 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
04529 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
04530 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
04531 
04532 /* Bit 21 : Include CH21 in channel group. */
04533 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
04534 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
04535 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
04536 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
04537 
04538 /* Bit 20 : Include CH20 in channel group. */
04539 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
04540 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
04541 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
04542 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
04543 
04544 /* Bit 15 : Include CH15 in channel group. */
04545 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
04546 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
04547 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
04548 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
04549 
04550 /* Bit 14 : Include CH14 in channel group. */
04551 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
04552 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
04553 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
04554 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
04555 
04556 /* Bit 13 : Include CH13 in channel group. */
04557 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
04558 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
04559 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
04560 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
04561 
04562 /* Bit 12 : Include CH12 in channel group. */
04563 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
04564 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
04565 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
04566 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
04567 
04568 /* Bit 11 : Include CH11 in channel group. */
04569 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
04570 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
04571 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
04572 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
04573 
04574 /* Bit 10 : Include CH10 in channel group. */
04575 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
04576 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
04577 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
04578 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
04579 
04580 /* Bit 9 : Include CH9 in channel group. */
04581 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
04582 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
04583 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
04584 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
04585 
04586 /* Bit 8 : Include CH8 in channel group. */
04587 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
04588 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
04589 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
04590 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
04591 
04592 /* Bit 7 : Include CH7 in channel group. */
04593 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
04594 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
04595 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
04596 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
04597 
04598 /* Bit 6 : Include CH6 in channel group. */
04599 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
04600 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
04601 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
04602 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
04603 
04604 /* Bit 5 : Include CH5 in channel group. */
04605 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
04606 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
04607 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
04608 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
04609 
04610 /* Bit 4 : Include CH4 in channel group. */
04611 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
04612 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
04613 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
04614 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
04615 
04616 /* Bit 3 : Include CH3 in channel group. */
04617 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
04618 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
04619 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
04620 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
04621 
04622 /* Bit 2 : Include CH2 in channel group. */
04623 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
04624 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
04625 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
04626 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
04627 
04628 /* Bit 1 : Include CH1 in channel group. */
04629 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
04630 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
04631 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
04632 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
04633 
04634 /* Bit 0 : Include CH0 in channel group. */
04635 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
04636 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
04637 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
04638 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
04639 
04640 
04641 /* Peripheral: PU */
04642 /* Description: Patch unit. */
04643 
04644 /* Register: PU_PATCHADDR */
04645 /* Description: Relative address of patch instructions. */
04646 
04647 /* Bits 24..0 : Relative address of patch instructions. */
04648 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
04649 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
04650 
04651 /* Register: PU_PATCHEN */
04652 /* Description: Patch enable register. */
04653 
04654 /* Bit 7 : Patch 7 enabled. */
04655 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
04656 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
04657 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
04658 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
04659 
04660 /* Bit 6 : Patch 6 enabled. */
04661 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
04662 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
04663 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
04664 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
04665 
04666 /* Bit 5 : Patch 5 enabled. */
04667 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
04668 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
04669 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
04670 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
04671 
04672 /* Bit 4 : Patch 4 enabled. */
04673 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
04674 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
04675 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
04676 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
04677 
04678 /* Bit 3 : Patch 3 enabled. */
04679 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
04680 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
04681 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
04682 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
04683 
04684 /* Bit 2 : Patch 2 enabled. */
04685 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
04686 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
04687 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
04688 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
04689 
04690 /* Bit 1 : Patch 1 enabled. */
04691 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
04692 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
04693 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
04694 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
04695 
04696 /* Bit 0 : Patch 0 enabled. */
04697 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
04698 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
04699 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
04700 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
04701 
04702 /* Register: PU_PATCHENSET */
04703 /* Description: Patch enable register. */
04704 
04705 /* Bit 7 : Patch 7 enabled. */
04706 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
04707 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
04708 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
04709 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
04710 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
04711 
04712 /* Bit 6 : Patch 6 enabled. */
04713 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
04714 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
04715 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
04716 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
04717 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
04718 
04719 /* Bit 5 : Patch 5 enabled. */
04720 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
04721 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
04722 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
04723 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
04724 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
04725 
04726 /* Bit 4 : Patch 4 enabled. */
04727 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
04728 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
04729 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
04730 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
04731 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
04732 
04733 /* Bit 3 : Patch 3 enabled. */
04734 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
04735 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
04736 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
04737 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
04738 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
04739 
04740 /* Bit 2 : Patch 2 enabled. */
04741 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
04742 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
04743 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
04744 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
04745 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
04746 
04747 /* Bit 1 : Patch 1 enabled. */
04748 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
04749 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
04750 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
04751 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
04752 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
04753 
04754 /* Bit 0 : Patch 0 enabled. */
04755 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
04756 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
04757 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
04758 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
04759 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
04760 
04761 /* Register: PU_PATCHENCLR */
04762 /* Description: Patch disable register. */
04763 
04764 /* Bit 7 : Patch 7 enabled. */
04765 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
04766 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
04767 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
04768 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
04769 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
04770 
04771 /* Bit 6 : Patch 6 enabled. */
04772 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
04773 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
04774 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
04775 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
04776 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
04777 
04778 /* Bit 5 : Patch 5 enabled. */
04779 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
04780 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
04781 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
04782 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
04783 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
04784 
04785 /* Bit 4 : Patch 4 enabled. */
04786 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
04787 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
04788 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
04789 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
04790 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
04791 
04792 /* Bit 3 : Patch 3 enabled. */
04793 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
04794 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
04795 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
04796 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
04797 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
04798 
04799 /* Bit 2 : Patch 2 enabled. */
04800 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
04801 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
04802 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
04803 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
04804 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
04805 
04806 /* Bit 1 : Patch 1 enabled. */
04807 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
04808 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
04809 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
04810 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
04811 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
04812 
04813 /* Bit 0 : Patch 0 enabled. */
04814 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
04815 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
04816 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
04817 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
04818 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
04819 
04820 
04821 /* Peripheral: QDEC */
04822 /* Description: Rotary decoder. */
04823 
04824 /* Register: QDEC_SHORTS */
04825 /* Description: Shortcuts for the QDEC. */
04826 
04827 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
04828 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
04829 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
04830 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
04831 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
04832 
04833 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
04834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
04835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
04836 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
04837 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
04838 
04839 /* Register: QDEC_INTENSET */
04840 /* Description: Interrupt enable set register. */
04841 
04842 /* Bit 2 : Enable interrupt on ACCOF event. */
04843 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
04844 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
04845 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
04846 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
04847 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
04848 
04849 /* Bit 1 : Enable interrupt on REPORTRDY event. */
04850 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
04851 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
04852 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
04853 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
04854 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
04855 
04856 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
04857 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
04858 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
04859 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
04860 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
04861 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
04862 
04863 /* Register: QDEC_INTENCLR */
04864 /* Description: Interrupt enable clear register. */
04865 
04866 /* Bit 2 : Disable interrupt on ACCOF event. */
04867 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
04868 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
04869 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
04870 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
04871 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
04872 
04873 /* Bit 1 : Disable interrupt on REPORTRDY event. */
04874 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
04875 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
04876 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
04877 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
04878 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
04879 
04880 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
04881 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
04882 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
04883 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
04884 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
04885 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
04886 
04887 /* Register: QDEC_ENABLE */
04888 /* Description: Enable the QDEC. */
04889 
04890 /* Bit 0 : Enable or disable QDEC. */
04891 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
04892 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
04893 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
04894 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
04895 
04896 /* Register: QDEC_LEDPOL */
04897 /* Description: LED output pin polarity. */
04898 
04899 /* Bit 0 : LED output pin polarity. */
04900 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
04901 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
04902 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
04903 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
04904 
04905 /* Register: QDEC_SAMPLEPER */
04906 /* Description: Sample period. */
04907 
04908 /* Bits 2..0 : Sample period. */
04909 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
04910 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
04911 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
04912 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
04913 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
04914 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
04915 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
04916 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
04917 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
04918 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
04919 
04920 /* Register: QDEC_SAMPLE */
04921 /* Description: Motion sample value. */
04922 
04923 /* Bits 31..0 : Last sample taken in compliment to 2. */
04924 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
04925 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
04926 
04927 /* Register: QDEC_REPORTPER */
04928 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
04929 
04930 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
04931 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
04932 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
04933 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
04934 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
04935 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
04936 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
04937 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
04938 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
04939 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
04940 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
04941 
04942 /* Register: QDEC_DBFEN */
04943 /* Description: Enable debouncer input filters. */
04944 
04945 /* Bit 0 : Enable debounce input filters. */
04946 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
04947 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
04948 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
04949 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
04950 
04951 /* Register: QDEC_LEDPRE */
04952 /* Description: Time LED is switched ON before the sample. */
04953 
04954 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
04955 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
04956 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
04957 
04958 /* Register: QDEC_ACCDBL */
04959 /* Description: Accumulated double (error) transitions register. */
04960 
04961 /* Bits 3..0 : Accumulated double (error) transitions. */
04962 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
04963 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
04964 
04965 /* Register: QDEC_ACCDBLREAD */
04966 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
04967 
04968 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
04969 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
04970 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
04971 
04972 /* Register: QDEC_POWER */
04973 /* Description: Peripheral power control. */
04974 
04975 /* Bit 0 : Peripheral power control. */
04976 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
04977 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
04978 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
04979 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
04980 
04981 
04982 /* Peripheral: RADIO */
04983 /* Description: The radio. */
04984 
04985 /* Register: RADIO_SHORTS */
04986 /* Description: Shortcuts for the radio. */
04987 
04988 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
04989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
04990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
04991 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
04992 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
04993 
04994 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
04995 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
04996 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
04997 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
04998 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
04999 
05000 /* Bit 5 : Shortcut between END event and START task. */
05001 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
05002 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
05003 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
05004 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
05005 
05006 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
05007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
05008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
05009 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
05010 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
05011 
05012 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
05013 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
05014 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
05015 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
05016 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
05017 
05018 /* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
05019 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
05020 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
05021 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
05022 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
05023 
05024 /* Bit 1 : Shortcut between END event and DISABLE task. */
05025 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
05026 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
05027 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
05028 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
05029 
05030 /* Bit 0 : Shortcut between READY event and START task. */
05031 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
05032 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
05033 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
05034 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
05035 
05036 /* Register: RADIO_INTENSET */
05037 /* Description: Interrupt enable set register. */
05038 
05039 /* Bit 10 : Enable interrupt on BCMATCH event. */
05040 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
05041 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
05042 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
05043 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
05044 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
05045 
05046 /* Bit 7 : Enable interrupt on RSSIEND event. */
05047 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
05048 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
05049 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
05050 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
05051 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
05052 
05053 /* Bit 6 : Enable interrupt on DEVMISS event. */
05054 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
05055 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
05056 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
05057 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
05058 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
05059 
05060 /* Bit 5 : Enable interrupt on DEVMATCH event. */
05061 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
05062 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
05063 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
05064 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
05065 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
05066 
05067 /* Bit 4 : Enable interrupt on DISABLED event. */
05068 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
05069 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
05070 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
05071 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
05072 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
05073 
05074 /* Bit 3 : Enable interrupt on END event. */
05075 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
05076 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
05077 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
05078 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
05079 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
05080 
05081 /* Bit 2 : Enable interrupt on PAYLOAD event. */
05082 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
05083 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
05084 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
05085 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
05086 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
05087 
05088 /* Bit 1 : Enable interrupt on ADDRESS event. */
05089 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
05090 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
05091 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
05092 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
05093 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
05094 
05095 /* Bit 0 : Enable interrupt on READY event. */
05096 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
05097 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
05098 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
05099 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
05100 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
05101 
05102 /* Register: RADIO_INTENCLR */
05103 /* Description: Interrupt enable clear register. */
05104 
05105 /* Bit 10 : Disable interrupt on BCMATCH event. */
05106 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
05107 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
05108 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
05109 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
05110 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
05111 
05112 /* Bit 7 : Disable interrupt on RSSIEND event. */
05113 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
05114 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
05115 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
05116 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
05117 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
05118 
05119 /* Bit 6 : Disable interrupt on DEVMISS event. */
05120 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
05121 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
05122 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
05123 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
05124 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
05125 
05126 /* Bit 5 : Disable interrupt on DEVMATCH event. */
05127 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
05128 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
05129 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
05130 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
05131 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
05132 
05133 /* Bit 4 : Disable interrupt on DISABLED event. */
05134 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
05135 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
05136 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
05137 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
05138 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
05139 
05140 /* Bit 3 : Disable interrupt on END event. */
05141 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
05142 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
05143 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
05144 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
05145 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
05146 
05147 /* Bit 2 : Disable interrupt on PAYLOAD event. */
05148 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
05149 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
05150 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
05151 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
05152 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
05153 
05154 /* Bit 1 : Disable interrupt on ADDRESS event. */
05155 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
05156 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
05157 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
05158 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
05159 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
05160 
05161 /* Bit 0 : Disable interrupt on READY event. */
05162 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
05163 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
05164 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
05165 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
05166 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
05167 
05168 /* Register: RADIO_CRCSTATUS */
05169 /* Description: CRC status of received packet. */
05170 
05171 /* Bit 0 : CRC status of received packet. */
05172 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
05173 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
05174 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
05175 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
05176 
05177 /* Register: RADIO_CD */
05178 /* Description: Carrier detect. */
05179 
05180 /* Bit 0 : Carrier detect. */
05181 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
05182 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
05183 
05184 /* Register: RADIO_RXMATCH */
05185 /* Description: Received address. */
05186 
05187 /* Bits 2..0 : Logical address in which previous packet was received. */
05188 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
05189 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
05190 
05191 /* Register: RADIO_RXCRC */
05192 /* Description: Received CRC. */
05193 
05194 /* Bits 23..0 : CRC field of previously received packet. */
05195 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
05196 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
05197 
05198 /* Register: RADIO_DAI */
05199 /* Description: Device address match index. */
05200 
05201 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
05202 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
05203 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
05204 
05205 /* Register: RADIO_FREQUENCY */
05206 /* Description: Frequency. */
05207 
05208 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
05209 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
05210 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
05211 
05212 /* Register: RADIO_TXPOWER */
05213 /* Description: Output power. */
05214 
05215 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
05216 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
05217 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
05218 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
05219 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
05220 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
05221 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
05222 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
05223 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
05224 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
05225 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
05226 
05227 /* Register: RADIO_MODE */
05228 /* Description: Data rate and modulation. */
05229 
05230 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
05231 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
05232 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
05233 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
05234 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
05235 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
05236 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
05237 
05238 /* Register: RADIO_PCNF0 */
05239 /* Description: Packet configuration 0. */
05240 
05241 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
05242 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
05243 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
05244 
05245 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
05246 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
05247 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
05248 
05249 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
05250 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
05251 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
05252 
05253 /* Register: RADIO_PCNF1 */
05254 /* Description: Packet configuration 1. */
05255 
05256 /* Bit 25 : Packet whitening enable. */
05257 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
05258 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
05259 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
05260 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
05261 
05262 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
05263 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
05264 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
05265 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
05266 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
05267 
05268 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
05269 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
05270 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
05271 
05272 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
05273 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
05274 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
05275 
05276 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
05277 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
05278 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
05279 
05280 /* Register: RADIO_PREFIX0 */
05281 /* Description: Prefixes bytes for logical addresses 0 to 3. */
05282 
05283 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
05284 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
05285 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
05286 
05287 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
05288 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
05289 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
05290 
05291 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
05292 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
05293 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
05294 
05295 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
05296 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
05297 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
05298 
05299 /* Register: RADIO_PREFIX1 */
05300 /* Description: Prefixes bytes for logical addresses 4 to 7. */
05301 
05302 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
05303 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
05304 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
05305 
05306 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
05307 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
05308 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
05309 
05310 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
05311 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
05312 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
05313 
05314 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
05315 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
05316 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
05317 
05318 /* Register: RADIO_TXADDRESS */
05319 /* Description: Transmit address select. */
05320 
05321 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
05322 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
05323 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
05324 
05325 /* Register: RADIO_RXADDRESSES */
05326 /* Description: Receive address select. */
05327 
05328 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
05329 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
05330 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
05331 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
05332 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
05333 
05334 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
05335 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
05336 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
05337 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
05338 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
05339 
05340 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
05341 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
05342 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
05343 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
05344 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
05345 
05346 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
05347 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
05348 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
05349 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
05350 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
05351 
05352 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
05353 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
05354 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
05355 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
05356 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
05357 
05358 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
05359 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
05360 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
05361 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
05362 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
05363 
05364 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
05365 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
05366 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
05367 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
05368 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
05369 
05370 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
05371 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
05372 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
05373 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
05374 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
05375 
05376 /* Register: RADIO_CRCCNF */
05377 /* Description: CRC configuration. */
05378 
05379 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
05380 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
05381 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
05382 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
05383 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
05384 
05385 /* Bits 1..0 : CRC length. Decision point: START task. */
05386 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
05387 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
05388 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
05389 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
05390 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
05391 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
05392 
05393 /* Register: RADIO_CRCPOLY */
05394 /* Description: CRC polynomial. */
05395 
05396 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
05397 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
05398 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
05399 
05400 /* Register: RADIO_CRCINIT */
05401 /* Description: CRC initial value. */
05402 
05403 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
05404 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
05405 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
05406 
05407 /* Register: RADIO_TEST */
05408 /* Description: Test features enable register. */
05409 
05410 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
05411 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
05412 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
05413 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
05414 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
05415 
05416 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
05417 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
05418 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
05419 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
05420 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
05421 
05422 /* Register: RADIO_TIFS */
05423 /* Description: Inter Frame Spacing in microseconds. */
05424 
05425 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
05426 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
05427 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
05428 
05429 /* Register: RADIO_RSSISAMPLE */
05430 /* Description: RSSI sample. */
05431 
05432 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
05433 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
05434 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
05435 
05436 /* Register: RADIO_STATE */
05437 /* Description: Current radio state. */
05438 
05439 /* Bits 3..0 : Current radio state. */
05440 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
05441 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
05442 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
05443 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
05444 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
05445 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
05446 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
05447 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
05448 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
05449 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
05450 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
05451 
05452 /* Register: RADIO_DATAWHITEIV */
05453 /* Description: Data whitening initial value. */
05454 
05455 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
05456 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
05457 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
05458 
05459 /* Register: RADIO_DAP */
05460 /* Description: Device address prefix. */
05461 
05462 /* Bits 15..0 : Device address prefix. */
05463 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
05464 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
05465 
05466 /* Register: RADIO_DACNF */
05467 /* Description: Device address match configuration. */
05468 
05469 /* Bit 15 : TxAdd for device address 7. */
05470 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
05471 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
05472 
05473 /* Bit 14 : TxAdd for device address 6. */
05474 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
05475 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
05476 
05477 /* Bit 13 : TxAdd for device address 5. */
05478 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
05479 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
05480 
05481 /* Bit 12 : TxAdd for device address 4. */
05482 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
05483 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
05484 
05485 /* Bit 11 : TxAdd for device address 3. */
05486 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
05487 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
05488 
05489 /* Bit 10 : TxAdd for device address 2. */
05490 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
05491 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
05492 
05493 /* Bit 9 : TxAdd for device address 1. */
05494 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
05495 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
05496 
05497 /* Bit 8 : TxAdd for device address 0. */
05498 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
05499 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
05500 
05501 /* Bit 7 : Enable or disable device address matching using device address 7. */
05502 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
05503 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
05504 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
05505 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
05506 
05507 /* Bit 6 : Enable or disable device address matching using device address 6. */
05508 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
05509 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
05510 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
05511 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
05512 
05513 /* Bit 5 : Enable or disable device address matching using device address 5. */
05514 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
05515 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
05516 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
05517 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
05518 
05519 /* Bit 4 : Enable or disable device address matching using device address 4. */
05520 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
05521 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
05522 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
05523 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
05524 
05525 /* Bit 3 : Enable or disable device address matching using device address 3. */
05526 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
05527 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
05528 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
05529 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
05530 
05531 /* Bit 2 : Enable or disable device address matching using device address 2. */
05532 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
05533 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
05534 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
05535 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
05536 
05537 /* Bit 1 : Enable or disable device address matching using device address 1. */
05538 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
05539 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
05540 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
05541 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
05542 
05543 /* Bit 0 : Enable or disable device address matching using device address 0. */
05544 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
05545 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
05546 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
05547 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
05548 
05549 /* Register: RADIO_OVERRIDE0 */
05550 /* Description: Trim value override register 0. */
05551 
05552 /* Bits 31..0 : Trim value override 0. */
05553 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
05554 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
05555 
05556 /* Register: RADIO_OVERRIDE1 */
05557 /* Description: Trim value override register 1. */
05558 
05559 /* Bits 31..0 : Trim value override 1. */
05560 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
05561 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
05562 
05563 /* Register: RADIO_OVERRIDE2 */
05564 /* Description: Trim value override register 2. */
05565 
05566 /* Bits 31..0 : Trim value override 2. */
05567 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
05568 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
05569 
05570 /* Register: RADIO_OVERRIDE3 */
05571 /* Description: Trim value override register 3. */
05572 
05573 /* Bits 31..0 : Trim value override 3. */
05574 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
05575 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
05576 
05577 /* Register: RADIO_OVERRIDE4 */
05578 /* Description: Trim value override register 4. */
05579 
05580 /* Bit 31 : Enable or disable override of default trim values. */
05581 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
05582 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
05583 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
05584 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
05585 
05586 /* Bits 27..0 : Trim value override 4. */
05587 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
05588 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
05589 
05590 /* Register: RADIO_POWER */
05591 /* Description: Peripheral power control. */
05592 
05593 /* Bit 0 : Peripheral power control. */
05594 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
05595 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
05596 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
05597 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
05598 
05599 
05600 /* Peripheral: RNG */
05601 /* Description: Random Number Generator. */
05602 
05603 /* Register: RNG_SHORTS */
05604 /* Description: Shortcuts for the RNG. */
05605 
05606 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
05607 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
05608 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
05609 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
05610 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
05611 
05612 /* Register: RNG_INTENSET */
05613 /* Description: Interrupt enable set register */
05614 
05615 /* Bit 0 : Enable interrupt on VALRDY event. */
05616 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
05617 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
05618 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
05619 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
05620 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
05621 
05622 /* Register: RNG_INTENCLR */
05623 /* Description: Interrupt enable clear register */
05624 
05625 /* Bit 0 : Disable interrupt on VALRDY event. */
05626 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
05627 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
05628 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
05629 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
05630 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
05631 
05632 /* Register: RNG_CONFIG */
05633 /* Description: Configuration register. */
05634 
05635 /* Bit 0 : Digital error correction enable. */
05636 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
05637 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
05638 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
05639 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
05640 
05641 /* Register: RNG_VALUE */
05642 /* Description: RNG random number. */
05643 
05644 /* Bits 7..0 : Generated random number. */
05645 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
05646 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
05647 
05648 /* Register: RNG_POWER */
05649 /* Description: Peripheral power control. */
05650 
05651 /* Bit 0 : Peripheral power control. */
05652 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
05653 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
05654 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
05655 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
05656 
05657 
05658 /* Peripheral: RTC */
05659 /* Description: Real time counter 0. */
05660 
05661 /* Register: RTC_INTENSET */
05662 /* Description: Interrupt enable set register. */
05663 
05664 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
05665 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
05666 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
05667 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
05668 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
05669 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
05670 
05671 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
05672 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
05673 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
05674 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
05675 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
05676 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
05677 
05678 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
05679 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
05680 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
05681 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
05682 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
05683 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
05684 
05685 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
05686 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
05687 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
05688 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
05689 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
05690 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
05691 
05692 /* Bit 1 : Enable interrupt on OVRFLW event. */
05693 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
05694 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
05695 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
05696 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
05697 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
05698 
05699 /* Bit 0 : Enable interrupt on TICK event. */
05700 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
05701 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
05702 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
05703 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
05704 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
05705 
05706 /* Register: RTC_INTENCLR */
05707 /* Description: Interrupt enable clear register. */
05708 
05709 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
05710 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
05711 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
05712 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
05713 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
05714 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
05715 
05716 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
05717 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
05718 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
05719 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
05720 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
05721 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
05722 
05723 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
05724 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
05725 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
05726 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
05727 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
05728 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
05729 
05730 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
05731 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
05732 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
05733 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
05734 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
05735 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
05736 
05737 /* Bit 1 : Disable interrupt on OVRFLW event. */
05738 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
05739 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
05740 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
05741 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
05742 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
05743 
05744 /* Bit 0 : Disable interrupt on TICK event. */
05745 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
05746 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
05747 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
05748 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
05749 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
05750 
05751 /* Register: RTC_EVTEN */
05752 /* Description: Configures event enable routing to PPI for each RTC event. */
05753 
05754 /* Bit 19 : COMPARE[3] event enable. */
05755 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
05756 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
05757 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
05758 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
05759 
05760 /* Bit 18 : COMPARE[2] event enable. */
05761 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
05762 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
05763 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
05764 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
05765 
05766 /* Bit 17 : COMPARE[1] event enable. */
05767 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
05768 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
05769 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
05770 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
05771 
05772 /* Bit 16 : COMPARE[0] event enable. */
05773 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
05774 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
05775 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
05776 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
05777 
05778 /* Bit 1 : OVRFLW event enable. */
05779 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
05780 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
05781 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
05782 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
05783 
05784 /* Bit 0 : TICK event enable. */
05785 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
05786 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
05787 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
05788 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
05789 
05790 /* Register: RTC_EVTENSET */
05791 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
05792 
05793 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
05794 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
05795 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
05796 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
05797 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
05798 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
05799 
05800 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
05801 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
05802 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
05803 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
05804 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
05805 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
05806 
05807 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
05808 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
05809 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
05810 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
05811 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
05812 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
05813 
05814 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
05815 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
05816 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
05817 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
05818 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
05819 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
05820 
05821 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
05822 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
05823 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
05824 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
05825 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
05826 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
05827 
05828 /* Bit 0 : Enable routing to PPI of TICK event. */
05829 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
05830 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
05831 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
05832 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
05833 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
05834 
05835 /* Register: RTC_EVTENCLR */
05836 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
05837 
05838 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
05839 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
05840 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
05841 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
05842 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
05843 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
05844 
05845 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
05846 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
05847 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
05848 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
05849 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
05850 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
05851 
05852 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
05853 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
05854 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
05855 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
05856 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
05857 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
05858 
05859 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
05860 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
05861 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
05862 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
05863 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
05864 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
05865 
05866 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
05867 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
05868 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
05869 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
05870 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
05871 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
05872 
05873 /* Bit 0 : Disable routing to PPI of TICK event. */
05874 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
05875 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
05876 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
05877 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
05878 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
05879 
05880 /* Register: RTC_COUNTER */
05881 /* Description: Current COUNTER value. */
05882 
05883 /* Bits 23..0 : Counter value. */
05884 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
05885 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
05886 
05887 /* Register: RTC_PRESCALER */
05888 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
05889 
05890 /* Bits 11..0 : RTC PRESCALER value. */
05891 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
05892 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
05893 
05894 /* Register: RTC_CC */
05895 /* Description: Capture/compare registers. */
05896 
05897 /* Bits 23..0 : Compare value. */
05898 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
05899 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
05900 
05901 /* Register: RTC_POWER */
05902 /* Description: Peripheral power control. */
05903 
05904 /* Bit 0 : Peripheral power control. */
05905 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
05906 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
05907 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
05908 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
05909 
05910 
05911 /* Peripheral: SPI */
05912 /* Description: SPI master 0. */
05913 
05914 /* Register: SPI_INTENSET */
05915 /* Description: Interrupt enable set register. */
05916 
05917 /* Bit 2 : Enable interrupt on READY event. */
05918 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
05919 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
05920 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
05921 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
05922 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
05923 
05924 /* Register: SPI_INTENCLR */
05925 /* Description: Interrupt enable clear register. */
05926 
05927 /* Bit 2 : Disable interrupt on READY event. */
05928 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
05929 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
05930 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
05931 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
05932 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
05933 
05934 /* Register: SPI_ENABLE */
05935 /* Description: Enable SPI. */
05936 
05937 /* Bits 2..0 : Enable or disable SPI. */
05938 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
05939 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
05940 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
05941 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
05942 
05943 /* Register: SPI_RXD */
05944 /* Description: RX data. */
05945 
05946 /* Bits 7..0 : RX data from last transfer. */
05947 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
05948 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
05949 
05950 /* Register: SPI_TXD */
05951 /* Description: TX data. */
05952 
05953 /* Bits 7..0 : TX data for next transfer. */
05954 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
05955 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
05956 
05957 /* Register: SPI_FREQUENCY */
05958 /* Description: SPI frequency */
05959 
05960 /* Bits 31..0 : SPI data rate. */
05961 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
05962 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
05963 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
05964 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
05965 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
05966 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
05967 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
05968 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
05969 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
05970 
05971 /* Register: SPI_CONFIG */
05972 /* Description: Configuration register. */
05973 
05974 /* Bit 2 : Serial clock (SCK) polarity. */
05975 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
05976 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
05977 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
05978 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
05979 
05980 /* Bit 1 : Serial clock (SCK) phase. */
05981 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
05982 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
05983 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
05984 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
05985 
05986 /* Bit 0 : Bit order. */
05987 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
05988 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
05989 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
05990 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
05991 
05992 /* Register: SPI_POWER */
05993 /* Description: Peripheral power control. */
05994 
05995 /* Bit 0 : Peripheral power control. */
05996 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
05997 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
05998 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
05999 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06000 
06001 
06002 /* Peripheral: SPIM */
06003 /* Description: SPI master with easyDMA 1. */
06004 
06005 /* Register: SPIM_SHORTS */
06006 /* Description: Shortcuts for SPIM. */
06007 
06008 /* Bit 17 : Shortcut between END event and START task. */
06009 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
06010 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
06011 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
06012 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
06013 
06014 /* Register: SPIM_INTENSET */
06015 /* Description: Interrupt enable set register. */
06016 
06017 /* Bit 19 : Enable interrupt on STARTED event. */
06018 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
06019 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
06020 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
06021 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
06022 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
06023 
06024 /* Bit 8 : Enable interrupt on ENDTX event. */
06025 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
06026 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
06027 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
06028 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
06029 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
06030 
06031 /* Bit 6 : Enable interrupt on END event. */
06032 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
06033 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
06034 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
06035 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
06036 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
06037 
06038 /* Bit 4 : Enable interrupt on ENDRX event. */
06039 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
06040 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
06041 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
06042 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
06043 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
06044 
06045 /* Bit 1 : Enable interrupt on STOPPED event. */
06046 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
06047 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
06048 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
06049 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
06050 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
06051 
06052 /* Register: SPIM_INTENCLR */
06053 /* Description: Interrupt enable clear register. */
06054 
06055 /* Bit 19 : Disable interrupt on STARTED event. */
06056 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
06057 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
06058 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
06059 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
06060 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
06061 
06062 /* Bit 8 : Disable interrupt on ENDTX event. */
06063 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
06064 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
06065 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
06066 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
06067 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
06068 
06069 /* Bit 6 : Disable interrupt on END event. */
06070 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
06071 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
06072 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
06073 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
06074 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
06075 
06076 /* Bit 4 : Disable interrupt on ENDRX event. */
06077 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
06078 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
06079 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
06080 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
06081 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
06082 
06083 /* Bit 1 : Disable interrupt on STOPPED event. */
06084 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
06085 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
06086 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
06087 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
06088 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
06089 
06090 /* Register: SPIM_ENABLE */
06091 /* Description: Enable SPIM. */
06092 
06093 /* Bits 3..0 : Enable or disable SPIM. */
06094 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
06095 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
06096 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
06097 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
06098 
06099 /* Register: SPIM_RXDDATA */
06100 /* Description: RXD register. */
06101 
06102 /* Bits 7..0 : RX data received. Double buffered. */
06103 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */
06104 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */
06105 
06106 /* Register: SPIM_TXDDATA */
06107 /* Description: TXD register. */
06108 
06109 /* Bits 7..0 : TX data to send. Double buffered. */
06110 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */
06111 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */
06112 
06113 /* Register: SPIM_FREQUENCY */
06114 /* Description: SPI frequency. */
06115 
06116 /* Bits 31..0 : SPI master data rate. */
06117 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
06118 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
06119 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
06120 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
06121 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
06122 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
06123 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
06124 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
06125 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
06126 
06127 /* Register: SPIM_CONFIG */
06128 /* Description: Configuration register. */
06129 
06130 /* Bit 2 : Serial clock (SCK) polarity. */
06131 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
06132 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
06133 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
06134 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
06135 
06136 /* Bit 1 : Serial clock (SCK) phase. */
06137 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
06138 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
06139 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
06140 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
06141 
06142 /* Bit 0 : Bit order. */
06143 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
06144 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
06145 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
06146 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
06147 
06148 /* Register: SPIM_ORC */
06149 /* Description: Over-read character. */
06150 
06151 /* Bits 7..0 : Over-read character. */
06152 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
06153 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
06154 
06155 /* Register: SPIM_POWER */
06156 /* Description: Peripheral power control. */
06157 
06158 /* Bit 0 : Peripheral power control. */
06159 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06160 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06161 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06162 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06163 
06164 /* Register: SPIM_RXD_PTR */
06165 /* Description: Data pointer. */
06166 
06167 /* Bits 31..0 : Data pointer. */
06168 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
06169 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
06170 
06171 /* Register: SPIM_RXD_MAXCNT */
06172 /* Description: Maximum number of buffer bytes to receive. */
06173 
06174 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
06175 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
06176 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
06177 
06178 /* Register: SPIM_RXD_AMOUNT */
06179 /* Description: Number of bytes received in the last transaction. */
06180 
06181 /* Bits 7..0 : Number of bytes received in the last transaction. */
06182 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
06183 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
06184 
06185 /* Register: SPIM_TXD_PTR */
06186 /* Description: Data pointer. */
06187 
06188 /* Bits 31..0 : Data pointer. */
06189 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
06190 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
06191 
06192 /* Register: SPIM_TXD_MAXCNT */
06193 /* Description: Maximum number of buffer bytes to send. */
06194 
06195 /* Bits 7..0 : Maximum number of buffer bytes to send. */
06196 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
06197 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
06198 
06199 /* Register: SPIM_TXD_AMOUNT */
06200 /* Description: Number of bytes sent in the last transaction. */
06201 
06202 /* Bits 7..0 : Number of bytes sent in the last transaction. */
06203 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
06204 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
06205 
06206 
06207 /* Peripheral: SPIS */
06208 /* Description: SPI slave 1. */
06209 
06210 /* Register: SPIS_SHORTS */
06211 /* Description: Shortcuts for SPIS. */
06212 
06213 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
06214 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
06215 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
06216 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
06217 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
06218 
06219 /* Register: SPIS_INTENSET */
06220 /* Description: Interrupt enable set register. */
06221 
06222 /* Bit 10 : Enable interrupt on ACQUIRED event. */
06223 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
06224 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
06225 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
06226 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
06227 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
06228 
06229 /* Bit 1 : Enable interrupt on END event. */
06230 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
06231 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
06232 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
06233 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
06234 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
06235 
06236 /* Register: SPIS_INTENCLR */
06237 /* Description: Interrupt enable clear register. */
06238 
06239 /* Bit 10 : Disable interrupt on ACQUIRED event. */
06240 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
06241 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
06242 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
06243 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
06244 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
06245 
06246 /* Bit 1 : Disable interrupt on END event. */
06247 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
06248 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
06249 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
06250 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
06251 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
06252 
06253 /* Register: SPIS_SEMSTAT */
06254 /* Description: Semaphore status. */
06255 
06256 /* Bits 1..0 : Semaphore status. */
06257 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
06258 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
06259 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
06260 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
06261 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
06262 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
06263 
06264 /* Register: SPIS_STATUS */
06265 /* Description: Status from last transaction. */
06266 
06267 /* Bit 1 : RX buffer overflow detected, and prevented. */
06268 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
06269 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
06270 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
06271 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
06272 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
06273 
06274 /* Bit 0 : TX buffer overread detected, and prevented. */
06275 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
06276 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
06277 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
06278 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
06279 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
06280 
06281 /* Register: SPIS_ENABLE */
06282 /* Description: Enable SPIS. */
06283 
06284 /* Bits 2..0 : Enable or disable SPIS. */
06285 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
06286 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
06287 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
06288 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
06289 
06290 /* Register: SPIS_MAXRX */
06291 /* Description: Maximum number of bytes in the receive buffer. */
06292 
06293 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
06294 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
06295 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
06296 
06297 /* Register: SPIS_AMOUNTRX */
06298 /* Description: Number of bytes received in last granted transaction. */
06299 
06300 /* Bits 7..0 : Number of bytes received in last granted transaction. */
06301 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
06302 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
06303 
06304 /* Register: SPIS_MAXTX */
06305 /* Description: Maximum number of bytes in the transmit buffer. */
06306 
06307 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
06308 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
06309 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
06310 
06311 /* Register: SPIS_AMOUNTTX */
06312 /* Description: Number of bytes transmitted in last granted transaction. */
06313 
06314 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
06315 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
06316 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
06317 
06318 /* Register: SPIS_CONFIG */
06319 /* Description: Configuration register. */
06320 
06321 /* Bit 2 : Serial clock (SCK) polarity. */
06322 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
06323 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
06324 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
06325 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
06326 
06327 /* Bit 1 : Serial clock (SCK) phase. */
06328 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
06329 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
06330 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
06331 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
06332 
06333 /* Bit 0 : Bit order. */
06334 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
06335 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
06336 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
06337 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
06338 
06339 /* Register: SPIS_DEF */
06340 /* Description: Default character. */
06341 
06342 /* Bits 7..0 : Default character. */
06343 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
06344 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
06345 
06346 /* Register: SPIS_ORC */
06347 /* Description: Over-read character. */
06348 
06349 /* Bits 7..0 : Over-read character. */
06350 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
06351 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
06352 
06353 /* Register: SPIS_POWER */
06354 /* Description: Peripheral power control. */
06355 
06356 /* Bit 0 : Peripheral power control. */
06357 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06358 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06359 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06360 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06361 
06362 
06363 /* Peripheral: TEMP */
06364 /* Description: Temperature Sensor. */
06365 
06366 /* Register: TEMP_INTENSET */
06367 /* Description: Interrupt enable set register. */
06368 
06369 /* Bit 0 : Enable interrupt on DATARDY event. */
06370 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
06371 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
06372 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
06373 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
06374 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
06375 
06376 /* Register: TEMP_INTENCLR */
06377 /* Description: Interrupt enable clear register. */
06378 
06379 /* Bit 0 : Disable interrupt on DATARDY event. */
06380 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
06381 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
06382 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
06383 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
06384 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
06385 
06386 /* Register: TEMP_POWER */
06387 /* Description: Peripheral power control. */
06388 
06389 /* Bit 0 : Peripheral power control. */
06390 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06391 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06392 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06393 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06394 
06395 
06396 /* Peripheral: TIMER */
06397 /* Description: Timer 0. */
06398 
06399 /* Register: TIMER_SHORTS */
06400 /* Description: Shortcuts for Timer. */
06401 
06402 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
06403 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
06404 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
06405 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
06406 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
06407 
06408 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
06409 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
06410 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
06411 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
06412 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
06413 
06414 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
06415 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
06416 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
06417 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
06418 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
06419 
06420 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
06421 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
06422 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
06423 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
06424 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
06425 
06426 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
06427 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
06428 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
06429 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
06430 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
06431 
06432 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
06433 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
06434 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
06435 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
06436 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
06437 
06438 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
06439 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
06440 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
06441 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
06442 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
06443 
06444 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
06445 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
06446 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
06447 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
06448 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
06449 
06450 /* Register: TIMER_INTENSET */
06451 /* Description: Interrupt enable set register. */
06452 
06453 /* Bit 19 : Enable interrupt on COMPARE[3] */
06454 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
06455 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
06456 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
06457 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
06458 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
06459 
06460 /* Bit 18 : Enable interrupt on COMPARE[2] */
06461 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
06462 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
06463 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
06464 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
06465 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
06466 
06467 /* Bit 17 : Enable interrupt on COMPARE[1] */
06468 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
06469 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
06470 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
06471 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
06472 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
06473 
06474 /* Bit 16 : Enable interrupt on COMPARE[0] */
06475 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
06476 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
06477 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
06478 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
06479 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
06480 
06481 /* Register: TIMER_INTENCLR */
06482 /* Description: Interrupt enable clear register. */
06483 
06484 /* Bit 19 : Disable interrupt on COMPARE[3] */
06485 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
06486 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
06487 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
06488 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
06489 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
06490 
06491 /* Bit 18 : Disable interrupt on COMPARE[2] */
06492 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
06493 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
06494 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
06495 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
06496 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
06497 
06498 /* Bit 17 : Disable interrupt on COMPARE[1] */
06499 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
06500 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
06501 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
06502 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
06503 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
06504 
06505 /* Bit 16 : Disable interrupt on COMPARE[0] */
06506 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
06507 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
06508 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
06509 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
06510 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
06511 
06512 /* Register: TIMER_MODE */
06513 /* Description: Timer Mode selection. */
06514 
06515 /* Bit 0 : Select Normal or Counter mode. */
06516 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
06517 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
06518 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
06519 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
06520 
06521 /* Register: TIMER_BITMODE */
06522 /* Description: Sets timer behaviour. */
06523 
06524 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
06525 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
06526 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
06527 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
06528 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
06529 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
06530 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
06531 
06532 /* Register: TIMER_PRESCALER */
06533 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
06534 
06535 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
06536 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
06537 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
06538 
06539 /* Register: TIMER_POWER */
06540 /* Description: Peripheral power control. */
06541 
06542 /* Bit 0 : Peripheral power control. */
06543 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06544 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06545 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06546 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06547 
06548 
06549 /* Peripheral: TWI */
06550 /* Description: Two-wire interface master 0. */
06551 
06552 /* Register: TWI_SHORTS */
06553 /* Description: Shortcuts for TWI. */
06554 
06555 /* Bit 1 : Shortcut between BB event and the STOP task. */
06556 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
06557 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
06558 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
06559 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
06560 
06561 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
06562 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
06563 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
06564 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
06565 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
06566 
06567 /* Register: TWI_INTENSET */
06568 /* Description: Interrupt enable set register. */
06569 
06570 /* Bit 18 : Enable interrupt on SUSPENDED event. */
06571 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
06572 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
06573 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
06574 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
06575 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
06576 
06577 /* Bit 14 : Enable interrupt on BB event. */
06578 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
06579 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
06580 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
06581 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
06582 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
06583 
06584 /* Bit 9 : Enable interrupt on ERROR event. */
06585 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
06586 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
06587 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
06588 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
06589 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
06590 
06591 /* Bit 7 : Enable interrupt on TXDSENT event. */
06592 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
06593 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
06594 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
06595 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
06596 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
06597 
06598 /* Bit 2 : Enable interrupt on READY event. */
06599 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
06600 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
06601 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
06602 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
06603 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
06604 
06605 /* Bit 1 : Enable interrupt on STOPPED event. */
06606 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
06607 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
06608 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
06609 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
06610 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
06611 
06612 /* Register: TWI_INTENCLR */
06613 /* Description: Interrupt enable clear register. */
06614 
06615 /* Bit 18 : Disable interrupt on SUSPENDED event. */
06616 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
06617 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
06618 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
06619 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
06620 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
06621 
06622 /* Bit 14 : Disable interrupt on BB event. */
06623 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
06624 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
06625 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
06626 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
06627 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
06628 
06629 /* Bit 9 : Disable interrupt on ERROR event. */
06630 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
06631 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
06632 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
06633 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
06634 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
06635 
06636 /* Bit 7 : Disable interrupt on TXDSENT event. */
06637 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
06638 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
06639 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
06640 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
06641 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
06642 
06643 /* Bit 2 : Disable interrupt on RXDREADY event. */
06644 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
06645 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
06646 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
06647 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
06648 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
06649 
06650 /* Bit 1 : Disable interrupt on STOPPED event. */
06651 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
06652 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
06653 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
06654 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
06655 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
06656 
06657 /* Register: TWI_ERRORSRC */
06658 /* Description: Two-wire error source. Write error field to 1 to clear error. */
06659 
06660 /* Bit 2 : NACK received after sending a data byte. */
06661 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
06662 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
06663 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
06664 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
06665 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
06666 
06667 /* Bit 1 : NACK received after sending the address. */
06668 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
06669 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
06670 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
06671 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
06672 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
06673 
06674 /* Register: TWI_ENABLE */
06675 /* Description: Enable two-wire master. */
06676 
06677 /* Bits 2..0 : Enable or disable W2M */
06678 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
06679 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
06680 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
06681 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
06682 
06683 /* Register: TWI_RXD */
06684 /* Description: RX data register. */
06685 
06686 /* Bits 7..0 : RX data from last transfer. */
06687 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
06688 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
06689 
06690 /* Register: TWI_TXD */
06691 /* Description: TX data register. */
06692 
06693 /* Bits 7..0 : TX data for next transfer. */
06694 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
06695 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
06696 
06697 /* Register: TWI_FREQUENCY */
06698 /* Description: Two-wire frequency. */
06699 
06700 /* Bits 31..0 : Two-wire master clock frequency. */
06701 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
06702 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
06703 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
06704 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
06705 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
06706 
06707 /* Register: TWI_ADDRESS */
06708 /* Description: Address used in the two-wire transfer. */
06709 
06710 /* Bits 6..0 : Two-wire address. */
06711 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
06712 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
06713 
06714 /* Register: TWI_POWER */
06715 /* Description: Peripheral power control. */
06716 
06717 /* Bit 0 : Peripheral power control. */
06718 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06719 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06720 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06721 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06722 
06723 
06724 /* Peripheral: UART */
06725 /* Description: Universal Asynchronous Receiver/Transmitter. */
06726 
06727 /* Register: UART_SHORTS */
06728 /* Description: Shortcuts for UART. */
06729 
06730 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
06731 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
06732 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
06733 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
06734 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
06735 
06736 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
06737 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
06738 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
06739 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
06740 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
06741 
06742 /* Register: UART_INTENSET */
06743 /* Description: Interrupt enable set register. */
06744 
06745 /* Bit 17 : Enable interrupt on RXTO event. */
06746 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
06747 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
06748 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
06749 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
06750 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
06751 
06752 /* Bit 9 : Enable interrupt on ERROR event. */
06753 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
06754 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
06755 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
06756 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
06757 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
06758 
06759 /* Bit 7 : Enable interrupt on TXRDY event. */
06760 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
06761 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
06762 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
06763 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
06764 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
06765 
06766 /* Bit 2 : Enable interrupt on RXRDY event. */
06767 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
06768 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
06769 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
06770 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
06771 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
06772 
06773 /* Bit 1 : Enable interrupt on NCTS event. */
06774 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
06775 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
06776 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
06777 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
06778 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
06779 
06780 /* Bit 0 : Enable interrupt on CTS event. */
06781 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
06782 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
06783 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
06784 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
06785 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
06786 
06787 /* Register: UART_INTENCLR */
06788 /* Description: Interrupt enable clear register. */
06789 
06790 /* Bit 17 : Disable interrupt on RXTO event. */
06791 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
06792 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
06793 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
06794 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
06795 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
06796 
06797 /* Bit 9 : Disable interrupt on ERROR event. */
06798 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
06799 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
06800 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
06801 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
06802 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
06803 
06804 /* Bit 7 : Disable interrupt on TXRDY event. */
06805 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
06806 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
06807 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
06808 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
06809 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
06810 
06811 /* Bit 2 : Disable interrupt on RXRDY event. */
06812 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
06813 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
06814 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
06815 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
06816 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
06817 
06818 /* Bit 1 : Disable interrupt on NCTS event. */
06819 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
06820 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
06821 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
06822 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
06823 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
06824 
06825 /* Bit 0 : Disable interrupt on CTS event. */
06826 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
06827 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
06828 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
06829 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
06830 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
06831 
06832 /* Register: UART_ERRORSRC */
06833 /* Description: Error source. Write error field to 1 to clear error. */
06834 
06835 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
06836 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
06837 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
06838 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
06839 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
06840 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
06841 
06842 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
06843 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
06844 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
06845 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
06846 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
06847 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
06848 
06849 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
06850 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
06851 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
06852 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
06853 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
06854 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
06855 
06856 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
06857 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
06858 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
06859 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
06860 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
06861 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
06862 
06863 /* Register: UART_ENABLE */
06864 /* Description: Enable UART and acquire IOs. */
06865 
06866 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
06867 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
06868 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
06869 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
06870 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
06871 
06872 /* Register: UART_RXD */
06873 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
06874 
06875 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
06876 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
06877 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
06878 
06879 /* Register: UART_TXD */
06880 /* Description: TXD register. */
06881 
06882 /* Bits 7..0 : TX data for transfer. */
06883 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
06884 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
06885 
06886 /* Register: UART_BAUDRATE */
06887 /* Description: UART Baudrate. */
06888 
06889 /* Bits 31..0 : UART baudrate. */
06890 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
06891 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
06892 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
06893 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
06894 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
06895 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
06896 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
06897 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
06898 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
06899 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
06900 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
06901 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
06902 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
06903 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
06904 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
06905 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
06906 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
06907 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
06908 
06909 /* Register: UART_CONFIG */
06910 /* Description: Configuration of parity and hardware flow control register. */
06911 
06912 /* Bits 3..1 : Include parity bit. */
06913 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
06914 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
06915 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
06916 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
06917 
06918 /* Bit 0 : Hardware flow control. */
06919 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
06920 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
06921 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
06922 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
06923 
06924 /* Register: UART_POWER */
06925 /* Description: Peripheral power control. */
06926 
06927 /* Bit 0 : Peripheral power control. */
06928 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
06929 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
06930 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
06931 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
06932 
06933 
06934 /* Peripheral: UICR */
06935 /* Description: User Information Configuration. */
06936 
06937 /* Register: UICR_RBPCONF */
06938 /* Description: Readback protection configuration. */
06939 
06940 /* Bits 15..8 : Readback protect all code in the device. */
06941 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
06942 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
06943 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
06944 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
06945 
06946 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
06947 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
06948 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
06949 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
06950 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
06951 
06952 /* Register: UICR_XTALFREQ */
06953 /* Description: Reset value for CLOCK XTALFREQ register. */
06954 
06955 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
06956 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
06957 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
06958 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
06959 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
06960 
06961 /* Register: UICR_FWID */
06962 /* Description: Firmware ID. */
06963 
06964 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
06965 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
06966 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
06967 
06968 
06969 /* Peripheral: WDT */
06970 /* Description: Watchdog Timer. */
06971 
06972 /* Register: WDT_INTENSET */
06973 /* Description: Interrupt enable set register. */
06974 
06975 /* Bit 0 : Enable interrupt on TIMEOUT event. */
06976 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
06977 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
06978 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
06979 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
06980 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
06981 
06982 /* Register: WDT_INTENCLR */
06983 /* Description: Interrupt enable clear register. */
06984 
06985 /* Bit 0 : Disable interrupt on TIMEOUT event. */
06986 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
06987 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
06988 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
06989 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
06990 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
06991 
06992 /* Register: WDT_RUNSTATUS */
06993 /* Description: Watchdog running status. */
06994 
06995 /* Bit 0 : Watchdog running status. */
06996 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
06997 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
06998 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
06999 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
07000 
07001 /* Register: WDT_REQSTATUS */
07002 /* Description: Request status. */
07003 
07004 /* Bit 7 : Request status for RR[7]. */
07005 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
07006 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
07007 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
07008 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
07009 
07010 /* Bit 6 : Request status for RR[6]. */
07011 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
07012 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
07013 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
07014 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
07015 
07016 /* Bit 5 : Request status for RR[5]. */
07017 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
07018 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
07019 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
07020 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
07021 
07022 /* Bit 4 : Request status for RR[4]. */
07023 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
07024 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
07025 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
07026 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
07027 
07028 /* Bit 3 : Request status for RR[3]. */
07029 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
07030 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
07031 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
07032 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
07033 
07034 /* Bit 2 : Request status for RR[2]. */
07035 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
07036 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
07037 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
07038 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
07039 
07040 /* Bit 1 : Request status for RR[1]. */
07041 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
07042 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
07043 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
07044 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
07045 
07046 /* Bit 0 : Request status for RR[0]. */
07047 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
07048 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
07049 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
07050 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
07051 
07052 /* Register: WDT_RREN */
07053 /* Description: Reload request enable. */
07054 
07055 /* Bit 7 : Enable or disable RR[7] register. */
07056 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
07057 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
07058 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
07059 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
07060 
07061 /* Bit 6 : Enable or disable RR[6] register. */
07062 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
07063 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
07064 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
07065 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
07066 
07067 /* Bit 5 : Enable or disable RR[5] register. */
07068 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
07069 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
07070 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
07071 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
07072 
07073 /* Bit 4 : Enable or disable RR[4] register. */
07074 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
07075 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
07076 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
07077 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
07078 
07079 /* Bit 3 : Enable or disable RR[3] register. */
07080 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
07081 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
07082 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
07083 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
07084 
07085 /* Bit 2 : Enable or disable RR[2] register. */
07086 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
07087 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
07088 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
07089 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
07090 
07091 /* Bit 1 : Enable or disable RR[1] register. */
07092 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
07093 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
07094 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
07095 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
07096 
07097 /* Bit 0 : Enable or disable RR[0] register. */
07098 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
07099 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
07100 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
07101 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
07102 
07103 /* Register: WDT_CONFIG */
07104 /* Description: Configuration register. */
07105 
07106 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
07107 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
07108 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
07109 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
07110 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
07111 
07112 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
07113 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
07114 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
07115 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
07116 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
07117 
07118 /* Register: WDT_RR */
07119 /* Description: Reload requests registers. */
07120 
07121 /* Bits 31..0 : Reload register. */
07122 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
07123 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
07124 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
07125 
07126 /* Register: WDT_POWER */
07127 /* Description: Peripheral power control. */
07128 
07129 /* Bit 0 : Peripheral power control. */
07130 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
07131 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
07132 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
07133 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
07134 
07135 
07136 /*lint --flb "Leave library region" */
07137 #endif