Glimworm Beacons
test
Fork of
nRF51822
by 
Nordic Semiconductor
Embed:
(wiki syntax)
Show/hide line numbers
nrf51.h
00001 /* 00002 * Copyright (c) Nordic Semiconductor ASA 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright notice, this 00009 * list of conditions and the following disclaimer. 00010 * 00011 * 2. Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 00016 * contributors to this software may be used to endorse or promote products 00017 * derived from this software without specific prior written permission. 00018 * 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00021 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00022 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00023 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00024 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00025 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00026 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00027 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00028 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00029 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00030 * 00031 */ 00032 00033 /** @addtogroup nRF51 00034 * @{ 00035 */ 00036 00037 #ifndef NRF51_H 00038 #define NRF51_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 00045 /* ------------------------- Interrupt Number Definition ------------------------ */ 00046 00047 typedef enum { 00048 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ 00049 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00050 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 00051 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00052 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 00053 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 00054 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 00055 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 00056 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */ 00057 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 00058 RADIO_IRQn = 1, /*!< 1 RADIO */ 00059 UART0_IRQn = 2, /*!< 2 UART0 */ 00060 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 00061 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 00062 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 00063 ADC_IRQn = 7, /*!< 7 ADC */ 00064 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 00065 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 00066 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 00067 RTC0_IRQn = 11, /*!< 11 RTC0 */ 00068 TEMP_IRQn = 12, /*!< 12 TEMP */ 00069 RNG_IRQn = 13, /*!< 13 RNG */ 00070 ECB_IRQn = 14, /*!< 14 ECB */ 00071 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 00072 WDT_IRQn = 16, /*!< 16 WDT */ 00073 RTC1_IRQn = 17, /*!< 17 RTC1 */ 00074 QDEC_IRQn = 18, /*!< 18 QDEC */ 00075 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 00076 SWI0_IRQn = 20, /*!< 20 SWI0 */ 00077 SWI1_IRQn = 21, /*!< 21 SWI1 */ 00078 SWI2_IRQn = 22, /*!< 22 SWI2 */ 00079 SWI3_IRQn = 23, /*!< 23 SWI3 */ 00080 SWI4_IRQn = 24, /*!< 24 SWI4 */ 00081 SWI5_IRQn = 25 /*!< 25 SWI5 */ 00082 } IRQn_Type ; 00083 00084 00085 /** @addtogroup Configuration_of_CMSIS 00086 * @{ 00087 */ 00088 00089 00090 /* ================================================================================ */ 00091 /* ================ Processor and Core Peripheral Section ================ */ 00092 /* ================================================================================ */ 00093 00094 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ 00095 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ 00096 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00097 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 00098 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00099 /** @} */ /* End of group Configuration_of_CMSIS */ 00100 00101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ 00102 #include "system_nrf51.h" /*!< nRF51 System */ 00103 00104 00105 /* ================================================================================ */ 00106 /* ================ Device Specific Peripheral Section ================ */ 00107 /* ================================================================================ */ 00108 00109 00110 /** @addtogroup Device_Peripheral_Registers 00111 * @{ 00112 */ 00113 00114 00115 /* ------------------- Start of section using anonymous unions ------------------ */ 00116 #if defined(__CC_ARM) 00117 #pragma push 00118 #pragma anon_unions 00119 #elif defined(__ICCARM__) 00120 #pragma language=extended 00121 #elif defined(__GNUC__) 00122 /* anonymous unions are enabled by default */ 00123 #elif defined(__TMS470__) 00124 /* anonymous unions are enabled by default */ 00125 #elif defined(__TASKING__) 00126 #pragma warning 586 00127 #else 00128 #warning Not supported compiler type 00129 #endif 00130 00131 00132 typedef struct { 00133 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ 00134 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ 00135 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ 00136 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ 00137 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ 00138 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ 00139 } AMLI_RAMPRI_Type; 00140 00141 typedef struct { 00142 __IO uint32_t SCK; /*!< Pin select for SCK. */ 00143 __IO uint32_t MOSI; /*!< Pin select for MOSI. */ 00144 __IO uint32_t MISO; /*!< Pin select for MISO. */ 00145 } SPIM_PSEL_Type; 00146 00147 typedef struct { 00148 __IO uint32_t PTR; /*!< Data pointer. */ 00149 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ 00150 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ 00151 } SPIM_RXD_Type; 00152 00153 typedef struct { 00154 __IO uint32_t PTR; /*!< Data pointer. */ 00155 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ 00156 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ 00157 } SPIM_TXD_Type; 00158 00159 typedef struct { 00160 __O uint32_t EN; /*!< Enable channel group. */ 00161 __O uint32_t DIS; /*!< Disable channel group. */ 00162 } PPI_TASKS_CHG_Type; 00163 00164 typedef struct { 00165 __IO uint32_t EEP; /*!< Channel event end-point. */ 00166 __IO uint32_t TEP; /*!< Channel task end-point. */ 00167 } PPI_CH_Type; 00168 00169 typedef struct { 00170 __I uint32_t PART; /*!< Part code */ 00171 __I uint32_t VARIANT; /*!< Part variant */ 00172 __I uint32_t PACKAGE; /*!< Package option */ 00173 __I uint32_t RAM; /*!< RAM variant */ 00174 __I uint32_t FLASH; /*!< Flash variant */ 00175 __I uint32_t RESERVED[3]; /*!< Reserved */ 00176 } FICR_INFO_Type; 00177 00178 00179 /* ================================================================================ */ 00180 /* ================ POWER ================ */ 00181 /* ================================================================================ */ 00182 00183 00184 /** 00185 * @brief Power Control. (POWER) 00186 */ 00187 00188 typedef struct { /*!< POWER Structure */ 00189 __I uint32_t RESERVED0[30]; 00190 __O uint32_t TASKS_CONSTLAT ; /*!< Enable constant latency mode. */ 00191 __O uint32_t TASKS_LOWPWR ; /*!< Enable low power mode (variable latency). */ 00192 __I uint32_t RESERVED1[34]; 00193 __IO uint32_t EVENTS_POFWARN ; /*!< Power failure warning. */ 00194 __I uint32_t RESERVED2[126]; 00195 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00196 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00197 __I uint32_t RESERVED3[61]; 00198 __IO uint32_t RESETREAS ; /*!< Reset reason. */ 00199 __I uint32_t RESERVED4[9]; 00200 __I uint32_t RAMSTATUS ; /*!< Ram status register. */ 00201 __I uint32_t RESERVED5[53]; 00202 __O uint32_t SYSTEMOFF ; /*!< System off register. */ 00203 __I uint32_t RESERVED6[3]; 00204 __IO uint32_t POFCON ; /*!< Power failure configuration. */ 00205 __I uint32_t RESERVED7[2]; 00206 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained 00207 register. */ 00208 __I uint32_t RESERVED8; 00209 __IO uint32_t RAMON ; /*!< Ram on/off. */ 00210 __I uint32_t RESERVED9[7]; 00211 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register 00212 is a retained register. */ 00213 __I uint32_t RESERVED10[3]; 00214 __IO uint32_t RAMONB ; /*!< Ram on/off. */ 00215 __I uint32_t RESERVED11[8]; 00216 __IO uint32_t DCDCEN ; /*!< DCDC converter enable configuration register. */ 00217 __I uint32_t RESERVED12[291]; 00218 __IO uint32_t DCDCFORCE ; /*!< DCDC power-up force register. */ 00219 } NRF_POWER_Type; 00220 00221 00222 /* ================================================================================ */ 00223 /* ================ CLOCK ================ */ 00224 /* ================================================================================ */ 00225 00226 00227 /** 00228 * @brief Clock control. (CLOCK) 00229 */ 00230 00231 typedef struct { /*!< CLOCK Structure */ 00232 __O uint32_t TASKS_HFCLKSTART ; /*!< Start HFCLK clock source. */ 00233 __O uint32_t TASKS_HFCLKSTOP ; /*!< Stop HFCLK clock source. */ 00234 __O uint32_t TASKS_LFCLKSTART ; /*!< Start LFCLK clock source. */ 00235 __O uint32_t TASKS_LFCLKSTOP ; /*!< Stop LFCLK clock source. */ 00236 __O uint32_t TASKS_CAL ; /*!< Start calibration of LFCLK RC oscillator. */ 00237 __O uint32_t TASKS_CTSTART ; /*!< Start calibration timer. */ 00238 __O uint32_t TASKS_CTSTOP ; /*!< Stop calibration timer. */ 00239 __I uint32_t RESERVED0[57]; 00240 __IO uint32_t EVENTS_HFCLKSTARTED ; /*!< HFCLK oscillator started. */ 00241 __IO uint32_t EVENTS_LFCLKSTARTED ; /*!< LFCLK oscillator started. */ 00242 __I uint32_t RESERVED1; 00243 __IO uint32_t EVENTS_DONE ; /*!< Calibration of LFCLK RC oscillator completed. */ 00244 __IO uint32_t EVENTS_CTTO ; /*!< Calibration timer timeout. */ 00245 __I uint32_t RESERVED2[124]; 00246 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00247 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00248 __I uint32_t RESERVED3[63]; 00249 __I uint32_t HFCLKRUN ; /*!< Task HFCLKSTART trigger status. */ 00250 __I uint32_t HFCLKSTAT ; /*!< High frequency clock status. */ 00251 __I uint32_t RESERVED4; 00252 __I uint32_t LFCLKRUN ; /*!< Task LFCLKSTART triggered status. */ 00253 __I uint32_t LFCLKSTAT ; /*!< Low frequency clock status. */ 00254 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is 00255 triggered. */ 00256 __I uint32_t RESERVED5[62]; 00257 __IO uint32_t LFCLKSRC ; /*!< Clock source for the LFCLK clock. */ 00258 __I uint32_t RESERVED6[7]; 00259 __IO uint32_t CTIV ; /*!< Calibration timer interval. */ 00260 __I uint32_t RESERVED7[5]; 00261 __IO uint32_t XTALFREQ ; /*!< Crystal frequency. */ 00262 } NRF_CLOCK_Type; 00263 00264 00265 /* ================================================================================ */ 00266 /* ================ MPU ================ */ 00267 /* ================================================================================ */ 00268 00269 00270 /** 00271 * @brief Memory Protection Unit. (MPU) 00272 */ 00273 00274 typedef struct { /*!< MPU Structure */ 00275 __I uint32_t RESERVED0[330]; 00276 __IO uint32_t PERR0 ; /*!< Configuration of peripherals in mpu regions. */ 00277 __IO uint32_t RLENR0 ; /*!< Length of RAM region 0. */ 00278 __I uint32_t RESERVED1[52]; 00279 __IO uint32_t PROTENSET0 ; /*!< Erase and write protection bit enable set register. */ 00280 __IO uint32_t PROTENSET1 ; /*!< Erase and write protection bit enable set register. */ 00281 __IO uint32_t DISABLEINDEBUG ; /*!< Disable erase and write protection mechanism in debug mode. */ 00282 __IO uint32_t PROTBLOCKSIZE ; /*!< Erase and write protection block size. */ 00283 } NRF_MPU_Type; 00284 00285 00286 /* ================================================================================ */ 00287 /* ================ PU ================ */ 00288 /* ================================================================================ */ 00289 00290 00291 /** 00292 * @brief Patch unit. (PU) 00293 */ 00294 00295 typedef struct { /*!< PU Structure */ 00296 __I uint32_t RESERVED0[448]; 00297 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */ 00298 __I uint32_t RESERVED1[24]; 00299 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */ 00300 __I uint32_t RESERVED2[24]; 00301 __IO uint32_t PATCHEN ; /*!< Patch enable register. */ 00302 __IO uint32_t PATCHENSET ; /*!< Patch enable register. */ 00303 __IO uint32_t PATCHENCLR ; /*!< Patch disable register. */ 00304 } NRF_PU_Type; 00305 00306 00307 /* ================================================================================ */ 00308 /* ================ AMLI ================ */ 00309 /* ================================================================================ */ 00310 00311 00312 /** 00313 * @brief AHB Multi-Layer Interface. (AMLI) 00314 */ 00315 00316 typedef struct { /*!< AMLI Structure */ 00317 __I uint32_t RESERVED0[896]; 00318 AMLI_RAMPRI_Type RAMPRI ; /*!< RAM configurable priority configuration structure. */ 00319 } NRF_AMLI_Type; 00320 00321 00322 /* ================================================================================ */ 00323 /* ================ RADIO ================ */ 00324 /* ================================================================================ */ 00325 00326 00327 /** 00328 * @brief The radio. (RADIO) 00329 */ 00330 00331 typedef struct { /*!< RADIO Structure */ 00332 __O uint32_t TASKS_TXEN ; /*!< Enable radio in TX mode. */ 00333 __O uint32_t TASKS_RXEN ; /*!< Enable radio in RX mode. */ 00334 __O uint32_t TASKS_START ; /*!< Start radio. */ 00335 __O uint32_t TASKS_STOP ; /*!< Stop radio. */ 00336 __O uint32_t TASKS_DISABLE ; /*!< Disable radio. */ 00337 __O uint32_t TASKS_RSSISTART ; /*!< Start the RSSI and take one sample of the receive signal strength. */ 00338 __O uint32_t TASKS_RSSISTOP ; /*!< Stop the RSSI measurement. */ 00339 __O uint32_t TASKS_BCSTART ; /*!< Start the bit counter. */ 00340 __O uint32_t TASKS_BCSTOP ; /*!< Stop the bit counter. */ 00341 __I uint32_t RESERVED0[55]; 00342 __IO uint32_t EVENTS_READY ; /*!< Ready event. */ 00343 __IO uint32_t EVENTS_ADDRESS ; /*!< Address event. */ 00344 __IO uint32_t EVENTS_PAYLOAD ; /*!< Payload event. */ 00345 __IO uint32_t EVENTS_END ; /*!< End event. */ 00346 __IO uint32_t EVENTS_DISABLED ; /*!< Disable event. */ 00347 __IO uint32_t EVENTS_DEVMATCH ; /*!< A device address match occurred on the last received packet. */ 00348 __IO uint32_t EVENTS_DEVMISS ; /*!< No device address match occurred on the last received packet. */ 00349 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI 00350 sample is ready for readout at the RSSISAMPLE register. */ 00351 __I uint32_t RESERVED1[2]; 00352 __IO uint32_t EVENTS_BCMATCH ; /*!< Bit counter reached bit count value specified in BC register. */ 00353 __I uint32_t RESERVED2[53]; 00354 __IO uint32_t SHORTS ; /*!< Shortcuts for the radio. */ 00355 __I uint32_t RESERVED3[64]; 00356 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00357 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00358 __I uint32_t RESERVED4[61]; 00359 __I uint32_t CRCSTATUS ; /*!< CRC status of received packet. */ 00360 __I uint32_t CD ; /*!< Carrier detect. */ 00361 __I uint32_t RXMATCH ; /*!< Received address. */ 00362 __I uint32_t RXCRC ; /*!< Received CRC. */ 00363 __I uint32_t DAI ; /*!< Device address match index. */ 00364 __I uint32_t RESERVED5[60]; 00365 __IO uint32_t PACKETPTR ; /*!< Packet pointer. Decision point: START task. */ 00366 __IO uint32_t FREQUENCY ; /*!< Frequency. */ 00367 __IO uint32_t TXPOWER ; /*!< Output power. */ 00368 __IO uint32_t MODE ; /*!< Data rate and modulation. */ 00369 __IO uint32_t PCNF0 ; /*!< Packet configuration 0. */ 00370 __IO uint32_t PCNF1 ; /*!< Packet configuration 1. */ 00371 __IO uint32_t BASE0 ; /*!< Radio base address 0. Decision point: START task. */ 00372 __IO uint32_t BASE1 ; /*!< Radio base address 1. Decision point: START task. */ 00373 __IO uint32_t PREFIX0 ; /*!< Prefixes bytes for logical addresses 0 to 3. */ 00374 __IO uint32_t PREFIX1 ; /*!< Prefixes bytes for logical addresses 4 to 7. */ 00375 __IO uint32_t TXADDRESS ; /*!< Transmit address select. */ 00376 __IO uint32_t RXADDRESSES ; /*!< Receive address select. */ 00377 __IO uint32_t CRCCNF ; /*!< CRC configuration. */ 00378 __IO uint32_t CRCPOLY ; /*!< CRC polynomial. */ 00379 __IO uint32_t CRCINIT ; /*!< CRC initial value. */ 00380 __IO uint32_t TEST ; /*!< Test features enable register. */ 00381 __IO uint32_t TIFS ; /*!< Inter Frame Spacing in microseconds. */ 00382 __I uint32_t RSSISAMPLE ; /*!< RSSI sample. */ 00383 __I uint32_t RESERVED6; 00384 __I uint32_t STATE ; /*!< Current radio state. */ 00385 __IO uint32_t DATAWHITEIV ; /*!< Data whitening initial value. */ 00386 __I uint32_t RESERVED7[2]; 00387 __IO uint32_t BCC ; /*!< Bit counter compare. */ 00388 __I uint32_t RESERVED8[39]; 00389 __IO uint32_t DAB[8]; /*!< Device address base segment. */ 00390 __IO uint32_t DAP[8]; /*!< Device address prefix. */ 00391 __IO uint32_t DACNF ; /*!< Device address match configuration. */ 00392 __I uint32_t RESERVED9[56]; 00393 __IO uint32_t OVERRIDE0 ; /*!< Trim value override register 0. */ 00394 __IO uint32_t OVERRIDE1 ; /*!< Trim value override register 1. */ 00395 __IO uint32_t OVERRIDE2 ; /*!< Trim value override register 2. */ 00396 __IO uint32_t OVERRIDE3 ; /*!< Trim value override register 3. */ 00397 __IO uint32_t OVERRIDE4 ; /*!< Trim value override register 4. */ 00398 __I uint32_t RESERVED10[561]; 00399 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00400 } NRF_RADIO_Type; 00401 00402 00403 /* ================================================================================ */ 00404 /* ================ UART ================ */ 00405 /* ================================================================================ */ 00406 00407 00408 /** 00409 * @brief Universal Asynchronous Receiver/Transmitter. (UART) 00410 */ 00411 00412 typedef struct { /*!< UART Structure */ 00413 __O uint32_t TASKS_STARTRX ; /*!< Start UART receiver. */ 00414 __O uint32_t TASKS_STOPRX ; /*!< Stop UART receiver. */ 00415 __O uint32_t TASKS_STARTTX ; /*!< Start UART transmitter. */ 00416 __O uint32_t TASKS_STOPTX ; /*!< Stop UART transmitter. */ 00417 __I uint32_t RESERVED0[3]; 00418 __O uint32_t TASKS_SUSPEND ; /*!< Suspend UART. */ 00419 __I uint32_t RESERVED1[56]; 00420 __IO uint32_t EVENTS_CTS ; /*!< CTS activated. */ 00421 __IO uint32_t EVENTS_NCTS ; /*!< CTS deactivated. */ 00422 __IO uint32_t EVENTS_RXDRDY ; /*!< Data received in RXD. */ 00423 __I uint32_t RESERVED2[4]; 00424 __IO uint32_t EVENTS_TXDRDY ; /*!< Data sent from TXD. */ 00425 __I uint32_t RESERVED3; 00426 __IO uint32_t EVENTS_ERROR ; /*!< Error detected. */ 00427 __I uint32_t RESERVED4[7]; 00428 __IO uint32_t EVENTS_RXTO ; /*!< Receiver timeout. */ 00429 __I uint32_t RESERVED5[46]; 00430 __IO uint32_t SHORTS ; /*!< Shortcuts for UART. */ 00431 __I uint32_t RESERVED6[64]; 00432 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00433 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00434 __I uint32_t RESERVED7[93]; 00435 __IO uint32_t ERRORSRC ; /*!< Error source. Write error field to 1 to clear error. */ 00436 __I uint32_t RESERVED8[31]; 00437 __IO uint32_t ENABLE ; /*!< Enable UART and acquire IOs. */ 00438 __I uint32_t RESERVED9; 00439 __IO uint32_t PSELRTS ; /*!< Pin select for RTS. */ 00440 __IO uint32_t PSELTXD ; /*!< Pin select for TXD. */ 00441 __IO uint32_t PSELCTS ; /*!< Pin select for CTS. */ 00442 __IO uint32_t PSELRXD ; /*!< Pin select for RXD. */ 00443 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. 00444 Once read the character is consumed. If read when no character 00445 available, the UART will stop working. */ 00446 __O uint32_t TXD ; /*!< TXD register. */ 00447 __I uint32_t RESERVED10; 00448 __IO uint32_t BAUDRATE ; /*!< UART Baudrate. */ 00449 __I uint32_t RESERVED11[17]; 00450 __IO uint32_t CONFIG ; /*!< Configuration of parity and hardware flow control register. */ 00451 __I uint32_t RESERVED12[675]; 00452 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00453 } NRF_UART_Type; 00454 00455 00456 /* ================================================================================ */ 00457 /* ================ SPI ================ */ 00458 /* ================================================================================ */ 00459 00460 00461 /** 00462 * @brief SPI master 0. (SPI) 00463 */ 00464 00465 typedef struct { /*!< SPI Structure */ 00466 __I uint32_t RESERVED0[66]; 00467 __IO uint32_t EVENTS_READY ; /*!< TXD byte sent and RXD byte received. */ 00468 __I uint32_t RESERVED1[126]; 00469 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00470 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00471 __I uint32_t RESERVED2[125]; 00472 __IO uint32_t ENABLE ; /*!< Enable SPI. */ 00473 __I uint32_t RESERVED3; 00474 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00475 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00476 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00477 __I uint32_t RESERVED4; 00478 __I uint32_t RXD ; /*!< RX data. */ 00479 __IO uint32_t TXD ; /*!< TX data. */ 00480 __I uint32_t RESERVED5; 00481 __IO uint32_t FREQUENCY ; /*!< SPI frequency */ 00482 __I uint32_t RESERVED6[11]; 00483 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00484 __I uint32_t RESERVED7[681]; 00485 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00486 } NRF_SPI_Type; 00487 00488 00489 /* ================================================================================ */ 00490 /* ================ TWI ================ */ 00491 /* ================================================================================ */ 00492 00493 00494 /** 00495 * @brief Two-wire interface master 0. (TWI) 00496 */ 00497 00498 typedef struct { /*!< TWI Structure */ 00499 __O uint32_t TASKS_STARTRX ; /*!< Start 2-Wire master receive sequence. */ 00500 __I uint32_t RESERVED0; 00501 __O uint32_t TASKS_STARTTX ; /*!< Start 2-Wire master transmit sequence. */ 00502 __I uint32_t RESERVED1[2]; 00503 __O uint32_t TASKS_STOP ; /*!< Stop 2-Wire transaction. */ 00504 __I uint32_t RESERVED2; 00505 __O uint32_t TASKS_SUSPEND ; /*!< Suspend 2-Wire transaction. */ 00506 __O uint32_t TASKS_RESUME ; /*!< Resume 2-Wire transaction. */ 00507 __I uint32_t RESERVED3[56]; 00508 __IO uint32_t EVENTS_STOPPED ; /*!< Two-wire stopped. */ 00509 __IO uint32_t EVENTS_RXDREADY ; /*!< Two-wire ready to deliver new RXD byte received. */ 00510 __I uint32_t RESERVED4[4]; 00511 __IO uint32_t EVENTS_TXDSENT ; /*!< Two-wire finished sending last TXD byte. */ 00512 __I uint32_t RESERVED5; 00513 __IO uint32_t EVENTS_ERROR ; /*!< Two-wire error detected. */ 00514 __I uint32_t RESERVED6[4]; 00515 __IO uint32_t EVENTS_BB ; /*!< Two-wire byte boundary. */ 00516 __I uint32_t RESERVED7[3]; 00517 __IO uint32_t EVENTS_SUSPENDED ; /*!< Two-wire suspended. */ 00518 __I uint32_t RESERVED8[45]; 00519 __IO uint32_t SHORTS ; /*!< Shortcuts for TWI. */ 00520 __I uint32_t RESERVED9[64]; 00521 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00522 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00523 __I uint32_t RESERVED10[110]; 00524 __IO uint32_t ERRORSRC ; /*!< Two-wire error source. Write error field to 1 to clear error. */ 00525 __I uint32_t RESERVED11[14]; 00526 __IO uint32_t ENABLE ; /*!< Enable two-wire master. */ 00527 __I uint32_t RESERVED12; 00528 __IO uint32_t PSELSCL ; /*!< Pin select for SCL. */ 00529 __IO uint32_t PSELSDA ; /*!< Pin select for SDA. */ 00530 __I uint32_t RESERVED13[2]; 00531 __I uint32_t RXD ; /*!< RX data register. */ 00532 __IO uint32_t TXD ; /*!< TX data register. */ 00533 __I uint32_t RESERVED14; 00534 __IO uint32_t FREQUENCY ; /*!< Two-wire frequency. */ 00535 __I uint32_t RESERVED15[24]; 00536 __IO uint32_t ADDRESS ; /*!< Address used in the two-wire transfer. */ 00537 __I uint32_t RESERVED16[668]; 00538 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00539 } NRF_TWI_Type; 00540 00541 00542 /* ================================================================================ */ 00543 /* ================ SPIS ================ */ 00544 /* ================================================================================ */ 00545 00546 00547 /** 00548 * @brief SPI slave 1. (SPIS) 00549 */ 00550 00551 typedef struct { /*!< SPIS Structure */ 00552 __I uint32_t RESERVED0[9]; 00553 __O uint32_t TASKS_ACQUIRE ; /*!< Acquire SPI semaphore. */ 00554 __O uint32_t TASKS_RELEASE ; /*!< Release SPI semaphore. */ 00555 __I uint32_t RESERVED1[54]; 00556 __IO uint32_t EVENTS_END ; /*!< Granted transaction completed. */ 00557 __I uint32_t RESERVED2[8]; 00558 __IO uint32_t EVENTS_ACQUIRED ; /*!< Semaphore acquired. */ 00559 __I uint32_t RESERVED3[53]; 00560 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIS. */ 00561 __I uint32_t RESERVED4[64]; 00562 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00563 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00564 __I uint32_t RESERVED5[61]; 00565 __I uint32_t SEMSTAT ; /*!< Semaphore status. */ 00566 __I uint32_t RESERVED6[15]; 00567 __IO uint32_t STATUS ; /*!< Status from last transaction. */ 00568 __I uint32_t RESERVED7[47]; 00569 __IO uint32_t ENABLE ; /*!< Enable SPIS. */ 00570 __I uint32_t RESERVED8; 00571 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00572 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00573 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00574 __IO uint32_t PSELCSN ; /*!< Pin select for CSN. */ 00575 __I uint32_t RESERVED9[7]; 00576 __IO uint32_t RXDPTR ; /*!< RX data pointer. */ 00577 __IO uint32_t MAXRX ; /*!< Maximum number of bytes in the receive buffer. */ 00578 __I uint32_t AMOUNTRX ; /*!< Number of bytes received in last granted transaction. */ 00579 __I uint32_t RESERVED10; 00580 __IO uint32_t TXDPTR ; /*!< TX data pointer. */ 00581 __IO uint32_t MAXTX ; /*!< Maximum number of bytes in the transmit buffer. */ 00582 __I uint32_t AMOUNTTX ; /*!< Number of bytes transmitted in last granted transaction. */ 00583 __I uint32_t RESERVED11; 00584 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00585 __I uint32_t RESERVED12; 00586 __IO uint32_t DEF ; /*!< Default character. */ 00587 __I uint32_t RESERVED13[24]; 00588 __IO uint32_t ORC ; /*!< Over-read character. */ 00589 __I uint32_t RESERVED14[654]; 00590 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00591 } NRF_SPIS_Type; 00592 00593 00594 /* ================================================================================ */ 00595 /* ================ SPIM ================ */ 00596 /* ================================================================================ */ 00597 00598 00599 /** 00600 * @brief SPI master with easyDMA 1. (SPIM) 00601 */ 00602 00603 typedef struct { /*!< SPIM Structure */ 00604 __I uint32_t RESERVED0[4]; 00605 __O uint32_t TASKS_START ; /*!< Start SPI transaction. */ 00606 __O uint32_t TASKS_STOP ; /*!< Stop SPI transaction. */ 00607 __I uint32_t RESERVED1; 00608 __O uint32_t TASKS_SUSPEND ; /*!< Suspend SPI transaction. */ 00609 __O uint32_t TASKS_RESUME ; /*!< Resume SPI transaction. */ 00610 __I uint32_t RESERVED2[56]; 00611 __IO uint32_t EVENTS_STOPPED ; /*!< SPI transaction has stopped. */ 00612 __I uint32_t RESERVED3[2]; 00613 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached. */ 00614 __I uint32_t RESERVED4; 00615 __IO uint32_t EVENTS_END ; /*!< End of RXD buffer and TXD buffer reached. */ 00616 __I uint32_t RESERVED5; 00617 __IO uint32_t EVENTS_ENDTX ; /*!< End of TXD buffer reached. */ 00618 __I uint32_t RESERVED6[10]; 00619 __IO uint32_t EVENTS_STARTED ; /*!< Transaction started. */ 00620 __I uint32_t RESERVED7[44]; 00621 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIM. */ 00622 __I uint32_t RESERVED8[64]; 00623 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00624 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00625 __I uint32_t RESERVED9[125]; 00626 __IO uint32_t ENABLE ; /*!< Enable SPIM. */ 00627 __I uint32_t RESERVED10; 00628 SPIM_PSEL_Type PSEL ; /*!< Pin select configuration. */ 00629 __I uint32_t RESERVED11; 00630 __I uint32_t RXDDATA ; /*!< RXD register. */ 00631 __IO uint32_t TXDDATA ; /*!< TXD register. */ 00632 __I uint32_t RESERVED12; 00633 __IO uint32_t FREQUENCY ; /*!< SPI frequency. */ 00634 __I uint32_t RESERVED13[3]; 00635 SPIM_RXD_Type RXD ; /*!< RXD EasyDMA configuration and status. */ 00636 __I uint32_t RESERVED14; 00637 SPIM_TXD_Type TXD ; /*!< TXD EasyDMA configuration and status. */ 00638 __I uint32_t RESERVED15; 00639 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00640 __I uint32_t RESERVED16[26]; 00641 __IO uint32_t ORC ; /*!< Over-read character. */ 00642 __I uint32_t RESERVED17[654]; 00643 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00644 } NRF_SPIM_Type; 00645 00646 00647 /* ================================================================================ */ 00648 /* ================ GPIOTE ================ */ 00649 /* ================================================================================ */ 00650 00651 00652 /** 00653 * @brief GPIO tasks and events. (GPIOTE) 00654 */ 00655 00656 typedef struct { /*!< GPIOTE Structure */ 00657 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00658 __I uint32_t RESERVED0[60]; 00659 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00660 __I uint32_t RESERVED1[27]; 00661 __IO uint32_t EVENTS_PORT ; /*!< Event generated from multiple pins. */ 00662 __I uint32_t RESERVED2[97]; 00663 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00664 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00665 __I uint32_t RESERVED3[129]; 00666 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ 00667 __I uint32_t RESERVED4[695]; 00668 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00669 } NRF_GPIOTE_Type; 00670 00671 00672 /* ================================================================================ */ 00673 /* ================ ADC ================ */ 00674 /* ================================================================================ */ 00675 00676 00677 /** 00678 * @brief Analog to digital converter. (ADC) 00679 */ 00680 00681 typedef struct { /*!< ADC Structure */ 00682 __O uint32_t TASKS_START ; /*!< Start an ADC conversion. */ 00683 __O uint32_t TASKS_STOP ; /*!< Stop ADC. */ 00684 __I uint32_t RESERVED0[62]; 00685 __IO uint32_t EVENTS_END ; /*!< ADC conversion complete. */ 00686 __I uint32_t RESERVED1[128]; 00687 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00688 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00689 __I uint32_t RESERVED2[61]; 00690 __I uint32_t BUSY ; /*!< ADC busy register. */ 00691 __I uint32_t RESERVED3[63]; 00692 __IO uint32_t ENABLE ; /*!< ADC enable. */ 00693 __IO uint32_t CONFIG ; /*!< ADC configuration register. */ 00694 __I uint32_t RESULT ; /*!< Result of ADC conversion. */ 00695 __I uint32_t RESERVED4[700]; 00696 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00697 } NRF_ADC_Type; 00698 00699 00700 /* ================================================================================ */ 00701 /* ================ TIMER ================ */ 00702 /* ================================================================================ */ 00703 00704 00705 /** 00706 * @brief Timer 0. (TIMER) 00707 */ 00708 00709 typedef struct { /*!< TIMER Structure */ 00710 __O uint32_t TASKS_START ; /*!< Start Timer. */ 00711 __O uint32_t TASKS_STOP ; /*!< Stop Timer. */ 00712 __O uint32_t TASKS_COUNT ; /*!< Increment Timer (In counter mode). */ 00713 __O uint32_t TASKS_CLEAR ; /*!< Clear timer. */ 00714 __O uint32_t TASKS_SHUTDOWN ; /*!< Shutdown timer. */ 00715 __I uint32_t RESERVED0[11]; 00716 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ 00717 __I uint32_t RESERVED1[60]; 00718 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00719 __I uint32_t RESERVED2[44]; 00720 __IO uint32_t SHORTS ; /*!< Shortcuts for Timer. */ 00721 __I uint32_t RESERVED3[64]; 00722 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00723 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00724 __I uint32_t RESERVED4[126]; 00725 __IO uint32_t MODE ; /*!< Timer Mode selection. */ 00726 __IO uint32_t BITMODE ; /*!< Sets timer behaviour. */ 00727 __I uint32_t RESERVED5; 00728 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source 00729 clock frequency is divided by 2^SCALE. */ 00730 __I uint32_t RESERVED6[11]; 00731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00732 __I uint32_t RESERVED7[683]; 00733 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00734 } NRF_TIMER_Type; 00735 00736 00737 /* ================================================================================ */ 00738 /* ================ RTC ================ */ 00739 /* ================================================================================ */ 00740 00741 00742 /** 00743 * @brief Real time counter 0. (RTC) 00744 */ 00745 00746 typedef struct { /*!< RTC Structure */ 00747 __O uint32_t TASKS_START ; /*!< Start RTC Counter. */ 00748 __O uint32_t TASKS_STOP ; /*!< Stop RTC Counter. */ 00749 __O uint32_t TASKS_CLEAR ; /*!< Clear RTC Counter. */ 00750 __O uint32_t TASKS_TRIGOVRFLW ; /*!< Set COUNTER to 0xFFFFFFF0. */ 00751 __I uint32_t RESERVED0[60]; 00752 __IO uint32_t EVENTS_TICK ; /*!< Event on COUNTER increment. */ 00753 __IO uint32_t EVENTS_OVRFLW ; /*!< Event on COUNTER overflow. */ 00754 __I uint32_t RESERVED1[14]; 00755 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00756 __I uint32_t RESERVED2[109]; 00757 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00758 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00759 __I uint32_t RESERVED3[13]; 00760 __IO uint32_t EVTEN ; /*!< Configures event enable routing to PPI for each RTC event. */ 00761 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives 00762 the value of EVTEN. */ 00763 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register 00764 gives the value of EVTEN. */ 00765 __I uint32_t RESERVED4[110]; 00766 __I uint32_t COUNTER ; /*!< Current COUNTER value. */ 00767 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 00768 Must be written when RTC is STOPed. */ 00769 __I uint32_t RESERVED5[13]; 00770 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00771 __I uint32_t RESERVED6[683]; 00772 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00773 } NRF_RTC_Type; 00774 00775 00776 /* ================================================================================ */ 00777 /* ================ TEMP ================ */ 00778 /* ================================================================================ */ 00779 00780 00781 /** 00782 * @brief Temperature Sensor. (TEMP) 00783 */ 00784 00785 typedef struct { /*!< TEMP Structure */ 00786 __O uint32_t TASKS_START ; /*!< Start temperature measurement. */ 00787 __O uint32_t TASKS_STOP ; /*!< Stop temperature measurement. */ 00788 __I uint32_t RESERVED0[62]; 00789 __IO uint32_t EVENTS_DATARDY ; /*!< Temperature measurement complete, data ready event. */ 00790 __I uint32_t RESERVED1[128]; 00791 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00792 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00793 __I uint32_t RESERVED2[127]; 00794 __I int32_t TEMP ; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ 00795 __I uint32_t RESERVED3[700]; 00796 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00797 } NRF_TEMP_Type; 00798 00799 00800 /* ================================================================================ */ 00801 /* ================ RNG ================ */ 00802 /* ================================================================================ */ 00803 00804 00805 /** 00806 * @brief Random Number Generator. (RNG) 00807 */ 00808 00809 typedef struct { /*!< RNG Structure */ 00810 __O uint32_t TASKS_START ; /*!< Start the random number generator. */ 00811 __O uint32_t TASKS_STOP ; /*!< Stop the random number generator. */ 00812 __I uint32_t RESERVED0[62]; 00813 __IO uint32_t EVENTS_VALRDY ; /*!< New random number generated and written to VALUE register. */ 00814 __I uint32_t RESERVED1[63]; 00815 __IO uint32_t SHORTS ; /*!< Shortcuts for the RNG. */ 00816 __I uint32_t RESERVED2[64]; 00817 __IO uint32_t INTENSET ; /*!< Interrupt enable set register */ 00818 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register */ 00819 __I uint32_t RESERVED3[126]; 00820 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00821 __I uint32_t VALUE ; /*!< RNG random number. */ 00822 __I uint32_t RESERVED4[700]; 00823 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00824 } NRF_RNG_Type; 00825 00826 00827 /* ================================================================================ */ 00828 /* ================ ECB ================ */ 00829 /* ================================================================================ */ 00830 00831 00832 /** 00833 * @brief AES ECB Mode Encryption. (ECB) 00834 */ 00835 00836 typedef struct { /*!< ECB Structure */ 00837 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this 00838 will not initiate a new encryption and the ERRORECB event will 00839 be triggered. */ 00840 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, 00841 this will will trigger the ERRORECB event. */ 00842 __I uint32_t RESERVED0[62]; 00843 __IO uint32_t EVENTS_ENDECB ; /*!< ECB block encrypt complete. */ 00844 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an 00845 error. */ 00846 __I uint32_t RESERVED1[127]; 00847 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00848 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00849 __I uint32_t RESERVED2[126]; 00850 __IO uint32_t ECBDATAPTR ; /*!< ECB block encrypt memory pointer. */ 00851 __I uint32_t RESERVED3[701]; 00852 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00853 } NRF_ECB_Type; 00854 00855 00856 /* ================================================================================ */ 00857 /* ================ AAR ================ */ 00858 /* ================================================================================ */ 00859 00860 00861 /** 00862 * @brief Accelerated Address Resolver. (AAR) 00863 */ 00864 00865 typedef struct { /*!< AAR Structure */ 00866 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK 00867 data structure. */ 00868 __I uint32_t RESERVED0; 00869 __O uint32_t TASKS_STOP ; /*!< Stop resolving addresses. */ 00870 __I uint32_t RESERVED1[61]; 00871 __IO uint32_t EVENTS_END ; /*!< Address resolution procedure completed. */ 00872 __IO uint32_t EVENTS_RESOLVED ; /*!< Address resolved. */ 00873 __IO uint32_t EVENTS_NOTRESOLVED ; /*!< Address not resolved. */ 00874 __I uint32_t RESERVED2[126]; 00875 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00876 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00877 __I uint32_t RESERVED3[61]; 00878 __I uint32_t STATUS ; /*!< Resolution status. */ 00879 __I uint32_t RESERVED4[63]; 00880 __IO uint32_t ENABLE ; /*!< Enable AAR. */ 00881 __IO uint32_t NIRK ; /*!< Number of Identity root Keys in the IRK data structure. */ 00882 __IO uint32_t IRKPTR ; /*!< Pointer to the IRK data structure. */ 00883 __I uint32_t RESERVED5; 00884 __IO uint32_t ADDRPTR ; /*!< Pointer to the resolvable address (6 bytes). */ 00885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00886 during resolution. A minimum of 3 bytes must be reserved. */ 00887 __I uint32_t RESERVED6[697]; 00888 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00889 } NRF_AAR_Type; 00890 00891 00892 /* ================================================================================ */ 00893 /* ================ CCM ================ */ 00894 /* ================================================================================ */ 00895 00896 00897 /** 00898 * @brief AES CCM Mode Encryption. (CCM) 00899 */ 00900 00901 typedef struct { /*!< CCM Structure */ 00902 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by 00903 itself when completed. */ 00904 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when 00905 completed. */ 00906 __O uint32_t TASKS_STOP ; /*!< Stop encrypt/decrypt. */ 00907 __I uint32_t RESERVED0[61]; 00908 __IO uint32_t EVENTS_ENDKSGEN ; /*!< Keystream generation completed. */ 00909 __IO uint32_t EVENTS_ENDCRYPT ; /*!< Encrypt/decrypt completed. */ 00910 __IO uint32_t EVENTS_ERROR ; /*!< Error happened. */ 00911 __I uint32_t RESERVED1[61]; 00912 __IO uint32_t SHORTS ; /*!< Shortcuts for the CCM. */ 00913 __I uint32_t RESERVED2[64]; 00914 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00915 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00916 __I uint32_t RESERVED3[61]; 00917 __I uint32_t MICSTATUS ; /*!< CCM RX MIC check result. */ 00918 __I uint32_t RESERVED4[63]; 00919 __IO uint32_t ENABLE ; /*!< CCM enable. */ 00920 __IO uint32_t MODE ; /*!< Operation mode. */ 00921 __IO uint32_t CNFPTR ; /*!< Pointer to a data structure holding AES key and NONCE vector. */ 00922 __IO uint32_t INPTR ; /*!< Pointer to the input packet. */ 00923 __IO uint32_t OUTPTR ; /*!< Pointer to the output packet. */ 00924 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage 00925 during resolution. A minimum of 43 bytes must be reserved. */ 00926 __I uint32_t RESERVED5[697]; 00927 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00928 } NRF_CCM_Type; 00929 00930 00931 /* ================================================================================ */ 00932 /* ================ WDT ================ */ 00933 /* ================================================================================ */ 00934 00935 00936 /** 00937 * @brief Watchdog Timer. (WDT) 00938 */ 00939 00940 typedef struct { /*!< WDT Structure */ 00941 __O uint32_t TASKS_START ; /*!< Start the watchdog. */ 00942 __I uint32_t RESERVED0[63]; 00943 __IO uint32_t EVENTS_TIMEOUT ; /*!< Watchdog timeout. */ 00944 __I uint32_t RESERVED1[128]; 00945 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00946 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00947 __I uint32_t RESERVED2[61]; 00948 __I uint32_t RUNSTATUS ; /*!< Watchdog running status. */ 00949 __I uint32_t REQSTATUS ; /*!< Request status. */ 00950 __I uint32_t RESERVED3[63]; 00951 __IO uint32_t CRV ; /*!< Counter reload value in number of 32kiHz clock cycles. */ 00952 __IO uint32_t RREN ; /*!< Reload request enable. */ 00953 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00954 __I uint32_t RESERVED4[60]; 00955 __O uint32_t RR[8]; /*!< Reload requests registers. */ 00956 __I uint32_t RESERVED5[631]; 00957 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00958 } NRF_WDT_Type; 00959 00960 00961 /* ================================================================================ */ 00962 /* ================ QDEC ================ */ 00963 /* ================================================================================ */ 00964 00965 00966 /** 00967 * @brief Rotary decoder. (QDEC) 00968 */ 00969 00970 typedef struct { /*!< QDEC Structure */ 00971 __O uint32_t TASKS_START ; /*!< Start the quadrature decoder. */ 00972 __O uint32_t TASKS_STOP ; /*!< Stop the quadrature decoder. */ 00973 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, 00974 and clears the ACC registers. */ 00975 __I uint32_t RESERVED0[61]; 00976 __IO uint32_t EVENTS_SAMPLERDY ; /*!< A new sample is written to the sample register. */ 00977 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and 00978 ACC register different than zero. */ 00979 __IO uint32_t EVENTS_ACCOF ; /*!< ACC or ACCDBL register overflow. */ 00980 __I uint32_t RESERVED1[61]; 00981 __IO uint32_t SHORTS ; /*!< Shortcuts for the QDEC. */ 00982 __I uint32_t RESERVED2[64]; 00983 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00984 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00985 __I uint32_t RESERVED3[125]; 00986 __IO uint32_t ENABLE ; /*!< Enable the QDEC. */ 00987 __IO uint32_t LEDPOL ; /*!< LED output pin polarity. */ 00988 __IO uint32_t SAMPLEPER ; /*!< Sample period. */ 00989 __I int32_t SAMPLE ; /*!< Motion sample value. */ 00990 __IO uint32_t REPORTPER ; /*!< Number of samples to generate an EVENT_REPORTRDY. */ 00991 __I int32_t ACC ; /*!< Accumulated valid transitions register. */ 00992 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC 00993 task. */ 00994 __IO uint32_t PSELLED ; /*!< Pin select for LED output. */ 00995 __IO uint32_t PSELA ; /*!< Pin select for phase A input. */ 00996 __IO uint32_t PSELB ; /*!< Pin select for phase B input. */ 00997 __IO uint32_t DBFEN ; /*!< Enable debouncer input filters. */ 00998 __I uint32_t RESERVED4[5]; 00999 __IO uint32_t LEDPRE ; /*!< Time LED is switched ON before the sample. */ 01000 __I uint32_t ACCDBL ; /*!< Accumulated double (error) transitions register. */ 01001 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC 01002 task. */ 01003 __I uint32_t RESERVED5[684]; 01004 __IO uint32_t POWER ; /*!< Peripheral power control. */ 01005 } NRF_QDEC_Type; 01006 01007 01008 /* ================================================================================ */ 01009 /* ================ LPCOMP ================ */ 01010 /* ================================================================================ */ 01011 01012 01013 /** 01014 * @brief Low power comparator. (LPCOMP) 01015 */ 01016 01017 typedef struct { /*!< LPCOMP Structure */ 01018 __O uint32_t TASKS_START ; /*!< Start the comparator. */ 01019 __O uint32_t TASKS_STOP ; /*!< Stop the comparator. */ 01020 __O uint32_t TASKS_SAMPLE ; /*!< Sample comparator value. */ 01021 __I uint32_t RESERVED0[61]; 01022 __IO uint32_t EVENTS_READY ; /*!< LPCOMP is ready and output is valid. */ 01023 __IO uint32_t EVENTS_DOWN ; /*!< Input voltage crossed the threshold going down. */ 01024 __IO uint32_t EVENTS_UP ; /*!< Input voltage crossed the threshold going up. */ 01025 __IO uint32_t EVENTS_CROSS ; /*!< Input voltage crossed the threshold in any direction. */ 01026 __I uint32_t RESERVED1[60]; 01027 __IO uint32_t SHORTS ; /*!< Shortcuts for the LPCOMP. */ 01028 __I uint32_t RESERVED2[64]; 01029 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 01030 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 01031 __I uint32_t RESERVED3[61]; 01032 __I uint32_t RESULT ; /*!< Result of last compare. */ 01033 __I uint32_t RESERVED4[63]; 01034 __IO uint32_t ENABLE ; /*!< Enable the LPCOMP. */ 01035 __IO uint32_t PSEL ; /*!< Input pin select. */ 01036 __IO uint32_t REFSEL ; /*!< Reference select. */ 01037 __IO uint32_t EXTREFSEL ; /*!< External reference select. */ 01038 __I uint32_t RESERVED5[4]; 01039 __IO uint32_t ANADETECT ; /*!< Analog detect configuration. */ 01040 __I uint32_t RESERVED6[694]; 01041 __IO uint32_t POWER ; /*!< Peripheral power control. */ 01042 } NRF_LPCOMP_Type; 01043 01044 01045 /* ================================================================================ */ 01046 /* ================ SWI ================ */ 01047 /* ================================================================================ */ 01048 01049 01050 /** 01051 * @brief SW Interrupts. (SWI) 01052 */ 01053 01054 typedef struct { /*!< SWI Structure */ 01055 __I uint32_t UNUSED ; /*!< Unused. */ 01056 } NRF_SWI_Type; 01057 01058 01059 /* ================================================================================ */ 01060 /* ================ NVMC ================ */ 01061 /* ================================================================================ */ 01062 01063 01064 /** 01065 * @brief Non Volatile Memory Controller. (NVMC) 01066 */ 01067 01068 typedef struct { /*!< NVMC Structure */ 01069 __I uint32_t RESERVED0[256]; 01070 __I uint32_t READY ; /*!< Ready flag. */ 01071 __I uint32_t RESERVED1[64]; 01072 __IO uint32_t CONFIG ; /*!< Configuration register. */ 01073 __IO uint32_t ERASEPAGE ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01074 __IO uint32_t ERASEALL ; /*!< Register for erasing all non-volatile user memory. */ 01075 __IO uint32_t ERASEPROTECTEDPAGE ; /*!< Register for erasing a protected non-volatile memory page. */ 01076 __IO uint32_t ERASEUICR ; /*!< Register for start erasing User Information Congfiguration Registers. */ 01077 } NRF_NVMC_Type; 01078 01079 01080 /* ================================================================================ */ 01081 /* ================ PPI ================ */ 01082 /* ================================================================================ */ 01083 01084 01085 /** 01086 * @brief PPI controller. (PPI) 01087 */ 01088 01089 typedef struct { /*!< PPI Structure */ 01090 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ 01091 __I uint32_t RESERVED0[312]; 01092 __IO uint32_t CHEN ; /*!< Channel enable. */ 01093 __IO uint32_t CHENSET ; /*!< Channel enable set. */ 01094 __IO uint32_t CHENCLR ; /*!< Channel enable clear. */ 01095 __I uint32_t RESERVED1; 01096 PPI_CH_Type CH[16]; /*!< PPI Channel. */ 01097 __I uint32_t RESERVED2[156]; 01098 __IO uint32_t CHG[4]; /*!< Channel group configuration. */ 01099 } NRF_PPI_Type; 01100 01101 01102 /* ================================================================================ */ 01103 /* ================ FICR ================ */ 01104 /* ================================================================================ */ 01105 01106 01107 /** 01108 * @brief Factory Information Configuration. (FICR) 01109 */ 01110 01111 typedef struct { /*!< FICR Structure */ 01112 __I uint32_t RESERVED0[4]; 01113 __I uint32_t CODEPAGESIZE ; /*!< Code memory page size in bytes. */ 01114 __I uint32_t CODESIZE ; /*!< Code memory size in pages. */ 01115 __I uint32_t RESERVED1[4]; 01116 __I uint32_t CLENR0 ; /*!< Length of code region 0 in bytes. */ 01117 __I uint32_t PPFC ; /*!< Pre-programmed factory code present. */ 01118 __I uint32_t RESERVED2; 01119 __I uint32_t NUMRAMBLOCK ; /*!< Number of individualy controllable RAM blocks. */ 01120 01121 union { 01122 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is 01123 kept for backward compatinility purposes. Use SIZERAMBLOCKS 01124 instead. */ 01125 __I uint32_t SIZERAMBLOCKS ; /*!< Size of RAM blocks in bytes. */ 01126 }; 01127 __I uint32_t RESERVED3[5]; 01128 __I uint32_t CONFIGID ; /*!< Configuration identifier. */ 01129 __I uint32_t DEVICEID[2]; /*!< Device identifier. */ 01130 __I uint32_t RESERVED4[6]; 01131 __I uint32_t ER[4]; /*!< Encryption root. */ 01132 __I uint32_t IR[4]; /*!< Identity root. */ 01133 __I uint32_t DEVICEADDRTYPE ; /*!< Device address type. */ 01134 __I uint32_t DEVICEADDR[2]; /*!< Device address. */ 01135 __I uint32_t OVERRIDEEN ; /*!< Radio calibration override enable. */ 01136 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit 01137 mode. */ 01138 __I uint32_t RESERVED5[10]; 01139 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit 01140 mode. */ 01141 FICR_INFO_Type INFO ; /*!< Device info */ 01142 } NRF_FICR_Type; 01143 01144 01145 /* ================================================================================ */ 01146 /* ================ UICR ================ */ 01147 /* ================================================================================ */ 01148 01149 01150 /** 01151 * @brief User Information Configuration. (UICR) 01152 */ 01153 01154 typedef struct { /*!< UICR Structure */ 01155 __IO uint32_t CLENR0 ; /*!< Length of code region 0. */ 01156 __IO uint32_t RBPCONF ; /*!< Readback protection configuration. */ 01157 __IO uint32_t XTALFREQ ; /*!< Reset value for CLOCK XTALFREQ register. */ 01158 __I uint32_t RESERVED0; 01159 __I uint32_t FWID ; /*!< Firmware ID. */ 01160 __IO uint32_t BOOTLOADERADDR ; /*!< Bootloader start address. */ 01161 } NRF_UICR_Type; 01162 01163 01164 /* ================================================================================ */ 01165 /* ================ GPIO ================ */ 01166 /* ================================================================================ */ 01167 01168 01169 /** 01170 * @brief General purpose input and output. (GPIO) 01171 */ 01172 01173 typedef struct { /*!< GPIO Structure */ 01174 __I uint32_t RESERVED0[321]; 01175 __IO uint32_t OUT ; /*!< Write GPIO port. */ 01176 __IO uint32_t OUTSET ; /*!< Set individual bits in GPIO port. */ 01177 __IO uint32_t OUTCLR ; /*!< Clear individual bits in GPIO port. */ 01178 __I uint32_t IN ; /*!< Read GPIO port. */ 01179 __IO uint32_t DIR ; /*!< Direction of GPIO pins. */ 01180 __IO uint32_t DIRSET ; /*!< DIR set register. */ 01181 __IO uint32_t DIRCLR ; /*!< DIR clear register. */ 01182 __I uint32_t RESERVED1[120]; 01183 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ 01184 } NRF_GPIO_Type; 01185 01186 01187 /* -------------------- End of section using anonymous unions ------------------- */ 01188 #if defined(__CC_ARM) 01189 #pragma pop 01190 #elif defined(__ICCARM__) 01191 /* leave anonymous unions enabled */ 01192 #elif defined(__GNUC__) 01193 /* anonymous unions are enabled by default */ 01194 #elif defined(__TMS470__) 01195 /* anonymous unions are enabled by default */ 01196 #elif defined(__TASKING__) 01197 #pragma warning restore 01198 #else 01199 #warning Not supported compiler type 01200 #endif 01201 01202 01203 01204 01205 /* ================================================================================ */ 01206 /* ================ Peripheral memory map ================ */ 01207 /* ================================================================================ */ 01208 01209 #define NRF_POWER_BASE 0x40000000UL 01210 #define NRF_CLOCK_BASE 0x40000000UL 01211 #define NRF_MPU_BASE 0x40000000UL 01212 #define NRF_PU_BASE 0x40000000UL 01213 #define NRF_AMLI_BASE 0x40000000UL 01214 #define NRF_RADIO_BASE 0x40001000UL 01215 #define NRF_UART0_BASE 0x40002000UL 01216 #define NRF_SPI0_BASE 0x40003000UL 01217 #define NRF_TWI0_BASE 0x40003000UL 01218 #define NRF_SPI1_BASE 0x40004000UL 01219 #define NRF_TWI1_BASE 0x40004000UL 01220 #define NRF_SPIS1_BASE 0x40004000UL 01221 #define NRF_SPIM1_BASE 0x40004000UL 01222 #define NRF_GPIOTE_BASE 0x40006000UL 01223 #define NRF_ADC_BASE 0x40007000UL 01224 #define NRF_TIMER0_BASE 0x40008000UL 01225 #define NRF_TIMER1_BASE 0x40009000UL 01226 #define NRF_TIMER2_BASE 0x4000A000UL 01227 #define NRF_RTC0_BASE 0x4000B000UL 01228 #define NRF_TEMP_BASE 0x4000C000UL 01229 #define NRF_RNG_BASE 0x4000D000UL 01230 #define NRF_ECB_BASE 0x4000E000UL 01231 #define NRF_AAR_BASE 0x4000F000UL 01232 #define NRF_CCM_BASE 0x4000F000UL 01233 #define NRF_WDT_BASE 0x40010000UL 01234 #define NRF_RTC1_BASE 0x40011000UL 01235 #define NRF_QDEC_BASE 0x40012000UL 01236 #define NRF_LPCOMP_BASE 0x40013000UL 01237 #define NRF_SWI_BASE 0x40014000UL 01238 #define NRF_NVMC_BASE 0x4001E000UL 01239 #define NRF_PPI_BASE 0x4001F000UL 01240 #define NRF_FICR_BASE 0x10000000UL 01241 #define NRF_UICR_BASE 0x10001000UL 01242 #define NRF_GPIO_BASE 0x50000000UL 01243 01244 01245 /* ================================================================================ */ 01246 /* ================ Peripheral declaration ================ */ 01247 /* ================================================================================ */ 01248 01249 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) 01250 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) 01251 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) 01252 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE) 01253 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) 01254 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) 01255 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) 01256 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) 01257 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) 01258 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) 01259 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) 01260 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) 01261 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) 01262 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) 01263 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) 01264 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) 01265 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) 01266 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) 01267 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) 01268 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) 01269 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) 01270 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) 01271 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) 01272 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) 01273 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) 01274 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) 01275 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) 01276 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) 01277 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) 01278 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) 01279 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) 01280 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) 01281 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) 01282 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) 01283 01284 01285 /** @} */ /* End of group Device_Peripheral_Registers */ 01286 /** @} */ /* End of group nRF51 */ 01287 /** @} */ /* End of group Nordic Semiconductor */ 01288 01289 #ifdef __cplusplus 01290 } 01291 #endif 01292 01293 01294 #endif /* nRF51_H */
Generated on Tue Jul 12 2022 21:00:16 by
1.7.2