Geremia G / mbed-src

- fix F411 F334 systeminit when HSI used - portinout always read IDR regardless of port direction

Fork of mbed-src by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h@332:e299ae530e63, 2014-09-27 (annotated)

Committer:
Geremia
Date:
Sat Sep 27 11:16:28 2014 +0000
Revision:
332:e299ae530e63
Parent:
46:bebbbd80dd87 
- fix F411 F334 systeminit when HSI used; - STMs PortInOut port.read() always read input data register (real external pin state) even if direction is output (same as other platforms)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 46:bebbbd80dd87 1 /****************************************************************************
mbed_official 46:bebbbd80dd87 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
mbed_official 46:bebbbd80dd87 3 * Project: NXP LPC8xx software example
mbed_official 46:bebbbd80dd87 4 *
mbed_official 46:bebbbd80dd87 5 * Description:
mbed_official 46:bebbbd80dd87 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
mbed_official 46:bebbbd80dd87 7 * NXP LPC800 Device Series
mbed_official 46:bebbbd80dd87 8 *
mbed_official 46:bebbbd80dd87 9 ****************************************************************************
mbed_official 46:bebbbd80dd87 10 * Software that is described herein is for illustrative purposes only
mbed_official 46:bebbbd80dd87 11 * which provides customers with programming information regarding the
mbed_official 46:bebbbd80dd87 12 * products. This software is supplied "AS IS" without any warranties.
mbed_official 46:bebbbd80dd87 13 * NXP Semiconductors assumes no responsibility or liability for the
mbed_official 46:bebbbd80dd87 14 * use of the software, conveys no license or title under any patent,
mbed_official 46:bebbbd80dd87 15 * copyright, or mask work right to the product. NXP Semiconductors
mbed_official 46:bebbbd80dd87 16 * reserves the right to make changes in the software without
mbed_official 46:bebbbd80dd87 17 * notification. NXP Semiconductors also make no representation or
mbed_official 46:bebbbd80dd87 18 * warranty that such application will be suitable for the specified
mbed_official 46:bebbbd80dd87 19 * use without further testing or modification.
mbed_official 46:bebbbd80dd87 20
mbed_official 46:bebbbd80dd87 21 * Permission to use, copy, modify, and distribute this software and its
mbed_official 46:bebbbd80dd87 22 * documentation is hereby granted, under NXP Semiconductors'
mbed_official 46:bebbbd80dd87 23 * relevant copyright in the software, without fee, provided that it
mbed_official 46:bebbbd80dd87 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
mbed_official 46:bebbbd80dd87 25 * copyright, permission, and disclaimer notice must appear in all copies of
mbed_official 46:bebbbd80dd87 26 * this code.
mbed_official 46:bebbbd80dd87 27 ****************************************************************************/
mbed_official 46:bebbbd80dd87 28 #ifndef __LPC8xx_H__
mbed_official 46:bebbbd80dd87 29 #define __LPC8xx_H__
mbed_official 46:bebbbd80dd87 30
mbed_official 46:bebbbd80dd87 31 #ifdef __cplusplus
mbed_official 46:bebbbd80dd87 32 extern "C" {
mbed_official 46:bebbbd80dd87 33 #endif
mbed_official 46:bebbbd80dd87 34
mbed_official 46:bebbbd80dd87 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
mbed_official 46:bebbbd80dd87 36 This file defines all structures and symbols for LPC8xx:
mbed_official 46:bebbbd80dd87 37 - Registers and bitfields
mbed_official 46:bebbbd80dd87 38 - peripheral base address
mbed_official 46:bebbbd80dd87 39 - PIO definitions
mbed_official 46:bebbbd80dd87 40 @{
mbed_official 46:bebbbd80dd87 41 */
mbed_official 46:bebbbd80dd87 42
mbed_official 46:bebbbd80dd87 43
mbed_official 46:bebbbd80dd87 44 /******************************************************************************/
mbed_official 46:bebbbd80dd87 45 /* Processor and Core Peripherals */
mbed_official 46:bebbbd80dd87 46 /******************************************************************************/
mbed_official 46:bebbbd80dd87 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
mbed_official 46:bebbbd80dd87 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
mbed_official 46:bebbbd80dd87 49 @{
mbed_official 46:bebbbd80dd87 50 */
mbed_official 46:bebbbd80dd87 51
mbed_official 46:bebbbd80dd87 52 /*
mbed_official 46:bebbbd80dd87 53 * ==========================================================================
mbed_official 46:bebbbd80dd87 54 * ---------- Interrupt Number Definition -----------------------------------
mbed_official 46:bebbbd80dd87 55 * ==========================================================================
mbed_official 46:bebbbd80dd87 56 */
mbed_official 46:bebbbd80dd87 57 typedef enum IRQn
mbed_official 46:bebbbd80dd87 58 {
mbed_official 46:bebbbd80dd87 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
mbed_official 46:bebbbd80dd87 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
mbed_official 46:bebbbd80dd87 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 46:bebbbd80dd87 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 46:bebbbd80dd87 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 46:bebbbd80dd87 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 46:bebbbd80dd87 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 46:bebbbd80dd87 66
mbed_official 46:bebbbd80dd87 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
mbed_official 46:bebbbd80dd87 68 SPI0_IRQn = 0, /*!< SPI0 */
mbed_official 46:bebbbd80dd87 69 SPI1_IRQn = 1, /*!< SPI1 */
mbed_official 46:bebbbd80dd87 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 71 UART0_IRQn = 3, /*!< USART0 */
mbed_official 46:bebbbd80dd87 72 UART1_IRQn = 4, /*!< USART1 */
mbed_official 46:bebbbd80dd87 73 UART2_IRQn = 5, /*!< USART2 */
mbed_official 46:bebbbd80dd87 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 76 I2C_IRQn = 8, /*!< I2C */
mbed_official 46:bebbbd80dd87 77 SCT_IRQn = 9, /*!< SCT */
mbed_official 46:bebbbd80dd87 78 MRT_IRQn = 10, /*!< MRT */
mbed_official 46:bebbbd80dd87 79 CMP_IRQn = 11, /*!< CMP */
mbed_official 46:bebbbd80dd87 80 WDT_IRQn = 12, /*!< WDT */
mbed_official 46:bebbbd80dd87 81 BOD_IRQn = 13, /*!< BOD */
mbed_official 46:bebbbd80dd87 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 83 WKT_IRQn = 15, /*!< WKT Interrupt */
mbed_official 46:bebbbd80dd87 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
mbed_official 46:bebbbd80dd87 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
mbed_official 46:bebbbd80dd87 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
mbed_official 46:bebbbd80dd87 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
mbed_official 46:bebbbd80dd87 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
mbed_official 46:bebbbd80dd87 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
mbed_official 46:bebbbd80dd87 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
mbed_official 46:bebbbd80dd87 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
mbed_official 46:bebbbd80dd87 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
mbed_official 46:bebbbd80dd87 100 } IRQn_Type;
mbed_official 46:bebbbd80dd87 101
mbed_official 46:bebbbd80dd87 102 /*
mbed_official 46:bebbbd80dd87 103 * ==========================================================================
mbed_official 46:bebbbd80dd87 104 * ----------- Processor and Core Peripheral Section ------------------------
mbed_official 46:bebbbd80dd87 105 * ==========================================================================
mbed_official 46:bebbbd80dd87 106 */
mbed_official 46:bebbbd80dd87 107
mbed_official 46:bebbbd80dd87 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
mbed_official 46:bebbbd80dd87 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 46:bebbbd80dd87 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
mbed_official 46:bebbbd80dd87 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
mbed_official 46:bebbbd80dd87 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 46:bebbbd80dd87 113
mbed_official 46:bebbbd80dd87 114 /*@}*/ /* end of group LPC8xx_CMSIS */
mbed_official 46:bebbbd80dd87 115
mbed_official 46:bebbbd80dd87 116
mbed_official 46:bebbbd80dd87 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
mbed_official 46:bebbbd80dd87 118 #include "system_LPC8xx.h" /* System Header */
mbed_official 46:bebbbd80dd87 119
mbed_official 46:bebbbd80dd87 120
mbed_official 46:bebbbd80dd87 121 /******************************************************************************/
mbed_official 46:bebbbd80dd87 122 /* Device Specific Peripheral Registers structures */
mbed_official 46:bebbbd80dd87 123 /******************************************************************************/
mbed_official 46:bebbbd80dd87 124
mbed_official 46:bebbbd80dd87 125 #if defined ( __CC_ARM )
mbed_official 46:bebbbd80dd87 126 #pragma anon_unions
mbed_official 46:bebbbd80dd87 127 #endif
mbed_official 46:bebbbd80dd87 128
mbed_official 46:bebbbd80dd87 129 /*------------- System Control (SYSCON) --------------------------------------*/
mbed_official 46:bebbbd80dd87 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
mbed_official 46:bebbbd80dd87 131 @{
mbed_official 46:bebbbd80dd87 132 */
mbed_official 46:bebbbd80dd87 133 typedef struct
mbed_official 46:bebbbd80dd87 134 {
mbed_official 46:bebbbd80dd87 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
mbed_official 46:bebbbd80dd87 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
mbed_official 46:bebbbd80dd87 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
mbed_official 46:bebbbd80dd87 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
mbed_official 46:bebbbd80dd87 139 uint32_t RESERVED0[4];
mbed_official 46:bebbbd80dd87 140
mbed_official 46:bebbbd80dd87 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
mbed_official 46:bebbbd80dd87 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
mbed_official 46:bebbbd80dd87 143 uint32_t RESERVED1[2];
mbed_official 46:bebbbd80dd87 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
mbed_official 46:bebbbd80dd87 145 uint32_t RESERVED2[3];
mbed_official 46:bebbbd80dd87 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
mbed_official 46:bebbbd80dd87 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
mbed_official 46:bebbbd80dd87 148 uint32_t RESERVED3[10];
mbed_official 46:bebbbd80dd87 149
mbed_official 46:bebbbd80dd87 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
mbed_official 46:bebbbd80dd87 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
mbed_official 46:bebbbd80dd87 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
mbed_official 46:bebbbd80dd87 153 uint32_t RESERVED4[1];
mbed_official 46:bebbbd80dd87 154
mbed_official 46:bebbbd80dd87 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
mbed_official 46:bebbbd80dd87 156 uint32_t RESERVED5[4];
mbed_official 46:bebbbd80dd87 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
mbed_official 46:bebbbd80dd87 158 uint32_t RESERVED6[18];
mbed_official 46:bebbbd80dd87 159
mbed_official 46:bebbbd80dd87 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
mbed_official 46:bebbbd80dd87 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
mbed_official 46:bebbbd80dd87 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
mbed_official 46:bebbbd80dd87 163 uint32_t RESERVED7;
mbed_official 46:bebbbd80dd87 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
mbed_official 46:bebbbd80dd87 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
mbed_official 46:bebbbd80dd87 166 uint32_t RESERVED8[1];
mbed_official 46:bebbbd80dd87 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
mbed_official 46:bebbbd80dd87 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
mbed_official 46:bebbbd80dd87 169 uint32_t RESERVED9[12];
mbed_official 46:bebbbd80dd87 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
mbed_official 46:bebbbd80dd87 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
mbed_official 46:bebbbd80dd87 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
mbed_official 46:bebbbd80dd87 173 uint32_t RESERVED10[6];
mbed_official 46:bebbbd80dd87 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
mbed_official 46:bebbbd80dd87 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
mbed_official 46:bebbbd80dd87 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
mbed_official 46:bebbbd80dd87 177 uint32_t RESERVED11[27];
mbed_official 46:bebbbd80dd87 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
mbed_official 46:bebbbd80dd87 179 uint32_t RESERVED12[3];
mbed_official 46:bebbbd80dd87 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
mbed_official 46:bebbbd80dd87 181 uint32_t RESERVED13[6];
mbed_official 46:bebbbd80dd87 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
mbed_official 46:bebbbd80dd87 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
mbed_official 46:bebbbd80dd87 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
mbed_official 46:bebbbd80dd87 185 uint32_t RESERVED14[110];
mbed_official 46:bebbbd80dd87 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
mbed_official 46:bebbbd80dd87 187 } LPC_SYSCON_TypeDef;
mbed_official 46:bebbbd80dd87 188 /*@}*/ /* end of group LPC8xx_SYSCON */
mbed_official 46:bebbbd80dd87 189
mbed_official 46:bebbbd80dd87 190
mbed_official 46:bebbbd80dd87 191 /**
mbed_official 46:bebbbd80dd87 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
mbed_official 46:bebbbd80dd87 193 */
mbed_official 46:bebbbd80dd87 194
mbed_official 46:bebbbd80dd87 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
mbed_official 46:bebbbd80dd87 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
mbed_official 46:bebbbd80dd87 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
mbed_official 46:bebbbd80dd87 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
mbed_official 46:bebbbd80dd87 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
mbed_official 46:bebbbd80dd87 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
mbed_official 46:bebbbd80dd87 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
mbed_official 46:bebbbd80dd87 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
mbed_official 46:bebbbd80dd87 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
mbed_official 46:bebbbd80dd87 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
mbed_official 46:bebbbd80dd87 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
mbed_official 46:bebbbd80dd87 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
mbed_official 46:bebbbd80dd87 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
mbed_official 46:bebbbd80dd87 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
mbed_official 46:bebbbd80dd87 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
mbed_official 46:bebbbd80dd87 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
mbed_official 46:bebbbd80dd87 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
mbed_official 46:bebbbd80dd87 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
mbed_official 46:bebbbd80dd87 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
mbed_official 46:bebbbd80dd87 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
mbed_official 46:bebbbd80dd87 215 } LPC_IOCON_TypeDef;
mbed_official 46:bebbbd80dd87 216 /*@}*/ /* end of group LPC8xx_IOCON */
mbed_official 46:bebbbd80dd87 217
mbed_official 46:bebbbd80dd87 218 /**
mbed_official 46:bebbbd80dd87 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
mbed_official 46:bebbbd80dd87 220 */
mbed_official 46:bebbbd80dd87 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
mbed_official 46:bebbbd80dd87 222 __I uint32_t RESERVED0[4];
mbed_official 46:bebbbd80dd87 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
mbed_official 46:bebbbd80dd87 224 __I uint32_t RESERVED1[3];
mbed_official 46:bebbbd80dd87 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
mbed_official 46:bebbbd80dd87 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
mbed_official 46:bebbbd80dd87 227 __I uint32_t RESERVED2;
mbed_official 46:bebbbd80dd87 228 __I uint32_t FMSW0;
mbed_official 46:bebbbd80dd87 229 } LPC_FLASHCTRL_TypeDef;
mbed_official 46:bebbbd80dd87 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
mbed_official 46:bebbbd80dd87 231
mbed_official 46:bebbbd80dd87 232
mbed_official 46:bebbbd80dd87 233 /*------------- Power Management Unit (PMU) --------------------------*/
mbed_official 46:bebbbd80dd87 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
mbed_official 46:bebbbd80dd87 235 @{
mbed_official 46:bebbbd80dd87 236 */
mbed_official 46:bebbbd80dd87 237 typedef struct
mbed_official 46:bebbbd80dd87 238 {
mbed_official 46:bebbbd80dd87 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
mbed_official 46:bebbbd80dd87 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
mbed_official 46:bebbbd80dd87 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
mbed_official 46:bebbbd80dd87 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
mbed_official 46:bebbbd80dd87 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
mbed_official 46:bebbbd80dd87 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
mbed_official 46:bebbbd80dd87 245 } LPC_PMU_TypeDef;
mbed_official 46:bebbbd80dd87 246 /*@}*/ /* end of group LPC8xx_PMU */
mbed_official 46:bebbbd80dd87 247
mbed_official 46:bebbbd80dd87 248
mbed_official 46:bebbbd80dd87 249 /*------------- Switch Matrix Port --------------------------*/
mbed_official 46:bebbbd80dd87 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
mbed_official 46:bebbbd80dd87 251 @{
mbed_official 46:bebbbd80dd87 252 */
mbed_official 46:bebbbd80dd87 253 typedef struct
mbed_official 46:bebbbd80dd87 254 {
mbed_official 46:bebbbd80dd87 255 union {
mbed_official 46:bebbbd80dd87 256 __IO uint32_t PINASSIGN[9];
mbed_official 46:bebbbd80dd87 257 struct {
mbed_official 46:bebbbd80dd87 258 __IO uint32_t PINASSIGN0;
mbed_official 46:bebbbd80dd87 259 __IO uint32_t PINASSIGN1;
mbed_official 46:bebbbd80dd87 260 __IO uint32_t PINASSIGN2;
mbed_official 46:bebbbd80dd87 261 __IO uint32_t PINASSIGN3;
mbed_official 46:bebbbd80dd87 262 __IO uint32_t PINASSIGN4;
mbed_official 46:bebbbd80dd87 263 __IO uint32_t PINASSIGN5;
mbed_official 46:bebbbd80dd87 264 __IO uint32_t PINASSIGN6;
mbed_official 46:bebbbd80dd87 265 __IO uint32_t PINASSIGN7;
mbed_official 46:bebbbd80dd87 266 __IO uint32_t PINASSIGN8;
mbed_official 46:bebbbd80dd87 267 };
mbed_official 46:bebbbd80dd87 268 };
mbed_official 46:bebbbd80dd87 269 __I uint32_t RESERVED0[103];
mbed_official 46:bebbbd80dd87 270 __IO uint32_t PINENABLE0;
mbed_official 46:bebbbd80dd87 271 } LPC_SWM_TypeDef;
mbed_official 46:bebbbd80dd87 272 /*@}*/ /* end of group LPC8xx_SWM */
mbed_official 46:bebbbd80dd87 273
mbed_official 46:bebbbd80dd87 274
mbed_official 46:bebbbd80dd87 275 // ------------------------------------------------------------------------------------------------
mbed_official 46:bebbbd80dd87 276 // ----- GPIO_PORT -----
mbed_official 46:bebbbd80dd87 277 // ------------------------------------------------------------------------------------------------
mbed_official 46:bebbbd80dd87 278
mbed_official 46:bebbbd80dd87 279 /**
mbed_official 46:bebbbd80dd87 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
mbed_official 46:bebbbd80dd87 281 */
mbed_official 46:bebbbd80dd87 282
mbed_official 46:bebbbd80dd87 283 typedef struct {
mbed_official 46:bebbbd80dd87 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
mbed_official 46:bebbbd80dd87 285 __I uint16_t RESERVED0[2039];
mbed_official 46:bebbbd80dd87 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
mbed_official 46:bebbbd80dd87 287 uint32_t RESERVED1[1006];
mbed_official 46:bebbbd80dd87 288 __IO uint32_t DIR0; /* 0x2000 */
mbed_official 46:bebbbd80dd87 289 uint32_t RESERVED2[31];
mbed_official 46:bebbbd80dd87 290 __IO uint32_t MASK0; /* 0x2080 */
mbed_official 46:bebbbd80dd87 291 uint32_t RESERVED3[31];
mbed_official 46:bebbbd80dd87 292 __IO uint32_t PIN0; /* 0x2100 */
mbed_official 46:bebbbd80dd87 293 uint32_t RESERVED4[31];
mbed_official 46:bebbbd80dd87 294 __IO uint32_t MPIN0; /* 0x2180 */
mbed_official 46:bebbbd80dd87 295 uint32_t RESERVED5[31];
mbed_official 46:bebbbd80dd87 296 __IO uint32_t SET0; /* 0x2200 */
mbed_official 46:bebbbd80dd87 297 uint32_t RESERVED6[31];
mbed_official 46:bebbbd80dd87 298 __O uint32_t CLR0; /* 0x2280 */
mbed_official 46:bebbbd80dd87 299 uint32_t RESERVED7[31];
mbed_official 46:bebbbd80dd87 300 __O uint32_t NOT0; /* 0x2300 */
mbed_official 46:bebbbd80dd87 301
mbed_official 46:bebbbd80dd87 302 } LPC_GPIO_PORT_TypeDef;
mbed_official 46:bebbbd80dd87 303
mbed_official 46:bebbbd80dd87 304
mbed_official 46:bebbbd80dd87 305 // ------------------------------------------------------------------------------------------------
mbed_official 46:bebbbd80dd87 306 // ----- PIN_INT -----
mbed_official 46:bebbbd80dd87 307 // ------------------------------------------------------------------------------------------------
mbed_official 46:bebbbd80dd87 308
mbed_official 46:bebbbd80dd87 309 /**
mbed_official 46:bebbbd80dd87 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
mbed_official 46:bebbbd80dd87 311 */
mbed_official 46:bebbbd80dd87 312
mbed_official 46:bebbbd80dd87 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
mbed_official 46:bebbbd80dd87 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
mbed_official 46:bebbbd80dd87 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
mbed_official 46:bebbbd80dd87 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
mbed_official 46:bebbbd80dd87 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
mbed_official 46:bebbbd80dd87 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
mbed_official 46:bebbbd80dd87 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
mbed_official 46:bebbbd80dd87 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
mbed_official 46:bebbbd80dd87 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
mbed_official 46:bebbbd80dd87 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
mbed_official 46:bebbbd80dd87 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
mbed_official 46:bebbbd80dd87 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
mbed_official 46:bebbbd80dd87 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
mbed_official 46:bebbbd80dd87 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
mbed_official 46:bebbbd80dd87 327 } LPC_PIN_INT_TypeDef;
mbed_official 46:bebbbd80dd87 328
mbed_official 46:bebbbd80dd87 329
mbed_official 46:bebbbd80dd87 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
mbed_official 46:bebbbd80dd87 331 /** @addtogroup LPC8xx_CRC
mbed_official 46:bebbbd80dd87 332 @{
mbed_official 46:bebbbd80dd87 333 */
mbed_official 46:bebbbd80dd87 334 typedef struct
mbed_official 46:bebbbd80dd87 335 {
mbed_official 46:bebbbd80dd87 336 __IO uint32_t MODE;
mbed_official 46:bebbbd80dd87 337 __IO uint32_t SEED;
mbed_official 46:bebbbd80dd87 338 union {
mbed_official 46:bebbbd80dd87 339 __I uint32_t SUM;
mbed_official 46:bebbbd80dd87 340 __O uint32_t WR_DATA_DWORD;
mbed_official 46:bebbbd80dd87 341 __O uint16_t WR_DATA_WORD;
mbed_official 46:bebbbd80dd87 342 uint16_t RESERVED_WORD;
mbed_official 46:bebbbd80dd87 343 __O uint8_t WR_DATA_BYTE;
mbed_official 46:bebbbd80dd87 344 uint8_t RESERVED_BYTE[3];
mbed_official 46:bebbbd80dd87 345 };
mbed_official 46:bebbbd80dd87 346 } LPC_CRC_TypeDef;
mbed_official 46:bebbbd80dd87 347 /*@}*/ /* end of group LPC8xx_CRC */
mbed_official 46:bebbbd80dd87 348
mbed_official 46:bebbbd80dd87 349 /*------------- Comparator (CMP) --------------------------------------------------*/
mbed_official 46:bebbbd80dd87 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
mbed_official 46:bebbbd80dd87 351 @{
mbed_official 46:bebbbd80dd87 352 */
mbed_official 46:bebbbd80dd87 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
mbed_official 46:bebbbd80dd87 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
mbed_official 46:bebbbd80dd87 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
mbed_official 46:bebbbd80dd87 356 } LPC_CMP_TypeDef;
mbed_official 46:bebbbd80dd87 357 /*@}*/ /* end of group LPC8xx_CMP */
mbed_official 46:bebbbd80dd87 358
mbed_official 46:bebbbd80dd87 359
mbed_official 46:bebbbd80dd87 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
mbed_official 46:bebbbd80dd87 361 /** @addtogroup LPC8xx_WKT
mbed_official 46:bebbbd80dd87 362 @{
mbed_official 46:bebbbd80dd87 363 */
mbed_official 46:bebbbd80dd87 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
mbed_official 46:bebbbd80dd87 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
mbed_official 46:bebbbd80dd87 366 uint32_t Reserved[2];
mbed_official 46:bebbbd80dd87 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
mbed_official 46:bebbbd80dd87 368 } LPC_WKT_TypeDef;
mbed_official 46:bebbbd80dd87 369 /*@}*/ /* end of group LPC8xx_WKT */
mbed_official 46:bebbbd80dd87 370
mbed_official 46:bebbbd80dd87 371
mbed_official 46:bebbbd80dd87 372 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
mbed_official 46:bebbbd80dd87 373 typedef struct {
mbed_official 46:bebbbd80dd87 374 __IO uint32_t INTVAL;
mbed_official 46:bebbbd80dd87 375 __IO uint32_t TIMER;
mbed_official 46:bebbbd80dd87 376 __IO uint32_t CTRL;
mbed_official 46:bebbbd80dd87 377 __IO uint32_t STAT;
mbed_official 46:bebbbd80dd87 378 } MRT_Channel_cfg_Type;
mbed_official 46:bebbbd80dd87 379
mbed_official 46:bebbbd80dd87 380 typedef struct {
mbed_official 46:bebbbd80dd87 381 MRT_Channel_cfg_Type Channel[4];
mbed_official 46:bebbbd80dd87 382 uint32_t Reserved0[1];
mbed_official 46:bebbbd80dd87 383 __IO uint32_t IDLE_CH;
mbed_official 46:bebbbd80dd87 384 __IO uint32_t IRQ_FLAG;
mbed_official 46:bebbbd80dd87 385 } LPC_MRT_TypeDef;
mbed_official 46:bebbbd80dd87 386
mbed_official 46:bebbbd80dd87 387
mbed_official 46:bebbbd80dd87 388 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
mbed_official 46:bebbbd80dd87 389 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
mbed_official 46:bebbbd80dd87 390 @{
mbed_official 46:bebbbd80dd87 391 */
mbed_official 46:bebbbd80dd87 392 /**
mbed_official 46:bebbbd80dd87 393 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
mbed_official 46:bebbbd80dd87 394 */
mbed_official 46:bebbbd80dd87 395 typedef struct
mbed_official 46:bebbbd80dd87 396 {
mbed_official 46:bebbbd80dd87 397 __IO uint32_t CFG; /* 0x00 */
mbed_official 46:bebbbd80dd87 398 __IO uint32_t CTRL;
mbed_official 46:bebbbd80dd87 399 __IO uint32_t STAT;
mbed_official 46:bebbbd80dd87 400 __IO uint32_t INTENSET;
mbed_official 46:bebbbd80dd87 401 __O uint32_t INTENCLR; /* 0x10 */
mbed_official 46:bebbbd80dd87 402 __I uint32_t RXDATA;
mbed_official 46:bebbbd80dd87 403 __I uint32_t RXDATA_STAT;
mbed_official 46:bebbbd80dd87 404 __IO uint32_t TXDATA;
mbed_official 46:bebbbd80dd87 405 __IO uint32_t BRG; /* 0x20 */
mbed_official 46:bebbbd80dd87 406 __IO uint32_t INTSTAT;
mbed_official 46:bebbbd80dd87 407 } LPC_USART_TypeDef;
mbed_official 46:bebbbd80dd87 408
mbed_official 46:bebbbd80dd87 409 /*@}*/ /* end of group LPC8xx_USART */
mbed_official 46:bebbbd80dd87 410
mbed_official 46:bebbbd80dd87 411
mbed_official 46:bebbbd80dd87 412 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
mbed_official 46:bebbbd80dd87 413 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
mbed_official 46:bebbbd80dd87 414 @{
mbed_official 46:bebbbd80dd87 415 */
mbed_official 46:bebbbd80dd87 416 typedef struct
mbed_official 46:bebbbd80dd87 417 {
mbed_official 46:bebbbd80dd87 418 __IO uint32_t CFG; /* 0x00 */
mbed_official 46:bebbbd80dd87 419 __IO uint32_t DLY;
mbed_official 46:bebbbd80dd87 420 __IO uint32_t STAT;
mbed_official 46:bebbbd80dd87 421 __IO uint32_t INTENSET;
mbed_official 46:bebbbd80dd87 422 __O uint32_t INTENCLR; /* 0x10 */
mbed_official 46:bebbbd80dd87 423 __I uint32_t RXDAT;
mbed_official 46:bebbbd80dd87 424 __IO uint32_t TXDATCTL;
mbed_official 46:bebbbd80dd87 425 __IO uint32_t TXDAT;
mbed_official 46:bebbbd80dd87 426 __IO uint32_t TXCTRL; /* 0x20 */
mbed_official 46:bebbbd80dd87 427 __IO uint32_t DIV;
mbed_official 46:bebbbd80dd87 428 __I uint32_t INTSTAT;
mbed_official 46:bebbbd80dd87 429 } LPC_SPI_TypeDef;
mbed_official 46:bebbbd80dd87 430 /*@}*/ /* end of group LPC8xx_SPI */
mbed_official 46:bebbbd80dd87 431
mbed_official 46:bebbbd80dd87 432
mbed_official 46:bebbbd80dd87 433 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
mbed_official 46:bebbbd80dd87 434 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
mbed_official 46:bebbbd80dd87 435 @{
mbed_official 46:bebbbd80dd87 436 */
mbed_official 46:bebbbd80dd87 437 typedef struct
mbed_official 46:bebbbd80dd87 438 {
mbed_official 46:bebbbd80dd87 439 __IO uint32_t CFG; /* 0x00 */
mbed_official 46:bebbbd80dd87 440 __IO uint32_t STAT;
mbed_official 46:bebbbd80dd87 441 __IO uint32_t INTENSET;
mbed_official 46:bebbbd80dd87 442 __O uint32_t INTENCLR;
mbed_official 46:bebbbd80dd87 443 __IO uint32_t TIMEOUT; /* 0x10 */
mbed_official 46:bebbbd80dd87 444 __IO uint32_t DIV;
mbed_official 46:bebbbd80dd87 445 __IO uint32_t INTSTAT;
mbed_official 46:bebbbd80dd87 446 uint32_t Reserved0[1];
mbed_official 46:bebbbd80dd87 447 __IO uint32_t MSTCTL; /* 0x20 */
mbed_official 46:bebbbd80dd87 448 __IO uint32_t MSTTIME;
mbed_official 46:bebbbd80dd87 449 __IO uint32_t MSTDAT;
mbed_official 46:bebbbd80dd87 450 uint32_t Reserved1[5];
mbed_official 46:bebbbd80dd87 451 __IO uint32_t SLVCTL; /* 0x40 */
mbed_official 46:bebbbd80dd87 452 __IO uint32_t SLVDAT;
mbed_official 46:bebbbd80dd87 453 __IO uint32_t SLVADR0;
mbed_official 46:bebbbd80dd87 454 __IO uint32_t SLVADR1;
mbed_official 46:bebbbd80dd87 455 __IO uint32_t SLVADR2; /* 0x50 */
mbed_official 46:bebbbd80dd87 456 __IO uint32_t SLVADR3;
mbed_official 46:bebbbd80dd87 457 __IO uint32_t SLVQUAL0;
mbed_official 46:bebbbd80dd87 458 uint32_t Reserved2[9];
mbed_official 46:bebbbd80dd87 459 __I uint32_t MONRXDAT; /* 0x80 */
mbed_official 46:bebbbd80dd87 460 } LPC_I2C_TypeDef;
mbed_official 46:bebbbd80dd87 461
mbed_official 46:bebbbd80dd87 462 /*@}*/ /* end of group LPC8xx_I2C */
mbed_official 46:bebbbd80dd87 463
mbed_official 46:bebbbd80dd87 464 /**
mbed_official 46:bebbbd80dd87 465 * @brief State Configurable Timer (SCT) (SCT)
mbed_official 46:bebbbd80dd87 466 */
mbed_official 46:bebbbd80dd87 467
mbed_official 46:bebbbd80dd87 468 /**
mbed_official 46:bebbbd80dd87 469 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
mbed_official 46:bebbbd80dd87 470 */
mbed_official 46:bebbbd80dd87 471
mbed_official 46:bebbbd80dd87 472 #define CONFIG_SCT_nEV (6) /* Number of events */
mbed_official 46:bebbbd80dd87 473 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
mbed_official 46:bebbbd80dd87 474 #define CONFIG_SCT_nOU (4) /* Number of outputs */
mbed_official 46:bebbbd80dd87 475
mbed_official 46:bebbbd80dd87 476 typedef struct
mbed_official 46:bebbbd80dd87 477 {
mbed_official 46:bebbbd80dd87 478 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
mbed_official 46:bebbbd80dd87 479 union {
mbed_official 46:bebbbd80dd87 480 __IO uint32_t CTRL_U; /* 0x004 Control Register */
mbed_official 46:bebbbd80dd87 481 struct {
mbed_official 46:bebbbd80dd87 482 __IO uint16_t CTRL_L; /* 0x004 low control register */
mbed_official 46:bebbbd80dd87 483 __IO uint16_t CTRL_H; /* 0x006 high control register */
mbed_official 46:bebbbd80dd87 484 };
mbed_official 46:bebbbd80dd87 485 };
mbed_official 46:bebbbd80dd87 486 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
mbed_official 46:bebbbd80dd87 487 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
mbed_official 46:bebbbd80dd87 488 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
mbed_official 46:bebbbd80dd87 489 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
mbed_official 46:bebbbd80dd87 490 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
mbed_official 46:bebbbd80dd87 491 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
mbed_official 46:bebbbd80dd87 492 __IO uint16_t START_L; /* 0x014 start register for counter L */
mbed_official 46:bebbbd80dd87 493 __IO uint16_t START_H; /* 0x016 start register for counter H */
mbed_official 46:bebbbd80dd87 494 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
mbed_official 46:bebbbd80dd87 495 union {
mbed_official 46:bebbbd80dd87 496 __IO uint32_t COUNT_U; /* 0x040 counter register */
mbed_official 46:bebbbd80dd87 497 struct {
mbed_official 46:bebbbd80dd87 498 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
mbed_official 46:bebbbd80dd87 499 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
mbed_official 46:bebbbd80dd87 500 };
mbed_official 46:bebbbd80dd87 501 };
mbed_official 46:bebbbd80dd87 502 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
mbed_official 46:bebbbd80dd87 503 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
mbed_official 46:bebbbd80dd87 504 __I uint32_t INPUT; /* 0x048 input register */
mbed_official 46:bebbbd80dd87 505 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
mbed_official 46:bebbbd80dd87 506 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
mbed_official 46:bebbbd80dd87 507 __IO uint32_t OUTPUT; /* 0x050 output register */
mbed_official 46:bebbbd80dd87 508 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
mbed_official 46:bebbbd80dd87 509 __IO uint32_t RES; /* 0x058 conflict resolution register */
mbed_official 46:bebbbd80dd87 510 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
mbed_official 46:bebbbd80dd87 511 __IO uint32_t EVEN; /* 0x0F0 event enable register */
mbed_official 46:bebbbd80dd87 512 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
mbed_official 46:bebbbd80dd87 513 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
mbed_official 46:bebbbd80dd87 514 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
mbed_official 46:bebbbd80dd87 515
mbed_official 46:bebbbd80dd87 516 union {
mbed_official 46:bebbbd80dd87 517 __IO union { /* 0x100-... Match / Capture value */
mbed_official 46:bebbbd80dd87 518 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
mbed_official 46:bebbbd80dd87 519 struct {
mbed_official 46:bebbbd80dd87 520 uint16_t L; /* SCTMATCH[i].L Access to L value */
mbed_official 46:bebbbd80dd87 521 uint16_t H; /* SCTMATCH[i].H Access to H value */
mbed_official 46:bebbbd80dd87 522 };
mbed_official 46:bebbbd80dd87 523 } MATCH[CONFIG_SCT_nRG];
mbed_official 46:bebbbd80dd87 524 __I union {
mbed_official 46:bebbbd80dd87 525 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
mbed_official 46:bebbbd80dd87 526 struct {
mbed_official 46:bebbbd80dd87 527 uint16_t L; /* SCTCAP[i].L Access to H value */
mbed_official 46:bebbbd80dd87 528 uint16_t H; /* SCTCAP[i].H Access to H value */
mbed_official 46:bebbbd80dd87 529 };
mbed_official 46:bebbbd80dd87 530 } CAP[CONFIG_SCT_nRG];
mbed_official 46:bebbbd80dd87 531 };
mbed_official 46:bebbbd80dd87 532
mbed_official 46:bebbbd80dd87 533
mbed_official 46:bebbbd80dd87 534 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
mbed_official 46:bebbbd80dd87 535
mbed_official 46:bebbbd80dd87 536 union {
mbed_official 46:bebbbd80dd87 537 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
mbed_official 46:bebbbd80dd87 538 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
mbed_official 46:bebbbd80dd87 539 };
mbed_official 46:bebbbd80dd87 540 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
mbed_official 46:bebbbd80dd87 541 union {
mbed_official 46:bebbbd80dd87 542 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
mbed_official 46:bebbbd80dd87 543 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
mbed_official 46:bebbbd80dd87 544 };
mbed_official 46:bebbbd80dd87 545
mbed_official 46:bebbbd80dd87 546 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
mbed_official 46:bebbbd80dd87 547
mbed_official 46:bebbbd80dd87 548
mbed_official 46:bebbbd80dd87 549 union {
mbed_official 46:bebbbd80dd87 550 __IO union { /* 0x200-... Match Reload / Capture Control value */
mbed_official 46:bebbbd80dd87 551 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
mbed_official 46:bebbbd80dd87 552 struct {
mbed_official 46:bebbbd80dd87 553 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
mbed_official 46:bebbbd80dd87 554 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
mbed_official 46:bebbbd80dd87 555 };
mbed_official 46:bebbbd80dd87 556 } MATCHREL[CONFIG_SCT_nRG];
mbed_official 46:bebbbd80dd87 557 __IO union {
mbed_official 46:bebbbd80dd87 558 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
mbed_official 46:bebbbd80dd87 559 struct {
mbed_official 46:bebbbd80dd87 560 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
mbed_official 46:bebbbd80dd87 561 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
mbed_official 46:bebbbd80dd87 562 };
mbed_official 46:bebbbd80dd87 563 } CAPCTRL[CONFIG_SCT_nRG];
mbed_official 46:bebbbd80dd87 564 };
mbed_official 46:bebbbd80dd87 565
mbed_official 46:bebbbd80dd87 566 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
mbed_official 46:bebbbd80dd87 567
mbed_official 46:bebbbd80dd87 568 union {
mbed_official 46:bebbbd80dd87 569 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
mbed_official 46:bebbbd80dd87 570 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
mbed_official 46:bebbbd80dd87 571 };
mbed_official 46:bebbbd80dd87 572 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
mbed_official 46:bebbbd80dd87 573 union {
mbed_official 46:bebbbd80dd87 574 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
mbed_official 46:bebbbd80dd87 575 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
mbed_official 46:bebbbd80dd87 576 };
mbed_official 46:bebbbd80dd87 577 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
mbed_official 46:bebbbd80dd87 578
mbed_official 46:bebbbd80dd87 579 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
mbed_official 46:bebbbd80dd87 580 uint32_t STATE; /* Event State Register */
mbed_official 46:bebbbd80dd87 581 uint32_t CTRL; /* Event Control Register */
mbed_official 46:bebbbd80dd87 582 } EVENT[CONFIG_SCT_nEV];
mbed_official 46:bebbbd80dd87 583
mbed_official 46:bebbbd80dd87 584 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
mbed_official 46:bebbbd80dd87 585
mbed_official 46:bebbbd80dd87 586 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
mbed_official 46:bebbbd80dd87 587 uint32_t SET; /* Output n Set Register */
mbed_official 46:bebbbd80dd87 588 uint32_t CLR; /* Output n Clear Register */
mbed_official 46:bebbbd80dd87 589 } OUT[CONFIG_SCT_nOU];
mbed_official 46:bebbbd80dd87 590
mbed_official 46:bebbbd80dd87 591 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
mbed_official 46:bebbbd80dd87 592
mbed_official 46:bebbbd80dd87 593 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
mbed_official 46:bebbbd80dd87 594
mbed_official 46:bebbbd80dd87 595 } LPC_SCT_TypeDef;
mbed_official 46:bebbbd80dd87 596 /*@}*/ /* end of group LPC8xx_SCT */
mbed_official 46:bebbbd80dd87 597
mbed_official 46:bebbbd80dd87 598
mbed_official 46:bebbbd80dd87 599 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
mbed_official 46:bebbbd80dd87 600 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
mbed_official 46:bebbbd80dd87 601 @{
mbed_official 46:bebbbd80dd87 602 */
mbed_official 46:bebbbd80dd87 603 typedef struct
mbed_official 46:bebbbd80dd87 604 {
mbed_official 46:bebbbd80dd87 605 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
mbed_official 46:bebbbd80dd87 606 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
mbed_official 46:bebbbd80dd87 607 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
mbed_official 46:bebbbd80dd87 608 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
mbed_official 46:bebbbd80dd87 609 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
mbed_official 46:bebbbd80dd87 610 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
mbed_official 46:bebbbd80dd87 611 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
mbed_official 46:bebbbd80dd87 612 } LPC_WWDT_TypeDef;
mbed_official 46:bebbbd80dd87 613 /*@}*/ /* end of group LPC8xx_WDT */
mbed_official 46:bebbbd80dd87 614
mbed_official 46:bebbbd80dd87 615
mbed_official 46:bebbbd80dd87 616 #if defined ( __CC_ARM )
mbed_official 46:bebbbd80dd87 617 #pragma no_anon_unions
mbed_official 46:bebbbd80dd87 618 #endif
mbed_official 46:bebbbd80dd87 619
mbed_official 46:bebbbd80dd87 620 /******************************************************************************/
mbed_official 46:bebbbd80dd87 621 /* Peripheral memory map */
mbed_official 46:bebbbd80dd87 622 /******************************************************************************/
mbed_official 46:bebbbd80dd87 623 /* Base addresses */
mbed_official 46:bebbbd80dd87 624 #define LPC_FLASH_BASE (0x00000000UL)
mbed_official 46:bebbbd80dd87 625 #define LPC_RAM_BASE (0x10000000UL)
mbed_official 46:bebbbd80dd87 626 #define LPC_ROM_BASE (0x1FFF0000UL)
mbed_official 46:bebbbd80dd87 627 #define LPC_APB0_BASE (0x40000000UL)
mbed_official 46:bebbbd80dd87 628 #define LPC_AHB_BASE (0x50000000UL)
mbed_official 46:bebbbd80dd87 629
mbed_official 46:bebbbd80dd87 630 /* APB0 peripherals */
mbed_official 46:bebbbd80dd87 631 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
mbed_official 46:bebbbd80dd87 632 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
mbed_official 46:bebbbd80dd87 633 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
mbed_official 46:bebbbd80dd87 634 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
mbed_official 46:bebbbd80dd87 635 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
mbed_official 46:bebbbd80dd87 636 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
mbed_official 46:bebbbd80dd87 637
mbed_official 46:bebbbd80dd87 638 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
mbed_official 46:bebbbd80dd87 639 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
mbed_official 46:bebbbd80dd87 640 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
mbed_official 46:bebbbd80dd87 641 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
mbed_official 46:bebbbd80dd87 642 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
mbed_official 46:bebbbd80dd87 643 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
mbed_official 46:bebbbd80dd87 644 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
mbed_official 46:bebbbd80dd87 645 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
mbed_official 46:bebbbd80dd87 646 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
mbed_official 46:bebbbd80dd87 647
mbed_official 46:bebbbd80dd87 648 /* AHB peripherals */
mbed_official 46:bebbbd80dd87 649 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
mbed_official 46:bebbbd80dd87 650 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
mbed_official 46:bebbbd80dd87 651
mbed_official 46:bebbbd80dd87 652 #define LPC_GPIO_PORT_BASE (0xA0000000)
mbed_official 46:bebbbd80dd87 653 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
mbed_official 46:bebbbd80dd87 654
mbed_official 46:bebbbd80dd87 655 /******************************************************************************/
mbed_official 46:bebbbd80dd87 656 /* Peripheral declaration */
mbed_official 46:bebbbd80dd87 657 /******************************************************************************/
mbed_official 46:bebbbd80dd87 658 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
mbed_official 46:bebbbd80dd87 659 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
mbed_official 46:bebbbd80dd87 660
mbed_official 46:bebbbd80dd87 661
mbed_official 46:bebbbd80dd87 662 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
mbed_official 46:bebbbd80dd87 663 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
mbed_official 46:bebbbd80dd87 664 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
mbed_official 46:bebbbd80dd87 665 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
mbed_official 46:bebbbd80dd87 666
mbed_official 46:bebbbd80dd87 667 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
mbed_official 46:bebbbd80dd87 668 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
mbed_official 46:bebbbd80dd87 669 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
mbed_official 46:bebbbd80dd87 670 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
mbed_official 46:bebbbd80dd87 671 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
mbed_official 46:bebbbd80dd87 672 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
mbed_official 46:bebbbd80dd87 673 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
mbed_official 46:bebbbd80dd87 674 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
mbed_official 46:bebbbd80dd87 675 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
mbed_official 46:bebbbd80dd87 676
mbed_official 46:bebbbd80dd87 677 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
mbed_official 46:bebbbd80dd87 678 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
mbed_official 46:bebbbd80dd87 679
mbed_official 46:bebbbd80dd87 680 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
mbed_official 46:bebbbd80dd87 681 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
mbed_official 46:bebbbd80dd87 682
mbed_official 46:bebbbd80dd87 683 #ifdef __cplusplus
mbed_official 46:bebbbd80dd87 684 }
mbed_official 46:bebbbd80dd87 685 #endif
mbed_official 46:bebbbd80dd87 686
mbed_official 46:bebbbd80dd87 687 #endif /* __LPC8xx_H__ */