mbed-src - - fix F411 F334 systeminit when HSI used - portin…

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- fix F411 F334 systeminit when HSI used - portinout always read IDR regardless of port direction

targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@332:e299ae530e63, 2014-09-27 (annotated)

Committer:: Geremia
Date:: Sat Sep 27 11:16:28 2014 +0000
Revision:: 332:e299ae530e63
Parent:: 174:8bb9f3a33240

- fix F411 F334 systeminit when HSI used; - STMs PortInOut port.read() always read input data register (real external pin state) even if direction is output (same as other platforms)

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	174:8bb9f3a33240	1
mbed_official	174:8bb9f3a33240	2	/**************************************************************************************************//
mbed_official	174:8bb9f3a33240	3	* @file LPC11U6x.h
mbed_official	174:8bb9f3a33240	4	*
mbed_official	174:8bb9f3a33240	5	* @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
mbed_official	174:8bb9f3a33240	6	* LPC11U6x from .
mbed_official	174:8bb9f3a33240	7	*
mbed_official	174:8bb9f3a33240	8	* @version V0.4
mbed_official	174:8bb9f3a33240	9	* @date 22. October 2013
mbed_official	174:8bb9f3a33240	10	*
mbed_official	174:8bb9f3a33240	11	* @note Generated with SVDConv V2.81a
mbed_official	174:8bb9f3a33240	12	* from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
mbed_official	174:8bb9f3a33240	13	*
mbed_official	174:8bb9f3a33240	14	* modified by Keil
mbed_official	174:8bb9f3a33240	15	*******************************************************************************************************/
mbed_official	174:8bb9f3a33240	16
mbed_official	174:8bb9f3a33240	17
mbed_official	174:8bb9f3a33240	18
mbed_official	174:8bb9f3a33240	19	/** @addtogroup (null)
mbed_official	174:8bb9f3a33240	20	* @{
mbed_official	174:8bb9f3a33240	21	*/
mbed_official	174:8bb9f3a33240	22
mbed_official	174:8bb9f3a33240	23	/** @addtogroup LPC11U6x
mbed_official	174:8bb9f3a33240	24	* @{
mbed_official	174:8bb9f3a33240	25	*/
mbed_official	174:8bb9f3a33240	26
mbed_official	174:8bb9f3a33240	27	#ifndef LPC11U6X_H
mbed_official	174:8bb9f3a33240	28	#define LPC11U6X_H
mbed_official	174:8bb9f3a33240	29
mbed_official	174:8bb9f3a33240	30	#ifdef __cplusplus
mbed_official	174:8bb9f3a33240	31	extern "C" {
mbed_official	174:8bb9f3a33240	32	#endif
mbed_official	174:8bb9f3a33240	33
mbed_official	174:8bb9f3a33240	34
mbed_official	174:8bb9f3a33240	35	/* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official	174:8bb9f3a33240	36
mbed_official	174:8bb9f3a33240	37	typedef enum {
mbed_official	174:8bb9f3a33240	38	/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
mbed_official	174:8bb9f3a33240	39	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
mbed_official	174:8bb9f3a33240	40	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
mbed_official	174:8bb9f3a33240	41	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
mbed_official	174:8bb9f3a33240	42
mbed_official	174:8bb9f3a33240	43
mbed_official	174:8bb9f3a33240	44
mbed_official	174:8bb9f3a33240	45	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
mbed_official	174:8bb9f3a33240	46
mbed_official	174:8bb9f3a33240	47
mbed_official	174:8bb9f3a33240	48	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
mbed_official	174:8bb9f3a33240	49	SysTick_IRQn = -1, /!< 15 System Tick Timer /
mbed_official	174:8bb9f3a33240	50	/* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
mbed_official	174:8bb9f3a33240	51	PIN_INT0_IRQn = 0, /!< 0 PIN_INT0 /
mbed_official	174:8bb9f3a33240	52	PIN_INT1_IRQn = 1, /!< 1 PIN_INT1 /
mbed_official	174:8bb9f3a33240	53	PIN_INT2_IRQn = 2, /!< 2 PIN_INT2 /
mbed_official	174:8bb9f3a33240	54	PIN_INT3_IRQn = 3, /!< 3 PIN_INT3 /
mbed_official	174:8bb9f3a33240	55	PIN_INT4_IRQn = 4, /!< 4 PIN_INT4 /
mbed_official	174:8bb9f3a33240	56	PIN_INT5_IRQn = 5, /!< 5 PIN_INT5 /
mbed_official	174:8bb9f3a33240	57	PIN_INT6_IRQn = 6, /!< 6 PIN_INT6 /
mbed_official	174:8bb9f3a33240	58	PIN_INT7_IRQn = 7, /!< 7 PIN_INT7 /
mbed_official	174:8bb9f3a33240	59	GINT0_IRQn = 8, /!< 8 GINT0 /
mbed_official	174:8bb9f3a33240	60	GINT1_IRQn = 9, /!< 9 GINT1 /
mbed_official	174:8bb9f3a33240	61	I2C1_IRQn = 10, /!< 10 I2C1 /
mbed_official	174:8bb9f3a33240	62	USART1_4_IRQn = 11, /!< 11 USART1_4 /
mbed_official	174:8bb9f3a33240	63	USART2_3_IRQn = 12, /!< 12 USART2_3 /
mbed_official	174:8bb9f3a33240	64	SCT0_1_IRQn = 13, /!< 13 SCT0_1 /
mbed_official	174:8bb9f3a33240	65	SSP1_IRQn = 14, /!< 14 SSP1 /
mbed_official	174:8bb9f3a33240	66	I2C0_IRQn = 15, /!< 15 I2C0 /
mbed_official	174:8bb9f3a33240	67	CT16B0_IRQn = 16, /!< 16 CT16B0 /
mbed_official	174:8bb9f3a33240	68	CT16B1_IRQn = 17, /!< 17 CT16B1 /
mbed_official	174:8bb9f3a33240	69	CT32B0_IRQn = 18, /!< 18 CT32B0 /
mbed_official	174:8bb9f3a33240	70	CT32B1_IRQn = 19, /!< 19 CT32B1 /
mbed_official	174:8bb9f3a33240	71	SSP0_IRQn = 20, /!< 20 SSP0 /
mbed_official	174:8bb9f3a33240	72	USART0_IRQn = 21, /!< 21 USART0 /
mbed_official	174:8bb9f3a33240	73	USB_IRQn = 22, /!< 22 USB /
mbed_official	174:8bb9f3a33240	74	USB_FIQ_IRQn = 23, /!< 23 USB_FIQ /
mbed_official	174:8bb9f3a33240	75	ADC_A_IRQn = 24, /!< 24 ADC_A /
mbed_official	174:8bb9f3a33240	76	RTC_IRQn = 25, /!< 25 RTC /
mbed_official	174:8bb9f3a33240	77	BOD_WDT_IRQn = 26, /!< 26 BOD_WDT /
mbed_official	174:8bb9f3a33240	78	FLASH_IRQn = 27, /!< 27 FLASH /
mbed_official	174:8bb9f3a33240	79	DMA_IRQn = 28, /!< 28 DMA /
mbed_official	174:8bb9f3a33240	80	ADC_B_IRQn = 29, /!< 29 ADC_B /
mbed_official	174:8bb9f3a33240	81	USBWAKEUP_IRQn = 30 /!< 30 USBWAKEUP /
mbed_official	174:8bb9f3a33240	82	} IRQn_Type;
mbed_official	174:8bb9f3a33240	83
mbed_official	174:8bb9f3a33240	84
mbed_official	174:8bb9f3a33240	85	/** @addtogroup Configuration_of_CMSIS
mbed_official	174:8bb9f3a33240	86	* @{
mbed_official	174:8bb9f3a33240	87	*/
mbed_official	174:8bb9f3a33240	88
mbed_official	174:8bb9f3a33240	89
mbed_official	174:8bb9f3a33240	90	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	91	/* ================ Processor and Core Peripheral Section ================ */
mbed_official	174:8bb9f3a33240	92	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	93
mbed_official	174:8bb9f3a33240	94	/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
mbed_official	174:8bb9f3a33240	95	#define __CM0PLUS_REV 0x0000 /!< Cortex-M0PLUS Core Revision /
mbed_official	174:8bb9f3a33240	96	#define __MPU_PRESENT 0 /!< MPU present or not /
mbed_official	174:8bb9f3a33240	97	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
mbed_official	174:8bb9f3a33240	98	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	174:8bb9f3a33240	99	#define __VTOR_PRESENT 1 /!< Set to 1 if CPU supports Vector Table Offset Register /
mbed_official	174:8bb9f3a33240	100	/** @} / / End of group Configuration_of_CMSIS */
mbed_official	174:8bb9f3a33240	101
mbed_official	174:8bb9f3a33240	102	#include "core_cm0plus.h" /!< Cortex-M0PLUS processor and core peripherals /
mbed_official	174:8bb9f3a33240	103	#include "system_LPC11U6x.h" /!< LPC11U6x System /
mbed_official	174:8bb9f3a33240	104
mbed_official	174:8bb9f3a33240	105
mbed_official	174:8bb9f3a33240	106	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	107	/* ================ Device Specific Peripheral Section ================ */
mbed_official	174:8bb9f3a33240	108	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	109
mbed_official	174:8bb9f3a33240	110
mbed_official	174:8bb9f3a33240	111	/** @addtogroup Device_Peripheral_Registers
mbed_official	174:8bb9f3a33240	112	* @{
mbed_official	174:8bb9f3a33240	113	*/
mbed_official	174:8bb9f3a33240	114
mbed_official	174:8bb9f3a33240	115
mbed_official	174:8bb9f3a33240	116	/* ------------------- Start of section using anonymous unions ------------------ */
mbed_official	174:8bb9f3a33240	117	#if defined(__CC_ARM)
mbed_official	174:8bb9f3a33240	118	#pragma push
mbed_official	174:8bb9f3a33240	119	#pragma anon_unions
mbed_official	174:8bb9f3a33240	120	#elif defined(__ICCARM__)
mbed_official	174:8bb9f3a33240	121	#pragma language=extended
mbed_official	174:8bb9f3a33240	122	#elif defined(__GNUC__)
mbed_official	174:8bb9f3a33240	123	/* anonymous unions are enabled by default */
mbed_official	174:8bb9f3a33240	124	#elif defined(__TMS470__)
mbed_official	174:8bb9f3a33240	125	/* anonymous unions are enabled by default */
mbed_official	174:8bb9f3a33240	126	#elif defined(__TASKING__)
mbed_official	174:8bb9f3a33240	127	#pragma warning 586
mbed_official	174:8bb9f3a33240	128	#else
mbed_official	174:8bb9f3a33240	129	#warning Not supported compiler type
mbed_official	174:8bb9f3a33240	130	#endif
mbed_official	174:8bb9f3a33240	131
mbed_official	174:8bb9f3a33240	132
mbed_official	174:8bb9f3a33240	133
mbed_official	174:8bb9f3a33240	134	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	135	/* ================ I2C0 ================ */
mbed_official	174:8bb9f3a33240	136	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	137
mbed_official	174:8bb9f3a33240	138
mbed_official	174:8bb9f3a33240	139	/**
mbed_official	174:8bb9f3a33240	140	* @brief I2C-bus controller (I2C0)
mbed_official	174:8bb9f3a33240	141	*/
mbed_official	174:8bb9f3a33240	142
mbed_official	174:8bb9f3a33240	143	typedef struct { /!< I2C0 Structure /
mbed_official	174:8bb9f3a33240	144	__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
mbed_official	174:8bb9f3a33240	145	this register, the corresponding bit in the I2C control register
mbed_official	174:8bb9f3a33240	146	is set. Writing a zero has no effect on the corresponding bit
mbed_official	174:8bb9f3a33240	147	in the I2C control register. */
mbed_official	174:8bb9f3a33240	148	__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
mbed_official	174:8bb9f3a33240	149	detailed status codes that allow software to determine the next
mbed_official	174:8bb9f3a33240	150	action needed. */
mbed_official	174:8bb9f3a33240	151	__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
mbed_official	174:8bb9f3a33240	152	to be transmitted is written to this register. During master
mbed_official	174:8bb9f3a33240	153	or slave receive mode, data that has been received may be read
mbed_official	174:8bb9f3a33240	154	from this register. */
mbed_official	174:8bb9f3a33240	155	__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
mbed_official	174:8bb9f3a33240	156	for operation of the I2C interface in slave mode, and is not
mbed_official	174:8bb9f3a33240	157	used in master mode. The least significant bit determines whether
mbed_official	174:8bb9f3a33240	158	a slave responds to the General Call address. */
mbed_official	174:8bb9f3a33240	159	__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
mbed_official	174:8bb9f3a33240	160	time of the I2C clock. */
mbed_official	174:8bb9f3a33240	161	__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
mbed_official	174:8bb9f3a33240	162	of the I2C clock. I2nSCLL and I2nSCLH together determine the
mbed_official	174:8bb9f3a33240	163	clock frequency generated by an I2C master and certain times
mbed_official	174:8bb9f3a33240	164	used in slave mode. */
mbed_official	174:8bb9f3a33240	165	__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
mbed_official	174:8bb9f3a33240	166	this register, the corresponding bit in the I2C control register
mbed_official	174:8bb9f3a33240	167	is cleared. Writing a zero has no effect on the corresponding
mbed_official	174:8bb9f3a33240	168	bit in the I2C control register. */
mbed_official	174:8bb9f3a33240	169	__IO uint32_t MMCTRL; /!< Monitor mode control register. /
mbed_official	174:8bb9f3a33240	170	__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
mbed_official	174:8bb9f3a33240	171	for operation of the I2C interface in slave mode, and is not
mbed_official	174:8bb9f3a33240	172	used in master mode. The least significant bit determines whether
mbed_official	174:8bb9f3a33240	173	a slave responds to the General Call address. */
mbed_official	174:8bb9f3a33240	174	__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
mbed_official	174:8bb9f3a33240	175	for operation of the I2C interface in slave mode, and is not
mbed_official	174:8bb9f3a33240	176	used in master mode. The least significant bit determines whether
mbed_official	174:8bb9f3a33240	177	a slave responds to the General Call address. */
mbed_official	174:8bb9f3a33240	178	__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
mbed_official	174:8bb9f3a33240	179	for operation of the I2C interface in slave mode, and is not
mbed_official	174:8bb9f3a33240	180	used in master mode. The least significant bit determines whether
mbed_official	174:8bb9f3a33240	181	a slave responds to the General Call address. */
mbed_official	174:8bb9f3a33240	182	__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
mbed_official	174:8bb9f3a33240	183	shift register will be transferred to the DATA_BUFFER automatically
mbed_official	174:8bb9f3a33240	184	after every nine bits (8 bits of data plus ACK or NACK) has
mbed_official	174:8bb9f3a33240	185	been received on the bus. */
mbed_official	174:8bb9f3a33240	186	__IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
mbed_official	174:8bb9f3a33240	187	with I2ADR0 to determine an address match. The mask register
mbed_official	174:8bb9f3a33240	188	has no effect when comparing to the General Call address (0000000). */
mbed_official	174:8bb9f3a33240	189	__IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
mbed_official	174:8bb9f3a33240	190	with I2ADR0 to determine an address match. The mask register
mbed_official	174:8bb9f3a33240	191	has no effect when comparing to the General Call address (0000000). */
mbed_official	174:8bb9f3a33240	192	__IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
mbed_official	174:8bb9f3a33240	193	with I2ADR0 to determine an address match. The mask register
mbed_official	174:8bb9f3a33240	194	has no effect when comparing to the General Call address (0000000). */
mbed_official	174:8bb9f3a33240	195	__IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
mbed_official	174:8bb9f3a33240	196	with I2ADR0 to determine an address match. The mask register
mbed_official	174:8bb9f3a33240	197	has no effect when comparing to the General Call address (0000000). */
mbed_official	174:8bb9f3a33240	198	} LPC_I2C0_Type;
mbed_official	174:8bb9f3a33240	199
mbed_official	174:8bb9f3a33240	200
mbed_official	174:8bb9f3a33240	201	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	202	/* ================ WWDT ================ */
mbed_official	174:8bb9f3a33240	203	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	204
mbed_official	174:8bb9f3a33240	205
mbed_official	174:8bb9f3a33240	206	/**
mbed_official	174:8bb9f3a33240	207	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
mbed_official	174:8bb9f3a33240	208	*/
mbed_official	174:8bb9f3a33240	209
mbed_official	174:8bb9f3a33240	210	typedef struct { /!< WWDT Structure /
mbed_official	174:8bb9f3a33240	211	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
mbed_official	174:8bb9f3a33240	212	and status of the Watchdog Timer. */
mbed_official	174:8bb9f3a33240	213	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
mbed_official	174:8bb9f3a33240	214	the time-out value. */
mbed_official	174:8bb9f3a33240	215	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
mbed_official	174:8bb9f3a33240	216	to this register reloads the Watchdog timer with the value contained
mbed_official	174:8bb9f3a33240	217	in WDTC. */
mbed_official	174:8bb9f3a33240	218	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
mbed_official	174:8bb9f3a33240	219	the current value of the Watchdog timer. */
mbed_official	174:8bb9f3a33240	220	__IO uint32_t CLKSEL; /!< Watchdog clock select register. /
mbed_official	174:8bb9f3a33240	221	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
mbed_official	174:8bb9f3a33240	222	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
mbed_official	174:8bb9f3a33240	223	} LPC_WWDT_Type;
mbed_official	174:8bb9f3a33240	224
mbed_official	174:8bb9f3a33240	225
mbed_official	174:8bb9f3a33240	226	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	227	/* ================ USART0 ================ */
mbed_official	174:8bb9f3a33240	228	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	229
mbed_official	174:8bb9f3a33240	230
mbed_official	174:8bb9f3a33240	231	/**
mbed_official	174:8bb9f3a33240	232	* @brief USART0 (USART0)
mbed_official	174:8bb9f3a33240	233	*/
mbed_official	174:8bb9f3a33240	234
mbed_official	174:8bb9f3a33240	235	typedef struct { /!< USART0 Structure /
mbed_official	174:8bb9f3a33240	236
mbed_official	174:8bb9f3a33240	237	union {
mbed_official	174:8bb9f3a33240	238	__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
mbed_official	174:8bb9f3a33240	239	value. The full divisor is used to generate a baud rate from
mbed_official	174:8bb9f3a33240	240	the fractional rate divider. (DLAB=1) */
mbed_official	174:8bb9f3a33240	241	__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
mbed_official	174:8bb9f3a33240	242	is written here. (DLAB=0) */
mbed_official	174:8bb9f3a33240	243	__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
mbed_official	174:8bb9f3a33240	244	to be read. (DLAB=0) */
mbed_official	174:8bb9f3a33240	245	};
mbed_official	174:8bb9f3a33240	246
mbed_official	174:8bb9f3a33240	247	union {
mbed_official	174:8bb9f3a33240	248	__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
mbed_official	174:8bb9f3a33240	249	bits for the 7 potential USART interrupts. (DLAB=0) */
mbed_official	174:8bb9f3a33240	250	__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
mbed_official	174:8bb9f3a33240	251	value. The full divisor is used to generate a baud rate from
mbed_official	174:8bb9f3a33240	252	the fractional rate divider. (DLAB=1) */
mbed_official	174:8bb9f3a33240	253	};
mbed_official	174:8bb9f3a33240	254
mbed_official	174:8bb9f3a33240	255	union {
mbed_official	174:8bb9f3a33240	256	__O uint32_t FCR; /!< FIFO Control Register. Controls USART FIFO usage and modes. /
mbed_official	174:8bb9f3a33240	257	__I uint32_t IIR; /!< Interrupt ID Register. Identifies which interrupt(s) are pending. /
mbed_official	174:8bb9f3a33240	258	};
mbed_official	174:8bb9f3a33240	259	__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
mbed_official	174:8bb9f3a33240	260	and break generation. */
mbed_official	174:8bb9f3a33240	261	__IO uint32_t MCR; /!< Modem Control Register. /
mbed_official	174:8bb9f3a33240	262	__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
mbed_official	174:8bb9f3a33240	263	status, including line errors. */
mbed_official	174:8bb9f3a33240	264	__I uint32_t MSR; /!< Modem Status Register. /
mbed_official	174:8bb9f3a33240	265	__IO uint32_t SCR; /!< Scratch Pad Register. Eight-bit temporary storage for software. /
mbed_official	174:8bb9f3a33240	266	__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
mbed_official	174:8bb9f3a33240	267	feature. */
mbed_official	174:8bb9f3a33240	268	__IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
mbed_official	174:8bb9f3a33240	269	control) mode. */
mbed_official	174:8bb9f3a33240	270	__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
mbed_official	174:8bb9f3a33240	271	baud rate divider. */
mbed_official	174:8bb9f3a33240	272	__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
mbed_official	174:8bb9f3a33240	273	each bit time. */
mbed_official	174:8bb9f3a33240	274	__IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
mbed_official	174:8bb9f3a33240	275	with software flow control. */
mbed_official	174:8bb9f3a33240	276	__I uint32_t RESERVED0[3];
mbed_official	174:8bb9f3a33240	277	__IO uint32_t HDEN; /!< Half duplex enable register. /
mbed_official	174:8bb9f3a33240	278	__I uint32_t RESERVED1;
mbed_official	174:8bb9f3a33240	279	__IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
mbed_official	174:8bb9f3a33240	280	the Smart Card Interface feature. */
mbed_official	174:8bb9f3a33240	281	__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
mbed_official	174:8bb9f3a33240	282	aspects of RS-485/EIA-485 modes. */
mbed_official	174:8bb9f3a33240	283	__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
mbed_official	174:8bb9f3a33240	284	for RS-485/EIA-485 mode. */
mbed_official	174:8bb9f3a33240	285	__IO uint32_t RS485DLY; /!< RS-485/EIA-485 direction control delay. /
mbed_official	174:8bb9f3a33240	286	__IO uint32_t SYNCCTRL; /!< Synchronous mode control register. /
mbed_official	174:8bb9f3a33240	287	} LPC_USART0_Type;
mbed_official	174:8bb9f3a33240	288
mbed_official	174:8bb9f3a33240	289
mbed_official	174:8bb9f3a33240	290	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	291	/* ================ CT16B0 ================ */
mbed_official	174:8bb9f3a33240	292	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	293
mbed_official	174:8bb9f3a33240	294
mbed_official	174:8bb9f3a33240	295	/**
mbed_official	174:8bb9f3a33240	296	* @brief 16-bit counter/timers CT16B0 (CT16B0)
mbed_official	174:8bb9f3a33240	297	*/
mbed_official	174:8bb9f3a33240	298
mbed_official	174:8bb9f3a33240	299	typedef struct { /!< CT16B0 Structure /
mbed_official	174:8bb9f3a33240	300	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
mbed_official	174:8bb9f3a33240	301	The IR can be read to identify which of eight possible interrupt
mbed_official	174:8bb9f3a33240	302	sources are pending. */
mbed_official	174:8bb9f3a33240	303	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
mbed_official	174:8bb9f3a33240	304	Counter functions. The Timer Counter can be disabled or reset
mbed_official	174:8bb9f3a33240	305	through the TCR. */
mbed_official	174:8bb9f3a33240	306	__IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
mbed_official	174:8bb9f3a33240	307	of PCLK. The TC is controlled through the TCR. */
mbed_official	174:8bb9f3a33240	308	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
mbed_official	174:8bb9f3a33240	309	to this value, the next clock increments the TC and clears the
mbed_official	174:8bb9f3a33240	310	PC. */
mbed_official	174:8bb9f3a33240	311	__IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
mbed_official	174:8bb9f3a33240	312	to the value stored in PR. When the value in PR is reached,
mbed_official	174:8bb9f3a33240	313	the TC is incremented and the PC is cleared. The PC is observable
mbed_official	174:8bb9f3a33240	314	and controllable through the bus interface. */
mbed_official	174:8bb9f3a33240	315	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
mbed_official	174:8bb9f3a33240	316	is generated and if the TC is reset when a Match occurs. */
mbed_official	174:8bb9f3a33240	317	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	318	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	319	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	320	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	321	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	322	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	323	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	324	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	325	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	326	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	327	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	328	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	329	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
mbed_official	174:8bb9f3a33240	330	capture inputs are used to load the Capture Registers and whether
mbed_official	174:8bb9f3a33240	331	or not an interrupt is generated when a capture takes place. */
mbed_official	174:8bb9f3a33240	332	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	333	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	334	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	335	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	336	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	337	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	338	__I uint32_t RESERVED0;
mbed_official	174:8bb9f3a33240	339	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
mbed_official	174:8bb9f3a33240	340	and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
mbed_official	174:8bb9f3a33240	341	__I uint32_t RESERVED1[12];
mbed_official	174:8bb9f3a33240	342	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
mbed_official	174:8bb9f3a33240	343	mode, and in Counter mode selects the signal and edge(s) for
mbed_official	174:8bb9f3a33240	344	counting. */
mbed_official	174:8bb9f3a33240	345	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
mbed_official	174:8bb9f3a33240	346	match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
mbed_official	174:8bb9f3a33240	347	} LPC_CT16B0_Type;
mbed_official	174:8bb9f3a33240	348
mbed_official	174:8bb9f3a33240	349
mbed_official	174:8bb9f3a33240	350	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	351	/* ================ CT32B0 ================ */
mbed_official	174:8bb9f3a33240	352	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	353
mbed_official	174:8bb9f3a33240	354
mbed_official	174:8bb9f3a33240	355	/**
mbed_official	174:8bb9f3a33240	356	* @brief 32-bit counter/timers CT32B0 (CT32B0)
mbed_official	174:8bb9f3a33240	357	*/
mbed_official	174:8bb9f3a33240	358
mbed_official	174:8bb9f3a33240	359	typedef struct { /!< CT32B0 Structure /
mbed_official	174:8bb9f3a33240	360	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
mbed_official	174:8bb9f3a33240	361	The IR can be read to identify which of eight possible interrupt
mbed_official	174:8bb9f3a33240	362	sources are pending. */
mbed_official	174:8bb9f3a33240	363	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
mbed_official	174:8bb9f3a33240	364	Counter functions. The Timer Counter can be disabled or reset
mbed_official	174:8bb9f3a33240	365	through the TCR. */
mbed_official	174:8bb9f3a33240	366	__IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
mbed_official	174:8bb9f3a33240	367	of PCLK. The TC is controlled through the TCR. */
mbed_official	174:8bb9f3a33240	368	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
mbed_official	174:8bb9f3a33240	369	to this value, the next clock increments the TC and clears the
mbed_official	174:8bb9f3a33240	370	PC. */
mbed_official	174:8bb9f3a33240	371	__IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
mbed_official	174:8bb9f3a33240	372	to the value stored in PR. When the value in PR is reached,
mbed_official	174:8bb9f3a33240	373	the TC is incremented and the PC is cleared. The PC is observable
mbed_official	174:8bb9f3a33240	374	and controllable through the bus interface. */
mbed_official	174:8bb9f3a33240	375	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
mbed_official	174:8bb9f3a33240	376	is generated and if the TC is reset when a Match occurs. */
mbed_official	174:8bb9f3a33240	377	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	378	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	379	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	380	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	381	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	382	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	383	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	384	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	385	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	386	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
mbed_official	174:8bb9f3a33240	387	TC, stop both the TC and PC, and/or generate an interrupt every
mbed_official	174:8bb9f3a33240	388	time MR0 matches the TC. */
mbed_official	174:8bb9f3a33240	389	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
mbed_official	174:8bb9f3a33240	390	capture inputs are used to load the Capture Registers and whether
mbed_official	174:8bb9f3a33240	391	or not an interrupt is generated when a capture takes place. */
mbed_official	174:8bb9f3a33240	392	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	393	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	394	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	395	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	396	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
mbed_official	174:8bb9f3a33240	397	is an event on the CAP input. */
mbed_official	174:8bb9f3a33240	398	__I uint32_t RESERVED0;
mbed_official	174:8bb9f3a33240	399	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
mbed_official	174:8bb9f3a33240	400	and the external match pins CT32Bn_MAT[3:0]. */
mbed_official	174:8bb9f3a33240	401	__I uint32_t RESERVED1[12];
mbed_official	174:8bb9f3a33240	402	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
mbed_official	174:8bb9f3a33240	403	mode, and in Counter mode selects the signal and edge(s) for
mbed_official	174:8bb9f3a33240	404	counting. */
mbed_official	174:8bb9f3a33240	405	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
mbed_official	174:8bb9f3a33240	406	match pins CT32Bn_MAT[3:0]. */
mbed_official	174:8bb9f3a33240	407	} LPC_CT32B0_Type;
mbed_official	174:8bb9f3a33240	408
mbed_official	174:8bb9f3a33240	409
mbed_official	174:8bb9f3a33240	410	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	411	/* ================ ADC ================ */
mbed_official	174:8bb9f3a33240	412	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	413
mbed_official	174:8bb9f3a33240	414
mbed_official	174:8bb9f3a33240	415	/**
mbed_official	174:8bb9f3a33240	416	* @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
mbed_official	174:8bb9f3a33240	417	*/
mbed_official	174:8bb9f3a33240	418
mbed_official	174:8bb9f3a33240	419	typedef struct { /!< ADC Structure /
mbed_official	174:8bb9f3a33240	420	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
mbed_official	174:8bb9f3a33240	421	bits for each sequence and the A/D power-down bit. */
mbed_official	174:8bb9f3a33240	422	__I uint32_t RESERVED0;
mbed_official	174:8bb9f3a33240	423	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
mbed_official	174:8bb9f3a33240	424	and channel selection for conversion sequence-A. Also specifies
mbed_official	174:8bb9f3a33240	425	interrupt mode for sequence-A. */
mbed_official	174:8bb9f3a33240	426	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
mbed_official	174:8bb9f3a33240	427	and channel selection for conversion sequence-B. Also specifies
mbed_official	174:8bb9f3a33240	428	interrupt mode for sequence-B. */
mbed_official	174:8bb9f3a33240	429	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
mbed_official	174:8bb9f3a33240	430	the result of the most recent A/D conversion performed under
mbed_official	174:8bb9f3a33240	431	sequence-A */
mbed_official	174:8bb9f3a33240	432	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
mbed_official	174:8bb9f3a33240	433	the result of the most recent A/D conversion performed under
mbed_official	174:8bb9f3a33240	434	sequence-B */
mbed_official	174:8bb9f3a33240	435	__I uint32_t RESERVED1[2];
mbed_official	174:8bb9f3a33240	436	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
mbed_official	174:8bb9f3a33240	437	of the most recent conversion completed on channel 0. */
mbed_official	174:8bb9f3a33240	438	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
mbed_official	174:8bb9f3a33240	439	level for automatic threshold comparison for any channels linked
mbed_official	174:8bb9f3a33240	440	to threshold pair 0. */
mbed_official	174:8bb9f3a33240	441	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
mbed_official	174:8bb9f3a33240	442	level for automatic threshold comparison for any channels linked
mbed_official	174:8bb9f3a33240	443	to threshold pair 1. */
mbed_official	174:8bb9f3a33240	444	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
mbed_official	174:8bb9f3a33240	445	level for automatic threshold comparison for any channels linked
mbed_official	174:8bb9f3a33240	446	to threshold pair 0. */
mbed_official	174:8bb9f3a33240	447	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
mbed_official	174:8bb9f3a33240	448	level for automatic threshold comparison for any channels linked
mbed_official	174:8bb9f3a33240	449	to threshold pair 1. */
mbed_official	174:8bb9f3a33240	450	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
mbed_official	174:8bb9f3a33240	451	threshold compare registers are to be used for each channel */
mbed_official	174:8bb9f3a33240	452	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
mbed_official	174:8bb9f3a33240	453	bits that enable the sequence-A, sequence-B, threshold compare
mbed_official	174:8bb9f3a33240	454	and data overrun interrupts to be generated. */
mbed_official	174:8bb9f3a33240	455	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
mbed_official	174:8bb9f3a33240	456	and the individual component overrun and threshold-compare flags.
mbed_official	174:8bb9f3a33240	457	(The overrun bits replicate information stored in the result
mbed_official	174:8bb9f3a33240	458	registers). */
mbed_official	174:8bb9f3a33240	459	__IO uint32_t TRM; /!< ADC trim register. /
mbed_official	174:8bb9f3a33240	460	} LPC_ADC_Type;
mbed_official	174:8bb9f3a33240	461
mbed_official	174:8bb9f3a33240	462
mbed_official	174:8bb9f3a33240	463	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	464	/* ================ RTC ================ */
mbed_official	174:8bb9f3a33240	465	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	466
mbed_official	174:8bb9f3a33240	467
mbed_official	174:8bb9f3a33240	468	/**
mbed_official	174:8bb9f3a33240	469	* @brief Real-Time Clock (RTC) (RTC)
mbed_official	174:8bb9f3a33240	470	*/
mbed_official	174:8bb9f3a33240	471
mbed_official	174:8bb9f3a33240	472	typedef struct { /!< RTC Structure /
mbed_official	174:8bb9f3a33240	473	__IO uint32_t CTRL; /!< RTC control register /
mbed_official	174:8bb9f3a33240	474	__IO uint32_t MATCH; /!< RTC match register /
mbed_official	174:8bb9f3a33240	475	__IO uint32_t COUNT; /!< RTC counter register /
mbed_official	174:8bb9f3a33240	476	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
mbed_official	174:8bb9f3a33240	477	} LPC_RTC_Type;
mbed_official	174:8bb9f3a33240	478
mbed_official	174:8bb9f3a33240	479
mbed_official	174:8bb9f3a33240	480	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	481	/* ================ DMATRIGMUX ================ */
mbed_official	174:8bb9f3a33240	482	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	483
mbed_official	174:8bb9f3a33240	484
mbed_official	174:8bb9f3a33240	485	/**
mbed_official	174:8bb9f3a33240	486	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
mbed_official	174:8bb9f3a33240	487	*/
mbed_official	174:8bb9f3a33240	488
mbed_official	174:8bb9f3a33240	489	typedef struct { /!< DMATRIGMUX Structure /
mbed_official	174:8bb9f3a33240	490	__IO uint32_t DMA_ITRIG_PINMUX[16]; /!< Trigger input select register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	491	} LPC_DMATRIGMUX_Type;
mbed_official	174:8bb9f3a33240	492
mbed_official	174:8bb9f3a33240	493
mbed_official	174:8bb9f3a33240	494	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	495	/* ================ PMU ================ */
mbed_official	174:8bb9f3a33240	496	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	497
mbed_official	174:8bb9f3a33240	498
mbed_official	174:8bb9f3a33240	499	/**
mbed_official	174:8bb9f3a33240	500	* @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
mbed_official	174:8bb9f3a33240	501	*/
mbed_official	174:8bb9f3a33240	502
mbed_official	174:8bb9f3a33240	503	typedef struct { /!< PMU Structure /
mbed_official	174:8bb9f3a33240	504	__IO uint32_t PCON; /!< Power control register /
mbed_official	174:8bb9f3a33240	505	__IO uint32_t GPREG0; /!< General purpose register 0 /
mbed_official	174:8bb9f3a33240	506	__IO uint32_t GPREG1; /!< General purpose register 0 /
mbed_official	174:8bb9f3a33240	507	__IO uint32_t GPREG2; /!< General purpose register 0 /
mbed_official	174:8bb9f3a33240	508	__IO uint32_t GPREG3; /!< General purpose register 0 /
mbed_official	174:8bb9f3a33240	509	__IO uint32_t DPDCTRL; /!< Deep power down control register /
mbed_official	174:8bb9f3a33240	510	} LPC_PMU_Type;
mbed_official	174:8bb9f3a33240	511
mbed_official	174:8bb9f3a33240	512
mbed_official	174:8bb9f3a33240	513	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	514	/* ================ FLASHCTRL ================ */
mbed_official	174:8bb9f3a33240	515	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	516
mbed_official	174:8bb9f3a33240	517
mbed_official	174:8bb9f3a33240	518	/**
mbed_official	174:8bb9f3a33240	519	* @brief Flash controller (FLASHCTRL)
mbed_official	174:8bb9f3a33240	520	*/
mbed_official	174:8bb9f3a33240	521
mbed_official	174:8bb9f3a33240	522	typedef struct { /!< FLASHCTRL Structure /
mbed_official	174:8bb9f3a33240	523	__I uint32_t RESERVED0[4];
mbed_official	174:8bb9f3a33240	524	__IO uint32_t FLASHCFG; /!< Flash configuration register /
mbed_official	174:8bb9f3a33240	525	__I uint32_t RESERVED1[3];
mbed_official	174:8bb9f3a33240	526	__IO uint32_t FMSSTART; /!< Signature start address register /
mbed_official	174:8bb9f3a33240	527	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
mbed_official	174:8bb9f3a33240	528	__I uint32_t RESERVED2;
mbed_official	174:8bb9f3a33240	529	__I uint32_t FMSW0; /!< Signature Word /
mbed_official	174:8bb9f3a33240	530	} LPC_FLASHCTRL_Type;
mbed_official	174:8bb9f3a33240	531
mbed_official	174:8bb9f3a33240	532
mbed_official	174:8bb9f3a33240	533	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	534	/* ================ SSP0 ================ */
mbed_official	174:8bb9f3a33240	535	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	536
mbed_official	174:8bb9f3a33240	537
mbed_official	174:8bb9f3a33240	538	/**
mbed_official	174:8bb9f3a33240	539	* @brief SSP/SPI (SSP0)
mbed_official	174:8bb9f3a33240	540	*/
mbed_official	174:8bb9f3a33240	541
mbed_official	174:8bb9f3a33240	542	typedef struct { /!< SSP0 Structure /
mbed_official	174:8bb9f3a33240	543	__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
mbed_official	174:8bb9f3a33240	544	and data size. */
mbed_official	174:8bb9f3a33240	545	__IO uint32_t CR1; /!< Control Register 1. Selects master/slave and other modes. /
mbed_official	174:8bb9f3a33240	546	__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
mbed_official	174:8bb9f3a33240	547	the receive FIFO. */
mbed_official	174:8bb9f3a33240	548	__I uint32_t SR; /!< Status Register /
mbed_official	174:8bb9f3a33240	549	__IO uint32_t CPSR; /!< Clock Prescale Register /
mbed_official	174:8bb9f3a33240	550	__IO uint32_t IMSC; /!< Interrupt Mask Set and Clear Register /
mbed_official	174:8bb9f3a33240	551	__I uint32_t RIS; /!< Raw Interrupt Status Register /
mbed_official	174:8bb9f3a33240	552	__I uint32_t MIS; /!< Masked Interrupt Status Register /
mbed_official	174:8bb9f3a33240	553	__O uint32_t ICR; /!< SSPICR Interrupt Clear Register /
mbed_official	174:8bb9f3a33240	554	} LPC_SSP0_Type;
mbed_official	174:8bb9f3a33240	555
mbed_official	174:8bb9f3a33240	556
mbed_official	174:8bb9f3a33240	557	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	558	/* ================ IOCON ================ */
mbed_official	174:8bb9f3a33240	559	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	560
mbed_official	174:8bb9f3a33240	561
mbed_official	174:8bb9f3a33240	562	/**
mbed_official	174:8bb9f3a33240	563	* @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
mbed_official	174:8bb9f3a33240	564	*/
mbed_official	174:8bb9f3a33240	565
mbed_official	174:8bb9f3a33240	566	typedef struct { /!< IOCON Structure /
mbed_official	174:8bb9f3a33240	567	__IO uint32_t PIO0_0; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	568	__IO uint32_t PIO0_1; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	569	__IO uint32_t PIO0_2; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	570	__IO uint32_t PIO0_3; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	571	__IO uint32_t PIO0_4; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	572	__IO uint32_t PIO0_5; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	573	__IO uint32_t PIO0_6; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	574	__IO uint32_t PIO0_7; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	575	__IO uint32_t PIO0_8; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	576	__IO uint32_t PIO0_9; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	577	__IO uint32_t PIO0_10; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	578	__IO uint32_t PIO0_11; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	579	__IO uint32_t PIO0_12; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	580	__IO uint32_t PIO0_13; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	581	__IO uint32_t PIO0_14; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	582	__IO uint32_t PIO0_15; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	583	__IO uint32_t PIO0_16; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	584	__IO uint32_t PIO0_17; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	585	__IO uint32_t PIO0_18; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	586	__IO uint32_t PIO0_19; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	587	__IO uint32_t PIO0_20; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	588	__IO uint32_t PIO0_21; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	589	__IO uint32_t PIO0_22; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	590	__IO uint32_t PIO0_23; /!< I/O configuration for port PIO0 /
mbed_official	174:8bb9f3a33240	591	__IO uint32_t PIO1_0; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	592	__IO uint32_t PIO1_1; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	593	__IO uint32_t PIO1_2; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	594	__IO uint32_t PIO1_3; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	595	__IO uint32_t PIO1_4; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	596	__IO uint32_t PIO1_5; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	597	__IO uint32_t PIO1_6; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	598	__IO uint32_t PIO1_7; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	599	__IO uint32_t PIO1_8; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	600	__IO uint32_t PIO1_9; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	601	__IO uint32_t PIO1_10; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	602	__IO uint32_t PIO1_11; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	603	__IO uint32_t PIO1_12; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	604	__IO uint32_t PIO1_13; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	605	__IO uint32_t PIO1_14; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	606	__IO uint32_t PIO1_15; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	607	__IO uint32_t PIO1_16; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	608	__IO uint32_t PIO1_17; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	609	__IO uint32_t PIO1_18; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	610	__IO uint32_t PIO1_19; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	611	__IO uint32_t PIO1_20; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	612	__IO uint32_t PIO1_21; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	613	__IO uint32_t PIO1_22; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	614	__IO uint32_t PIO1_23; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	615	__IO uint32_t PIO1_24; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	616	__IO uint32_t PIO1_25; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	617	__IO uint32_t PIO1_26; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	618	__IO uint32_t PIO1_27; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	619	__IO uint32_t PIO1_28; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	620	__IO uint32_t PIO1_29; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	621	__IO uint32_t PIO1_30; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	622	__IO uint32_t PIO1_31; /!< I/O configuration for port PIO1 /
mbed_official	174:8bb9f3a33240	623	__I uint32_t RESERVED0[4];
mbed_official	174:8bb9f3a33240	624	__IO uint32_t PIO2_0; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	625	__IO uint32_t PIO2_1; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	626	__I uint32_t RESERVED1;
mbed_official	174:8bb9f3a33240	627	__IO uint32_t PIO2_2; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	628	__IO uint32_t PIO2_3; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	629	__IO uint32_t PIO2_4; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	630	__IO uint32_t PIO2_5; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	631	__IO uint32_t PIO2_6; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	632	__IO uint32_t PIO2_7; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	633	__IO uint32_t PIO2_8; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	634	__IO uint32_t PIO2_9; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	635	__IO uint32_t PIO2_10; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	636	__IO uint32_t PIO2_11; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	637	__IO uint32_t PIO2_12; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	638	__IO uint32_t PIO2_13; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	639	__IO uint32_t PIO2_14; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	640	__IO uint32_t PIO2_15; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	641	__IO uint32_t PIO2_16; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	642	__IO uint32_t PIO2_17; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	643	__IO uint32_t PIO2_18; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	644	__IO uint32_t PIO2_19; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	645	__IO uint32_t PIO2_20; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	646	__IO uint32_t PIO2_21; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	647	__IO uint32_t PIO2_22; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	648	__IO uint32_t PIO2_23; /!< I/O configuration for port PIO2 /
mbed_official	174:8bb9f3a33240	649	} LPC_IOCON_Type;
mbed_official	174:8bb9f3a33240	650
mbed_official	174:8bb9f3a33240	651
mbed_official	174:8bb9f3a33240	652	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	653	/* ================ SYSCON ================ */
mbed_official	174:8bb9f3a33240	654	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	655
mbed_official	174:8bb9f3a33240	656
mbed_official	174:8bb9f3a33240	657	/**
mbed_official	174:8bb9f3a33240	658	* @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
mbed_official	174:8bb9f3a33240	659	*/
mbed_official	174:8bb9f3a33240	660
mbed_official	174:8bb9f3a33240	661	typedef struct { /!< SYSCON Structure /
mbed_official	174:8bb9f3a33240	662	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
mbed_official	174:8bb9f3a33240	663	__IO uint32_t PRESETCTRL; /!< Peripheral reset control /
mbed_official	174:8bb9f3a33240	664	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
mbed_official	174:8bb9f3a33240	665	__I uint32_t SYSPLLSTAT; /!< System PLL status /
mbed_official	174:8bb9f3a33240	666	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
mbed_official	174:8bb9f3a33240	667	__I uint32_t USBPLLSTAT; /!< USB PLL status /
mbed_official	174:8bb9f3a33240	668	__I uint32_t RESERVED0;
mbed_official	174:8bb9f3a33240	669	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator 32 kHz output control /
mbed_official	174:8bb9f3a33240	670	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
mbed_official	174:8bb9f3a33240	671	__IO uint32_t WDTOSCCTRL; /!< Watchdog oscillator control /
mbed_official	174:8bb9f3a33240	672	__I uint32_t RESERVED1[2];
mbed_official	174:8bb9f3a33240	673	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
mbed_official	174:8bb9f3a33240	674	__I uint32_t RESERVED2[3];
mbed_official	174:8bb9f3a33240	675	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
mbed_official	174:8bb9f3a33240	676	__IO uint32_t SYSPLLCLKUEN; /!< System PLL clock source update enable /
mbed_official	174:8bb9f3a33240	677	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
mbed_official	174:8bb9f3a33240	678	__IO uint32_t USBPLLCLKUEN; /!< USB PLL clock source update enable /
mbed_official	174:8bb9f3a33240	679	__I uint32_t RESERVED3[8];
mbed_official	174:8bb9f3a33240	680	__IO uint32_t MAINCLKSEL; /!< Main clock source select /
mbed_official	174:8bb9f3a33240	681	__IO uint32_t MAINCLKUEN; /!< Main clock source update enable /
mbed_official	174:8bb9f3a33240	682	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
mbed_official	174:8bb9f3a33240	683	__I uint32_t RESERVED4;
mbed_official	174:8bb9f3a33240	684	__IO uint32_t SYSAHBCLKCTRL; /!< System clock control /
mbed_official	174:8bb9f3a33240	685	__I uint32_t RESERVED5[4];
mbed_official	174:8bb9f3a33240	686	__IO uint32_t SSP0CLKDIV; /!< SSP0 clock divider /
mbed_official	174:8bb9f3a33240	687	__IO uint32_t USART0CLKDIV; /!< USART0 clock divider /
mbed_official	174:8bb9f3a33240	688	__IO uint32_t SSP1CLKDIV; /!< SSP1 clock divider /
mbed_official	174:8bb9f3a33240	689	__IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
mbed_official	174:8bb9f3a33240	690	of USART1 to USART4 */
mbed_official	174:8bb9f3a33240	691	__I uint32_t RESERVED6[7];
mbed_official	174:8bb9f3a33240	692	__IO uint32_t USBCLKSEL; /!< USB clock source select /
mbed_official	174:8bb9f3a33240	693	__IO uint32_t USBCLKUEN; /!< USB clock source update enable /
mbed_official	174:8bb9f3a33240	694	__IO uint32_t USBCLKDIV; /!< USB clock source divider /
mbed_official	174:8bb9f3a33240	695	__I uint32_t RESERVED7[5];
mbed_official	174:8bb9f3a33240	696	__IO uint32_t CLKOUTSEL; /!< CLKOUT clock source select /
mbed_official	174:8bb9f3a33240	697	__IO uint32_t CLKOUTUEN; /!< CLKOUT clock source update enable /
mbed_official	174:8bb9f3a33240	698	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
mbed_official	174:8bb9f3a33240	699	__I uint32_t RESERVED8;
mbed_official	174:8bb9f3a33240	700	__IO uint32_t UARTFRGDIV; /!< USART fractional generator divider value /
mbed_official	174:8bb9f3a33240	701	__IO uint32_t UARTFRGMULT; /!< USART fractional generator multiplier value /
mbed_official	174:8bb9f3a33240	702	__I uint32_t RESERVED9;
mbed_official	174:8bb9f3a33240	703	__IO uint32_t EXTTRACECMD; /!< External trace buffer command register /
mbed_official	174:8bb9f3a33240	704	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
mbed_official	174:8bb9f3a33240	705	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
mbed_official	174:8bb9f3a33240	706	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 1 /
mbed_official	174:8bb9f3a33240	707	__I uint32_t RESERVED10[10];
mbed_official	174:8bb9f3a33240	708	__IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	709	filter */
mbed_official	174:8bb9f3a33240	710	__IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	711	filter */
mbed_official	174:8bb9f3a33240	712	__IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	713	filter */
mbed_official	174:8bb9f3a33240	714	__IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	715	filter */
mbed_official	174:8bb9f3a33240	716	__IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	717	filter */
mbed_official	174:8bb9f3a33240	718	__IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	719	filter */
mbed_official	174:8bb9f3a33240	720	__IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
mbed_official	174:8bb9f3a33240	721	filter */
mbed_official	174:8bb9f3a33240	722	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
mbed_official	174:8bb9f3a33240	723	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
mbed_official	174:8bb9f3a33240	724	__IO uint32_t AHBMATRIXPRIO; /!< AHB matrix priority configuration /
mbed_official	174:8bb9f3a33240	725	__I uint32_t RESERVED11[5];
mbed_official	174:8bb9f3a33240	726	__IO uint32_t IRQLATENCY; /!< IRQ delay. Allows trade-off between interrupt latency and determinism. /
mbed_official	174:8bb9f3a33240	727	__IO uint32_t NMISRC; /!< NMI Source Control /
mbed_official	174:8bb9f3a33240	728	union {
mbed_official	174:8bb9f3a33240	729	__IO uint32_t PINTSEL[8];
mbed_official	174:8bb9f3a33240	730	struct {
mbed_official	174:8bb9f3a33240	731	__IO uint32_t PINTSEL0; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	732	__IO uint32_t PINTSEL1; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	733	__IO uint32_t PINTSEL2; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	734	__IO uint32_t PINTSEL3; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	735	__IO uint32_t PINTSEL4; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	736	__IO uint32_t PINTSEL5; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	737	__IO uint32_t PINTSEL6; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	738	__IO uint32_t PINTSEL7; /!< GPIO Pin Interrupt Select register 0 /
mbed_official	174:8bb9f3a33240	739	};
mbed_official	174:8bb9f3a33240	740	};
mbed_official	174:8bb9f3a33240	741	__IO uint32_t USBCLKCTRL; /!< USB clock control /
mbed_official	174:8bb9f3a33240	742	__I uint32_t USBCLKST; /!< USB clock status /
mbed_official	174:8bb9f3a33240	743	__I uint32_t RESERVED12[25];
mbed_official	174:8bb9f3a33240	744	__IO uint32_t STARTERP0; /!< Start logic 0 interrupt wake-up enable register 0 /
mbed_official	174:8bb9f3a33240	745	__I uint32_t RESERVED13[3];
mbed_official	174:8bb9f3a33240	746	__IO uint32_t STARTERP1; /!< Start logic 1 interrupt wake-up enable register 1 /
mbed_official	174:8bb9f3a33240	747	__I uint32_t RESERVED14[6];
mbed_official	174:8bb9f3a33240	748	__IO uint32_t PDSLEEPCFG; /!< Power-down states in deep-sleep mode /
mbed_official	174:8bb9f3a33240	749	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
mbed_official	174:8bb9f3a33240	750	__IO uint32_t PDRUNCFG; /!< Power configuration register /
mbed_official	174:8bb9f3a33240	751	__I uint32_t RESERVED15[110];
mbed_official	174:8bb9f3a33240	752	__I uint32_t DEVICE_ID; /!< Device ID /
mbed_official	174:8bb9f3a33240	753	} LPC_SYSCON_Type;
mbed_official	174:8bb9f3a33240	754
mbed_official	174:8bb9f3a33240	755
mbed_official	174:8bb9f3a33240	756	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	757	/* ================ USART4 ================ */
mbed_official	174:8bb9f3a33240	758	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	759
mbed_official	174:8bb9f3a33240	760
mbed_official	174:8bb9f3a33240	761	/**
mbed_official	174:8bb9f3a33240	762	* @brief USART4 (USART4)
mbed_official	174:8bb9f3a33240	763	*/
mbed_official	174:8bb9f3a33240	764
mbed_official	174:8bb9f3a33240	765	typedef struct { /!< USART4 Structure /
mbed_official	174:8bb9f3a33240	766	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
mbed_official	174:8bb9f3a33240	767	that typically are not changed during operation. */
mbed_official	174:8bb9f3a33240	768	__IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
mbed_official	174:8bb9f3a33240	769	likely to change during operation. */
mbed_official	174:8bb9f3a33240	770	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
mbed_official	174:8bb9f3a33240	771	here. Writing ones clears some bits in the register. Some bits
mbed_official	174:8bb9f3a33240	772	can be cleared by writing a 1 to them. */
mbed_official	174:8bb9f3a33240	773	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
mbed_official	174:8bb9f3a33240	774	interrupt enable bit for each potential USART interrupt. A complete
mbed_official	174:8bb9f3a33240	775	value may be read from this register. Writing a 1 to any implemented
mbed_official	174:8bb9f3a33240	776	bit position causes that bit to be set. */
mbed_official	174:8bb9f3a33240	777	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
mbed_official	174:8bb9f3a33240	778	of bits in the INTENSET register. Writing a 1 to any implemented
mbed_official	174:8bb9f3a33240	779	bit position causes the corresponding bit to be cleared. */
mbed_official	174:8bb9f3a33240	780	__I uint32_t RXDAT; /!< Receiver Data register. Contains the last character received. /
mbed_official	174:8bb9f3a33240	781	__I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
mbed_official	174:8bb9f3a33240	782	received with the current USART receive status. Allows DMA or
mbed_official	174:8bb9f3a33240	783	software to recover incoming data and status together. */
mbed_official	174:8bb9f3a33240	784	__IO uint32_t TXDAT; /!< Transmit Data register. Data to be transmitted is written here. /
mbed_official	174:8bb9f3a33240	785	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
mbed_official	174:8bb9f3a33240	786	value. */
mbed_official	174:8bb9f3a33240	787	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
mbed_official	174:8bb9f3a33240	788	enabled. */
mbed_official	174:8bb9f3a33240	789	__IO uint32_t OSR; /!< Oversample selection register for asynchronous communication. /
mbed_official	174:8bb9f3a33240	790	__IO uint32_t ADDR; /!< Address register for automatic address matching. /
mbed_official	174:8bb9f3a33240	791	} LPC_USART4_Type;
mbed_official	174:8bb9f3a33240	792
mbed_official	174:8bb9f3a33240	793
mbed_official	174:8bb9f3a33240	794	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	795	/* ================ GINT0 ================ */
mbed_official	174:8bb9f3a33240	796	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	797
mbed_official	174:8bb9f3a33240	798
mbed_official	174:8bb9f3a33240	799	/**
mbed_official	174:8bb9f3a33240	800	* @brief GPIO group interrupt 0 (GINT0)
mbed_official	174:8bb9f3a33240	801	*/
mbed_official	174:8bb9f3a33240	802
mbed_official	174:8bb9f3a33240	803	typedef struct { /!< GINT0 Structure /
mbed_official	174:8bb9f3a33240	804	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
mbed_official	174:8bb9f3a33240	805	__I uint32_t RESERVED0[7];
mbed_official	174:8bb9f3a33240	806	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
mbed_official	174:8bb9f3a33240	807	__I uint32_t RESERVED1[5];
mbed_official	174:8bb9f3a33240	808	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port enable register /
mbed_official	174:8bb9f3a33240	809	} LPC_GINT0_Type;
mbed_official	174:8bb9f3a33240	810
mbed_official	174:8bb9f3a33240	811
mbed_official	174:8bb9f3a33240	812	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	813	/* ================ USB ================ */
mbed_official	174:8bb9f3a33240	814	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	815
mbed_official	174:8bb9f3a33240	816
mbed_official	174:8bb9f3a33240	817	/**
mbed_official	174:8bb9f3a33240	818	* @brief USB device controller (USB)
mbed_official	174:8bb9f3a33240	819	*/
mbed_official	174:8bb9f3a33240	820
mbed_official	174:8bb9f3a33240	821	typedef struct { /!< USB Structure /
mbed_official	174:8bb9f3a33240	822	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
mbed_official	174:8bb9f3a33240	823	__IO uint32_t INFO; /!< USB Info register /
mbed_official	174:8bb9f3a33240	824	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
mbed_official	174:8bb9f3a33240	825	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
mbed_official	174:8bb9f3a33240	826	__IO uint32_t LPM; /!< Link Power Management register /
mbed_official	174:8bb9f3a33240	827	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
mbed_official	174:8bb9f3a33240	828	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
mbed_official	174:8bb9f3a33240	829	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
mbed_official	174:8bb9f3a33240	830	__IO uint32_t INTSTAT; /!< USB interrupt status register /
mbed_official	174:8bb9f3a33240	831	__IO uint32_t INTEN; /!< USB interrupt enable register /
mbed_official	174:8bb9f3a33240	832	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
mbed_official	174:8bb9f3a33240	833	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
mbed_official	174:8bb9f3a33240	834	__I uint32_t RESERVED0;
mbed_official	174:8bb9f3a33240	835	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
mbed_official	174:8bb9f3a33240	836	} LPC_USB_Type;
mbed_official	174:8bb9f3a33240	837
mbed_official	174:8bb9f3a33240	838
mbed_official	174:8bb9f3a33240	839	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	840	/* ================ CRC ================ */
mbed_official	174:8bb9f3a33240	841	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	842
mbed_official	174:8bb9f3a33240	843
mbed_official	174:8bb9f3a33240	844	/**
mbed_official	174:8bb9f3a33240	845	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
mbed_official	174:8bb9f3a33240	846	*/
mbed_official	174:8bb9f3a33240	847
mbed_official	174:8bb9f3a33240	848	typedef struct { /!< CRC Structure /
mbed_official	174:8bb9f3a33240	849	__IO uint32_t MODE; /!< CRC mode register /
mbed_official	174:8bb9f3a33240	850	__IO uint32_t SEED; /!< CRC seed register /
mbed_official	174:8bb9f3a33240	851
mbed_official	174:8bb9f3a33240	852	union {
mbed_official	174:8bb9f3a33240	853	__O uint32_t WR_DATA; /!< CRC data register /
mbed_official	174:8bb9f3a33240	854	__I uint32_t SUM; /!< CRC checksum register /
mbed_official	174:8bb9f3a33240	855	};
mbed_official	174:8bb9f3a33240	856	} LPC_CRC_Type;
mbed_official	174:8bb9f3a33240	857
mbed_official	174:8bb9f3a33240	858
mbed_official	174:8bb9f3a33240	859	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	860	/* ================ DMA ================ */
mbed_official	174:8bb9f3a33240	861	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	862
mbed_official	174:8bb9f3a33240	863
mbed_official	174:8bb9f3a33240	864	/**
mbed_official	174:8bb9f3a33240	865	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
mbed_official	174:8bb9f3a33240	866	*/
mbed_official	174:8bb9f3a33240	867
mbed_official	174:8bb9f3a33240	868	typedef struct { /!< DMA Structure /
mbed_official	174:8bb9f3a33240	869	__IO uint32_t CTRL; /!< DMA control. /
mbed_official	174:8bb9f3a33240	870	__I uint32_t INTSTAT; /!< Interrupt status. /
mbed_official	174:8bb9f3a33240	871	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
mbed_official	174:8bb9f3a33240	872	__I uint32_t RESERVED0[5];
mbed_official	174:8bb9f3a33240	873	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
mbed_official	174:8bb9f3a33240	874	__I uint32_t RESERVED1;
mbed_official	174:8bb9f3a33240	875	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
mbed_official	174:8bb9f3a33240	876	__I uint32_t RESERVED2;
mbed_official	174:8bb9f3a33240	877	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
mbed_official	174:8bb9f3a33240	878	__I uint32_t RESERVED3;
mbed_official	174:8bb9f3a33240	879	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
mbed_official	174:8bb9f3a33240	880	__I uint32_t RESERVED4;
mbed_official	174:8bb9f3a33240	881	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
mbed_official	174:8bb9f3a33240	882	__I uint32_t RESERVED5;
mbed_official	174:8bb9f3a33240	883	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
mbed_official	174:8bb9f3a33240	884	__I uint32_t RESERVED6;
mbed_official	174:8bb9f3a33240	885	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
mbed_official	174:8bb9f3a33240	886	__I uint32_t RESERVED7;
mbed_official	174:8bb9f3a33240	887	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
mbed_official	174:8bb9f3a33240	888	__I uint32_t RESERVED8;
mbed_official	174:8bb9f3a33240	889	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
mbed_official	174:8bb9f3a33240	890	__I uint32_t RESERVED9;
mbed_official	174:8bb9f3a33240	891	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
mbed_official	174:8bb9f3a33240	892	__I uint32_t RESERVED10;
mbed_official	174:8bb9f3a33240	893	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
mbed_official	174:8bb9f3a33240	894	__I uint32_t RESERVED11;
mbed_official	174:8bb9f3a33240	895	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
mbed_official	174:8bb9f3a33240	896	__I uint32_t RESERVED12[225];
mbed_official	174:8bb9f3a33240	897	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	898	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	899	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	900	__I uint32_t RESERVED13;
mbed_official	174:8bb9f3a33240	901	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	902	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	903	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	904	__I uint32_t RESERVED14;
mbed_official	174:8bb9f3a33240	905	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	906	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	907	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	908	__I uint32_t RESERVED15;
mbed_official	174:8bb9f3a33240	909	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	910	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	911	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	912	__I uint32_t RESERVED16;
mbed_official	174:8bb9f3a33240	913	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	914	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	915	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	916	__I uint32_t RESERVED17;
mbed_official	174:8bb9f3a33240	917	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	918	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	919	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	920	__I uint32_t RESERVED18;
mbed_official	174:8bb9f3a33240	921	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	922	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	923	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	924	__I uint32_t RESERVED19;
mbed_official	174:8bb9f3a33240	925	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	926	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	927	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	928	__I uint32_t RESERVED20;
mbed_official	174:8bb9f3a33240	929	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	930	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	931	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	932	__I uint32_t RESERVED21;
mbed_official	174:8bb9f3a33240	933	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	934	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	935	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	936	__I uint32_t RESERVED22;
mbed_official	174:8bb9f3a33240	937	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	938	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	939	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	940	__I uint32_t RESERVED23;
mbed_official	174:8bb9f3a33240	941	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	942	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	943	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	944	__I uint32_t RESERVED24;
mbed_official	174:8bb9f3a33240	945	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	946	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	947	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	948	__I uint32_t RESERVED25;
mbed_official	174:8bb9f3a33240	949	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	950	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	951	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	952	__I uint32_t RESERVED26;
mbed_official	174:8bb9f3a33240	953	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	954	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	955	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	956	__I uint32_t RESERVED27;
mbed_official	174:8bb9f3a33240	957	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	958	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	959	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
mbed_official	174:8bb9f3a33240	960	} LPC_DMA_Type;
mbed_official	174:8bb9f3a33240	961
mbed_official	174:8bb9f3a33240	962
mbed_official	174:8bb9f3a33240	963	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	964	/* ================ SCT0 ================ */
mbed_official	174:8bb9f3a33240	965	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	966
mbed_official	174:8bb9f3a33240	967
mbed_official	174:8bb9f3a33240	968	/**
mbed_official	174:8bb9f3a33240	969	* @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
mbed_official	174:8bb9f3a33240	970	*/
mbed_official	174:8bb9f3a33240	971
mbed_official	174:8bb9f3a33240	972	typedef struct { /!< SCT0 Structure /
mbed_official	174:8bb9f3a33240	973	__IO uint32_t CONFIG; /!< SCT configuration register /
mbed_official	174:8bb9f3a33240	974	__IO uint32_t CTRL; /!< SCT control register /
mbed_official	174:8bb9f3a33240	975	__IO uint32_t LIMIT; /!< SCT limit register /
mbed_official	174:8bb9f3a33240	976	__IO uint32_t HALT; /!< SCT halt condition register /
mbed_official	174:8bb9f3a33240	977	__IO uint32_t STOP; /!< SCT stop condition register /
mbed_official	174:8bb9f3a33240	978	__IO uint32_t START; /!< SCT start condition register /
mbed_official	174:8bb9f3a33240	979	__I uint32_t RESERVED0[10];
mbed_official	174:8bb9f3a33240	980	__IO uint32_t COUNT; /!< SCT counter register /
mbed_official	174:8bb9f3a33240	981	__IO uint32_t STATE; /!< SCT state register /
mbed_official	174:8bb9f3a33240	982	__I uint32_t INPUT; /!< SCT input register /
mbed_official	174:8bb9f3a33240	983	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
mbed_official	174:8bb9f3a33240	984	__IO uint32_t OUTPUT; /!< SCT output register /
mbed_official	174:8bb9f3a33240	985	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
mbed_official	174:8bb9f3a33240	986	__IO uint32_t RES; /!< SCT conflict resolution register /
mbed_official	174:8bb9f3a33240	987	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
mbed_official	174:8bb9f3a33240	988	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
mbed_official	174:8bb9f3a33240	989	__I uint32_t RESERVED1[35];
mbed_official	174:8bb9f3a33240	990	__IO uint32_t EVEN; /!< SCT event enable register /
mbed_official	174:8bb9f3a33240	991	__IO uint32_t EVFLAG; /!< SCT event flag register /
mbed_official	174:8bb9f3a33240	992	__IO uint32_t CONEN; /!< SCT conflict enable register /
mbed_official	174:8bb9f3a33240	993	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
mbed_official	174:8bb9f3a33240	994
mbed_official	174:8bb9f3a33240	995	union {
mbed_official	174:8bb9f3a33240	996	__IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
mbed_official	174:8bb9f3a33240	997	= 1 */
mbed_official	174:8bb9f3a33240	998	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
mbed_official	174:8bb9f3a33240	999	REGMODE4 = 0 */
mbed_official	174:8bb9f3a33240	1000	};
mbed_official	174:8bb9f3a33240	1001
mbed_official	174:8bb9f3a33240	1002	union {
mbed_official	174:8bb9f3a33240	1003	__IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
mbed_official	174:8bb9f3a33240	1004	= 1 */
mbed_official	174:8bb9f3a33240	1005	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
mbed_official	174:8bb9f3a33240	1006	REGMODE4 = 0 */
mbed_official	174:8bb9f3a33240	1007	};
mbed_official	174:8bb9f3a33240	1008
mbed_official	174:8bb9f3a33240	1009	union {
mbed_official	174:8bb9f3a33240	1010	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
mbed_official	174:8bb9f3a33240	1011	REGMODE4 = 0 */
mbed_official	174:8bb9f3a33240	1012	__IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
mbed_official	174:8bb9f3a33240	1013	= 1 */
mbed_official	174:8bb9f3a33240	1014	};
mbed_official	174:8bb9f3a33240	1015
mbed_official	174:8bb9f3a33240	1016	union {
mbed_official	174:8bb9f3a33240	1017	__IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
mbed_official	174:8bb9f3a33240	1018	= 1 */
mbed_official	174:8bb9f3a33240	1019	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
mbed_official	174:8bb9f3a33240	1020	REGMODE4 = 0 */
mbed_official	174:8bb9f3a33240	1021	};
mbed_official	174:8bb9f3a33240	1022
mbed_official	174:8bb9f3a33240	1023	union {
mbed_official	174:8bb9f3a33240	1024	__IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
mbed_official	174:8bb9f3a33240	1025	= 1 */
mbed_official	174:8bb9f3a33240	1026	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
mbed_official	174:8bb9f3a33240	1027	REGMODE4 = 0 */
mbed_official	174:8bb9f3a33240	1028	};
mbed_official	174:8bb9f3a33240	1029	__I uint32_t RESERVED2[59];
mbed_official	174:8bb9f3a33240	1030
mbed_official	174:8bb9f3a33240	1031	union {
mbed_official	174:8bb9f3a33240	1032	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
mbed_official	174:8bb9f3a33240	1033	= 1 */
mbed_official	174:8bb9f3a33240	1034	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
mbed_official	174:8bb9f3a33240	1035	= 0 */
mbed_official	174:8bb9f3a33240	1036	};
mbed_official	174:8bb9f3a33240	1037
mbed_official	174:8bb9f3a33240	1038	union {
mbed_official	174:8bb9f3a33240	1039	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
mbed_official	174:8bb9f3a33240	1040	= 0 */
mbed_official	174:8bb9f3a33240	1041	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
mbed_official	174:8bb9f3a33240	1042	= 1 */
mbed_official	174:8bb9f3a33240	1043	};
mbed_official	174:8bb9f3a33240	1044
mbed_official	174:8bb9f3a33240	1045	union {
mbed_official	174:8bb9f3a33240	1046	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
mbed_official	174:8bb9f3a33240	1047	= 0 */
mbed_official	174:8bb9f3a33240	1048	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
mbed_official	174:8bb9f3a33240	1049	= 1 */
mbed_official	174:8bb9f3a33240	1050	};
mbed_official	174:8bb9f3a33240	1051
mbed_official	174:8bb9f3a33240	1052	union {
mbed_official	174:8bb9f3a33240	1053	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
mbed_official	174:8bb9f3a33240	1054	= 1 */
mbed_official	174:8bb9f3a33240	1055	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
mbed_official	174:8bb9f3a33240	1056	= 0 */
mbed_official	174:8bb9f3a33240	1057	};
mbed_official	174:8bb9f3a33240	1058
mbed_official	174:8bb9f3a33240	1059	union {
mbed_official	174:8bb9f3a33240	1060	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
mbed_official	174:8bb9f3a33240	1061	= 1 */
mbed_official	174:8bb9f3a33240	1062	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
mbed_official	174:8bb9f3a33240	1063	= 0 */
mbed_official	174:8bb9f3a33240	1064	};
mbed_official	174:8bb9f3a33240	1065	__I uint32_t RESERVED3[59];
mbed_official	174:8bb9f3a33240	1066	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1067	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1068	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1069	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1070	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1071	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1072	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1073	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1074	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1075	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1076	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
mbed_official	174:8bb9f3a33240	1077	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
mbed_official	174:8bb9f3a33240	1078	__I uint32_t RESERVED4[116];
mbed_official	174:8bb9f3a33240	1079	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
mbed_official	174:8bb9f3a33240	1080	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
mbed_official	174:8bb9f3a33240	1081	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
mbed_official	174:8bb9f3a33240	1082	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
mbed_official	174:8bb9f3a33240	1083	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
mbed_official	174:8bb9f3a33240	1084	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
mbed_official	174:8bb9f3a33240	1085	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
mbed_official	174:8bb9f3a33240	1086	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
mbed_official	174:8bb9f3a33240	1087	} LPC_SCT0_Type;
mbed_official	174:8bb9f3a33240	1088
mbed_official	174:8bb9f3a33240	1089
mbed_official	174:8bb9f3a33240	1090	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1091	/* ================ GPIO_PORT ================ */
mbed_official	174:8bb9f3a33240	1092	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1093
mbed_official	174:8bb9f3a33240	1094
mbed_official	174:8bb9f3a33240	1095	/**
mbed_official	174:8bb9f3a33240	1096	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
mbed_official	174:8bb9f3a33240	1097	*/
mbed_official	174:8bb9f3a33240	1098
mbed_official	174:8bb9f3a33240	1099	typedef struct { /!< GPIO_PORT Structure /
mbed_official	174:8bb9f3a33240	1100	__IO uint8_t B[88]; /!< Byte pin registers /
mbed_official	174:8bb9f3a33240	1101	__I uint32_t RESERVED0[42];
mbed_official	174:8bb9f3a33240	1102	__IO uint32_t W[88]; /!< Word pin registers /
mbed_official	174:8bb9f3a33240	1103	__I uint32_t RESERVED1[1896];
mbed_official	174:8bb9f3a33240	1104	__IO uint32_t DIR[3]; /!< Port Direction registers /
mbed_official	174:8bb9f3a33240	1105	__I uint32_t RESERVED2[29];
mbed_official	174:8bb9f3a33240	1106	__IO uint32_t MASK[3]; /!< Port Mask register /
mbed_official	174:8bb9f3a33240	1107	__I uint32_t RESERVED3[29];
mbed_official	174:8bb9f3a33240	1108	__IO uint32_t PIN[3]; /!< Port pin register /
mbed_official	174:8bb9f3a33240	1109	__I uint32_t RESERVED4[29];
mbed_official	174:8bb9f3a33240	1110	__IO uint32_t MPIN[3]; /!< Masked port register /
mbed_official	174:8bb9f3a33240	1111	__I uint32_t RESERVED5[29];
mbed_official	174:8bb9f3a33240	1112	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
mbed_official	174:8bb9f3a33240	1113	__I uint32_t RESERVED6[29];
mbed_official	174:8bb9f3a33240	1114	__O uint32_t CLR[3]; /!< Clear port /
mbed_official	174:8bb9f3a33240	1115	__I uint32_t RESERVED7[29];
mbed_official	174:8bb9f3a33240	1116	__O uint32_t NOT[3]; /!< Toggle port /
mbed_official	174:8bb9f3a33240	1117	} LPC_GPIO_PORT_Type;
mbed_official	174:8bb9f3a33240	1118
mbed_official	174:8bb9f3a33240	1119
mbed_official	174:8bb9f3a33240	1120	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1121	/* ================ PINT ================ */
mbed_official	174:8bb9f3a33240	1122	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1123
mbed_official	174:8bb9f3a33240	1124
mbed_official	174:8bb9f3a33240	1125	/**
mbed_official	174:8bb9f3a33240	1126	* @brief Pin interruptand pattern match (PINT) (PINT)
mbed_official	174:8bb9f3a33240	1127	*/
mbed_official	174:8bb9f3a33240	1128
mbed_official	174:8bb9f3a33240	1129	typedef struct { /!< PINT Structure /
mbed_official	174:8bb9f3a33240	1130	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
mbed_official	174:8bb9f3a33240	1131	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
mbed_official	174:8bb9f3a33240	1132	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
mbed_official	174:8bb9f3a33240	1133	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
mbed_official	174:8bb9f3a33240	1134	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
mbed_official	174:8bb9f3a33240	1135	register */
mbed_official	174:8bb9f3a33240	1136	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
mbed_official	174:8bb9f3a33240	1137	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
mbed_official	174:8bb9f3a33240	1138	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
mbed_official	174:8bb9f3a33240	1139	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
mbed_official	174:8bb9f3a33240	1140	__IO uint32_t IST; /!< Pin interrupt status register /
mbed_official	174:8bb9f3a33240	1141	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
mbed_official	174:8bb9f3a33240	1142	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
mbed_official	174:8bb9f3a33240	1143	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
mbed_official	174:8bb9f3a33240	1144	} LPC_PINT_Type;
mbed_official	174:8bb9f3a33240	1145
mbed_official	174:8bb9f3a33240	1146
mbed_official	174:8bb9f3a33240	1147	/* -------------------- End of section using anonymous unions ------------------- */
mbed_official	174:8bb9f3a33240	1148	#if defined(__CC_ARM)
mbed_official	174:8bb9f3a33240	1149	#pragma pop
mbed_official	174:8bb9f3a33240	1150	#elif defined(__ICCARM__)
mbed_official	174:8bb9f3a33240	1151	/* leave anonymous unions enabled */
mbed_official	174:8bb9f3a33240	1152	#elif defined(__GNUC__)
mbed_official	174:8bb9f3a33240	1153	/* anonymous unions are enabled by default */
mbed_official	174:8bb9f3a33240	1154	#elif defined(__TMS470__)
mbed_official	174:8bb9f3a33240	1155	/* anonymous unions are enabled by default */
mbed_official	174:8bb9f3a33240	1156	#elif defined(__TASKING__)
mbed_official	174:8bb9f3a33240	1157	#pragma warning restore
mbed_official	174:8bb9f3a33240	1158	#else
mbed_official	174:8bb9f3a33240	1159	#warning Not supported compiler type
mbed_official	174:8bb9f3a33240	1160	#endif
mbed_official	174:8bb9f3a33240	1161
mbed_official	174:8bb9f3a33240	1162
mbed_official	174:8bb9f3a33240	1163
mbed_official	174:8bb9f3a33240	1164
mbed_official	174:8bb9f3a33240	1165	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1166	/* ================ Peripheral memory map ================ */
mbed_official	174:8bb9f3a33240	1167	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1168
mbed_official	174:8bb9f3a33240	1169	#define LPC_I2C0_BASE 0x40000000UL
mbed_official	174:8bb9f3a33240	1170	#define LPC_WWDT_BASE 0x40004000UL
mbed_official	174:8bb9f3a33240	1171	#define LPC_USART0_BASE 0x40008000UL
mbed_official	174:8bb9f3a33240	1172	#define LPC_CT16B0_BASE 0x4000C000UL
mbed_official	174:8bb9f3a33240	1173	#define LPC_CT16B1_BASE 0x40010000UL
mbed_official	174:8bb9f3a33240	1174	#define LPC_CT32B0_BASE 0x40014000UL
mbed_official	174:8bb9f3a33240	1175	#define LPC_CT32B1_BASE 0x40018000UL
mbed_official	174:8bb9f3a33240	1176	#define LPC_ADC_BASE 0x4001C000UL
mbed_official	174:8bb9f3a33240	1177	#define LPC_I2C1_BASE 0x40020000UL
mbed_official	174:8bb9f3a33240	1178	#define LPC_RTC_BASE 0x40024000UL
mbed_official	174:8bb9f3a33240	1179	#define LPC_DMATRIGMUX_BASE 0x40028000UL
mbed_official	174:8bb9f3a33240	1180	#define LPC_PMU_BASE 0x40038000UL
mbed_official	174:8bb9f3a33240	1181	#define LPC_FLASHCTRL_BASE 0x4003C000UL
mbed_official	174:8bb9f3a33240	1182	#define LPC_SSP0_BASE 0x40040000UL
mbed_official	174:8bb9f3a33240	1183	#define LPC_IOCON_BASE 0x40044000UL
mbed_official	174:8bb9f3a33240	1184	#define LPC_SYSCON_BASE 0x40048000UL
mbed_official	174:8bb9f3a33240	1185	#define LPC_USART4_BASE 0x4004C000UL
mbed_official	174:8bb9f3a33240	1186	#define LPC_SSP1_BASE 0x40058000UL
mbed_official	174:8bb9f3a33240	1187	#define LPC_GINT0_BASE 0x4005C000UL
mbed_official	174:8bb9f3a33240	1188	#define LPC_GINT1_BASE 0x40060000UL
mbed_official	174:8bb9f3a33240	1189	#define LPC_USART1_BASE 0x4006C000UL
mbed_official	174:8bb9f3a33240	1190	#define LPC_USART2_BASE 0x40070000UL
mbed_official	174:8bb9f3a33240	1191	#define LPC_USART3_BASE 0x40074000UL
mbed_official	174:8bb9f3a33240	1192	#define LPC_USB_BASE 0x40080000UL
mbed_official	174:8bb9f3a33240	1193	#define LPC_CRC_BASE 0x50000000UL
mbed_official	174:8bb9f3a33240	1194	#define LPC_DMA_BASE 0x50004000UL
mbed_official	174:8bb9f3a33240	1195	#define LPC_SCT0_BASE 0x5000C000UL
mbed_official	174:8bb9f3a33240	1196	#define LPC_SCT1_BASE 0x5000E000UL
mbed_official	174:8bb9f3a33240	1197	#define LPC_GPIO_PORT_BASE 0xA0000000UL
mbed_official	174:8bb9f3a33240	1198	#define LPC_PINT_BASE 0xA0004000UL
mbed_official	174:8bb9f3a33240	1199
mbed_official	174:8bb9f3a33240	1200
mbed_official	174:8bb9f3a33240	1201	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1202	/* ================ Peripheral declaration ================ */
mbed_official	174:8bb9f3a33240	1203	/* ================================================================================ */
mbed_official	174:8bb9f3a33240	1204
mbed_official	174:8bb9f3a33240	1205	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
mbed_official	174:8bb9f3a33240	1206	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
mbed_official	174:8bb9f3a33240	1207	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
mbed_official	174:8bb9f3a33240	1208	#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
mbed_official	174:8bb9f3a33240	1209	#define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
mbed_official	174:8bb9f3a33240	1210	#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
mbed_official	174:8bb9f3a33240	1211	#define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
mbed_official	174:8bb9f3a33240	1212	#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
mbed_official	174:8bb9f3a33240	1213	#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
mbed_official	174:8bb9f3a33240	1214	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
mbed_official	174:8bb9f3a33240	1215	#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
mbed_official	174:8bb9f3a33240	1216	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
mbed_official	174:8bb9f3a33240	1217	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
mbed_official	174:8bb9f3a33240	1218	#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
mbed_official	174:8bb9f3a33240	1219	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
mbed_official	174:8bb9f3a33240	1220	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
mbed_official	174:8bb9f3a33240	1221	#define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
mbed_official	174:8bb9f3a33240	1222	#define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
mbed_official	174:8bb9f3a33240	1223	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
mbed_official	174:8bb9f3a33240	1224	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
mbed_official	174:8bb9f3a33240	1225	#define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
mbed_official	174:8bb9f3a33240	1226	#define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
mbed_official	174:8bb9f3a33240	1227	#define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
mbed_official	174:8bb9f3a33240	1228	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
mbed_official	174:8bb9f3a33240	1229	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
mbed_official	174:8bb9f3a33240	1230	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
mbed_official	174:8bb9f3a33240	1231	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
mbed_official	174:8bb9f3a33240	1232	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
mbed_official	174:8bb9f3a33240	1233	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
mbed_official	174:8bb9f3a33240	1234	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
mbed_official	174:8bb9f3a33240	1235
mbed_official	174:8bb9f3a33240	1236
mbed_official	174:8bb9f3a33240	1237	/** @} / / End of group Device_Peripheral_Registers */
mbed_official	174:8bb9f3a33240	1238	/** @} / / End of group LPC11U6x */
mbed_official	174:8bb9f3a33240	1239	/** @} / / End of group (null) */
mbed_official	174:8bb9f3a33240	1240
mbed_official	174:8bb9f3a33240	1241	#ifdef __cplusplus
mbed_official	174:8bb9f3a33240	1242	}
mbed_official	174:8bb9f3a33240	1243	#endif
mbed_official	174:8bb9f3a33240	1244
mbed_official	174:8bb9f3a33240	1245
mbed_official	174:8bb9f3a33240	1246	#endif /* LPC11U6x_H */
mbed_official	174:8bb9f3a33240	1247

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Type:	Library
Created:	27 Sep 2014
Imports:	24
Forks:	0
Commits:	333
Dependents:	0
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Followers:	2

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targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@332:e299ae530e63, 2014-09-27 (annotated)

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