Geremia G / mbed-src

- fix F411 F334 systeminit when HSI used - portinout always read IDR regardless of port direction

Fork of mbed-src by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h@332:e299ae530e63, 2014-09-27 (annotated)

Committer:
Geremia
Date:
Sat Sep 27 11:16:28 2014 +0000
Revision:
332:e299ae530e63
Parent:
324:406fd2029f23 
- fix F411 F334 systeminit when HSI used; - STMs PortInOut port.read() always read input data register (real external pin state) even if direction is output (same as other platforms)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 324:406fd2029f23 7 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 10 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 11 ** Build: b140604
mbed_official 324:406fd2029f23 12 **
mbed_official 324:406fd2029f23 13 ** Abstract:
mbed_official 324:406fd2029f23 14 ** CMSIS Peripheral Access Layer for MK22F51212
mbed_official 324:406fd2029f23 15 **
mbed_official 324:406fd2029f23 16 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 17 ** All rights reserved.
mbed_official 324:406fd2029f23 18 **
mbed_official 324:406fd2029f23 19 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 20 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 23 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 24 **
mbed_official 324:406fd2029f23 25 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 26 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 27 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 28 **
mbed_official 324:406fd2029f23 29 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 30 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 31 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 32 **
mbed_official 324:406fd2029f23 33 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 34 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 35 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 36 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 37 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 38 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 39 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 40 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 41 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 42 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 43 **
mbed_official 324:406fd2029f23 44 ** http: www.freescale.com
mbed_official 324:406fd2029f23 45 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 46 **
mbed_official 324:406fd2029f23 47 ** Revisions:
mbed_official 324:406fd2029f23 48 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 49 ** Initial version.
mbed_official 324:406fd2029f23 50 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 51 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 52 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 53 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 54 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 55 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 56 ** System initialization updated.
mbed_official 324:406fd2029f23 57 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 58 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 59 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 60 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 61 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 63 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 64 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 65 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 66 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 67 ** Update of system and startup files.
mbed_official 324:406fd2029f23 68 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 69 **
mbed_official 324:406fd2029f23 70 ** ###################################################################
mbed_official 324:406fd2029f23 71 */
mbed_official 324:406fd2029f23 72
mbed_official 324:406fd2029f23 73 /*!
mbed_official 324:406fd2029f23 74 * @file MK22F51212.h
mbed_official 324:406fd2029f23 75 * @version 2.5
mbed_official 324:406fd2029f23 76 * @date 2014-05-06
mbed_official 324:406fd2029f23 77 * @brief CMSIS Peripheral Access Layer for MK22F51212
mbed_official 324:406fd2029f23 78 *
mbed_official 324:406fd2029f23 79 * CMSIS Peripheral Access Layer for MK22F51212
mbed_official 324:406fd2029f23 80 */
mbed_official 324:406fd2029f23 81
mbed_official 324:406fd2029f23 82
mbed_official 324:406fd2029f23 83 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 84 -- MCU activation
mbed_official 324:406fd2029f23 85 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 86
mbed_official 324:406fd2029f23 87 /* Prevention from multiple including the same memory map */
mbed_official 324:406fd2029f23 88 #if !defined(MK22F51212_H_) /* Check if memory map has not been already included */
mbed_official 324:406fd2029f23 89 #define MK22F51212_H_
mbed_official 324:406fd2029f23 90 #define MCU_MK22F51212
mbed_official 324:406fd2029f23 91
mbed_official 324:406fd2029f23 92 /* Check if another memory map has not been also included */
mbed_official 324:406fd2029f23 93 #if (defined(MCU_ACTIVE))
mbed_official 324:406fd2029f23 94 #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included.
mbed_official 324:406fd2029f23 95 #endif /* (defined(MCU_ACTIVE)) */
mbed_official 324:406fd2029f23 96 #define MCU_ACTIVE
mbed_official 324:406fd2029f23 97
mbed_official 324:406fd2029f23 98 #include <stdint.h>
mbed_official 324:406fd2029f23 99
mbed_official 324:406fd2029f23 100 /** Memory map major version (memory maps with equal major version number are
mbed_official 324:406fd2029f23 101 * compatible) */
mbed_official 324:406fd2029f23 102 #define MCU_MEM_MAP_VERSION 0x0200u
mbed_official 324:406fd2029f23 103 /** Memory map minor version */
mbed_official 324:406fd2029f23 104 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 /**
mbed_official 324:406fd2029f23 107 * @brief Macro to calculate address of an aliased word in the peripheral
mbed_official 324:406fd2029f23 108 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
mbed_official 324:406fd2029f23 109 * 0x400FFFFF).
mbed_official 324:406fd2029f23 110 * @param Reg Register to access.
mbed_official 324:406fd2029f23 111 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 112 * @return Address of the aliased word in the peripheral bitband area.
mbed_official 324:406fd2029f23 113 */
mbed_official 324:406fd2029f23 114 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
mbed_official 324:406fd2029f23 115 /**
mbed_official 324:406fd2029f23 116 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 324:406fd2029f23 117 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 324:406fd2029f23 118 * be used for peripherals with 32bit access allowed.
mbed_official 324:406fd2029f23 119 * @param Reg Register to access.
mbed_official 324:406fd2029f23 120 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 121 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 122 */
mbed_official 324:406fd2029f23 123 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 324:406fd2029f23 124 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
mbed_official 324:406fd2029f23 125 /**
mbed_official 324:406fd2029f23 126 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 324:406fd2029f23 127 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 324:406fd2029f23 128 * be used for peripherals with 16bit access allowed.
mbed_official 324:406fd2029f23 129 * @param Reg Register to access.
mbed_official 324:406fd2029f23 130 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 131 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 132 */
mbed_official 324:406fd2029f23 133 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 324:406fd2029f23 134 /**
mbed_official 324:406fd2029f23 135 * @brief Macro to access a single bit of a peripheral register (bit band region
mbed_official 324:406fd2029f23 136 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
mbed_official 324:406fd2029f23 137 * be used for peripherals with 8bit access allowed.
mbed_official 324:406fd2029f23 138 * @param Reg Register to access.
mbed_official 324:406fd2029f23 139 * @param Bit Bit number to access.
mbed_official 324:406fd2029f23 140 * @return Value of the targeted bit in the bit band region.
mbed_official 324:406fd2029f23 141 */
mbed_official 324:406fd2029f23 142 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
mbed_official 324:406fd2029f23 143
mbed_official 324:406fd2029f23 144 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 145 -- Interrupt vector numbers
mbed_official 324:406fd2029f23 146 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 147
mbed_official 324:406fd2029f23 148 /*!
mbed_official 324:406fd2029f23 149 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 324:406fd2029f23 150 * @{
mbed_official 324:406fd2029f23 151 */
mbed_official 324:406fd2029f23 152
mbed_official 324:406fd2029f23 153 /** Interrupt Number Definitions */
mbed_official 324:406fd2029f23 154 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
mbed_official 324:406fd2029f23 155
mbed_official 324:406fd2029f23 156 typedef enum IRQn {
mbed_official 324:406fd2029f23 157 /* Core interrupts */
mbed_official 324:406fd2029f23 158 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 324:406fd2029f23 159 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
mbed_official 324:406fd2029f23 160 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
mbed_official 324:406fd2029f23 161 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
mbed_official 324:406fd2029f23 162 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
mbed_official 324:406fd2029f23 163 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
mbed_official 324:406fd2029f23 164 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
mbed_official 324:406fd2029f23 165 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
mbed_official 324:406fd2029f23 166 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
mbed_official 324:406fd2029f23 167
mbed_official 324:406fd2029f23 168 /* Device specific interrupts */
mbed_official 324:406fd2029f23 169 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
mbed_official 324:406fd2029f23 170 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
mbed_official 324:406fd2029f23 171 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
mbed_official 324:406fd2029f23 172 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
mbed_official 324:406fd2029f23 173 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
mbed_official 324:406fd2029f23 174 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
mbed_official 324:406fd2029f23 175 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
mbed_official 324:406fd2029f23 176 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
mbed_official 324:406fd2029f23 177 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
mbed_official 324:406fd2029f23 178 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
mbed_official 324:406fd2029f23 179 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
mbed_official 324:406fd2029f23 180 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
mbed_official 324:406fd2029f23 181 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
mbed_official 324:406fd2029f23 182 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
mbed_official 324:406fd2029f23 183 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
mbed_official 324:406fd2029f23 184 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
mbed_official 324:406fd2029f23 185 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
mbed_official 324:406fd2029f23 186 MCM_IRQn = 17, /**< Normal Interrupt */
mbed_official 324:406fd2029f23 187 FTF_IRQn = 18, /**< FTFA Command complete interrupt */
mbed_official 324:406fd2029f23 188 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
mbed_official 324:406fd2029f23 189 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 324:406fd2029f23 190 LLW_IRQn = 21, /**< Low Leakage Wakeup */
mbed_official 324:406fd2029f23 191 Watchdog_IRQn = 22, /**< WDOG Interrupt */
mbed_official 324:406fd2029f23 192 RNG_IRQn = 23, /**< RNG Interrupt */
mbed_official 324:406fd2029f23 193 I2C0_IRQn = 24, /**< I2C0 interrupt */
mbed_official 324:406fd2029f23 194 I2C1_IRQn = 25, /**< I2C1 interrupt */
mbed_official 324:406fd2029f23 195 SPI0_IRQn = 26, /**< SPI0 Interrupt */
mbed_official 324:406fd2029f23 196 SPI1_IRQn = 27, /**< SPI1 Interrupt */
mbed_official 324:406fd2029f23 197 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
mbed_official 324:406fd2029f23 198 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
mbed_official 324:406fd2029f23 199 LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
mbed_official 324:406fd2029f23 200 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
mbed_official 324:406fd2029f23 201 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
mbed_official 324:406fd2029f23 202 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
mbed_official 324:406fd2029f23 203 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
mbed_official 324:406fd2029f23 204 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
mbed_official 324:406fd2029f23 205 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
mbed_official 324:406fd2029f23 206 Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
mbed_official 324:406fd2029f23 207 Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
mbed_official 324:406fd2029f23 208 ADC0_IRQn = 39, /**< ADC0 interrupt */
mbed_official 324:406fd2029f23 209 CMP0_IRQn = 40, /**< CMP0 interrupt */
mbed_official 324:406fd2029f23 210 CMP1_IRQn = 41, /**< CMP1 interrupt */
mbed_official 324:406fd2029f23 211 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
mbed_official 324:406fd2029f23 212 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
mbed_official 324:406fd2029f23 213 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
mbed_official 324:406fd2029f23 214 Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
mbed_official 324:406fd2029f23 215 RTC_IRQn = 46, /**< RTC interrupt */
mbed_official 324:406fd2029f23 216 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
mbed_official 324:406fd2029f23 217 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
mbed_official 324:406fd2029f23 218 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
mbed_official 324:406fd2029f23 219 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
mbed_official 324:406fd2029f23 220 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
mbed_official 324:406fd2029f23 221 PDB0_IRQn = 52, /**< PDB0 Interrupt */
mbed_official 324:406fd2029f23 222 USB0_IRQn = 53, /**< USB0 interrupt */
mbed_official 324:406fd2029f23 223 Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
mbed_official 324:406fd2029f23 224 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
mbed_official 324:406fd2029f23 225 DAC0_IRQn = 56, /**< DAC0 interrupt */
mbed_official 324:406fd2029f23 226 MCG_IRQn = 57, /**< MCG Interrupt */
mbed_official 324:406fd2029f23 227 LPTimer_IRQn = 58, /**< LPTimer interrupt */
mbed_official 324:406fd2029f23 228 PORTA_IRQn = 59, /**< Port A interrupt */
mbed_official 324:406fd2029f23 229 PORTB_IRQn = 60, /**< Port B interrupt */
mbed_official 324:406fd2029f23 230 PORTC_IRQn = 61, /**< Port C interrupt */
mbed_official 324:406fd2029f23 231 PORTD_IRQn = 62, /**< Port D interrupt */
mbed_official 324:406fd2029f23 232 PORTE_IRQn = 63, /**< Port E interrupt */
mbed_official 324:406fd2029f23 233 SWI_IRQn = 64, /**< Software interrupt */
mbed_official 324:406fd2029f23 234 Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
mbed_official 324:406fd2029f23 235 Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
mbed_official 324:406fd2029f23 236 Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
mbed_official 324:406fd2029f23 237 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
mbed_official 324:406fd2029f23 238 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
mbed_official 324:406fd2029f23 239 Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
mbed_official 324:406fd2029f23 240 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
mbed_official 324:406fd2029f23 241 DAC1_IRQn = 72, /**< DAC1 interrupt */
mbed_official 324:406fd2029f23 242 ADC1_IRQn = 73, /**< ADC1 interrupt */
mbed_official 324:406fd2029f23 243 Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
mbed_official 324:406fd2029f23 244 Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
mbed_official 324:406fd2029f23 245 Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
mbed_official 324:406fd2029f23 246 Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
mbed_official 324:406fd2029f23 247 Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
mbed_official 324:406fd2029f23 248 Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
mbed_official 324:406fd2029f23 249 Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
mbed_official 324:406fd2029f23 250 Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
mbed_official 324:406fd2029f23 251 Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
mbed_official 324:406fd2029f23 252 Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
mbed_official 324:406fd2029f23 253 Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
mbed_official 324:406fd2029f23 254 Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
mbed_official 324:406fd2029f23 255 } IRQn_Type;
mbed_official 324:406fd2029f23 256
mbed_official 324:406fd2029f23 257 /*!
mbed_official 324:406fd2029f23 258 * @}
mbed_official 324:406fd2029f23 259 */ /* end of group Interrupt_vector_numbers */
mbed_official 324:406fd2029f23 260
mbed_official 324:406fd2029f23 261
mbed_official 324:406fd2029f23 262 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 263 -- Cortex M4 Core Configuration
mbed_official 324:406fd2029f23 264 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 265
mbed_official 324:406fd2029f23 266 /*!
mbed_official 324:406fd2029f23 267 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
mbed_official 324:406fd2029f23 268 * @{
mbed_official 324:406fd2029f23 269 */
mbed_official 324:406fd2029f23 270
mbed_official 324:406fd2029f23 271 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 324:406fd2029f23 272 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
mbed_official 324:406fd2029f23 273 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 324:406fd2029f23 274 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
mbed_official 324:406fd2029f23 275
mbed_official 324:406fd2029f23 276 #include "core_cm4.h" /* Core Peripheral Access Layer */
mbed_official 324:406fd2029f23 277 #include "system_MK22F51212.h" /* Device specific configuration file */
mbed_official 324:406fd2029f23 278
mbed_official 324:406fd2029f23 279 /*!
mbed_official 324:406fd2029f23 280 * @}
mbed_official 324:406fd2029f23 281 */ /* end of group Cortex_Core_Configuration */
mbed_official 324:406fd2029f23 282
mbed_official 324:406fd2029f23 283
mbed_official 324:406fd2029f23 284 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 285 -- Device Peripheral Access Layer
mbed_official 324:406fd2029f23 286 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 287
mbed_official 324:406fd2029f23 288 /*!
mbed_official 324:406fd2029f23 289 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 324:406fd2029f23 290 * @{
mbed_official 324:406fd2029f23 291 */
mbed_official 324:406fd2029f23 292
mbed_official 324:406fd2029f23 293
mbed_official 324:406fd2029f23 294 /*
mbed_official 324:406fd2029f23 295 ** Start of section using anonymous unions
mbed_official 324:406fd2029f23 296 */
mbed_official 324:406fd2029f23 297
mbed_official 324:406fd2029f23 298 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 299 #pragma push
mbed_official 324:406fd2029f23 300 #pragma anon_unions
mbed_official 324:406fd2029f23 301 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 302 #pragma push
mbed_official 324:406fd2029f23 303 #pragma cpp_extensions on
mbed_official 324:406fd2029f23 304 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 305 /* anonymous unions are enabled by default */
mbed_official 324:406fd2029f23 306 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 307 #pragma language=extended
mbed_official 324:406fd2029f23 308 #else
mbed_official 324:406fd2029f23 309 #error Not supported compiler type
mbed_official 324:406fd2029f23 310 #endif
mbed_official 324:406fd2029f23 311
mbed_official 324:406fd2029f23 312 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 313 -- ADC Peripheral Access Layer
mbed_official 324:406fd2029f23 314 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 315
mbed_official 324:406fd2029f23 316 /*!
mbed_official 324:406fd2029f23 317 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 324:406fd2029f23 318 * @{
mbed_official 324:406fd2029f23 319 */
mbed_official 324:406fd2029f23 320
mbed_official 324:406fd2029f23 321 /** ADC - Register Layout Typedef */
mbed_official 324:406fd2029f23 322 typedef struct {
mbed_official 324:406fd2029f23 323 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 324:406fd2029f23 324 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 324:406fd2029f23 325 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 324:406fd2029f23 326 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 324:406fd2029f23 327 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 324:406fd2029f23 328 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 324:406fd2029f23 329 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 324:406fd2029f23 330 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 324:406fd2029f23 331 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 324:406fd2029f23 332 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 324:406fd2029f23 333 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 324:406fd2029f23 334 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 324:406fd2029f23 335 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 324:406fd2029f23 336 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 324:406fd2029f23 337 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 324:406fd2029f23 338 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 324:406fd2029f23 339 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 324:406fd2029f23 340 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 324:406fd2029f23 341 uint8_t RESERVED_0[4];
mbed_official 324:406fd2029f23 342 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 324:406fd2029f23 343 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 324:406fd2029f23 344 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 324:406fd2029f23 345 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 324:406fd2029f23 346 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 324:406fd2029f23 347 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 324:406fd2029f23 348 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 324:406fd2029f23 349 } ADC_Type, *ADC_MemMapPtr;
mbed_official 324:406fd2029f23 350
mbed_official 324:406fd2029f23 351 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 352 -- ADC - Register accessor macros
mbed_official 324:406fd2029f23 353 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 354
mbed_official 324:406fd2029f23 355 /*!
mbed_official 324:406fd2029f23 356 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 324:406fd2029f23 357 * @{
mbed_official 324:406fd2029f23 358 */
mbed_official 324:406fd2029f23 359
mbed_official 324:406fd2029f23 360
mbed_official 324:406fd2029f23 361 /* ADC - Register accessors */
mbed_official 324:406fd2029f23 362 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
mbed_official 324:406fd2029f23 363 #define ADC_CFG1_REG(base) ((base)->CFG1)
mbed_official 324:406fd2029f23 364 #define ADC_CFG2_REG(base) ((base)->CFG2)
mbed_official 324:406fd2029f23 365 #define ADC_R_REG(base,index) ((base)->R[index])
mbed_official 324:406fd2029f23 366 #define ADC_CV1_REG(base) ((base)->CV1)
mbed_official 324:406fd2029f23 367 #define ADC_CV2_REG(base) ((base)->CV2)
mbed_official 324:406fd2029f23 368 #define ADC_SC2_REG(base) ((base)->SC2)
mbed_official 324:406fd2029f23 369 #define ADC_SC3_REG(base) ((base)->SC3)
mbed_official 324:406fd2029f23 370 #define ADC_OFS_REG(base) ((base)->OFS)
mbed_official 324:406fd2029f23 371 #define ADC_PG_REG(base) ((base)->PG)
mbed_official 324:406fd2029f23 372 #define ADC_MG_REG(base) ((base)->MG)
mbed_official 324:406fd2029f23 373 #define ADC_CLPD_REG(base) ((base)->CLPD)
mbed_official 324:406fd2029f23 374 #define ADC_CLPS_REG(base) ((base)->CLPS)
mbed_official 324:406fd2029f23 375 #define ADC_CLP4_REG(base) ((base)->CLP4)
mbed_official 324:406fd2029f23 376 #define ADC_CLP3_REG(base) ((base)->CLP3)
mbed_official 324:406fd2029f23 377 #define ADC_CLP2_REG(base) ((base)->CLP2)
mbed_official 324:406fd2029f23 378 #define ADC_CLP1_REG(base) ((base)->CLP1)
mbed_official 324:406fd2029f23 379 #define ADC_CLP0_REG(base) ((base)->CLP0)
mbed_official 324:406fd2029f23 380 #define ADC_CLMD_REG(base) ((base)->CLMD)
mbed_official 324:406fd2029f23 381 #define ADC_CLMS_REG(base) ((base)->CLMS)
mbed_official 324:406fd2029f23 382 #define ADC_CLM4_REG(base) ((base)->CLM4)
mbed_official 324:406fd2029f23 383 #define ADC_CLM3_REG(base) ((base)->CLM3)
mbed_official 324:406fd2029f23 384 #define ADC_CLM2_REG(base) ((base)->CLM2)
mbed_official 324:406fd2029f23 385 #define ADC_CLM1_REG(base) ((base)->CLM1)
mbed_official 324:406fd2029f23 386 #define ADC_CLM0_REG(base) ((base)->CLM0)
mbed_official 324:406fd2029f23 387
mbed_official 324:406fd2029f23 388 /*!
mbed_official 324:406fd2029f23 389 * @}
mbed_official 324:406fd2029f23 390 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 391
mbed_official 324:406fd2029f23 392
mbed_official 324:406fd2029f23 393 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 394 -- ADC Register Masks
mbed_official 324:406fd2029f23 395 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 396
mbed_official 324:406fd2029f23 397 /*!
mbed_official 324:406fd2029f23 398 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 324:406fd2029f23 399 * @{
mbed_official 324:406fd2029f23 400 */
mbed_official 324:406fd2029f23 401
mbed_official 324:406fd2029f23 402 /* SC1 Bit Fields */
mbed_official 324:406fd2029f23 403 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 324:406fd2029f23 404 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 324:406fd2029f23 405 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 324:406fd2029f23 406 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 324:406fd2029f23 407 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 324:406fd2029f23 408 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 324:406fd2029f23 409 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 324:406fd2029f23 410 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 324:406fd2029f23 411 #define ADC_SC1_COCO_SHIFT 7
mbed_official 324:406fd2029f23 412 /* CFG1 Bit Fields */
mbed_official 324:406fd2029f23 413 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 324:406fd2029f23 414 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 324:406fd2029f23 415 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 324:406fd2029f23 416 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 324:406fd2029f23 417 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 324:406fd2029f23 418 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 324:406fd2029f23 419 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 324:406fd2029f23 420 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 324:406fd2029f23 421 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 324:406fd2029f23 422 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 324:406fd2029f23 423 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 324:406fd2029f23 424 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 324:406fd2029f23 425 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 324:406fd2029f23 426 /* CFG2 Bit Fields */
mbed_official 324:406fd2029f23 427 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 324:406fd2029f23 428 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 324:406fd2029f23 429 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 324:406fd2029f23 430 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 324:406fd2029f23 431 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 324:406fd2029f23 432 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 324:406fd2029f23 433 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 324:406fd2029f23 434 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 324:406fd2029f23 435 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 324:406fd2029f23 436 /* R Bit Fields */
mbed_official 324:406fd2029f23 437 #define ADC_R_D_MASK 0xFFFFu
mbed_official 324:406fd2029f23 438 #define ADC_R_D_SHIFT 0
mbed_official 324:406fd2029f23 439 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 324:406fd2029f23 440 /* CV1 Bit Fields */
mbed_official 324:406fd2029f23 441 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 324:406fd2029f23 442 #define ADC_CV1_CV_SHIFT 0
mbed_official 324:406fd2029f23 443 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 324:406fd2029f23 444 /* CV2 Bit Fields */
mbed_official 324:406fd2029f23 445 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 324:406fd2029f23 446 #define ADC_CV2_CV_SHIFT 0
mbed_official 324:406fd2029f23 447 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 324:406fd2029f23 448 /* SC2 Bit Fields */
mbed_official 324:406fd2029f23 449 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 324:406fd2029f23 450 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 324:406fd2029f23 451 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 324:406fd2029f23 452 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 324:406fd2029f23 453 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 324:406fd2029f23 454 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 324:406fd2029f23 455 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 324:406fd2029f23 456 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 324:406fd2029f23 457 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 324:406fd2029f23 458 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 324:406fd2029f23 459 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 324:406fd2029f23 460 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 324:406fd2029f23 461 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 324:406fd2029f23 462 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 324:406fd2029f23 463 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 324:406fd2029f23 464 /* SC3 Bit Fields */
mbed_official 324:406fd2029f23 465 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 324:406fd2029f23 466 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 324:406fd2029f23 467 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 324:406fd2029f23 468 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 324:406fd2029f23 469 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 324:406fd2029f23 470 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 324:406fd2029f23 471 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 324:406fd2029f23 472 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 324:406fd2029f23 473 #define ADC_SC3_CALF_SHIFT 6
mbed_official 324:406fd2029f23 474 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 324:406fd2029f23 475 #define ADC_SC3_CAL_SHIFT 7
mbed_official 324:406fd2029f23 476 /* OFS Bit Fields */
mbed_official 324:406fd2029f23 477 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 324:406fd2029f23 478 #define ADC_OFS_OFS_SHIFT 0
mbed_official 324:406fd2029f23 479 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 324:406fd2029f23 480 /* PG Bit Fields */
mbed_official 324:406fd2029f23 481 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 324:406fd2029f23 482 #define ADC_PG_PG_SHIFT 0
mbed_official 324:406fd2029f23 483 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 324:406fd2029f23 484 /* MG Bit Fields */
mbed_official 324:406fd2029f23 485 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 324:406fd2029f23 486 #define ADC_MG_MG_SHIFT 0
mbed_official 324:406fd2029f23 487 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 324:406fd2029f23 488 /* CLPD Bit Fields */
mbed_official 324:406fd2029f23 489 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 324:406fd2029f23 490 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 324:406fd2029f23 491 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 324:406fd2029f23 492 /* CLPS Bit Fields */
mbed_official 324:406fd2029f23 493 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 324:406fd2029f23 494 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 324:406fd2029f23 495 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 324:406fd2029f23 496 /* CLP4 Bit Fields */
mbed_official 324:406fd2029f23 497 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 324:406fd2029f23 498 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 324:406fd2029f23 499 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 324:406fd2029f23 500 /* CLP3 Bit Fields */
mbed_official 324:406fd2029f23 501 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 324:406fd2029f23 502 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 324:406fd2029f23 503 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 324:406fd2029f23 504 /* CLP2 Bit Fields */
mbed_official 324:406fd2029f23 505 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 324:406fd2029f23 506 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 324:406fd2029f23 507 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 324:406fd2029f23 508 /* CLP1 Bit Fields */
mbed_official 324:406fd2029f23 509 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 324:406fd2029f23 510 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 324:406fd2029f23 511 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 324:406fd2029f23 512 /* CLP0 Bit Fields */
mbed_official 324:406fd2029f23 513 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 324:406fd2029f23 514 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 324:406fd2029f23 515 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 324:406fd2029f23 516 /* CLMD Bit Fields */
mbed_official 324:406fd2029f23 517 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 324:406fd2029f23 518 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 324:406fd2029f23 519 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 324:406fd2029f23 520 /* CLMS Bit Fields */
mbed_official 324:406fd2029f23 521 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 324:406fd2029f23 522 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 324:406fd2029f23 523 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 324:406fd2029f23 524 /* CLM4 Bit Fields */
mbed_official 324:406fd2029f23 525 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 324:406fd2029f23 526 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 324:406fd2029f23 527 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 324:406fd2029f23 528 /* CLM3 Bit Fields */
mbed_official 324:406fd2029f23 529 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 324:406fd2029f23 530 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 324:406fd2029f23 531 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 324:406fd2029f23 532 /* CLM2 Bit Fields */
mbed_official 324:406fd2029f23 533 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 324:406fd2029f23 534 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 324:406fd2029f23 535 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 324:406fd2029f23 536 /* CLM1 Bit Fields */
mbed_official 324:406fd2029f23 537 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 324:406fd2029f23 538 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 324:406fd2029f23 539 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 324:406fd2029f23 540 /* CLM0 Bit Fields */
mbed_official 324:406fd2029f23 541 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 324:406fd2029f23 542 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 324:406fd2029f23 543 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 324:406fd2029f23 544
mbed_official 324:406fd2029f23 545 /*!
mbed_official 324:406fd2029f23 546 * @}
mbed_official 324:406fd2029f23 547 */ /* end of group ADC_Register_Masks */
mbed_official 324:406fd2029f23 548
mbed_official 324:406fd2029f23 549
mbed_official 324:406fd2029f23 550 /* ADC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 551 /** Peripheral ADC0 base address */
mbed_official 324:406fd2029f23 552 #define ADC0_BASE (0x4003B000u)
mbed_official 324:406fd2029f23 553 /** Peripheral ADC0 base pointer */
mbed_official 324:406fd2029f23 554 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 324:406fd2029f23 555 #define ADC0_BASE_PTR (ADC0)
mbed_official 324:406fd2029f23 556 /** Peripheral ADC1 base address */
mbed_official 324:406fd2029f23 557 #define ADC1_BASE (0x40027000u)
mbed_official 324:406fd2029f23 558 /** Peripheral ADC1 base pointer */
mbed_official 324:406fd2029f23 559 #define ADC1 ((ADC_Type *)ADC1_BASE)
mbed_official 324:406fd2029f23 560 #define ADC1_BASE_PTR (ADC1)
mbed_official 324:406fd2029f23 561 /** Array initializer of ADC peripheral base addresses */
mbed_official 324:406fd2029f23 562 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
mbed_official 324:406fd2029f23 563 /** Array initializer of ADC peripheral base pointers */
mbed_official 324:406fd2029f23 564 #define ADC_BASE_PTRS { ADC0, ADC1 }
mbed_official 324:406fd2029f23 565 /** Interrupt vectors for the ADC peripheral type */
mbed_official 324:406fd2029f23 566 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
mbed_official 324:406fd2029f23 567
mbed_official 324:406fd2029f23 568 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 569 -- ADC - Register accessor macros
mbed_official 324:406fd2029f23 570 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 571
mbed_official 324:406fd2029f23 572 /*!
mbed_official 324:406fd2029f23 573 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 324:406fd2029f23 574 * @{
mbed_official 324:406fd2029f23 575 */
mbed_official 324:406fd2029f23 576
mbed_official 324:406fd2029f23 577
mbed_official 324:406fd2029f23 578 /* ADC - Register instance definitions */
mbed_official 324:406fd2029f23 579 /* ADC0 */
mbed_official 324:406fd2029f23 580 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
mbed_official 324:406fd2029f23 581 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
mbed_official 324:406fd2029f23 582 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
mbed_official 324:406fd2029f23 583 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
mbed_official 324:406fd2029f23 584 #define ADC0_RA ADC_R_REG(ADC0,0)
mbed_official 324:406fd2029f23 585 #define ADC0_RB ADC_R_REG(ADC0,1)
mbed_official 324:406fd2029f23 586 #define ADC0_CV1 ADC_CV1_REG(ADC0)
mbed_official 324:406fd2029f23 587 #define ADC0_CV2 ADC_CV2_REG(ADC0)
mbed_official 324:406fd2029f23 588 #define ADC0_SC2 ADC_SC2_REG(ADC0)
mbed_official 324:406fd2029f23 589 #define ADC0_SC3 ADC_SC3_REG(ADC0)
mbed_official 324:406fd2029f23 590 #define ADC0_OFS ADC_OFS_REG(ADC0)
mbed_official 324:406fd2029f23 591 #define ADC0_PG ADC_PG_REG(ADC0)
mbed_official 324:406fd2029f23 592 #define ADC0_MG ADC_MG_REG(ADC0)
mbed_official 324:406fd2029f23 593 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
mbed_official 324:406fd2029f23 594 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
mbed_official 324:406fd2029f23 595 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
mbed_official 324:406fd2029f23 596 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
mbed_official 324:406fd2029f23 597 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
mbed_official 324:406fd2029f23 598 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
mbed_official 324:406fd2029f23 599 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
mbed_official 324:406fd2029f23 600 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
mbed_official 324:406fd2029f23 601 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
mbed_official 324:406fd2029f23 602 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
mbed_official 324:406fd2029f23 603 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
mbed_official 324:406fd2029f23 604 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
mbed_official 324:406fd2029f23 605 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
mbed_official 324:406fd2029f23 606 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
mbed_official 324:406fd2029f23 607 /* ADC1 */
mbed_official 324:406fd2029f23 608 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
mbed_official 324:406fd2029f23 609 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
mbed_official 324:406fd2029f23 610 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
mbed_official 324:406fd2029f23 611 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
mbed_official 324:406fd2029f23 612 #define ADC1_RA ADC_R_REG(ADC1,0)
mbed_official 324:406fd2029f23 613 #define ADC1_RB ADC_R_REG(ADC1,1)
mbed_official 324:406fd2029f23 614 #define ADC1_CV1 ADC_CV1_REG(ADC1)
mbed_official 324:406fd2029f23 615 #define ADC1_CV2 ADC_CV2_REG(ADC1)
mbed_official 324:406fd2029f23 616 #define ADC1_SC2 ADC_SC2_REG(ADC1)
mbed_official 324:406fd2029f23 617 #define ADC1_SC3 ADC_SC3_REG(ADC1)
mbed_official 324:406fd2029f23 618 #define ADC1_OFS ADC_OFS_REG(ADC1)
mbed_official 324:406fd2029f23 619 #define ADC1_PG ADC_PG_REG(ADC1)
mbed_official 324:406fd2029f23 620 #define ADC1_MG ADC_MG_REG(ADC1)
mbed_official 324:406fd2029f23 621 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
mbed_official 324:406fd2029f23 622 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
mbed_official 324:406fd2029f23 623 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
mbed_official 324:406fd2029f23 624 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
mbed_official 324:406fd2029f23 625 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
mbed_official 324:406fd2029f23 626 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
mbed_official 324:406fd2029f23 627 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
mbed_official 324:406fd2029f23 628 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
mbed_official 324:406fd2029f23 629 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
mbed_official 324:406fd2029f23 630 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
mbed_official 324:406fd2029f23 631 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
mbed_official 324:406fd2029f23 632 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
mbed_official 324:406fd2029f23 633 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
mbed_official 324:406fd2029f23 634 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
mbed_official 324:406fd2029f23 635
mbed_official 324:406fd2029f23 636 /* ADC - Register array accessors */
mbed_official 324:406fd2029f23 637 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
mbed_official 324:406fd2029f23 638 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
mbed_official 324:406fd2029f23 639 #define ADC0_R(index) ADC_R_REG(ADC0,index)
mbed_official 324:406fd2029f23 640 #define ADC1_R(index) ADC_R_REG(ADC1,index)
mbed_official 324:406fd2029f23 641
mbed_official 324:406fd2029f23 642 /*!
mbed_official 324:406fd2029f23 643 * @}
mbed_official 324:406fd2029f23 644 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 645
mbed_official 324:406fd2029f23 646
mbed_official 324:406fd2029f23 647 /*!
mbed_official 324:406fd2029f23 648 * @}
mbed_official 324:406fd2029f23 649 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 650
mbed_official 324:406fd2029f23 651
mbed_official 324:406fd2029f23 652 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 653 -- CMP Peripheral Access Layer
mbed_official 324:406fd2029f23 654 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 655
mbed_official 324:406fd2029f23 656 /*!
mbed_official 324:406fd2029f23 657 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 324:406fd2029f23 658 * @{
mbed_official 324:406fd2029f23 659 */
mbed_official 324:406fd2029f23 660
mbed_official 324:406fd2029f23 661 /** CMP - Register Layout Typedef */
mbed_official 324:406fd2029f23 662 typedef struct {
mbed_official 324:406fd2029f23 663 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 324:406fd2029f23 664 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 324:406fd2029f23 665 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 324:406fd2029f23 666 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 324:406fd2029f23 667 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 324:406fd2029f23 668 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 324:406fd2029f23 669 } CMP_Type, *CMP_MemMapPtr;
mbed_official 324:406fd2029f23 670
mbed_official 324:406fd2029f23 671 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 672 -- CMP - Register accessor macros
mbed_official 324:406fd2029f23 673 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 674
mbed_official 324:406fd2029f23 675 /*!
mbed_official 324:406fd2029f23 676 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 324:406fd2029f23 677 * @{
mbed_official 324:406fd2029f23 678 */
mbed_official 324:406fd2029f23 679
mbed_official 324:406fd2029f23 680
mbed_official 324:406fd2029f23 681 /* CMP - Register accessors */
mbed_official 324:406fd2029f23 682 #define CMP_CR0_REG(base) ((base)->CR0)
mbed_official 324:406fd2029f23 683 #define CMP_CR1_REG(base) ((base)->CR1)
mbed_official 324:406fd2029f23 684 #define CMP_FPR_REG(base) ((base)->FPR)
mbed_official 324:406fd2029f23 685 #define CMP_SCR_REG(base) ((base)->SCR)
mbed_official 324:406fd2029f23 686 #define CMP_DACCR_REG(base) ((base)->DACCR)
mbed_official 324:406fd2029f23 687 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
mbed_official 324:406fd2029f23 688
mbed_official 324:406fd2029f23 689 /*!
mbed_official 324:406fd2029f23 690 * @}
mbed_official 324:406fd2029f23 691 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 692
mbed_official 324:406fd2029f23 693
mbed_official 324:406fd2029f23 694 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 695 -- CMP Register Masks
mbed_official 324:406fd2029f23 696 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 697
mbed_official 324:406fd2029f23 698 /*!
mbed_official 324:406fd2029f23 699 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 324:406fd2029f23 700 * @{
mbed_official 324:406fd2029f23 701 */
mbed_official 324:406fd2029f23 702
mbed_official 324:406fd2029f23 703 /* CR0 Bit Fields */
mbed_official 324:406fd2029f23 704 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 324:406fd2029f23 705 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 324:406fd2029f23 706 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 324:406fd2029f23 707 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 324:406fd2029f23 708 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 324:406fd2029f23 709 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 324:406fd2029f23 710 /* CR1 Bit Fields */
mbed_official 324:406fd2029f23 711 #define CMP_CR1_EN_MASK 0x1u
mbed_official 324:406fd2029f23 712 #define CMP_CR1_EN_SHIFT 0
mbed_official 324:406fd2029f23 713 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 324:406fd2029f23 714 #define CMP_CR1_OPE_SHIFT 1
mbed_official 324:406fd2029f23 715 #define CMP_CR1_COS_MASK 0x4u
mbed_official 324:406fd2029f23 716 #define CMP_CR1_COS_SHIFT 2
mbed_official 324:406fd2029f23 717 #define CMP_CR1_INV_MASK 0x8u
mbed_official 324:406fd2029f23 718 #define CMP_CR1_INV_SHIFT 3
mbed_official 324:406fd2029f23 719 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 324:406fd2029f23 720 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 324:406fd2029f23 721 #define CMP_CR1_TRIGM_MASK 0x20u
mbed_official 324:406fd2029f23 722 #define CMP_CR1_TRIGM_SHIFT 5
mbed_official 324:406fd2029f23 723 #define CMP_CR1_WE_MASK 0x40u
mbed_official 324:406fd2029f23 724 #define CMP_CR1_WE_SHIFT 6
mbed_official 324:406fd2029f23 725 #define CMP_CR1_SE_MASK 0x80u
mbed_official 324:406fd2029f23 726 #define CMP_CR1_SE_SHIFT 7
mbed_official 324:406fd2029f23 727 /* FPR Bit Fields */
mbed_official 324:406fd2029f23 728 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 324:406fd2029f23 729 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 324:406fd2029f23 730 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 324:406fd2029f23 731 /* SCR Bit Fields */
mbed_official 324:406fd2029f23 732 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 324:406fd2029f23 733 #define CMP_SCR_COUT_SHIFT 0
mbed_official 324:406fd2029f23 734 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 324:406fd2029f23 735 #define CMP_SCR_CFF_SHIFT 1
mbed_official 324:406fd2029f23 736 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 324:406fd2029f23 737 #define CMP_SCR_CFR_SHIFT 2
mbed_official 324:406fd2029f23 738 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 324:406fd2029f23 739 #define CMP_SCR_IEF_SHIFT 3
mbed_official 324:406fd2029f23 740 #define CMP_SCR_IER_MASK 0x10u
mbed_official 324:406fd2029f23 741 #define CMP_SCR_IER_SHIFT 4
mbed_official 324:406fd2029f23 742 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 324:406fd2029f23 743 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 324:406fd2029f23 744 /* DACCR Bit Fields */
mbed_official 324:406fd2029f23 745 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 324:406fd2029f23 746 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 324:406fd2029f23 747 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 324:406fd2029f23 748 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 324:406fd2029f23 749 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 324:406fd2029f23 750 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 324:406fd2029f23 751 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 324:406fd2029f23 752 /* MUXCR Bit Fields */
mbed_official 324:406fd2029f23 753 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 324:406fd2029f23 754 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 324:406fd2029f23 755 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 324:406fd2029f23 756 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 324:406fd2029f23 757 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 324:406fd2029f23 758 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 324:406fd2029f23 759
mbed_official 324:406fd2029f23 760 /*!
mbed_official 324:406fd2029f23 761 * @}
mbed_official 324:406fd2029f23 762 */ /* end of group CMP_Register_Masks */
mbed_official 324:406fd2029f23 763
mbed_official 324:406fd2029f23 764
mbed_official 324:406fd2029f23 765 /* CMP - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 766 /** Peripheral CMP0 base address */
mbed_official 324:406fd2029f23 767 #define CMP0_BASE (0x40073000u)
mbed_official 324:406fd2029f23 768 /** Peripheral CMP0 base pointer */
mbed_official 324:406fd2029f23 769 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 324:406fd2029f23 770 #define CMP0_BASE_PTR (CMP0)
mbed_official 324:406fd2029f23 771 /** Peripheral CMP1 base address */
mbed_official 324:406fd2029f23 772 #define CMP1_BASE (0x40073008u)
mbed_official 324:406fd2029f23 773 /** Peripheral CMP1 base pointer */
mbed_official 324:406fd2029f23 774 #define CMP1 ((CMP_Type *)CMP1_BASE)
mbed_official 324:406fd2029f23 775 #define CMP1_BASE_PTR (CMP1)
mbed_official 324:406fd2029f23 776 /** Array initializer of CMP peripheral base addresses */
mbed_official 324:406fd2029f23 777 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
mbed_official 324:406fd2029f23 778 /** Array initializer of CMP peripheral base pointers */
mbed_official 324:406fd2029f23 779 #define CMP_BASE_PTRS { CMP0, CMP1 }
mbed_official 324:406fd2029f23 780 /** Interrupt vectors for the CMP peripheral type */
mbed_official 324:406fd2029f23 781 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
mbed_official 324:406fd2029f23 782
mbed_official 324:406fd2029f23 783 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 784 -- CMP - Register accessor macros
mbed_official 324:406fd2029f23 785 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 786
mbed_official 324:406fd2029f23 787 /*!
mbed_official 324:406fd2029f23 788 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 324:406fd2029f23 789 * @{
mbed_official 324:406fd2029f23 790 */
mbed_official 324:406fd2029f23 791
mbed_official 324:406fd2029f23 792
mbed_official 324:406fd2029f23 793 /* CMP - Register instance definitions */
mbed_official 324:406fd2029f23 794 /* CMP0 */
mbed_official 324:406fd2029f23 795 #define CMP0_CR0 CMP_CR0_REG(CMP0)
mbed_official 324:406fd2029f23 796 #define CMP0_CR1 CMP_CR1_REG(CMP0)
mbed_official 324:406fd2029f23 797 #define CMP0_FPR CMP_FPR_REG(CMP0)
mbed_official 324:406fd2029f23 798 #define CMP0_SCR CMP_SCR_REG(CMP0)
mbed_official 324:406fd2029f23 799 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
mbed_official 324:406fd2029f23 800 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
mbed_official 324:406fd2029f23 801 /* CMP1 */
mbed_official 324:406fd2029f23 802 #define CMP1_CR0 CMP_CR0_REG(CMP1)
mbed_official 324:406fd2029f23 803 #define CMP1_CR1 CMP_CR1_REG(CMP1)
mbed_official 324:406fd2029f23 804 #define CMP1_FPR CMP_FPR_REG(CMP1)
mbed_official 324:406fd2029f23 805 #define CMP1_SCR CMP_SCR_REG(CMP1)
mbed_official 324:406fd2029f23 806 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
mbed_official 324:406fd2029f23 807 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
mbed_official 324:406fd2029f23 808
mbed_official 324:406fd2029f23 809 /*!
mbed_official 324:406fd2029f23 810 * @}
mbed_official 324:406fd2029f23 811 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 812
mbed_official 324:406fd2029f23 813
mbed_official 324:406fd2029f23 814 /*!
mbed_official 324:406fd2029f23 815 * @}
mbed_official 324:406fd2029f23 816 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 817
mbed_official 324:406fd2029f23 818
mbed_official 324:406fd2029f23 819 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 820 -- CRC Peripheral Access Layer
mbed_official 324:406fd2029f23 821 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 822
mbed_official 324:406fd2029f23 823 /*!
mbed_official 324:406fd2029f23 824 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
mbed_official 324:406fd2029f23 825 * @{
mbed_official 324:406fd2029f23 826 */
mbed_official 324:406fd2029f23 827
mbed_official 324:406fd2029f23 828 /** CRC - Register Layout Typedef */
mbed_official 324:406fd2029f23 829 typedef struct {
mbed_official 324:406fd2029f23 830 union { /* offset: 0x0 */
mbed_official 324:406fd2029f23 831 struct { /* offset: 0x0 */
mbed_official 324:406fd2029f23 832 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
mbed_official 324:406fd2029f23 833 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
mbed_official 324:406fd2029f23 834 } ACCESS16BIT;
mbed_official 324:406fd2029f23 835 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
mbed_official 324:406fd2029f23 836 struct { /* offset: 0x0 */
mbed_official 324:406fd2029f23 837 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
mbed_official 324:406fd2029f23 838 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
mbed_official 324:406fd2029f23 839 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
mbed_official 324:406fd2029f23 840 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
mbed_official 324:406fd2029f23 841 } ACCESS8BIT;
mbed_official 324:406fd2029f23 842 };
mbed_official 324:406fd2029f23 843 union { /* offset: 0x4 */
mbed_official 324:406fd2029f23 844 struct { /* offset: 0x4 */
mbed_official 324:406fd2029f23 845 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
mbed_official 324:406fd2029f23 846 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
mbed_official 324:406fd2029f23 847 } GPOLY_ACCESS16BIT;
mbed_official 324:406fd2029f23 848 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
mbed_official 324:406fd2029f23 849 struct { /* offset: 0x4 */
mbed_official 324:406fd2029f23 850 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
mbed_official 324:406fd2029f23 851 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
mbed_official 324:406fd2029f23 852 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
mbed_official 324:406fd2029f23 853 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
mbed_official 324:406fd2029f23 854 } GPOLY_ACCESS8BIT;
mbed_official 324:406fd2029f23 855 };
mbed_official 324:406fd2029f23 856 union { /* offset: 0x8 */
mbed_official 324:406fd2029f23 857 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
mbed_official 324:406fd2029f23 858 struct { /* offset: 0x8 */
mbed_official 324:406fd2029f23 859 uint8_t RESERVED_0[3];
mbed_official 324:406fd2029f23 860 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
mbed_official 324:406fd2029f23 861 } CTRL_ACCESS8BIT;
mbed_official 324:406fd2029f23 862 };
mbed_official 324:406fd2029f23 863 } CRC_Type, *CRC_MemMapPtr;
mbed_official 324:406fd2029f23 864
mbed_official 324:406fd2029f23 865 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 866 -- CRC - Register accessor macros
mbed_official 324:406fd2029f23 867 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 868
mbed_official 324:406fd2029f23 869 /*!
mbed_official 324:406fd2029f23 870 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
mbed_official 324:406fd2029f23 871 * @{
mbed_official 324:406fd2029f23 872 */
mbed_official 324:406fd2029f23 873
mbed_official 324:406fd2029f23 874
mbed_official 324:406fd2029f23 875 /* CRC - Register accessors */
mbed_official 324:406fd2029f23 876 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
mbed_official 324:406fd2029f23 877 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
mbed_official 324:406fd2029f23 878 #define CRC_DATA_REG(base) ((base)->DATA)
mbed_official 324:406fd2029f23 879 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
mbed_official 324:406fd2029f23 880 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
mbed_official 324:406fd2029f23 881 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
mbed_official 324:406fd2029f23 882 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
mbed_official 324:406fd2029f23 883 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
mbed_official 324:406fd2029f23 884 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
mbed_official 324:406fd2029f23 885 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
mbed_official 324:406fd2029f23 886 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
mbed_official 324:406fd2029f23 887 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
mbed_official 324:406fd2029f23 888 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
mbed_official 324:406fd2029f23 889 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
mbed_official 324:406fd2029f23 890 #define CRC_CTRL_REG(base) ((base)->CTRL)
mbed_official 324:406fd2029f23 891 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
mbed_official 324:406fd2029f23 892
mbed_official 324:406fd2029f23 893 /*!
mbed_official 324:406fd2029f23 894 * @}
mbed_official 324:406fd2029f23 895 */ /* end of group CRC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 896
mbed_official 324:406fd2029f23 897
mbed_official 324:406fd2029f23 898 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 899 -- CRC Register Masks
mbed_official 324:406fd2029f23 900 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 901
mbed_official 324:406fd2029f23 902 /*!
mbed_official 324:406fd2029f23 903 * @addtogroup CRC_Register_Masks CRC Register Masks
mbed_official 324:406fd2029f23 904 * @{
mbed_official 324:406fd2029f23 905 */
mbed_official 324:406fd2029f23 906
mbed_official 324:406fd2029f23 907 /* DATAL Bit Fields */
mbed_official 324:406fd2029f23 908 #define CRC_DATAL_DATAL_MASK 0xFFFFu
mbed_official 324:406fd2029f23 909 #define CRC_DATAL_DATAL_SHIFT 0
mbed_official 324:406fd2029f23 910 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
mbed_official 324:406fd2029f23 911 /* DATAH Bit Fields */
mbed_official 324:406fd2029f23 912 #define CRC_DATAH_DATAH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 913 #define CRC_DATAH_DATAH_SHIFT 0
mbed_official 324:406fd2029f23 914 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
mbed_official 324:406fd2029f23 915 /* DATA Bit Fields */
mbed_official 324:406fd2029f23 916 #define CRC_DATA_LL_MASK 0xFFu
mbed_official 324:406fd2029f23 917 #define CRC_DATA_LL_SHIFT 0
mbed_official 324:406fd2029f23 918 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
mbed_official 324:406fd2029f23 919 #define CRC_DATA_LU_MASK 0xFF00u
mbed_official 324:406fd2029f23 920 #define CRC_DATA_LU_SHIFT 8
mbed_official 324:406fd2029f23 921 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
mbed_official 324:406fd2029f23 922 #define CRC_DATA_HL_MASK 0xFF0000u
mbed_official 324:406fd2029f23 923 #define CRC_DATA_HL_SHIFT 16
mbed_official 324:406fd2029f23 924 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
mbed_official 324:406fd2029f23 925 #define CRC_DATA_HU_MASK 0xFF000000u
mbed_official 324:406fd2029f23 926 #define CRC_DATA_HU_SHIFT 24
mbed_official 324:406fd2029f23 927 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
mbed_official 324:406fd2029f23 928 /* DATALL Bit Fields */
mbed_official 324:406fd2029f23 929 #define CRC_DATALL_DATALL_MASK 0xFFu
mbed_official 324:406fd2029f23 930 #define CRC_DATALL_DATALL_SHIFT 0
mbed_official 324:406fd2029f23 931 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
mbed_official 324:406fd2029f23 932 /* DATALU Bit Fields */
mbed_official 324:406fd2029f23 933 #define CRC_DATALU_DATALU_MASK 0xFFu
mbed_official 324:406fd2029f23 934 #define CRC_DATALU_DATALU_SHIFT 0
mbed_official 324:406fd2029f23 935 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
mbed_official 324:406fd2029f23 936 /* DATAHL Bit Fields */
mbed_official 324:406fd2029f23 937 #define CRC_DATAHL_DATAHL_MASK 0xFFu
mbed_official 324:406fd2029f23 938 #define CRC_DATAHL_DATAHL_SHIFT 0
mbed_official 324:406fd2029f23 939 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
mbed_official 324:406fd2029f23 940 /* DATAHU Bit Fields */
mbed_official 324:406fd2029f23 941 #define CRC_DATAHU_DATAHU_MASK 0xFFu
mbed_official 324:406fd2029f23 942 #define CRC_DATAHU_DATAHU_SHIFT 0
mbed_official 324:406fd2029f23 943 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
mbed_official 324:406fd2029f23 944 /* GPOLYL Bit Fields */
mbed_official 324:406fd2029f23 945 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
mbed_official 324:406fd2029f23 946 #define CRC_GPOLYL_GPOLYL_SHIFT 0
mbed_official 324:406fd2029f23 947 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
mbed_official 324:406fd2029f23 948 /* GPOLYH Bit Fields */
mbed_official 324:406fd2029f23 949 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 950 #define CRC_GPOLYH_GPOLYH_SHIFT 0
mbed_official 324:406fd2029f23 951 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
mbed_official 324:406fd2029f23 952 /* GPOLY Bit Fields */
mbed_official 324:406fd2029f23 953 #define CRC_GPOLY_LOW_MASK 0xFFFFu
mbed_official 324:406fd2029f23 954 #define CRC_GPOLY_LOW_SHIFT 0
mbed_official 324:406fd2029f23 955 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
mbed_official 324:406fd2029f23 956 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 957 #define CRC_GPOLY_HIGH_SHIFT 16
mbed_official 324:406fd2029f23 958 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
mbed_official 324:406fd2029f23 959 /* GPOLYLL Bit Fields */
mbed_official 324:406fd2029f23 960 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
mbed_official 324:406fd2029f23 961 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
mbed_official 324:406fd2029f23 962 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
mbed_official 324:406fd2029f23 963 /* GPOLYLU Bit Fields */
mbed_official 324:406fd2029f23 964 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
mbed_official 324:406fd2029f23 965 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
mbed_official 324:406fd2029f23 966 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
mbed_official 324:406fd2029f23 967 /* GPOLYHL Bit Fields */
mbed_official 324:406fd2029f23 968 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
mbed_official 324:406fd2029f23 969 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
mbed_official 324:406fd2029f23 970 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
mbed_official 324:406fd2029f23 971 /* GPOLYHU Bit Fields */
mbed_official 324:406fd2029f23 972 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
mbed_official 324:406fd2029f23 973 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
mbed_official 324:406fd2029f23 974 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
mbed_official 324:406fd2029f23 975 /* CTRL Bit Fields */
mbed_official 324:406fd2029f23 976 #define CRC_CTRL_TCRC_MASK 0x1000000u
mbed_official 324:406fd2029f23 977 #define CRC_CTRL_TCRC_SHIFT 24
mbed_official 324:406fd2029f23 978 #define CRC_CTRL_WAS_MASK 0x2000000u
mbed_official 324:406fd2029f23 979 #define CRC_CTRL_WAS_SHIFT 25
mbed_official 324:406fd2029f23 980 #define CRC_CTRL_FXOR_MASK 0x4000000u
mbed_official 324:406fd2029f23 981 #define CRC_CTRL_FXOR_SHIFT 26
mbed_official 324:406fd2029f23 982 #define CRC_CTRL_TOTR_MASK 0x30000000u
mbed_official 324:406fd2029f23 983 #define CRC_CTRL_TOTR_SHIFT 28
mbed_official 324:406fd2029f23 984 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
mbed_official 324:406fd2029f23 985 #define CRC_CTRL_TOT_MASK 0xC0000000u
mbed_official 324:406fd2029f23 986 #define CRC_CTRL_TOT_SHIFT 30
mbed_official 324:406fd2029f23 987 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
mbed_official 324:406fd2029f23 988 /* CTRLHU Bit Fields */
mbed_official 324:406fd2029f23 989 #define CRC_CTRLHU_TCRC_MASK 0x1u
mbed_official 324:406fd2029f23 990 #define CRC_CTRLHU_TCRC_SHIFT 0
mbed_official 324:406fd2029f23 991 #define CRC_CTRLHU_WAS_MASK 0x2u
mbed_official 324:406fd2029f23 992 #define CRC_CTRLHU_WAS_SHIFT 1
mbed_official 324:406fd2029f23 993 #define CRC_CTRLHU_FXOR_MASK 0x4u
mbed_official 324:406fd2029f23 994 #define CRC_CTRLHU_FXOR_SHIFT 2
mbed_official 324:406fd2029f23 995 #define CRC_CTRLHU_TOTR_MASK 0x30u
mbed_official 324:406fd2029f23 996 #define CRC_CTRLHU_TOTR_SHIFT 4
mbed_official 324:406fd2029f23 997 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
mbed_official 324:406fd2029f23 998 #define CRC_CTRLHU_TOT_MASK 0xC0u
mbed_official 324:406fd2029f23 999 #define CRC_CTRLHU_TOT_SHIFT 6
mbed_official 324:406fd2029f23 1000 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
mbed_official 324:406fd2029f23 1001
mbed_official 324:406fd2029f23 1002 /*!
mbed_official 324:406fd2029f23 1003 * @}
mbed_official 324:406fd2029f23 1004 */ /* end of group CRC_Register_Masks */
mbed_official 324:406fd2029f23 1005
mbed_official 324:406fd2029f23 1006
mbed_official 324:406fd2029f23 1007 /* CRC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 1008 /** Peripheral CRC base address */
mbed_official 324:406fd2029f23 1009 #define CRC_BASE (0x40032000u)
mbed_official 324:406fd2029f23 1010 /** Peripheral CRC base pointer */
mbed_official 324:406fd2029f23 1011 #define CRC0 ((CRC_Type *)CRC_BASE)
mbed_official 324:406fd2029f23 1012 #define CRC_BASE_PTR (CRC0)
mbed_official 324:406fd2029f23 1013 /** Array initializer of CRC peripheral base addresses */
mbed_official 324:406fd2029f23 1014 #define CRC_BASE_ADDRS { CRC_BASE }
mbed_official 324:406fd2029f23 1015 /** Array initializer of CRC peripheral base pointers */
mbed_official 324:406fd2029f23 1016 #define CRC_BASE_PTRS { CRC0 }
mbed_official 324:406fd2029f23 1017
mbed_official 324:406fd2029f23 1018 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1019 -- CRC - Register accessor macros
mbed_official 324:406fd2029f23 1020 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1021
mbed_official 324:406fd2029f23 1022 /*!
mbed_official 324:406fd2029f23 1023 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
mbed_official 324:406fd2029f23 1024 * @{
mbed_official 324:406fd2029f23 1025 */
mbed_official 324:406fd2029f23 1026
mbed_official 324:406fd2029f23 1027
mbed_official 324:406fd2029f23 1028 /* CRC - Register instance definitions */
mbed_official 324:406fd2029f23 1029 /* CRC */
mbed_official 324:406fd2029f23 1030 #define CRC_DATA CRC_DATA_REG(CRC0)
mbed_official 324:406fd2029f23 1031 #define CRC_DATAL CRC_DATAL_REG(CRC0)
mbed_official 324:406fd2029f23 1032 #define CRC_DATALL CRC_DATALL_REG(CRC0)
mbed_official 324:406fd2029f23 1033 #define CRC_DATALU CRC_DATALU_REG(CRC0)
mbed_official 324:406fd2029f23 1034 #define CRC_DATAH CRC_DATAH_REG(CRC0)
mbed_official 324:406fd2029f23 1035 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
mbed_official 324:406fd2029f23 1036 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
mbed_official 324:406fd2029f23 1037 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
mbed_official 324:406fd2029f23 1038 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
mbed_official 324:406fd2029f23 1039 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
mbed_official 324:406fd2029f23 1040 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
mbed_official 324:406fd2029f23 1041 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
mbed_official 324:406fd2029f23 1042 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
mbed_official 324:406fd2029f23 1043 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
mbed_official 324:406fd2029f23 1044 #define CRC_CTRL CRC_CTRL_REG(CRC0)
mbed_official 324:406fd2029f23 1045 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
mbed_official 324:406fd2029f23 1046
mbed_official 324:406fd2029f23 1047 /*!
mbed_official 324:406fd2029f23 1048 * @}
mbed_official 324:406fd2029f23 1049 */ /* end of group CRC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 1050
mbed_official 324:406fd2029f23 1051
mbed_official 324:406fd2029f23 1052 /*!
mbed_official 324:406fd2029f23 1053 * @}
mbed_official 324:406fd2029f23 1054 */ /* end of group CRC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 1055
mbed_official 324:406fd2029f23 1056
mbed_official 324:406fd2029f23 1057 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1058 -- DAC Peripheral Access Layer
mbed_official 324:406fd2029f23 1059 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1060
mbed_official 324:406fd2029f23 1061 /*!
mbed_official 324:406fd2029f23 1062 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 324:406fd2029f23 1063 * @{
mbed_official 324:406fd2029f23 1064 */
mbed_official 324:406fd2029f23 1065
mbed_official 324:406fd2029f23 1066 /** DAC - Register Layout Typedef */
mbed_official 324:406fd2029f23 1067 typedef struct {
mbed_official 324:406fd2029f23 1068 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 324:406fd2029f23 1069 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 324:406fd2029f23 1070 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 324:406fd2029f23 1071 } DAT[16];
mbed_official 324:406fd2029f23 1072 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 324:406fd2029f23 1073 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 324:406fd2029f23 1074 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 324:406fd2029f23 1075 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 324:406fd2029f23 1076 } DAC_Type, *DAC_MemMapPtr;
mbed_official 324:406fd2029f23 1077
mbed_official 324:406fd2029f23 1078 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1079 -- DAC - Register accessor macros
mbed_official 324:406fd2029f23 1080 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1081
mbed_official 324:406fd2029f23 1082 /*!
mbed_official 324:406fd2029f23 1083 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 324:406fd2029f23 1084 * @{
mbed_official 324:406fd2029f23 1085 */
mbed_official 324:406fd2029f23 1086
mbed_official 324:406fd2029f23 1087
mbed_official 324:406fd2029f23 1088 /* DAC - Register accessors */
mbed_official 324:406fd2029f23 1089 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
mbed_official 324:406fd2029f23 1090 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
mbed_official 324:406fd2029f23 1091 #define DAC_SR_REG(base) ((base)->SR)
mbed_official 324:406fd2029f23 1092 #define DAC_C0_REG(base) ((base)->C0)
mbed_official 324:406fd2029f23 1093 #define DAC_C1_REG(base) ((base)->C1)
mbed_official 324:406fd2029f23 1094 #define DAC_C2_REG(base) ((base)->C2)
mbed_official 324:406fd2029f23 1095
mbed_official 324:406fd2029f23 1096 /*!
mbed_official 324:406fd2029f23 1097 * @}
mbed_official 324:406fd2029f23 1098 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 1099
mbed_official 324:406fd2029f23 1100
mbed_official 324:406fd2029f23 1101 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1102 -- DAC Register Masks
mbed_official 324:406fd2029f23 1103 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1104
mbed_official 324:406fd2029f23 1105 /*!
mbed_official 324:406fd2029f23 1106 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 324:406fd2029f23 1107 * @{
mbed_official 324:406fd2029f23 1108 */
mbed_official 324:406fd2029f23 1109
mbed_official 324:406fd2029f23 1110 /* DATL Bit Fields */
mbed_official 324:406fd2029f23 1111 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 324:406fd2029f23 1112 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 324:406fd2029f23 1113 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 324:406fd2029f23 1114 /* DATH Bit Fields */
mbed_official 324:406fd2029f23 1115 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 324:406fd2029f23 1116 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 324:406fd2029f23 1117 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 324:406fd2029f23 1118 /* SR Bit Fields */
mbed_official 324:406fd2029f23 1119 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 324:406fd2029f23 1120 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 324:406fd2029f23 1121 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 324:406fd2029f23 1122 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 324:406fd2029f23 1123 #define DAC_SR_DACBFWMF_MASK 0x4u
mbed_official 324:406fd2029f23 1124 #define DAC_SR_DACBFWMF_SHIFT 2
mbed_official 324:406fd2029f23 1125 /* C0 Bit Fields */
mbed_official 324:406fd2029f23 1126 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 324:406fd2029f23 1127 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 324:406fd2029f23 1128 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 324:406fd2029f23 1129 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 324:406fd2029f23 1130 #define DAC_C0_DACBWIEN_MASK 0x4u
mbed_official 324:406fd2029f23 1131 #define DAC_C0_DACBWIEN_SHIFT 2
mbed_official 324:406fd2029f23 1132 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 324:406fd2029f23 1133 #define DAC_C0_LPEN_SHIFT 3
mbed_official 324:406fd2029f23 1134 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 324:406fd2029f23 1135 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 324:406fd2029f23 1136 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 324:406fd2029f23 1137 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 324:406fd2029f23 1138 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 324:406fd2029f23 1139 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 324:406fd2029f23 1140 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 324:406fd2029f23 1141 #define DAC_C0_DACEN_SHIFT 7
mbed_official 324:406fd2029f23 1142 /* C1 Bit Fields */
mbed_official 324:406fd2029f23 1143 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 324:406fd2029f23 1144 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 324:406fd2029f23 1145 #define DAC_C1_DACBFMD_MASK 0x6u
mbed_official 324:406fd2029f23 1146 #define DAC_C1_DACBFMD_SHIFT 1
mbed_official 324:406fd2029f23 1147 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
mbed_official 324:406fd2029f23 1148 #define DAC_C1_DACBFWM_MASK 0x18u
mbed_official 324:406fd2029f23 1149 #define DAC_C1_DACBFWM_SHIFT 3
mbed_official 324:406fd2029f23 1150 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
mbed_official 324:406fd2029f23 1151 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 324:406fd2029f23 1152 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 324:406fd2029f23 1153 /* C2 Bit Fields */
mbed_official 324:406fd2029f23 1154 #define DAC_C2_DACBFUP_MASK 0xFu
mbed_official 324:406fd2029f23 1155 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 324:406fd2029f23 1156 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
mbed_official 324:406fd2029f23 1157 #define DAC_C2_DACBFRP_MASK 0xF0u
mbed_official 324:406fd2029f23 1158 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 324:406fd2029f23 1159 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
mbed_official 324:406fd2029f23 1160
mbed_official 324:406fd2029f23 1161 /*!
mbed_official 324:406fd2029f23 1162 * @}
mbed_official 324:406fd2029f23 1163 */ /* end of group DAC_Register_Masks */
mbed_official 324:406fd2029f23 1164
mbed_official 324:406fd2029f23 1165
mbed_official 324:406fd2029f23 1166 /* DAC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 1167 /** Peripheral DAC0 base address */
mbed_official 324:406fd2029f23 1168 #define DAC0_BASE (0x4003F000u)
mbed_official 324:406fd2029f23 1169 /** Peripheral DAC0 base pointer */
mbed_official 324:406fd2029f23 1170 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 324:406fd2029f23 1171 #define DAC0_BASE_PTR (DAC0)
mbed_official 324:406fd2029f23 1172 /** Peripheral DAC1 base address */
mbed_official 324:406fd2029f23 1173 #define DAC1_BASE (0x40028000u)
mbed_official 324:406fd2029f23 1174 /** Peripheral DAC1 base pointer */
mbed_official 324:406fd2029f23 1175 #define DAC1 ((DAC_Type *)DAC1_BASE)
mbed_official 324:406fd2029f23 1176 #define DAC1_BASE_PTR (DAC1)
mbed_official 324:406fd2029f23 1177 /** Array initializer of DAC peripheral base addresses */
mbed_official 324:406fd2029f23 1178 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
mbed_official 324:406fd2029f23 1179 /** Array initializer of DAC peripheral base pointers */
mbed_official 324:406fd2029f23 1180 #define DAC_BASE_PTRS { DAC0, DAC1 }
mbed_official 324:406fd2029f23 1181 /** Interrupt vectors for the DAC peripheral type */
mbed_official 324:406fd2029f23 1182 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
mbed_official 324:406fd2029f23 1183
mbed_official 324:406fd2029f23 1184 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1185 -- DAC - Register accessor macros
mbed_official 324:406fd2029f23 1186 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1187
mbed_official 324:406fd2029f23 1188 /*!
mbed_official 324:406fd2029f23 1189 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 324:406fd2029f23 1190 * @{
mbed_official 324:406fd2029f23 1191 */
mbed_official 324:406fd2029f23 1192
mbed_official 324:406fd2029f23 1193
mbed_official 324:406fd2029f23 1194 /* DAC - Register instance definitions */
mbed_official 324:406fd2029f23 1195 /* DAC0 */
mbed_official 324:406fd2029f23 1196 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
mbed_official 324:406fd2029f23 1197 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
mbed_official 324:406fd2029f23 1198 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
mbed_official 324:406fd2029f23 1199 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
mbed_official 324:406fd2029f23 1200 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
mbed_official 324:406fd2029f23 1201 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
mbed_official 324:406fd2029f23 1202 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
mbed_official 324:406fd2029f23 1203 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
mbed_official 324:406fd2029f23 1204 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
mbed_official 324:406fd2029f23 1205 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
mbed_official 324:406fd2029f23 1206 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
mbed_official 324:406fd2029f23 1207 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
mbed_official 324:406fd2029f23 1208 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
mbed_official 324:406fd2029f23 1209 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
mbed_official 324:406fd2029f23 1210 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
mbed_official 324:406fd2029f23 1211 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
mbed_official 324:406fd2029f23 1212 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
mbed_official 324:406fd2029f23 1213 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
mbed_official 324:406fd2029f23 1214 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
mbed_official 324:406fd2029f23 1215 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
mbed_official 324:406fd2029f23 1216 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
mbed_official 324:406fd2029f23 1217 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
mbed_official 324:406fd2029f23 1218 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
mbed_official 324:406fd2029f23 1219 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
mbed_official 324:406fd2029f23 1220 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
mbed_official 324:406fd2029f23 1221 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
mbed_official 324:406fd2029f23 1222 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
mbed_official 324:406fd2029f23 1223 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
mbed_official 324:406fd2029f23 1224 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
mbed_official 324:406fd2029f23 1225 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
mbed_official 324:406fd2029f23 1226 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
mbed_official 324:406fd2029f23 1227 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
mbed_official 324:406fd2029f23 1228 #define DAC0_SR DAC_SR_REG(DAC0)
mbed_official 324:406fd2029f23 1229 #define DAC0_C0 DAC_C0_REG(DAC0)
mbed_official 324:406fd2029f23 1230 #define DAC0_C1 DAC_C1_REG(DAC0)
mbed_official 324:406fd2029f23 1231 #define DAC0_C2 DAC_C2_REG(DAC0)
mbed_official 324:406fd2029f23 1232 /* DAC1 */
mbed_official 324:406fd2029f23 1233 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
mbed_official 324:406fd2029f23 1234 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
mbed_official 324:406fd2029f23 1235 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
mbed_official 324:406fd2029f23 1236 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
mbed_official 324:406fd2029f23 1237 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
mbed_official 324:406fd2029f23 1238 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
mbed_official 324:406fd2029f23 1239 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
mbed_official 324:406fd2029f23 1240 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
mbed_official 324:406fd2029f23 1241 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
mbed_official 324:406fd2029f23 1242 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
mbed_official 324:406fd2029f23 1243 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
mbed_official 324:406fd2029f23 1244 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
mbed_official 324:406fd2029f23 1245 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
mbed_official 324:406fd2029f23 1246 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
mbed_official 324:406fd2029f23 1247 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
mbed_official 324:406fd2029f23 1248 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
mbed_official 324:406fd2029f23 1249 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
mbed_official 324:406fd2029f23 1250 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
mbed_official 324:406fd2029f23 1251 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
mbed_official 324:406fd2029f23 1252 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
mbed_official 324:406fd2029f23 1253 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
mbed_official 324:406fd2029f23 1254 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
mbed_official 324:406fd2029f23 1255 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
mbed_official 324:406fd2029f23 1256 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
mbed_official 324:406fd2029f23 1257 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
mbed_official 324:406fd2029f23 1258 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
mbed_official 324:406fd2029f23 1259 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
mbed_official 324:406fd2029f23 1260 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
mbed_official 324:406fd2029f23 1261 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
mbed_official 324:406fd2029f23 1262 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
mbed_official 324:406fd2029f23 1263 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
mbed_official 324:406fd2029f23 1264 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
mbed_official 324:406fd2029f23 1265 #define DAC1_SR DAC_SR_REG(DAC1)
mbed_official 324:406fd2029f23 1266 #define DAC1_C0 DAC_C0_REG(DAC1)
mbed_official 324:406fd2029f23 1267 #define DAC1_C1 DAC_C1_REG(DAC1)
mbed_official 324:406fd2029f23 1268 #define DAC1_C2 DAC_C2_REG(DAC1)
mbed_official 324:406fd2029f23 1269
mbed_official 324:406fd2029f23 1270 /* DAC - Register array accessors */
mbed_official 324:406fd2029f23 1271 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
mbed_official 324:406fd2029f23 1272 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
mbed_official 324:406fd2029f23 1273 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
mbed_official 324:406fd2029f23 1274 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
mbed_official 324:406fd2029f23 1275
mbed_official 324:406fd2029f23 1276 /*!
mbed_official 324:406fd2029f23 1277 * @}
mbed_official 324:406fd2029f23 1278 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 1279
mbed_official 324:406fd2029f23 1280
mbed_official 324:406fd2029f23 1281 /*!
mbed_official 324:406fd2029f23 1282 * @}
mbed_official 324:406fd2029f23 1283 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 1284
mbed_official 324:406fd2029f23 1285
mbed_official 324:406fd2029f23 1286 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1287 -- DMA Peripheral Access Layer
mbed_official 324:406fd2029f23 1288 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1289
mbed_official 324:406fd2029f23 1290 /*!
mbed_official 324:406fd2029f23 1291 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 324:406fd2029f23 1292 * @{
mbed_official 324:406fd2029f23 1293 */
mbed_official 324:406fd2029f23 1294
mbed_official 324:406fd2029f23 1295 /** DMA - Register Layout Typedef */
mbed_official 324:406fd2029f23 1296 typedef struct {
mbed_official 324:406fd2029f23 1297 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 1298 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
mbed_official 324:406fd2029f23 1299 uint8_t RESERVED_0[4];
mbed_official 324:406fd2029f23 1300 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
mbed_official 324:406fd2029f23 1301 uint8_t RESERVED_1[4];
mbed_official 324:406fd2029f23 1302 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
mbed_official 324:406fd2029f23 1303 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
mbed_official 324:406fd2029f23 1304 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
mbed_official 324:406fd2029f23 1305 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
mbed_official 324:406fd2029f23 1306 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
mbed_official 324:406fd2029f23 1307 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
mbed_official 324:406fd2029f23 1308 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
mbed_official 324:406fd2029f23 1309 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
mbed_official 324:406fd2029f23 1310 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
mbed_official 324:406fd2029f23 1311 uint8_t RESERVED_2[4];
mbed_official 324:406fd2029f23 1312 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
mbed_official 324:406fd2029f23 1313 uint8_t RESERVED_3[4];
mbed_official 324:406fd2029f23 1314 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
mbed_official 324:406fd2029f23 1315 uint8_t RESERVED_4[4];
mbed_official 324:406fd2029f23 1316 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
mbed_official 324:406fd2029f23 1317 uint8_t RESERVED_5[12];
mbed_official 324:406fd2029f23 1318 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
mbed_official 324:406fd2029f23 1319 uint8_t RESERVED_6[184];
mbed_official 324:406fd2029f23 1320 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
mbed_official 324:406fd2029f23 1321 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
mbed_official 324:406fd2029f23 1322 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
mbed_official 324:406fd2029f23 1323 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
mbed_official 324:406fd2029f23 1324 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
mbed_official 324:406fd2029f23 1325 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
mbed_official 324:406fd2029f23 1326 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
mbed_official 324:406fd2029f23 1327 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
mbed_official 324:406fd2029f23 1328 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
mbed_official 324:406fd2029f23 1329 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
mbed_official 324:406fd2029f23 1330 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
mbed_official 324:406fd2029f23 1331 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
mbed_official 324:406fd2029f23 1332 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
mbed_official 324:406fd2029f23 1333 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
mbed_official 324:406fd2029f23 1334 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
mbed_official 324:406fd2029f23 1335 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
mbed_official 324:406fd2029f23 1336 uint8_t RESERVED_7[3824];
mbed_official 324:406fd2029f23 1337 struct { /* offset: 0x1000, array step: 0x20 */
mbed_official 324:406fd2029f23 1338 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
mbed_official 324:406fd2029f23 1339 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
mbed_official 324:406fd2029f23 1340 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
mbed_official 324:406fd2029f23 1341 union { /* offset: 0x1008, array step: 0x20 */
mbed_official 324:406fd2029f23 1342 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 324:406fd2029f23 1343 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
mbed_official 324:406fd2029f23 1344 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
mbed_official 324:406fd2029f23 1345 };
mbed_official 324:406fd2029f23 1346 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
mbed_official 324:406fd2029f23 1347 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
mbed_official 324:406fd2029f23 1348 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
mbed_official 324:406fd2029f23 1349 union { /* offset: 0x1016, array step: 0x20 */
mbed_official 324:406fd2029f23 1350 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
mbed_official 324:406fd2029f23 1351 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
mbed_official 324:406fd2029f23 1352 };
mbed_official 324:406fd2029f23 1353 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
mbed_official 324:406fd2029f23 1354 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
mbed_official 324:406fd2029f23 1355 union { /* offset: 0x101E, array step: 0x20 */
mbed_official 324:406fd2029f23 1356 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
mbed_official 324:406fd2029f23 1357 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
mbed_official 324:406fd2029f23 1358 };
mbed_official 324:406fd2029f23 1359 } TCD[16];
mbed_official 324:406fd2029f23 1360 } DMA_Type, *DMA_MemMapPtr;
mbed_official 324:406fd2029f23 1361
mbed_official 324:406fd2029f23 1362 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1363 -- DMA - Register accessor macros
mbed_official 324:406fd2029f23 1364 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1365
mbed_official 324:406fd2029f23 1366 /*!
mbed_official 324:406fd2029f23 1367 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 324:406fd2029f23 1368 * @{
mbed_official 324:406fd2029f23 1369 */
mbed_official 324:406fd2029f23 1370
mbed_official 324:406fd2029f23 1371
mbed_official 324:406fd2029f23 1372 /* DMA - Register accessors */
mbed_official 324:406fd2029f23 1373 #define DMA_CR_REG(base) ((base)->CR)
mbed_official 324:406fd2029f23 1374 #define DMA_ES_REG(base) ((base)->ES)
mbed_official 324:406fd2029f23 1375 #define DMA_ERQ_REG(base) ((base)->ERQ)
mbed_official 324:406fd2029f23 1376 #define DMA_EEI_REG(base) ((base)->EEI)
mbed_official 324:406fd2029f23 1377 #define DMA_CEEI_REG(base) ((base)->CEEI)
mbed_official 324:406fd2029f23 1378 #define DMA_SEEI_REG(base) ((base)->SEEI)
mbed_official 324:406fd2029f23 1379 #define DMA_CERQ_REG(base) ((base)->CERQ)
mbed_official 324:406fd2029f23 1380 #define DMA_SERQ_REG(base) ((base)->SERQ)
mbed_official 324:406fd2029f23 1381 #define DMA_CDNE_REG(base) ((base)->CDNE)
mbed_official 324:406fd2029f23 1382 #define DMA_SSRT_REG(base) ((base)->SSRT)
mbed_official 324:406fd2029f23 1383 #define DMA_CERR_REG(base) ((base)->CERR)
mbed_official 324:406fd2029f23 1384 #define DMA_CINT_REG(base) ((base)->CINT)
mbed_official 324:406fd2029f23 1385 #define DMA_INT_REG(base) ((base)->INT)
mbed_official 324:406fd2029f23 1386 #define DMA_ERR_REG(base) ((base)->ERR)
mbed_official 324:406fd2029f23 1387 #define DMA_HRS_REG(base) ((base)->HRS)
mbed_official 324:406fd2029f23 1388 #define DMA_EARS_REG(base) ((base)->EARS)
mbed_official 324:406fd2029f23 1389 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
mbed_official 324:406fd2029f23 1390 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
mbed_official 324:406fd2029f23 1391 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
mbed_official 324:406fd2029f23 1392 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
mbed_official 324:406fd2029f23 1393 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
mbed_official 324:406fd2029f23 1394 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
mbed_official 324:406fd2029f23 1395 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
mbed_official 324:406fd2029f23 1396 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
mbed_official 324:406fd2029f23 1397 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
mbed_official 324:406fd2029f23 1398 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
mbed_official 324:406fd2029f23 1399 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
mbed_official 324:406fd2029f23 1400 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
mbed_official 324:406fd2029f23 1401 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
mbed_official 324:406fd2029f23 1402 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
mbed_official 324:406fd2029f23 1403 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
mbed_official 324:406fd2029f23 1404 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
mbed_official 324:406fd2029f23 1405 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
mbed_official 324:406fd2029f23 1406 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
mbed_official 324:406fd2029f23 1407 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
mbed_official 324:406fd2029f23 1408 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
mbed_official 324:406fd2029f23 1409 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
mbed_official 324:406fd2029f23 1410 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
mbed_official 324:406fd2029f23 1411 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
mbed_official 324:406fd2029f23 1412 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
mbed_official 324:406fd2029f23 1413 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
mbed_official 324:406fd2029f23 1414 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
mbed_official 324:406fd2029f23 1415 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
mbed_official 324:406fd2029f23 1416 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
mbed_official 324:406fd2029f23 1417 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
mbed_official 324:406fd2029f23 1418 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
mbed_official 324:406fd2029f23 1419 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
mbed_official 324:406fd2029f23 1420
mbed_official 324:406fd2029f23 1421 /*!
mbed_official 324:406fd2029f23 1422 * @}
mbed_official 324:406fd2029f23 1423 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 1424
mbed_official 324:406fd2029f23 1425
mbed_official 324:406fd2029f23 1426 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 1427 -- DMA Register Masks
mbed_official 324:406fd2029f23 1428 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 1429
mbed_official 324:406fd2029f23 1430 /*!
mbed_official 324:406fd2029f23 1431 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 324:406fd2029f23 1432 * @{
mbed_official 324:406fd2029f23 1433 */
mbed_official 324:406fd2029f23 1434
mbed_official 324:406fd2029f23 1435 /* CR Bit Fields */
mbed_official 324:406fd2029f23 1436 #define DMA_CR_EDBG_MASK 0x2u
mbed_official 324:406fd2029f23 1437 #define DMA_CR_EDBG_SHIFT 1
mbed_official 324:406fd2029f23 1438 #define DMA_CR_ERCA_MASK 0x4u
mbed_official 324:406fd2029f23 1439 #define DMA_CR_ERCA_SHIFT 2
mbed_official 324:406fd2029f23 1440 #define DMA_CR_HOE_MASK 0x10u
mbed_official 324:406fd2029f23 1441 #define DMA_CR_HOE_SHIFT 4
mbed_official 324:406fd2029f23 1442 #define DMA_CR_HALT_MASK 0x20u
mbed_official 324:406fd2029f23 1443 #define DMA_CR_HALT_SHIFT 5
mbed_official 324:406fd2029f23 1444 #define DMA_CR_CLM_MASK 0x40u
mbed_official 324:406fd2029f23 1445 #define DMA_CR_CLM_SHIFT 6
mbed_official 324:406fd2029f23 1446 #define DMA_CR_EMLM_MASK 0x80u
mbed_official 324:406fd2029f23 1447 #define DMA_CR_EMLM_SHIFT 7
mbed_official 324:406fd2029f23 1448 #define DMA_CR_ECX_MASK 0x10000u
mbed_official 324:406fd2029f23 1449 #define DMA_CR_ECX_SHIFT 16
mbed_official 324:406fd2029f23 1450 #define DMA_CR_CX_MASK 0x20000u
mbed_official 324:406fd2029f23 1451 #define DMA_CR_CX_SHIFT 17
mbed_official 324:406fd2029f23 1452 /* ES Bit Fields */
mbed_official 324:406fd2029f23 1453 #define DMA_ES_DBE_MASK 0x1u
mbed_official 324:406fd2029f23 1454 #define DMA_ES_DBE_SHIFT 0
mbed_official 324:406fd2029f23 1455 #define DMA_ES_SBE_MASK 0x2u
mbed_official 324:406fd2029f23 1456 #define DMA_ES_SBE_SHIFT 1
mbed_official 324:406fd2029f23 1457 #define DMA_ES_SGE_MASK 0x4u
mbed_official 324:406fd2029f23 1458 #define DMA_ES_SGE_SHIFT 2
mbed_official 324:406fd2029f23 1459 #define DMA_ES_NCE_MASK 0x8u
mbed_official 324:406fd2029f23 1460 #define DMA_ES_NCE_SHIFT 3
mbed_official 324:406fd2029f23 1461 #define DMA_ES_DOE_MASK 0x10u
mbed_official 324:406fd2029f23 1462 #define DMA_ES_DOE_SHIFT 4
mbed_official 324:406fd2029f23 1463 #define DMA_ES_DAE_MASK 0x20u
mbed_official 324:406fd2029f23 1464 #define DMA_ES_DAE_SHIFT 5
mbed_official 324:406fd2029f23 1465 #define DMA_ES_SOE_MASK 0x40u
mbed_official 324:406fd2029f23 1466 #define DMA_ES_SOE_SHIFT 6
mbed_official 324:406fd2029f23 1467 #define DMA_ES_SAE_MASK 0x80u
mbed_official 324:406fd2029f23 1468 #define DMA_ES_SAE_SHIFT 7
mbed_official 324:406fd2029f23 1469 #define DMA_ES_ERRCHN_MASK 0xF00u
mbed_official 324:406fd2029f23 1470 #define DMA_ES_ERRCHN_SHIFT 8
mbed_official 324:406fd2029f23 1471 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
mbed_official 324:406fd2029f23 1472 #define DMA_ES_CPE_MASK 0x4000u
mbed_official 324:406fd2029f23 1473 #define DMA_ES_CPE_SHIFT 14
mbed_official 324:406fd2029f23 1474 #define DMA_ES_ECX_MASK 0x10000u
mbed_official 324:406fd2029f23 1475 #define DMA_ES_ECX_SHIFT 16
mbed_official 324:406fd2029f23 1476 #define DMA_ES_VLD_MASK 0x80000000u
mbed_official 324:406fd2029f23 1477 #define DMA_ES_VLD_SHIFT 31
mbed_official 324:406fd2029f23 1478 /* ERQ Bit Fields */
mbed_official 324:406fd2029f23 1479 #define DMA_ERQ_ERQ0_MASK 0x1u
mbed_official 324:406fd2029f23 1480 #define DMA_ERQ_ERQ0_SHIFT 0
mbed_official 324:406fd2029f23 1481 #define DMA_ERQ_ERQ1_MASK 0x2u
mbed_official 324:406fd2029f23 1482 #define DMA_ERQ_ERQ1_SHIFT 1
mbed_official 324:406fd2029f23 1483 #define DMA_ERQ_ERQ2_MASK 0x4u
mbed_official 324:406fd2029f23 1484 #define DMA_ERQ_ERQ2_SHIFT 2
mbed_official 324:406fd2029f23 1485 #define DMA_ERQ_ERQ3_MASK 0x8u
mbed_official 324:406fd2029f23 1486 #define DMA_ERQ_ERQ3_SHIFT 3
mbed_official 324:406fd2029f23 1487 #define DMA_ERQ_ERQ4_MASK 0x10u
mbed_official 324:406fd2029f23 1488 #define DMA_ERQ_ERQ4_SHIFT 4
mbed_official 324:406fd2029f23 1489 #define DMA_ERQ_ERQ5_MASK 0x20u
mbed_official 324:406fd2029f23 1490 #define DMA_ERQ_ERQ5_SHIFT 5
mbed_official 324:406fd2029f23 1491 #define DMA_ERQ_ERQ6_MASK 0x40u
mbed_official 324:406fd2029f23 1492 #define DMA_ERQ_ERQ6_SHIFT 6
mbed_official 324:406fd2029f23 1493 #define DMA_ERQ_ERQ7_MASK 0x80u
mbed_official 324:406fd2029f23 1494 #define DMA_ERQ_ERQ7_SHIFT 7
mbed_official 324:406fd2029f23 1495 #define DMA_ERQ_ERQ8_MASK 0x100u
mbed_official 324:406fd2029f23 1496 #define DMA_ERQ_ERQ8_SHIFT 8
mbed_official 324:406fd2029f23 1497 #define DMA_ERQ_ERQ9_MASK 0x200u
mbed_official 324:406fd2029f23 1498 #define DMA_ERQ_ERQ9_SHIFT 9
mbed_official 324:406fd2029f23 1499 #define DMA_ERQ_ERQ10_MASK 0x400u
mbed_official 324:406fd2029f23 1500 #define DMA_ERQ_ERQ10_SHIFT 10
mbed_official 324:406fd2029f23 1501 #define DMA_ERQ_ERQ11_MASK 0x800u
mbed_official 324:406fd2029f23 1502 #define DMA_ERQ_ERQ11_SHIFT 11
mbed_official 324:406fd2029f23 1503 #define DMA_ERQ_ERQ12_MASK 0x1000u
mbed_official 324:406fd2029f23 1504 #define DMA_ERQ_ERQ12_SHIFT 12
mbed_official 324:406fd2029f23 1505 #define DMA_ERQ_ERQ13_MASK 0x2000u
mbed_official 324:406fd2029f23 1506 #define DMA_ERQ_ERQ13_SHIFT 13
mbed_official 324:406fd2029f23 1507 #define DMA_ERQ_ERQ14_MASK 0x4000u
mbed_official 324:406fd2029f23 1508 #define DMA_ERQ_ERQ14_SHIFT 14
mbed_official 324:406fd2029f23 1509 #define DMA_ERQ_ERQ15_MASK 0x8000u
mbed_official 324:406fd2029f23 1510 #define DMA_ERQ_ERQ15_SHIFT 15
mbed_official 324:406fd2029f23 1511 /* EEI Bit Fields */
mbed_official 324:406fd2029f23 1512 #define DMA_EEI_EEI0_MASK 0x1u
mbed_official 324:406fd2029f23 1513 #define DMA_EEI_EEI0_SHIFT 0
mbed_official 324:406fd2029f23 1514 #define DMA_EEI_EEI1_MASK 0x2u
mbed_official 324:406fd2029f23 1515 #define DMA_EEI_EEI1_SHIFT 1
mbed_official 324:406fd2029f23 1516 #define DMA_EEI_EEI2_MASK 0x4u
mbed_official 324:406fd2029f23 1517 #define DMA_EEI_EEI2_SHIFT 2
mbed_official 324:406fd2029f23 1518 #define DMA_EEI_EEI3_MASK 0x8u
mbed_official 324:406fd2029f23 1519 #define DMA_EEI_EEI3_SHIFT 3
mbed_official 324:406fd2029f23 1520 #define DMA_EEI_EEI4_MASK 0x10u
mbed_official 324:406fd2029f23 1521 #define DMA_EEI_EEI4_SHIFT 4
mbed_official 324:406fd2029f23 1522 #define DMA_EEI_EEI5_MASK 0x20u
mbed_official 324:406fd2029f23 1523 #define DMA_EEI_EEI5_SHIFT 5
mbed_official 324:406fd2029f23 1524 #define DMA_EEI_EEI6_MASK 0x40u
mbed_official 324:406fd2029f23 1525 #define DMA_EEI_EEI6_SHIFT 6
mbed_official 324:406fd2029f23 1526 #define DMA_EEI_EEI7_MASK 0x80u
mbed_official 324:406fd2029f23 1527 #define DMA_EEI_EEI7_SHIFT 7
mbed_official 324:406fd2029f23 1528 #define DMA_EEI_EEI8_MASK 0x100u
mbed_official 324:406fd2029f23 1529 #define DMA_EEI_EEI8_SHIFT 8
mbed_official 324:406fd2029f23 1530 #define DMA_EEI_EEI9_MASK 0x200u
mbed_official 324:406fd2029f23 1531 #define DMA_EEI_EEI9_SHIFT 9
mbed_official 324:406fd2029f23 1532 #define DMA_EEI_EEI10_MASK 0x400u
mbed_official 324:406fd2029f23 1533 #define DMA_EEI_EEI10_SHIFT 10
mbed_official 324:406fd2029f23 1534 #define DMA_EEI_EEI11_MASK 0x800u
mbed_official 324:406fd2029f23 1535 #define DMA_EEI_EEI11_SHIFT 11
mbed_official 324:406fd2029f23 1536 #define DMA_EEI_EEI12_MASK 0x1000u
mbed_official 324:406fd2029f23 1537 #define DMA_EEI_EEI12_SHIFT 12
mbed_official 324:406fd2029f23 1538 #define DMA_EEI_EEI13_MASK 0x2000u
mbed_official 324:406fd2029f23 1539 #define DMA_EEI_EEI13_SHIFT 13
mbed_official 324:406fd2029f23 1540 #define DMA_EEI_EEI14_MASK 0x4000u
mbed_official 324:406fd2029f23 1541 #define DMA_EEI_EEI14_SHIFT 14
mbed_official 324:406fd2029f23 1542 #define DMA_EEI_EEI15_MASK 0x8000u
mbed_official 324:406fd2029f23 1543 #define DMA_EEI_EEI15_SHIFT 15
mbed_official 324:406fd2029f23 1544 /* CEEI Bit Fields */
mbed_official 324:406fd2029f23 1545 #define DMA_CEEI_CEEI_MASK 0xFu
mbed_official 324:406fd2029f23 1546 #define DMA_CEEI_CEEI_SHIFT 0
mbed_official 324:406fd2029f23 1547 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
mbed_official 324:406fd2029f23 1548 #define DMA_CEEI_CAEE_MASK 0x40u
mbed_official 324:406fd2029f23 1549 #define DMA_CEEI_CAEE_SHIFT 6
mbed_official 324:406fd2029f23 1550 #define DMA_CEEI_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1551 #define DMA_CEEI_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1552 /* SEEI Bit Fields */
mbed_official 324:406fd2029f23 1553 #define DMA_SEEI_SEEI_MASK 0xFu
mbed_official 324:406fd2029f23 1554 #define DMA_SEEI_SEEI_SHIFT 0
mbed_official 324:406fd2029f23 1555 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
mbed_official 324:406fd2029f23 1556 #define DMA_SEEI_SAEE_MASK 0x40u
mbed_official 324:406fd2029f23 1557 #define DMA_SEEI_SAEE_SHIFT 6
mbed_official 324:406fd2029f23 1558 #define DMA_SEEI_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1559 #define DMA_SEEI_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1560 /* CERQ Bit Fields */
mbed_official 324:406fd2029f23 1561 #define DMA_CERQ_CERQ_MASK 0xFu
mbed_official 324:406fd2029f23 1562 #define DMA_CERQ_CERQ_SHIFT 0
mbed_official 324:406fd2029f23 1563 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
mbed_official 324:406fd2029f23 1564 #define DMA_CERQ_CAER_MASK 0x40u
mbed_official 324:406fd2029f23 1565 #define DMA_CERQ_CAER_SHIFT 6
mbed_official 324:406fd2029f23 1566 #define DMA_CERQ_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1567 #define DMA_CERQ_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1568 /* SERQ Bit Fields */
mbed_official 324:406fd2029f23 1569 #define DMA_SERQ_SERQ_MASK 0xFu
mbed_official 324:406fd2029f23 1570 #define DMA_SERQ_SERQ_SHIFT 0
mbed_official 324:406fd2029f23 1571 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
mbed_official 324:406fd2029f23 1572 #define DMA_SERQ_SAER_MASK 0x40u
mbed_official 324:406fd2029f23 1573 #define DMA_SERQ_SAER_SHIFT 6
mbed_official 324:406fd2029f23 1574 #define DMA_SERQ_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1575 #define DMA_SERQ_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1576 /* CDNE Bit Fields */
mbed_official 324:406fd2029f23 1577 #define DMA_CDNE_CDNE_MASK 0xFu
mbed_official 324:406fd2029f23 1578 #define DMA_CDNE_CDNE_SHIFT 0
mbed_official 324:406fd2029f23 1579 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
mbed_official 324:406fd2029f23 1580 #define DMA_CDNE_CADN_MASK 0x40u
mbed_official 324:406fd2029f23 1581 #define DMA_CDNE_CADN_SHIFT 6
mbed_official 324:406fd2029f23 1582 #define DMA_CDNE_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1583 #define DMA_CDNE_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1584 /* SSRT Bit Fields */
mbed_official 324:406fd2029f23 1585 #define DMA_SSRT_SSRT_MASK 0xFu
mbed_official 324:406fd2029f23 1586 #define DMA_SSRT_SSRT_SHIFT 0
mbed_official 324:406fd2029f23 1587 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
mbed_official 324:406fd2029f23 1588 #define DMA_SSRT_SAST_MASK 0x40u
mbed_official 324:406fd2029f23 1589 #define DMA_SSRT_SAST_SHIFT 6
mbed_official 324:406fd2029f23 1590 #define DMA_SSRT_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1591 #define DMA_SSRT_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1592 /* CERR Bit Fields */
mbed_official 324:406fd2029f23 1593 #define DMA_CERR_CERR_MASK 0xFu
mbed_official 324:406fd2029f23 1594 #define DMA_CERR_CERR_SHIFT 0
mbed_official 324:406fd2029f23 1595 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
mbed_official 324:406fd2029f23 1596 #define DMA_CERR_CAEI_MASK 0x40u
mbed_official 324:406fd2029f23 1597 #define DMA_CERR_CAEI_SHIFT 6
mbed_official 324:406fd2029f23 1598 #define DMA_CERR_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1599 #define DMA_CERR_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1600 /* CINT Bit Fields */
mbed_official 324:406fd2029f23 1601 #define DMA_CINT_CINT_MASK 0xFu
mbed_official 324:406fd2029f23 1602 #define DMA_CINT_CINT_SHIFT 0
mbed_official 324:406fd2029f23 1603 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
mbed_official 324:406fd2029f23 1604 #define DMA_CINT_CAIR_MASK 0x40u
mbed_official 324:406fd2029f23 1605 #define DMA_CINT_CAIR_SHIFT 6
mbed_official 324:406fd2029f23 1606 #define DMA_CINT_NOP_MASK 0x80u
mbed_official 324:406fd2029f23 1607 #define DMA_CINT_NOP_SHIFT 7
mbed_official 324:406fd2029f23 1608 /* INT Bit Fields */
mbed_official 324:406fd2029f23 1609 #define DMA_INT_INT0_MASK 0x1u
mbed_official 324:406fd2029f23 1610 #define DMA_INT_INT0_SHIFT 0
mbed_official 324:406fd2029f23 1611 #define DMA_INT_INT1_MASK 0x2u
mbed_official 324:406fd2029f23 1612 #define DMA_INT_INT1_SHIFT 1
mbed_official 324:406fd2029f23 1613 #define DMA_INT_INT2_MASK 0x4u
mbed_official 324:406fd2029f23 1614 #define DMA_INT_INT2_SHIFT 2
mbed_official 324:406fd2029f23 1615 #define DMA_INT_INT3_MASK 0x8u
mbed_official 324:406fd2029f23 1616 #define DMA_INT_INT3_SHIFT 3
mbed_official 324:406fd2029f23 1617 #define DMA_INT_INT4_MASK 0x10u
mbed_official 324:406fd2029f23 1618 #define DMA_INT_INT4_SHIFT 4
mbed_official 324:406fd2029f23 1619 #define DMA_INT_INT5_MASK 0x20u
mbed_official 324:406fd2029f23 1620 #define DMA_INT_INT5_SHIFT 5
mbed_official 324:406fd2029f23 1621 #define DMA_INT_INT6_MASK 0x40u
mbed_official 324:406fd2029f23 1622 #define DMA_INT_INT6_SHIFT 6
mbed_official 324:406fd2029f23 1623 #define DMA_INT_INT7_MASK 0x80u
mbed_official 324:406fd2029f23 1624 #define DMA_INT_INT7_SHIFT 7
mbed_official 324:406fd2029f23 1625 #define DMA_INT_INT8_MASK 0x100u
mbed_official 324:406fd2029f23 1626 #define DMA_INT_INT8_SHIFT 8
mbed_official 324:406fd2029f23 1627 #define DMA_INT_INT9_MASK 0x200u
mbed_official 324:406fd2029f23 1628 #define DMA_INT_INT9_SHIFT 9
mbed_official 324:406fd2029f23 1629 #define DMA_INT_INT10_MASK 0x400u
mbed_official 324:406fd2029f23 1630 #define DMA_INT_INT10_SHIFT 10
mbed_official 324:406fd2029f23 1631 #define DMA_INT_INT11_MASK 0x800u
mbed_official 324:406fd2029f23 1632 #define DMA_INT_INT11_SHIFT 11
mbed_official 324:406fd2029f23 1633 #define DMA_INT_INT12_MASK 0x1000u
mbed_official 324:406fd2029f23 1634 #define DMA_INT_INT12_SHIFT 12
mbed_official 324:406fd2029f23 1635 #define DMA_INT_INT13_MASK 0x2000u
mbed_official 324:406fd2029f23 1636 #define DMA_INT_INT13_SHIFT 13
mbed_official 324:406fd2029f23 1637 #define DMA_INT_INT14_MASK 0x4000u
mbed_official 324:406fd2029f23 1638 #define DMA_INT_INT14_SHIFT 14
mbed_official 324:406fd2029f23 1639 #define DMA_INT_INT15_MASK 0x8000u
mbed_official 324:406fd2029f23 1640 #define DMA_INT_INT15_SHIFT 15
mbed_official 324:406fd2029f23 1641 /* ERR Bit Fields */
mbed_official 324:406fd2029f23 1642 #define DMA_ERR_ERR0_MASK 0x1u
mbed_official 324:406fd2029f23 1643 #define DMA_ERR_ERR0_SHIFT 0
mbed_official 324:406fd2029f23 1644 #define DMA_ERR_ERR1_MASK 0x2u
mbed_official 324:406fd2029f23 1645 #define DMA_ERR_ERR1_SHIFT 1
mbed_official 324:406fd2029f23 1646 #define DMA_ERR_ERR2_MASK 0x4u
mbed_official 324:406fd2029f23 1647 #define DMA_ERR_ERR2_SHIFT 2
mbed_official 324:406fd2029f23 1648 #define DMA_ERR_ERR3_MASK 0x8u
mbed_official 324:406fd2029f23 1649 #define DMA_ERR_ERR3_SHIFT 3
mbed_official 324:406fd2029f23 1650 #define DMA_ERR_ERR4_MASK 0x10u
mbed_official 324:406fd2029f23 1651 #define DMA_ERR_ERR4_SHIFT 4
mbed_official 324:406fd2029f23 1652 #define DMA_ERR_ERR5_MASK 0x20u
mbed_official 324:406fd2029f23 1653 #define DMA_ERR_ERR5_SHIFT 5
mbed_official 324:406fd2029f23 1654 #define DMA_ERR_ERR6_MASK 0x40u
mbed_official 324:406fd2029f23 1655 #define DMA_ERR_ERR6_SHIFT 6
mbed_official 324:406fd2029f23 1656 #define DMA_ERR_ERR7_MASK 0x80u
mbed_official 324:406fd2029f23 1657 #define DMA_ERR_ERR7_SHIFT 7
mbed_official 324:406fd2029f23 1658 #define DMA_ERR_ERR8_MASK 0x100u
mbed_official 324:406fd2029f23 1659 #define DMA_ERR_ERR8_SHIFT 8
mbed_official 324:406fd2029f23 1660 #define DMA_ERR_ERR9_MASK 0x200u
mbed_official 324:406fd2029f23 1661 #define DMA_ERR_ERR9_SHIFT 9
mbed_official 324:406fd2029f23 1662 #define DMA_ERR_ERR10_MASK 0x400u
mbed_official 324:406fd2029f23 1663 #define DMA_ERR_ERR10_SHIFT 10
mbed_official 324:406fd2029f23 1664 #define DMA_ERR_ERR11_MASK 0x800u
mbed_official 324:406fd2029f23 1665 #define DMA_ERR_ERR11_SHIFT 11
mbed_official 324:406fd2029f23 1666 #define DMA_ERR_ERR12_MASK 0x1000u
mbed_official 324:406fd2029f23 1667 #define DMA_ERR_ERR12_SHIFT 12
mbed_official 324:406fd2029f23 1668 #define DMA_ERR_ERR13_MASK 0x2000u
mbed_official 324:406fd2029f23 1669 #define DMA_ERR_ERR13_SHIFT 13
mbed_official 324:406fd2029f23 1670 #define DMA_ERR_ERR14_MASK 0x4000u
mbed_official 324:406fd2029f23 1671 #define DMA_ERR_ERR14_SHIFT 14
mbed_official 324:406fd2029f23 1672 #define DMA_ERR_ERR15_MASK 0x8000u
mbed_official 324:406fd2029f23 1673 #define DMA_ERR_ERR15_SHIFT 15
mbed_official 324:406fd2029f23 1674 /* HRS Bit Fields */
mbed_official 324:406fd2029f23 1675 #define DMA_HRS_HRS0_MASK 0x1u
mbed_official 324:406fd2029f23 1676 #define DMA_HRS_HRS0_SHIFT 0
mbed_official 324:406fd2029f23 1677 #define DMA_HRS_HRS1_MASK 0x2u
mbed_official 324:406fd2029f23 1678 #define DMA_HRS_HRS1_SHIFT 1
mbed_official 324:406fd2029f23 1679 #define DMA_HRS_HRS2_MASK 0x4u
mbed_official 324:406fd2029f23 1680 #define DMA_HRS_HRS2_SHIFT 2
mbed_official 324:406fd2029f23 1681 #define DMA_HRS_HRS3_MASK 0x8u
mbed_official 324:406fd2029f23 1682 #define DMA_HRS_HRS3_SHIFT 3
mbed_official 324:406fd2029f23 1683 #define DMA_HRS_HRS4_MASK 0x10u
mbed_official 324:406fd2029f23 1684 #define DMA_HRS_HRS4_SHIFT 4
mbed_official 324:406fd2029f23 1685 #define DMA_HRS_HRS5_MASK 0x20u
mbed_official 324:406fd2029f23 1686 #define DMA_HRS_HRS5_SHIFT 5
mbed_official 324:406fd2029f23 1687 #define DMA_HRS_HRS6_MASK 0x40u
mbed_official 324:406fd2029f23 1688 #define DMA_HRS_HRS6_SHIFT 6
mbed_official 324:406fd2029f23 1689 #define DMA_HRS_HRS7_MASK 0x80u
mbed_official 324:406fd2029f23 1690 #define DMA_HRS_HRS7_SHIFT 7
mbed_official 324:406fd2029f23 1691 #define DMA_HRS_HRS8_MASK 0x100u
mbed_official 324:406fd2029f23 1692 #define DMA_HRS_HRS8_SHIFT 8
mbed_official 324:406fd2029f23 1693 #define DMA_HRS_HRS9_MASK 0x200u
mbed_official 324:406fd2029f23 1694 #define DMA_HRS_HRS9_SHIFT 9
mbed_official 324:406fd2029f23 1695 #define DMA_HRS_HRS10_MASK 0x400u
mbed_official 324:406fd2029f23 1696 #define DMA_HRS_HRS10_SHIFT 10
mbed_official 324:406fd2029f23 1697 #define DMA_HRS_HRS11_MASK 0x800u
mbed_official 324:406fd2029f23 1698 #define DMA_HRS_HRS11_SHIFT 11
mbed_official 324:406fd2029f23 1699 #define DMA_HRS_HRS12_MASK 0x1000u
mbed_official 324:406fd2029f23 1700 #define DMA_HRS_HRS12_SHIFT 12
mbed_official 324:406fd2029f23 1701 #define DMA_HRS_HRS13_MASK 0x2000u
mbed_official 324:406fd2029f23 1702 #define DMA_HRS_HRS13_SHIFT 13
mbed_official 324:406fd2029f23 1703 #define DMA_HRS_HRS14_MASK 0x4000u
mbed_official 324:406fd2029f23 1704 #define DMA_HRS_HRS14_SHIFT 14
mbed_official 324:406fd2029f23 1705 #define DMA_HRS_HRS15_MASK 0x8000u
mbed_official 324:406fd2029f23 1706 #define DMA_HRS_HRS15_SHIFT 15
mbed_official 324:406fd2029f23 1707 /* EARS Bit Fields */
mbed_official 324:406fd2029f23 1708 #define DMA_EARS_EDREQ_0_MASK 0x1u
mbed_official 324:406fd2029f23 1709 #define DMA_EARS_EDREQ_0_SHIFT 0
mbed_official 324:406fd2029f23 1710 #define DMA_EARS_EDREQ_1_MASK 0x2u
mbed_official 324:406fd2029f23 1711 #define DMA_EARS_EDREQ_1_SHIFT 1
mbed_official 324:406fd2029f23 1712 #define DMA_EARS_EDREQ_2_MASK 0x4u
mbed_official 324:406fd2029f23 1713 #define DMA_EARS_EDREQ_2_SHIFT 2
mbed_official 324:406fd2029f23 1714 #define DMA_EARS_EDREQ_3_MASK 0x8u
mbed_official 324:406fd2029f23 1715 #define DMA_EARS_EDREQ_3_SHIFT 3
mbed_official 324:406fd2029f23 1716 #define DMA_EARS_EDREQ_4_MASK 0x10u
mbed_official 324:406fd2029f23 1717 #define DMA_EARS_EDREQ_4_SHIFT 4
mbed_official 324:406fd2029f23 1718 #define DMA_EARS_EDREQ_5_MASK 0x20u
mbed_official 324:406fd2029f23 1719 #define DMA_EARS_EDREQ_5_SHIFT 5
mbed_official 324:406fd2029f23 1720 #define DMA_EARS_EDREQ_6_MASK 0x40u
mbed_official 324:406fd2029f23 1721 #define DMA_EARS_EDREQ_6_SHIFT 6
mbed_official 324:406fd2029f23 1722 #define DMA_EARS_EDREQ_7_MASK 0x80u
mbed_official 324:406fd2029f23 1723 #define DMA_EARS_EDREQ_7_SHIFT 7
mbed_official 324:406fd2029f23 1724 #define DMA_EARS_EDREQ_8_MASK 0x100u
mbed_official 324:406fd2029f23 1725 #define DMA_EARS_EDREQ_8_SHIFT 8
mbed_official 324:406fd2029f23 1726 #define DMA_EARS_EDREQ_9_MASK 0x200u
mbed_official 324:406fd2029f23 1727 #define DMA_EARS_EDREQ_9_SHIFT 9
mbed_official 324:406fd2029f23 1728 #define DMA_EARS_EDREQ_10_MASK 0x400u
mbed_official 324:406fd2029f23 1729 #define DMA_EARS_EDREQ_10_SHIFT 10
mbed_official 324:406fd2029f23 1730 #define DMA_EARS_EDREQ_11_MASK 0x800u
mbed_official 324:406fd2029f23 1731 #define DMA_EARS_EDREQ_11_SHIFT 11
mbed_official 324:406fd2029f23 1732 #define DMA_EARS_EDREQ_12_MASK 0x1000u
mbed_official 324:406fd2029f23 1733 #define DMA_EARS_EDREQ_12_SHIFT 12
mbed_official 324:406fd2029f23 1734 #define DMA_EARS_EDREQ_13_MASK 0x2000u
mbed_official 324:406fd2029f23 1735 #define DMA_EARS_EDREQ_13_SHIFT 13
mbed_official 324:406fd2029f23 1736 #define DMA_EARS_EDREQ_14_MASK 0x4000u
mbed_official 324:406fd2029f23 1737 #define DMA_EARS_EDREQ_14_SHIFT 14
mbed_official 324:406fd2029f23 1738 #define DMA_EARS_EDREQ_15_MASK 0x8000u
mbed_official 324:406fd2029f23 1739 #define DMA_EARS_EDREQ_15_SHIFT 15
mbed_official 324:406fd2029f23 1740 /* DCHPRI3 Bit Fields */
mbed_official 324:406fd2029f23 1741 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1742 #define DMA_DCHPRI3_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1743 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
mbed_official 324:406fd2029f23 1744 #define DMA_DCHPRI3_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1745 #define DMA_DCHPRI3_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1746 #define DMA_DCHPRI3_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1747 #define DMA_DCHPRI3_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1748 /* DCHPRI2 Bit Fields */
mbed_official 324:406fd2029f23 1749 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1750 #define DMA_DCHPRI2_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1751 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
mbed_official 324:406fd2029f23 1752 #define DMA_DCHPRI2_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1753 #define DMA_DCHPRI2_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1754 #define DMA_DCHPRI2_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1755 #define DMA_DCHPRI2_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1756 /* DCHPRI1 Bit Fields */
mbed_official 324:406fd2029f23 1757 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1758 #define DMA_DCHPRI1_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1759 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
mbed_official 324:406fd2029f23 1760 #define DMA_DCHPRI1_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1761 #define DMA_DCHPRI1_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1762 #define DMA_DCHPRI1_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1763 #define DMA_DCHPRI1_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1764 /* DCHPRI0 Bit Fields */
mbed_official 324:406fd2029f23 1765 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1766 #define DMA_DCHPRI0_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1767 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
mbed_official 324:406fd2029f23 1768 #define DMA_DCHPRI0_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1769 #define DMA_DCHPRI0_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1770 #define DMA_DCHPRI0_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1771 #define DMA_DCHPRI0_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1772 /* DCHPRI7 Bit Fields */
mbed_official 324:406fd2029f23 1773 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1774 #define DMA_DCHPRI7_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1775 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
mbed_official 324:406fd2029f23 1776 #define DMA_DCHPRI7_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1777 #define DMA_DCHPRI7_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1778 #define DMA_DCHPRI7_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1779 #define DMA_DCHPRI7_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1780 /* DCHPRI6 Bit Fields */
mbed_official 324:406fd2029f23 1781 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1782 #define DMA_DCHPRI6_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1783 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
mbed_official 324:406fd2029f23 1784 #define DMA_DCHPRI6_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1785 #define DMA_DCHPRI6_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1786 #define DMA_DCHPRI6_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1787 #define DMA_DCHPRI6_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1788 /* DCHPRI5 Bit Fields */
mbed_official 324:406fd2029f23 1789 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1790 #define DMA_DCHPRI5_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1791 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
mbed_official 324:406fd2029f23 1792 #define DMA_DCHPRI5_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1793 #define DMA_DCHPRI5_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1794 #define DMA_DCHPRI5_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1795 #define DMA_DCHPRI5_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1796 /* DCHPRI4 Bit Fields */
mbed_official 324:406fd2029f23 1797 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1798 #define DMA_DCHPRI4_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1799 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
mbed_official 324:406fd2029f23 1800 #define DMA_DCHPRI4_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1801 #define DMA_DCHPRI4_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1802 #define DMA_DCHPRI4_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1803 #define DMA_DCHPRI4_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1804 /* DCHPRI11 Bit Fields */
mbed_official 324:406fd2029f23 1805 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1806 #define DMA_DCHPRI11_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1807 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
mbed_official 324:406fd2029f23 1808 #define DMA_DCHPRI11_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1809 #define DMA_DCHPRI11_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1810 #define DMA_DCHPRI11_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1811 #define DMA_DCHPRI11_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1812 /* DCHPRI10 Bit Fields */
mbed_official 324:406fd2029f23 1813 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1814 #define DMA_DCHPRI10_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1815 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
mbed_official 324:406fd2029f23 1816 #define DMA_DCHPRI10_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1817 #define DMA_DCHPRI10_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1818 #define DMA_DCHPRI10_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1819 #define DMA_DCHPRI10_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1820 /* DCHPRI9 Bit Fields */
mbed_official 324:406fd2029f23 1821 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1822 #define DMA_DCHPRI9_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1823 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
mbed_official 324:406fd2029f23 1824 #define DMA_DCHPRI9_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1825 #define DMA_DCHPRI9_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1826 #define DMA_DCHPRI9_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1827 #define DMA_DCHPRI9_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1828 /* DCHPRI8 Bit Fields */
mbed_official 324:406fd2029f23 1829 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1830 #define DMA_DCHPRI8_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1831 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
mbed_official 324:406fd2029f23 1832 #define DMA_DCHPRI8_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1833 #define DMA_DCHPRI8_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1834 #define DMA_DCHPRI8_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1835 #define DMA_DCHPRI8_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1836 /* DCHPRI15 Bit Fields */
mbed_official 324:406fd2029f23 1837 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1838 #define DMA_DCHPRI15_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1839 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
mbed_official 324:406fd2029f23 1840 #define DMA_DCHPRI15_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1841 #define DMA_DCHPRI15_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1842 #define DMA_DCHPRI15_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1843 #define DMA_DCHPRI15_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1844 /* DCHPRI14 Bit Fields */
mbed_official 324:406fd2029f23 1845 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1846 #define DMA_DCHPRI14_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1847 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
mbed_official 324:406fd2029f23 1848 #define DMA_DCHPRI14_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1849 #define DMA_DCHPRI14_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1850 #define DMA_DCHPRI14_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1851 #define DMA_DCHPRI14_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1852 /* DCHPRI13 Bit Fields */
mbed_official 324:406fd2029f23 1853 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1854 #define DMA_DCHPRI13_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1855 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
mbed_official 324:406fd2029f23 1856 #define DMA_DCHPRI13_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1857 #define DMA_DCHPRI13_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1858 #define DMA_DCHPRI13_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1859 #define DMA_DCHPRI13_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1860 /* DCHPRI12 Bit Fields */
mbed_official 324:406fd2029f23 1861 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
mbed_official 324:406fd2029f23 1862 #define DMA_DCHPRI12_CHPRI_SHIFT 0
mbed_official 324:406fd2029f23 1863 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
mbed_official 324:406fd2029f23 1864 #define DMA_DCHPRI12_DPA_MASK 0x40u
mbed_official 324:406fd2029f23 1865 #define DMA_DCHPRI12_DPA_SHIFT 6
mbed_official 324:406fd2029f23 1866 #define DMA_DCHPRI12_ECP_MASK 0x80u
mbed_official 324:406fd2029f23 1867 #define DMA_DCHPRI12_ECP_SHIFT 7
mbed_official 324:406fd2029f23 1868 /* SADDR Bit Fields */
mbed_official 324:406fd2029f23 1869 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 1870 #define DMA_SADDR_SADDR_SHIFT 0
mbed_official 324:406fd2029f23 1871 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
mbed_official 324:406fd2029f23 1872 /* SOFF Bit Fields */
mbed_official 324:406fd2029f23 1873 #define DMA_SOFF_SOFF_MASK 0xFFFFu
mbed_official 324:406fd2029f23 1874 #define DMA_SOFF_SOFF_SHIFT 0
mbed_official 324:406fd2029f23 1875 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
mbed_official 324:406fd2029f23 1876 /* ATTR Bit Fields */
mbed_official 324:406fd2029f23 1877 #define DMA_ATTR_DSIZE_MASK 0x7u
mbed_official 324:406fd2029f23 1878 #define DMA_ATTR_DSIZE_SHIFT 0
mbed_official 324:406fd2029f23 1879 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
mbed_official 324:406fd2029f23 1880 #define DMA_ATTR_DMOD_MASK 0xF8u
mbed_official 324:406fd2029f23 1881 #define DMA_ATTR_DMOD_SHIFT 3
mbed_official 324:406fd2029f23 1882 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
mbed_official 324:406fd2029f23 1883 #define DMA_ATTR_SSIZE_MASK 0x700u
mbed_official 324:406fd2029f23 1884 #define DMA_ATTR_SSIZE_SHIFT 8
mbed_official 324:406fd2029f23 1885 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
mbed_official 324:406fd2029f23 1886 #define DMA_ATTR_SMOD_MASK 0xF800u
mbed_official 324:406fd2029f23 1887 #define DMA_ATTR_SMOD_SHIFT 11
mbed_official 324:406fd2029f23 1888 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
mbed_official 324:406fd2029f23 1889 /* NBYTES_MLNO Bit Fields */
mbed_official 324:406fd2029f23 1890 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 1891 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
mbed_official 324:406fd2029f23 1892 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
mbed_official 324:406fd2029f23 1893 /* NBYTES_MLOFFNO Bit Fields */
mbed_official 324:406fd2029f23 1894 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
mbed_official 324:406fd2029f23 1895 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
mbed_official 324:406fd2029f23 1896 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
mbed_official 324:406fd2029f23 1897 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
mbed_official 324:406fd2029f23 1898 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
mbed_official 324:406fd2029f23 1899 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
mbed_official 324:406fd2029f23 1900 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
mbed_official 324:406fd2029f23 1901 /* NBYTES_MLOFFYES Bit Fields */
mbed_official 324:406fd2029f23 1902 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
mbed_official 324:406fd2029f23 1903 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
mbed_official 324:406fd2029f23 1904 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
mbed_official 324:406fd2029f23 1905 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
mbed_official 324:406fd2029f23 1906 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
mbed_official 324:406fd2029f23 1907 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
mbed_official 324:406fd2029f23 1908 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
mbed_official 324:406fd2029f23 1909 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
mbed_official 324:406fd2029f23 1910 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
mbed_official 324:406fd2029f23 1911 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
mbed_official 324:406fd2029f23 1912 /* SLAST Bit Fields */
mbed_official 324:406fd2029f23 1913 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 1914 #define DMA_SLAST_SLAST_SHIFT 0
mbed_official 324:406fd2029f23 1915 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
mbed_official 324:406fd2029f23 1916 /* DADDR Bit Fields */
mbed_official 324:406fd2029f23 1917 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 1918 #define DMA_DADDR_DADDR_SHIFT 0
mbed_official 324:406fd2029f23 1919 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
mbed_official 324:406fd2029f23 1920 /* DOFF Bit Fields */
mbed_official 324:406fd2029f23 1921 #define DMA_DOFF_DOFF_MASK 0xFFFFu
mbed_official 324:406fd2029f23 1922 #define DMA_DOFF_DOFF_SHIFT 0
mbed_official 324:406fd2029f23 1923 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
mbed_official 324:406fd2029f23 1924 /* CITER_ELINKNO Bit Fields */
mbed_official 324:406fd2029f23 1925 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
mbed_official 324:406fd2029f23 1926 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
mbed_official 324:406fd2029f23 1927 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
mbed_official 324:406fd2029f23 1928 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 324:406fd2029f23 1929 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
mbed_official 324:406fd2029f23 1930 /* CITER_ELINKYES Bit Fields */
mbed_official 324:406fd2029f23 1931 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
mbed_official 324:406fd2029f23 1932 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
mbed_official 324:406fd2029f23 1933 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
mbed_official 324:406fd2029f23 1934 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 324:406fd2029f23 1935 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 324:406fd2029f23 1936 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
mbed_official 324:406fd2029f23 1937 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 324:406fd2029f23 1938 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
mbed_official 324:406fd2029f23 1939 /* DLAST_SGA Bit Fields */
mbed_official 324:406fd2029f23 1940 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 1941 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
mbed_official 324:406fd2029f23 1942 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
mbed_official 324:406fd2029f23 1943 /* CSR Bit Fields */
mbed_official 324:406fd2029f23 1944 #define DMA_CSR_START_MASK 0x1u
mbed_official 324:406fd2029f23 1945 #define DMA_CSR_START_SHIFT 0
mbed_official 324:406fd2029f23 1946 #define DMA_CSR_INTMAJOR_MASK 0x2u
mbed_official 324:406fd2029f23 1947 #define DMA_CSR_INTMAJOR_SHIFT 1
mbed_official 324:406fd2029f23 1948 #define DMA_CSR_INTHALF_MASK 0x4u
mbed_official 324:406fd2029f23 1949 #define DMA_CSR_INTHALF_SHIFT 2
mbed_official 324:406fd2029f23 1950 #define DMA_CSR_DREQ_MASK 0x8u
mbed_official 324:406fd2029f23 1951 #define DMA_CSR_DREQ_SHIFT 3
mbed_official 324:406fd2029f23 1952 #define DMA_CSR_ESG_MASK 0x10u
mbed_official 324:406fd2029f23 1953 #define DMA_CSR_ESG_SHIFT 4
mbed_official 324:406fd2029f23 1954 #define DMA_CSR_MAJORELINK_MASK 0x20u
mbed_official 324:406fd2029f23 1955 #define DMA_CSR_MAJORELINK_SHIFT 5
mbed_official 324:406fd2029f23 1956 #define DMA_CSR_ACTIVE_MASK 0x40u
mbed_official 324:406fd2029f23 1957 #define DMA_CSR_ACTIVE_SHIFT 6
mbed_official 324:406fd2029f23 1958 #define DMA_CSR_DONE_MASK 0x80u
mbed_official 324:406fd2029f23 1959 #define DMA_CSR_DONE_SHIFT 7
mbed_official 324:406fd2029f23 1960 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
mbed_official 324:406fd2029f23 1961 #define DMA_CSR_MAJORLINKCH_SHIFT 8
mbed_official 324:406fd2029f23 1962 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
mbed_official 324:406fd2029f23 1963 #define DMA_CSR_BWC_MASK 0xC000u
mbed_official 324:406fd2029f23 1964 #define DMA_CSR_BWC_SHIFT 14
mbed_official 324:406fd2029f23 1965 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
mbed_official 324:406fd2029f23 1966 /* BITER_ELINKNO Bit Fields */
mbed_official 324:406fd2029f23 1967 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
mbed_official 324:406fd2029f23 1968 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
mbed_official 324:406fd2029f23 1969 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
mbed_official 324:406fd2029f23 1970 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
mbed_official 324:406fd2029f23 1971 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
mbed_official 324:406fd2029f23 1972 /* BITER_ELINKYES Bit Fields */
mbed_official 324:406fd2029f23 1973 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
mbed_official 324:406fd2029f23 1974 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
mbed_official 324:406fd2029f23 1975 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
mbed_official 324:406fd2029f23 1976 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
mbed_official 324:406fd2029f23 1977 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
mbed_official 324:406fd2029f23 1978 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
mbed_official 324:406fd2029f23 1979 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
mbed_official 324:406fd2029f23 1980 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
mbed_official 324:406fd2029f23 1981
mbed_official 324:406fd2029f23 1982 /*!
mbed_official 324:406fd2029f23 1983 * @}
mbed_official 324:406fd2029f23 1984 */ /* end of group DMA_Register_Masks */
mbed_official 324:406fd2029f23 1985
mbed_official 324:406fd2029f23 1986
mbed_official 324:406fd2029f23 1987 /* DMA - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 1988 /** Peripheral DMA base address */
mbed_official 324:406fd2029f23 1989 #define DMA_BASE (0x40008000u)
mbed_official 324:406fd2029f23 1990 /** Peripheral DMA base pointer */
mbed_official 324:406fd2029f23 1991 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 324:406fd2029f23 1992 #define DMA_BASE_PTR (DMA0)
mbed_official 324:406fd2029f23 1993 /** Array initializer of DMA peripheral base addresses */
mbed_official 324:406fd2029f23 1994 #define DMA_BASE_ADDRS { DMA_BASE }
mbed_official 324:406fd2029f23 1995 /** Array initializer of DMA peripheral base pointers */
mbed_official 324:406fd2029f23 1996 #define DMA_BASE_PTRS { DMA0 }
mbed_official 324:406fd2029f23 1997 /** Interrupt vectors for the DMA peripheral type */
mbed_official 324:406fd2029f23 1998 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
mbed_official 324:406fd2029f23 1999 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
mbed_official 324:406fd2029f23 2000
mbed_official 324:406fd2029f23 2001 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2002 -- DMA - Register accessor macros
mbed_official 324:406fd2029f23 2003 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2004
mbed_official 324:406fd2029f23 2005 /*!
mbed_official 324:406fd2029f23 2006 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 324:406fd2029f23 2007 * @{
mbed_official 324:406fd2029f23 2008 */
mbed_official 324:406fd2029f23 2009
mbed_official 324:406fd2029f23 2010
mbed_official 324:406fd2029f23 2011 /* DMA - Register instance definitions */
mbed_official 324:406fd2029f23 2012 /* DMA */
mbed_official 324:406fd2029f23 2013 #define DMA_CR DMA_CR_REG(DMA0)
mbed_official 324:406fd2029f23 2014 #define DMA_ES DMA_ES_REG(DMA0)
mbed_official 324:406fd2029f23 2015 #define DMA_ERQ DMA_ERQ_REG(DMA0)
mbed_official 324:406fd2029f23 2016 #define DMA_EEI DMA_EEI_REG(DMA0)
mbed_official 324:406fd2029f23 2017 #define DMA_CEEI DMA_CEEI_REG(DMA0)
mbed_official 324:406fd2029f23 2018 #define DMA_SEEI DMA_SEEI_REG(DMA0)
mbed_official 324:406fd2029f23 2019 #define DMA_CERQ DMA_CERQ_REG(DMA0)
mbed_official 324:406fd2029f23 2020 #define DMA_SERQ DMA_SERQ_REG(DMA0)
mbed_official 324:406fd2029f23 2021 #define DMA_CDNE DMA_CDNE_REG(DMA0)
mbed_official 324:406fd2029f23 2022 #define DMA_SSRT DMA_SSRT_REG(DMA0)
mbed_official 324:406fd2029f23 2023 #define DMA_CERR DMA_CERR_REG(DMA0)
mbed_official 324:406fd2029f23 2024 #define DMA_CINT DMA_CINT_REG(DMA0)
mbed_official 324:406fd2029f23 2025 #define DMA_INT DMA_INT_REG(DMA0)
mbed_official 324:406fd2029f23 2026 #define DMA_ERR DMA_ERR_REG(DMA0)
mbed_official 324:406fd2029f23 2027 #define DMA_HRS DMA_HRS_REG(DMA0)
mbed_official 324:406fd2029f23 2028 #define DMA_EARS DMA_EARS_REG(DMA0)
mbed_official 324:406fd2029f23 2029 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
mbed_official 324:406fd2029f23 2030 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
mbed_official 324:406fd2029f23 2031 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
mbed_official 324:406fd2029f23 2032 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
mbed_official 324:406fd2029f23 2033 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
mbed_official 324:406fd2029f23 2034 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
mbed_official 324:406fd2029f23 2035 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
mbed_official 324:406fd2029f23 2036 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
mbed_official 324:406fd2029f23 2037 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
mbed_official 324:406fd2029f23 2038 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
mbed_official 324:406fd2029f23 2039 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
mbed_official 324:406fd2029f23 2040 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
mbed_official 324:406fd2029f23 2041 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
mbed_official 324:406fd2029f23 2042 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
mbed_official 324:406fd2029f23 2043 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
mbed_official 324:406fd2029f23 2044 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
mbed_official 324:406fd2029f23 2045 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
mbed_official 324:406fd2029f23 2046 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
mbed_official 324:406fd2029f23 2047 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
mbed_official 324:406fd2029f23 2048 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
mbed_official 324:406fd2029f23 2049 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
mbed_official 324:406fd2029f23 2050 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
mbed_official 324:406fd2029f23 2051 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
mbed_official 324:406fd2029f23 2052 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
mbed_official 324:406fd2029f23 2053 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
mbed_official 324:406fd2029f23 2054 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
mbed_official 324:406fd2029f23 2055 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
mbed_official 324:406fd2029f23 2056 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
mbed_official 324:406fd2029f23 2057 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
mbed_official 324:406fd2029f23 2058 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
mbed_official 324:406fd2029f23 2059 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
mbed_official 324:406fd2029f23 2060 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
mbed_official 324:406fd2029f23 2061 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
mbed_official 324:406fd2029f23 2062 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
mbed_official 324:406fd2029f23 2063 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
mbed_official 324:406fd2029f23 2064 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
mbed_official 324:406fd2029f23 2065 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
mbed_official 324:406fd2029f23 2066 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
mbed_official 324:406fd2029f23 2067 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
mbed_official 324:406fd2029f23 2068 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
mbed_official 324:406fd2029f23 2069 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
mbed_official 324:406fd2029f23 2070 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
mbed_official 324:406fd2029f23 2071 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
mbed_official 324:406fd2029f23 2072 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
mbed_official 324:406fd2029f23 2073 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
mbed_official 324:406fd2029f23 2074 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
mbed_official 324:406fd2029f23 2075 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
mbed_official 324:406fd2029f23 2076 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
mbed_official 324:406fd2029f23 2077 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
mbed_official 324:406fd2029f23 2078 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
mbed_official 324:406fd2029f23 2079 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
mbed_official 324:406fd2029f23 2080 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
mbed_official 324:406fd2029f23 2081 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
mbed_official 324:406fd2029f23 2082 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
mbed_official 324:406fd2029f23 2083 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
mbed_official 324:406fd2029f23 2084 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
mbed_official 324:406fd2029f23 2085 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
mbed_official 324:406fd2029f23 2086 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
mbed_official 324:406fd2029f23 2087 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
mbed_official 324:406fd2029f23 2088 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
mbed_official 324:406fd2029f23 2089 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
mbed_official 324:406fd2029f23 2090 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
mbed_official 324:406fd2029f23 2091 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
mbed_official 324:406fd2029f23 2092 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
mbed_official 324:406fd2029f23 2093 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
mbed_official 324:406fd2029f23 2094 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
mbed_official 324:406fd2029f23 2095 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
mbed_official 324:406fd2029f23 2096 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
mbed_official 324:406fd2029f23 2097 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
mbed_official 324:406fd2029f23 2098 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
mbed_official 324:406fd2029f23 2099 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
mbed_official 324:406fd2029f23 2100 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
mbed_official 324:406fd2029f23 2101 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
mbed_official 324:406fd2029f23 2102 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
mbed_official 324:406fd2029f23 2103 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
mbed_official 324:406fd2029f23 2104 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
mbed_official 324:406fd2029f23 2105 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
mbed_official 324:406fd2029f23 2106 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
mbed_official 324:406fd2029f23 2107 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
mbed_official 324:406fd2029f23 2108 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
mbed_official 324:406fd2029f23 2109 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
mbed_official 324:406fd2029f23 2110 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
mbed_official 324:406fd2029f23 2111 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
mbed_official 324:406fd2029f23 2112 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
mbed_official 324:406fd2029f23 2113 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
mbed_official 324:406fd2029f23 2114 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
mbed_official 324:406fd2029f23 2115 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
mbed_official 324:406fd2029f23 2116 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
mbed_official 324:406fd2029f23 2117 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
mbed_official 324:406fd2029f23 2118 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
mbed_official 324:406fd2029f23 2119 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
mbed_official 324:406fd2029f23 2120 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
mbed_official 324:406fd2029f23 2121 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
mbed_official 324:406fd2029f23 2122 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
mbed_official 324:406fd2029f23 2123 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
mbed_official 324:406fd2029f23 2124 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
mbed_official 324:406fd2029f23 2125 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
mbed_official 324:406fd2029f23 2126 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
mbed_official 324:406fd2029f23 2127 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
mbed_official 324:406fd2029f23 2128 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
mbed_official 324:406fd2029f23 2129 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
mbed_official 324:406fd2029f23 2130 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
mbed_official 324:406fd2029f23 2131 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
mbed_official 324:406fd2029f23 2132 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
mbed_official 324:406fd2029f23 2133 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
mbed_official 324:406fd2029f23 2134 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
mbed_official 324:406fd2029f23 2135 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
mbed_official 324:406fd2029f23 2136 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
mbed_official 324:406fd2029f23 2137 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
mbed_official 324:406fd2029f23 2138 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
mbed_official 324:406fd2029f23 2139 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
mbed_official 324:406fd2029f23 2140 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
mbed_official 324:406fd2029f23 2141 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
mbed_official 324:406fd2029f23 2142 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
mbed_official 324:406fd2029f23 2143 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
mbed_official 324:406fd2029f23 2144 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
mbed_official 324:406fd2029f23 2145 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
mbed_official 324:406fd2029f23 2146 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
mbed_official 324:406fd2029f23 2147 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
mbed_official 324:406fd2029f23 2148 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
mbed_official 324:406fd2029f23 2149 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
mbed_official 324:406fd2029f23 2150 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
mbed_official 324:406fd2029f23 2151 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
mbed_official 324:406fd2029f23 2152 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
mbed_official 324:406fd2029f23 2153 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
mbed_official 324:406fd2029f23 2154 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
mbed_official 324:406fd2029f23 2155 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
mbed_official 324:406fd2029f23 2156 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
mbed_official 324:406fd2029f23 2157 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
mbed_official 324:406fd2029f23 2158 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
mbed_official 324:406fd2029f23 2159 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
mbed_official 324:406fd2029f23 2160 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
mbed_official 324:406fd2029f23 2161 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
mbed_official 324:406fd2029f23 2162 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
mbed_official 324:406fd2029f23 2163 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
mbed_official 324:406fd2029f23 2164 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
mbed_official 324:406fd2029f23 2165 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
mbed_official 324:406fd2029f23 2166 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
mbed_official 324:406fd2029f23 2167 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
mbed_official 324:406fd2029f23 2168 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
mbed_official 324:406fd2029f23 2169 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
mbed_official 324:406fd2029f23 2170 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
mbed_official 324:406fd2029f23 2171 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
mbed_official 324:406fd2029f23 2172 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
mbed_official 324:406fd2029f23 2173 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
mbed_official 324:406fd2029f23 2174 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
mbed_official 324:406fd2029f23 2175 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
mbed_official 324:406fd2029f23 2176 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
mbed_official 324:406fd2029f23 2177 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
mbed_official 324:406fd2029f23 2178 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
mbed_official 324:406fd2029f23 2179 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
mbed_official 324:406fd2029f23 2180 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
mbed_official 324:406fd2029f23 2181 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
mbed_official 324:406fd2029f23 2182 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
mbed_official 324:406fd2029f23 2183 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
mbed_official 324:406fd2029f23 2184 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
mbed_official 324:406fd2029f23 2185 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
mbed_official 324:406fd2029f23 2186 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
mbed_official 324:406fd2029f23 2187 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
mbed_official 324:406fd2029f23 2188 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
mbed_official 324:406fd2029f23 2189 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
mbed_official 324:406fd2029f23 2190 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
mbed_official 324:406fd2029f23 2191 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
mbed_official 324:406fd2029f23 2192 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
mbed_official 324:406fd2029f23 2193 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
mbed_official 324:406fd2029f23 2194 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
mbed_official 324:406fd2029f23 2195 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
mbed_official 324:406fd2029f23 2196 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
mbed_official 324:406fd2029f23 2197 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
mbed_official 324:406fd2029f23 2198 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
mbed_official 324:406fd2029f23 2199 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
mbed_official 324:406fd2029f23 2200 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
mbed_official 324:406fd2029f23 2201 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
mbed_official 324:406fd2029f23 2202 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
mbed_official 324:406fd2029f23 2203 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
mbed_official 324:406fd2029f23 2204 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
mbed_official 324:406fd2029f23 2205 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
mbed_official 324:406fd2029f23 2206 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
mbed_official 324:406fd2029f23 2207 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
mbed_official 324:406fd2029f23 2208 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
mbed_official 324:406fd2029f23 2209 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
mbed_official 324:406fd2029f23 2210 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
mbed_official 324:406fd2029f23 2211 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
mbed_official 324:406fd2029f23 2212 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
mbed_official 324:406fd2029f23 2213 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
mbed_official 324:406fd2029f23 2214 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
mbed_official 324:406fd2029f23 2215 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
mbed_official 324:406fd2029f23 2216 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
mbed_official 324:406fd2029f23 2217 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
mbed_official 324:406fd2029f23 2218 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
mbed_official 324:406fd2029f23 2219 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
mbed_official 324:406fd2029f23 2220 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
mbed_official 324:406fd2029f23 2221 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
mbed_official 324:406fd2029f23 2222 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
mbed_official 324:406fd2029f23 2223 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
mbed_official 324:406fd2029f23 2224 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
mbed_official 324:406fd2029f23 2225 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
mbed_official 324:406fd2029f23 2226 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
mbed_official 324:406fd2029f23 2227 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
mbed_official 324:406fd2029f23 2228 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
mbed_official 324:406fd2029f23 2229 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
mbed_official 324:406fd2029f23 2230 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
mbed_official 324:406fd2029f23 2231 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
mbed_official 324:406fd2029f23 2232 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
mbed_official 324:406fd2029f23 2233 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
mbed_official 324:406fd2029f23 2234 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
mbed_official 324:406fd2029f23 2235 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
mbed_official 324:406fd2029f23 2236 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
mbed_official 324:406fd2029f23 2237 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
mbed_official 324:406fd2029f23 2238 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
mbed_official 324:406fd2029f23 2239 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
mbed_official 324:406fd2029f23 2240 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
mbed_official 324:406fd2029f23 2241 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
mbed_official 324:406fd2029f23 2242 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
mbed_official 324:406fd2029f23 2243 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
mbed_official 324:406fd2029f23 2244 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
mbed_official 324:406fd2029f23 2245 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
mbed_official 324:406fd2029f23 2246 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
mbed_official 324:406fd2029f23 2247 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
mbed_official 324:406fd2029f23 2248 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
mbed_official 324:406fd2029f23 2249 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
mbed_official 324:406fd2029f23 2250 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
mbed_official 324:406fd2029f23 2251 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
mbed_official 324:406fd2029f23 2252 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
mbed_official 324:406fd2029f23 2253 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
mbed_official 324:406fd2029f23 2254 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
mbed_official 324:406fd2029f23 2255 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
mbed_official 324:406fd2029f23 2256 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
mbed_official 324:406fd2029f23 2257 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
mbed_official 324:406fd2029f23 2258 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
mbed_official 324:406fd2029f23 2259 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
mbed_official 324:406fd2029f23 2260 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
mbed_official 324:406fd2029f23 2261 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
mbed_official 324:406fd2029f23 2262 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
mbed_official 324:406fd2029f23 2263 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
mbed_official 324:406fd2029f23 2264 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
mbed_official 324:406fd2029f23 2265 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
mbed_official 324:406fd2029f23 2266 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
mbed_official 324:406fd2029f23 2267 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
mbed_official 324:406fd2029f23 2268 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
mbed_official 324:406fd2029f23 2269 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
mbed_official 324:406fd2029f23 2270 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
mbed_official 324:406fd2029f23 2271 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
mbed_official 324:406fd2029f23 2272 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
mbed_official 324:406fd2029f23 2273 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
mbed_official 324:406fd2029f23 2274 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
mbed_official 324:406fd2029f23 2275 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
mbed_official 324:406fd2029f23 2276 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
mbed_official 324:406fd2029f23 2277 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
mbed_official 324:406fd2029f23 2278 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
mbed_official 324:406fd2029f23 2279 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
mbed_official 324:406fd2029f23 2280 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
mbed_official 324:406fd2029f23 2281 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
mbed_official 324:406fd2029f23 2282 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
mbed_official 324:406fd2029f23 2283 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
mbed_official 324:406fd2029f23 2284 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
mbed_official 324:406fd2029f23 2285
mbed_official 324:406fd2029f23 2286 /* DMA - Register array accessors */
mbed_official 324:406fd2029f23 2287 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
mbed_official 324:406fd2029f23 2288 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
mbed_official 324:406fd2029f23 2289 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
mbed_official 324:406fd2029f23 2290 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
mbed_official 324:406fd2029f23 2291 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
mbed_official 324:406fd2029f23 2292 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
mbed_official 324:406fd2029f23 2293 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
mbed_official 324:406fd2029f23 2294 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
mbed_official 324:406fd2029f23 2295 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
mbed_official 324:406fd2029f23 2296 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
mbed_official 324:406fd2029f23 2297 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
mbed_official 324:406fd2029f23 2298 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
mbed_official 324:406fd2029f23 2299 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
mbed_official 324:406fd2029f23 2300 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
mbed_official 324:406fd2029f23 2301 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
mbed_official 324:406fd2029f23 2302
mbed_official 324:406fd2029f23 2303 /*!
mbed_official 324:406fd2029f23 2304 * @}
mbed_official 324:406fd2029f23 2305 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2306
mbed_official 324:406fd2029f23 2307
mbed_official 324:406fd2029f23 2308 /*!
mbed_official 324:406fd2029f23 2309 * @}
mbed_official 324:406fd2029f23 2310 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 2311
mbed_official 324:406fd2029f23 2312
mbed_official 324:406fd2029f23 2313 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2314 -- DMAMUX Peripheral Access Layer
mbed_official 324:406fd2029f23 2315 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2316
mbed_official 324:406fd2029f23 2317 /*!
mbed_official 324:406fd2029f23 2318 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 324:406fd2029f23 2319 * @{
mbed_official 324:406fd2029f23 2320 */
mbed_official 324:406fd2029f23 2321
mbed_official 324:406fd2029f23 2322 /** DMAMUX - Register Layout Typedef */
mbed_official 324:406fd2029f23 2323 typedef struct {
mbed_official 324:406fd2029f23 2324 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 324:406fd2029f23 2325 } DMAMUX_Type, *DMAMUX_MemMapPtr;
mbed_official 324:406fd2029f23 2326
mbed_official 324:406fd2029f23 2327 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2328 -- DMAMUX - Register accessor macros
mbed_official 324:406fd2029f23 2329 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2330
mbed_official 324:406fd2029f23 2331 /*!
mbed_official 324:406fd2029f23 2332 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 324:406fd2029f23 2333 * @{
mbed_official 324:406fd2029f23 2334 */
mbed_official 324:406fd2029f23 2335
mbed_official 324:406fd2029f23 2336
mbed_official 324:406fd2029f23 2337 /* DMAMUX - Register accessors */
mbed_official 324:406fd2029f23 2338 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
mbed_official 324:406fd2029f23 2339
mbed_official 324:406fd2029f23 2340 /*!
mbed_official 324:406fd2029f23 2341 * @}
mbed_official 324:406fd2029f23 2342 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2343
mbed_official 324:406fd2029f23 2344
mbed_official 324:406fd2029f23 2345 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2346 -- DMAMUX Register Masks
mbed_official 324:406fd2029f23 2347 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2348
mbed_official 324:406fd2029f23 2349 /*!
mbed_official 324:406fd2029f23 2350 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 324:406fd2029f23 2351 * @{
mbed_official 324:406fd2029f23 2352 */
mbed_official 324:406fd2029f23 2353
mbed_official 324:406fd2029f23 2354 /* CHCFG Bit Fields */
mbed_official 324:406fd2029f23 2355 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 324:406fd2029f23 2356 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 324:406fd2029f23 2357 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 324:406fd2029f23 2358 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 324:406fd2029f23 2359 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 324:406fd2029f23 2360 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 324:406fd2029f23 2361 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 324:406fd2029f23 2362
mbed_official 324:406fd2029f23 2363 /*!
mbed_official 324:406fd2029f23 2364 * @}
mbed_official 324:406fd2029f23 2365 */ /* end of group DMAMUX_Register_Masks */
mbed_official 324:406fd2029f23 2366
mbed_official 324:406fd2029f23 2367
mbed_official 324:406fd2029f23 2368 /* DMAMUX - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 2369 /** Peripheral DMAMUX base address */
mbed_official 324:406fd2029f23 2370 #define DMAMUX_BASE (0x40021000u)
mbed_official 324:406fd2029f23 2371 /** Peripheral DMAMUX base pointer */
mbed_official 324:406fd2029f23 2372 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
mbed_official 324:406fd2029f23 2373 #define DMAMUX_BASE_PTR (DMAMUX)
mbed_official 324:406fd2029f23 2374 /** Array initializer of DMAMUX peripheral base addresses */
mbed_official 324:406fd2029f23 2375 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
mbed_official 324:406fd2029f23 2376 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 324:406fd2029f23 2377 #define DMAMUX_BASE_PTRS { DMAMUX }
mbed_official 324:406fd2029f23 2378
mbed_official 324:406fd2029f23 2379 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2380 -- DMAMUX - Register accessor macros
mbed_official 324:406fd2029f23 2381 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2382
mbed_official 324:406fd2029f23 2383 /*!
mbed_official 324:406fd2029f23 2384 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 324:406fd2029f23 2385 * @{
mbed_official 324:406fd2029f23 2386 */
mbed_official 324:406fd2029f23 2387
mbed_official 324:406fd2029f23 2388
mbed_official 324:406fd2029f23 2389 /* DMAMUX - Register instance definitions */
mbed_official 324:406fd2029f23 2390 /* DMAMUX */
mbed_official 324:406fd2029f23 2391 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
mbed_official 324:406fd2029f23 2392 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
mbed_official 324:406fd2029f23 2393 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
mbed_official 324:406fd2029f23 2394 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
mbed_official 324:406fd2029f23 2395 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
mbed_official 324:406fd2029f23 2396 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
mbed_official 324:406fd2029f23 2397 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
mbed_official 324:406fd2029f23 2398 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
mbed_official 324:406fd2029f23 2399 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
mbed_official 324:406fd2029f23 2400 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
mbed_official 324:406fd2029f23 2401 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
mbed_official 324:406fd2029f23 2402 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
mbed_official 324:406fd2029f23 2403 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
mbed_official 324:406fd2029f23 2404 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
mbed_official 324:406fd2029f23 2405 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
mbed_official 324:406fd2029f23 2406 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
mbed_official 324:406fd2029f23 2407
mbed_official 324:406fd2029f23 2408 /* DMAMUX - Register array accessors */
mbed_official 324:406fd2029f23 2409 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
mbed_official 324:406fd2029f23 2410
mbed_official 324:406fd2029f23 2411 /*!
mbed_official 324:406fd2029f23 2412 * @}
mbed_official 324:406fd2029f23 2413 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2414
mbed_official 324:406fd2029f23 2415
mbed_official 324:406fd2029f23 2416 /*!
mbed_official 324:406fd2029f23 2417 * @}
mbed_official 324:406fd2029f23 2418 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 2419
mbed_official 324:406fd2029f23 2420
mbed_official 324:406fd2029f23 2421 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2422 -- EWM Peripheral Access Layer
mbed_official 324:406fd2029f23 2423 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2424
mbed_official 324:406fd2029f23 2425 /*!
mbed_official 324:406fd2029f23 2426 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
mbed_official 324:406fd2029f23 2427 * @{
mbed_official 324:406fd2029f23 2428 */
mbed_official 324:406fd2029f23 2429
mbed_official 324:406fd2029f23 2430 /** EWM - Register Layout Typedef */
mbed_official 324:406fd2029f23 2431 typedef struct {
mbed_official 324:406fd2029f23 2432 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 2433 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
mbed_official 324:406fd2029f23 2434 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
mbed_official 324:406fd2029f23 2435 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
mbed_official 324:406fd2029f23 2436 uint8_t RESERVED_0[1];
mbed_official 324:406fd2029f23 2437 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
mbed_official 324:406fd2029f23 2438 } EWM_Type, *EWM_MemMapPtr;
mbed_official 324:406fd2029f23 2439
mbed_official 324:406fd2029f23 2440 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2441 -- EWM - Register accessor macros
mbed_official 324:406fd2029f23 2442 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2443
mbed_official 324:406fd2029f23 2444 /*!
mbed_official 324:406fd2029f23 2445 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
mbed_official 324:406fd2029f23 2446 * @{
mbed_official 324:406fd2029f23 2447 */
mbed_official 324:406fd2029f23 2448
mbed_official 324:406fd2029f23 2449
mbed_official 324:406fd2029f23 2450 /* EWM - Register accessors */
mbed_official 324:406fd2029f23 2451 #define EWM_CTRL_REG(base) ((base)->CTRL)
mbed_official 324:406fd2029f23 2452 #define EWM_SERV_REG(base) ((base)->SERV)
mbed_official 324:406fd2029f23 2453 #define EWM_CMPL_REG(base) ((base)->CMPL)
mbed_official 324:406fd2029f23 2454 #define EWM_CMPH_REG(base) ((base)->CMPH)
mbed_official 324:406fd2029f23 2455 #define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
mbed_official 324:406fd2029f23 2456
mbed_official 324:406fd2029f23 2457 /*!
mbed_official 324:406fd2029f23 2458 * @}
mbed_official 324:406fd2029f23 2459 */ /* end of group EWM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2460
mbed_official 324:406fd2029f23 2461
mbed_official 324:406fd2029f23 2462 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2463 -- EWM Register Masks
mbed_official 324:406fd2029f23 2464 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2465
mbed_official 324:406fd2029f23 2466 /*!
mbed_official 324:406fd2029f23 2467 * @addtogroup EWM_Register_Masks EWM Register Masks
mbed_official 324:406fd2029f23 2468 * @{
mbed_official 324:406fd2029f23 2469 */
mbed_official 324:406fd2029f23 2470
mbed_official 324:406fd2029f23 2471 /* CTRL Bit Fields */
mbed_official 324:406fd2029f23 2472 #define EWM_CTRL_EWMEN_MASK 0x1u
mbed_official 324:406fd2029f23 2473 #define EWM_CTRL_EWMEN_SHIFT 0
mbed_official 324:406fd2029f23 2474 #define EWM_CTRL_ASSIN_MASK 0x2u
mbed_official 324:406fd2029f23 2475 #define EWM_CTRL_ASSIN_SHIFT 1
mbed_official 324:406fd2029f23 2476 #define EWM_CTRL_INEN_MASK 0x4u
mbed_official 324:406fd2029f23 2477 #define EWM_CTRL_INEN_SHIFT 2
mbed_official 324:406fd2029f23 2478 #define EWM_CTRL_INTEN_MASK 0x8u
mbed_official 324:406fd2029f23 2479 #define EWM_CTRL_INTEN_SHIFT 3
mbed_official 324:406fd2029f23 2480 /* SERV Bit Fields */
mbed_official 324:406fd2029f23 2481 #define EWM_SERV_SERVICE_MASK 0xFFu
mbed_official 324:406fd2029f23 2482 #define EWM_SERV_SERVICE_SHIFT 0
mbed_official 324:406fd2029f23 2483 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
mbed_official 324:406fd2029f23 2484 /* CMPL Bit Fields */
mbed_official 324:406fd2029f23 2485 #define EWM_CMPL_COMPAREL_MASK 0xFFu
mbed_official 324:406fd2029f23 2486 #define EWM_CMPL_COMPAREL_SHIFT 0
mbed_official 324:406fd2029f23 2487 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
mbed_official 324:406fd2029f23 2488 /* CMPH Bit Fields */
mbed_official 324:406fd2029f23 2489 #define EWM_CMPH_COMPAREH_MASK 0xFFu
mbed_official 324:406fd2029f23 2490 #define EWM_CMPH_COMPAREH_SHIFT 0
mbed_official 324:406fd2029f23 2491 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
mbed_official 324:406fd2029f23 2492 /* CLKPRESCALER Bit Fields */
mbed_official 324:406fd2029f23 2493 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
mbed_official 324:406fd2029f23 2494 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
mbed_official 324:406fd2029f23 2495 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
mbed_official 324:406fd2029f23 2496
mbed_official 324:406fd2029f23 2497 /*!
mbed_official 324:406fd2029f23 2498 * @}
mbed_official 324:406fd2029f23 2499 */ /* end of group EWM_Register_Masks */
mbed_official 324:406fd2029f23 2500
mbed_official 324:406fd2029f23 2501
mbed_official 324:406fd2029f23 2502 /* EWM - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 2503 /** Peripheral EWM base address */
mbed_official 324:406fd2029f23 2504 #define EWM_BASE (0x40061000u)
mbed_official 324:406fd2029f23 2505 /** Peripheral EWM base pointer */
mbed_official 324:406fd2029f23 2506 #define EWM ((EWM_Type *)EWM_BASE)
mbed_official 324:406fd2029f23 2507 #define EWM_BASE_PTR (EWM)
mbed_official 324:406fd2029f23 2508 /** Array initializer of EWM peripheral base addresses */
mbed_official 324:406fd2029f23 2509 #define EWM_BASE_ADDRS { EWM_BASE }
mbed_official 324:406fd2029f23 2510 /** Array initializer of EWM peripheral base pointers */
mbed_official 324:406fd2029f23 2511 #define EWM_BASE_PTRS { EWM }
mbed_official 324:406fd2029f23 2512 /** Interrupt vectors for the EWM peripheral type */
mbed_official 324:406fd2029f23 2513 #define EWM_IRQS { Watchdog_IRQn }
mbed_official 324:406fd2029f23 2514
mbed_official 324:406fd2029f23 2515 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2516 -- EWM - Register accessor macros
mbed_official 324:406fd2029f23 2517 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2518
mbed_official 324:406fd2029f23 2519 /*!
mbed_official 324:406fd2029f23 2520 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
mbed_official 324:406fd2029f23 2521 * @{
mbed_official 324:406fd2029f23 2522 */
mbed_official 324:406fd2029f23 2523
mbed_official 324:406fd2029f23 2524
mbed_official 324:406fd2029f23 2525 /* EWM - Register instance definitions */
mbed_official 324:406fd2029f23 2526 /* EWM */
mbed_official 324:406fd2029f23 2527 #define EWM_CTRL EWM_CTRL_REG(EWM)
mbed_official 324:406fd2029f23 2528 #define EWM_SERV EWM_SERV_REG(EWM)
mbed_official 324:406fd2029f23 2529 #define EWM_CMPL EWM_CMPL_REG(EWM)
mbed_official 324:406fd2029f23 2530 #define EWM_CMPH EWM_CMPH_REG(EWM)
mbed_official 324:406fd2029f23 2531 #define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
mbed_official 324:406fd2029f23 2532
mbed_official 324:406fd2029f23 2533 /*!
mbed_official 324:406fd2029f23 2534 * @}
mbed_official 324:406fd2029f23 2535 */ /* end of group EWM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2536
mbed_official 324:406fd2029f23 2537
mbed_official 324:406fd2029f23 2538 /*!
mbed_official 324:406fd2029f23 2539 * @}
mbed_official 324:406fd2029f23 2540 */ /* end of group EWM_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 2541
mbed_official 324:406fd2029f23 2542
mbed_official 324:406fd2029f23 2543 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2544 -- FB Peripheral Access Layer
mbed_official 324:406fd2029f23 2545 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2546
mbed_official 324:406fd2029f23 2547 /*!
mbed_official 324:406fd2029f23 2548 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
mbed_official 324:406fd2029f23 2549 * @{
mbed_official 324:406fd2029f23 2550 */
mbed_official 324:406fd2029f23 2551
mbed_official 324:406fd2029f23 2552 /** FB - Register Layout Typedef */
mbed_official 324:406fd2029f23 2553 typedef struct {
mbed_official 324:406fd2029f23 2554 struct { /* offset: 0x0, array step: 0xC */
mbed_official 324:406fd2029f23 2555 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
mbed_official 324:406fd2029f23 2556 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
mbed_official 324:406fd2029f23 2557 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
mbed_official 324:406fd2029f23 2558 } CS[6];
mbed_official 324:406fd2029f23 2559 uint8_t RESERVED_0[24];
mbed_official 324:406fd2029f23 2560 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
mbed_official 324:406fd2029f23 2561 } FB_Type, *FB_MemMapPtr;
mbed_official 324:406fd2029f23 2562
mbed_official 324:406fd2029f23 2563 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2564 -- FB - Register accessor macros
mbed_official 324:406fd2029f23 2565 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2566
mbed_official 324:406fd2029f23 2567 /*!
mbed_official 324:406fd2029f23 2568 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
mbed_official 324:406fd2029f23 2569 * @{
mbed_official 324:406fd2029f23 2570 */
mbed_official 324:406fd2029f23 2571
mbed_official 324:406fd2029f23 2572
mbed_official 324:406fd2029f23 2573 /* FB - Register accessors */
mbed_official 324:406fd2029f23 2574 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
mbed_official 324:406fd2029f23 2575 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
mbed_official 324:406fd2029f23 2576 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
mbed_official 324:406fd2029f23 2577 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
mbed_official 324:406fd2029f23 2578
mbed_official 324:406fd2029f23 2579 /*!
mbed_official 324:406fd2029f23 2580 * @}
mbed_official 324:406fd2029f23 2581 */ /* end of group FB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2582
mbed_official 324:406fd2029f23 2583
mbed_official 324:406fd2029f23 2584 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2585 -- FB Register Masks
mbed_official 324:406fd2029f23 2586 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2587
mbed_official 324:406fd2029f23 2588 /*!
mbed_official 324:406fd2029f23 2589 * @addtogroup FB_Register_Masks FB Register Masks
mbed_official 324:406fd2029f23 2590 * @{
mbed_official 324:406fd2029f23 2591 */
mbed_official 324:406fd2029f23 2592
mbed_official 324:406fd2029f23 2593 /* CSAR Bit Fields */
mbed_official 324:406fd2029f23 2594 #define FB_CSAR_BA_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 2595 #define FB_CSAR_BA_SHIFT 16
mbed_official 324:406fd2029f23 2596 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
mbed_official 324:406fd2029f23 2597 /* CSMR Bit Fields */
mbed_official 324:406fd2029f23 2598 #define FB_CSMR_V_MASK 0x1u
mbed_official 324:406fd2029f23 2599 #define FB_CSMR_V_SHIFT 0
mbed_official 324:406fd2029f23 2600 #define FB_CSMR_WP_MASK 0x100u
mbed_official 324:406fd2029f23 2601 #define FB_CSMR_WP_SHIFT 8
mbed_official 324:406fd2029f23 2602 #define FB_CSMR_BAM_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 2603 #define FB_CSMR_BAM_SHIFT 16
mbed_official 324:406fd2029f23 2604 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
mbed_official 324:406fd2029f23 2605 /* CSCR Bit Fields */
mbed_official 324:406fd2029f23 2606 #define FB_CSCR_BSTW_MASK 0x8u
mbed_official 324:406fd2029f23 2607 #define FB_CSCR_BSTW_SHIFT 3
mbed_official 324:406fd2029f23 2608 #define FB_CSCR_BSTR_MASK 0x10u
mbed_official 324:406fd2029f23 2609 #define FB_CSCR_BSTR_SHIFT 4
mbed_official 324:406fd2029f23 2610 #define FB_CSCR_BEM_MASK 0x20u
mbed_official 324:406fd2029f23 2611 #define FB_CSCR_BEM_SHIFT 5
mbed_official 324:406fd2029f23 2612 #define FB_CSCR_PS_MASK 0xC0u
mbed_official 324:406fd2029f23 2613 #define FB_CSCR_PS_SHIFT 6
mbed_official 324:406fd2029f23 2614 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
mbed_official 324:406fd2029f23 2615 #define FB_CSCR_AA_MASK 0x100u
mbed_official 324:406fd2029f23 2616 #define FB_CSCR_AA_SHIFT 8
mbed_official 324:406fd2029f23 2617 #define FB_CSCR_BLS_MASK 0x200u
mbed_official 324:406fd2029f23 2618 #define FB_CSCR_BLS_SHIFT 9
mbed_official 324:406fd2029f23 2619 #define FB_CSCR_WS_MASK 0xFC00u
mbed_official 324:406fd2029f23 2620 #define FB_CSCR_WS_SHIFT 10
mbed_official 324:406fd2029f23 2621 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
mbed_official 324:406fd2029f23 2622 #define FB_CSCR_WRAH_MASK 0x30000u
mbed_official 324:406fd2029f23 2623 #define FB_CSCR_WRAH_SHIFT 16
mbed_official 324:406fd2029f23 2624 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
mbed_official 324:406fd2029f23 2625 #define FB_CSCR_RDAH_MASK 0xC0000u
mbed_official 324:406fd2029f23 2626 #define FB_CSCR_RDAH_SHIFT 18
mbed_official 324:406fd2029f23 2627 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
mbed_official 324:406fd2029f23 2628 #define FB_CSCR_ASET_MASK 0x300000u
mbed_official 324:406fd2029f23 2629 #define FB_CSCR_ASET_SHIFT 20
mbed_official 324:406fd2029f23 2630 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
mbed_official 324:406fd2029f23 2631 #define FB_CSCR_EXTS_MASK 0x400000u
mbed_official 324:406fd2029f23 2632 #define FB_CSCR_EXTS_SHIFT 22
mbed_official 324:406fd2029f23 2633 #define FB_CSCR_SWSEN_MASK 0x800000u
mbed_official 324:406fd2029f23 2634 #define FB_CSCR_SWSEN_SHIFT 23
mbed_official 324:406fd2029f23 2635 #define FB_CSCR_SWS_MASK 0xFC000000u
mbed_official 324:406fd2029f23 2636 #define FB_CSCR_SWS_SHIFT 26
mbed_official 324:406fd2029f23 2637 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
mbed_official 324:406fd2029f23 2638 /* CSPMCR Bit Fields */
mbed_official 324:406fd2029f23 2639 #define FB_CSPMCR_GROUP5_MASK 0xF000u
mbed_official 324:406fd2029f23 2640 #define FB_CSPMCR_GROUP5_SHIFT 12
mbed_official 324:406fd2029f23 2641 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
mbed_official 324:406fd2029f23 2642 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
mbed_official 324:406fd2029f23 2643 #define FB_CSPMCR_GROUP4_SHIFT 16
mbed_official 324:406fd2029f23 2644 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
mbed_official 324:406fd2029f23 2645 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
mbed_official 324:406fd2029f23 2646 #define FB_CSPMCR_GROUP3_SHIFT 20
mbed_official 324:406fd2029f23 2647 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
mbed_official 324:406fd2029f23 2648 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
mbed_official 324:406fd2029f23 2649 #define FB_CSPMCR_GROUP2_SHIFT 24
mbed_official 324:406fd2029f23 2650 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
mbed_official 324:406fd2029f23 2651 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
mbed_official 324:406fd2029f23 2652 #define FB_CSPMCR_GROUP1_SHIFT 28
mbed_official 324:406fd2029f23 2653 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
mbed_official 324:406fd2029f23 2654
mbed_official 324:406fd2029f23 2655 /*!
mbed_official 324:406fd2029f23 2656 * @}
mbed_official 324:406fd2029f23 2657 */ /* end of group FB_Register_Masks */
mbed_official 324:406fd2029f23 2658
mbed_official 324:406fd2029f23 2659
mbed_official 324:406fd2029f23 2660 /* FB - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 2661 /** Peripheral FB base address */
mbed_official 324:406fd2029f23 2662 #define FB_BASE (0x4000C000u)
mbed_official 324:406fd2029f23 2663 /** Peripheral FB base pointer */
mbed_official 324:406fd2029f23 2664 #define FB ((FB_Type *)FB_BASE)
mbed_official 324:406fd2029f23 2665 #define FB_BASE_PTR (FB)
mbed_official 324:406fd2029f23 2666 /** Array initializer of FB peripheral base addresses */
mbed_official 324:406fd2029f23 2667 #define FB_BASE_ADDRS { FB_BASE }
mbed_official 324:406fd2029f23 2668 /** Array initializer of FB peripheral base pointers */
mbed_official 324:406fd2029f23 2669 #define FB_BASE_PTRS { FB }
mbed_official 324:406fd2029f23 2670
mbed_official 324:406fd2029f23 2671 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2672 -- FB - Register accessor macros
mbed_official 324:406fd2029f23 2673 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2674
mbed_official 324:406fd2029f23 2675 /*!
mbed_official 324:406fd2029f23 2676 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
mbed_official 324:406fd2029f23 2677 * @{
mbed_official 324:406fd2029f23 2678 */
mbed_official 324:406fd2029f23 2679
mbed_official 324:406fd2029f23 2680
mbed_official 324:406fd2029f23 2681 /* FB - Register instance definitions */
mbed_official 324:406fd2029f23 2682 /* FB */
mbed_official 324:406fd2029f23 2683 #define FB_CSAR0 FB_CSAR_REG(FB,0)
mbed_official 324:406fd2029f23 2684 #define FB_CSMR0 FB_CSMR_REG(FB,0)
mbed_official 324:406fd2029f23 2685 #define FB_CSCR0 FB_CSCR_REG(FB,0)
mbed_official 324:406fd2029f23 2686 #define FB_CSAR1 FB_CSAR_REG(FB,1)
mbed_official 324:406fd2029f23 2687 #define FB_CSMR1 FB_CSMR_REG(FB,1)
mbed_official 324:406fd2029f23 2688 #define FB_CSCR1 FB_CSCR_REG(FB,1)
mbed_official 324:406fd2029f23 2689 #define FB_CSAR2 FB_CSAR_REG(FB,2)
mbed_official 324:406fd2029f23 2690 #define FB_CSMR2 FB_CSMR_REG(FB,2)
mbed_official 324:406fd2029f23 2691 #define FB_CSCR2 FB_CSCR_REG(FB,2)
mbed_official 324:406fd2029f23 2692 #define FB_CSAR3 FB_CSAR_REG(FB,3)
mbed_official 324:406fd2029f23 2693 #define FB_CSMR3 FB_CSMR_REG(FB,3)
mbed_official 324:406fd2029f23 2694 #define FB_CSCR3 FB_CSCR_REG(FB,3)
mbed_official 324:406fd2029f23 2695 #define FB_CSAR4 FB_CSAR_REG(FB,4)
mbed_official 324:406fd2029f23 2696 #define FB_CSMR4 FB_CSMR_REG(FB,4)
mbed_official 324:406fd2029f23 2697 #define FB_CSCR4 FB_CSCR_REG(FB,4)
mbed_official 324:406fd2029f23 2698 #define FB_CSAR5 FB_CSAR_REG(FB,5)
mbed_official 324:406fd2029f23 2699 #define FB_CSMR5 FB_CSMR_REG(FB,5)
mbed_official 324:406fd2029f23 2700 #define FB_CSCR5 FB_CSCR_REG(FB,5)
mbed_official 324:406fd2029f23 2701 #define FB_CSPMCR FB_CSPMCR_REG(FB)
mbed_official 324:406fd2029f23 2702
mbed_official 324:406fd2029f23 2703 /* FB - Register array accessors */
mbed_official 324:406fd2029f23 2704 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
mbed_official 324:406fd2029f23 2705 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
mbed_official 324:406fd2029f23 2706 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
mbed_official 324:406fd2029f23 2707
mbed_official 324:406fd2029f23 2708 /*!
mbed_official 324:406fd2029f23 2709 * @}
mbed_official 324:406fd2029f23 2710 */ /* end of group FB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2711
mbed_official 324:406fd2029f23 2712
mbed_official 324:406fd2029f23 2713 /*!
mbed_official 324:406fd2029f23 2714 * @}
mbed_official 324:406fd2029f23 2715 */ /* end of group FB_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 2716
mbed_official 324:406fd2029f23 2717
mbed_official 324:406fd2029f23 2718 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2719 -- FMC Peripheral Access Layer
mbed_official 324:406fd2029f23 2720 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2721
mbed_official 324:406fd2029f23 2722 /*!
mbed_official 324:406fd2029f23 2723 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
mbed_official 324:406fd2029f23 2724 * @{
mbed_official 324:406fd2029f23 2725 */
mbed_official 324:406fd2029f23 2726
mbed_official 324:406fd2029f23 2727 /** FMC - Register Layout Typedef */
mbed_official 324:406fd2029f23 2728 typedef struct {
mbed_official 324:406fd2029f23 2729 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
mbed_official 324:406fd2029f23 2730 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
mbed_official 324:406fd2029f23 2731 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
mbed_official 324:406fd2029f23 2732 uint8_t RESERVED_0[244];
mbed_official 324:406fd2029f23 2733 __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
mbed_official 324:406fd2029f23 2734 __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
mbed_official 324:406fd2029f23 2735 __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
mbed_official 324:406fd2029f23 2736 __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
mbed_official 324:406fd2029f23 2737 uint8_t RESERVED_1[128];
mbed_official 324:406fd2029f23 2738 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
mbed_official 324:406fd2029f23 2739 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
mbed_official 324:406fd2029f23 2740 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
mbed_official 324:406fd2029f23 2741 } SET[4][8];
mbed_official 324:406fd2029f23 2742 } FMC_Type, *FMC_MemMapPtr;
mbed_official 324:406fd2029f23 2743
mbed_official 324:406fd2029f23 2744 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2745 -- FMC - Register accessor macros
mbed_official 324:406fd2029f23 2746 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2747
mbed_official 324:406fd2029f23 2748 /*!
mbed_official 324:406fd2029f23 2749 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
mbed_official 324:406fd2029f23 2750 * @{
mbed_official 324:406fd2029f23 2751 */
mbed_official 324:406fd2029f23 2752
mbed_official 324:406fd2029f23 2753
mbed_official 324:406fd2029f23 2754 /* FMC - Register accessors */
mbed_official 324:406fd2029f23 2755 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
mbed_official 324:406fd2029f23 2756 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
mbed_official 324:406fd2029f23 2757 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
mbed_official 324:406fd2029f23 2758 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
mbed_official 324:406fd2029f23 2759 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
mbed_official 324:406fd2029f23 2760 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
mbed_official 324:406fd2029f23 2761 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
mbed_official 324:406fd2029f23 2762 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
mbed_official 324:406fd2029f23 2763 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
mbed_official 324:406fd2029f23 2764
mbed_official 324:406fd2029f23 2765 /*!
mbed_official 324:406fd2029f23 2766 * @}
mbed_official 324:406fd2029f23 2767 */ /* end of group FMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 2768
mbed_official 324:406fd2029f23 2769
mbed_official 324:406fd2029f23 2770 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2771 -- FMC Register Masks
mbed_official 324:406fd2029f23 2772 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2773
mbed_official 324:406fd2029f23 2774 /*!
mbed_official 324:406fd2029f23 2775 * @addtogroup FMC_Register_Masks FMC Register Masks
mbed_official 324:406fd2029f23 2776 * @{
mbed_official 324:406fd2029f23 2777 */
mbed_official 324:406fd2029f23 2778
mbed_official 324:406fd2029f23 2779 /* PFAPR Bit Fields */
mbed_official 324:406fd2029f23 2780 #define FMC_PFAPR_M0AP_MASK 0x3u
mbed_official 324:406fd2029f23 2781 #define FMC_PFAPR_M0AP_SHIFT 0
mbed_official 324:406fd2029f23 2782 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
mbed_official 324:406fd2029f23 2783 #define FMC_PFAPR_M1AP_MASK 0xCu
mbed_official 324:406fd2029f23 2784 #define FMC_PFAPR_M1AP_SHIFT 2
mbed_official 324:406fd2029f23 2785 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
mbed_official 324:406fd2029f23 2786 #define FMC_PFAPR_M2AP_MASK 0x30u
mbed_official 324:406fd2029f23 2787 #define FMC_PFAPR_M2AP_SHIFT 4
mbed_official 324:406fd2029f23 2788 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
mbed_official 324:406fd2029f23 2789 #define FMC_PFAPR_M3AP_MASK 0xC0u
mbed_official 324:406fd2029f23 2790 #define FMC_PFAPR_M3AP_SHIFT 6
mbed_official 324:406fd2029f23 2791 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
mbed_official 324:406fd2029f23 2792 #define FMC_PFAPR_M4AP_MASK 0x300u
mbed_official 324:406fd2029f23 2793 #define FMC_PFAPR_M4AP_SHIFT 8
mbed_official 324:406fd2029f23 2794 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
mbed_official 324:406fd2029f23 2795 #define FMC_PFAPR_M5AP_MASK 0xC00u
mbed_official 324:406fd2029f23 2796 #define FMC_PFAPR_M5AP_SHIFT 10
mbed_official 324:406fd2029f23 2797 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
mbed_official 324:406fd2029f23 2798 #define FMC_PFAPR_M6AP_MASK 0x3000u
mbed_official 324:406fd2029f23 2799 #define FMC_PFAPR_M6AP_SHIFT 12
mbed_official 324:406fd2029f23 2800 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
mbed_official 324:406fd2029f23 2801 #define FMC_PFAPR_M7AP_MASK 0xC000u
mbed_official 324:406fd2029f23 2802 #define FMC_PFAPR_M7AP_SHIFT 14
mbed_official 324:406fd2029f23 2803 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
mbed_official 324:406fd2029f23 2804 #define FMC_PFAPR_M0PFD_MASK 0x10000u
mbed_official 324:406fd2029f23 2805 #define FMC_PFAPR_M0PFD_SHIFT 16
mbed_official 324:406fd2029f23 2806 #define FMC_PFAPR_M1PFD_MASK 0x20000u
mbed_official 324:406fd2029f23 2807 #define FMC_PFAPR_M1PFD_SHIFT 17
mbed_official 324:406fd2029f23 2808 #define FMC_PFAPR_M2PFD_MASK 0x40000u
mbed_official 324:406fd2029f23 2809 #define FMC_PFAPR_M2PFD_SHIFT 18
mbed_official 324:406fd2029f23 2810 #define FMC_PFAPR_M3PFD_MASK 0x80000u
mbed_official 324:406fd2029f23 2811 #define FMC_PFAPR_M3PFD_SHIFT 19
mbed_official 324:406fd2029f23 2812 #define FMC_PFAPR_M4PFD_MASK 0x100000u
mbed_official 324:406fd2029f23 2813 #define FMC_PFAPR_M4PFD_SHIFT 20
mbed_official 324:406fd2029f23 2814 #define FMC_PFAPR_M5PFD_MASK 0x200000u
mbed_official 324:406fd2029f23 2815 #define FMC_PFAPR_M5PFD_SHIFT 21
mbed_official 324:406fd2029f23 2816 #define FMC_PFAPR_M6PFD_MASK 0x400000u
mbed_official 324:406fd2029f23 2817 #define FMC_PFAPR_M6PFD_SHIFT 22
mbed_official 324:406fd2029f23 2818 #define FMC_PFAPR_M7PFD_MASK 0x800000u
mbed_official 324:406fd2029f23 2819 #define FMC_PFAPR_M7PFD_SHIFT 23
mbed_official 324:406fd2029f23 2820 /* PFB0CR Bit Fields */
mbed_official 324:406fd2029f23 2821 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
mbed_official 324:406fd2029f23 2822 #define FMC_PFB0CR_B0SEBE_SHIFT 0
mbed_official 324:406fd2029f23 2823 #define FMC_PFB0CR_B0IPE_MASK 0x2u
mbed_official 324:406fd2029f23 2824 #define FMC_PFB0CR_B0IPE_SHIFT 1
mbed_official 324:406fd2029f23 2825 #define FMC_PFB0CR_B0DPE_MASK 0x4u
mbed_official 324:406fd2029f23 2826 #define FMC_PFB0CR_B0DPE_SHIFT 2
mbed_official 324:406fd2029f23 2827 #define FMC_PFB0CR_B0ICE_MASK 0x8u
mbed_official 324:406fd2029f23 2828 #define FMC_PFB0CR_B0ICE_SHIFT 3
mbed_official 324:406fd2029f23 2829 #define FMC_PFB0CR_B0DCE_MASK 0x10u
mbed_official 324:406fd2029f23 2830 #define FMC_PFB0CR_B0DCE_SHIFT 4
mbed_official 324:406fd2029f23 2831 #define FMC_PFB0CR_CRC_MASK 0xE0u
mbed_official 324:406fd2029f23 2832 #define FMC_PFB0CR_CRC_SHIFT 5
mbed_official 324:406fd2029f23 2833 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
mbed_official 324:406fd2029f23 2834 #define FMC_PFB0CR_B0MW_MASK 0x60000u
mbed_official 324:406fd2029f23 2835 #define FMC_PFB0CR_B0MW_SHIFT 17
mbed_official 324:406fd2029f23 2836 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
mbed_official 324:406fd2029f23 2837 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
mbed_official 324:406fd2029f23 2838 #define FMC_PFB0CR_S_B_INV_SHIFT 19
mbed_official 324:406fd2029f23 2839 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
mbed_official 324:406fd2029f23 2840 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
mbed_official 324:406fd2029f23 2841 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
mbed_official 324:406fd2029f23 2842 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
mbed_official 324:406fd2029f23 2843 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
mbed_official 324:406fd2029f23 2844 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
mbed_official 324:406fd2029f23 2845 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
mbed_official 324:406fd2029f23 2846 #define FMC_PFB0CR_B0RWSC_SHIFT 28
mbed_official 324:406fd2029f23 2847 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
mbed_official 324:406fd2029f23 2848 /* PFB1CR Bit Fields */
mbed_official 324:406fd2029f23 2849 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
mbed_official 324:406fd2029f23 2850 #define FMC_PFB1CR_B1SEBE_SHIFT 0
mbed_official 324:406fd2029f23 2851 #define FMC_PFB1CR_B1IPE_MASK 0x2u
mbed_official 324:406fd2029f23 2852 #define FMC_PFB1CR_B1IPE_SHIFT 1
mbed_official 324:406fd2029f23 2853 #define FMC_PFB1CR_B1DPE_MASK 0x4u
mbed_official 324:406fd2029f23 2854 #define FMC_PFB1CR_B1DPE_SHIFT 2
mbed_official 324:406fd2029f23 2855 #define FMC_PFB1CR_B1ICE_MASK 0x8u
mbed_official 324:406fd2029f23 2856 #define FMC_PFB1CR_B1ICE_SHIFT 3
mbed_official 324:406fd2029f23 2857 #define FMC_PFB1CR_B1DCE_MASK 0x10u
mbed_official 324:406fd2029f23 2858 #define FMC_PFB1CR_B1DCE_SHIFT 4
mbed_official 324:406fd2029f23 2859 #define FMC_PFB1CR_B1MW_MASK 0x60000u
mbed_official 324:406fd2029f23 2860 #define FMC_PFB1CR_B1MW_SHIFT 17
mbed_official 324:406fd2029f23 2861 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
mbed_official 324:406fd2029f23 2862 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
mbed_official 324:406fd2029f23 2863 #define FMC_PFB1CR_B1RWSC_SHIFT 28
mbed_official 324:406fd2029f23 2864 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
mbed_official 324:406fd2029f23 2865 /* TAGVDW0S Bit Fields */
mbed_official 324:406fd2029f23 2866 #define FMC_TAGVDW0S_valid_MASK 0x1u
mbed_official 324:406fd2029f23 2867 #define FMC_TAGVDW0S_valid_SHIFT 0
mbed_official 324:406fd2029f23 2868 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
mbed_official 324:406fd2029f23 2869 #define FMC_TAGVDW0S_tag_SHIFT 5
mbed_official 324:406fd2029f23 2870 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
mbed_official 324:406fd2029f23 2871 /* TAGVDW1S Bit Fields */
mbed_official 324:406fd2029f23 2872 #define FMC_TAGVDW1S_valid_MASK 0x1u
mbed_official 324:406fd2029f23 2873 #define FMC_TAGVDW1S_valid_SHIFT 0
mbed_official 324:406fd2029f23 2874 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
mbed_official 324:406fd2029f23 2875 #define FMC_TAGVDW1S_tag_SHIFT 5
mbed_official 324:406fd2029f23 2876 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
mbed_official 324:406fd2029f23 2877 /* TAGVDW2S Bit Fields */
mbed_official 324:406fd2029f23 2878 #define FMC_TAGVDW2S_valid_MASK 0x1u
mbed_official 324:406fd2029f23 2879 #define FMC_TAGVDW2S_valid_SHIFT 0
mbed_official 324:406fd2029f23 2880 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
mbed_official 324:406fd2029f23 2881 #define FMC_TAGVDW2S_tag_SHIFT 5
mbed_official 324:406fd2029f23 2882 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
mbed_official 324:406fd2029f23 2883 /* TAGVDW3S Bit Fields */
mbed_official 324:406fd2029f23 2884 #define FMC_TAGVDW3S_valid_MASK 0x1u
mbed_official 324:406fd2029f23 2885 #define FMC_TAGVDW3S_valid_SHIFT 0
mbed_official 324:406fd2029f23 2886 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
mbed_official 324:406fd2029f23 2887 #define FMC_TAGVDW3S_tag_SHIFT 5
mbed_official 324:406fd2029f23 2888 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
mbed_official 324:406fd2029f23 2889 /* DATA_U Bit Fields */
mbed_official 324:406fd2029f23 2890 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 2891 #define FMC_DATA_U_data_SHIFT 0
mbed_official 324:406fd2029f23 2892 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
mbed_official 324:406fd2029f23 2893 /* DATA_L Bit Fields */
mbed_official 324:406fd2029f23 2894 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 2895 #define FMC_DATA_L_data_SHIFT 0
mbed_official 324:406fd2029f23 2896 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
mbed_official 324:406fd2029f23 2897
mbed_official 324:406fd2029f23 2898 /*!
mbed_official 324:406fd2029f23 2899 * @}
mbed_official 324:406fd2029f23 2900 */ /* end of group FMC_Register_Masks */
mbed_official 324:406fd2029f23 2901
mbed_official 324:406fd2029f23 2902
mbed_official 324:406fd2029f23 2903 /* FMC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 2904 /** Peripheral FMC base address */
mbed_official 324:406fd2029f23 2905 #define FMC_BASE (0x4001F000u)
mbed_official 324:406fd2029f23 2906 /** Peripheral FMC base pointer */
mbed_official 324:406fd2029f23 2907 #define FMC ((FMC_Type *)FMC_BASE)
mbed_official 324:406fd2029f23 2908 #define FMC_BASE_PTR (FMC)
mbed_official 324:406fd2029f23 2909 /** Array initializer of FMC peripheral base addresses */
mbed_official 324:406fd2029f23 2910 #define FMC_BASE_ADDRS { FMC_BASE }
mbed_official 324:406fd2029f23 2911 /** Array initializer of FMC peripheral base pointers */
mbed_official 324:406fd2029f23 2912 #define FMC_BASE_PTRS { FMC }
mbed_official 324:406fd2029f23 2913
mbed_official 324:406fd2029f23 2914 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 2915 -- FMC - Register accessor macros
mbed_official 324:406fd2029f23 2916 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 2917
mbed_official 324:406fd2029f23 2918 /*!
mbed_official 324:406fd2029f23 2919 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
mbed_official 324:406fd2029f23 2920 * @{
mbed_official 324:406fd2029f23 2921 */
mbed_official 324:406fd2029f23 2922
mbed_official 324:406fd2029f23 2923
mbed_official 324:406fd2029f23 2924 /* FMC - Register instance definitions */
mbed_official 324:406fd2029f23 2925 /* FMC */
mbed_official 324:406fd2029f23 2926 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
mbed_official 324:406fd2029f23 2927 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
mbed_official 324:406fd2029f23 2928 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
mbed_official 324:406fd2029f23 2929 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
mbed_official 324:406fd2029f23 2930 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
mbed_official 324:406fd2029f23 2931 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
mbed_official 324:406fd2029f23 2932 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
mbed_official 324:406fd2029f23 2933 #define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
mbed_official 324:406fd2029f23 2934 #define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
mbed_official 324:406fd2029f23 2935 #define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
mbed_official 324:406fd2029f23 2936 #define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
mbed_official 324:406fd2029f23 2937 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
mbed_official 324:406fd2029f23 2938 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
mbed_official 324:406fd2029f23 2939 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
mbed_official 324:406fd2029f23 2940 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
mbed_official 324:406fd2029f23 2941 #define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
mbed_official 324:406fd2029f23 2942 #define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
mbed_official 324:406fd2029f23 2943 #define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
mbed_official 324:406fd2029f23 2944 #define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
mbed_official 324:406fd2029f23 2945 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
mbed_official 324:406fd2029f23 2946 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
mbed_official 324:406fd2029f23 2947 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
mbed_official 324:406fd2029f23 2948 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
mbed_official 324:406fd2029f23 2949 #define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
mbed_official 324:406fd2029f23 2950 #define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
mbed_official 324:406fd2029f23 2951 #define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
mbed_official 324:406fd2029f23 2952 #define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
mbed_official 324:406fd2029f23 2953 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
mbed_official 324:406fd2029f23 2954 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
mbed_official 324:406fd2029f23 2955 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
mbed_official 324:406fd2029f23 2956 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
mbed_official 324:406fd2029f23 2957 #define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
mbed_official 324:406fd2029f23 2958 #define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
mbed_official 324:406fd2029f23 2959 #define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
mbed_official 324:406fd2029f23 2960 #define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
mbed_official 324:406fd2029f23 2961 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
mbed_official 324:406fd2029f23 2962 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
mbed_official 324:406fd2029f23 2963 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
mbed_official 324:406fd2029f23 2964 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
mbed_official 324:406fd2029f23 2965 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
mbed_official 324:406fd2029f23 2966 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
mbed_official 324:406fd2029f23 2967 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
mbed_official 324:406fd2029f23 2968 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
mbed_official 324:406fd2029f23 2969 #define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
mbed_official 324:406fd2029f23 2970 #define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
mbed_official 324:406fd2029f23 2971 #define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
mbed_official 324:406fd2029f23 2972 #define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
mbed_official 324:406fd2029f23 2973 #define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
mbed_official 324:406fd2029f23 2974 #define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
mbed_official 324:406fd2029f23 2975 #define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
mbed_official 324:406fd2029f23 2976 #define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
mbed_official 324:406fd2029f23 2977 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
mbed_official 324:406fd2029f23 2978 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
mbed_official 324:406fd2029f23 2979 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
mbed_official 324:406fd2029f23 2980 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
mbed_official 324:406fd2029f23 2981 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
mbed_official 324:406fd2029f23 2982 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
mbed_official 324:406fd2029f23 2983 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
mbed_official 324:406fd2029f23 2984 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
mbed_official 324:406fd2029f23 2985 #define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
mbed_official 324:406fd2029f23 2986 #define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
mbed_official 324:406fd2029f23 2987 #define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
mbed_official 324:406fd2029f23 2988 #define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
mbed_official 324:406fd2029f23 2989 #define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
mbed_official 324:406fd2029f23 2990 #define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
mbed_official 324:406fd2029f23 2991 #define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
mbed_official 324:406fd2029f23 2992 #define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
mbed_official 324:406fd2029f23 2993 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
mbed_official 324:406fd2029f23 2994 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
mbed_official 324:406fd2029f23 2995 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
mbed_official 324:406fd2029f23 2996 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
mbed_official 324:406fd2029f23 2997 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
mbed_official 324:406fd2029f23 2998 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
mbed_official 324:406fd2029f23 2999 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
mbed_official 324:406fd2029f23 3000 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
mbed_official 324:406fd2029f23 3001 #define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
mbed_official 324:406fd2029f23 3002 #define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
mbed_official 324:406fd2029f23 3003 #define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
mbed_official 324:406fd2029f23 3004 #define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
mbed_official 324:406fd2029f23 3005 #define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
mbed_official 324:406fd2029f23 3006 #define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
mbed_official 324:406fd2029f23 3007 #define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
mbed_official 324:406fd2029f23 3008 #define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
mbed_official 324:406fd2029f23 3009 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
mbed_official 324:406fd2029f23 3010 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
mbed_official 324:406fd2029f23 3011 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
mbed_official 324:406fd2029f23 3012 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
mbed_official 324:406fd2029f23 3013 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
mbed_official 324:406fd2029f23 3014 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
mbed_official 324:406fd2029f23 3015 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
mbed_official 324:406fd2029f23 3016 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
mbed_official 324:406fd2029f23 3017 #define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
mbed_official 324:406fd2029f23 3018 #define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
mbed_official 324:406fd2029f23 3019 #define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
mbed_official 324:406fd2029f23 3020 #define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
mbed_official 324:406fd2029f23 3021 #define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
mbed_official 324:406fd2029f23 3022 #define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
mbed_official 324:406fd2029f23 3023 #define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
mbed_official 324:406fd2029f23 3024 #define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
mbed_official 324:406fd2029f23 3025
mbed_official 324:406fd2029f23 3026 /* FMC - Register array accessors */
mbed_official 324:406fd2029f23 3027 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
mbed_official 324:406fd2029f23 3028 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
mbed_official 324:406fd2029f23 3029 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
mbed_official 324:406fd2029f23 3030 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
mbed_official 324:406fd2029f23 3031 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
mbed_official 324:406fd2029f23 3032 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
mbed_official 324:406fd2029f23 3033
mbed_official 324:406fd2029f23 3034 /*!
mbed_official 324:406fd2029f23 3035 * @}
mbed_official 324:406fd2029f23 3036 */ /* end of group FMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 3037
mbed_official 324:406fd2029f23 3038
mbed_official 324:406fd2029f23 3039 /*!
mbed_official 324:406fd2029f23 3040 * @}
mbed_official 324:406fd2029f23 3041 */ /* end of group FMC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 3042
mbed_official 324:406fd2029f23 3043
mbed_official 324:406fd2029f23 3044 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3045 -- FTFA Peripheral Access Layer
mbed_official 324:406fd2029f23 3046 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3047
mbed_official 324:406fd2029f23 3048 /*!
mbed_official 324:406fd2029f23 3049 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mbed_official 324:406fd2029f23 3050 * @{
mbed_official 324:406fd2029f23 3051 */
mbed_official 324:406fd2029f23 3052
mbed_official 324:406fd2029f23 3053 /** FTFA - Register Layout Typedef */
mbed_official 324:406fd2029f23 3054 typedef struct {
mbed_official 324:406fd2029f23 3055 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 324:406fd2029f23 3056 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 324:406fd2029f23 3057 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 324:406fd2029f23 3058 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 324:406fd2029f23 3059 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 324:406fd2029f23 3060 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 324:406fd2029f23 3061 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 324:406fd2029f23 3062 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 324:406fd2029f23 3063 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 324:406fd2029f23 3064 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 324:406fd2029f23 3065 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 324:406fd2029f23 3066 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 324:406fd2029f23 3067 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 324:406fd2029f23 3068 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 324:406fd2029f23 3069 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 324:406fd2029f23 3070 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 324:406fd2029f23 3071 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 324:406fd2029f23 3072 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 324:406fd2029f23 3073 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 324:406fd2029f23 3074 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 324:406fd2029f23 3075 uint8_t RESERVED_0[4];
mbed_official 324:406fd2029f23 3076 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
mbed_official 324:406fd2029f23 3077 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
mbed_official 324:406fd2029f23 3078 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
mbed_official 324:406fd2029f23 3079 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
mbed_official 324:406fd2029f23 3080 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
mbed_official 324:406fd2029f23 3081 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
mbed_official 324:406fd2029f23 3082 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
mbed_official 324:406fd2029f23 3083 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
mbed_official 324:406fd2029f23 3084 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
mbed_official 324:406fd2029f23 3085 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
mbed_official 324:406fd2029f23 3086 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
mbed_official 324:406fd2029f23 3087 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
mbed_official 324:406fd2029f23 3088 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
mbed_official 324:406fd2029f23 3089 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
mbed_official 324:406fd2029f23 3090 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
mbed_official 324:406fd2029f23 3091 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
mbed_official 324:406fd2029f23 3092 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
mbed_official 324:406fd2029f23 3093 uint8_t RESERVED_1[2];
mbed_official 324:406fd2029f23 3094 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
mbed_official 324:406fd2029f23 3095 } FTFA_Type, *FTFA_MemMapPtr;
mbed_official 324:406fd2029f23 3096
mbed_official 324:406fd2029f23 3097 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3098 -- FTFA - Register accessor macros
mbed_official 324:406fd2029f23 3099 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3100
mbed_official 324:406fd2029f23 3101 /*!
mbed_official 324:406fd2029f23 3102 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
mbed_official 324:406fd2029f23 3103 * @{
mbed_official 324:406fd2029f23 3104 */
mbed_official 324:406fd2029f23 3105
mbed_official 324:406fd2029f23 3106
mbed_official 324:406fd2029f23 3107 /* FTFA - Register accessors */
mbed_official 324:406fd2029f23 3108 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
mbed_official 324:406fd2029f23 3109 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
mbed_official 324:406fd2029f23 3110 #define FTFA_FSEC_REG(base) ((base)->FSEC)
mbed_official 324:406fd2029f23 3111 #define FTFA_FOPT_REG(base) ((base)->FOPT)
mbed_official 324:406fd2029f23 3112 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
mbed_official 324:406fd2029f23 3113 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
mbed_official 324:406fd2029f23 3114 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
mbed_official 324:406fd2029f23 3115 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
mbed_official 324:406fd2029f23 3116 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
mbed_official 324:406fd2029f23 3117 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
mbed_official 324:406fd2029f23 3118 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
mbed_official 324:406fd2029f23 3119 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
mbed_official 324:406fd2029f23 3120 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
mbed_official 324:406fd2029f23 3121 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
mbed_official 324:406fd2029f23 3122 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
mbed_official 324:406fd2029f23 3123 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
mbed_official 324:406fd2029f23 3124 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 324:406fd2029f23 3125 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 324:406fd2029f23 3126 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 324:406fd2029f23 3127 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 324:406fd2029f23 3128 #define FTFA_XACCH3_REG(base) ((base)->XACCH3)
mbed_official 324:406fd2029f23 3129 #define FTFA_XACCH2_REG(base) ((base)->XACCH2)
mbed_official 324:406fd2029f23 3130 #define FTFA_XACCH1_REG(base) ((base)->XACCH1)
mbed_official 324:406fd2029f23 3131 #define FTFA_XACCH0_REG(base) ((base)->XACCH0)
mbed_official 324:406fd2029f23 3132 #define FTFA_XACCL3_REG(base) ((base)->XACCL3)
mbed_official 324:406fd2029f23 3133 #define FTFA_XACCL2_REG(base) ((base)->XACCL2)
mbed_official 324:406fd2029f23 3134 #define FTFA_XACCL1_REG(base) ((base)->XACCL1)
mbed_official 324:406fd2029f23 3135 #define FTFA_XACCL0_REG(base) ((base)->XACCL0)
mbed_official 324:406fd2029f23 3136 #define FTFA_SACCH3_REG(base) ((base)->SACCH3)
mbed_official 324:406fd2029f23 3137 #define FTFA_SACCH2_REG(base) ((base)->SACCH2)
mbed_official 324:406fd2029f23 3138 #define FTFA_SACCH1_REG(base) ((base)->SACCH1)
mbed_official 324:406fd2029f23 3139 #define FTFA_SACCH0_REG(base) ((base)->SACCH0)
mbed_official 324:406fd2029f23 3140 #define FTFA_SACCL3_REG(base) ((base)->SACCL3)
mbed_official 324:406fd2029f23 3141 #define FTFA_SACCL2_REG(base) ((base)->SACCL2)
mbed_official 324:406fd2029f23 3142 #define FTFA_SACCL1_REG(base) ((base)->SACCL1)
mbed_official 324:406fd2029f23 3143 #define FTFA_SACCL0_REG(base) ((base)->SACCL0)
mbed_official 324:406fd2029f23 3144 #define FTFA_FACSS_REG(base) ((base)->FACSS)
mbed_official 324:406fd2029f23 3145 #define FTFA_FACSN_REG(base) ((base)->FACSN)
mbed_official 324:406fd2029f23 3146
mbed_official 324:406fd2029f23 3147 /*!
mbed_official 324:406fd2029f23 3148 * @}
mbed_official 324:406fd2029f23 3149 */ /* end of group FTFA_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 3150
mbed_official 324:406fd2029f23 3151
mbed_official 324:406fd2029f23 3152 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3153 -- FTFA Register Masks
mbed_official 324:406fd2029f23 3154 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3155
mbed_official 324:406fd2029f23 3156 /*!
mbed_official 324:406fd2029f23 3157 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mbed_official 324:406fd2029f23 3158 * @{
mbed_official 324:406fd2029f23 3159 */
mbed_official 324:406fd2029f23 3160
mbed_official 324:406fd2029f23 3161 /* FSTAT Bit Fields */
mbed_official 324:406fd2029f23 3162 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 324:406fd2029f23 3163 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mbed_official 324:406fd2029f23 3164 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mbed_official 324:406fd2029f23 3165 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mbed_official 324:406fd2029f23 3166 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mbed_official 324:406fd2029f23 3167 #define FTFA_FSTAT_ACCERR_SHIFT 5
mbed_official 324:406fd2029f23 3168 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 324:406fd2029f23 3169 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mbed_official 324:406fd2029f23 3170 #define FTFA_FSTAT_CCIF_MASK 0x80u
mbed_official 324:406fd2029f23 3171 #define FTFA_FSTAT_CCIF_SHIFT 7
mbed_official 324:406fd2029f23 3172 /* FCNFG Bit Fields */
mbed_official 324:406fd2029f23 3173 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 324:406fd2029f23 3174 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mbed_official 324:406fd2029f23 3175 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 324:406fd2029f23 3176 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mbed_official 324:406fd2029f23 3177 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 324:406fd2029f23 3178 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 324:406fd2029f23 3179 #define FTFA_FCNFG_CCIE_MASK 0x80u
mbed_official 324:406fd2029f23 3180 #define FTFA_FCNFG_CCIE_SHIFT 7
mbed_official 324:406fd2029f23 3181 /* FSEC Bit Fields */
mbed_official 324:406fd2029f23 3182 #define FTFA_FSEC_SEC_MASK 0x3u
mbed_official 324:406fd2029f23 3183 #define FTFA_FSEC_SEC_SHIFT 0
mbed_official 324:406fd2029f23 3184 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mbed_official 324:406fd2029f23 3185 #define FTFA_FSEC_FSLACC_MASK 0xCu
mbed_official 324:406fd2029f23 3186 #define FTFA_FSEC_FSLACC_SHIFT 2
mbed_official 324:406fd2029f23 3187 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mbed_official 324:406fd2029f23 3188 #define FTFA_FSEC_MEEN_MASK 0x30u
mbed_official 324:406fd2029f23 3189 #define FTFA_FSEC_MEEN_SHIFT 4
mbed_official 324:406fd2029f23 3190 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mbed_official 324:406fd2029f23 3191 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mbed_official 324:406fd2029f23 3192 #define FTFA_FSEC_KEYEN_SHIFT 6
mbed_official 324:406fd2029f23 3193 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mbed_official 324:406fd2029f23 3194 /* FOPT Bit Fields */
mbed_official 324:406fd2029f23 3195 #define FTFA_FOPT_OPT_MASK 0xFFu
mbed_official 324:406fd2029f23 3196 #define FTFA_FOPT_OPT_SHIFT 0
mbed_official 324:406fd2029f23 3197 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mbed_official 324:406fd2029f23 3198 /* FCCOB3 Bit Fields */
mbed_official 324:406fd2029f23 3199 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3200 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3201 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mbed_official 324:406fd2029f23 3202 /* FCCOB2 Bit Fields */
mbed_official 324:406fd2029f23 3203 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3204 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3205 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mbed_official 324:406fd2029f23 3206 /* FCCOB1 Bit Fields */
mbed_official 324:406fd2029f23 3207 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3208 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3209 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mbed_official 324:406fd2029f23 3210 /* FCCOB0 Bit Fields */
mbed_official 324:406fd2029f23 3211 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3212 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3213 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mbed_official 324:406fd2029f23 3214 /* FCCOB7 Bit Fields */
mbed_official 324:406fd2029f23 3215 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3216 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3217 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mbed_official 324:406fd2029f23 3218 /* FCCOB6 Bit Fields */
mbed_official 324:406fd2029f23 3219 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3220 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3221 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mbed_official 324:406fd2029f23 3222 /* FCCOB5 Bit Fields */
mbed_official 324:406fd2029f23 3223 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3224 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3225 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mbed_official 324:406fd2029f23 3226 /* FCCOB4 Bit Fields */
mbed_official 324:406fd2029f23 3227 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3228 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3229 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mbed_official 324:406fd2029f23 3230 /* FCCOBB Bit Fields */
mbed_official 324:406fd2029f23 3231 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3232 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3233 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mbed_official 324:406fd2029f23 3234 /* FCCOBA Bit Fields */
mbed_official 324:406fd2029f23 3235 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3236 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3237 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mbed_official 324:406fd2029f23 3238 /* FCCOB9 Bit Fields */
mbed_official 324:406fd2029f23 3239 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3240 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3241 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mbed_official 324:406fd2029f23 3242 /* FCCOB8 Bit Fields */
mbed_official 324:406fd2029f23 3243 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 324:406fd2029f23 3244 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mbed_official 324:406fd2029f23 3245 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mbed_official 324:406fd2029f23 3246 /* FPROT3 Bit Fields */
mbed_official 324:406fd2029f23 3247 #define FTFA_FPROT3_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 3248 #define FTFA_FPROT3_PROT_SHIFT 0
mbed_official 324:406fd2029f23 3249 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mbed_official 324:406fd2029f23 3250 /* FPROT2 Bit Fields */
mbed_official 324:406fd2029f23 3251 #define FTFA_FPROT2_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 3252 #define FTFA_FPROT2_PROT_SHIFT 0
mbed_official 324:406fd2029f23 3253 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mbed_official 324:406fd2029f23 3254 /* FPROT1 Bit Fields */
mbed_official 324:406fd2029f23 3255 #define FTFA_FPROT1_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 3256 #define FTFA_FPROT1_PROT_SHIFT 0
mbed_official 324:406fd2029f23 3257 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mbed_official 324:406fd2029f23 3258 /* FPROT0 Bit Fields */
mbed_official 324:406fd2029f23 3259 #define FTFA_FPROT0_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 3260 #define FTFA_FPROT0_PROT_SHIFT 0
mbed_official 324:406fd2029f23 3261 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mbed_official 324:406fd2029f23 3262 /* XACCH3 Bit Fields */
mbed_official 324:406fd2029f23 3263 #define FTFA_XACCH3_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3264 #define FTFA_XACCH3_XA_SHIFT 0
mbed_official 324:406fd2029f23 3265 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
mbed_official 324:406fd2029f23 3266 /* XACCH2 Bit Fields */
mbed_official 324:406fd2029f23 3267 #define FTFA_XACCH2_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3268 #define FTFA_XACCH2_XA_SHIFT 0
mbed_official 324:406fd2029f23 3269 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
mbed_official 324:406fd2029f23 3270 /* XACCH1 Bit Fields */
mbed_official 324:406fd2029f23 3271 #define FTFA_XACCH1_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3272 #define FTFA_XACCH1_XA_SHIFT 0
mbed_official 324:406fd2029f23 3273 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
mbed_official 324:406fd2029f23 3274 /* XACCH0 Bit Fields */
mbed_official 324:406fd2029f23 3275 #define FTFA_XACCH0_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3276 #define FTFA_XACCH0_XA_SHIFT 0
mbed_official 324:406fd2029f23 3277 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
mbed_official 324:406fd2029f23 3278 /* XACCL3 Bit Fields */
mbed_official 324:406fd2029f23 3279 #define FTFA_XACCL3_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3280 #define FTFA_XACCL3_XA_SHIFT 0
mbed_official 324:406fd2029f23 3281 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
mbed_official 324:406fd2029f23 3282 /* XACCL2 Bit Fields */
mbed_official 324:406fd2029f23 3283 #define FTFA_XACCL2_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3284 #define FTFA_XACCL2_XA_SHIFT 0
mbed_official 324:406fd2029f23 3285 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
mbed_official 324:406fd2029f23 3286 /* XACCL1 Bit Fields */
mbed_official 324:406fd2029f23 3287 #define FTFA_XACCL1_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3288 #define FTFA_XACCL1_XA_SHIFT 0
mbed_official 324:406fd2029f23 3289 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
mbed_official 324:406fd2029f23 3290 /* XACCL0 Bit Fields */
mbed_official 324:406fd2029f23 3291 #define FTFA_XACCL0_XA_MASK 0xFFu
mbed_official 324:406fd2029f23 3292 #define FTFA_XACCL0_XA_SHIFT 0
mbed_official 324:406fd2029f23 3293 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
mbed_official 324:406fd2029f23 3294 /* SACCH3 Bit Fields */
mbed_official 324:406fd2029f23 3295 #define FTFA_SACCH3_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3296 #define FTFA_SACCH3_SA_SHIFT 0
mbed_official 324:406fd2029f23 3297 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
mbed_official 324:406fd2029f23 3298 /* SACCH2 Bit Fields */
mbed_official 324:406fd2029f23 3299 #define FTFA_SACCH2_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3300 #define FTFA_SACCH2_SA_SHIFT 0
mbed_official 324:406fd2029f23 3301 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
mbed_official 324:406fd2029f23 3302 /* SACCH1 Bit Fields */
mbed_official 324:406fd2029f23 3303 #define FTFA_SACCH1_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3304 #define FTFA_SACCH1_SA_SHIFT 0
mbed_official 324:406fd2029f23 3305 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
mbed_official 324:406fd2029f23 3306 /* SACCH0 Bit Fields */
mbed_official 324:406fd2029f23 3307 #define FTFA_SACCH0_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3308 #define FTFA_SACCH0_SA_SHIFT 0
mbed_official 324:406fd2029f23 3309 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
mbed_official 324:406fd2029f23 3310 /* SACCL3 Bit Fields */
mbed_official 324:406fd2029f23 3311 #define FTFA_SACCL3_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3312 #define FTFA_SACCL3_SA_SHIFT 0
mbed_official 324:406fd2029f23 3313 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
mbed_official 324:406fd2029f23 3314 /* SACCL2 Bit Fields */
mbed_official 324:406fd2029f23 3315 #define FTFA_SACCL2_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3316 #define FTFA_SACCL2_SA_SHIFT 0
mbed_official 324:406fd2029f23 3317 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
mbed_official 324:406fd2029f23 3318 /* SACCL1 Bit Fields */
mbed_official 324:406fd2029f23 3319 #define FTFA_SACCL1_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3320 #define FTFA_SACCL1_SA_SHIFT 0
mbed_official 324:406fd2029f23 3321 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
mbed_official 324:406fd2029f23 3322 /* SACCL0 Bit Fields */
mbed_official 324:406fd2029f23 3323 #define FTFA_SACCL0_SA_MASK 0xFFu
mbed_official 324:406fd2029f23 3324 #define FTFA_SACCL0_SA_SHIFT 0
mbed_official 324:406fd2029f23 3325 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
mbed_official 324:406fd2029f23 3326 /* FACSS Bit Fields */
mbed_official 324:406fd2029f23 3327 #define FTFA_FACSS_SGSIZE_MASK 0xFFu
mbed_official 324:406fd2029f23 3328 #define FTFA_FACSS_SGSIZE_SHIFT 0
mbed_official 324:406fd2029f23 3329 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
mbed_official 324:406fd2029f23 3330 /* FACSN Bit Fields */
mbed_official 324:406fd2029f23 3331 #define FTFA_FACSN_NUMSG_MASK 0xFFu
mbed_official 324:406fd2029f23 3332 #define FTFA_FACSN_NUMSG_SHIFT 0
mbed_official 324:406fd2029f23 3333 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
mbed_official 324:406fd2029f23 3334
mbed_official 324:406fd2029f23 3335 /*!
mbed_official 324:406fd2029f23 3336 * @}
mbed_official 324:406fd2029f23 3337 */ /* end of group FTFA_Register_Masks */
mbed_official 324:406fd2029f23 3338
mbed_official 324:406fd2029f23 3339
mbed_official 324:406fd2029f23 3340 /* FTFA - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 3341 /** Peripheral FTFA base address */
mbed_official 324:406fd2029f23 3342 #define FTFA_BASE (0x40020000u)
mbed_official 324:406fd2029f23 3343 /** Peripheral FTFA base pointer */
mbed_official 324:406fd2029f23 3344 #define FTFA ((FTFA_Type *)FTFA_BASE)
mbed_official 324:406fd2029f23 3345 #define FTFA_BASE_PTR (FTFA)
mbed_official 324:406fd2029f23 3346 /** Array initializer of FTFA peripheral base addresses */
mbed_official 324:406fd2029f23 3347 #define FTFA_BASE_ADDRS { FTFA_BASE }
mbed_official 324:406fd2029f23 3348 /** Array initializer of FTFA peripheral base pointers */
mbed_official 324:406fd2029f23 3349 #define FTFA_BASE_PTRS { FTFA }
mbed_official 324:406fd2029f23 3350 /** Interrupt vectors for the FTFA peripheral type */
mbed_official 324:406fd2029f23 3351 #define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
mbed_official 324:406fd2029f23 3352 #define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
mbed_official 324:406fd2029f23 3353
mbed_official 324:406fd2029f23 3354 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3355 -- FTFA - Register accessor macros
mbed_official 324:406fd2029f23 3356 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3357
mbed_official 324:406fd2029f23 3358 /*!
mbed_official 324:406fd2029f23 3359 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
mbed_official 324:406fd2029f23 3360 * @{
mbed_official 324:406fd2029f23 3361 */
mbed_official 324:406fd2029f23 3362
mbed_official 324:406fd2029f23 3363
mbed_official 324:406fd2029f23 3364 /* FTFA - Register instance definitions */
mbed_official 324:406fd2029f23 3365 /* FTFA */
mbed_official 324:406fd2029f23 3366 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
mbed_official 324:406fd2029f23 3367 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
mbed_official 324:406fd2029f23 3368 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
mbed_official 324:406fd2029f23 3369 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
mbed_official 324:406fd2029f23 3370 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
mbed_official 324:406fd2029f23 3371 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
mbed_official 324:406fd2029f23 3372 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
mbed_official 324:406fd2029f23 3373 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
mbed_official 324:406fd2029f23 3374 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
mbed_official 324:406fd2029f23 3375 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
mbed_official 324:406fd2029f23 3376 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
mbed_official 324:406fd2029f23 3377 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
mbed_official 324:406fd2029f23 3378 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
mbed_official 324:406fd2029f23 3379 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
mbed_official 324:406fd2029f23 3380 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
mbed_official 324:406fd2029f23 3381 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
mbed_official 324:406fd2029f23 3382 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
mbed_official 324:406fd2029f23 3383 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
mbed_official 324:406fd2029f23 3384 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
mbed_official 324:406fd2029f23 3385 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
mbed_official 324:406fd2029f23 3386 #define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
mbed_official 324:406fd2029f23 3387 #define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
mbed_official 324:406fd2029f23 3388 #define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
mbed_official 324:406fd2029f23 3389 #define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
mbed_official 324:406fd2029f23 3390 #define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
mbed_official 324:406fd2029f23 3391 #define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
mbed_official 324:406fd2029f23 3392 #define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
mbed_official 324:406fd2029f23 3393 #define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
mbed_official 324:406fd2029f23 3394 #define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
mbed_official 324:406fd2029f23 3395 #define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
mbed_official 324:406fd2029f23 3396 #define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
mbed_official 324:406fd2029f23 3397 #define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
mbed_official 324:406fd2029f23 3398 #define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
mbed_official 324:406fd2029f23 3399 #define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
mbed_official 324:406fd2029f23 3400 #define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
mbed_official 324:406fd2029f23 3401 #define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
mbed_official 324:406fd2029f23 3402 #define FTFA_FACSS FTFA_FACSS_REG(FTFA)
mbed_official 324:406fd2029f23 3403 #define FTFA_FACSN FTFA_FACSN_REG(FTFA)
mbed_official 324:406fd2029f23 3404
mbed_official 324:406fd2029f23 3405 /*!
mbed_official 324:406fd2029f23 3406 * @}
mbed_official 324:406fd2029f23 3407 */ /* end of group FTFA_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 3408
mbed_official 324:406fd2029f23 3409
mbed_official 324:406fd2029f23 3410 /*!
mbed_official 324:406fd2029f23 3411 * @}
mbed_official 324:406fd2029f23 3412 */ /* end of group FTFA_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 3413
mbed_official 324:406fd2029f23 3414
mbed_official 324:406fd2029f23 3415 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3416 -- FTM Peripheral Access Layer
mbed_official 324:406fd2029f23 3417 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3418
mbed_official 324:406fd2029f23 3419 /*!
mbed_official 324:406fd2029f23 3420 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
mbed_official 324:406fd2029f23 3421 * @{
mbed_official 324:406fd2029f23 3422 */
mbed_official 324:406fd2029f23 3423
mbed_official 324:406fd2029f23 3424 /** FTM - Register Layout Typedef */
mbed_official 324:406fd2029f23 3425 typedef struct {
mbed_official 324:406fd2029f23 3426 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
mbed_official 324:406fd2029f23 3427 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 324:406fd2029f23 3428 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 324:406fd2029f23 3429 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 324:406fd2029f23 3430 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
mbed_official 324:406fd2029f23 3431 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 324:406fd2029f23 3432 } CONTROLS[8];
mbed_official 324:406fd2029f23 3433 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
mbed_official 324:406fd2029f23 3434 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
mbed_official 324:406fd2029f23 3435 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
mbed_official 324:406fd2029f23 3436 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
mbed_official 324:406fd2029f23 3437 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
mbed_official 324:406fd2029f23 3438 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
mbed_official 324:406fd2029f23 3439 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
mbed_official 324:406fd2029f23 3440 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
mbed_official 324:406fd2029f23 3441 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
mbed_official 324:406fd2029f23 3442 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
mbed_official 324:406fd2029f23 3443 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
mbed_official 324:406fd2029f23 3444 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
mbed_official 324:406fd2029f23 3445 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
mbed_official 324:406fd2029f23 3446 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
mbed_official 324:406fd2029f23 3447 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 324:406fd2029f23 3448 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
mbed_official 324:406fd2029f23 3449 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
mbed_official 324:406fd2029f23 3450 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
mbed_official 324:406fd2029f23 3451 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
mbed_official 324:406fd2029f23 3452 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
mbed_official 324:406fd2029f23 3453 } FTM_Type, *FTM_MemMapPtr;
mbed_official 324:406fd2029f23 3454
mbed_official 324:406fd2029f23 3455 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3456 -- FTM - Register accessor macros
mbed_official 324:406fd2029f23 3457 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3458
mbed_official 324:406fd2029f23 3459 /*!
mbed_official 324:406fd2029f23 3460 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
mbed_official 324:406fd2029f23 3461 * @{
mbed_official 324:406fd2029f23 3462 */
mbed_official 324:406fd2029f23 3463
mbed_official 324:406fd2029f23 3464
mbed_official 324:406fd2029f23 3465 /* FTM - Register accessors */
mbed_official 324:406fd2029f23 3466 #define FTM_SC_REG(base) ((base)->SC)
mbed_official 324:406fd2029f23 3467 #define FTM_CNT_REG(base) ((base)->CNT)
mbed_official 324:406fd2029f23 3468 #define FTM_MOD_REG(base) ((base)->MOD)
mbed_official 324:406fd2029f23 3469 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
mbed_official 324:406fd2029f23 3470 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
mbed_official 324:406fd2029f23 3471 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
mbed_official 324:406fd2029f23 3472 #define FTM_STATUS_REG(base) ((base)->STATUS)
mbed_official 324:406fd2029f23 3473 #define FTM_MODE_REG(base) ((base)->MODE)
mbed_official 324:406fd2029f23 3474 #define FTM_SYNC_REG(base) ((base)->SYNC)
mbed_official 324:406fd2029f23 3475 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
mbed_official 324:406fd2029f23 3476 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
mbed_official 324:406fd2029f23 3477 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
mbed_official 324:406fd2029f23 3478 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
mbed_official 324:406fd2029f23 3479 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
mbed_official 324:406fd2029f23 3480 #define FTM_POL_REG(base) ((base)->POL)
mbed_official 324:406fd2029f23 3481 #define FTM_FMS_REG(base) ((base)->FMS)
mbed_official 324:406fd2029f23 3482 #define FTM_FILTER_REG(base) ((base)->FILTER)
mbed_official 324:406fd2029f23 3483 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
mbed_official 324:406fd2029f23 3484 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
mbed_official 324:406fd2029f23 3485 #define FTM_CONF_REG(base) ((base)->CONF)
mbed_official 324:406fd2029f23 3486 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
mbed_official 324:406fd2029f23 3487 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
mbed_official 324:406fd2029f23 3488 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
mbed_official 324:406fd2029f23 3489 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
mbed_official 324:406fd2029f23 3490 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
mbed_official 324:406fd2029f23 3491
mbed_official 324:406fd2029f23 3492 /*!
mbed_official 324:406fd2029f23 3493 * @}
mbed_official 324:406fd2029f23 3494 */ /* end of group FTM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 3495
mbed_official 324:406fd2029f23 3496
mbed_official 324:406fd2029f23 3497 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3498 -- FTM Register Masks
mbed_official 324:406fd2029f23 3499 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3500
mbed_official 324:406fd2029f23 3501 /*!
mbed_official 324:406fd2029f23 3502 * @addtogroup FTM_Register_Masks FTM Register Masks
mbed_official 324:406fd2029f23 3503 * @{
mbed_official 324:406fd2029f23 3504 */
mbed_official 324:406fd2029f23 3505
mbed_official 324:406fd2029f23 3506 /* SC Bit Fields */
mbed_official 324:406fd2029f23 3507 #define FTM_SC_PS_MASK 0x7u
mbed_official 324:406fd2029f23 3508 #define FTM_SC_PS_SHIFT 0
mbed_official 324:406fd2029f23 3509 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
mbed_official 324:406fd2029f23 3510 #define FTM_SC_CLKS_MASK 0x18u
mbed_official 324:406fd2029f23 3511 #define FTM_SC_CLKS_SHIFT 3
mbed_official 324:406fd2029f23 3512 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
mbed_official 324:406fd2029f23 3513 #define FTM_SC_CPWMS_MASK 0x20u
mbed_official 324:406fd2029f23 3514 #define FTM_SC_CPWMS_SHIFT 5
mbed_official 324:406fd2029f23 3515 #define FTM_SC_TOIE_MASK 0x40u
mbed_official 324:406fd2029f23 3516 #define FTM_SC_TOIE_SHIFT 6
mbed_official 324:406fd2029f23 3517 #define FTM_SC_TOF_MASK 0x80u
mbed_official 324:406fd2029f23 3518 #define FTM_SC_TOF_SHIFT 7
mbed_official 324:406fd2029f23 3519 /* CNT Bit Fields */
mbed_official 324:406fd2029f23 3520 #define FTM_CNT_COUNT_MASK 0xFFFFu
mbed_official 324:406fd2029f23 3521 #define FTM_CNT_COUNT_SHIFT 0
mbed_official 324:406fd2029f23 3522 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
mbed_official 324:406fd2029f23 3523 /* MOD Bit Fields */
mbed_official 324:406fd2029f23 3524 #define FTM_MOD_MOD_MASK 0xFFFFu
mbed_official 324:406fd2029f23 3525 #define FTM_MOD_MOD_SHIFT 0
mbed_official 324:406fd2029f23 3526 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
mbed_official 324:406fd2029f23 3527 /* CnSC Bit Fields */
mbed_official 324:406fd2029f23 3528 #define FTM_CnSC_DMA_MASK 0x1u
mbed_official 324:406fd2029f23 3529 #define FTM_CnSC_DMA_SHIFT 0
mbed_official 324:406fd2029f23 3530 #define FTM_CnSC_ICRST_MASK 0x2u
mbed_official 324:406fd2029f23 3531 #define FTM_CnSC_ICRST_SHIFT 1
mbed_official 324:406fd2029f23 3532 #define FTM_CnSC_ELSA_MASK 0x4u
mbed_official 324:406fd2029f23 3533 #define FTM_CnSC_ELSA_SHIFT 2
mbed_official 324:406fd2029f23 3534 #define FTM_CnSC_ELSB_MASK 0x8u
mbed_official 324:406fd2029f23 3535 #define FTM_CnSC_ELSB_SHIFT 3
mbed_official 324:406fd2029f23 3536 #define FTM_CnSC_MSA_MASK 0x10u
mbed_official 324:406fd2029f23 3537 #define FTM_CnSC_MSA_SHIFT 4
mbed_official 324:406fd2029f23 3538 #define FTM_CnSC_MSB_MASK 0x20u
mbed_official 324:406fd2029f23 3539 #define FTM_CnSC_MSB_SHIFT 5
mbed_official 324:406fd2029f23 3540 #define FTM_CnSC_CHIE_MASK 0x40u
mbed_official 324:406fd2029f23 3541 #define FTM_CnSC_CHIE_SHIFT 6
mbed_official 324:406fd2029f23 3542 #define FTM_CnSC_CHF_MASK 0x80u
mbed_official 324:406fd2029f23 3543 #define FTM_CnSC_CHF_SHIFT 7
mbed_official 324:406fd2029f23 3544 /* CnV Bit Fields */
mbed_official 324:406fd2029f23 3545 #define FTM_CnV_VAL_MASK 0xFFFFu
mbed_official 324:406fd2029f23 3546 #define FTM_CnV_VAL_SHIFT 0
mbed_official 324:406fd2029f23 3547 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
mbed_official 324:406fd2029f23 3548 /* CNTIN Bit Fields */
mbed_official 324:406fd2029f23 3549 #define FTM_CNTIN_INIT_MASK 0xFFFFu
mbed_official 324:406fd2029f23 3550 #define FTM_CNTIN_INIT_SHIFT 0
mbed_official 324:406fd2029f23 3551 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
mbed_official 324:406fd2029f23 3552 /* STATUS Bit Fields */
mbed_official 324:406fd2029f23 3553 #define FTM_STATUS_CH0F_MASK 0x1u
mbed_official 324:406fd2029f23 3554 #define FTM_STATUS_CH0F_SHIFT 0
mbed_official 324:406fd2029f23 3555 #define FTM_STATUS_CH1F_MASK 0x2u
mbed_official 324:406fd2029f23 3556 #define FTM_STATUS_CH1F_SHIFT 1
mbed_official 324:406fd2029f23 3557 #define FTM_STATUS_CH2F_MASK 0x4u
mbed_official 324:406fd2029f23 3558 #define FTM_STATUS_CH2F_SHIFT 2
mbed_official 324:406fd2029f23 3559 #define FTM_STATUS_CH3F_MASK 0x8u
mbed_official 324:406fd2029f23 3560 #define FTM_STATUS_CH3F_SHIFT 3
mbed_official 324:406fd2029f23 3561 #define FTM_STATUS_CH4F_MASK 0x10u
mbed_official 324:406fd2029f23 3562 #define FTM_STATUS_CH4F_SHIFT 4
mbed_official 324:406fd2029f23 3563 #define FTM_STATUS_CH5F_MASK 0x20u
mbed_official 324:406fd2029f23 3564 #define FTM_STATUS_CH5F_SHIFT 5
mbed_official 324:406fd2029f23 3565 #define FTM_STATUS_CH6F_MASK 0x40u
mbed_official 324:406fd2029f23 3566 #define FTM_STATUS_CH6F_SHIFT 6
mbed_official 324:406fd2029f23 3567 #define FTM_STATUS_CH7F_MASK 0x80u
mbed_official 324:406fd2029f23 3568 #define FTM_STATUS_CH7F_SHIFT 7
mbed_official 324:406fd2029f23 3569 /* MODE Bit Fields */
mbed_official 324:406fd2029f23 3570 #define FTM_MODE_FTMEN_MASK 0x1u
mbed_official 324:406fd2029f23 3571 #define FTM_MODE_FTMEN_SHIFT 0
mbed_official 324:406fd2029f23 3572 #define FTM_MODE_INIT_MASK 0x2u
mbed_official 324:406fd2029f23 3573 #define FTM_MODE_INIT_SHIFT 1
mbed_official 324:406fd2029f23 3574 #define FTM_MODE_WPDIS_MASK 0x4u
mbed_official 324:406fd2029f23 3575 #define FTM_MODE_WPDIS_SHIFT 2
mbed_official 324:406fd2029f23 3576 #define FTM_MODE_PWMSYNC_MASK 0x8u
mbed_official 324:406fd2029f23 3577 #define FTM_MODE_PWMSYNC_SHIFT 3
mbed_official 324:406fd2029f23 3578 #define FTM_MODE_CAPTEST_MASK 0x10u
mbed_official 324:406fd2029f23 3579 #define FTM_MODE_CAPTEST_SHIFT 4
mbed_official 324:406fd2029f23 3580 #define FTM_MODE_FAULTM_MASK 0x60u
mbed_official 324:406fd2029f23 3581 #define FTM_MODE_FAULTM_SHIFT 5
mbed_official 324:406fd2029f23 3582 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
mbed_official 324:406fd2029f23 3583 #define FTM_MODE_FAULTIE_MASK 0x80u
mbed_official 324:406fd2029f23 3584 #define FTM_MODE_FAULTIE_SHIFT 7
mbed_official 324:406fd2029f23 3585 /* SYNC Bit Fields */
mbed_official 324:406fd2029f23 3586 #define FTM_SYNC_CNTMIN_MASK 0x1u
mbed_official 324:406fd2029f23 3587 #define FTM_SYNC_CNTMIN_SHIFT 0
mbed_official 324:406fd2029f23 3588 #define FTM_SYNC_CNTMAX_MASK 0x2u
mbed_official 324:406fd2029f23 3589 #define FTM_SYNC_CNTMAX_SHIFT 1
mbed_official 324:406fd2029f23 3590 #define FTM_SYNC_REINIT_MASK 0x4u
mbed_official 324:406fd2029f23 3591 #define FTM_SYNC_REINIT_SHIFT 2
mbed_official 324:406fd2029f23 3592 #define FTM_SYNC_SYNCHOM_MASK 0x8u
mbed_official 324:406fd2029f23 3593 #define FTM_SYNC_SYNCHOM_SHIFT 3
mbed_official 324:406fd2029f23 3594 #define FTM_SYNC_TRIG0_MASK 0x10u
mbed_official 324:406fd2029f23 3595 #define FTM_SYNC_TRIG0_SHIFT 4
mbed_official 324:406fd2029f23 3596 #define FTM_SYNC_TRIG1_MASK 0x20u
mbed_official 324:406fd2029f23 3597 #define FTM_SYNC_TRIG1_SHIFT 5
mbed_official 324:406fd2029f23 3598 #define FTM_SYNC_TRIG2_MASK 0x40u
mbed_official 324:406fd2029f23 3599 #define FTM_SYNC_TRIG2_SHIFT 6
mbed_official 324:406fd2029f23 3600 #define FTM_SYNC_SWSYNC_MASK 0x80u
mbed_official 324:406fd2029f23 3601 #define FTM_SYNC_SWSYNC_SHIFT 7
mbed_official 324:406fd2029f23 3602 /* OUTINIT Bit Fields */
mbed_official 324:406fd2029f23 3603 #define FTM_OUTINIT_CH0OI_MASK 0x1u
mbed_official 324:406fd2029f23 3604 #define FTM_OUTINIT_CH0OI_SHIFT 0
mbed_official 324:406fd2029f23 3605 #define FTM_OUTINIT_CH1OI_MASK 0x2u
mbed_official 324:406fd2029f23 3606 #define FTM_OUTINIT_CH1OI_SHIFT 1
mbed_official 324:406fd2029f23 3607 #define FTM_OUTINIT_CH2OI_MASK 0x4u
mbed_official 324:406fd2029f23 3608 #define FTM_OUTINIT_CH2OI_SHIFT 2
mbed_official 324:406fd2029f23 3609 #define FTM_OUTINIT_CH3OI_MASK 0x8u
mbed_official 324:406fd2029f23 3610 #define FTM_OUTINIT_CH3OI_SHIFT 3
mbed_official 324:406fd2029f23 3611 #define FTM_OUTINIT_CH4OI_MASK 0x10u
mbed_official 324:406fd2029f23 3612 #define FTM_OUTINIT_CH4OI_SHIFT 4
mbed_official 324:406fd2029f23 3613 #define FTM_OUTINIT_CH5OI_MASK 0x20u
mbed_official 324:406fd2029f23 3614 #define FTM_OUTINIT_CH5OI_SHIFT 5
mbed_official 324:406fd2029f23 3615 #define FTM_OUTINIT_CH6OI_MASK 0x40u
mbed_official 324:406fd2029f23 3616 #define FTM_OUTINIT_CH6OI_SHIFT 6
mbed_official 324:406fd2029f23 3617 #define FTM_OUTINIT_CH7OI_MASK 0x80u
mbed_official 324:406fd2029f23 3618 #define FTM_OUTINIT_CH7OI_SHIFT 7
mbed_official 324:406fd2029f23 3619 /* OUTMASK Bit Fields */
mbed_official 324:406fd2029f23 3620 #define FTM_OUTMASK_CH0OM_MASK 0x1u
mbed_official 324:406fd2029f23 3621 #define FTM_OUTMASK_CH0OM_SHIFT 0
mbed_official 324:406fd2029f23 3622 #define FTM_OUTMASK_CH1OM_MASK 0x2u
mbed_official 324:406fd2029f23 3623 #define FTM_OUTMASK_CH1OM_SHIFT 1
mbed_official 324:406fd2029f23 3624 #define FTM_OUTMASK_CH2OM_MASK 0x4u
mbed_official 324:406fd2029f23 3625 #define FTM_OUTMASK_CH2OM_SHIFT 2
mbed_official 324:406fd2029f23 3626 #define FTM_OUTMASK_CH3OM_MASK 0x8u
mbed_official 324:406fd2029f23 3627 #define FTM_OUTMASK_CH3OM_SHIFT 3
mbed_official 324:406fd2029f23 3628 #define FTM_OUTMASK_CH4OM_MASK 0x10u
mbed_official 324:406fd2029f23 3629 #define FTM_OUTMASK_CH4OM_SHIFT 4
mbed_official 324:406fd2029f23 3630 #define FTM_OUTMASK_CH5OM_MASK 0x20u
mbed_official 324:406fd2029f23 3631 #define FTM_OUTMASK_CH5OM_SHIFT 5
mbed_official 324:406fd2029f23 3632 #define FTM_OUTMASK_CH6OM_MASK 0x40u
mbed_official 324:406fd2029f23 3633 #define FTM_OUTMASK_CH6OM_SHIFT 6
mbed_official 324:406fd2029f23 3634 #define FTM_OUTMASK_CH7OM_MASK 0x80u
mbed_official 324:406fd2029f23 3635 #define FTM_OUTMASK_CH7OM_SHIFT 7
mbed_official 324:406fd2029f23 3636 /* COMBINE Bit Fields */
mbed_official 324:406fd2029f23 3637 #define FTM_COMBINE_COMBINE0_MASK 0x1u
mbed_official 324:406fd2029f23 3638 #define FTM_COMBINE_COMBINE0_SHIFT 0
mbed_official 324:406fd2029f23 3639 #define FTM_COMBINE_COMP0_MASK 0x2u
mbed_official 324:406fd2029f23 3640 #define FTM_COMBINE_COMP0_SHIFT 1
mbed_official 324:406fd2029f23 3641 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
mbed_official 324:406fd2029f23 3642 #define FTM_COMBINE_DECAPEN0_SHIFT 2
mbed_official 324:406fd2029f23 3643 #define FTM_COMBINE_DECAP0_MASK 0x8u
mbed_official 324:406fd2029f23 3644 #define FTM_COMBINE_DECAP0_SHIFT 3
mbed_official 324:406fd2029f23 3645 #define FTM_COMBINE_DTEN0_MASK 0x10u
mbed_official 324:406fd2029f23 3646 #define FTM_COMBINE_DTEN0_SHIFT 4
mbed_official 324:406fd2029f23 3647 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
mbed_official 324:406fd2029f23 3648 #define FTM_COMBINE_SYNCEN0_SHIFT 5
mbed_official 324:406fd2029f23 3649 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
mbed_official 324:406fd2029f23 3650 #define FTM_COMBINE_FAULTEN0_SHIFT 6
mbed_official 324:406fd2029f23 3651 #define FTM_COMBINE_COMBINE1_MASK 0x100u
mbed_official 324:406fd2029f23 3652 #define FTM_COMBINE_COMBINE1_SHIFT 8
mbed_official 324:406fd2029f23 3653 #define FTM_COMBINE_COMP1_MASK 0x200u
mbed_official 324:406fd2029f23 3654 #define FTM_COMBINE_COMP1_SHIFT 9
mbed_official 324:406fd2029f23 3655 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
mbed_official 324:406fd2029f23 3656 #define FTM_COMBINE_DECAPEN1_SHIFT 10
mbed_official 324:406fd2029f23 3657 #define FTM_COMBINE_DECAP1_MASK 0x800u
mbed_official 324:406fd2029f23 3658 #define FTM_COMBINE_DECAP1_SHIFT 11
mbed_official 324:406fd2029f23 3659 #define FTM_COMBINE_DTEN1_MASK 0x1000u
mbed_official 324:406fd2029f23 3660 #define FTM_COMBINE_DTEN1_SHIFT 12
mbed_official 324:406fd2029f23 3661 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
mbed_official 324:406fd2029f23 3662 #define FTM_COMBINE_SYNCEN1_SHIFT 13
mbed_official 324:406fd2029f23 3663 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
mbed_official 324:406fd2029f23 3664 #define FTM_COMBINE_FAULTEN1_SHIFT 14
mbed_official 324:406fd2029f23 3665 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
mbed_official 324:406fd2029f23 3666 #define FTM_COMBINE_COMBINE2_SHIFT 16
mbed_official 324:406fd2029f23 3667 #define FTM_COMBINE_COMP2_MASK 0x20000u
mbed_official 324:406fd2029f23 3668 #define FTM_COMBINE_COMP2_SHIFT 17
mbed_official 324:406fd2029f23 3669 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
mbed_official 324:406fd2029f23 3670 #define FTM_COMBINE_DECAPEN2_SHIFT 18
mbed_official 324:406fd2029f23 3671 #define FTM_COMBINE_DECAP2_MASK 0x80000u
mbed_official 324:406fd2029f23 3672 #define FTM_COMBINE_DECAP2_SHIFT 19
mbed_official 324:406fd2029f23 3673 #define FTM_COMBINE_DTEN2_MASK 0x100000u
mbed_official 324:406fd2029f23 3674 #define FTM_COMBINE_DTEN2_SHIFT 20
mbed_official 324:406fd2029f23 3675 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
mbed_official 324:406fd2029f23 3676 #define FTM_COMBINE_SYNCEN2_SHIFT 21
mbed_official 324:406fd2029f23 3677 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
mbed_official 324:406fd2029f23 3678 #define FTM_COMBINE_FAULTEN2_SHIFT 22
mbed_official 324:406fd2029f23 3679 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
mbed_official 324:406fd2029f23 3680 #define FTM_COMBINE_COMBINE3_SHIFT 24
mbed_official 324:406fd2029f23 3681 #define FTM_COMBINE_COMP3_MASK 0x2000000u
mbed_official 324:406fd2029f23 3682 #define FTM_COMBINE_COMP3_SHIFT 25
mbed_official 324:406fd2029f23 3683 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
mbed_official 324:406fd2029f23 3684 #define FTM_COMBINE_DECAPEN3_SHIFT 26
mbed_official 324:406fd2029f23 3685 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
mbed_official 324:406fd2029f23 3686 #define FTM_COMBINE_DECAP3_SHIFT 27
mbed_official 324:406fd2029f23 3687 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
mbed_official 324:406fd2029f23 3688 #define FTM_COMBINE_DTEN3_SHIFT 28
mbed_official 324:406fd2029f23 3689 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
mbed_official 324:406fd2029f23 3690 #define FTM_COMBINE_SYNCEN3_SHIFT 29
mbed_official 324:406fd2029f23 3691 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
mbed_official 324:406fd2029f23 3692 #define FTM_COMBINE_FAULTEN3_SHIFT 30
mbed_official 324:406fd2029f23 3693 /* DEADTIME Bit Fields */
mbed_official 324:406fd2029f23 3694 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
mbed_official 324:406fd2029f23 3695 #define FTM_DEADTIME_DTVAL_SHIFT 0
mbed_official 324:406fd2029f23 3696 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
mbed_official 324:406fd2029f23 3697 #define FTM_DEADTIME_DTPS_MASK 0xC0u
mbed_official 324:406fd2029f23 3698 #define FTM_DEADTIME_DTPS_SHIFT 6
mbed_official 324:406fd2029f23 3699 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
mbed_official 324:406fd2029f23 3700 /* EXTTRIG Bit Fields */
mbed_official 324:406fd2029f23 3701 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
mbed_official 324:406fd2029f23 3702 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
mbed_official 324:406fd2029f23 3703 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
mbed_official 324:406fd2029f23 3704 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
mbed_official 324:406fd2029f23 3705 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
mbed_official 324:406fd2029f23 3706 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
mbed_official 324:406fd2029f23 3707 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
mbed_official 324:406fd2029f23 3708 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
mbed_official 324:406fd2029f23 3709 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
mbed_official 324:406fd2029f23 3710 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
mbed_official 324:406fd2029f23 3711 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
mbed_official 324:406fd2029f23 3712 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
mbed_official 324:406fd2029f23 3713 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
mbed_official 324:406fd2029f23 3714 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
mbed_official 324:406fd2029f23 3715 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
mbed_official 324:406fd2029f23 3716 #define FTM_EXTTRIG_TRIGF_SHIFT 7
mbed_official 324:406fd2029f23 3717 /* POL Bit Fields */
mbed_official 324:406fd2029f23 3718 #define FTM_POL_POL0_MASK 0x1u
mbed_official 324:406fd2029f23 3719 #define FTM_POL_POL0_SHIFT 0
mbed_official 324:406fd2029f23 3720 #define FTM_POL_POL1_MASK 0x2u
mbed_official 324:406fd2029f23 3721 #define FTM_POL_POL1_SHIFT 1
mbed_official 324:406fd2029f23 3722 #define FTM_POL_POL2_MASK 0x4u
mbed_official 324:406fd2029f23 3723 #define FTM_POL_POL2_SHIFT 2
mbed_official 324:406fd2029f23 3724 #define FTM_POL_POL3_MASK 0x8u
mbed_official 324:406fd2029f23 3725 #define FTM_POL_POL3_SHIFT 3
mbed_official 324:406fd2029f23 3726 #define FTM_POL_POL4_MASK 0x10u
mbed_official 324:406fd2029f23 3727 #define FTM_POL_POL4_SHIFT 4
mbed_official 324:406fd2029f23 3728 #define FTM_POL_POL5_MASK 0x20u
mbed_official 324:406fd2029f23 3729 #define FTM_POL_POL5_SHIFT 5
mbed_official 324:406fd2029f23 3730 #define FTM_POL_POL6_MASK 0x40u
mbed_official 324:406fd2029f23 3731 #define FTM_POL_POL6_SHIFT 6
mbed_official 324:406fd2029f23 3732 #define FTM_POL_POL7_MASK 0x80u
mbed_official 324:406fd2029f23 3733 #define FTM_POL_POL7_SHIFT 7
mbed_official 324:406fd2029f23 3734 /* FMS Bit Fields */
mbed_official 324:406fd2029f23 3735 #define FTM_FMS_FAULTF0_MASK 0x1u
mbed_official 324:406fd2029f23 3736 #define FTM_FMS_FAULTF0_SHIFT 0
mbed_official 324:406fd2029f23 3737 #define FTM_FMS_FAULTF1_MASK 0x2u
mbed_official 324:406fd2029f23 3738 #define FTM_FMS_FAULTF1_SHIFT 1
mbed_official 324:406fd2029f23 3739 #define FTM_FMS_FAULTF2_MASK 0x4u
mbed_official 324:406fd2029f23 3740 #define FTM_FMS_FAULTF2_SHIFT 2
mbed_official 324:406fd2029f23 3741 #define FTM_FMS_FAULTF3_MASK 0x8u
mbed_official 324:406fd2029f23 3742 #define FTM_FMS_FAULTF3_SHIFT 3
mbed_official 324:406fd2029f23 3743 #define FTM_FMS_FAULTIN_MASK 0x20u
mbed_official 324:406fd2029f23 3744 #define FTM_FMS_FAULTIN_SHIFT 5
mbed_official 324:406fd2029f23 3745 #define FTM_FMS_WPEN_MASK 0x40u
mbed_official 324:406fd2029f23 3746 #define FTM_FMS_WPEN_SHIFT 6
mbed_official 324:406fd2029f23 3747 #define FTM_FMS_FAULTF_MASK 0x80u
mbed_official 324:406fd2029f23 3748 #define FTM_FMS_FAULTF_SHIFT 7
mbed_official 324:406fd2029f23 3749 /* FILTER Bit Fields */
mbed_official 324:406fd2029f23 3750 #define FTM_FILTER_CH0FVAL_MASK 0xFu
mbed_official 324:406fd2029f23 3751 #define FTM_FILTER_CH0FVAL_SHIFT 0
mbed_official 324:406fd2029f23 3752 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
mbed_official 324:406fd2029f23 3753 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
mbed_official 324:406fd2029f23 3754 #define FTM_FILTER_CH1FVAL_SHIFT 4
mbed_official 324:406fd2029f23 3755 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
mbed_official 324:406fd2029f23 3756 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
mbed_official 324:406fd2029f23 3757 #define FTM_FILTER_CH2FVAL_SHIFT 8
mbed_official 324:406fd2029f23 3758 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
mbed_official 324:406fd2029f23 3759 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
mbed_official 324:406fd2029f23 3760 #define FTM_FILTER_CH3FVAL_SHIFT 12
mbed_official 324:406fd2029f23 3761 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
mbed_official 324:406fd2029f23 3762 /* FLTCTRL Bit Fields */
mbed_official 324:406fd2029f23 3763 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
mbed_official 324:406fd2029f23 3764 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
mbed_official 324:406fd2029f23 3765 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
mbed_official 324:406fd2029f23 3766 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
mbed_official 324:406fd2029f23 3767 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
mbed_official 324:406fd2029f23 3768 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
mbed_official 324:406fd2029f23 3769 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
mbed_official 324:406fd2029f23 3770 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
mbed_official 324:406fd2029f23 3771 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
mbed_official 324:406fd2029f23 3772 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
mbed_official 324:406fd2029f23 3773 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
mbed_official 324:406fd2029f23 3774 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
mbed_official 324:406fd2029f23 3775 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
mbed_official 324:406fd2029f23 3776 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
mbed_official 324:406fd2029f23 3777 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
mbed_official 324:406fd2029f23 3778 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
mbed_official 324:406fd2029f23 3779 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
mbed_official 324:406fd2029f23 3780 #define FTM_FLTCTRL_FFVAL_SHIFT 8
mbed_official 324:406fd2029f23 3781 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
mbed_official 324:406fd2029f23 3782 /* QDCTRL Bit Fields */
mbed_official 324:406fd2029f23 3783 #define FTM_QDCTRL_QUADEN_MASK 0x1u
mbed_official 324:406fd2029f23 3784 #define FTM_QDCTRL_QUADEN_SHIFT 0
mbed_official 324:406fd2029f23 3785 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
mbed_official 324:406fd2029f23 3786 #define FTM_QDCTRL_TOFDIR_SHIFT 1
mbed_official 324:406fd2029f23 3787 #define FTM_QDCTRL_QUADIR_MASK 0x4u
mbed_official 324:406fd2029f23 3788 #define FTM_QDCTRL_QUADIR_SHIFT 2
mbed_official 324:406fd2029f23 3789 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
mbed_official 324:406fd2029f23 3790 #define FTM_QDCTRL_QUADMODE_SHIFT 3
mbed_official 324:406fd2029f23 3791 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
mbed_official 324:406fd2029f23 3792 #define FTM_QDCTRL_PHBPOL_SHIFT 4
mbed_official 324:406fd2029f23 3793 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
mbed_official 324:406fd2029f23 3794 #define FTM_QDCTRL_PHAPOL_SHIFT 5
mbed_official 324:406fd2029f23 3795 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
mbed_official 324:406fd2029f23 3796 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
mbed_official 324:406fd2029f23 3797 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
mbed_official 324:406fd2029f23 3798 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
mbed_official 324:406fd2029f23 3799 /* CONF Bit Fields */
mbed_official 324:406fd2029f23 3800 #define FTM_CONF_NUMTOF_MASK 0x1Fu
mbed_official 324:406fd2029f23 3801 #define FTM_CONF_NUMTOF_SHIFT 0
mbed_official 324:406fd2029f23 3802 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
mbed_official 324:406fd2029f23 3803 #define FTM_CONF_BDMMODE_MASK 0xC0u
mbed_official 324:406fd2029f23 3804 #define FTM_CONF_BDMMODE_SHIFT 6
mbed_official 324:406fd2029f23 3805 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
mbed_official 324:406fd2029f23 3806 #define FTM_CONF_GTBEEN_MASK 0x200u
mbed_official 324:406fd2029f23 3807 #define FTM_CONF_GTBEEN_SHIFT 9
mbed_official 324:406fd2029f23 3808 #define FTM_CONF_GTBEOUT_MASK 0x400u
mbed_official 324:406fd2029f23 3809 #define FTM_CONF_GTBEOUT_SHIFT 10
mbed_official 324:406fd2029f23 3810 /* FLTPOL Bit Fields */
mbed_official 324:406fd2029f23 3811 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
mbed_official 324:406fd2029f23 3812 #define FTM_FLTPOL_FLT0POL_SHIFT 0
mbed_official 324:406fd2029f23 3813 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
mbed_official 324:406fd2029f23 3814 #define FTM_FLTPOL_FLT1POL_SHIFT 1
mbed_official 324:406fd2029f23 3815 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
mbed_official 324:406fd2029f23 3816 #define FTM_FLTPOL_FLT2POL_SHIFT 2
mbed_official 324:406fd2029f23 3817 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
mbed_official 324:406fd2029f23 3818 #define FTM_FLTPOL_FLT3POL_SHIFT 3
mbed_official 324:406fd2029f23 3819 /* SYNCONF Bit Fields */
mbed_official 324:406fd2029f23 3820 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
mbed_official 324:406fd2029f23 3821 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
mbed_official 324:406fd2029f23 3822 #define FTM_SYNCONF_CNTINC_MASK 0x4u
mbed_official 324:406fd2029f23 3823 #define FTM_SYNCONF_CNTINC_SHIFT 2
mbed_official 324:406fd2029f23 3824 #define FTM_SYNCONF_INVC_MASK 0x10u
mbed_official 324:406fd2029f23 3825 #define FTM_SYNCONF_INVC_SHIFT 4
mbed_official 324:406fd2029f23 3826 #define FTM_SYNCONF_SWOC_MASK 0x20u
mbed_official 324:406fd2029f23 3827 #define FTM_SYNCONF_SWOC_SHIFT 5
mbed_official 324:406fd2029f23 3828 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
mbed_official 324:406fd2029f23 3829 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
mbed_official 324:406fd2029f23 3830 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
mbed_official 324:406fd2029f23 3831 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
mbed_official 324:406fd2029f23 3832 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
mbed_official 324:406fd2029f23 3833 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
mbed_official 324:406fd2029f23 3834 #define FTM_SYNCONF_SWOM_MASK 0x400u
mbed_official 324:406fd2029f23 3835 #define FTM_SYNCONF_SWOM_SHIFT 10
mbed_official 324:406fd2029f23 3836 #define FTM_SYNCONF_SWINVC_MASK 0x800u
mbed_official 324:406fd2029f23 3837 #define FTM_SYNCONF_SWINVC_SHIFT 11
mbed_official 324:406fd2029f23 3838 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
mbed_official 324:406fd2029f23 3839 #define FTM_SYNCONF_SWSOC_SHIFT 12
mbed_official 324:406fd2029f23 3840 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
mbed_official 324:406fd2029f23 3841 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
mbed_official 324:406fd2029f23 3842 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
mbed_official 324:406fd2029f23 3843 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
mbed_official 324:406fd2029f23 3844 #define FTM_SYNCONF_HWOM_MASK 0x40000u
mbed_official 324:406fd2029f23 3845 #define FTM_SYNCONF_HWOM_SHIFT 18
mbed_official 324:406fd2029f23 3846 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
mbed_official 324:406fd2029f23 3847 #define FTM_SYNCONF_HWINVC_SHIFT 19
mbed_official 324:406fd2029f23 3848 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
mbed_official 324:406fd2029f23 3849 #define FTM_SYNCONF_HWSOC_SHIFT 20
mbed_official 324:406fd2029f23 3850 /* INVCTRL Bit Fields */
mbed_official 324:406fd2029f23 3851 #define FTM_INVCTRL_INV0EN_MASK 0x1u
mbed_official 324:406fd2029f23 3852 #define FTM_INVCTRL_INV0EN_SHIFT 0
mbed_official 324:406fd2029f23 3853 #define FTM_INVCTRL_INV1EN_MASK 0x2u
mbed_official 324:406fd2029f23 3854 #define FTM_INVCTRL_INV1EN_SHIFT 1
mbed_official 324:406fd2029f23 3855 #define FTM_INVCTRL_INV2EN_MASK 0x4u
mbed_official 324:406fd2029f23 3856 #define FTM_INVCTRL_INV2EN_SHIFT 2
mbed_official 324:406fd2029f23 3857 #define FTM_INVCTRL_INV3EN_MASK 0x8u
mbed_official 324:406fd2029f23 3858 #define FTM_INVCTRL_INV3EN_SHIFT 3
mbed_official 324:406fd2029f23 3859 /* SWOCTRL Bit Fields */
mbed_official 324:406fd2029f23 3860 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
mbed_official 324:406fd2029f23 3861 #define FTM_SWOCTRL_CH0OC_SHIFT 0
mbed_official 324:406fd2029f23 3862 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
mbed_official 324:406fd2029f23 3863 #define FTM_SWOCTRL_CH1OC_SHIFT 1
mbed_official 324:406fd2029f23 3864 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
mbed_official 324:406fd2029f23 3865 #define FTM_SWOCTRL_CH2OC_SHIFT 2
mbed_official 324:406fd2029f23 3866 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
mbed_official 324:406fd2029f23 3867 #define FTM_SWOCTRL_CH3OC_SHIFT 3
mbed_official 324:406fd2029f23 3868 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
mbed_official 324:406fd2029f23 3869 #define FTM_SWOCTRL_CH4OC_SHIFT 4
mbed_official 324:406fd2029f23 3870 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
mbed_official 324:406fd2029f23 3871 #define FTM_SWOCTRL_CH5OC_SHIFT 5
mbed_official 324:406fd2029f23 3872 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
mbed_official 324:406fd2029f23 3873 #define FTM_SWOCTRL_CH6OC_SHIFT 6
mbed_official 324:406fd2029f23 3874 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
mbed_official 324:406fd2029f23 3875 #define FTM_SWOCTRL_CH7OC_SHIFT 7
mbed_official 324:406fd2029f23 3876 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
mbed_official 324:406fd2029f23 3877 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
mbed_official 324:406fd2029f23 3878 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
mbed_official 324:406fd2029f23 3879 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
mbed_official 324:406fd2029f23 3880 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
mbed_official 324:406fd2029f23 3881 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
mbed_official 324:406fd2029f23 3882 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
mbed_official 324:406fd2029f23 3883 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
mbed_official 324:406fd2029f23 3884 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
mbed_official 324:406fd2029f23 3885 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
mbed_official 324:406fd2029f23 3886 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
mbed_official 324:406fd2029f23 3887 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
mbed_official 324:406fd2029f23 3888 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
mbed_official 324:406fd2029f23 3889 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
mbed_official 324:406fd2029f23 3890 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
mbed_official 324:406fd2029f23 3891 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
mbed_official 324:406fd2029f23 3892 /* PWMLOAD Bit Fields */
mbed_official 324:406fd2029f23 3893 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
mbed_official 324:406fd2029f23 3894 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
mbed_official 324:406fd2029f23 3895 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
mbed_official 324:406fd2029f23 3896 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
mbed_official 324:406fd2029f23 3897 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
mbed_official 324:406fd2029f23 3898 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
mbed_official 324:406fd2029f23 3899 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
mbed_official 324:406fd2029f23 3900 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
mbed_official 324:406fd2029f23 3901 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
mbed_official 324:406fd2029f23 3902 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
mbed_official 324:406fd2029f23 3903 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
mbed_official 324:406fd2029f23 3904 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
mbed_official 324:406fd2029f23 3905 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
mbed_official 324:406fd2029f23 3906 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
mbed_official 324:406fd2029f23 3907 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
mbed_official 324:406fd2029f23 3908 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
mbed_official 324:406fd2029f23 3909 #define FTM_PWMLOAD_LDOK_MASK 0x200u
mbed_official 324:406fd2029f23 3910 #define FTM_PWMLOAD_LDOK_SHIFT 9
mbed_official 324:406fd2029f23 3911
mbed_official 324:406fd2029f23 3912 /*!
mbed_official 324:406fd2029f23 3913 * @}
mbed_official 324:406fd2029f23 3914 */ /* end of group FTM_Register_Masks */
mbed_official 324:406fd2029f23 3915
mbed_official 324:406fd2029f23 3916
mbed_official 324:406fd2029f23 3917 /* FTM - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 3918 /** Peripheral FTM0 base address */
mbed_official 324:406fd2029f23 3919 #define FTM0_BASE (0x40038000u)
mbed_official 324:406fd2029f23 3920 /** Peripheral FTM0 base pointer */
mbed_official 324:406fd2029f23 3921 #define FTM0 ((FTM_Type *)FTM0_BASE)
mbed_official 324:406fd2029f23 3922 #define FTM0_BASE_PTR (FTM0)
mbed_official 324:406fd2029f23 3923 /** Peripheral FTM1 base address */
mbed_official 324:406fd2029f23 3924 #define FTM1_BASE (0x40039000u)
mbed_official 324:406fd2029f23 3925 /** Peripheral FTM1 base pointer */
mbed_official 324:406fd2029f23 3926 #define FTM1 ((FTM_Type *)FTM1_BASE)
mbed_official 324:406fd2029f23 3927 #define FTM1_BASE_PTR (FTM1)
mbed_official 324:406fd2029f23 3928 /** Peripheral FTM2 base address */
mbed_official 324:406fd2029f23 3929 #define FTM2_BASE (0x4003A000u)
mbed_official 324:406fd2029f23 3930 /** Peripheral FTM2 base pointer */
mbed_official 324:406fd2029f23 3931 #define FTM2 ((FTM_Type *)FTM2_BASE)
mbed_official 324:406fd2029f23 3932 #define FTM2_BASE_PTR (FTM2)
mbed_official 324:406fd2029f23 3933 /** Peripheral FTM3 base address */
mbed_official 324:406fd2029f23 3934 #define FTM3_BASE (0x40026000u)
mbed_official 324:406fd2029f23 3935 /** Peripheral FTM3 base pointer */
mbed_official 324:406fd2029f23 3936 #define FTM3 ((FTM_Type *)FTM3_BASE)
mbed_official 324:406fd2029f23 3937 #define FTM3_BASE_PTR (FTM3)
mbed_official 324:406fd2029f23 3938 /** Array initializer of FTM peripheral base addresses */
mbed_official 324:406fd2029f23 3939 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
mbed_official 324:406fd2029f23 3940 /** Array initializer of FTM peripheral base pointers */
mbed_official 324:406fd2029f23 3941 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
mbed_official 324:406fd2029f23 3942 /** Interrupt vectors for the FTM peripheral type */
mbed_official 324:406fd2029f23 3943 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
mbed_official 324:406fd2029f23 3944
mbed_official 324:406fd2029f23 3945 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 3946 -- FTM - Register accessor macros
mbed_official 324:406fd2029f23 3947 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 3948
mbed_official 324:406fd2029f23 3949 /*!
mbed_official 324:406fd2029f23 3950 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
mbed_official 324:406fd2029f23 3951 * @{
mbed_official 324:406fd2029f23 3952 */
mbed_official 324:406fd2029f23 3953
mbed_official 324:406fd2029f23 3954
mbed_official 324:406fd2029f23 3955 /* FTM - Register instance definitions */
mbed_official 324:406fd2029f23 3956 /* FTM0 */
mbed_official 324:406fd2029f23 3957 #define FTM0_SC FTM_SC_REG(FTM0)
mbed_official 324:406fd2029f23 3958 #define FTM0_CNT FTM_CNT_REG(FTM0)
mbed_official 324:406fd2029f23 3959 #define FTM0_MOD FTM_MOD_REG(FTM0)
mbed_official 324:406fd2029f23 3960 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
mbed_official 324:406fd2029f23 3961 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
mbed_official 324:406fd2029f23 3962 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
mbed_official 324:406fd2029f23 3963 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
mbed_official 324:406fd2029f23 3964 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
mbed_official 324:406fd2029f23 3965 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
mbed_official 324:406fd2029f23 3966 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
mbed_official 324:406fd2029f23 3967 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
mbed_official 324:406fd2029f23 3968 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
mbed_official 324:406fd2029f23 3969 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
mbed_official 324:406fd2029f23 3970 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
mbed_official 324:406fd2029f23 3971 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
mbed_official 324:406fd2029f23 3972 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
mbed_official 324:406fd2029f23 3973 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
mbed_official 324:406fd2029f23 3974 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
mbed_official 324:406fd2029f23 3975 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
mbed_official 324:406fd2029f23 3976 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
mbed_official 324:406fd2029f23 3977 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
mbed_official 324:406fd2029f23 3978 #define FTM0_MODE FTM_MODE_REG(FTM0)
mbed_official 324:406fd2029f23 3979 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
mbed_official 324:406fd2029f23 3980 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
mbed_official 324:406fd2029f23 3981 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
mbed_official 324:406fd2029f23 3982 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
mbed_official 324:406fd2029f23 3983 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
mbed_official 324:406fd2029f23 3984 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
mbed_official 324:406fd2029f23 3985 #define FTM0_POL FTM_POL_REG(FTM0)
mbed_official 324:406fd2029f23 3986 #define FTM0_FMS FTM_FMS_REG(FTM0)
mbed_official 324:406fd2029f23 3987 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
mbed_official 324:406fd2029f23 3988 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
mbed_official 324:406fd2029f23 3989 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
mbed_official 324:406fd2029f23 3990 #define FTM0_CONF FTM_CONF_REG(FTM0)
mbed_official 324:406fd2029f23 3991 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
mbed_official 324:406fd2029f23 3992 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
mbed_official 324:406fd2029f23 3993 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
mbed_official 324:406fd2029f23 3994 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
mbed_official 324:406fd2029f23 3995 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
mbed_official 324:406fd2029f23 3996 /* FTM1 */
mbed_official 324:406fd2029f23 3997 #define FTM1_SC FTM_SC_REG(FTM1)
mbed_official 324:406fd2029f23 3998 #define FTM1_CNT FTM_CNT_REG(FTM1)
mbed_official 324:406fd2029f23 3999 #define FTM1_MOD FTM_MOD_REG(FTM1)
mbed_official 324:406fd2029f23 4000 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
mbed_official 324:406fd2029f23 4001 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
mbed_official 324:406fd2029f23 4002 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
mbed_official 324:406fd2029f23 4003 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
mbed_official 324:406fd2029f23 4004 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
mbed_official 324:406fd2029f23 4005 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
mbed_official 324:406fd2029f23 4006 #define FTM1_MODE FTM_MODE_REG(FTM1)
mbed_official 324:406fd2029f23 4007 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
mbed_official 324:406fd2029f23 4008 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
mbed_official 324:406fd2029f23 4009 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
mbed_official 324:406fd2029f23 4010 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
mbed_official 324:406fd2029f23 4011 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
mbed_official 324:406fd2029f23 4012 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
mbed_official 324:406fd2029f23 4013 #define FTM1_POL FTM_POL_REG(FTM1)
mbed_official 324:406fd2029f23 4014 #define FTM1_FMS FTM_FMS_REG(FTM1)
mbed_official 324:406fd2029f23 4015 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
mbed_official 324:406fd2029f23 4016 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
mbed_official 324:406fd2029f23 4017 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
mbed_official 324:406fd2029f23 4018 #define FTM1_CONF FTM_CONF_REG(FTM1)
mbed_official 324:406fd2029f23 4019 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
mbed_official 324:406fd2029f23 4020 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
mbed_official 324:406fd2029f23 4021 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
mbed_official 324:406fd2029f23 4022 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
mbed_official 324:406fd2029f23 4023 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
mbed_official 324:406fd2029f23 4024 /* FTM2 */
mbed_official 324:406fd2029f23 4025 #define FTM2_SC FTM_SC_REG(FTM2)
mbed_official 324:406fd2029f23 4026 #define FTM2_CNT FTM_CNT_REG(FTM2)
mbed_official 324:406fd2029f23 4027 #define FTM2_MOD FTM_MOD_REG(FTM2)
mbed_official 324:406fd2029f23 4028 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
mbed_official 324:406fd2029f23 4029 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
mbed_official 324:406fd2029f23 4030 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
mbed_official 324:406fd2029f23 4031 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
mbed_official 324:406fd2029f23 4032 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
mbed_official 324:406fd2029f23 4033 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
mbed_official 324:406fd2029f23 4034 #define FTM2_MODE FTM_MODE_REG(FTM2)
mbed_official 324:406fd2029f23 4035 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
mbed_official 324:406fd2029f23 4036 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
mbed_official 324:406fd2029f23 4037 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
mbed_official 324:406fd2029f23 4038 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
mbed_official 324:406fd2029f23 4039 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
mbed_official 324:406fd2029f23 4040 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
mbed_official 324:406fd2029f23 4041 #define FTM2_POL FTM_POL_REG(FTM2)
mbed_official 324:406fd2029f23 4042 #define FTM2_FMS FTM_FMS_REG(FTM2)
mbed_official 324:406fd2029f23 4043 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
mbed_official 324:406fd2029f23 4044 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
mbed_official 324:406fd2029f23 4045 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
mbed_official 324:406fd2029f23 4046 #define FTM2_CONF FTM_CONF_REG(FTM2)
mbed_official 324:406fd2029f23 4047 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
mbed_official 324:406fd2029f23 4048 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
mbed_official 324:406fd2029f23 4049 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
mbed_official 324:406fd2029f23 4050 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
mbed_official 324:406fd2029f23 4051 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
mbed_official 324:406fd2029f23 4052 /* FTM3 */
mbed_official 324:406fd2029f23 4053 #define FTM3_SC FTM_SC_REG(FTM3)
mbed_official 324:406fd2029f23 4054 #define FTM3_CNT FTM_CNT_REG(FTM3)
mbed_official 324:406fd2029f23 4055 #define FTM3_MOD FTM_MOD_REG(FTM3)
mbed_official 324:406fd2029f23 4056 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
mbed_official 324:406fd2029f23 4057 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
mbed_official 324:406fd2029f23 4058 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
mbed_official 324:406fd2029f23 4059 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
mbed_official 324:406fd2029f23 4060 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
mbed_official 324:406fd2029f23 4061 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
mbed_official 324:406fd2029f23 4062 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
mbed_official 324:406fd2029f23 4063 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
mbed_official 324:406fd2029f23 4064 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
mbed_official 324:406fd2029f23 4065 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
mbed_official 324:406fd2029f23 4066 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
mbed_official 324:406fd2029f23 4067 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
mbed_official 324:406fd2029f23 4068 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
mbed_official 324:406fd2029f23 4069 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
mbed_official 324:406fd2029f23 4070 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
mbed_official 324:406fd2029f23 4071 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
mbed_official 324:406fd2029f23 4072 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
mbed_official 324:406fd2029f23 4073 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
mbed_official 324:406fd2029f23 4074 #define FTM3_MODE FTM_MODE_REG(FTM3)
mbed_official 324:406fd2029f23 4075 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
mbed_official 324:406fd2029f23 4076 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
mbed_official 324:406fd2029f23 4077 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
mbed_official 324:406fd2029f23 4078 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
mbed_official 324:406fd2029f23 4079 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
mbed_official 324:406fd2029f23 4080 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
mbed_official 324:406fd2029f23 4081 #define FTM3_POL FTM_POL_REG(FTM3)
mbed_official 324:406fd2029f23 4082 #define FTM3_FMS FTM_FMS_REG(FTM3)
mbed_official 324:406fd2029f23 4083 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
mbed_official 324:406fd2029f23 4084 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
mbed_official 324:406fd2029f23 4085 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
mbed_official 324:406fd2029f23 4086 #define FTM3_CONF FTM_CONF_REG(FTM3)
mbed_official 324:406fd2029f23 4087 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
mbed_official 324:406fd2029f23 4088 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
mbed_official 324:406fd2029f23 4089 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
mbed_official 324:406fd2029f23 4090 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
mbed_official 324:406fd2029f23 4091 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
mbed_official 324:406fd2029f23 4092
mbed_official 324:406fd2029f23 4093 /* FTM - Register array accessors */
mbed_official 324:406fd2029f23 4094 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
mbed_official 324:406fd2029f23 4095 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
mbed_official 324:406fd2029f23 4096 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
mbed_official 324:406fd2029f23 4097 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
mbed_official 324:406fd2029f23 4098 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
mbed_official 324:406fd2029f23 4099 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
mbed_official 324:406fd2029f23 4100 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
mbed_official 324:406fd2029f23 4101 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
mbed_official 324:406fd2029f23 4102
mbed_official 324:406fd2029f23 4103 /*!
mbed_official 324:406fd2029f23 4104 * @}
mbed_official 324:406fd2029f23 4105 */ /* end of group FTM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4106
mbed_official 324:406fd2029f23 4107
mbed_official 324:406fd2029f23 4108 /*!
mbed_official 324:406fd2029f23 4109 * @}
mbed_official 324:406fd2029f23 4110 */ /* end of group FTM_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 4111
mbed_official 324:406fd2029f23 4112
mbed_official 324:406fd2029f23 4113 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4114 -- GPIO Peripheral Access Layer
mbed_official 324:406fd2029f23 4115 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4116
mbed_official 324:406fd2029f23 4117 /*!
mbed_official 324:406fd2029f23 4118 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 324:406fd2029f23 4119 * @{
mbed_official 324:406fd2029f23 4120 */
mbed_official 324:406fd2029f23 4121
mbed_official 324:406fd2029f23 4122 /** GPIO - Register Layout Typedef */
mbed_official 324:406fd2029f23 4123 typedef struct {
mbed_official 324:406fd2029f23 4124 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 324:406fd2029f23 4125 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 324:406fd2029f23 4126 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 324:406fd2029f23 4127 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 324:406fd2029f23 4128 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 324:406fd2029f23 4129 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 324:406fd2029f23 4130 } GPIO_Type, *GPIO_MemMapPtr;
mbed_official 324:406fd2029f23 4131
mbed_official 324:406fd2029f23 4132 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4133 -- GPIO - Register accessor macros
mbed_official 324:406fd2029f23 4134 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4135
mbed_official 324:406fd2029f23 4136 /*!
mbed_official 324:406fd2029f23 4137 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 324:406fd2029f23 4138 * @{
mbed_official 324:406fd2029f23 4139 */
mbed_official 324:406fd2029f23 4140
mbed_official 324:406fd2029f23 4141
mbed_official 324:406fd2029f23 4142 /* GPIO - Register accessors */
mbed_official 324:406fd2029f23 4143 #define GPIO_PDOR_REG(base) ((base)->PDOR)
mbed_official 324:406fd2029f23 4144 #define GPIO_PSOR_REG(base) ((base)->PSOR)
mbed_official 324:406fd2029f23 4145 #define GPIO_PCOR_REG(base) ((base)->PCOR)
mbed_official 324:406fd2029f23 4146 #define GPIO_PTOR_REG(base) ((base)->PTOR)
mbed_official 324:406fd2029f23 4147 #define GPIO_PDIR_REG(base) ((base)->PDIR)
mbed_official 324:406fd2029f23 4148 #define GPIO_PDDR_REG(base) ((base)->PDDR)
mbed_official 324:406fd2029f23 4149
mbed_official 324:406fd2029f23 4150 /*!
mbed_official 324:406fd2029f23 4151 * @}
mbed_official 324:406fd2029f23 4152 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4153
mbed_official 324:406fd2029f23 4154
mbed_official 324:406fd2029f23 4155 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4156 -- GPIO Register Masks
mbed_official 324:406fd2029f23 4157 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4158
mbed_official 324:406fd2029f23 4159 /*!
mbed_official 324:406fd2029f23 4160 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 324:406fd2029f23 4161 * @{
mbed_official 324:406fd2029f23 4162 */
mbed_official 324:406fd2029f23 4163
mbed_official 324:406fd2029f23 4164 /* PDOR Bit Fields */
mbed_official 324:406fd2029f23 4165 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4166 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 324:406fd2029f23 4167 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 324:406fd2029f23 4168 /* PSOR Bit Fields */
mbed_official 324:406fd2029f23 4169 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4170 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 324:406fd2029f23 4171 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 324:406fd2029f23 4172 /* PCOR Bit Fields */
mbed_official 324:406fd2029f23 4173 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4174 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 324:406fd2029f23 4175 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 324:406fd2029f23 4176 /* PTOR Bit Fields */
mbed_official 324:406fd2029f23 4177 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4178 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 324:406fd2029f23 4179 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 324:406fd2029f23 4180 /* PDIR Bit Fields */
mbed_official 324:406fd2029f23 4181 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4182 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 324:406fd2029f23 4183 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 324:406fd2029f23 4184 /* PDDR Bit Fields */
mbed_official 324:406fd2029f23 4185 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4186 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 324:406fd2029f23 4187 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 324:406fd2029f23 4188
mbed_official 324:406fd2029f23 4189 /*!
mbed_official 324:406fd2029f23 4190 * @}
mbed_official 324:406fd2029f23 4191 */ /* end of group GPIO_Register_Masks */
mbed_official 324:406fd2029f23 4192
mbed_official 324:406fd2029f23 4193
mbed_official 324:406fd2029f23 4194 /* GPIO - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 4195 /** Peripheral PTA base address */
mbed_official 324:406fd2029f23 4196 #define PTA_BASE (0x400FF000u)
mbed_official 324:406fd2029f23 4197 /** Peripheral PTA base pointer */
mbed_official 324:406fd2029f23 4198 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 324:406fd2029f23 4199 #define PTA_BASE_PTR (PTA)
mbed_official 324:406fd2029f23 4200 /** Peripheral PTB base address */
mbed_official 324:406fd2029f23 4201 #define PTB_BASE (0x400FF040u)
mbed_official 324:406fd2029f23 4202 /** Peripheral PTB base pointer */
mbed_official 324:406fd2029f23 4203 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 324:406fd2029f23 4204 #define PTB_BASE_PTR (PTB)
mbed_official 324:406fd2029f23 4205 /** Peripheral PTC base address */
mbed_official 324:406fd2029f23 4206 #define PTC_BASE (0x400FF080u)
mbed_official 324:406fd2029f23 4207 /** Peripheral PTC base pointer */
mbed_official 324:406fd2029f23 4208 #define PTC ((GPIO_Type *)PTC_BASE)
mbed_official 324:406fd2029f23 4209 #define PTC_BASE_PTR (PTC)
mbed_official 324:406fd2029f23 4210 /** Peripheral PTD base address */
mbed_official 324:406fd2029f23 4211 #define PTD_BASE (0x400FF0C0u)
mbed_official 324:406fd2029f23 4212 /** Peripheral PTD base pointer */
mbed_official 324:406fd2029f23 4213 #define PTD ((GPIO_Type *)PTD_BASE)
mbed_official 324:406fd2029f23 4214 #define PTD_BASE_PTR (PTD)
mbed_official 324:406fd2029f23 4215 /** Peripheral PTE base address */
mbed_official 324:406fd2029f23 4216 #define PTE_BASE (0x400FF100u)
mbed_official 324:406fd2029f23 4217 /** Peripheral PTE base pointer */
mbed_official 324:406fd2029f23 4218 #define PTE ((GPIO_Type *)PTE_BASE)
mbed_official 324:406fd2029f23 4219 #define PTE_BASE_PTR (PTE)
mbed_official 324:406fd2029f23 4220 /** Array initializer of GPIO peripheral base addresses */
mbed_official 324:406fd2029f23 4221 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
mbed_official 324:406fd2029f23 4222 /** Array initializer of GPIO peripheral base pointers */
mbed_official 324:406fd2029f23 4223 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
mbed_official 324:406fd2029f23 4224
mbed_official 324:406fd2029f23 4225 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4226 -- GPIO - Register accessor macros
mbed_official 324:406fd2029f23 4227 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4228
mbed_official 324:406fd2029f23 4229 /*!
mbed_official 324:406fd2029f23 4230 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 324:406fd2029f23 4231 * @{
mbed_official 324:406fd2029f23 4232 */
mbed_official 324:406fd2029f23 4233
mbed_official 324:406fd2029f23 4234
mbed_official 324:406fd2029f23 4235 /* GPIO - Register instance definitions */
mbed_official 324:406fd2029f23 4236 /* PTA */
mbed_official 324:406fd2029f23 4237 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
mbed_official 324:406fd2029f23 4238 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
mbed_official 324:406fd2029f23 4239 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
mbed_official 324:406fd2029f23 4240 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
mbed_official 324:406fd2029f23 4241 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
mbed_official 324:406fd2029f23 4242 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
mbed_official 324:406fd2029f23 4243 /* PTB */
mbed_official 324:406fd2029f23 4244 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
mbed_official 324:406fd2029f23 4245 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
mbed_official 324:406fd2029f23 4246 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
mbed_official 324:406fd2029f23 4247 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
mbed_official 324:406fd2029f23 4248 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
mbed_official 324:406fd2029f23 4249 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
mbed_official 324:406fd2029f23 4250 /* PTC */
mbed_official 324:406fd2029f23 4251 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
mbed_official 324:406fd2029f23 4252 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
mbed_official 324:406fd2029f23 4253 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
mbed_official 324:406fd2029f23 4254 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
mbed_official 324:406fd2029f23 4255 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
mbed_official 324:406fd2029f23 4256 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
mbed_official 324:406fd2029f23 4257 /* PTD */
mbed_official 324:406fd2029f23 4258 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
mbed_official 324:406fd2029f23 4259 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
mbed_official 324:406fd2029f23 4260 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
mbed_official 324:406fd2029f23 4261 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
mbed_official 324:406fd2029f23 4262 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
mbed_official 324:406fd2029f23 4263 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
mbed_official 324:406fd2029f23 4264 /* PTE */
mbed_official 324:406fd2029f23 4265 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
mbed_official 324:406fd2029f23 4266 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
mbed_official 324:406fd2029f23 4267 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
mbed_official 324:406fd2029f23 4268 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
mbed_official 324:406fd2029f23 4269 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
mbed_official 324:406fd2029f23 4270 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
mbed_official 324:406fd2029f23 4271
mbed_official 324:406fd2029f23 4272 /*!
mbed_official 324:406fd2029f23 4273 * @}
mbed_official 324:406fd2029f23 4274 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4275
mbed_official 324:406fd2029f23 4276
mbed_official 324:406fd2029f23 4277 /*!
mbed_official 324:406fd2029f23 4278 * @}
mbed_official 324:406fd2029f23 4279 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 4280
mbed_official 324:406fd2029f23 4281
mbed_official 324:406fd2029f23 4282 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4283 -- I2C Peripheral Access Layer
mbed_official 324:406fd2029f23 4284 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4285
mbed_official 324:406fd2029f23 4286 /*!
mbed_official 324:406fd2029f23 4287 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 324:406fd2029f23 4288 * @{
mbed_official 324:406fd2029f23 4289 */
mbed_official 324:406fd2029f23 4290
mbed_official 324:406fd2029f23 4291 /** I2C - Register Layout Typedef */
mbed_official 324:406fd2029f23 4292 typedef struct {
mbed_official 324:406fd2029f23 4293 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 324:406fd2029f23 4294 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 324:406fd2029f23 4295 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 324:406fd2029f23 4296 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 324:406fd2029f23 4297 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 324:406fd2029f23 4298 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 324:406fd2029f23 4299 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 324:406fd2029f23 4300 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 324:406fd2029f23 4301 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 324:406fd2029f23 4302 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 324:406fd2029f23 4303 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 324:406fd2029f23 4304 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 324:406fd2029f23 4305 } I2C_Type, *I2C_MemMapPtr;
mbed_official 324:406fd2029f23 4306
mbed_official 324:406fd2029f23 4307 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4308 -- I2C - Register accessor macros
mbed_official 324:406fd2029f23 4309 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4310
mbed_official 324:406fd2029f23 4311 /*!
mbed_official 324:406fd2029f23 4312 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 324:406fd2029f23 4313 * @{
mbed_official 324:406fd2029f23 4314 */
mbed_official 324:406fd2029f23 4315
mbed_official 324:406fd2029f23 4316
mbed_official 324:406fd2029f23 4317 /* I2C - Register accessors */
mbed_official 324:406fd2029f23 4318 #define I2C_A1_REG(base) ((base)->A1)
mbed_official 324:406fd2029f23 4319 #define I2C_F_REG(base) ((base)->F)
mbed_official 324:406fd2029f23 4320 #define I2C_C1_REG(base) ((base)->C1)
mbed_official 324:406fd2029f23 4321 #define I2C_S_REG(base) ((base)->S)
mbed_official 324:406fd2029f23 4322 #define I2C_D_REG(base) ((base)->D)
mbed_official 324:406fd2029f23 4323 #define I2C_C2_REG(base) ((base)->C2)
mbed_official 324:406fd2029f23 4324 #define I2C_FLT_REG(base) ((base)->FLT)
mbed_official 324:406fd2029f23 4325 #define I2C_RA_REG(base) ((base)->RA)
mbed_official 324:406fd2029f23 4326 #define I2C_SMB_REG(base) ((base)->SMB)
mbed_official 324:406fd2029f23 4327 #define I2C_A2_REG(base) ((base)->A2)
mbed_official 324:406fd2029f23 4328 #define I2C_SLTH_REG(base) ((base)->SLTH)
mbed_official 324:406fd2029f23 4329 #define I2C_SLTL_REG(base) ((base)->SLTL)
mbed_official 324:406fd2029f23 4330
mbed_official 324:406fd2029f23 4331 /*!
mbed_official 324:406fd2029f23 4332 * @}
mbed_official 324:406fd2029f23 4333 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4334
mbed_official 324:406fd2029f23 4335
mbed_official 324:406fd2029f23 4336 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4337 -- I2C Register Masks
mbed_official 324:406fd2029f23 4338 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4339
mbed_official 324:406fd2029f23 4340 /*!
mbed_official 324:406fd2029f23 4341 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 324:406fd2029f23 4342 * @{
mbed_official 324:406fd2029f23 4343 */
mbed_official 324:406fd2029f23 4344
mbed_official 324:406fd2029f23 4345 /* A1 Bit Fields */
mbed_official 324:406fd2029f23 4346 #define I2C_A1_AD_MASK 0xFEu
mbed_official 324:406fd2029f23 4347 #define I2C_A1_AD_SHIFT 1
mbed_official 324:406fd2029f23 4348 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 324:406fd2029f23 4349 /* F Bit Fields */
mbed_official 324:406fd2029f23 4350 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 324:406fd2029f23 4351 #define I2C_F_ICR_SHIFT 0
mbed_official 324:406fd2029f23 4352 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 324:406fd2029f23 4353 #define I2C_F_MULT_MASK 0xC0u
mbed_official 324:406fd2029f23 4354 #define I2C_F_MULT_SHIFT 6
mbed_official 324:406fd2029f23 4355 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 324:406fd2029f23 4356 /* C1 Bit Fields */
mbed_official 324:406fd2029f23 4357 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 324:406fd2029f23 4358 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 324:406fd2029f23 4359 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 324:406fd2029f23 4360 #define I2C_C1_WUEN_SHIFT 1
mbed_official 324:406fd2029f23 4361 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 324:406fd2029f23 4362 #define I2C_C1_RSTA_SHIFT 2
mbed_official 324:406fd2029f23 4363 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 324:406fd2029f23 4364 #define I2C_C1_TXAK_SHIFT 3
mbed_official 324:406fd2029f23 4365 #define I2C_C1_TX_MASK 0x10u
mbed_official 324:406fd2029f23 4366 #define I2C_C1_TX_SHIFT 4
mbed_official 324:406fd2029f23 4367 #define I2C_C1_MST_MASK 0x20u
mbed_official 324:406fd2029f23 4368 #define I2C_C1_MST_SHIFT 5
mbed_official 324:406fd2029f23 4369 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 324:406fd2029f23 4370 #define I2C_C1_IICIE_SHIFT 6
mbed_official 324:406fd2029f23 4371 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 324:406fd2029f23 4372 #define I2C_C1_IICEN_SHIFT 7
mbed_official 324:406fd2029f23 4373 /* S Bit Fields */
mbed_official 324:406fd2029f23 4374 #define I2C_S_RXAK_MASK 0x1u
mbed_official 324:406fd2029f23 4375 #define I2C_S_RXAK_SHIFT 0
mbed_official 324:406fd2029f23 4376 #define I2C_S_IICIF_MASK 0x2u
mbed_official 324:406fd2029f23 4377 #define I2C_S_IICIF_SHIFT 1
mbed_official 324:406fd2029f23 4378 #define I2C_S_SRW_MASK 0x4u
mbed_official 324:406fd2029f23 4379 #define I2C_S_SRW_SHIFT 2
mbed_official 324:406fd2029f23 4380 #define I2C_S_RAM_MASK 0x8u
mbed_official 324:406fd2029f23 4381 #define I2C_S_RAM_SHIFT 3
mbed_official 324:406fd2029f23 4382 #define I2C_S_ARBL_MASK 0x10u
mbed_official 324:406fd2029f23 4383 #define I2C_S_ARBL_SHIFT 4
mbed_official 324:406fd2029f23 4384 #define I2C_S_BUSY_MASK 0x20u
mbed_official 324:406fd2029f23 4385 #define I2C_S_BUSY_SHIFT 5
mbed_official 324:406fd2029f23 4386 #define I2C_S_IAAS_MASK 0x40u
mbed_official 324:406fd2029f23 4387 #define I2C_S_IAAS_SHIFT 6
mbed_official 324:406fd2029f23 4388 #define I2C_S_TCF_MASK 0x80u
mbed_official 324:406fd2029f23 4389 #define I2C_S_TCF_SHIFT 7
mbed_official 324:406fd2029f23 4390 /* D Bit Fields */
mbed_official 324:406fd2029f23 4391 #define I2C_D_DATA_MASK 0xFFu
mbed_official 324:406fd2029f23 4392 #define I2C_D_DATA_SHIFT 0
mbed_official 324:406fd2029f23 4393 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 324:406fd2029f23 4394 /* C2 Bit Fields */
mbed_official 324:406fd2029f23 4395 #define I2C_C2_AD_MASK 0x7u
mbed_official 324:406fd2029f23 4396 #define I2C_C2_AD_SHIFT 0
mbed_official 324:406fd2029f23 4397 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 324:406fd2029f23 4398 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 324:406fd2029f23 4399 #define I2C_C2_RMEN_SHIFT 3
mbed_official 324:406fd2029f23 4400 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 324:406fd2029f23 4401 #define I2C_C2_SBRC_SHIFT 4
mbed_official 324:406fd2029f23 4402 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 324:406fd2029f23 4403 #define I2C_C2_HDRS_SHIFT 5
mbed_official 324:406fd2029f23 4404 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 324:406fd2029f23 4405 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 324:406fd2029f23 4406 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 324:406fd2029f23 4407 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 324:406fd2029f23 4408 /* FLT Bit Fields */
mbed_official 324:406fd2029f23 4409 #define I2C_FLT_FLT_MASK 0xFu
mbed_official 324:406fd2029f23 4410 #define I2C_FLT_FLT_SHIFT 0
mbed_official 324:406fd2029f23 4411 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 324:406fd2029f23 4412 #define I2C_FLT_STARTF_MASK 0x10u
mbed_official 324:406fd2029f23 4413 #define I2C_FLT_STARTF_SHIFT 4
mbed_official 324:406fd2029f23 4414 #define I2C_FLT_SSIE_MASK 0x20u
mbed_official 324:406fd2029f23 4415 #define I2C_FLT_SSIE_SHIFT 5
mbed_official 324:406fd2029f23 4416 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 324:406fd2029f23 4417 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 324:406fd2029f23 4418 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 324:406fd2029f23 4419 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 324:406fd2029f23 4420 /* RA Bit Fields */
mbed_official 324:406fd2029f23 4421 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 324:406fd2029f23 4422 #define I2C_RA_RAD_SHIFT 1
mbed_official 324:406fd2029f23 4423 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 324:406fd2029f23 4424 /* SMB Bit Fields */
mbed_official 324:406fd2029f23 4425 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 324:406fd2029f23 4426 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 324:406fd2029f23 4427 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 324:406fd2029f23 4428 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 324:406fd2029f23 4429 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 324:406fd2029f23 4430 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 324:406fd2029f23 4431 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 324:406fd2029f23 4432 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 324:406fd2029f23 4433 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 324:406fd2029f23 4434 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 324:406fd2029f23 4435 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 324:406fd2029f23 4436 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 324:406fd2029f23 4437 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 324:406fd2029f23 4438 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 324:406fd2029f23 4439 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 324:406fd2029f23 4440 #define I2C_SMB_FACK_SHIFT 7
mbed_official 324:406fd2029f23 4441 /* A2 Bit Fields */
mbed_official 324:406fd2029f23 4442 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 324:406fd2029f23 4443 #define I2C_A2_SAD_SHIFT 1
mbed_official 324:406fd2029f23 4444 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 324:406fd2029f23 4445 /* SLTH Bit Fields */
mbed_official 324:406fd2029f23 4446 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 324:406fd2029f23 4447 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 324:406fd2029f23 4448 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 324:406fd2029f23 4449 /* SLTL Bit Fields */
mbed_official 324:406fd2029f23 4450 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 324:406fd2029f23 4451 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 324:406fd2029f23 4452 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 324:406fd2029f23 4453
mbed_official 324:406fd2029f23 4454 /*!
mbed_official 324:406fd2029f23 4455 * @}
mbed_official 324:406fd2029f23 4456 */ /* end of group I2C_Register_Masks */
mbed_official 324:406fd2029f23 4457
mbed_official 324:406fd2029f23 4458
mbed_official 324:406fd2029f23 4459 /* I2C - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 4460 /** Peripheral I2C0 base address */
mbed_official 324:406fd2029f23 4461 #define I2C0_BASE (0x40066000u)
mbed_official 324:406fd2029f23 4462 /** Peripheral I2C0 base pointer */
mbed_official 324:406fd2029f23 4463 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 324:406fd2029f23 4464 #define I2C0_BASE_PTR (I2C0)
mbed_official 324:406fd2029f23 4465 /** Peripheral I2C1 base address */
mbed_official 324:406fd2029f23 4466 #define I2C1_BASE (0x40067000u)
mbed_official 324:406fd2029f23 4467 /** Peripheral I2C1 base pointer */
mbed_official 324:406fd2029f23 4468 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 324:406fd2029f23 4469 #define I2C1_BASE_PTR (I2C1)
mbed_official 324:406fd2029f23 4470 /** Array initializer of I2C peripheral base addresses */
mbed_official 324:406fd2029f23 4471 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
mbed_official 324:406fd2029f23 4472 /** Array initializer of I2C peripheral base pointers */
mbed_official 324:406fd2029f23 4473 #define I2C_BASE_PTRS { I2C0, I2C1 }
mbed_official 324:406fd2029f23 4474 /** Interrupt vectors for the I2C peripheral type */
mbed_official 324:406fd2029f23 4475 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
mbed_official 324:406fd2029f23 4476
mbed_official 324:406fd2029f23 4477 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4478 -- I2C - Register accessor macros
mbed_official 324:406fd2029f23 4479 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4480
mbed_official 324:406fd2029f23 4481 /*!
mbed_official 324:406fd2029f23 4482 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 324:406fd2029f23 4483 * @{
mbed_official 324:406fd2029f23 4484 */
mbed_official 324:406fd2029f23 4485
mbed_official 324:406fd2029f23 4486
mbed_official 324:406fd2029f23 4487 /* I2C - Register instance definitions */
mbed_official 324:406fd2029f23 4488 /* I2C0 */
mbed_official 324:406fd2029f23 4489 #define I2C0_A1 I2C_A1_REG(I2C0)
mbed_official 324:406fd2029f23 4490 #define I2C0_F I2C_F_REG(I2C0)
mbed_official 324:406fd2029f23 4491 #define I2C0_C1 I2C_C1_REG(I2C0)
mbed_official 324:406fd2029f23 4492 #define I2C0_S I2C_S_REG(I2C0)
mbed_official 324:406fd2029f23 4493 #define I2C0_D I2C_D_REG(I2C0)
mbed_official 324:406fd2029f23 4494 #define I2C0_C2 I2C_C2_REG(I2C0)
mbed_official 324:406fd2029f23 4495 #define I2C0_FLT I2C_FLT_REG(I2C0)
mbed_official 324:406fd2029f23 4496 #define I2C0_RA I2C_RA_REG(I2C0)
mbed_official 324:406fd2029f23 4497 #define I2C0_SMB I2C_SMB_REG(I2C0)
mbed_official 324:406fd2029f23 4498 #define I2C0_A2 I2C_A2_REG(I2C0)
mbed_official 324:406fd2029f23 4499 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
mbed_official 324:406fd2029f23 4500 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
mbed_official 324:406fd2029f23 4501 /* I2C1 */
mbed_official 324:406fd2029f23 4502 #define I2C1_A1 I2C_A1_REG(I2C1)
mbed_official 324:406fd2029f23 4503 #define I2C1_F I2C_F_REG(I2C1)
mbed_official 324:406fd2029f23 4504 #define I2C1_C1 I2C_C1_REG(I2C1)
mbed_official 324:406fd2029f23 4505 #define I2C1_S I2C_S_REG(I2C1)
mbed_official 324:406fd2029f23 4506 #define I2C1_D I2C_D_REG(I2C1)
mbed_official 324:406fd2029f23 4507 #define I2C1_C2 I2C_C2_REG(I2C1)
mbed_official 324:406fd2029f23 4508 #define I2C1_FLT I2C_FLT_REG(I2C1)
mbed_official 324:406fd2029f23 4509 #define I2C1_RA I2C_RA_REG(I2C1)
mbed_official 324:406fd2029f23 4510 #define I2C1_SMB I2C_SMB_REG(I2C1)
mbed_official 324:406fd2029f23 4511 #define I2C1_A2 I2C_A2_REG(I2C1)
mbed_official 324:406fd2029f23 4512 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
mbed_official 324:406fd2029f23 4513 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
mbed_official 324:406fd2029f23 4514
mbed_official 324:406fd2029f23 4515 /*!
mbed_official 324:406fd2029f23 4516 * @}
mbed_official 324:406fd2029f23 4517 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4518
mbed_official 324:406fd2029f23 4519
mbed_official 324:406fd2029f23 4520 /*!
mbed_official 324:406fd2029f23 4521 * @}
mbed_official 324:406fd2029f23 4522 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 4523
mbed_official 324:406fd2029f23 4524
mbed_official 324:406fd2029f23 4525 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4526 -- I2S Peripheral Access Layer
mbed_official 324:406fd2029f23 4527 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4528
mbed_official 324:406fd2029f23 4529 /*!
mbed_official 324:406fd2029f23 4530 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 324:406fd2029f23 4531 * @{
mbed_official 324:406fd2029f23 4532 */
mbed_official 324:406fd2029f23 4533
mbed_official 324:406fd2029f23 4534 /** I2S - Register Layout Typedef */
mbed_official 324:406fd2029f23 4535 typedef struct {
mbed_official 324:406fd2029f23 4536 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 4537 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
mbed_official 324:406fd2029f23 4538 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 324:406fd2029f23 4539 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 324:406fd2029f23 4540 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 324:406fd2029f23 4541 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 324:406fd2029f23 4542 uint8_t RESERVED_0[8];
mbed_official 324:406fd2029f23 4543 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 324:406fd2029f23 4544 uint8_t RESERVED_1[28];
mbed_official 324:406fd2029f23 4545 __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
mbed_official 324:406fd2029f23 4546 uint8_t RESERVED_2[28];
mbed_official 324:406fd2029f23 4547 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 324:406fd2029f23 4548 uint8_t RESERVED_3[28];
mbed_official 324:406fd2029f23 4549 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 324:406fd2029f23 4550 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
mbed_official 324:406fd2029f23 4551 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 324:406fd2029f23 4552 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 324:406fd2029f23 4553 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 324:406fd2029f23 4554 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 324:406fd2029f23 4555 uint8_t RESERVED_4[8];
mbed_official 324:406fd2029f23 4556 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 324:406fd2029f23 4557 uint8_t RESERVED_5[28];
mbed_official 324:406fd2029f23 4558 __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
mbed_official 324:406fd2029f23 4559 uint8_t RESERVED_6[28];
mbed_official 324:406fd2029f23 4560 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 324:406fd2029f23 4561 uint8_t RESERVED_7[28];
mbed_official 324:406fd2029f23 4562 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 324:406fd2029f23 4563 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
mbed_official 324:406fd2029f23 4564 } I2S_Type, *I2S_MemMapPtr;
mbed_official 324:406fd2029f23 4565
mbed_official 324:406fd2029f23 4566 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4567 -- I2S - Register accessor macros
mbed_official 324:406fd2029f23 4568 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4569
mbed_official 324:406fd2029f23 4570 /*!
mbed_official 324:406fd2029f23 4571 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 324:406fd2029f23 4572 * @{
mbed_official 324:406fd2029f23 4573 */
mbed_official 324:406fd2029f23 4574
mbed_official 324:406fd2029f23 4575
mbed_official 324:406fd2029f23 4576 /* I2S - Register accessors */
mbed_official 324:406fd2029f23 4577 #define I2S_TCSR_REG(base) ((base)->TCSR)
mbed_official 324:406fd2029f23 4578 #define I2S_TCR1_REG(base) ((base)->TCR1)
mbed_official 324:406fd2029f23 4579 #define I2S_TCR2_REG(base) ((base)->TCR2)
mbed_official 324:406fd2029f23 4580 #define I2S_TCR3_REG(base) ((base)->TCR3)
mbed_official 324:406fd2029f23 4581 #define I2S_TCR4_REG(base) ((base)->TCR4)
mbed_official 324:406fd2029f23 4582 #define I2S_TCR5_REG(base) ((base)->TCR5)
mbed_official 324:406fd2029f23 4583 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
mbed_official 324:406fd2029f23 4584 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
mbed_official 324:406fd2029f23 4585 #define I2S_TMR_REG(base) ((base)->TMR)
mbed_official 324:406fd2029f23 4586 #define I2S_RCSR_REG(base) ((base)->RCSR)
mbed_official 324:406fd2029f23 4587 #define I2S_RCR1_REG(base) ((base)->RCR1)
mbed_official 324:406fd2029f23 4588 #define I2S_RCR2_REG(base) ((base)->RCR2)
mbed_official 324:406fd2029f23 4589 #define I2S_RCR3_REG(base) ((base)->RCR3)
mbed_official 324:406fd2029f23 4590 #define I2S_RCR4_REG(base) ((base)->RCR4)
mbed_official 324:406fd2029f23 4591 #define I2S_RCR5_REG(base) ((base)->RCR5)
mbed_official 324:406fd2029f23 4592 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
mbed_official 324:406fd2029f23 4593 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
mbed_official 324:406fd2029f23 4594 #define I2S_RMR_REG(base) ((base)->RMR)
mbed_official 324:406fd2029f23 4595 #define I2S_MCR_REG(base) ((base)->MCR)
mbed_official 324:406fd2029f23 4596 #define I2S_MDR_REG(base) ((base)->MDR)
mbed_official 324:406fd2029f23 4597
mbed_official 324:406fd2029f23 4598 /*!
mbed_official 324:406fd2029f23 4599 * @}
mbed_official 324:406fd2029f23 4600 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4601
mbed_official 324:406fd2029f23 4602
mbed_official 324:406fd2029f23 4603 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4604 -- I2S Register Masks
mbed_official 324:406fd2029f23 4605 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4606
mbed_official 324:406fd2029f23 4607 /*!
mbed_official 324:406fd2029f23 4608 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 324:406fd2029f23 4609 * @{
mbed_official 324:406fd2029f23 4610 */
mbed_official 324:406fd2029f23 4611
mbed_official 324:406fd2029f23 4612 /* TCSR Bit Fields */
mbed_official 324:406fd2029f23 4613 #define I2S_TCSR_FRDE_MASK 0x1u
mbed_official 324:406fd2029f23 4614 #define I2S_TCSR_FRDE_SHIFT 0
mbed_official 324:406fd2029f23 4615 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 324:406fd2029f23 4616 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 324:406fd2029f23 4617 #define I2S_TCSR_FRIE_MASK 0x100u
mbed_official 324:406fd2029f23 4618 #define I2S_TCSR_FRIE_SHIFT 8
mbed_official 324:406fd2029f23 4619 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 324:406fd2029f23 4620 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 324:406fd2029f23 4621 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 324:406fd2029f23 4622 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 324:406fd2029f23 4623 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 324:406fd2029f23 4624 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 324:406fd2029f23 4625 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 324:406fd2029f23 4626 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 324:406fd2029f23 4627 #define I2S_TCSR_FRF_MASK 0x10000u
mbed_official 324:406fd2029f23 4628 #define I2S_TCSR_FRF_SHIFT 16
mbed_official 324:406fd2029f23 4629 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 324:406fd2029f23 4630 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 324:406fd2029f23 4631 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 324:406fd2029f23 4632 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 324:406fd2029f23 4633 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 324:406fd2029f23 4634 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 324:406fd2029f23 4635 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 324:406fd2029f23 4636 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 324:406fd2029f23 4637 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 324:406fd2029f23 4638 #define I2S_TCSR_SR_SHIFT 24
mbed_official 324:406fd2029f23 4639 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 324:406fd2029f23 4640 #define I2S_TCSR_FR_SHIFT 25
mbed_official 324:406fd2029f23 4641 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 324:406fd2029f23 4642 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 324:406fd2029f23 4643 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 324:406fd2029f23 4644 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 324:406fd2029f23 4645 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 324:406fd2029f23 4646 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 324:406fd2029f23 4647 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 324:406fd2029f23 4648 #define I2S_TCSR_TE_SHIFT 31
mbed_official 324:406fd2029f23 4649 /* TCR1 Bit Fields */
mbed_official 324:406fd2029f23 4650 #define I2S_TCR1_TFW_MASK 0x7u
mbed_official 324:406fd2029f23 4651 #define I2S_TCR1_TFW_SHIFT 0
mbed_official 324:406fd2029f23 4652 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
mbed_official 324:406fd2029f23 4653 /* TCR2 Bit Fields */
mbed_official 324:406fd2029f23 4654 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 324:406fd2029f23 4655 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 324:406fd2029f23 4656 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 324:406fd2029f23 4657 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 324:406fd2029f23 4658 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 324:406fd2029f23 4659 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 324:406fd2029f23 4660 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 324:406fd2029f23 4661 #define I2S_TCR2_MSEL_MASK 0xC000000u
mbed_official 324:406fd2029f23 4662 #define I2S_TCR2_MSEL_SHIFT 26
mbed_official 324:406fd2029f23 4663 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
mbed_official 324:406fd2029f23 4664 #define I2S_TCR2_BCI_MASK 0x10000000u
mbed_official 324:406fd2029f23 4665 #define I2S_TCR2_BCI_SHIFT 28
mbed_official 324:406fd2029f23 4666 #define I2S_TCR2_BCS_MASK 0x20000000u
mbed_official 324:406fd2029f23 4667 #define I2S_TCR2_BCS_SHIFT 29
mbed_official 324:406fd2029f23 4668 #define I2S_TCR2_SYNC_MASK 0xC0000000u
mbed_official 324:406fd2029f23 4669 #define I2S_TCR2_SYNC_SHIFT 30
mbed_official 324:406fd2029f23 4670 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
mbed_official 324:406fd2029f23 4671 /* TCR3 Bit Fields */
mbed_official 324:406fd2029f23 4672 #define I2S_TCR3_WDFL_MASK 0xFu
mbed_official 324:406fd2029f23 4673 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 324:406fd2029f23 4674 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
mbed_official 324:406fd2029f23 4675 #define I2S_TCR3_TCE_MASK 0x10000u
mbed_official 324:406fd2029f23 4676 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 324:406fd2029f23 4677 /* TCR4 Bit Fields */
mbed_official 324:406fd2029f23 4678 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 324:406fd2029f23 4679 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 324:406fd2029f23 4680 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 324:406fd2029f23 4681 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 324:406fd2029f23 4682 #define I2S_TCR4_ONDEM_MASK 0x4u
mbed_official 324:406fd2029f23 4683 #define I2S_TCR4_ONDEM_SHIFT 2
mbed_official 324:406fd2029f23 4684 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 324:406fd2029f23 4685 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 324:406fd2029f23 4686 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 324:406fd2029f23 4687 #define I2S_TCR4_MF_SHIFT 4
mbed_official 324:406fd2029f23 4688 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 324:406fd2029f23 4689 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 324:406fd2029f23 4690 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 324:406fd2029f23 4691 #define I2S_TCR4_FRSZ_MASK 0xF0000u
mbed_official 324:406fd2029f23 4692 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 324:406fd2029f23 4693 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
mbed_official 324:406fd2029f23 4694 #define I2S_TCR4_FPACK_MASK 0x3000000u
mbed_official 324:406fd2029f23 4695 #define I2S_TCR4_FPACK_SHIFT 24
mbed_official 324:406fd2029f23 4696 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
mbed_official 324:406fd2029f23 4697 #define I2S_TCR4_FCONT_MASK 0x10000000u
mbed_official 324:406fd2029f23 4698 #define I2S_TCR4_FCONT_SHIFT 28
mbed_official 324:406fd2029f23 4699 /* TCR5 Bit Fields */
mbed_official 324:406fd2029f23 4700 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 324:406fd2029f23 4701 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 324:406fd2029f23 4702 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 324:406fd2029f23 4703 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 324:406fd2029f23 4704 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 324:406fd2029f23 4705 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 324:406fd2029f23 4706 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 324:406fd2029f23 4707 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 324:406fd2029f23 4708 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 324:406fd2029f23 4709 /* TDR Bit Fields */
mbed_official 324:406fd2029f23 4710 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4711 #define I2S_TDR_TDR_SHIFT 0
mbed_official 324:406fd2029f23 4712 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 324:406fd2029f23 4713 /* TFR Bit Fields */
mbed_official 324:406fd2029f23 4714 #define I2S_TFR_RFP_MASK 0xFu
mbed_official 324:406fd2029f23 4715 #define I2S_TFR_RFP_SHIFT 0
mbed_official 324:406fd2029f23 4716 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
mbed_official 324:406fd2029f23 4717 #define I2S_TFR_WFP_MASK 0xF0000u
mbed_official 324:406fd2029f23 4718 #define I2S_TFR_WFP_SHIFT 16
mbed_official 324:406fd2029f23 4719 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
mbed_official 324:406fd2029f23 4720 /* TMR Bit Fields */
mbed_official 324:406fd2029f23 4721 #define I2S_TMR_TWM_MASK 0xFFFFu
mbed_official 324:406fd2029f23 4722 #define I2S_TMR_TWM_SHIFT 0
mbed_official 324:406fd2029f23 4723 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 324:406fd2029f23 4724 /* RCSR Bit Fields */
mbed_official 324:406fd2029f23 4725 #define I2S_RCSR_FRDE_MASK 0x1u
mbed_official 324:406fd2029f23 4726 #define I2S_RCSR_FRDE_SHIFT 0
mbed_official 324:406fd2029f23 4727 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 324:406fd2029f23 4728 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 324:406fd2029f23 4729 #define I2S_RCSR_FRIE_MASK 0x100u
mbed_official 324:406fd2029f23 4730 #define I2S_RCSR_FRIE_SHIFT 8
mbed_official 324:406fd2029f23 4731 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 324:406fd2029f23 4732 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 324:406fd2029f23 4733 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 324:406fd2029f23 4734 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 324:406fd2029f23 4735 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 324:406fd2029f23 4736 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 324:406fd2029f23 4737 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 324:406fd2029f23 4738 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 324:406fd2029f23 4739 #define I2S_RCSR_FRF_MASK 0x10000u
mbed_official 324:406fd2029f23 4740 #define I2S_RCSR_FRF_SHIFT 16
mbed_official 324:406fd2029f23 4741 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 324:406fd2029f23 4742 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 324:406fd2029f23 4743 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 324:406fd2029f23 4744 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 324:406fd2029f23 4745 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 324:406fd2029f23 4746 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 324:406fd2029f23 4747 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 324:406fd2029f23 4748 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 324:406fd2029f23 4749 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 324:406fd2029f23 4750 #define I2S_RCSR_SR_SHIFT 24
mbed_official 324:406fd2029f23 4751 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 324:406fd2029f23 4752 #define I2S_RCSR_FR_SHIFT 25
mbed_official 324:406fd2029f23 4753 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 324:406fd2029f23 4754 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 324:406fd2029f23 4755 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 324:406fd2029f23 4756 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 324:406fd2029f23 4757 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 324:406fd2029f23 4758 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 324:406fd2029f23 4759 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 324:406fd2029f23 4760 #define I2S_RCSR_RE_SHIFT 31
mbed_official 324:406fd2029f23 4761 /* RCR1 Bit Fields */
mbed_official 324:406fd2029f23 4762 #define I2S_RCR1_RFW_MASK 0x7u
mbed_official 324:406fd2029f23 4763 #define I2S_RCR1_RFW_SHIFT 0
mbed_official 324:406fd2029f23 4764 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
mbed_official 324:406fd2029f23 4765 /* RCR2 Bit Fields */
mbed_official 324:406fd2029f23 4766 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 324:406fd2029f23 4767 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 324:406fd2029f23 4768 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 324:406fd2029f23 4769 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 324:406fd2029f23 4770 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 324:406fd2029f23 4771 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 324:406fd2029f23 4772 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 324:406fd2029f23 4773 #define I2S_RCR2_MSEL_MASK 0xC000000u
mbed_official 324:406fd2029f23 4774 #define I2S_RCR2_MSEL_SHIFT 26
mbed_official 324:406fd2029f23 4775 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
mbed_official 324:406fd2029f23 4776 #define I2S_RCR2_BCI_MASK 0x10000000u
mbed_official 324:406fd2029f23 4777 #define I2S_RCR2_BCI_SHIFT 28
mbed_official 324:406fd2029f23 4778 #define I2S_RCR2_BCS_MASK 0x20000000u
mbed_official 324:406fd2029f23 4779 #define I2S_RCR2_BCS_SHIFT 29
mbed_official 324:406fd2029f23 4780 #define I2S_RCR2_SYNC_MASK 0xC0000000u
mbed_official 324:406fd2029f23 4781 #define I2S_RCR2_SYNC_SHIFT 30
mbed_official 324:406fd2029f23 4782 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
mbed_official 324:406fd2029f23 4783 /* RCR3 Bit Fields */
mbed_official 324:406fd2029f23 4784 #define I2S_RCR3_WDFL_MASK 0xFu
mbed_official 324:406fd2029f23 4785 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 324:406fd2029f23 4786 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
mbed_official 324:406fd2029f23 4787 #define I2S_RCR3_RCE_MASK 0x10000u
mbed_official 324:406fd2029f23 4788 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 324:406fd2029f23 4789 /* RCR4 Bit Fields */
mbed_official 324:406fd2029f23 4790 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 324:406fd2029f23 4791 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 324:406fd2029f23 4792 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 324:406fd2029f23 4793 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 324:406fd2029f23 4794 #define I2S_RCR4_ONDEM_MASK 0x4u
mbed_official 324:406fd2029f23 4795 #define I2S_RCR4_ONDEM_SHIFT 2
mbed_official 324:406fd2029f23 4796 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 324:406fd2029f23 4797 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 324:406fd2029f23 4798 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 324:406fd2029f23 4799 #define I2S_RCR4_MF_SHIFT 4
mbed_official 324:406fd2029f23 4800 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 324:406fd2029f23 4801 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 324:406fd2029f23 4802 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 324:406fd2029f23 4803 #define I2S_RCR4_FRSZ_MASK 0xF0000u
mbed_official 324:406fd2029f23 4804 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 324:406fd2029f23 4805 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
mbed_official 324:406fd2029f23 4806 #define I2S_RCR4_FPACK_MASK 0x3000000u
mbed_official 324:406fd2029f23 4807 #define I2S_RCR4_FPACK_SHIFT 24
mbed_official 324:406fd2029f23 4808 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
mbed_official 324:406fd2029f23 4809 #define I2S_RCR4_FCONT_MASK 0x10000000u
mbed_official 324:406fd2029f23 4810 #define I2S_RCR4_FCONT_SHIFT 28
mbed_official 324:406fd2029f23 4811 /* RCR5 Bit Fields */
mbed_official 324:406fd2029f23 4812 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 324:406fd2029f23 4813 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 324:406fd2029f23 4814 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 324:406fd2029f23 4815 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 324:406fd2029f23 4816 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 324:406fd2029f23 4817 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 324:406fd2029f23 4818 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 324:406fd2029f23 4819 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 324:406fd2029f23 4820 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 324:406fd2029f23 4821 /* RDR Bit Fields */
mbed_official 324:406fd2029f23 4822 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 4823 #define I2S_RDR_RDR_SHIFT 0
mbed_official 324:406fd2029f23 4824 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 324:406fd2029f23 4825 /* RFR Bit Fields */
mbed_official 324:406fd2029f23 4826 #define I2S_RFR_RFP_MASK 0xFu
mbed_official 324:406fd2029f23 4827 #define I2S_RFR_RFP_SHIFT 0
mbed_official 324:406fd2029f23 4828 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
mbed_official 324:406fd2029f23 4829 #define I2S_RFR_WFP_MASK 0xF0000u
mbed_official 324:406fd2029f23 4830 #define I2S_RFR_WFP_SHIFT 16
mbed_official 324:406fd2029f23 4831 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
mbed_official 324:406fd2029f23 4832 /* RMR Bit Fields */
mbed_official 324:406fd2029f23 4833 #define I2S_RMR_RWM_MASK 0xFFFFu
mbed_official 324:406fd2029f23 4834 #define I2S_RMR_RWM_SHIFT 0
mbed_official 324:406fd2029f23 4835 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 324:406fd2029f23 4836 /* MCR Bit Fields */
mbed_official 324:406fd2029f23 4837 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 324:406fd2029f23 4838 #define I2S_MCR_MICS_SHIFT 24
mbed_official 324:406fd2029f23 4839 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 324:406fd2029f23 4840 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 324:406fd2029f23 4841 #define I2S_MCR_MOE_SHIFT 30
mbed_official 324:406fd2029f23 4842 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 324:406fd2029f23 4843 #define I2S_MCR_DUF_SHIFT 31
mbed_official 324:406fd2029f23 4844 /* MDR Bit Fields */
mbed_official 324:406fd2029f23 4845 #define I2S_MDR_DIVIDE_MASK 0xFFFu
mbed_official 324:406fd2029f23 4846 #define I2S_MDR_DIVIDE_SHIFT 0
mbed_official 324:406fd2029f23 4847 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
mbed_official 324:406fd2029f23 4848 #define I2S_MDR_FRACT_MASK 0xFF000u
mbed_official 324:406fd2029f23 4849 #define I2S_MDR_FRACT_SHIFT 12
mbed_official 324:406fd2029f23 4850 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
mbed_official 324:406fd2029f23 4851
mbed_official 324:406fd2029f23 4852 /*!
mbed_official 324:406fd2029f23 4853 * @}
mbed_official 324:406fd2029f23 4854 */ /* end of group I2S_Register_Masks */
mbed_official 324:406fd2029f23 4855
mbed_official 324:406fd2029f23 4856
mbed_official 324:406fd2029f23 4857 /* I2S - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 4858 /** Peripheral I2S0 base address */
mbed_official 324:406fd2029f23 4859 #define I2S0_BASE (0x4002F000u)
mbed_official 324:406fd2029f23 4860 /** Peripheral I2S0 base pointer */
mbed_official 324:406fd2029f23 4861 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 324:406fd2029f23 4862 #define I2S0_BASE_PTR (I2S0)
mbed_official 324:406fd2029f23 4863 /** Array initializer of I2S peripheral base addresses */
mbed_official 324:406fd2029f23 4864 #define I2S_BASE_ADDRS { I2S0_BASE }
mbed_official 324:406fd2029f23 4865 /** Array initializer of I2S peripheral base pointers */
mbed_official 324:406fd2029f23 4866 #define I2S_BASE_PTRS { I2S0 }
mbed_official 324:406fd2029f23 4867 /** Interrupt vectors for the I2S peripheral type */
mbed_official 324:406fd2029f23 4868 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
mbed_official 324:406fd2029f23 4869 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
mbed_official 324:406fd2029f23 4870
mbed_official 324:406fd2029f23 4871 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4872 -- I2S - Register accessor macros
mbed_official 324:406fd2029f23 4873 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4874
mbed_official 324:406fd2029f23 4875 /*!
mbed_official 324:406fd2029f23 4876 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 324:406fd2029f23 4877 * @{
mbed_official 324:406fd2029f23 4878 */
mbed_official 324:406fd2029f23 4879
mbed_official 324:406fd2029f23 4880
mbed_official 324:406fd2029f23 4881 /* I2S - Register instance definitions */
mbed_official 324:406fd2029f23 4882 /* I2S0 */
mbed_official 324:406fd2029f23 4883 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
mbed_official 324:406fd2029f23 4884 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
mbed_official 324:406fd2029f23 4885 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
mbed_official 324:406fd2029f23 4886 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
mbed_official 324:406fd2029f23 4887 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
mbed_official 324:406fd2029f23 4888 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
mbed_official 324:406fd2029f23 4889 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
mbed_official 324:406fd2029f23 4890 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
mbed_official 324:406fd2029f23 4891 #define I2S0_TMR I2S_TMR_REG(I2S0)
mbed_official 324:406fd2029f23 4892 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
mbed_official 324:406fd2029f23 4893 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
mbed_official 324:406fd2029f23 4894 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
mbed_official 324:406fd2029f23 4895 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
mbed_official 324:406fd2029f23 4896 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
mbed_official 324:406fd2029f23 4897 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
mbed_official 324:406fd2029f23 4898 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
mbed_official 324:406fd2029f23 4899 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
mbed_official 324:406fd2029f23 4900 #define I2S0_RMR I2S_RMR_REG(I2S0)
mbed_official 324:406fd2029f23 4901 #define I2S0_MCR I2S_MCR_REG(I2S0)
mbed_official 324:406fd2029f23 4902 #define I2S0_MDR I2S_MDR_REG(I2S0)
mbed_official 324:406fd2029f23 4903
mbed_official 324:406fd2029f23 4904 /* I2S - Register array accessors */
mbed_official 324:406fd2029f23 4905 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
mbed_official 324:406fd2029f23 4906 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
mbed_official 324:406fd2029f23 4907 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
mbed_official 324:406fd2029f23 4908 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
mbed_official 324:406fd2029f23 4909
mbed_official 324:406fd2029f23 4910 /*!
mbed_official 324:406fd2029f23 4911 * @}
mbed_official 324:406fd2029f23 4912 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4913
mbed_official 324:406fd2029f23 4914
mbed_official 324:406fd2029f23 4915 /*!
mbed_official 324:406fd2029f23 4916 * @}
mbed_official 324:406fd2029f23 4917 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 4918
mbed_official 324:406fd2029f23 4919
mbed_official 324:406fd2029f23 4920 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4921 -- LLWU Peripheral Access Layer
mbed_official 324:406fd2029f23 4922 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4923
mbed_official 324:406fd2029f23 4924 /*!
mbed_official 324:406fd2029f23 4925 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 324:406fd2029f23 4926 * @{
mbed_official 324:406fd2029f23 4927 */
mbed_official 324:406fd2029f23 4928
mbed_official 324:406fd2029f23 4929 /** LLWU - Register Layout Typedef */
mbed_official 324:406fd2029f23 4930 typedef struct {
mbed_official 324:406fd2029f23 4931 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 324:406fd2029f23 4932 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 324:406fd2029f23 4933 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 324:406fd2029f23 4934 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 324:406fd2029f23 4935 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 324:406fd2029f23 4936 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 324:406fd2029f23 4937 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 324:406fd2029f23 4938 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 324:406fd2029f23 4939 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 324:406fd2029f23 4940 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 324:406fd2029f23 4941 } LLWU_Type, *LLWU_MemMapPtr;
mbed_official 324:406fd2029f23 4942
mbed_official 324:406fd2029f23 4943 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4944 -- LLWU - Register accessor macros
mbed_official 324:406fd2029f23 4945 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4946
mbed_official 324:406fd2029f23 4947 /*!
mbed_official 324:406fd2029f23 4948 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 324:406fd2029f23 4949 * @{
mbed_official 324:406fd2029f23 4950 */
mbed_official 324:406fd2029f23 4951
mbed_official 324:406fd2029f23 4952
mbed_official 324:406fd2029f23 4953 /* LLWU - Register accessors */
mbed_official 324:406fd2029f23 4954 #define LLWU_PE1_REG(base) ((base)->PE1)
mbed_official 324:406fd2029f23 4955 #define LLWU_PE2_REG(base) ((base)->PE2)
mbed_official 324:406fd2029f23 4956 #define LLWU_PE3_REG(base) ((base)->PE3)
mbed_official 324:406fd2029f23 4957 #define LLWU_PE4_REG(base) ((base)->PE4)
mbed_official 324:406fd2029f23 4958 #define LLWU_ME_REG(base) ((base)->ME)
mbed_official 324:406fd2029f23 4959 #define LLWU_F1_REG(base) ((base)->F1)
mbed_official 324:406fd2029f23 4960 #define LLWU_F2_REG(base) ((base)->F2)
mbed_official 324:406fd2029f23 4961 #define LLWU_F3_REG(base) ((base)->F3)
mbed_official 324:406fd2029f23 4962 #define LLWU_FILT1_REG(base) ((base)->FILT1)
mbed_official 324:406fd2029f23 4963 #define LLWU_FILT2_REG(base) ((base)->FILT2)
mbed_official 324:406fd2029f23 4964
mbed_official 324:406fd2029f23 4965 /*!
mbed_official 324:406fd2029f23 4966 * @}
mbed_official 324:406fd2029f23 4967 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 4968
mbed_official 324:406fd2029f23 4969
mbed_official 324:406fd2029f23 4970 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 4971 -- LLWU Register Masks
mbed_official 324:406fd2029f23 4972 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 4973
mbed_official 324:406fd2029f23 4974 /*!
mbed_official 324:406fd2029f23 4975 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 324:406fd2029f23 4976 * @{
mbed_official 324:406fd2029f23 4977 */
mbed_official 324:406fd2029f23 4978
mbed_official 324:406fd2029f23 4979 /* PE1 Bit Fields */
mbed_official 324:406fd2029f23 4980 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 324:406fd2029f23 4981 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 324:406fd2029f23 4982 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 324:406fd2029f23 4983 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 324:406fd2029f23 4984 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 324:406fd2029f23 4985 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 324:406fd2029f23 4986 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 324:406fd2029f23 4987 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 324:406fd2029f23 4988 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 324:406fd2029f23 4989 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 324:406fd2029f23 4990 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 324:406fd2029f23 4991 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 324:406fd2029f23 4992 /* PE2 Bit Fields */
mbed_official 324:406fd2029f23 4993 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 324:406fd2029f23 4994 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 324:406fd2029f23 4995 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 324:406fd2029f23 4996 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 324:406fd2029f23 4997 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 324:406fd2029f23 4998 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 324:406fd2029f23 4999 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 324:406fd2029f23 5000 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 324:406fd2029f23 5001 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 324:406fd2029f23 5002 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 324:406fd2029f23 5003 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 324:406fd2029f23 5004 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 324:406fd2029f23 5005 /* PE3 Bit Fields */
mbed_official 324:406fd2029f23 5006 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 324:406fd2029f23 5007 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 324:406fd2029f23 5008 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 324:406fd2029f23 5009 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 324:406fd2029f23 5010 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 324:406fd2029f23 5011 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 324:406fd2029f23 5012 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 324:406fd2029f23 5013 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 324:406fd2029f23 5014 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 324:406fd2029f23 5015 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 324:406fd2029f23 5016 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 324:406fd2029f23 5017 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 324:406fd2029f23 5018 /* PE4 Bit Fields */
mbed_official 324:406fd2029f23 5019 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 324:406fd2029f23 5020 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 324:406fd2029f23 5021 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 324:406fd2029f23 5022 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 324:406fd2029f23 5023 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 324:406fd2029f23 5024 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 324:406fd2029f23 5025 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 324:406fd2029f23 5026 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 324:406fd2029f23 5027 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 324:406fd2029f23 5028 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 324:406fd2029f23 5029 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 324:406fd2029f23 5030 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 324:406fd2029f23 5031 /* ME Bit Fields */
mbed_official 324:406fd2029f23 5032 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 324:406fd2029f23 5033 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 324:406fd2029f23 5034 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 324:406fd2029f23 5035 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 324:406fd2029f23 5036 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 324:406fd2029f23 5037 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 324:406fd2029f23 5038 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 324:406fd2029f23 5039 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 324:406fd2029f23 5040 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 324:406fd2029f23 5041 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 324:406fd2029f23 5042 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 324:406fd2029f23 5043 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 324:406fd2029f23 5044 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 324:406fd2029f23 5045 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 324:406fd2029f23 5046 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 324:406fd2029f23 5047 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 324:406fd2029f23 5048 /* F1 Bit Fields */
mbed_official 324:406fd2029f23 5049 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 324:406fd2029f23 5050 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 324:406fd2029f23 5051 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 324:406fd2029f23 5052 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 324:406fd2029f23 5053 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 324:406fd2029f23 5054 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 324:406fd2029f23 5055 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 324:406fd2029f23 5056 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 324:406fd2029f23 5057 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 324:406fd2029f23 5058 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 324:406fd2029f23 5059 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 324:406fd2029f23 5060 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 324:406fd2029f23 5061 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 324:406fd2029f23 5062 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 324:406fd2029f23 5063 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 324:406fd2029f23 5064 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 324:406fd2029f23 5065 /* F2 Bit Fields */
mbed_official 324:406fd2029f23 5066 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 324:406fd2029f23 5067 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 324:406fd2029f23 5068 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 324:406fd2029f23 5069 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 324:406fd2029f23 5070 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 324:406fd2029f23 5071 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 324:406fd2029f23 5072 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 324:406fd2029f23 5073 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 324:406fd2029f23 5074 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 324:406fd2029f23 5075 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 324:406fd2029f23 5076 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 324:406fd2029f23 5077 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 324:406fd2029f23 5078 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 324:406fd2029f23 5079 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 324:406fd2029f23 5080 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 324:406fd2029f23 5081 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 324:406fd2029f23 5082 /* F3 Bit Fields */
mbed_official 324:406fd2029f23 5083 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 324:406fd2029f23 5084 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 324:406fd2029f23 5085 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 324:406fd2029f23 5086 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 324:406fd2029f23 5087 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 324:406fd2029f23 5088 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 324:406fd2029f23 5089 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 324:406fd2029f23 5090 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 324:406fd2029f23 5091 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 324:406fd2029f23 5092 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 324:406fd2029f23 5093 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 324:406fd2029f23 5094 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 324:406fd2029f23 5095 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 324:406fd2029f23 5096 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 324:406fd2029f23 5097 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 324:406fd2029f23 5098 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 324:406fd2029f23 5099 /* FILT1 Bit Fields */
mbed_official 324:406fd2029f23 5100 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 324:406fd2029f23 5101 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 324:406fd2029f23 5102 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 324:406fd2029f23 5103 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 324:406fd2029f23 5104 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 324:406fd2029f23 5105 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 324:406fd2029f23 5106 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 324:406fd2029f23 5107 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 324:406fd2029f23 5108 /* FILT2 Bit Fields */
mbed_official 324:406fd2029f23 5109 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 324:406fd2029f23 5110 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 324:406fd2029f23 5111 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 324:406fd2029f23 5112 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 324:406fd2029f23 5113 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 324:406fd2029f23 5114 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 324:406fd2029f23 5115 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 324:406fd2029f23 5116 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 324:406fd2029f23 5117
mbed_official 324:406fd2029f23 5118 /*!
mbed_official 324:406fd2029f23 5119 * @}
mbed_official 324:406fd2029f23 5120 */ /* end of group LLWU_Register_Masks */
mbed_official 324:406fd2029f23 5121
mbed_official 324:406fd2029f23 5122
mbed_official 324:406fd2029f23 5123 /* LLWU - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 5124 /** Peripheral LLWU base address */
mbed_official 324:406fd2029f23 5125 #define LLWU_BASE (0x4007C000u)
mbed_official 324:406fd2029f23 5126 /** Peripheral LLWU base pointer */
mbed_official 324:406fd2029f23 5127 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 324:406fd2029f23 5128 #define LLWU_BASE_PTR (LLWU)
mbed_official 324:406fd2029f23 5129 /** Array initializer of LLWU peripheral base addresses */
mbed_official 324:406fd2029f23 5130 #define LLWU_BASE_ADDRS { LLWU_BASE }
mbed_official 324:406fd2029f23 5131 /** Array initializer of LLWU peripheral base pointers */
mbed_official 324:406fd2029f23 5132 #define LLWU_BASE_PTRS { LLWU }
mbed_official 324:406fd2029f23 5133 /** Interrupt vectors for the LLWU peripheral type */
mbed_official 324:406fd2029f23 5134 #define LLWU_IRQS { LLW_IRQn }
mbed_official 324:406fd2029f23 5135
mbed_official 324:406fd2029f23 5136 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5137 -- LLWU - Register accessor macros
mbed_official 324:406fd2029f23 5138 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5139
mbed_official 324:406fd2029f23 5140 /*!
mbed_official 324:406fd2029f23 5141 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 324:406fd2029f23 5142 * @{
mbed_official 324:406fd2029f23 5143 */
mbed_official 324:406fd2029f23 5144
mbed_official 324:406fd2029f23 5145
mbed_official 324:406fd2029f23 5146 /* LLWU - Register instance definitions */
mbed_official 324:406fd2029f23 5147 /* LLWU */
mbed_official 324:406fd2029f23 5148 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
mbed_official 324:406fd2029f23 5149 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
mbed_official 324:406fd2029f23 5150 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
mbed_official 324:406fd2029f23 5151 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
mbed_official 324:406fd2029f23 5152 #define LLWU_ME LLWU_ME_REG(LLWU)
mbed_official 324:406fd2029f23 5153 #define LLWU_F1 LLWU_F1_REG(LLWU)
mbed_official 324:406fd2029f23 5154 #define LLWU_F2 LLWU_F2_REG(LLWU)
mbed_official 324:406fd2029f23 5155 #define LLWU_F3 LLWU_F3_REG(LLWU)
mbed_official 324:406fd2029f23 5156 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
mbed_official 324:406fd2029f23 5157 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
mbed_official 324:406fd2029f23 5158
mbed_official 324:406fd2029f23 5159 /*!
mbed_official 324:406fd2029f23 5160 * @}
mbed_official 324:406fd2029f23 5161 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5162
mbed_official 324:406fd2029f23 5163
mbed_official 324:406fd2029f23 5164 /*!
mbed_official 324:406fd2029f23 5165 * @}
mbed_official 324:406fd2029f23 5166 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 5167
mbed_official 324:406fd2029f23 5168
mbed_official 324:406fd2029f23 5169 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5170 -- LPTMR Peripheral Access Layer
mbed_official 324:406fd2029f23 5171 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5172
mbed_official 324:406fd2029f23 5173 /*!
mbed_official 324:406fd2029f23 5174 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 324:406fd2029f23 5175 * @{
mbed_official 324:406fd2029f23 5176 */
mbed_official 324:406fd2029f23 5177
mbed_official 324:406fd2029f23 5178 /** LPTMR - Register Layout Typedef */
mbed_official 324:406fd2029f23 5179 typedef struct {
mbed_official 324:406fd2029f23 5180 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 324:406fd2029f23 5181 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 324:406fd2029f23 5182 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 324:406fd2029f23 5183 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 324:406fd2029f23 5184 } LPTMR_Type, *LPTMR_MemMapPtr;
mbed_official 324:406fd2029f23 5185
mbed_official 324:406fd2029f23 5186 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5187 -- LPTMR - Register accessor macros
mbed_official 324:406fd2029f23 5188 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5189
mbed_official 324:406fd2029f23 5190 /*!
mbed_official 324:406fd2029f23 5191 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 324:406fd2029f23 5192 * @{
mbed_official 324:406fd2029f23 5193 */
mbed_official 324:406fd2029f23 5194
mbed_official 324:406fd2029f23 5195
mbed_official 324:406fd2029f23 5196 /* LPTMR - Register accessors */
mbed_official 324:406fd2029f23 5197 #define LPTMR_CSR_REG(base) ((base)->CSR)
mbed_official 324:406fd2029f23 5198 #define LPTMR_PSR_REG(base) ((base)->PSR)
mbed_official 324:406fd2029f23 5199 #define LPTMR_CMR_REG(base) ((base)->CMR)
mbed_official 324:406fd2029f23 5200 #define LPTMR_CNR_REG(base) ((base)->CNR)
mbed_official 324:406fd2029f23 5201
mbed_official 324:406fd2029f23 5202 /*!
mbed_official 324:406fd2029f23 5203 * @}
mbed_official 324:406fd2029f23 5204 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5205
mbed_official 324:406fd2029f23 5206
mbed_official 324:406fd2029f23 5207 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5208 -- LPTMR Register Masks
mbed_official 324:406fd2029f23 5209 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5210
mbed_official 324:406fd2029f23 5211 /*!
mbed_official 324:406fd2029f23 5212 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 324:406fd2029f23 5213 * @{
mbed_official 324:406fd2029f23 5214 */
mbed_official 324:406fd2029f23 5215
mbed_official 324:406fd2029f23 5216 /* CSR Bit Fields */
mbed_official 324:406fd2029f23 5217 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 324:406fd2029f23 5218 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 324:406fd2029f23 5219 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 324:406fd2029f23 5220 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 324:406fd2029f23 5221 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 324:406fd2029f23 5222 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 324:406fd2029f23 5223 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 324:406fd2029f23 5224 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 324:406fd2029f23 5225 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 324:406fd2029f23 5226 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 324:406fd2029f23 5227 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 324:406fd2029f23 5228 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 324:406fd2029f23 5229 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 324:406fd2029f23 5230 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 324:406fd2029f23 5231 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 324:406fd2029f23 5232 /* PSR Bit Fields */
mbed_official 324:406fd2029f23 5233 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 324:406fd2029f23 5234 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 324:406fd2029f23 5235 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 324:406fd2029f23 5236 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 324:406fd2029f23 5237 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 324:406fd2029f23 5238 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 324:406fd2029f23 5239 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 324:406fd2029f23 5240 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 324:406fd2029f23 5241 /* CMR Bit Fields */
mbed_official 324:406fd2029f23 5242 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 324:406fd2029f23 5243 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 324:406fd2029f23 5244 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 324:406fd2029f23 5245 /* CNR Bit Fields */
mbed_official 324:406fd2029f23 5246 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 324:406fd2029f23 5247 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 324:406fd2029f23 5248 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 324:406fd2029f23 5249
mbed_official 324:406fd2029f23 5250 /*!
mbed_official 324:406fd2029f23 5251 * @}
mbed_official 324:406fd2029f23 5252 */ /* end of group LPTMR_Register_Masks */
mbed_official 324:406fd2029f23 5253
mbed_official 324:406fd2029f23 5254
mbed_official 324:406fd2029f23 5255 /* LPTMR - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 5256 /** Peripheral LPTMR0 base address */
mbed_official 324:406fd2029f23 5257 #define LPTMR0_BASE (0x40040000u)
mbed_official 324:406fd2029f23 5258 /** Peripheral LPTMR0 base pointer */
mbed_official 324:406fd2029f23 5259 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 324:406fd2029f23 5260 #define LPTMR0_BASE_PTR (LPTMR0)
mbed_official 324:406fd2029f23 5261 /** Array initializer of LPTMR peripheral base addresses */
mbed_official 324:406fd2029f23 5262 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
mbed_official 324:406fd2029f23 5263 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 324:406fd2029f23 5264 #define LPTMR_BASE_PTRS { LPTMR0 }
mbed_official 324:406fd2029f23 5265 /** Interrupt vectors for the LPTMR peripheral type */
mbed_official 324:406fd2029f23 5266 #define LPTMR_IRQS { LPTimer_IRQn }
mbed_official 324:406fd2029f23 5267
mbed_official 324:406fd2029f23 5268 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5269 -- LPTMR - Register accessor macros
mbed_official 324:406fd2029f23 5270 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5271
mbed_official 324:406fd2029f23 5272 /*!
mbed_official 324:406fd2029f23 5273 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 324:406fd2029f23 5274 * @{
mbed_official 324:406fd2029f23 5275 */
mbed_official 324:406fd2029f23 5276
mbed_official 324:406fd2029f23 5277
mbed_official 324:406fd2029f23 5278 /* LPTMR - Register instance definitions */
mbed_official 324:406fd2029f23 5279 /* LPTMR0 */
mbed_official 324:406fd2029f23 5280 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
mbed_official 324:406fd2029f23 5281 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
mbed_official 324:406fd2029f23 5282 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
mbed_official 324:406fd2029f23 5283 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
mbed_official 324:406fd2029f23 5284
mbed_official 324:406fd2029f23 5285 /*!
mbed_official 324:406fd2029f23 5286 * @}
mbed_official 324:406fd2029f23 5287 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5288
mbed_official 324:406fd2029f23 5289
mbed_official 324:406fd2029f23 5290 /*!
mbed_official 324:406fd2029f23 5291 * @}
mbed_official 324:406fd2029f23 5292 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 5293
mbed_official 324:406fd2029f23 5294
mbed_official 324:406fd2029f23 5295 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5296 -- LPUART Peripheral Access Layer
mbed_official 324:406fd2029f23 5297 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5298
mbed_official 324:406fd2029f23 5299 /*!
mbed_official 324:406fd2029f23 5300 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
mbed_official 324:406fd2029f23 5301 * @{
mbed_official 324:406fd2029f23 5302 */
mbed_official 324:406fd2029f23 5303
mbed_official 324:406fd2029f23 5304 /** LPUART - Register Layout Typedef */
mbed_official 324:406fd2029f23 5305 typedef struct {
mbed_official 324:406fd2029f23 5306 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
mbed_official 324:406fd2029f23 5307 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
mbed_official 324:406fd2029f23 5308 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
mbed_official 324:406fd2029f23 5309 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
mbed_official 324:406fd2029f23 5310 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
mbed_official 324:406fd2029f23 5311 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
mbed_official 324:406fd2029f23 5312 } LPUART_Type, *LPUART_MemMapPtr;
mbed_official 324:406fd2029f23 5313
mbed_official 324:406fd2029f23 5314 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5315 -- LPUART - Register accessor macros
mbed_official 324:406fd2029f23 5316 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5317
mbed_official 324:406fd2029f23 5318 /*!
mbed_official 324:406fd2029f23 5319 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
mbed_official 324:406fd2029f23 5320 * @{
mbed_official 324:406fd2029f23 5321 */
mbed_official 324:406fd2029f23 5322
mbed_official 324:406fd2029f23 5323
mbed_official 324:406fd2029f23 5324 /* LPUART - Register accessors */
mbed_official 324:406fd2029f23 5325 #define LPUART_BAUD_REG(base) ((base)->BAUD)
mbed_official 324:406fd2029f23 5326 #define LPUART_STAT_REG(base) ((base)->STAT)
mbed_official 324:406fd2029f23 5327 #define LPUART_CTRL_REG(base) ((base)->CTRL)
mbed_official 324:406fd2029f23 5328 #define LPUART_DATA_REG(base) ((base)->DATA)
mbed_official 324:406fd2029f23 5329 #define LPUART_MATCH_REG(base) ((base)->MATCH)
mbed_official 324:406fd2029f23 5330 #define LPUART_MODIR_REG(base) ((base)->MODIR)
mbed_official 324:406fd2029f23 5331
mbed_official 324:406fd2029f23 5332 /*!
mbed_official 324:406fd2029f23 5333 * @}
mbed_official 324:406fd2029f23 5334 */ /* end of group LPUART_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5335
mbed_official 324:406fd2029f23 5336
mbed_official 324:406fd2029f23 5337 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5338 -- LPUART Register Masks
mbed_official 324:406fd2029f23 5339 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5340
mbed_official 324:406fd2029f23 5341 /*!
mbed_official 324:406fd2029f23 5342 * @addtogroup LPUART_Register_Masks LPUART Register Masks
mbed_official 324:406fd2029f23 5343 * @{
mbed_official 324:406fd2029f23 5344 */
mbed_official 324:406fd2029f23 5345
mbed_official 324:406fd2029f23 5346 /* BAUD Bit Fields */
mbed_official 324:406fd2029f23 5347 #define LPUART_BAUD_SBR_MASK 0x1FFFu
mbed_official 324:406fd2029f23 5348 #define LPUART_BAUD_SBR_SHIFT 0
mbed_official 324:406fd2029f23 5349 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
mbed_official 324:406fd2029f23 5350 #define LPUART_BAUD_SBNS_MASK 0x2000u
mbed_official 324:406fd2029f23 5351 #define LPUART_BAUD_SBNS_SHIFT 13
mbed_official 324:406fd2029f23 5352 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
mbed_official 324:406fd2029f23 5353 #define LPUART_BAUD_RXEDGIE_SHIFT 14
mbed_official 324:406fd2029f23 5354 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
mbed_official 324:406fd2029f23 5355 #define LPUART_BAUD_LBKDIE_SHIFT 15
mbed_official 324:406fd2029f23 5356 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
mbed_official 324:406fd2029f23 5357 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
mbed_official 324:406fd2029f23 5358 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
mbed_official 324:406fd2029f23 5359 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
mbed_official 324:406fd2029f23 5360 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
mbed_official 324:406fd2029f23 5361 #define LPUART_BAUD_MATCFG_SHIFT 18
mbed_official 324:406fd2029f23 5362 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
mbed_official 324:406fd2029f23 5363 #define LPUART_BAUD_RDMAE_MASK 0x200000u
mbed_official 324:406fd2029f23 5364 #define LPUART_BAUD_RDMAE_SHIFT 21
mbed_official 324:406fd2029f23 5365 #define LPUART_BAUD_TDMAE_MASK 0x800000u
mbed_official 324:406fd2029f23 5366 #define LPUART_BAUD_TDMAE_SHIFT 23
mbed_official 324:406fd2029f23 5367 #define LPUART_BAUD_OSR_MASK 0x1F000000u
mbed_official 324:406fd2029f23 5368 #define LPUART_BAUD_OSR_SHIFT 24
mbed_official 324:406fd2029f23 5369 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
mbed_official 324:406fd2029f23 5370 #define LPUART_BAUD_M10_MASK 0x20000000u
mbed_official 324:406fd2029f23 5371 #define LPUART_BAUD_M10_SHIFT 29
mbed_official 324:406fd2029f23 5372 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
mbed_official 324:406fd2029f23 5373 #define LPUART_BAUD_MAEN2_SHIFT 30
mbed_official 324:406fd2029f23 5374 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
mbed_official 324:406fd2029f23 5375 #define LPUART_BAUD_MAEN1_SHIFT 31
mbed_official 324:406fd2029f23 5376 /* STAT Bit Fields */
mbed_official 324:406fd2029f23 5377 #define LPUART_STAT_MA2F_MASK 0x4000u
mbed_official 324:406fd2029f23 5378 #define LPUART_STAT_MA2F_SHIFT 14
mbed_official 324:406fd2029f23 5379 #define LPUART_STAT_MA1F_MASK 0x8000u
mbed_official 324:406fd2029f23 5380 #define LPUART_STAT_MA1F_SHIFT 15
mbed_official 324:406fd2029f23 5381 #define LPUART_STAT_PF_MASK 0x10000u
mbed_official 324:406fd2029f23 5382 #define LPUART_STAT_PF_SHIFT 16
mbed_official 324:406fd2029f23 5383 #define LPUART_STAT_FE_MASK 0x20000u
mbed_official 324:406fd2029f23 5384 #define LPUART_STAT_FE_SHIFT 17
mbed_official 324:406fd2029f23 5385 #define LPUART_STAT_NF_MASK 0x40000u
mbed_official 324:406fd2029f23 5386 #define LPUART_STAT_NF_SHIFT 18
mbed_official 324:406fd2029f23 5387 #define LPUART_STAT_OR_MASK 0x80000u
mbed_official 324:406fd2029f23 5388 #define LPUART_STAT_OR_SHIFT 19
mbed_official 324:406fd2029f23 5389 #define LPUART_STAT_IDLE_MASK 0x100000u
mbed_official 324:406fd2029f23 5390 #define LPUART_STAT_IDLE_SHIFT 20
mbed_official 324:406fd2029f23 5391 #define LPUART_STAT_RDRF_MASK 0x200000u
mbed_official 324:406fd2029f23 5392 #define LPUART_STAT_RDRF_SHIFT 21
mbed_official 324:406fd2029f23 5393 #define LPUART_STAT_TC_MASK 0x400000u
mbed_official 324:406fd2029f23 5394 #define LPUART_STAT_TC_SHIFT 22
mbed_official 324:406fd2029f23 5395 #define LPUART_STAT_TDRE_MASK 0x800000u
mbed_official 324:406fd2029f23 5396 #define LPUART_STAT_TDRE_SHIFT 23
mbed_official 324:406fd2029f23 5397 #define LPUART_STAT_RAF_MASK 0x1000000u
mbed_official 324:406fd2029f23 5398 #define LPUART_STAT_RAF_SHIFT 24
mbed_official 324:406fd2029f23 5399 #define LPUART_STAT_LBKDE_MASK 0x2000000u
mbed_official 324:406fd2029f23 5400 #define LPUART_STAT_LBKDE_SHIFT 25
mbed_official 324:406fd2029f23 5401 #define LPUART_STAT_BRK13_MASK 0x4000000u
mbed_official 324:406fd2029f23 5402 #define LPUART_STAT_BRK13_SHIFT 26
mbed_official 324:406fd2029f23 5403 #define LPUART_STAT_RWUID_MASK 0x8000000u
mbed_official 324:406fd2029f23 5404 #define LPUART_STAT_RWUID_SHIFT 27
mbed_official 324:406fd2029f23 5405 #define LPUART_STAT_RXINV_MASK 0x10000000u
mbed_official 324:406fd2029f23 5406 #define LPUART_STAT_RXINV_SHIFT 28
mbed_official 324:406fd2029f23 5407 #define LPUART_STAT_MSBF_MASK 0x20000000u
mbed_official 324:406fd2029f23 5408 #define LPUART_STAT_MSBF_SHIFT 29
mbed_official 324:406fd2029f23 5409 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
mbed_official 324:406fd2029f23 5410 #define LPUART_STAT_RXEDGIF_SHIFT 30
mbed_official 324:406fd2029f23 5411 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
mbed_official 324:406fd2029f23 5412 #define LPUART_STAT_LBKDIF_SHIFT 31
mbed_official 324:406fd2029f23 5413 /* CTRL Bit Fields */
mbed_official 324:406fd2029f23 5414 #define LPUART_CTRL_PT_MASK 0x1u
mbed_official 324:406fd2029f23 5415 #define LPUART_CTRL_PT_SHIFT 0
mbed_official 324:406fd2029f23 5416 #define LPUART_CTRL_PE_MASK 0x2u
mbed_official 324:406fd2029f23 5417 #define LPUART_CTRL_PE_SHIFT 1
mbed_official 324:406fd2029f23 5418 #define LPUART_CTRL_ILT_MASK 0x4u
mbed_official 324:406fd2029f23 5419 #define LPUART_CTRL_ILT_SHIFT 2
mbed_official 324:406fd2029f23 5420 #define LPUART_CTRL_WAKE_MASK 0x8u
mbed_official 324:406fd2029f23 5421 #define LPUART_CTRL_WAKE_SHIFT 3
mbed_official 324:406fd2029f23 5422 #define LPUART_CTRL_M_MASK 0x10u
mbed_official 324:406fd2029f23 5423 #define LPUART_CTRL_M_SHIFT 4
mbed_official 324:406fd2029f23 5424 #define LPUART_CTRL_RSRC_MASK 0x20u
mbed_official 324:406fd2029f23 5425 #define LPUART_CTRL_RSRC_SHIFT 5
mbed_official 324:406fd2029f23 5426 #define LPUART_CTRL_DOZEEN_MASK 0x40u
mbed_official 324:406fd2029f23 5427 #define LPUART_CTRL_DOZEEN_SHIFT 6
mbed_official 324:406fd2029f23 5428 #define LPUART_CTRL_LOOPS_MASK 0x80u
mbed_official 324:406fd2029f23 5429 #define LPUART_CTRL_LOOPS_SHIFT 7
mbed_official 324:406fd2029f23 5430 #define LPUART_CTRL_IDLECFG_MASK 0x700u
mbed_official 324:406fd2029f23 5431 #define LPUART_CTRL_IDLECFG_SHIFT 8
mbed_official 324:406fd2029f23 5432 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
mbed_official 324:406fd2029f23 5433 #define LPUART_CTRL_MA2IE_MASK 0x4000u
mbed_official 324:406fd2029f23 5434 #define LPUART_CTRL_MA2IE_SHIFT 14
mbed_official 324:406fd2029f23 5435 #define LPUART_CTRL_MA1IE_MASK 0x8000u
mbed_official 324:406fd2029f23 5436 #define LPUART_CTRL_MA1IE_SHIFT 15
mbed_official 324:406fd2029f23 5437 #define LPUART_CTRL_SBK_MASK 0x10000u
mbed_official 324:406fd2029f23 5438 #define LPUART_CTRL_SBK_SHIFT 16
mbed_official 324:406fd2029f23 5439 #define LPUART_CTRL_RWU_MASK 0x20000u
mbed_official 324:406fd2029f23 5440 #define LPUART_CTRL_RWU_SHIFT 17
mbed_official 324:406fd2029f23 5441 #define LPUART_CTRL_RE_MASK 0x40000u
mbed_official 324:406fd2029f23 5442 #define LPUART_CTRL_RE_SHIFT 18
mbed_official 324:406fd2029f23 5443 #define LPUART_CTRL_TE_MASK 0x80000u
mbed_official 324:406fd2029f23 5444 #define LPUART_CTRL_TE_SHIFT 19
mbed_official 324:406fd2029f23 5445 #define LPUART_CTRL_ILIE_MASK 0x100000u
mbed_official 324:406fd2029f23 5446 #define LPUART_CTRL_ILIE_SHIFT 20
mbed_official 324:406fd2029f23 5447 #define LPUART_CTRL_RIE_MASK 0x200000u
mbed_official 324:406fd2029f23 5448 #define LPUART_CTRL_RIE_SHIFT 21
mbed_official 324:406fd2029f23 5449 #define LPUART_CTRL_TCIE_MASK 0x400000u
mbed_official 324:406fd2029f23 5450 #define LPUART_CTRL_TCIE_SHIFT 22
mbed_official 324:406fd2029f23 5451 #define LPUART_CTRL_TIE_MASK 0x800000u
mbed_official 324:406fd2029f23 5452 #define LPUART_CTRL_TIE_SHIFT 23
mbed_official 324:406fd2029f23 5453 #define LPUART_CTRL_PEIE_MASK 0x1000000u
mbed_official 324:406fd2029f23 5454 #define LPUART_CTRL_PEIE_SHIFT 24
mbed_official 324:406fd2029f23 5455 #define LPUART_CTRL_FEIE_MASK 0x2000000u
mbed_official 324:406fd2029f23 5456 #define LPUART_CTRL_FEIE_SHIFT 25
mbed_official 324:406fd2029f23 5457 #define LPUART_CTRL_NEIE_MASK 0x4000000u
mbed_official 324:406fd2029f23 5458 #define LPUART_CTRL_NEIE_SHIFT 26
mbed_official 324:406fd2029f23 5459 #define LPUART_CTRL_ORIE_MASK 0x8000000u
mbed_official 324:406fd2029f23 5460 #define LPUART_CTRL_ORIE_SHIFT 27
mbed_official 324:406fd2029f23 5461 #define LPUART_CTRL_TXINV_MASK 0x10000000u
mbed_official 324:406fd2029f23 5462 #define LPUART_CTRL_TXINV_SHIFT 28
mbed_official 324:406fd2029f23 5463 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
mbed_official 324:406fd2029f23 5464 #define LPUART_CTRL_TXDIR_SHIFT 29
mbed_official 324:406fd2029f23 5465 #define LPUART_CTRL_R9T8_MASK 0x40000000u
mbed_official 324:406fd2029f23 5466 #define LPUART_CTRL_R9T8_SHIFT 30
mbed_official 324:406fd2029f23 5467 #define LPUART_CTRL_R8T9_MASK 0x80000000u
mbed_official 324:406fd2029f23 5468 #define LPUART_CTRL_R8T9_SHIFT 31
mbed_official 324:406fd2029f23 5469 /* DATA Bit Fields */
mbed_official 324:406fd2029f23 5470 #define LPUART_DATA_R0T0_MASK 0x1u
mbed_official 324:406fd2029f23 5471 #define LPUART_DATA_R0T0_SHIFT 0
mbed_official 324:406fd2029f23 5472 #define LPUART_DATA_R1T1_MASK 0x2u
mbed_official 324:406fd2029f23 5473 #define LPUART_DATA_R1T1_SHIFT 1
mbed_official 324:406fd2029f23 5474 #define LPUART_DATA_R2T2_MASK 0x4u
mbed_official 324:406fd2029f23 5475 #define LPUART_DATA_R2T2_SHIFT 2
mbed_official 324:406fd2029f23 5476 #define LPUART_DATA_R3T3_MASK 0x8u
mbed_official 324:406fd2029f23 5477 #define LPUART_DATA_R3T3_SHIFT 3
mbed_official 324:406fd2029f23 5478 #define LPUART_DATA_R4T4_MASK 0x10u
mbed_official 324:406fd2029f23 5479 #define LPUART_DATA_R4T4_SHIFT 4
mbed_official 324:406fd2029f23 5480 #define LPUART_DATA_R5T5_MASK 0x20u
mbed_official 324:406fd2029f23 5481 #define LPUART_DATA_R5T5_SHIFT 5
mbed_official 324:406fd2029f23 5482 #define LPUART_DATA_R6T6_MASK 0x40u
mbed_official 324:406fd2029f23 5483 #define LPUART_DATA_R6T6_SHIFT 6
mbed_official 324:406fd2029f23 5484 #define LPUART_DATA_R7T7_MASK 0x80u
mbed_official 324:406fd2029f23 5485 #define LPUART_DATA_R7T7_SHIFT 7
mbed_official 324:406fd2029f23 5486 #define LPUART_DATA_R8T8_MASK 0x100u
mbed_official 324:406fd2029f23 5487 #define LPUART_DATA_R8T8_SHIFT 8
mbed_official 324:406fd2029f23 5488 #define LPUART_DATA_R9T9_MASK 0x200u
mbed_official 324:406fd2029f23 5489 #define LPUART_DATA_R9T9_SHIFT 9
mbed_official 324:406fd2029f23 5490 #define LPUART_DATA_IDLINE_MASK 0x800u
mbed_official 324:406fd2029f23 5491 #define LPUART_DATA_IDLINE_SHIFT 11
mbed_official 324:406fd2029f23 5492 #define LPUART_DATA_RXEMPT_MASK 0x1000u
mbed_official 324:406fd2029f23 5493 #define LPUART_DATA_RXEMPT_SHIFT 12
mbed_official 324:406fd2029f23 5494 #define LPUART_DATA_FRETSC_MASK 0x2000u
mbed_official 324:406fd2029f23 5495 #define LPUART_DATA_FRETSC_SHIFT 13
mbed_official 324:406fd2029f23 5496 #define LPUART_DATA_PARITYE_MASK 0x4000u
mbed_official 324:406fd2029f23 5497 #define LPUART_DATA_PARITYE_SHIFT 14
mbed_official 324:406fd2029f23 5498 #define LPUART_DATA_NOISY_MASK 0x8000u
mbed_official 324:406fd2029f23 5499 #define LPUART_DATA_NOISY_SHIFT 15
mbed_official 324:406fd2029f23 5500 /* MATCH Bit Fields */
mbed_official 324:406fd2029f23 5501 #define LPUART_MATCH_MA1_MASK 0x3FFu
mbed_official 324:406fd2029f23 5502 #define LPUART_MATCH_MA1_SHIFT 0
mbed_official 324:406fd2029f23 5503 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
mbed_official 324:406fd2029f23 5504 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
mbed_official 324:406fd2029f23 5505 #define LPUART_MATCH_MA2_SHIFT 16
mbed_official 324:406fd2029f23 5506 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
mbed_official 324:406fd2029f23 5507 /* MODIR Bit Fields */
mbed_official 324:406fd2029f23 5508 #define LPUART_MODIR_TXCTSE_MASK 0x1u
mbed_official 324:406fd2029f23 5509 #define LPUART_MODIR_TXCTSE_SHIFT 0
mbed_official 324:406fd2029f23 5510 #define LPUART_MODIR_TXRTSE_MASK 0x2u
mbed_official 324:406fd2029f23 5511 #define LPUART_MODIR_TXRTSE_SHIFT 1
mbed_official 324:406fd2029f23 5512 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
mbed_official 324:406fd2029f23 5513 #define LPUART_MODIR_TXRTSPOL_SHIFT 2
mbed_official 324:406fd2029f23 5514 #define LPUART_MODIR_RXRTSE_MASK 0x8u
mbed_official 324:406fd2029f23 5515 #define LPUART_MODIR_RXRTSE_SHIFT 3
mbed_official 324:406fd2029f23 5516 #define LPUART_MODIR_TXCTSC_MASK 0x10u
mbed_official 324:406fd2029f23 5517 #define LPUART_MODIR_TXCTSC_SHIFT 4
mbed_official 324:406fd2029f23 5518 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
mbed_official 324:406fd2029f23 5519 #define LPUART_MODIR_TXCTSSRC_SHIFT 5
mbed_official 324:406fd2029f23 5520 #define LPUART_MODIR_TNP_MASK 0x30000u
mbed_official 324:406fd2029f23 5521 #define LPUART_MODIR_TNP_SHIFT 16
mbed_official 324:406fd2029f23 5522 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
mbed_official 324:406fd2029f23 5523 #define LPUART_MODIR_IREN_MASK 0x40000u
mbed_official 324:406fd2029f23 5524 #define LPUART_MODIR_IREN_SHIFT 18
mbed_official 324:406fd2029f23 5525
mbed_official 324:406fd2029f23 5526 /*!
mbed_official 324:406fd2029f23 5527 * @}
mbed_official 324:406fd2029f23 5528 */ /* end of group LPUART_Register_Masks */
mbed_official 324:406fd2029f23 5529
mbed_official 324:406fd2029f23 5530
mbed_official 324:406fd2029f23 5531 /* LPUART - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 5532 /** Peripheral LPUART0 base address */
mbed_official 324:406fd2029f23 5533 #define LPUART0_BASE (0x4002A000u)
mbed_official 324:406fd2029f23 5534 /** Peripheral LPUART0 base pointer */
mbed_official 324:406fd2029f23 5535 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
mbed_official 324:406fd2029f23 5536 #define LPUART0_BASE_PTR (LPUART0)
mbed_official 324:406fd2029f23 5537 /** Array initializer of LPUART peripheral base addresses */
mbed_official 324:406fd2029f23 5538 #define LPUART_BASE_ADDRS { LPUART0_BASE }
mbed_official 324:406fd2029f23 5539 /** Array initializer of LPUART peripheral base pointers */
mbed_official 324:406fd2029f23 5540 #define LPUART_BASE_PTRS { LPUART0 }
mbed_official 324:406fd2029f23 5541 /** Interrupt vectors for the LPUART peripheral type */
mbed_official 324:406fd2029f23 5542 #define LPUART_RX_TX_IRQS { LPUART0_IRQn }
mbed_official 324:406fd2029f23 5543 #define LPUART_ERR_IRQS { LPUART0_IRQn }
mbed_official 324:406fd2029f23 5544
mbed_official 324:406fd2029f23 5545 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5546 -- LPUART - Register accessor macros
mbed_official 324:406fd2029f23 5547 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5548
mbed_official 324:406fd2029f23 5549 /*!
mbed_official 324:406fd2029f23 5550 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
mbed_official 324:406fd2029f23 5551 * @{
mbed_official 324:406fd2029f23 5552 */
mbed_official 324:406fd2029f23 5553
mbed_official 324:406fd2029f23 5554
mbed_official 324:406fd2029f23 5555 /* LPUART - Register instance definitions */
mbed_official 324:406fd2029f23 5556 /* LPUART0 */
mbed_official 324:406fd2029f23 5557 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
mbed_official 324:406fd2029f23 5558 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
mbed_official 324:406fd2029f23 5559 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
mbed_official 324:406fd2029f23 5560 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
mbed_official 324:406fd2029f23 5561 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
mbed_official 324:406fd2029f23 5562 #define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
mbed_official 324:406fd2029f23 5563
mbed_official 324:406fd2029f23 5564 /*!
mbed_official 324:406fd2029f23 5565 * @}
mbed_official 324:406fd2029f23 5566 */ /* end of group LPUART_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5567
mbed_official 324:406fd2029f23 5568
mbed_official 324:406fd2029f23 5569 /*!
mbed_official 324:406fd2029f23 5570 * @}
mbed_official 324:406fd2029f23 5571 */ /* end of group LPUART_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 5572
mbed_official 324:406fd2029f23 5573
mbed_official 324:406fd2029f23 5574 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5575 -- MCG Peripheral Access Layer
mbed_official 324:406fd2029f23 5576 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5577
mbed_official 324:406fd2029f23 5578 /*!
mbed_official 324:406fd2029f23 5579 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 324:406fd2029f23 5580 * @{
mbed_official 324:406fd2029f23 5581 */
mbed_official 324:406fd2029f23 5582
mbed_official 324:406fd2029f23 5583 /** MCG - Register Layout Typedef */
mbed_official 324:406fd2029f23 5584 typedef struct {
mbed_official 324:406fd2029f23 5585 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 324:406fd2029f23 5586 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 324:406fd2029f23 5587 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 324:406fd2029f23 5588 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 324:406fd2029f23 5589 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 324:406fd2029f23 5590 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 324:406fd2029f23 5591 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 324:406fd2029f23 5592 uint8_t RESERVED_0[1];
mbed_official 324:406fd2029f23 5593 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 324:406fd2029f23 5594 uint8_t RESERVED_1[1];
mbed_official 324:406fd2029f23 5595 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 324:406fd2029f23 5596 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 324:406fd2029f23 5597 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
mbed_official 324:406fd2029f23 5598 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
mbed_official 324:406fd2029f23 5599 } MCG_Type, *MCG_MemMapPtr;
mbed_official 324:406fd2029f23 5600
mbed_official 324:406fd2029f23 5601 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5602 -- MCG - Register accessor macros
mbed_official 324:406fd2029f23 5603 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5604
mbed_official 324:406fd2029f23 5605 /*!
mbed_official 324:406fd2029f23 5606 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 324:406fd2029f23 5607 * @{
mbed_official 324:406fd2029f23 5608 */
mbed_official 324:406fd2029f23 5609
mbed_official 324:406fd2029f23 5610
mbed_official 324:406fd2029f23 5611 /* MCG - Register accessors */
mbed_official 324:406fd2029f23 5612 #define MCG_C1_REG(base) ((base)->C1)
mbed_official 324:406fd2029f23 5613 #define MCG_C2_REG(base) ((base)->C2)
mbed_official 324:406fd2029f23 5614 #define MCG_C3_REG(base) ((base)->C3)
mbed_official 324:406fd2029f23 5615 #define MCG_C4_REG(base) ((base)->C4)
mbed_official 324:406fd2029f23 5616 #define MCG_C5_REG(base) ((base)->C5)
mbed_official 324:406fd2029f23 5617 #define MCG_C6_REG(base) ((base)->C6)
mbed_official 324:406fd2029f23 5618 #define MCG_S_REG(base) ((base)->S)
mbed_official 324:406fd2029f23 5619 #define MCG_SC_REG(base) ((base)->SC)
mbed_official 324:406fd2029f23 5620 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
mbed_official 324:406fd2029f23 5621 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
mbed_official 324:406fd2029f23 5622 #define MCG_C7_REG(base) ((base)->C7)
mbed_official 324:406fd2029f23 5623 #define MCG_C8_REG(base) ((base)->C8)
mbed_official 324:406fd2029f23 5624
mbed_official 324:406fd2029f23 5625 /*!
mbed_official 324:406fd2029f23 5626 * @}
mbed_official 324:406fd2029f23 5627 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5628
mbed_official 324:406fd2029f23 5629
mbed_official 324:406fd2029f23 5630 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5631 -- MCG Register Masks
mbed_official 324:406fd2029f23 5632 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5633
mbed_official 324:406fd2029f23 5634 /*!
mbed_official 324:406fd2029f23 5635 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 324:406fd2029f23 5636 * @{
mbed_official 324:406fd2029f23 5637 */
mbed_official 324:406fd2029f23 5638
mbed_official 324:406fd2029f23 5639 /* C1 Bit Fields */
mbed_official 324:406fd2029f23 5640 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 324:406fd2029f23 5641 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 324:406fd2029f23 5642 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 324:406fd2029f23 5643 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 324:406fd2029f23 5644 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 324:406fd2029f23 5645 #define MCG_C1_IREFS_SHIFT 2
mbed_official 324:406fd2029f23 5646 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 324:406fd2029f23 5647 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 324:406fd2029f23 5648 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 324:406fd2029f23 5649 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 324:406fd2029f23 5650 #define MCG_C1_CLKS_SHIFT 6
mbed_official 324:406fd2029f23 5651 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 324:406fd2029f23 5652 /* C2 Bit Fields */
mbed_official 324:406fd2029f23 5653 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 324:406fd2029f23 5654 #define MCG_C2_IRCS_SHIFT 0
mbed_official 324:406fd2029f23 5655 #define MCG_C2_LP_MASK 0x2u
mbed_official 324:406fd2029f23 5656 #define MCG_C2_LP_SHIFT 1
mbed_official 324:406fd2029f23 5657 #define MCG_C2_EREFS_MASK 0x4u
mbed_official 324:406fd2029f23 5658 #define MCG_C2_EREFS_SHIFT 2
mbed_official 324:406fd2029f23 5659 #define MCG_C2_HGO_MASK 0x8u
mbed_official 324:406fd2029f23 5660 #define MCG_C2_HGO_SHIFT 3
mbed_official 324:406fd2029f23 5661 #define MCG_C2_RANGE_MASK 0x30u
mbed_official 324:406fd2029f23 5662 #define MCG_C2_RANGE_SHIFT 4
mbed_official 324:406fd2029f23 5663 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
mbed_official 324:406fd2029f23 5664 #define MCG_C2_FCFTRIM_MASK 0x40u
mbed_official 324:406fd2029f23 5665 #define MCG_C2_FCFTRIM_SHIFT 6
mbed_official 324:406fd2029f23 5666 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 324:406fd2029f23 5667 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 324:406fd2029f23 5668 /* C3 Bit Fields */
mbed_official 324:406fd2029f23 5669 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 324:406fd2029f23 5670 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 324:406fd2029f23 5671 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 324:406fd2029f23 5672 /* C4 Bit Fields */
mbed_official 324:406fd2029f23 5673 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 324:406fd2029f23 5674 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 324:406fd2029f23 5675 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 324:406fd2029f23 5676 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 324:406fd2029f23 5677 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 324:406fd2029f23 5678 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 324:406fd2029f23 5679 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 324:406fd2029f23 5680 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 324:406fd2029f23 5681 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 324:406fd2029f23 5682 #define MCG_C4_DMX32_SHIFT 7
mbed_official 324:406fd2029f23 5683 /* C5 Bit Fields */
mbed_official 324:406fd2029f23 5684 #define MCG_C5_PRDIV0_MASK 0x1Fu
mbed_official 324:406fd2029f23 5685 #define MCG_C5_PRDIV0_SHIFT 0
mbed_official 324:406fd2029f23 5686 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
mbed_official 324:406fd2029f23 5687 #define MCG_C5_PLLSTEN0_MASK 0x20u
mbed_official 324:406fd2029f23 5688 #define MCG_C5_PLLSTEN0_SHIFT 5
mbed_official 324:406fd2029f23 5689 #define MCG_C5_PLLCLKEN0_MASK 0x40u
mbed_official 324:406fd2029f23 5690 #define MCG_C5_PLLCLKEN0_SHIFT 6
mbed_official 324:406fd2029f23 5691 /* C6 Bit Fields */
mbed_official 324:406fd2029f23 5692 #define MCG_C6_VDIV0_MASK 0x1Fu
mbed_official 324:406fd2029f23 5693 #define MCG_C6_VDIV0_SHIFT 0
mbed_official 324:406fd2029f23 5694 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
mbed_official 324:406fd2029f23 5695 #define MCG_C6_CME0_MASK 0x20u
mbed_official 324:406fd2029f23 5696 #define MCG_C6_CME0_SHIFT 5
mbed_official 324:406fd2029f23 5697 #define MCG_C6_PLLS_MASK 0x40u
mbed_official 324:406fd2029f23 5698 #define MCG_C6_PLLS_SHIFT 6
mbed_official 324:406fd2029f23 5699 #define MCG_C6_LOLIE0_MASK 0x80u
mbed_official 324:406fd2029f23 5700 #define MCG_C6_LOLIE0_SHIFT 7
mbed_official 324:406fd2029f23 5701 /* S Bit Fields */
mbed_official 324:406fd2029f23 5702 #define MCG_S_IRCST_MASK 0x1u
mbed_official 324:406fd2029f23 5703 #define MCG_S_IRCST_SHIFT 0
mbed_official 324:406fd2029f23 5704 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 324:406fd2029f23 5705 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 324:406fd2029f23 5706 #define MCG_S_CLKST_MASK 0xCu
mbed_official 324:406fd2029f23 5707 #define MCG_S_CLKST_SHIFT 2
mbed_official 324:406fd2029f23 5708 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 324:406fd2029f23 5709 #define MCG_S_IREFST_MASK 0x10u
mbed_official 324:406fd2029f23 5710 #define MCG_S_IREFST_SHIFT 4
mbed_official 324:406fd2029f23 5711 #define MCG_S_PLLST_MASK 0x20u
mbed_official 324:406fd2029f23 5712 #define MCG_S_PLLST_SHIFT 5
mbed_official 324:406fd2029f23 5713 #define MCG_S_LOCK0_MASK 0x40u
mbed_official 324:406fd2029f23 5714 #define MCG_S_LOCK0_SHIFT 6
mbed_official 324:406fd2029f23 5715 #define MCG_S_LOLS0_MASK 0x80u
mbed_official 324:406fd2029f23 5716 #define MCG_S_LOLS0_SHIFT 7
mbed_official 324:406fd2029f23 5717 /* SC Bit Fields */
mbed_official 324:406fd2029f23 5718 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 324:406fd2029f23 5719 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 324:406fd2029f23 5720 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 324:406fd2029f23 5721 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 324:406fd2029f23 5722 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 324:406fd2029f23 5723 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 324:406fd2029f23 5724 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 324:406fd2029f23 5725 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 324:406fd2029f23 5726 #define MCG_SC_ATMF_SHIFT 5
mbed_official 324:406fd2029f23 5727 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 324:406fd2029f23 5728 #define MCG_SC_ATMS_SHIFT 6
mbed_official 324:406fd2029f23 5729 #define MCG_SC_ATME_MASK 0x80u
mbed_official 324:406fd2029f23 5730 #define MCG_SC_ATME_SHIFT 7
mbed_official 324:406fd2029f23 5731 /* ATCVH Bit Fields */
mbed_official 324:406fd2029f23 5732 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 324:406fd2029f23 5733 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 324:406fd2029f23 5734 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 324:406fd2029f23 5735 /* ATCVL Bit Fields */
mbed_official 324:406fd2029f23 5736 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 324:406fd2029f23 5737 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 324:406fd2029f23 5738 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 324:406fd2029f23 5739 /* C7 Bit Fields */
mbed_official 324:406fd2029f23 5740 #define MCG_C7_OSCSEL_MASK 0x3u
mbed_official 324:406fd2029f23 5741 #define MCG_C7_OSCSEL_SHIFT 0
mbed_official 324:406fd2029f23 5742 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
mbed_official 324:406fd2029f23 5743 /* C8 Bit Fields */
mbed_official 324:406fd2029f23 5744 #define MCG_C8_LOCS1_MASK 0x1u
mbed_official 324:406fd2029f23 5745 #define MCG_C8_LOCS1_SHIFT 0
mbed_official 324:406fd2029f23 5746 #define MCG_C8_CME1_MASK 0x20u
mbed_official 324:406fd2029f23 5747 #define MCG_C8_CME1_SHIFT 5
mbed_official 324:406fd2029f23 5748 #define MCG_C8_LOLRE_MASK 0x40u
mbed_official 324:406fd2029f23 5749 #define MCG_C8_LOLRE_SHIFT 6
mbed_official 324:406fd2029f23 5750 #define MCG_C8_LOCRE1_MASK 0x80u
mbed_official 324:406fd2029f23 5751 #define MCG_C8_LOCRE1_SHIFT 7
mbed_official 324:406fd2029f23 5752
mbed_official 324:406fd2029f23 5753 /*!
mbed_official 324:406fd2029f23 5754 * @}
mbed_official 324:406fd2029f23 5755 */ /* end of group MCG_Register_Masks */
mbed_official 324:406fd2029f23 5756
mbed_official 324:406fd2029f23 5757
mbed_official 324:406fd2029f23 5758 /* MCG - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 5759 /** Peripheral MCG base address */
mbed_official 324:406fd2029f23 5760 #define MCG_BASE (0x40064000u)
mbed_official 324:406fd2029f23 5761 /** Peripheral MCG base pointer */
mbed_official 324:406fd2029f23 5762 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 324:406fd2029f23 5763 #define MCG_BASE_PTR (MCG)
mbed_official 324:406fd2029f23 5764 /** Array initializer of MCG peripheral base addresses */
mbed_official 324:406fd2029f23 5765 #define MCG_BASE_ADDRS { MCG_BASE }
mbed_official 324:406fd2029f23 5766 /** Array initializer of MCG peripheral base pointers */
mbed_official 324:406fd2029f23 5767 #define MCG_BASE_PTRS { MCG }
mbed_official 324:406fd2029f23 5768
mbed_official 324:406fd2029f23 5769 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5770 -- MCG - Register accessor macros
mbed_official 324:406fd2029f23 5771 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5772
mbed_official 324:406fd2029f23 5773 /*!
mbed_official 324:406fd2029f23 5774 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 324:406fd2029f23 5775 * @{
mbed_official 324:406fd2029f23 5776 */
mbed_official 324:406fd2029f23 5777
mbed_official 324:406fd2029f23 5778
mbed_official 324:406fd2029f23 5779 /* MCG - Register instance definitions */
mbed_official 324:406fd2029f23 5780 /* MCG */
mbed_official 324:406fd2029f23 5781 #define MCG_C1 MCG_C1_REG(MCG)
mbed_official 324:406fd2029f23 5782 #define MCG_C2 MCG_C2_REG(MCG)
mbed_official 324:406fd2029f23 5783 #define MCG_C3 MCG_C3_REG(MCG)
mbed_official 324:406fd2029f23 5784 #define MCG_C4 MCG_C4_REG(MCG)
mbed_official 324:406fd2029f23 5785 #define MCG_C5 MCG_C5_REG(MCG)
mbed_official 324:406fd2029f23 5786 #define MCG_C6 MCG_C6_REG(MCG)
mbed_official 324:406fd2029f23 5787 #define MCG_S MCG_S_REG(MCG)
mbed_official 324:406fd2029f23 5788 #define MCG_SC MCG_SC_REG(MCG)
mbed_official 324:406fd2029f23 5789 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
mbed_official 324:406fd2029f23 5790 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
mbed_official 324:406fd2029f23 5791 #define MCG_C7 MCG_C7_REG(MCG)
mbed_official 324:406fd2029f23 5792 #define MCG_C8 MCG_C8_REG(MCG)
mbed_official 324:406fd2029f23 5793
mbed_official 324:406fd2029f23 5794 /*!
mbed_official 324:406fd2029f23 5795 * @}
mbed_official 324:406fd2029f23 5796 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5797
mbed_official 324:406fd2029f23 5798
mbed_official 324:406fd2029f23 5799 /*!
mbed_official 324:406fd2029f23 5800 * @}
mbed_official 324:406fd2029f23 5801 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 5802
mbed_official 324:406fd2029f23 5803
mbed_official 324:406fd2029f23 5804 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5805 -- MCM Peripheral Access Layer
mbed_official 324:406fd2029f23 5806 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5807
mbed_official 324:406fd2029f23 5808 /*!
mbed_official 324:406fd2029f23 5809 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 324:406fd2029f23 5810 * @{
mbed_official 324:406fd2029f23 5811 */
mbed_official 324:406fd2029f23 5812
mbed_official 324:406fd2029f23 5813 /** MCM - Register Layout Typedef */
mbed_official 324:406fd2029f23 5814 typedef struct {
mbed_official 324:406fd2029f23 5815 uint8_t RESERVED_0[8];
mbed_official 324:406fd2029f23 5816 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 324:406fd2029f23 5817 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 324:406fd2029f23 5818 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
mbed_official 324:406fd2029f23 5819 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
mbed_official 324:406fd2029f23 5820 uint8_t RESERVED_1[44];
mbed_official 324:406fd2029f23 5821 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mbed_official 324:406fd2029f23 5822 } MCM_Type, *MCM_MemMapPtr;
mbed_official 324:406fd2029f23 5823
mbed_official 324:406fd2029f23 5824 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5825 -- MCM - Register accessor macros
mbed_official 324:406fd2029f23 5826 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5827
mbed_official 324:406fd2029f23 5828 /*!
mbed_official 324:406fd2029f23 5829 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 324:406fd2029f23 5830 * @{
mbed_official 324:406fd2029f23 5831 */
mbed_official 324:406fd2029f23 5832
mbed_official 324:406fd2029f23 5833
mbed_official 324:406fd2029f23 5834 /* MCM - Register accessors */
mbed_official 324:406fd2029f23 5835 #define MCM_PLASC_REG(base) ((base)->PLASC)
mbed_official 324:406fd2029f23 5836 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
mbed_official 324:406fd2029f23 5837 #define MCM_PLACR_REG(base) ((base)->PLACR)
mbed_official 324:406fd2029f23 5838 #define MCM_ISCR_REG(base) ((base)->ISCR)
mbed_official 324:406fd2029f23 5839 #define MCM_CPO_REG(base) ((base)->CPO)
mbed_official 324:406fd2029f23 5840
mbed_official 324:406fd2029f23 5841 /*!
mbed_official 324:406fd2029f23 5842 * @}
mbed_official 324:406fd2029f23 5843 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5844
mbed_official 324:406fd2029f23 5845
mbed_official 324:406fd2029f23 5846 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5847 -- MCM Register Masks
mbed_official 324:406fd2029f23 5848 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5849
mbed_official 324:406fd2029f23 5850 /*!
mbed_official 324:406fd2029f23 5851 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 324:406fd2029f23 5852 * @{
mbed_official 324:406fd2029f23 5853 */
mbed_official 324:406fd2029f23 5854
mbed_official 324:406fd2029f23 5855 /* PLASC Bit Fields */
mbed_official 324:406fd2029f23 5856 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 324:406fd2029f23 5857 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 324:406fd2029f23 5858 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 324:406fd2029f23 5859 /* PLAMC Bit Fields */
mbed_official 324:406fd2029f23 5860 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 324:406fd2029f23 5861 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 324:406fd2029f23 5862 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 324:406fd2029f23 5863 /* PLACR Bit Fields */
mbed_official 324:406fd2029f23 5864 #define MCM_PLACR_ARB_MASK 0x200u
mbed_official 324:406fd2029f23 5865 #define MCM_PLACR_ARB_SHIFT 9
mbed_official 324:406fd2029f23 5866 /* ISCR Bit Fields */
mbed_official 324:406fd2029f23 5867 #define MCM_ISCR_FIOC_MASK 0x100u
mbed_official 324:406fd2029f23 5868 #define MCM_ISCR_FIOC_SHIFT 8
mbed_official 324:406fd2029f23 5869 #define MCM_ISCR_FDZC_MASK 0x200u
mbed_official 324:406fd2029f23 5870 #define MCM_ISCR_FDZC_SHIFT 9
mbed_official 324:406fd2029f23 5871 #define MCM_ISCR_FOFC_MASK 0x400u
mbed_official 324:406fd2029f23 5872 #define MCM_ISCR_FOFC_SHIFT 10
mbed_official 324:406fd2029f23 5873 #define MCM_ISCR_FUFC_MASK 0x800u
mbed_official 324:406fd2029f23 5874 #define MCM_ISCR_FUFC_SHIFT 11
mbed_official 324:406fd2029f23 5875 #define MCM_ISCR_FIXC_MASK 0x1000u
mbed_official 324:406fd2029f23 5876 #define MCM_ISCR_FIXC_SHIFT 12
mbed_official 324:406fd2029f23 5877 #define MCM_ISCR_FIDC_MASK 0x8000u
mbed_official 324:406fd2029f23 5878 #define MCM_ISCR_FIDC_SHIFT 15
mbed_official 324:406fd2029f23 5879 #define MCM_ISCR_FIOCE_MASK 0x1000000u
mbed_official 324:406fd2029f23 5880 #define MCM_ISCR_FIOCE_SHIFT 24
mbed_official 324:406fd2029f23 5881 #define MCM_ISCR_FDZCE_MASK 0x2000000u
mbed_official 324:406fd2029f23 5882 #define MCM_ISCR_FDZCE_SHIFT 25
mbed_official 324:406fd2029f23 5883 #define MCM_ISCR_FOFCE_MASK 0x4000000u
mbed_official 324:406fd2029f23 5884 #define MCM_ISCR_FOFCE_SHIFT 26
mbed_official 324:406fd2029f23 5885 #define MCM_ISCR_FUFCE_MASK 0x8000000u
mbed_official 324:406fd2029f23 5886 #define MCM_ISCR_FUFCE_SHIFT 27
mbed_official 324:406fd2029f23 5887 #define MCM_ISCR_FIXCE_MASK 0x10000000u
mbed_official 324:406fd2029f23 5888 #define MCM_ISCR_FIXCE_SHIFT 28
mbed_official 324:406fd2029f23 5889 #define MCM_ISCR_FIDCE_MASK 0x80000000u
mbed_official 324:406fd2029f23 5890 #define MCM_ISCR_FIDCE_SHIFT 31
mbed_official 324:406fd2029f23 5891 /* CPO Bit Fields */
mbed_official 324:406fd2029f23 5892 #define MCM_CPO_CPOREQ_MASK 0x1u
mbed_official 324:406fd2029f23 5893 #define MCM_CPO_CPOREQ_SHIFT 0
mbed_official 324:406fd2029f23 5894 #define MCM_CPO_CPOACK_MASK 0x2u
mbed_official 324:406fd2029f23 5895 #define MCM_CPO_CPOACK_SHIFT 1
mbed_official 324:406fd2029f23 5896 #define MCM_CPO_CPOWOI_MASK 0x4u
mbed_official 324:406fd2029f23 5897 #define MCM_CPO_CPOWOI_SHIFT 2
mbed_official 324:406fd2029f23 5898
mbed_official 324:406fd2029f23 5899 /*!
mbed_official 324:406fd2029f23 5900 * @}
mbed_official 324:406fd2029f23 5901 */ /* end of group MCM_Register_Masks */
mbed_official 324:406fd2029f23 5902
mbed_official 324:406fd2029f23 5903
mbed_official 324:406fd2029f23 5904 /* MCM - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 5905 /** Peripheral MCM base address */
mbed_official 324:406fd2029f23 5906 #define MCM_BASE (0xE0080000u)
mbed_official 324:406fd2029f23 5907 /** Peripheral MCM base pointer */
mbed_official 324:406fd2029f23 5908 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 324:406fd2029f23 5909 #define MCM_BASE_PTR (MCM)
mbed_official 324:406fd2029f23 5910 /** Array initializer of MCM peripheral base addresses */
mbed_official 324:406fd2029f23 5911 #define MCM_BASE_ADDRS { MCM_BASE }
mbed_official 324:406fd2029f23 5912 /** Array initializer of MCM peripheral base pointers */
mbed_official 324:406fd2029f23 5913 #define MCM_BASE_PTRS { MCM }
mbed_official 324:406fd2029f23 5914
mbed_official 324:406fd2029f23 5915 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5916 -- MCM - Register accessor macros
mbed_official 324:406fd2029f23 5917 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5918
mbed_official 324:406fd2029f23 5919 /*!
mbed_official 324:406fd2029f23 5920 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 324:406fd2029f23 5921 * @{
mbed_official 324:406fd2029f23 5922 */
mbed_official 324:406fd2029f23 5923
mbed_official 324:406fd2029f23 5924
mbed_official 324:406fd2029f23 5925 /* MCM - Register instance definitions */
mbed_official 324:406fd2029f23 5926 /* MCM */
mbed_official 324:406fd2029f23 5927 #define MCM_PLASC MCM_PLASC_REG(MCM)
mbed_official 324:406fd2029f23 5928 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
mbed_official 324:406fd2029f23 5929 #define MCM_PLACR MCM_PLACR_REG(MCM)
mbed_official 324:406fd2029f23 5930 #define MCM_ISCR MCM_ISCR_REG(MCM)
mbed_official 324:406fd2029f23 5931 #define MCM_CPO MCM_CPO_REG(MCM)
mbed_official 324:406fd2029f23 5932
mbed_official 324:406fd2029f23 5933 /*!
mbed_official 324:406fd2029f23 5934 * @}
mbed_official 324:406fd2029f23 5935 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5936
mbed_official 324:406fd2029f23 5937
mbed_official 324:406fd2029f23 5938 /*!
mbed_official 324:406fd2029f23 5939 * @}
mbed_official 324:406fd2029f23 5940 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 5941
mbed_official 324:406fd2029f23 5942
mbed_official 324:406fd2029f23 5943 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5944 -- NV Peripheral Access Layer
mbed_official 324:406fd2029f23 5945 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5946
mbed_official 324:406fd2029f23 5947 /*!
mbed_official 324:406fd2029f23 5948 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 324:406fd2029f23 5949 * @{
mbed_official 324:406fd2029f23 5950 */
mbed_official 324:406fd2029f23 5951
mbed_official 324:406fd2029f23 5952 /** NV - Register Layout Typedef */
mbed_official 324:406fd2029f23 5953 typedef struct {
mbed_official 324:406fd2029f23 5954 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 324:406fd2029f23 5955 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 324:406fd2029f23 5956 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 324:406fd2029f23 5957 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 324:406fd2029f23 5958 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 324:406fd2029f23 5959 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 324:406fd2029f23 5960 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 324:406fd2029f23 5961 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 324:406fd2029f23 5962 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 324:406fd2029f23 5963 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 324:406fd2029f23 5964 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 324:406fd2029f23 5965 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 324:406fd2029f23 5966 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 324:406fd2029f23 5967 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 324:406fd2029f23 5968 } NV_Type, *NV_MemMapPtr;
mbed_official 324:406fd2029f23 5969
mbed_official 324:406fd2029f23 5970 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 5971 -- NV - Register accessor macros
mbed_official 324:406fd2029f23 5972 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 5973
mbed_official 324:406fd2029f23 5974 /*!
mbed_official 324:406fd2029f23 5975 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 324:406fd2029f23 5976 * @{
mbed_official 324:406fd2029f23 5977 */
mbed_official 324:406fd2029f23 5978
mbed_official 324:406fd2029f23 5979
mbed_official 324:406fd2029f23 5980 /* NV - Register accessors */
mbed_official 324:406fd2029f23 5981 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
mbed_official 324:406fd2029f23 5982 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
mbed_official 324:406fd2029f23 5983 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
mbed_official 324:406fd2029f23 5984 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
mbed_official 324:406fd2029f23 5985 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
mbed_official 324:406fd2029f23 5986 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
mbed_official 324:406fd2029f23 5987 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
mbed_official 324:406fd2029f23 5988 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
mbed_official 324:406fd2029f23 5989 #define NV_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 324:406fd2029f23 5990 #define NV_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 324:406fd2029f23 5991 #define NV_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 324:406fd2029f23 5992 #define NV_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 324:406fd2029f23 5993 #define NV_FSEC_REG(base) ((base)->FSEC)
mbed_official 324:406fd2029f23 5994 #define NV_FOPT_REG(base) ((base)->FOPT)
mbed_official 324:406fd2029f23 5995
mbed_official 324:406fd2029f23 5996 /*!
mbed_official 324:406fd2029f23 5997 * @}
mbed_official 324:406fd2029f23 5998 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 5999
mbed_official 324:406fd2029f23 6000
mbed_official 324:406fd2029f23 6001 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6002 -- NV Register Masks
mbed_official 324:406fd2029f23 6003 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6004
mbed_official 324:406fd2029f23 6005 /*!
mbed_official 324:406fd2029f23 6006 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 324:406fd2029f23 6007 * @{
mbed_official 324:406fd2029f23 6008 */
mbed_official 324:406fd2029f23 6009
mbed_official 324:406fd2029f23 6010 /* BACKKEY3 Bit Fields */
mbed_official 324:406fd2029f23 6011 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6012 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6013 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 324:406fd2029f23 6014 /* BACKKEY2 Bit Fields */
mbed_official 324:406fd2029f23 6015 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6016 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6017 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 324:406fd2029f23 6018 /* BACKKEY1 Bit Fields */
mbed_official 324:406fd2029f23 6019 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6020 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6021 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 324:406fd2029f23 6022 /* BACKKEY0 Bit Fields */
mbed_official 324:406fd2029f23 6023 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6024 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6025 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 324:406fd2029f23 6026 /* BACKKEY7 Bit Fields */
mbed_official 324:406fd2029f23 6027 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6028 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6029 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 324:406fd2029f23 6030 /* BACKKEY6 Bit Fields */
mbed_official 324:406fd2029f23 6031 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6032 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6033 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 324:406fd2029f23 6034 /* BACKKEY5 Bit Fields */
mbed_official 324:406fd2029f23 6035 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6036 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6037 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 324:406fd2029f23 6038 /* BACKKEY4 Bit Fields */
mbed_official 324:406fd2029f23 6039 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 324:406fd2029f23 6040 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 324:406fd2029f23 6041 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 324:406fd2029f23 6042 /* FPROT3 Bit Fields */
mbed_official 324:406fd2029f23 6043 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 6044 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 324:406fd2029f23 6045 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 324:406fd2029f23 6046 /* FPROT2 Bit Fields */
mbed_official 324:406fd2029f23 6047 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 6048 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 324:406fd2029f23 6049 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 324:406fd2029f23 6050 /* FPROT1 Bit Fields */
mbed_official 324:406fd2029f23 6051 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 6052 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 324:406fd2029f23 6053 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 324:406fd2029f23 6054 /* FPROT0 Bit Fields */
mbed_official 324:406fd2029f23 6055 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 324:406fd2029f23 6056 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 324:406fd2029f23 6057 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 324:406fd2029f23 6058 /* FSEC Bit Fields */
mbed_official 324:406fd2029f23 6059 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 324:406fd2029f23 6060 #define NV_FSEC_SEC_SHIFT 0
mbed_official 324:406fd2029f23 6061 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 324:406fd2029f23 6062 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 324:406fd2029f23 6063 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 324:406fd2029f23 6064 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 324:406fd2029f23 6065 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 324:406fd2029f23 6066 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 324:406fd2029f23 6067 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 324:406fd2029f23 6068 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 324:406fd2029f23 6069 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 324:406fd2029f23 6070 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 324:406fd2029f23 6071 /* FOPT Bit Fields */
mbed_official 324:406fd2029f23 6072 #define NV_FOPT_LPBOOT_MASK 0x1u
mbed_official 324:406fd2029f23 6073 #define NV_FOPT_LPBOOT_SHIFT 0
mbed_official 324:406fd2029f23 6074 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
mbed_official 324:406fd2029f23 6075 #define NV_FOPT_EZPORT_DIS_SHIFT 1
mbed_official 324:406fd2029f23 6076 #define NV_FOPT_NMI_DIS_MASK 0x4u
mbed_official 324:406fd2029f23 6077 #define NV_FOPT_NMI_DIS_SHIFT 2
mbed_official 324:406fd2029f23 6078 #define NV_FOPT_FAST_INIT_MASK 0x20u
mbed_official 324:406fd2029f23 6079 #define NV_FOPT_FAST_INIT_SHIFT 5
mbed_official 324:406fd2029f23 6080
mbed_official 324:406fd2029f23 6081 /*!
mbed_official 324:406fd2029f23 6082 * @}
mbed_official 324:406fd2029f23 6083 */ /* end of group NV_Register_Masks */
mbed_official 324:406fd2029f23 6084
mbed_official 324:406fd2029f23 6085
mbed_official 324:406fd2029f23 6086 /* NV - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6087 /** Peripheral FTFA_FlashConfig base address */
mbed_official 324:406fd2029f23 6088 #define FTFA_FlashConfig_BASE (0x400u)
mbed_official 324:406fd2029f23 6089 /** Peripheral FTFA_FlashConfig base pointer */
mbed_official 324:406fd2029f23 6090 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mbed_official 324:406fd2029f23 6091 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6092 /** Array initializer of NV peripheral base addresses */
mbed_official 324:406fd2029f23 6093 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
mbed_official 324:406fd2029f23 6094 /** Array initializer of NV peripheral base pointers */
mbed_official 324:406fd2029f23 6095 #define NV_BASE_PTRS { FTFA_FlashConfig }
mbed_official 324:406fd2029f23 6096
mbed_official 324:406fd2029f23 6097 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6098 -- NV - Register accessor macros
mbed_official 324:406fd2029f23 6099 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6100
mbed_official 324:406fd2029f23 6101 /*!
mbed_official 324:406fd2029f23 6102 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 324:406fd2029f23 6103 * @{
mbed_official 324:406fd2029f23 6104 */
mbed_official 324:406fd2029f23 6105
mbed_official 324:406fd2029f23 6106
mbed_official 324:406fd2029f23 6107 /* NV - Register instance definitions */
mbed_official 324:406fd2029f23 6108 /* FTFA_FlashConfig */
mbed_official 324:406fd2029f23 6109 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6110 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6111 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6112 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6113 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6114 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6115 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6116 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6117 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6118 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6119 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6120 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6121 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6122 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
mbed_official 324:406fd2029f23 6123
mbed_official 324:406fd2029f23 6124 /*!
mbed_official 324:406fd2029f23 6125 * @}
mbed_official 324:406fd2029f23 6126 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6127
mbed_official 324:406fd2029f23 6128
mbed_official 324:406fd2029f23 6129 /*!
mbed_official 324:406fd2029f23 6130 * @}
mbed_official 324:406fd2029f23 6131 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 6132
mbed_official 324:406fd2029f23 6133
mbed_official 324:406fd2029f23 6134 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6135 -- OSC Peripheral Access Layer
mbed_official 324:406fd2029f23 6136 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6137
mbed_official 324:406fd2029f23 6138 /*!
mbed_official 324:406fd2029f23 6139 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 324:406fd2029f23 6140 * @{
mbed_official 324:406fd2029f23 6141 */
mbed_official 324:406fd2029f23 6142
mbed_official 324:406fd2029f23 6143 /** OSC - Register Layout Typedef */
mbed_official 324:406fd2029f23 6144 typedef struct {
mbed_official 324:406fd2029f23 6145 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 6146 uint8_t RESERVED_0[1];
mbed_official 324:406fd2029f23 6147 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
mbed_official 324:406fd2029f23 6148 } OSC_Type, *OSC_MemMapPtr;
mbed_official 324:406fd2029f23 6149
mbed_official 324:406fd2029f23 6150 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6151 -- OSC - Register accessor macros
mbed_official 324:406fd2029f23 6152 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6153
mbed_official 324:406fd2029f23 6154 /*!
mbed_official 324:406fd2029f23 6155 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 324:406fd2029f23 6156 * @{
mbed_official 324:406fd2029f23 6157 */
mbed_official 324:406fd2029f23 6158
mbed_official 324:406fd2029f23 6159
mbed_official 324:406fd2029f23 6160 /* OSC - Register accessors */
mbed_official 324:406fd2029f23 6161 #define OSC_CR_REG(base) ((base)->CR)
mbed_official 324:406fd2029f23 6162 #define OSC_DIV_REG(base) ((base)->DIV)
mbed_official 324:406fd2029f23 6163
mbed_official 324:406fd2029f23 6164 /*!
mbed_official 324:406fd2029f23 6165 * @}
mbed_official 324:406fd2029f23 6166 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6167
mbed_official 324:406fd2029f23 6168
mbed_official 324:406fd2029f23 6169 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6170 -- OSC Register Masks
mbed_official 324:406fd2029f23 6171 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6172
mbed_official 324:406fd2029f23 6173 /*!
mbed_official 324:406fd2029f23 6174 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 324:406fd2029f23 6175 * @{
mbed_official 324:406fd2029f23 6176 */
mbed_official 324:406fd2029f23 6177
mbed_official 324:406fd2029f23 6178 /* CR Bit Fields */
mbed_official 324:406fd2029f23 6179 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 324:406fd2029f23 6180 #define OSC_CR_SC16P_SHIFT 0
mbed_official 324:406fd2029f23 6181 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 324:406fd2029f23 6182 #define OSC_CR_SC8P_SHIFT 1
mbed_official 324:406fd2029f23 6183 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 324:406fd2029f23 6184 #define OSC_CR_SC4P_SHIFT 2
mbed_official 324:406fd2029f23 6185 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 324:406fd2029f23 6186 #define OSC_CR_SC2P_SHIFT 3
mbed_official 324:406fd2029f23 6187 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 324:406fd2029f23 6188 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 324:406fd2029f23 6189 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 324:406fd2029f23 6190 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 324:406fd2029f23 6191 /* DIV Bit Fields */
mbed_official 324:406fd2029f23 6192 #define OSC_DIV_ERPS_MASK 0xC0u
mbed_official 324:406fd2029f23 6193 #define OSC_DIV_ERPS_SHIFT 6
mbed_official 324:406fd2029f23 6194 #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
mbed_official 324:406fd2029f23 6195
mbed_official 324:406fd2029f23 6196 /*!
mbed_official 324:406fd2029f23 6197 * @}
mbed_official 324:406fd2029f23 6198 */ /* end of group OSC_Register_Masks */
mbed_official 324:406fd2029f23 6199
mbed_official 324:406fd2029f23 6200
mbed_official 324:406fd2029f23 6201 /* OSC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6202 /** Peripheral OSC base address */
mbed_official 324:406fd2029f23 6203 #define OSC_BASE (0x40065000u)
mbed_official 324:406fd2029f23 6204 /** Peripheral OSC base pointer */
mbed_official 324:406fd2029f23 6205 #define OSC ((OSC_Type *)OSC_BASE)
mbed_official 324:406fd2029f23 6206 #define OSC_BASE_PTR (OSC)
mbed_official 324:406fd2029f23 6207 /** Array initializer of OSC peripheral base addresses */
mbed_official 324:406fd2029f23 6208 #define OSC_BASE_ADDRS { OSC_BASE }
mbed_official 324:406fd2029f23 6209 /** Array initializer of OSC peripheral base pointers */
mbed_official 324:406fd2029f23 6210 #define OSC_BASE_PTRS { OSC }
mbed_official 324:406fd2029f23 6211
mbed_official 324:406fd2029f23 6212 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6213 -- OSC - Register accessor macros
mbed_official 324:406fd2029f23 6214 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6215
mbed_official 324:406fd2029f23 6216 /*!
mbed_official 324:406fd2029f23 6217 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 324:406fd2029f23 6218 * @{
mbed_official 324:406fd2029f23 6219 */
mbed_official 324:406fd2029f23 6220
mbed_official 324:406fd2029f23 6221
mbed_official 324:406fd2029f23 6222 /* OSC - Register instance definitions */
mbed_official 324:406fd2029f23 6223 /* OSC */
mbed_official 324:406fd2029f23 6224 #define OSC_CR OSC_CR_REG(OSC)
mbed_official 324:406fd2029f23 6225 #define OSC_DIV OSC_DIV_REG(OSC)
mbed_official 324:406fd2029f23 6226
mbed_official 324:406fd2029f23 6227 /*!
mbed_official 324:406fd2029f23 6228 * @}
mbed_official 324:406fd2029f23 6229 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6230
mbed_official 324:406fd2029f23 6231
mbed_official 324:406fd2029f23 6232 /*!
mbed_official 324:406fd2029f23 6233 * @}
mbed_official 324:406fd2029f23 6234 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 6235
mbed_official 324:406fd2029f23 6236
mbed_official 324:406fd2029f23 6237 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6238 -- PDB Peripheral Access Layer
mbed_official 324:406fd2029f23 6239 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6240
mbed_official 324:406fd2029f23 6241 /*!
mbed_official 324:406fd2029f23 6242 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
mbed_official 324:406fd2029f23 6243 * @{
mbed_official 324:406fd2029f23 6244 */
mbed_official 324:406fd2029f23 6245
mbed_official 324:406fd2029f23 6246 /** PDB - Register Layout Typedef */
mbed_official 324:406fd2029f23 6247 typedef struct {
mbed_official 324:406fd2029f23 6248 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
mbed_official 324:406fd2029f23 6249 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
mbed_official 324:406fd2029f23 6250 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
mbed_official 324:406fd2029f23 6251 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
mbed_official 324:406fd2029f23 6252 struct { /* offset: 0x10, array step: 0x28 */
mbed_official 324:406fd2029f23 6253 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
mbed_official 324:406fd2029f23 6254 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
mbed_official 324:406fd2029f23 6255 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
mbed_official 324:406fd2029f23 6256 uint8_t RESERVED_0[24];
mbed_official 324:406fd2029f23 6257 } CH[2];
mbed_official 324:406fd2029f23 6258 uint8_t RESERVED_0[240];
mbed_official 324:406fd2029f23 6259 struct { /* offset: 0x150, array step: 0x8 */
mbed_official 324:406fd2029f23 6260 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
mbed_official 324:406fd2029f23 6261 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
mbed_official 324:406fd2029f23 6262 } DAC[2];
mbed_official 324:406fd2029f23 6263 uint8_t RESERVED_1[48];
mbed_official 324:406fd2029f23 6264 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
mbed_official 324:406fd2029f23 6265 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
mbed_official 324:406fd2029f23 6266 } PDB_Type, *PDB_MemMapPtr;
mbed_official 324:406fd2029f23 6267
mbed_official 324:406fd2029f23 6268 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6269 -- PDB - Register accessor macros
mbed_official 324:406fd2029f23 6270 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6271
mbed_official 324:406fd2029f23 6272 /*!
mbed_official 324:406fd2029f23 6273 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
mbed_official 324:406fd2029f23 6274 * @{
mbed_official 324:406fd2029f23 6275 */
mbed_official 324:406fd2029f23 6276
mbed_official 324:406fd2029f23 6277
mbed_official 324:406fd2029f23 6278 /* PDB - Register accessors */
mbed_official 324:406fd2029f23 6279 #define PDB_SC_REG(base) ((base)->SC)
mbed_official 324:406fd2029f23 6280 #define PDB_MOD_REG(base) ((base)->MOD)
mbed_official 324:406fd2029f23 6281 #define PDB_CNT_REG(base) ((base)->CNT)
mbed_official 324:406fd2029f23 6282 #define PDB_IDLY_REG(base) ((base)->IDLY)
mbed_official 324:406fd2029f23 6283 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
mbed_official 324:406fd2029f23 6284 #define PDB_S_REG(base,index) ((base)->CH[index].S)
mbed_official 324:406fd2029f23 6285 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
mbed_official 324:406fd2029f23 6286 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
mbed_official 324:406fd2029f23 6287 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
mbed_official 324:406fd2029f23 6288 #define PDB_POEN_REG(base) ((base)->POEN)
mbed_official 324:406fd2029f23 6289 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
mbed_official 324:406fd2029f23 6290
mbed_official 324:406fd2029f23 6291 /*!
mbed_official 324:406fd2029f23 6292 * @}
mbed_official 324:406fd2029f23 6293 */ /* end of group PDB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6294
mbed_official 324:406fd2029f23 6295
mbed_official 324:406fd2029f23 6296 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6297 -- PDB Register Masks
mbed_official 324:406fd2029f23 6298 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6299
mbed_official 324:406fd2029f23 6300 /*!
mbed_official 324:406fd2029f23 6301 * @addtogroup PDB_Register_Masks PDB Register Masks
mbed_official 324:406fd2029f23 6302 * @{
mbed_official 324:406fd2029f23 6303 */
mbed_official 324:406fd2029f23 6304
mbed_official 324:406fd2029f23 6305 /* SC Bit Fields */
mbed_official 324:406fd2029f23 6306 #define PDB_SC_LDOK_MASK 0x1u
mbed_official 324:406fd2029f23 6307 #define PDB_SC_LDOK_SHIFT 0
mbed_official 324:406fd2029f23 6308 #define PDB_SC_CONT_MASK 0x2u
mbed_official 324:406fd2029f23 6309 #define PDB_SC_CONT_SHIFT 1
mbed_official 324:406fd2029f23 6310 #define PDB_SC_MULT_MASK 0xCu
mbed_official 324:406fd2029f23 6311 #define PDB_SC_MULT_SHIFT 2
mbed_official 324:406fd2029f23 6312 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
mbed_official 324:406fd2029f23 6313 #define PDB_SC_PDBIE_MASK 0x20u
mbed_official 324:406fd2029f23 6314 #define PDB_SC_PDBIE_SHIFT 5
mbed_official 324:406fd2029f23 6315 #define PDB_SC_PDBIF_MASK 0x40u
mbed_official 324:406fd2029f23 6316 #define PDB_SC_PDBIF_SHIFT 6
mbed_official 324:406fd2029f23 6317 #define PDB_SC_PDBEN_MASK 0x80u
mbed_official 324:406fd2029f23 6318 #define PDB_SC_PDBEN_SHIFT 7
mbed_official 324:406fd2029f23 6319 #define PDB_SC_TRGSEL_MASK 0xF00u
mbed_official 324:406fd2029f23 6320 #define PDB_SC_TRGSEL_SHIFT 8
mbed_official 324:406fd2029f23 6321 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
mbed_official 324:406fd2029f23 6322 #define PDB_SC_PRESCALER_MASK 0x7000u
mbed_official 324:406fd2029f23 6323 #define PDB_SC_PRESCALER_SHIFT 12
mbed_official 324:406fd2029f23 6324 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
mbed_official 324:406fd2029f23 6325 #define PDB_SC_DMAEN_MASK 0x8000u
mbed_official 324:406fd2029f23 6326 #define PDB_SC_DMAEN_SHIFT 15
mbed_official 324:406fd2029f23 6327 #define PDB_SC_SWTRIG_MASK 0x10000u
mbed_official 324:406fd2029f23 6328 #define PDB_SC_SWTRIG_SHIFT 16
mbed_official 324:406fd2029f23 6329 #define PDB_SC_PDBEIE_MASK 0x20000u
mbed_official 324:406fd2029f23 6330 #define PDB_SC_PDBEIE_SHIFT 17
mbed_official 324:406fd2029f23 6331 #define PDB_SC_LDMOD_MASK 0xC0000u
mbed_official 324:406fd2029f23 6332 #define PDB_SC_LDMOD_SHIFT 18
mbed_official 324:406fd2029f23 6333 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
mbed_official 324:406fd2029f23 6334 /* MOD Bit Fields */
mbed_official 324:406fd2029f23 6335 #define PDB_MOD_MOD_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6336 #define PDB_MOD_MOD_SHIFT 0
mbed_official 324:406fd2029f23 6337 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
mbed_official 324:406fd2029f23 6338 /* CNT Bit Fields */
mbed_official 324:406fd2029f23 6339 #define PDB_CNT_CNT_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6340 #define PDB_CNT_CNT_SHIFT 0
mbed_official 324:406fd2029f23 6341 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
mbed_official 324:406fd2029f23 6342 /* IDLY Bit Fields */
mbed_official 324:406fd2029f23 6343 #define PDB_IDLY_IDLY_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6344 #define PDB_IDLY_IDLY_SHIFT 0
mbed_official 324:406fd2029f23 6345 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
mbed_official 324:406fd2029f23 6346 /* C1 Bit Fields */
mbed_official 324:406fd2029f23 6347 #define PDB_C1_EN_MASK 0xFFu
mbed_official 324:406fd2029f23 6348 #define PDB_C1_EN_SHIFT 0
mbed_official 324:406fd2029f23 6349 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
mbed_official 324:406fd2029f23 6350 #define PDB_C1_TOS_MASK 0xFF00u
mbed_official 324:406fd2029f23 6351 #define PDB_C1_TOS_SHIFT 8
mbed_official 324:406fd2029f23 6352 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
mbed_official 324:406fd2029f23 6353 #define PDB_C1_BB_MASK 0xFF0000u
mbed_official 324:406fd2029f23 6354 #define PDB_C1_BB_SHIFT 16
mbed_official 324:406fd2029f23 6355 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
mbed_official 324:406fd2029f23 6356 /* S Bit Fields */
mbed_official 324:406fd2029f23 6357 #define PDB_S_ERR_MASK 0xFFu
mbed_official 324:406fd2029f23 6358 #define PDB_S_ERR_SHIFT 0
mbed_official 324:406fd2029f23 6359 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
mbed_official 324:406fd2029f23 6360 #define PDB_S_CF_MASK 0xFF0000u
mbed_official 324:406fd2029f23 6361 #define PDB_S_CF_SHIFT 16
mbed_official 324:406fd2029f23 6362 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
mbed_official 324:406fd2029f23 6363 /* DLY Bit Fields */
mbed_official 324:406fd2029f23 6364 #define PDB_DLY_DLY_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6365 #define PDB_DLY_DLY_SHIFT 0
mbed_official 324:406fd2029f23 6366 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
mbed_official 324:406fd2029f23 6367 /* INTC Bit Fields */
mbed_official 324:406fd2029f23 6368 #define PDB_INTC_TOE_MASK 0x1u
mbed_official 324:406fd2029f23 6369 #define PDB_INTC_TOE_SHIFT 0
mbed_official 324:406fd2029f23 6370 #define PDB_INTC_EXT_MASK 0x2u
mbed_official 324:406fd2029f23 6371 #define PDB_INTC_EXT_SHIFT 1
mbed_official 324:406fd2029f23 6372 /* INT Bit Fields */
mbed_official 324:406fd2029f23 6373 #define PDB_INT_INT_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6374 #define PDB_INT_INT_SHIFT 0
mbed_official 324:406fd2029f23 6375 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
mbed_official 324:406fd2029f23 6376 /* POEN Bit Fields */
mbed_official 324:406fd2029f23 6377 #define PDB_POEN_POEN_MASK 0xFFu
mbed_official 324:406fd2029f23 6378 #define PDB_POEN_POEN_SHIFT 0
mbed_official 324:406fd2029f23 6379 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
mbed_official 324:406fd2029f23 6380 /* PODLY Bit Fields */
mbed_official 324:406fd2029f23 6381 #define PDB_PODLY_DLY2_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6382 #define PDB_PODLY_DLY2_SHIFT 0
mbed_official 324:406fd2029f23 6383 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
mbed_official 324:406fd2029f23 6384 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 6385 #define PDB_PODLY_DLY1_SHIFT 16
mbed_official 324:406fd2029f23 6386 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
mbed_official 324:406fd2029f23 6387
mbed_official 324:406fd2029f23 6388 /*!
mbed_official 324:406fd2029f23 6389 * @}
mbed_official 324:406fd2029f23 6390 */ /* end of group PDB_Register_Masks */
mbed_official 324:406fd2029f23 6391
mbed_official 324:406fd2029f23 6392
mbed_official 324:406fd2029f23 6393 /* PDB - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6394 /** Peripheral PDB0 base address */
mbed_official 324:406fd2029f23 6395 #define PDB0_BASE (0x40036000u)
mbed_official 324:406fd2029f23 6396 /** Peripheral PDB0 base pointer */
mbed_official 324:406fd2029f23 6397 #define PDB0 ((PDB_Type *)PDB0_BASE)
mbed_official 324:406fd2029f23 6398 #define PDB0_BASE_PTR (PDB0)
mbed_official 324:406fd2029f23 6399 /** Array initializer of PDB peripheral base addresses */
mbed_official 324:406fd2029f23 6400 #define PDB_BASE_ADDRS { PDB0_BASE }
mbed_official 324:406fd2029f23 6401 /** Array initializer of PDB peripheral base pointers */
mbed_official 324:406fd2029f23 6402 #define PDB_BASE_PTRS { PDB0 }
mbed_official 324:406fd2029f23 6403 /** Interrupt vectors for the PDB peripheral type */
mbed_official 324:406fd2029f23 6404 #define PDB_IRQS { PDB0_IRQn }
mbed_official 324:406fd2029f23 6405
mbed_official 324:406fd2029f23 6406 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6407 -- PDB - Register accessor macros
mbed_official 324:406fd2029f23 6408 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6409
mbed_official 324:406fd2029f23 6410 /*!
mbed_official 324:406fd2029f23 6411 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
mbed_official 324:406fd2029f23 6412 * @{
mbed_official 324:406fd2029f23 6413 */
mbed_official 324:406fd2029f23 6414
mbed_official 324:406fd2029f23 6415
mbed_official 324:406fd2029f23 6416 /* PDB - Register instance definitions */
mbed_official 324:406fd2029f23 6417 /* PDB0 */
mbed_official 324:406fd2029f23 6418 #define PDB0_SC PDB_SC_REG(PDB0)
mbed_official 324:406fd2029f23 6419 #define PDB0_MOD PDB_MOD_REG(PDB0)
mbed_official 324:406fd2029f23 6420 #define PDB0_CNT PDB_CNT_REG(PDB0)
mbed_official 324:406fd2029f23 6421 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
mbed_official 324:406fd2029f23 6422 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
mbed_official 324:406fd2029f23 6423 #define PDB0_CH0S PDB_S_REG(PDB0,0)
mbed_official 324:406fd2029f23 6424 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
mbed_official 324:406fd2029f23 6425 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
mbed_official 324:406fd2029f23 6426 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
mbed_official 324:406fd2029f23 6427 #define PDB0_CH1S PDB_S_REG(PDB0,1)
mbed_official 324:406fd2029f23 6428 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
mbed_official 324:406fd2029f23 6429 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
mbed_official 324:406fd2029f23 6430 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
mbed_official 324:406fd2029f23 6431 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
mbed_official 324:406fd2029f23 6432 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
mbed_official 324:406fd2029f23 6433 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
mbed_official 324:406fd2029f23 6434 #define PDB0_POEN PDB_POEN_REG(PDB0)
mbed_official 324:406fd2029f23 6435 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
mbed_official 324:406fd2029f23 6436 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
mbed_official 324:406fd2029f23 6437
mbed_official 324:406fd2029f23 6438 /* PDB - Register array accessors */
mbed_official 324:406fd2029f23 6439 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
mbed_official 324:406fd2029f23 6440 #define PDB0_S(index) PDB_S_REG(PDB0,index)
mbed_official 324:406fd2029f23 6441 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
mbed_official 324:406fd2029f23 6442 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
mbed_official 324:406fd2029f23 6443 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
mbed_official 324:406fd2029f23 6444 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
mbed_official 324:406fd2029f23 6445
mbed_official 324:406fd2029f23 6446 /*!
mbed_official 324:406fd2029f23 6447 * @}
mbed_official 324:406fd2029f23 6448 */ /* end of group PDB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6449
mbed_official 324:406fd2029f23 6450
mbed_official 324:406fd2029f23 6451 /*!
mbed_official 324:406fd2029f23 6452 * @}
mbed_official 324:406fd2029f23 6453 */ /* end of group PDB_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 6454
mbed_official 324:406fd2029f23 6455
mbed_official 324:406fd2029f23 6456 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6457 -- PIT Peripheral Access Layer
mbed_official 324:406fd2029f23 6458 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6459
mbed_official 324:406fd2029f23 6460 /*!
mbed_official 324:406fd2029f23 6461 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 324:406fd2029f23 6462 * @{
mbed_official 324:406fd2029f23 6463 */
mbed_official 324:406fd2029f23 6464
mbed_official 324:406fd2029f23 6465 /** PIT - Register Layout Typedef */
mbed_official 324:406fd2029f23 6466 typedef struct {
mbed_official 324:406fd2029f23 6467 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 6468 uint8_t RESERVED_0[252];
mbed_official 324:406fd2029f23 6469 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 324:406fd2029f23 6470 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 324:406fd2029f23 6471 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 324:406fd2029f23 6472 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 324:406fd2029f23 6473 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 324:406fd2029f23 6474 } CHANNEL[4];
mbed_official 324:406fd2029f23 6475 } PIT_Type, *PIT_MemMapPtr;
mbed_official 324:406fd2029f23 6476
mbed_official 324:406fd2029f23 6477 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6478 -- PIT - Register accessor macros
mbed_official 324:406fd2029f23 6479 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6480
mbed_official 324:406fd2029f23 6481 /*!
mbed_official 324:406fd2029f23 6482 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 324:406fd2029f23 6483 * @{
mbed_official 324:406fd2029f23 6484 */
mbed_official 324:406fd2029f23 6485
mbed_official 324:406fd2029f23 6486
mbed_official 324:406fd2029f23 6487 /* PIT - Register accessors */
mbed_official 324:406fd2029f23 6488 #define PIT_MCR_REG(base) ((base)->MCR)
mbed_official 324:406fd2029f23 6489 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
mbed_official 324:406fd2029f23 6490 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
mbed_official 324:406fd2029f23 6491 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
mbed_official 324:406fd2029f23 6492 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
mbed_official 324:406fd2029f23 6493
mbed_official 324:406fd2029f23 6494 /*!
mbed_official 324:406fd2029f23 6495 * @}
mbed_official 324:406fd2029f23 6496 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6497
mbed_official 324:406fd2029f23 6498
mbed_official 324:406fd2029f23 6499 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6500 -- PIT Register Masks
mbed_official 324:406fd2029f23 6501 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6502
mbed_official 324:406fd2029f23 6503 /*!
mbed_official 324:406fd2029f23 6504 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 324:406fd2029f23 6505 * @{
mbed_official 324:406fd2029f23 6506 */
mbed_official 324:406fd2029f23 6507
mbed_official 324:406fd2029f23 6508 /* MCR Bit Fields */
mbed_official 324:406fd2029f23 6509 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 324:406fd2029f23 6510 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 324:406fd2029f23 6511 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 324:406fd2029f23 6512 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 324:406fd2029f23 6513 /* LDVAL Bit Fields */
mbed_official 324:406fd2029f23 6514 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 6515 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 324:406fd2029f23 6516 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 324:406fd2029f23 6517 /* CVAL Bit Fields */
mbed_official 324:406fd2029f23 6518 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 6519 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 324:406fd2029f23 6520 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 324:406fd2029f23 6521 /* TCTRL Bit Fields */
mbed_official 324:406fd2029f23 6522 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 324:406fd2029f23 6523 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 324:406fd2029f23 6524 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 324:406fd2029f23 6525 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 324:406fd2029f23 6526 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 324:406fd2029f23 6527 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 324:406fd2029f23 6528 /* TFLG Bit Fields */
mbed_official 324:406fd2029f23 6529 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 324:406fd2029f23 6530 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 324:406fd2029f23 6531
mbed_official 324:406fd2029f23 6532 /*!
mbed_official 324:406fd2029f23 6533 * @}
mbed_official 324:406fd2029f23 6534 */ /* end of group PIT_Register_Masks */
mbed_official 324:406fd2029f23 6535
mbed_official 324:406fd2029f23 6536
mbed_official 324:406fd2029f23 6537 /* PIT - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6538 /** Peripheral PIT base address */
mbed_official 324:406fd2029f23 6539 #define PIT_BASE (0x40037000u)
mbed_official 324:406fd2029f23 6540 /** Peripheral PIT base pointer */
mbed_official 324:406fd2029f23 6541 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 324:406fd2029f23 6542 #define PIT_BASE_PTR (PIT)
mbed_official 324:406fd2029f23 6543 /** Array initializer of PIT peripheral base addresses */
mbed_official 324:406fd2029f23 6544 #define PIT_BASE_ADDRS { PIT_BASE }
mbed_official 324:406fd2029f23 6545 /** Array initializer of PIT peripheral base pointers */
mbed_official 324:406fd2029f23 6546 #define PIT_BASE_PTRS { PIT }
mbed_official 324:406fd2029f23 6547 /** Interrupt vectors for the PIT peripheral type */
mbed_official 324:406fd2029f23 6548 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
mbed_official 324:406fd2029f23 6549
mbed_official 324:406fd2029f23 6550 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6551 -- PIT - Register accessor macros
mbed_official 324:406fd2029f23 6552 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6553
mbed_official 324:406fd2029f23 6554 /*!
mbed_official 324:406fd2029f23 6555 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 324:406fd2029f23 6556 * @{
mbed_official 324:406fd2029f23 6557 */
mbed_official 324:406fd2029f23 6558
mbed_official 324:406fd2029f23 6559
mbed_official 324:406fd2029f23 6560 /* PIT - Register instance definitions */
mbed_official 324:406fd2029f23 6561 /* PIT */
mbed_official 324:406fd2029f23 6562 #define PIT_MCR PIT_MCR_REG(PIT)
mbed_official 324:406fd2029f23 6563 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
mbed_official 324:406fd2029f23 6564 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
mbed_official 324:406fd2029f23 6565 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
mbed_official 324:406fd2029f23 6566 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
mbed_official 324:406fd2029f23 6567 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
mbed_official 324:406fd2029f23 6568 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
mbed_official 324:406fd2029f23 6569 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
mbed_official 324:406fd2029f23 6570 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
mbed_official 324:406fd2029f23 6571 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
mbed_official 324:406fd2029f23 6572 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
mbed_official 324:406fd2029f23 6573 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
mbed_official 324:406fd2029f23 6574 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
mbed_official 324:406fd2029f23 6575 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
mbed_official 324:406fd2029f23 6576 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
mbed_official 324:406fd2029f23 6577 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
mbed_official 324:406fd2029f23 6578 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
mbed_official 324:406fd2029f23 6579
mbed_official 324:406fd2029f23 6580 /* PIT - Register array accessors */
mbed_official 324:406fd2029f23 6581 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
mbed_official 324:406fd2029f23 6582 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
mbed_official 324:406fd2029f23 6583 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
mbed_official 324:406fd2029f23 6584 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
mbed_official 324:406fd2029f23 6585
mbed_official 324:406fd2029f23 6586 /*!
mbed_official 324:406fd2029f23 6587 * @}
mbed_official 324:406fd2029f23 6588 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6589
mbed_official 324:406fd2029f23 6590
mbed_official 324:406fd2029f23 6591 /*!
mbed_official 324:406fd2029f23 6592 * @}
mbed_official 324:406fd2029f23 6593 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 6594
mbed_official 324:406fd2029f23 6595
mbed_official 324:406fd2029f23 6596 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6597 -- PMC Peripheral Access Layer
mbed_official 324:406fd2029f23 6598 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6599
mbed_official 324:406fd2029f23 6600 /*!
mbed_official 324:406fd2029f23 6601 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 324:406fd2029f23 6602 * @{
mbed_official 324:406fd2029f23 6603 */
mbed_official 324:406fd2029f23 6604
mbed_official 324:406fd2029f23 6605 /** PMC - Register Layout Typedef */
mbed_official 324:406fd2029f23 6606 typedef struct {
mbed_official 324:406fd2029f23 6607 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 324:406fd2029f23 6608 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 324:406fd2029f23 6609 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 324:406fd2029f23 6610 } PMC_Type, *PMC_MemMapPtr;
mbed_official 324:406fd2029f23 6611
mbed_official 324:406fd2029f23 6612 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6613 -- PMC - Register accessor macros
mbed_official 324:406fd2029f23 6614 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6615
mbed_official 324:406fd2029f23 6616 /*!
mbed_official 324:406fd2029f23 6617 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 324:406fd2029f23 6618 * @{
mbed_official 324:406fd2029f23 6619 */
mbed_official 324:406fd2029f23 6620
mbed_official 324:406fd2029f23 6621
mbed_official 324:406fd2029f23 6622 /* PMC - Register accessors */
mbed_official 324:406fd2029f23 6623 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
mbed_official 324:406fd2029f23 6624 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
mbed_official 324:406fd2029f23 6625 #define PMC_REGSC_REG(base) ((base)->REGSC)
mbed_official 324:406fd2029f23 6626
mbed_official 324:406fd2029f23 6627 /*!
mbed_official 324:406fd2029f23 6628 * @}
mbed_official 324:406fd2029f23 6629 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6630
mbed_official 324:406fd2029f23 6631
mbed_official 324:406fd2029f23 6632 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6633 -- PMC Register Masks
mbed_official 324:406fd2029f23 6634 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6635
mbed_official 324:406fd2029f23 6636 /*!
mbed_official 324:406fd2029f23 6637 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 324:406fd2029f23 6638 * @{
mbed_official 324:406fd2029f23 6639 */
mbed_official 324:406fd2029f23 6640
mbed_official 324:406fd2029f23 6641 /* LVDSC1 Bit Fields */
mbed_official 324:406fd2029f23 6642 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 324:406fd2029f23 6643 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 324:406fd2029f23 6644 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 324:406fd2029f23 6645 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 324:406fd2029f23 6646 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 324:406fd2029f23 6647 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 324:406fd2029f23 6648 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 324:406fd2029f23 6649 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 324:406fd2029f23 6650 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 324:406fd2029f23 6651 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 324:406fd2029f23 6652 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 324:406fd2029f23 6653 /* LVDSC2 Bit Fields */
mbed_official 324:406fd2029f23 6654 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 324:406fd2029f23 6655 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 324:406fd2029f23 6656 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 324:406fd2029f23 6657 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 324:406fd2029f23 6658 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 324:406fd2029f23 6659 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 324:406fd2029f23 6660 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 324:406fd2029f23 6661 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 324:406fd2029f23 6662 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 324:406fd2029f23 6663 /* REGSC Bit Fields */
mbed_official 324:406fd2029f23 6664 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 324:406fd2029f23 6665 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 324:406fd2029f23 6666 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 324:406fd2029f23 6667 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 324:406fd2029f23 6668 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 324:406fd2029f23 6669 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 324:406fd2029f23 6670 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 324:406fd2029f23 6671 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 324:406fd2029f23 6672
mbed_official 324:406fd2029f23 6673 /*!
mbed_official 324:406fd2029f23 6674 * @}
mbed_official 324:406fd2029f23 6675 */ /* end of group PMC_Register_Masks */
mbed_official 324:406fd2029f23 6676
mbed_official 324:406fd2029f23 6677
mbed_official 324:406fd2029f23 6678 /* PMC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6679 /** Peripheral PMC base address */
mbed_official 324:406fd2029f23 6680 #define PMC_BASE (0x4007D000u)
mbed_official 324:406fd2029f23 6681 /** Peripheral PMC base pointer */
mbed_official 324:406fd2029f23 6682 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 324:406fd2029f23 6683 #define PMC_BASE_PTR (PMC)
mbed_official 324:406fd2029f23 6684 /** Array initializer of PMC peripheral base addresses */
mbed_official 324:406fd2029f23 6685 #define PMC_BASE_ADDRS { PMC_BASE }
mbed_official 324:406fd2029f23 6686 /** Array initializer of PMC peripheral base pointers */
mbed_official 324:406fd2029f23 6687 #define PMC_BASE_PTRS { PMC }
mbed_official 324:406fd2029f23 6688 /** Interrupt vectors for the PMC peripheral type */
mbed_official 324:406fd2029f23 6689 #define PMC_IRQS { LVD_LVW_IRQn }
mbed_official 324:406fd2029f23 6690
mbed_official 324:406fd2029f23 6691 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6692 -- PMC - Register accessor macros
mbed_official 324:406fd2029f23 6693 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6694
mbed_official 324:406fd2029f23 6695 /*!
mbed_official 324:406fd2029f23 6696 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 324:406fd2029f23 6697 * @{
mbed_official 324:406fd2029f23 6698 */
mbed_official 324:406fd2029f23 6699
mbed_official 324:406fd2029f23 6700
mbed_official 324:406fd2029f23 6701 /* PMC - Register instance definitions */
mbed_official 324:406fd2029f23 6702 /* PMC */
mbed_official 324:406fd2029f23 6703 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
mbed_official 324:406fd2029f23 6704 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
mbed_official 324:406fd2029f23 6705 #define PMC_REGSC PMC_REGSC_REG(PMC)
mbed_official 324:406fd2029f23 6706
mbed_official 324:406fd2029f23 6707 /*!
mbed_official 324:406fd2029f23 6708 * @}
mbed_official 324:406fd2029f23 6709 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6710
mbed_official 324:406fd2029f23 6711
mbed_official 324:406fd2029f23 6712 /*!
mbed_official 324:406fd2029f23 6713 * @}
mbed_official 324:406fd2029f23 6714 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 6715
mbed_official 324:406fd2029f23 6716
mbed_official 324:406fd2029f23 6717 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6718 -- PORT Peripheral Access Layer
mbed_official 324:406fd2029f23 6719 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6720
mbed_official 324:406fd2029f23 6721 /*!
mbed_official 324:406fd2029f23 6722 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 324:406fd2029f23 6723 * @{
mbed_official 324:406fd2029f23 6724 */
mbed_official 324:406fd2029f23 6725
mbed_official 324:406fd2029f23 6726 /** PORT - Register Layout Typedef */
mbed_official 324:406fd2029f23 6727 typedef struct {
mbed_official 324:406fd2029f23 6728 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 324:406fd2029f23 6729 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 324:406fd2029f23 6730 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 324:406fd2029f23 6731 uint8_t RESERVED_0[24];
mbed_official 324:406fd2029f23 6732 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 324:406fd2029f23 6733 uint8_t RESERVED_1[28];
mbed_official 324:406fd2029f23 6734 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
mbed_official 324:406fd2029f23 6735 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
mbed_official 324:406fd2029f23 6736 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
mbed_official 324:406fd2029f23 6737 } PORT_Type, *PORT_MemMapPtr;
mbed_official 324:406fd2029f23 6738
mbed_official 324:406fd2029f23 6739 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6740 -- PORT - Register accessor macros
mbed_official 324:406fd2029f23 6741 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6742
mbed_official 324:406fd2029f23 6743 /*!
mbed_official 324:406fd2029f23 6744 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 324:406fd2029f23 6745 * @{
mbed_official 324:406fd2029f23 6746 */
mbed_official 324:406fd2029f23 6747
mbed_official 324:406fd2029f23 6748
mbed_official 324:406fd2029f23 6749 /* PORT - Register accessors */
mbed_official 324:406fd2029f23 6750 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
mbed_official 324:406fd2029f23 6751 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
mbed_official 324:406fd2029f23 6752 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
mbed_official 324:406fd2029f23 6753 #define PORT_ISFR_REG(base) ((base)->ISFR)
mbed_official 324:406fd2029f23 6754 #define PORT_DFER_REG(base) ((base)->DFER)
mbed_official 324:406fd2029f23 6755 #define PORT_DFCR_REG(base) ((base)->DFCR)
mbed_official 324:406fd2029f23 6756 #define PORT_DFWR_REG(base) ((base)->DFWR)
mbed_official 324:406fd2029f23 6757
mbed_official 324:406fd2029f23 6758 /*!
mbed_official 324:406fd2029f23 6759 * @}
mbed_official 324:406fd2029f23 6760 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 6761
mbed_official 324:406fd2029f23 6762
mbed_official 324:406fd2029f23 6763 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6764 -- PORT Register Masks
mbed_official 324:406fd2029f23 6765 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6766
mbed_official 324:406fd2029f23 6767 /*!
mbed_official 324:406fd2029f23 6768 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 324:406fd2029f23 6769 * @{
mbed_official 324:406fd2029f23 6770 */
mbed_official 324:406fd2029f23 6771
mbed_official 324:406fd2029f23 6772 /* PCR Bit Fields */
mbed_official 324:406fd2029f23 6773 #define PORT_PCR_PS_MASK 0x1u
mbed_official 324:406fd2029f23 6774 #define PORT_PCR_PS_SHIFT 0
mbed_official 324:406fd2029f23 6775 #define PORT_PCR_PE_MASK 0x2u
mbed_official 324:406fd2029f23 6776 #define PORT_PCR_PE_SHIFT 1
mbed_official 324:406fd2029f23 6777 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 324:406fd2029f23 6778 #define PORT_PCR_SRE_SHIFT 2
mbed_official 324:406fd2029f23 6779 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 324:406fd2029f23 6780 #define PORT_PCR_PFE_SHIFT 4
mbed_official 324:406fd2029f23 6781 #define PORT_PCR_ODE_MASK 0x20u
mbed_official 324:406fd2029f23 6782 #define PORT_PCR_ODE_SHIFT 5
mbed_official 324:406fd2029f23 6783 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 324:406fd2029f23 6784 #define PORT_PCR_DSE_SHIFT 6
mbed_official 324:406fd2029f23 6785 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 324:406fd2029f23 6786 #define PORT_PCR_MUX_SHIFT 8
mbed_official 324:406fd2029f23 6787 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 324:406fd2029f23 6788 #define PORT_PCR_LK_MASK 0x8000u
mbed_official 324:406fd2029f23 6789 #define PORT_PCR_LK_SHIFT 15
mbed_official 324:406fd2029f23 6790 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 324:406fd2029f23 6791 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 324:406fd2029f23 6792 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 324:406fd2029f23 6793 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 324:406fd2029f23 6794 #define PORT_PCR_ISF_SHIFT 24
mbed_official 324:406fd2029f23 6795 /* GPCLR Bit Fields */
mbed_official 324:406fd2029f23 6796 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6797 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 324:406fd2029f23 6798 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 324:406fd2029f23 6799 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 6800 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 324:406fd2029f23 6801 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 324:406fd2029f23 6802 /* GPCHR Bit Fields */
mbed_official 324:406fd2029f23 6803 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 324:406fd2029f23 6804 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 324:406fd2029f23 6805 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 324:406fd2029f23 6806 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 6807 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 324:406fd2029f23 6808 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 324:406fd2029f23 6809 /* ISFR Bit Fields */
mbed_official 324:406fd2029f23 6810 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 6811 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 324:406fd2029f23 6812 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 324:406fd2029f23 6813 /* DFER Bit Fields */
mbed_official 324:406fd2029f23 6814 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 6815 #define PORT_DFER_DFE_SHIFT 0
mbed_official 324:406fd2029f23 6816 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
mbed_official 324:406fd2029f23 6817 /* DFCR Bit Fields */
mbed_official 324:406fd2029f23 6818 #define PORT_DFCR_CS_MASK 0x1u
mbed_official 324:406fd2029f23 6819 #define PORT_DFCR_CS_SHIFT 0
mbed_official 324:406fd2029f23 6820 /* DFWR Bit Fields */
mbed_official 324:406fd2029f23 6821 #define PORT_DFWR_FILT_MASK 0x1Fu
mbed_official 324:406fd2029f23 6822 #define PORT_DFWR_FILT_SHIFT 0
mbed_official 324:406fd2029f23 6823 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
mbed_official 324:406fd2029f23 6824
mbed_official 324:406fd2029f23 6825 /*!
mbed_official 324:406fd2029f23 6826 * @}
mbed_official 324:406fd2029f23 6827 */ /* end of group PORT_Register_Masks */
mbed_official 324:406fd2029f23 6828
mbed_official 324:406fd2029f23 6829
mbed_official 324:406fd2029f23 6830 /* PORT - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 6831 /** Peripheral PORTA base address */
mbed_official 324:406fd2029f23 6832 #define PORTA_BASE (0x40049000u)
mbed_official 324:406fd2029f23 6833 /** Peripheral PORTA base pointer */
mbed_official 324:406fd2029f23 6834 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 324:406fd2029f23 6835 #define PORTA_BASE_PTR (PORTA)
mbed_official 324:406fd2029f23 6836 /** Peripheral PORTB base address */
mbed_official 324:406fd2029f23 6837 #define PORTB_BASE (0x4004A000u)
mbed_official 324:406fd2029f23 6838 /** Peripheral PORTB base pointer */
mbed_official 324:406fd2029f23 6839 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 324:406fd2029f23 6840 #define PORTB_BASE_PTR (PORTB)
mbed_official 324:406fd2029f23 6841 /** Peripheral PORTC base address */
mbed_official 324:406fd2029f23 6842 #define PORTC_BASE (0x4004B000u)
mbed_official 324:406fd2029f23 6843 /** Peripheral PORTC base pointer */
mbed_official 324:406fd2029f23 6844 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 324:406fd2029f23 6845 #define PORTC_BASE_PTR (PORTC)
mbed_official 324:406fd2029f23 6846 /** Peripheral PORTD base address */
mbed_official 324:406fd2029f23 6847 #define PORTD_BASE (0x4004C000u)
mbed_official 324:406fd2029f23 6848 /** Peripheral PORTD base pointer */
mbed_official 324:406fd2029f23 6849 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 324:406fd2029f23 6850 #define PORTD_BASE_PTR (PORTD)
mbed_official 324:406fd2029f23 6851 /** Peripheral PORTE base address */
mbed_official 324:406fd2029f23 6852 #define PORTE_BASE (0x4004D000u)
mbed_official 324:406fd2029f23 6853 /** Peripheral PORTE base pointer */
mbed_official 324:406fd2029f23 6854 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 324:406fd2029f23 6855 #define PORTE_BASE_PTR (PORTE)
mbed_official 324:406fd2029f23 6856 /** Array initializer of PORT peripheral base addresses */
mbed_official 324:406fd2029f23 6857 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
mbed_official 324:406fd2029f23 6858 /** Array initializer of PORT peripheral base pointers */
mbed_official 324:406fd2029f23 6859 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 324:406fd2029f23 6860 /** Interrupt vectors for the PORT peripheral type */
mbed_official 324:406fd2029f23 6861 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
mbed_official 324:406fd2029f23 6862
mbed_official 324:406fd2029f23 6863 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 6864 -- PORT - Register accessor macros
mbed_official 324:406fd2029f23 6865 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 6866
mbed_official 324:406fd2029f23 6867 /*!
mbed_official 324:406fd2029f23 6868 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 324:406fd2029f23 6869 * @{
mbed_official 324:406fd2029f23 6870 */
mbed_official 324:406fd2029f23 6871
mbed_official 324:406fd2029f23 6872
mbed_official 324:406fd2029f23 6873 /* PORT - Register instance definitions */
mbed_official 324:406fd2029f23 6874 /* PORTA */
mbed_official 324:406fd2029f23 6875 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
mbed_official 324:406fd2029f23 6876 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
mbed_official 324:406fd2029f23 6877 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
mbed_official 324:406fd2029f23 6878 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
mbed_official 324:406fd2029f23 6879 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
mbed_official 324:406fd2029f23 6880 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
mbed_official 324:406fd2029f23 6881 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
mbed_official 324:406fd2029f23 6882 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
mbed_official 324:406fd2029f23 6883 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
mbed_official 324:406fd2029f23 6884 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
mbed_official 324:406fd2029f23 6885 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
mbed_official 324:406fd2029f23 6886 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
mbed_official 324:406fd2029f23 6887 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
mbed_official 324:406fd2029f23 6888 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
mbed_official 324:406fd2029f23 6889 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
mbed_official 324:406fd2029f23 6890 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
mbed_official 324:406fd2029f23 6891 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
mbed_official 324:406fd2029f23 6892 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
mbed_official 324:406fd2029f23 6893 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
mbed_official 324:406fd2029f23 6894 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
mbed_official 324:406fd2029f23 6895 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
mbed_official 324:406fd2029f23 6896 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
mbed_official 324:406fd2029f23 6897 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
mbed_official 324:406fd2029f23 6898 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
mbed_official 324:406fd2029f23 6899 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
mbed_official 324:406fd2029f23 6900 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
mbed_official 324:406fd2029f23 6901 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
mbed_official 324:406fd2029f23 6902 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
mbed_official 324:406fd2029f23 6903 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
mbed_official 324:406fd2029f23 6904 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
mbed_official 324:406fd2029f23 6905 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
mbed_official 324:406fd2029f23 6906 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
mbed_official 324:406fd2029f23 6907 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
mbed_official 324:406fd2029f23 6908 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
mbed_official 324:406fd2029f23 6909 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
mbed_official 324:406fd2029f23 6910 /* PORTB */
mbed_official 324:406fd2029f23 6911 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
mbed_official 324:406fd2029f23 6912 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
mbed_official 324:406fd2029f23 6913 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
mbed_official 324:406fd2029f23 6914 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
mbed_official 324:406fd2029f23 6915 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
mbed_official 324:406fd2029f23 6916 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
mbed_official 324:406fd2029f23 6917 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
mbed_official 324:406fd2029f23 6918 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
mbed_official 324:406fd2029f23 6919 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
mbed_official 324:406fd2029f23 6920 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
mbed_official 324:406fd2029f23 6921 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
mbed_official 324:406fd2029f23 6922 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
mbed_official 324:406fd2029f23 6923 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
mbed_official 324:406fd2029f23 6924 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
mbed_official 324:406fd2029f23 6925 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
mbed_official 324:406fd2029f23 6926 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
mbed_official 324:406fd2029f23 6927 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
mbed_official 324:406fd2029f23 6928 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
mbed_official 324:406fd2029f23 6929 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
mbed_official 324:406fd2029f23 6930 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
mbed_official 324:406fd2029f23 6931 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
mbed_official 324:406fd2029f23 6932 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
mbed_official 324:406fd2029f23 6933 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
mbed_official 324:406fd2029f23 6934 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
mbed_official 324:406fd2029f23 6935 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
mbed_official 324:406fd2029f23 6936 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
mbed_official 324:406fd2029f23 6937 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
mbed_official 324:406fd2029f23 6938 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
mbed_official 324:406fd2029f23 6939 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
mbed_official 324:406fd2029f23 6940 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
mbed_official 324:406fd2029f23 6941 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
mbed_official 324:406fd2029f23 6942 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
mbed_official 324:406fd2029f23 6943 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
mbed_official 324:406fd2029f23 6944 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
mbed_official 324:406fd2029f23 6945 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
mbed_official 324:406fd2029f23 6946 /* PORTC */
mbed_official 324:406fd2029f23 6947 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
mbed_official 324:406fd2029f23 6948 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
mbed_official 324:406fd2029f23 6949 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
mbed_official 324:406fd2029f23 6950 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
mbed_official 324:406fd2029f23 6951 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
mbed_official 324:406fd2029f23 6952 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
mbed_official 324:406fd2029f23 6953 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
mbed_official 324:406fd2029f23 6954 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
mbed_official 324:406fd2029f23 6955 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
mbed_official 324:406fd2029f23 6956 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
mbed_official 324:406fd2029f23 6957 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
mbed_official 324:406fd2029f23 6958 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
mbed_official 324:406fd2029f23 6959 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
mbed_official 324:406fd2029f23 6960 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
mbed_official 324:406fd2029f23 6961 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
mbed_official 324:406fd2029f23 6962 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
mbed_official 324:406fd2029f23 6963 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
mbed_official 324:406fd2029f23 6964 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
mbed_official 324:406fd2029f23 6965 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
mbed_official 324:406fd2029f23 6966 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
mbed_official 324:406fd2029f23 6967 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
mbed_official 324:406fd2029f23 6968 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
mbed_official 324:406fd2029f23 6969 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
mbed_official 324:406fd2029f23 6970 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
mbed_official 324:406fd2029f23 6971 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
mbed_official 324:406fd2029f23 6972 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
mbed_official 324:406fd2029f23 6973 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
mbed_official 324:406fd2029f23 6974 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
mbed_official 324:406fd2029f23 6975 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
mbed_official 324:406fd2029f23 6976 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
mbed_official 324:406fd2029f23 6977 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
mbed_official 324:406fd2029f23 6978 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
mbed_official 324:406fd2029f23 6979 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
mbed_official 324:406fd2029f23 6980 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
mbed_official 324:406fd2029f23 6981 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
mbed_official 324:406fd2029f23 6982 /* PORTD */
mbed_official 324:406fd2029f23 6983 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
mbed_official 324:406fd2029f23 6984 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
mbed_official 324:406fd2029f23 6985 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
mbed_official 324:406fd2029f23 6986 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
mbed_official 324:406fd2029f23 6987 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
mbed_official 324:406fd2029f23 6988 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
mbed_official 324:406fd2029f23 6989 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
mbed_official 324:406fd2029f23 6990 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
mbed_official 324:406fd2029f23 6991 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
mbed_official 324:406fd2029f23 6992 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
mbed_official 324:406fd2029f23 6993 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
mbed_official 324:406fd2029f23 6994 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
mbed_official 324:406fd2029f23 6995 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
mbed_official 324:406fd2029f23 6996 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
mbed_official 324:406fd2029f23 6997 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
mbed_official 324:406fd2029f23 6998 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
mbed_official 324:406fd2029f23 6999 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
mbed_official 324:406fd2029f23 7000 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
mbed_official 324:406fd2029f23 7001 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
mbed_official 324:406fd2029f23 7002 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
mbed_official 324:406fd2029f23 7003 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
mbed_official 324:406fd2029f23 7004 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
mbed_official 324:406fd2029f23 7005 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
mbed_official 324:406fd2029f23 7006 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
mbed_official 324:406fd2029f23 7007 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
mbed_official 324:406fd2029f23 7008 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
mbed_official 324:406fd2029f23 7009 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
mbed_official 324:406fd2029f23 7010 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
mbed_official 324:406fd2029f23 7011 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
mbed_official 324:406fd2029f23 7012 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
mbed_official 324:406fd2029f23 7013 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
mbed_official 324:406fd2029f23 7014 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
mbed_official 324:406fd2029f23 7015 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
mbed_official 324:406fd2029f23 7016 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
mbed_official 324:406fd2029f23 7017 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
mbed_official 324:406fd2029f23 7018 #define PORTD_DFER PORT_DFER_REG(PORTD)
mbed_official 324:406fd2029f23 7019 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
mbed_official 324:406fd2029f23 7020 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
mbed_official 324:406fd2029f23 7021 /* PORTE */
mbed_official 324:406fd2029f23 7022 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
mbed_official 324:406fd2029f23 7023 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
mbed_official 324:406fd2029f23 7024 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
mbed_official 324:406fd2029f23 7025 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
mbed_official 324:406fd2029f23 7026 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
mbed_official 324:406fd2029f23 7027 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
mbed_official 324:406fd2029f23 7028 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
mbed_official 324:406fd2029f23 7029 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
mbed_official 324:406fd2029f23 7030 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
mbed_official 324:406fd2029f23 7031 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
mbed_official 324:406fd2029f23 7032 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
mbed_official 324:406fd2029f23 7033 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
mbed_official 324:406fd2029f23 7034 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
mbed_official 324:406fd2029f23 7035 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
mbed_official 324:406fd2029f23 7036 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
mbed_official 324:406fd2029f23 7037 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
mbed_official 324:406fd2029f23 7038 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
mbed_official 324:406fd2029f23 7039 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
mbed_official 324:406fd2029f23 7040 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
mbed_official 324:406fd2029f23 7041 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
mbed_official 324:406fd2029f23 7042 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
mbed_official 324:406fd2029f23 7043 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
mbed_official 324:406fd2029f23 7044 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
mbed_official 324:406fd2029f23 7045 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
mbed_official 324:406fd2029f23 7046 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
mbed_official 324:406fd2029f23 7047 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
mbed_official 324:406fd2029f23 7048 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
mbed_official 324:406fd2029f23 7049 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
mbed_official 324:406fd2029f23 7050 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
mbed_official 324:406fd2029f23 7051 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
mbed_official 324:406fd2029f23 7052 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
mbed_official 324:406fd2029f23 7053 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
mbed_official 324:406fd2029f23 7054 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
mbed_official 324:406fd2029f23 7055 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
mbed_official 324:406fd2029f23 7056 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
mbed_official 324:406fd2029f23 7057
mbed_official 324:406fd2029f23 7058 /* PORT - Register array accessors */
mbed_official 324:406fd2029f23 7059 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
mbed_official 324:406fd2029f23 7060 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
mbed_official 324:406fd2029f23 7061 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
mbed_official 324:406fd2029f23 7062 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
mbed_official 324:406fd2029f23 7063 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
mbed_official 324:406fd2029f23 7064
mbed_official 324:406fd2029f23 7065 /*!
mbed_official 324:406fd2029f23 7066 * @}
mbed_official 324:406fd2029f23 7067 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7068
mbed_official 324:406fd2029f23 7069
mbed_official 324:406fd2029f23 7070 /*!
mbed_official 324:406fd2029f23 7071 * @}
mbed_official 324:406fd2029f23 7072 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7073
mbed_official 324:406fd2029f23 7074
mbed_official 324:406fd2029f23 7075 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7076 -- RCM Peripheral Access Layer
mbed_official 324:406fd2029f23 7077 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7078
mbed_official 324:406fd2029f23 7079 /*!
mbed_official 324:406fd2029f23 7080 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 324:406fd2029f23 7081 * @{
mbed_official 324:406fd2029f23 7082 */
mbed_official 324:406fd2029f23 7083
mbed_official 324:406fd2029f23 7084 /** RCM - Register Layout Typedef */
mbed_official 324:406fd2029f23 7085 typedef struct {
mbed_official 324:406fd2029f23 7086 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 324:406fd2029f23 7087 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 324:406fd2029f23 7088 uint8_t RESERVED_0[2];
mbed_official 324:406fd2029f23 7089 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 324:406fd2029f23 7090 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 324:406fd2029f23 7091 uint8_t RESERVED_1[1];
mbed_official 324:406fd2029f23 7092 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
mbed_official 324:406fd2029f23 7093 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
mbed_official 324:406fd2029f23 7094 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
mbed_official 324:406fd2029f23 7095 } RCM_Type, *RCM_MemMapPtr;
mbed_official 324:406fd2029f23 7096
mbed_official 324:406fd2029f23 7097 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7098 -- RCM - Register accessor macros
mbed_official 324:406fd2029f23 7099 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7100
mbed_official 324:406fd2029f23 7101 /*!
mbed_official 324:406fd2029f23 7102 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 324:406fd2029f23 7103 * @{
mbed_official 324:406fd2029f23 7104 */
mbed_official 324:406fd2029f23 7105
mbed_official 324:406fd2029f23 7106
mbed_official 324:406fd2029f23 7107 /* RCM - Register accessors */
mbed_official 324:406fd2029f23 7108 #define RCM_SRS0_REG(base) ((base)->SRS0)
mbed_official 324:406fd2029f23 7109 #define RCM_SRS1_REG(base) ((base)->SRS1)
mbed_official 324:406fd2029f23 7110 #define RCM_RPFC_REG(base) ((base)->RPFC)
mbed_official 324:406fd2029f23 7111 #define RCM_RPFW_REG(base) ((base)->RPFW)
mbed_official 324:406fd2029f23 7112 #define RCM_MR_REG(base) ((base)->MR)
mbed_official 324:406fd2029f23 7113 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
mbed_official 324:406fd2029f23 7114 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
mbed_official 324:406fd2029f23 7115
mbed_official 324:406fd2029f23 7116 /*!
mbed_official 324:406fd2029f23 7117 * @}
mbed_official 324:406fd2029f23 7118 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7119
mbed_official 324:406fd2029f23 7120
mbed_official 324:406fd2029f23 7121 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7122 -- RCM Register Masks
mbed_official 324:406fd2029f23 7123 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7124
mbed_official 324:406fd2029f23 7125 /*!
mbed_official 324:406fd2029f23 7126 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 324:406fd2029f23 7127 * @{
mbed_official 324:406fd2029f23 7128 */
mbed_official 324:406fd2029f23 7129
mbed_official 324:406fd2029f23 7130 /* SRS0 Bit Fields */
mbed_official 324:406fd2029f23 7131 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 324:406fd2029f23 7132 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 324:406fd2029f23 7133 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 324:406fd2029f23 7134 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 324:406fd2029f23 7135 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 324:406fd2029f23 7136 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 324:406fd2029f23 7137 #define RCM_SRS0_LOL_MASK 0x8u
mbed_official 324:406fd2029f23 7138 #define RCM_SRS0_LOL_SHIFT 3
mbed_official 324:406fd2029f23 7139 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 324:406fd2029f23 7140 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 324:406fd2029f23 7141 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 324:406fd2029f23 7142 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 324:406fd2029f23 7143 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 324:406fd2029f23 7144 #define RCM_SRS0_POR_SHIFT 7
mbed_official 324:406fd2029f23 7145 /* SRS1 Bit Fields */
mbed_official 324:406fd2029f23 7146 #define RCM_SRS1_JTAG_MASK 0x1u
mbed_official 324:406fd2029f23 7147 #define RCM_SRS1_JTAG_SHIFT 0
mbed_official 324:406fd2029f23 7148 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 324:406fd2029f23 7149 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 324:406fd2029f23 7150 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 324:406fd2029f23 7151 #define RCM_SRS1_SW_SHIFT 2
mbed_official 324:406fd2029f23 7152 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 324:406fd2029f23 7153 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 324:406fd2029f23 7154 #define RCM_SRS1_EZPT_MASK 0x10u
mbed_official 324:406fd2029f23 7155 #define RCM_SRS1_EZPT_SHIFT 4
mbed_official 324:406fd2029f23 7156 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 324:406fd2029f23 7157 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 324:406fd2029f23 7158 /* RPFC Bit Fields */
mbed_official 324:406fd2029f23 7159 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 324:406fd2029f23 7160 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 324:406fd2029f23 7161 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 324:406fd2029f23 7162 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 324:406fd2029f23 7163 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 324:406fd2029f23 7164 /* RPFW Bit Fields */
mbed_official 324:406fd2029f23 7165 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 324:406fd2029f23 7166 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 324:406fd2029f23 7167 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 324:406fd2029f23 7168 /* MR Bit Fields */
mbed_official 324:406fd2029f23 7169 #define RCM_MR_EZP_MS_MASK 0x2u
mbed_official 324:406fd2029f23 7170 #define RCM_MR_EZP_MS_SHIFT 1
mbed_official 324:406fd2029f23 7171 /* SSRS0 Bit Fields */
mbed_official 324:406fd2029f23 7172 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
mbed_official 324:406fd2029f23 7173 #define RCM_SSRS0_SWAKEUP_SHIFT 0
mbed_official 324:406fd2029f23 7174 #define RCM_SSRS0_SLVD_MASK 0x2u
mbed_official 324:406fd2029f23 7175 #define RCM_SSRS0_SLVD_SHIFT 1
mbed_official 324:406fd2029f23 7176 #define RCM_SSRS0_SLOC_MASK 0x4u
mbed_official 324:406fd2029f23 7177 #define RCM_SSRS0_SLOC_SHIFT 2
mbed_official 324:406fd2029f23 7178 #define RCM_SSRS0_SLOL_MASK 0x8u
mbed_official 324:406fd2029f23 7179 #define RCM_SSRS0_SLOL_SHIFT 3
mbed_official 324:406fd2029f23 7180 #define RCM_SSRS0_SWDOG_MASK 0x20u
mbed_official 324:406fd2029f23 7181 #define RCM_SSRS0_SWDOG_SHIFT 5
mbed_official 324:406fd2029f23 7182 #define RCM_SSRS0_SPIN_MASK 0x40u
mbed_official 324:406fd2029f23 7183 #define RCM_SSRS0_SPIN_SHIFT 6
mbed_official 324:406fd2029f23 7184 #define RCM_SSRS0_SPOR_MASK 0x80u
mbed_official 324:406fd2029f23 7185 #define RCM_SSRS0_SPOR_SHIFT 7
mbed_official 324:406fd2029f23 7186 /* SSRS1 Bit Fields */
mbed_official 324:406fd2029f23 7187 #define RCM_SSRS1_SJTAG_MASK 0x1u
mbed_official 324:406fd2029f23 7188 #define RCM_SSRS1_SJTAG_SHIFT 0
mbed_official 324:406fd2029f23 7189 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
mbed_official 324:406fd2029f23 7190 #define RCM_SSRS1_SLOCKUP_SHIFT 1
mbed_official 324:406fd2029f23 7191 #define RCM_SSRS1_SSW_MASK 0x4u
mbed_official 324:406fd2029f23 7192 #define RCM_SSRS1_SSW_SHIFT 2
mbed_official 324:406fd2029f23 7193 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
mbed_official 324:406fd2029f23 7194 #define RCM_SSRS1_SMDM_AP_SHIFT 3
mbed_official 324:406fd2029f23 7195 #define RCM_SSRS1_SEZPT_MASK 0x10u
mbed_official 324:406fd2029f23 7196 #define RCM_SSRS1_SEZPT_SHIFT 4
mbed_official 324:406fd2029f23 7197 #define RCM_SSRS1_SSACKERR_MASK 0x20u
mbed_official 324:406fd2029f23 7198 #define RCM_SSRS1_SSACKERR_SHIFT 5
mbed_official 324:406fd2029f23 7199
mbed_official 324:406fd2029f23 7200 /*!
mbed_official 324:406fd2029f23 7201 * @}
mbed_official 324:406fd2029f23 7202 */ /* end of group RCM_Register_Masks */
mbed_official 324:406fd2029f23 7203
mbed_official 324:406fd2029f23 7204
mbed_official 324:406fd2029f23 7205 /* RCM - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 7206 /** Peripheral RCM base address */
mbed_official 324:406fd2029f23 7207 #define RCM_BASE (0x4007F000u)
mbed_official 324:406fd2029f23 7208 /** Peripheral RCM base pointer */
mbed_official 324:406fd2029f23 7209 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 324:406fd2029f23 7210 #define RCM_BASE_PTR (RCM)
mbed_official 324:406fd2029f23 7211 /** Array initializer of RCM peripheral base addresses */
mbed_official 324:406fd2029f23 7212 #define RCM_BASE_ADDRS { RCM_BASE }
mbed_official 324:406fd2029f23 7213 /** Array initializer of RCM peripheral base pointers */
mbed_official 324:406fd2029f23 7214 #define RCM_BASE_PTRS { RCM }
mbed_official 324:406fd2029f23 7215
mbed_official 324:406fd2029f23 7216 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7217 -- RCM - Register accessor macros
mbed_official 324:406fd2029f23 7218 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7219
mbed_official 324:406fd2029f23 7220 /*!
mbed_official 324:406fd2029f23 7221 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 324:406fd2029f23 7222 * @{
mbed_official 324:406fd2029f23 7223 */
mbed_official 324:406fd2029f23 7224
mbed_official 324:406fd2029f23 7225
mbed_official 324:406fd2029f23 7226 /* RCM - Register instance definitions */
mbed_official 324:406fd2029f23 7227 /* RCM */
mbed_official 324:406fd2029f23 7228 #define RCM_SRS0 RCM_SRS0_REG(RCM)
mbed_official 324:406fd2029f23 7229 #define RCM_SRS1 RCM_SRS1_REG(RCM)
mbed_official 324:406fd2029f23 7230 #define RCM_RPFC RCM_RPFC_REG(RCM)
mbed_official 324:406fd2029f23 7231 #define RCM_RPFW RCM_RPFW_REG(RCM)
mbed_official 324:406fd2029f23 7232 #define RCM_MR RCM_MR_REG(RCM)
mbed_official 324:406fd2029f23 7233 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
mbed_official 324:406fd2029f23 7234 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
mbed_official 324:406fd2029f23 7235
mbed_official 324:406fd2029f23 7236 /*!
mbed_official 324:406fd2029f23 7237 * @}
mbed_official 324:406fd2029f23 7238 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7239
mbed_official 324:406fd2029f23 7240
mbed_official 324:406fd2029f23 7241 /*!
mbed_official 324:406fd2029f23 7242 * @}
mbed_official 324:406fd2029f23 7243 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7244
mbed_official 324:406fd2029f23 7245
mbed_official 324:406fd2029f23 7246 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7247 -- RFSYS Peripheral Access Layer
mbed_official 324:406fd2029f23 7248 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7249
mbed_official 324:406fd2029f23 7250 /*!
mbed_official 324:406fd2029f23 7251 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
mbed_official 324:406fd2029f23 7252 * @{
mbed_official 324:406fd2029f23 7253 */
mbed_official 324:406fd2029f23 7254
mbed_official 324:406fd2029f23 7255 /** RFSYS - Register Layout Typedef */
mbed_official 324:406fd2029f23 7256 typedef struct {
mbed_official 324:406fd2029f23 7257 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
mbed_official 324:406fd2029f23 7258 } RFSYS_Type, *RFSYS_MemMapPtr;
mbed_official 324:406fd2029f23 7259
mbed_official 324:406fd2029f23 7260 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7261 -- RFSYS - Register accessor macros
mbed_official 324:406fd2029f23 7262 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7263
mbed_official 324:406fd2029f23 7264 /*!
mbed_official 324:406fd2029f23 7265 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 324:406fd2029f23 7266 * @{
mbed_official 324:406fd2029f23 7267 */
mbed_official 324:406fd2029f23 7268
mbed_official 324:406fd2029f23 7269
mbed_official 324:406fd2029f23 7270 /* RFSYS - Register accessors */
mbed_official 324:406fd2029f23 7271 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
mbed_official 324:406fd2029f23 7272
mbed_official 324:406fd2029f23 7273 /*!
mbed_official 324:406fd2029f23 7274 * @}
mbed_official 324:406fd2029f23 7275 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7276
mbed_official 324:406fd2029f23 7277
mbed_official 324:406fd2029f23 7278 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7279 -- RFSYS Register Masks
mbed_official 324:406fd2029f23 7280 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7281
mbed_official 324:406fd2029f23 7282 /*!
mbed_official 324:406fd2029f23 7283 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
mbed_official 324:406fd2029f23 7284 * @{
mbed_official 324:406fd2029f23 7285 */
mbed_official 324:406fd2029f23 7286
mbed_official 324:406fd2029f23 7287 /* REG Bit Fields */
mbed_official 324:406fd2029f23 7288 #define RFSYS_REG_LL_MASK 0xFFu
mbed_official 324:406fd2029f23 7289 #define RFSYS_REG_LL_SHIFT 0
mbed_official 324:406fd2029f23 7290 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
mbed_official 324:406fd2029f23 7291 #define RFSYS_REG_LH_MASK 0xFF00u
mbed_official 324:406fd2029f23 7292 #define RFSYS_REG_LH_SHIFT 8
mbed_official 324:406fd2029f23 7293 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
mbed_official 324:406fd2029f23 7294 #define RFSYS_REG_HL_MASK 0xFF0000u
mbed_official 324:406fd2029f23 7295 #define RFSYS_REG_HL_SHIFT 16
mbed_official 324:406fd2029f23 7296 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
mbed_official 324:406fd2029f23 7297 #define RFSYS_REG_HH_MASK 0xFF000000u
mbed_official 324:406fd2029f23 7298 #define RFSYS_REG_HH_SHIFT 24
mbed_official 324:406fd2029f23 7299 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
mbed_official 324:406fd2029f23 7300
mbed_official 324:406fd2029f23 7301 /*!
mbed_official 324:406fd2029f23 7302 * @}
mbed_official 324:406fd2029f23 7303 */ /* end of group RFSYS_Register_Masks */
mbed_official 324:406fd2029f23 7304
mbed_official 324:406fd2029f23 7305
mbed_official 324:406fd2029f23 7306 /* RFSYS - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 7307 /** Peripheral RFSYS base address */
mbed_official 324:406fd2029f23 7308 #define RFSYS_BASE (0x40041000u)
mbed_official 324:406fd2029f23 7309 /** Peripheral RFSYS base pointer */
mbed_official 324:406fd2029f23 7310 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
mbed_official 324:406fd2029f23 7311 #define RFSYS_BASE_PTR (RFSYS)
mbed_official 324:406fd2029f23 7312 /** Array initializer of RFSYS peripheral base addresses */
mbed_official 324:406fd2029f23 7313 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
mbed_official 324:406fd2029f23 7314 /** Array initializer of RFSYS peripheral base pointers */
mbed_official 324:406fd2029f23 7315 #define RFSYS_BASE_PTRS { RFSYS }
mbed_official 324:406fd2029f23 7316
mbed_official 324:406fd2029f23 7317 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7318 -- RFSYS - Register accessor macros
mbed_official 324:406fd2029f23 7319 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7320
mbed_official 324:406fd2029f23 7321 /*!
mbed_official 324:406fd2029f23 7322 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 324:406fd2029f23 7323 * @{
mbed_official 324:406fd2029f23 7324 */
mbed_official 324:406fd2029f23 7325
mbed_official 324:406fd2029f23 7326
mbed_official 324:406fd2029f23 7327 /* RFSYS - Register instance definitions */
mbed_official 324:406fd2029f23 7328 /* RFSYS */
mbed_official 324:406fd2029f23 7329 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
mbed_official 324:406fd2029f23 7330 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
mbed_official 324:406fd2029f23 7331 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
mbed_official 324:406fd2029f23 7332 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
mbed_official 324:406fd2029f23 7333 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
mbed_official 324:406fd2029f23 7334 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
mbed_official 324:406fd2029f23 7335 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
mbed_official 324:406fd2029f23 7336 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
mbed_official 324:406fd2029f23 7337
mbed_official 324:406fd2029f23 7338 /* RFSYS - Register array accessors */
mbed_official 324:406fd2029f23 7339 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
mbed_official 324:406fd2029f23 7340
mbed_official 324:406fd2029f23 7341 /*!
mbed_official 324:406fd2029f23 7342 * @}
mbed_official 324:406fd2029f23 7343 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7344
mbed_official 324:406fd2029f23 7345
mbed_official 324:406fd2029f23 7346 /*!
mbed_official 324:406fd2029f23 7347 * @}
mbed_official 324:406fd2029f23 7348 */ /* end of group RFSYS_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7349
mbed_official 324:406fd2029f23 7350
mbed_official 324:406fd2029f23 7351 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7352 -- RFVBAT Peripheral Access Layer
mbed_official 324:406fd2029f23 7353 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7354
mbed_official 324:406fd2029f23 7355 /*!
mbed_official 324:406fd2029f23 7356 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
mbed_official 324:406fd2029f23 7357 * @{
mbed_official 324:406fd2029f23 7358 */
mbed_official 324:406fd2029f23 7359
mbed_official 324:406fd2029f23 7360 /** RFVBAT - Register Layout Typedef */
mbed_official 324:406fd2029f23 7361 typedef struct {
mbed_official 324:406fd2029f23 7362 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
mbed_official 324:406fd2029f23 7363 } RFVBAT_Type, *RFVBAT_MemMapPtr;
mbed_official 324:406fd2029f23 7364
mbed_official 324:406fd2029f23 7365 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7366 -- RFVBAT - Register accessor macros
mbed_official 324:406fd2029f23 7367 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7368
mbed_official 324:406fd2029f23 7369 /*!
mbed_official 324:406fd2029f23 7370 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
mbed_official 324:406fd2029f23 7371 * @{
mbed_official 324:406fd2029f23 7372 */
mbed_official 324:406fd2029f23 7373
mbed_official 324:406fd2029f23 7374
mbed_official 324:406fd2029f23 7375 /* RFVBAT - Register accessors */
mbed_official 324:406fd2029f23 7376 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
mbed_official 324:406fd2029f23 7377
mbed_official 324:406fd2029f23 7378 /*!
mbed_official 324:406fd2029f23 7379 * @}
mbed_official 324:406fd2029f23 7380 */ /* end of group RFVBAT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7381
mbed_official 324:406fd2029f23 7382
mbed_official 324:406fd2029f23 7383 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7384 -- RFVBAT Register Masks
mbed_official 324:406fd2029f23 7385 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7386
mbed_official 324:406fd2029f23 7387 /*!
mbed_official 324:406fd2029f23 7388 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
mbed_official 324:406fd2029f23 7389 * @{
mbed_official 324:406fd2029f23 7390 */
mbed_official 324:406fd2029f23 7391
mbed_official 324:406fd2029f23 7392 /* REG Bit Fields */
mbed_official 324:406fd2029f23 7393 #define RFVBAT_REG_LL_MASK 0xFFu
mbed_official 324:406fd2029f23 7394 #define RFVBAT_REG_LL_SHIFT 0
mbed_official 324:406fd2029f23 7395 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
mbed_official 324:406fd2029f23 7396 #define RFVBAT_REG_LH_MASK 0xFF00u
mbed_official 324:406fd2029f23 7397 #define RFVBAT_REG_LH_SHIFT 8
mbed_official 324:406fd2029f23 7398 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
mbed_official 324:406fd2029f23 7399 #define RFVBAT_REG_HL_MASK 0xFF0000u
mbed_official 324:406fd2029f23 7400 #define RFVBAT_REG_HL_SHIFT 16
mbed_official 324:406fd2029f23 7401 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
mbed_official 324:406fd2029f23 7402 #define RFVBAT_REG_HH_MASK 0xFF000000u
mbed_official 324:406fd2029f23 7403 #define RFVBAT_REG_HH_SHIFT 24
mbed_official 324:406fd2029f23 7404 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
mbed_official 324:406fd2029f23 7405
mbed_official 324:406fd2029f23 7406 /*!
mbed_official 324:406fd2029f23 7407 * @}
mbed_official 324:406fd2029f23 7408 */ /* end of group RFVBAT_Register_Masks */
mbed_official 324:406fd2029f23 7409
mbed_official 324:406fd2029f23 7410
mbed_official 324:406fd2029f23 7411 /* RFVBAT - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 7412 /** Peripheral RFVBAT base address */
mbed_official 324:406fd2029f23 7413 #define RFVBAT_BASE (0x4003E000u)
mbed_official 324:406fd2029f23 7414 /** Peripheral RFVBAT base pointer */
mbed_official 324:406fd2029f23 7415 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
mbed_official 324:406fd2029f23 7416 #define RFVBAT_BASE_PTR (RFVBAT)
mbed_official 324:406fd2029f23 7417 /** Array initializer of RFVBAT peripheral base addresses */
mbed_official 324:406fd2029f23 7418 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
mbed_official 324:406fd2029f23 7419 /** Array initializer of RFVBAT peripheral base pointers */
mbed_official 324:406fd2029f23 7420 #define RFVBAT_BASE_PTRS { RFVBAT }
mbed_official 324:406fd2029f23 7421
mbed_official 324:406fd2029f23 7422 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7423 -- RFVBAT - Register accessor macros
mbed_official 324:406fd2029f23 7424 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7425
mbed_official 324:406fd2029f23 7426 /*!
mbed_official 324:406fd2029f23 7427 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
mbed_official 324:406fd2029f23 7428 * @{
mbed_official 324:406fd2029f23 7429 */
mbed_official 324:406fd2029f23 7430
mbed_official 324:406fd2029f23 7431
mbed_official 324:406fd2029f23 7432 /* RFVBAT - Register instance definitions */
mbed_official 324:406fd2029f23 7433 /* RFVBAT */
mbed_official 324:406fd2029f23 7434 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
mbed_official 324:406fd2029f23 7435 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
mbed_official 324:406fd2029f23 7436 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
mbed_official 324:406fd2029f23 7437 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
mbed_official 324:406fd2029f23 7438 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
mbed_official 324:406fd2029f23 7439 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
mbed_official 324:406fd2029f23 7440 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
mbed_official 324:406fd2029f23 7441 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
mbed_official 324:406fd2029f23 7442
mbed_official 324:406fd2029f23 7443 /* RFVBAT - Register array accessors */
mbed_official 324:406fd2029f23 7444 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
mbed_official 324:406fd2029f23 7445
mbed_official 324:406fd2029f23 7446 /*!
mbed_official 324:406fd2029f23 7447 * @}
mbed_official 324:406fd2029f23 7448 */ /* end of group RFVBAT_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7449
mbed_official 324:406fd2029f23 7450
mbed_official 324:406fd2029f23 7451 /*!
mbed_official 324:406fd2029f23 7452 * @}
mbed_official 324:406fd2029f23 7453 */ /* end of group RFVBAT_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7454
mbed_official 324:406fd2029f23 7455
mbed_official 324:406fd2029f23 7456 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7457 -- RNG Peripheral Access Layer
mbed_official 324:406fd2029f23 7458 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7459
mbed_official 324:406fd2029f23 7460 /*!
mbed_official 324:406fd2029f23 7461 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
mbed_official 324:406fd2029f23 7462 * @{
mbed_official 324:406fd2029f23 7463 */
mbed_official 324:406fd2029f23 7464
mbed_official 324:406fd2029f23 7465 /** RNG - Register Layout Typedef */
mbed_official 324:406fd2029f23 7466 typedef struct {
mbed_official 324:406fd2029f23 7467 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
mbed_official 324:406fd2029f23 7468 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
mbed_official 324:406fd2029f23 7469 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
mbed_official 324:406fd2029f23 7470 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
mbed_official 324:406fd2029f23 7471 } RNG_Type, *RNG_MemMapPtr;
mbed_official 324:406fd2029f23 7472
mbed_official 324:406fd2029f23 7473 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7474 -- RNG - Register accessor macros
mbed_official 324:406fd2029f23 7475 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7476
mbed_official 324:406fd2029f23 7477 /*!
mbed_official 324:406fd2029f23 7478 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
mbed_official 324:406fd2029f23 7479 * @{
mbed_official 324:406fd2029f23 7480 */
mbed_official 324:406fd2029f23 7481
mbed_official 324:406fd2029f23 7482
mbed_official 324:406fd2029f23 7483 /* RNG - Register accessors */
mbed_official 324:406fd2029f23 7484 #define RNG_CR_REG(base) ((base)->CR)
mbed_official 324:406fd2029f23 7485 #define RNG_SR_REG(base) ((base)->SR)
mbed_official 324:406fd2029f23 7486 #define RNG_ER_REG(base) ((base)->ER)
mbed_official 324:406fd2029f23 7487 #define RNG_OR_REG(base) ((base)->OR)
mbed_official 324:406fd2029f23 7488
mbed_official 324:406fd2029f23 7489 /*!
mbed_official 324:406fd2029f23 7490 * @}
mbed_official 324:406fd2029f23 7491 */ /* end of group RNG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7492
mbed_official 324:406fd2029f23 7493
mbed_official 324:406fd2029f23 7494 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7495 -- RNG Register Masks
mbed_official 324:406fd2029f23 7496 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7497
mbed_official 324:406fd2029f23 7498 /*!
mbed_official 324:406fd2029f23 7499 * @addtogroup RNG_Register_Masks RNG Register Masks
mbed_official 324:406fd2029f23 7500 * @{
mbed_official 324:406fd2029f23 7501 */
mbed_official 324:406fd2029f23 7502
mbed_official 324:406fd2029f23 7503 /* CR Bit Fields */
mbed_official 324:406fd2029f23 7504 #define RNG_CR_GO_MASK 0x1u
mbed_official 324:406fd2029f23 7505 #define RNG_CR_GO_SHIFT 0
mbed_official 324:406fd2029f23 7506 #define RNG_CR_HA_MASK 0x2u
mbed_official 324:406fd2029f23 7507 #define RNG_CR_HA_SHIFT 1
mbed_official 324:406fd2029f23 7508 #define RNG_CR_INTM_MASK 0x4u
mbed_official 324:406fd2029f23 7509 #define RNG_CR_INTM_SHIFT 2
mbed_official 324:406fd2029f23 7510 #define RNG_CR_CLRI_MASK 0x8u
mbed_official 324:406fd2029f23 7511 #define RNG_CR_CLRI_SHIFT 3
mbed_official 324:406fd2029f23 7512 #define RNG_CR_SLP_MASK 0x10u
mbed_official 324:406fd2029f23 7513 #define RNG_CR_SLP_SHIFT 4
mbed_official 324:406fd2029f23 7514 /* SR Bit Fields */
mbed_official 324:406fd2029f23 7515 #define RNG_SR_SECV_MASK 0x1u
mbed_official 324:406fd2029f23 7516 #define RNG_SR_SECV_SHIFT 0
mbed_official 324:406fd2029f23 7517 #define RNG_SR_LRS_MASK 0x2u
mbed_official 324:406fd2029f23 7518 #define RNG_SR_LRS_SHIFT 1
mbed_official 324:406fd2029f23 7519 #define RNG_SR_ORU_MASK 0x4u
mbed_official 324:406fd2029f23 7520 #define RNG_SR_ORU_SHIFT 2
mbed_official 324:406fd2029f23 7521 #define RNG_SR_ERRI_MASK 0x8u
mbed_official 324:406fd2029f23 7522 #define RNG_SR_ERRI_SHIFT 3
mbed_official 324:406fd2029f23 7523 #define RNG_SR_SLP_MASK 0x10u
mbed_official 324:406fd2029f23 7524 #define RNG_SR_SLP_SHIFT 4
mbed_official 324:406fd2029f23 7525 #define RNG_SR_OREG_LVL_MASK 0xFF00u
mbed_official 324:406fd2029f23 7526 #define RNG_SR_OREG_LVL_SHIFT 8
mbed_official 324:406fd2029f23 7527 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
mbed_official 324:406fd2029f23 7528 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
mbed_official 324:406fd2029f23 7529 #define RNG_SR_OREG_SIZE_SHIFT 16
mbed_official 324:406fd2029f23 7530 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
mbed_official 324:406fd2029f23 7531 /* ER Bit Fields */
mbed_official 324:406fd2029f23 7532 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 7533 #define RNG_ER_EXT_ENT_SHIFT 0
mbed_official 324:406fd2029f23 7534 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
mbed_official 324:406fd2029f23 7535 /* OR Bit Fields */
mbed_official 324:406fd2029f23 7536 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 7537 #define RNG_OR_RANDOUT_SHIFT 0
mbed_official 324:406fd2029f23 7538 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
mbed_official 324:406fd2029f23 7539
mbed_official 324:406fd2029f23 7540 /*!
mbed_official 324:406fd2029f23 7541 * @}
mbed_official 324:406fd2029f23 7542 */ /* end of group RNG_Register_Masks */
mbed_official 324:406fd2029f23 7543
mbed_official 324:406fd2029f23 7544
mbed_official 324:406fd2029f23 7545 /* RNG - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 7546 /** Peripheral RNG base address */
mbed_official 324:406fd2029f23 7547 #define RNG_BASE (0x40029000u)
mbed_official 324:406fd2029f23 7548 /** Peripheral RNG base pointer */
mbed_official 324:406fd2029f23 7549 #define RNG ((RNG_Type *)RNG_BASE)
mbed_official 324:406fd2029f23 7550 #define RNG_BASE_PTR (RNG)
mbed_official 324:406fd2029f23 7551 /** Array initializer of RNG peripheral base addresses */
mbed_official 324:406fd2029f23 7552 #define RNG_BASE_ADDRS { RNG_BASE }
mbed_official 324:406fd2029f23 7553 /** Array initializer of RNG peripheral base pointers */
mbed_official 324:406fd2029f23 7554 #define RNG_BASE_PTRS { RNG }
mbed_official 324:406fd2029f23 7555 /** Interrupt vectors for the RNG peripheral type */
mbed_official 324:406fd2029f23 7556 #define RNG_IRQS { RNG_IRQn }
mbed_official 324:406fd2029f23 7557
mbed_official 324:406fd2029f23 7558 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7559 -- RNG - Register accessor macros
mbed_official 324:406fd2029f23 7560 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7561
mbed_official 324:406fd2029f23 7562 /*!
mbed_official 324:406fd2029f23 7563 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
mbed_official 324:406fd2029f23 7564 * @{
mbed_official 324:406fd2029f23 7565 */
mbed_official 324:406fd2029f23 7566
mbed_official 324:406fd2029f23 7567
mbed_official 324:406fd2029f23 7568 /* RNG - Register instance definitions */
mbed_official 324:406fd2029f23 7569 /* RNG */
mbed_official 324:406fd2029f23 7570 #define RNG_CR RNG_CR_REG(RNG)
mbed_official 324:406fd2029f23 7571 #define RNG_SR RNG_SR_REG(RNG)
mbed_official 324:406fd2029f23 7572 #define RNG_ER RNG_ER_REG(RNG)
mbed_official 324:406fd2029f23 7573 #define RNG_OR RNG_OR_REG(RNG)
mbed_official 324:406fd2029f23 7574
mbed_official 324:406fd2029f23 7575 /*!
mbed_official 324:406fd2029f23 7576 * @}
mbed_official 324:406fd2029f23 7577 */ /* end of group RNG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7578
mbed_official 324:406fd2029f23 7579
mbed_official 324:406fd2029f23 7580 /*!
mbed_official 324:406fd2029f23 7581 * @}
mbed_official 324:406fd2029f23 7582 */ /* end of group RNG_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7583
mbed_official 324:406fd2029f23 7584
mbed_official 324:406fd2029f23 7585 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7586 -- RTC Peripheral Access Layer
mbed_official 324:406fd2029f23 7587 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7588
mbed_official 324:406fd2029f23 7589 /*!
mbed_official 324:406fd2029f23 7590 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 324:406fd2029f23 7591 * @{
mbed_official 324:406fd2029f23 7592 */
mbed_official 324:406fd2029f23 7593
mbed_official 324:406fd2029f23 7594 /** RTC - Register Layout Typedef */
mbed_official 324:406fd2029f23 7595 typedef struct {
mbed_official 324:406fd2029f23 7596 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 324:406fd2029f23 7597 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 324:406fd2029f23 7598 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 324:406fd2029f23 7599 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 324:406fd2029f23 7600 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 324:406fd2029f23 7601 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 324:406fd2029f23 7602 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 324:406fd2029f23 7603 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 324:406fd2029f23 7604 uint8_t RESERVED_0[2016];
mbed_official 324:406fd2029f23 7605 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
mbed_official 324:406fd2029f23 7606 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
mbed_official 324:406fd2029f23 7607 } RTC_Type, *RTC_MemMapPtr;
mbed_official 324:406fd2029f23 7608
mbed_official 324:406fd2029f23 7609 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7610 -- RTC - Register accessor macros
mbed_official 324:406fd2029f23 7611 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7612
mbed_official 324:406fd2029f23 7613 /*!
mbed_official 324:406fd2029f23 7614 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 324:406fd2029f23 7615 * @{
mbed_official 324:406fd2029f23 7616 */
mbed_official 324:406fd2029f23 7617
mbed_official 324:406fd2029f23 7618
mbed_official 324:406fd2029f23 7619 /* RTC - Register accessors */
mbed_official 324:406fd2029f23 7620 #define RTC_TSR_REG(base) ((base)->TSR)
mbed_official 324:406fd2029f23 7621 #define RTC_TPR_REG(base) ((base)->TPR)
mbed_official 324:406fd2029f23 7622 #define RTC_TAR_REG(base) ((base)->TAR)
mbed_official 324:406fd2029f23 7623 #define RTC_TCR_REG(base) ((base)->TCR)
mbed_official 324:406fd2029f23 7624 #define RTC_CR_REG(base) ((base)->CR)
mbed_official 324:406fd2029f23 7625 #define RTC_SR_REG(base) ((base)->SR)
mbed_official 324:406fd2029f23 7626 #define RTC_LR_REG(base) ((base)->LR)
mbed_official 324:406fd2029f23 7627 #define RTC_IER_REG(base) ((base)->IER)
mbed_official 324:406fd2029f23 7628 #define RTC_WAR_REG(base) ((base)->WAR)
mbed_official 324:406fd2029f23 7629 #define RTC_RAR_REG(base) ((base)->RAR)
mbed_official 324:406fd2029f23 7630
mbed_official 324:406fd2029f23 7631 /*!
mbed_official 324:406fd2029f23 7632 * @}
mbed_official 324:406fd2029f23 7633 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7634
mbed_official 324:406fd2029f23 7635
mbed_official 324:406fd2029f23 7636 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7637 -- RTC Register Masks
mbed_official 324:406fd2029f23 7638 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7639
mbed_official 324:406fd2029f23 7640 /*!
mbed_official 324:406fd2029f23 7641 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 324:406fd2029f23 7642 * @{
mbed_official 324:406fd2029f23 7643 */
mbed_official 324:406fd2029f23 7644
mbed_official 324:406fd2029f23 7645 /* TSR Bit Fields */
mbed_official 324:406fd2029f23 7646 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 7647 #define RTC_TSR_TSR_SHIFT 0
mbed_official 324:406fd2029f23 7648 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 324:406fd2029f23 7649 /* TPR Bit Fields */
mbed_official 324:406fd2029f23 7650 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 324:406fd2029f23 7651 #define RTC_TPR_TPR_SHIFT 0
mbed_official 324:406fd2029f23 7652 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 324:406fd2029f23 7653 /* TAR Bit Fields */
mbed_official 324:406fd2029f23 7654 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 7655 #define RTC_TAR_TAR_SHIFT 0
mbed_official 324:406fd2029f23 7656 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 324:406fd2029f23 7657 /* TCR Bit Fields */
mbed_official 324:406fd2029f23 7658 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 324:406fd2029f23 7659 #define RTC_TCR_TCR_SHIFT 0
mbed_official 324:406fd2029f23 7660 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 324:406fd2029f23 7661 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 324:406fd2029f23 7662 #define RTC_TCR_CIR_SHIFT 8
mbed_official 324:406fd2029f23 7663 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 324:406fd2029f23 7664 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 324:406fd2029f23 7665 #define RTC_TCR_TCV_SHIFT 16
mbed_official 324:406fd2029f23 7666 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 324:406fd2029f23 7667 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 324:406fd2029f23 7668 #define RTC_TCR_CIC_SHIFT 24
mbed_official 324:406fd2029f23 7669 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 324:406fd2029f23 7670 /* CR Bit Fields */
mbed_official 324:406fd2029f23 7671 #define RTC_CR_SWR_MASK 0x1u
mbed_official 324:406fd2029f23 7672 #define RTC_CR_SWR_SHIFT 0
mbed_official 324:406fd2029f23 7673 #define RTC_CR_WPE_MASK 0x2u
mbed_official 324:406fd2029f23 7674 #define RTC_CR_WPE_SHIFT 1
mbed_official 324:406fd2029f23 7675 #define RTC_CR_SUP_MASK 0x4u
mbed_official 324:406fd2029f23 7676 #define RTC_CR_SUP_SHIFT 2
mbed_official 324:406fd2029f23 7677 #define RTC_CR_UM_MASK 0x8u
mbed_official 324:406fd2029f23 7678 #define RTC_CR_UM_SHIFT 3
mbed_official 324:406fd2029f23 7679 #define RTC_CR_WPS_MASK 0x10u
mbed_official 324:406fd2029f23 7680 #define RTC_CR_WPS_SHIFT 4
mbed_official 324:406fd2029f23 7681 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 324:406fd2029f23 7682 #define RTC_CR_OSCE_SHIFT 8
mbed_official 324:406fd2029f23 7683 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 324:406fd2029f23 7684 #define RTC_CR_CLKO_SHIFT 9
mbed_official 324:406fd2029f23 7685 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 324:406fd2029f23 7686 #define RTC_CR_SC16P_SHIFT 10
mbed_official 324:406fd2029f23 7687 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 324:406fd2029f23 7688 #define RTC_CR_SC8P_SHIFT 11
mbed_official 324:406fd2029f23 7689 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 324:406fd2029f23 7690 #define RTC_CR_SC4P_SHIFT 12
mbed_official 324:406fd2029f23 7691 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 324:406fd2029f23 7692 #define RTC_CR_SC2P_SHIFT 13
mbed_official 324:406fd2029f23 7693 /* SR Bit Fields */
mbed_official 324:406fd2029f23 7694 #define RTC_SR_TIF_MASK 0x1u
mbed_official 324:406fd2029f23 7695 #define RTC_SR_TIF_SHIFT 0
mbed_official 324:406fd2029f23 7696 #define RTC_SR_TOF_MASK 0x2u
mbed_official 324:406fd2029f23 7697 #define RTC_SR_TOF_SHIFT 1
mbed_official 324:406fd2029f23 7698 #define RTC_SR_TAF_MASK 0x4u
mbed_official 324:406fd2029f23 7699 #define RTC_SR_TAF_SHIFT 2
mbed_official 324:406fd2029f23 7700 #define RTC_SR_TCE_MASK 0x10u
mbed_official 324:406fd2029f23 7701 #define RTC_SR_TCE_SHIFT 4
mbed_official 324:406fd2029f23 7702 /* LR Bit Fields */
mbed_official 324:406fd2029f23 7703 #define RTC_LR_TCL_MASK 0x8u
mbed_official 324:406fd2029f23 7704 #define RTC_LR_TCL_SHIFT 3
mbed_official 324:406fd2029f23 7705 #define RTC_LR_CRL_MASK 0x10u
mbed_official 324:406fd2029f23 7706 #define RTC_LR_CRL_SHIFT 4
mbed_official 324:406fd2029f23 7707 #define RTC_LR_SRL_MASK 0x20u
mbed_official 324:406fd2029f23 7708 #define RTC_LR_SRL_SHIFT 5
mbed_official 324:406fd2029f23 7709 #define RTC_LR_LRL_MASK 0x40u
mbed_official 324:406fd2029f23 7710 #define RTC_LR_LRL_SHIFT 6
mbed_official 324:406fd2029f23 7711 /* IER Bit Fields */
mbed_official 324:406fd2029f23 7712 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 324:406fd2029f23 7713 #define RTC_IER_TIIE_SHIFT 0
mbed_official 324:406fd2029f23 7714 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 324:406fd2029f23 7715 #define RTC_IER_TOIE_SHIFT 1
mbed_official 324:406fd2029f23 7716 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 324:406fd2029f23 7717 #define RTC_IER_TAIE_SHIFT 2
mbed_official 324:406fd2029f23 7718 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 324:406fd2029f23 7719 #define RTC_IER_TSIE_SHIFT 4
mbed_official 324:406fd2029f23 7720 #define RTC_IER_WPON_MASK 0x80u
mbed_official 324:406fd2029f23 7721 #define RTC_IER_WPON_SHIFT 7
mbed_official 324:406fd2029f23 7722 /* WAR Bit Fields */
mbed_official 324:406fd2029f23 7723 #define RTC_WAR_TSRW_MASK 0x1u
mbed_official 324:406fd2029f23 7724 #define RTC_WAR_TSRW_SHIFT 0
mbed_official 324:406fd2029f23 7725 #define RTC_WAR_TPRW_MASK 0x2u
mbed_official 324:406fd2029f23 7726 #define RTC_WAR_TPRW_SHIFT 1
mbed_official 324:406fd2029f23 7727 #define RTC_WAR_TARW_MASK 0x4u
mbed_official 324:406fd2029f23 7728 #define RTC_WAR_TARW_SHIFT 2
mbed_official 324:406fd2029f23 7729 #define RTC_WAR_TCRW_MASK 0x8u
mbed_official 324:406fd2029f23 7730 #define RTC_WAR_TCRW_SHIFT 3
mbed_official 324:406fd2029f23 7731 #define RTC_WAR_CRW_MASK 0x10u
mbed_official 324:406fd2029f23 7732 #define RTC_WAR_CRW_SHIFT 4
mbed_official 324:406fd2029f23 7733 #define RTC_WAR_SRW_MASK 0x20u
mbed_official 324:406fd2029f23 7734 #define RTC_WAR_SRW_SHIFT 5
mbed_official 324:406fd2029f23 7735 #define RTC_WAR_LRW_MASK 0x40u
mbed_official 324:406fd2029f23 7736 #define RTC_WAR_LRW_SHIFT 6
mbed_official 324:406fd2029f23 7737 #define RTC_WAR_IERW_MASK 0x80u
mbed_official 324:406fd2029f23 7738 #define RTC_WAR_IERW_SHIFT 7
mbed_official 324:406fd2029f23 7739 /* RAR Bit Fields */
mbed_official 324:406fd2029f23 7740 #define RTC_RAR_TSRR_MASK 0x1u
mbed_official 324:406fd2029f23 7741 #define RTC_RAR_TSRR_SHIFT 0
mbed_official 324:406fd2029f23 7742 #define RTC_RAR_TPRR_MASK 0x2u
mbed_official 324:406fd2029f23 7743 #define RTC_RAR_TPRR_SHIFT 1
mbed_official 324:406fd2029f23 7744 #define RTC_RAR_TARR_MASK 0x4u
mbed_official 324:406fd2029f23 7745 #define RTC_RAR_TARR_SHIFT 2
mbed_official 324:406fd2029f23 7746 #define RTC_RAR_TCRR_MASK 0x8u
mbed_official 324:406fd2029f23 7747 #define RTC_RAR_TCRR_SHIFT 3
mbed_official 324:406fd2029f23 7748 #define RTC_RAR_CRR_MASK 0x10u
mbed_official 324:406fd2029f23 7749 #define RTC_RAR_CRR_SHIFT 4
mbed_official 324:406fd2029f23 7750 #define RTC_RAR_SRR_MASK 0x20u
mbed_official 324:406fd2029f23 7751 #define RTC_RAR_SRR_SHIFT 5
mbed_official 324:406fd2029f23 7752 #define RTC_RAR_LRR_MASK 0x40u
mbed_official 324:406fd2029f23 7753 #define RTC_RAR_LRR_SHIFT 6
mbed_official 324:406fd2029f23 7754 #define RTC_RAR_IERR_MASK 0x80u
mbed_official 324:406fd2029f23 7755 #define RTC_RAR_IERR_SHIFT 7
mbed_official 324:406fd2029f23 7756
mbed_official 324:406fd2029f23 7757 /*!
mbed_official 324:406fd2029f23 7758 * @}
mbed_official 324:406fd2029f23 7759 */ /* end of group RTC_Register_Masks */
mbed_official 324:406fd2029f23 7760
mbed_official 324:406fd2029f23 7761
mbed_official 324:406fd2029f23 7762 /* RTC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 7763 /** Peripheral RTC base address */
mbed_official 324:406fd2029f23 7764 #define RTC_BASE (0x4003D000u)
mbed_official 324:406fd2029f23 7765 /** Peripheral RTC base pointer */
mbed_official 324:406fd2029f23 7766 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 324:406fd2029f23 7767 #define RTC_BASE_PTR (RTC)
mbed_official 324:406fd2029f23 7768 /** Array initializer of RTC peripheral base addresses */
mbed_official 324:406fd2029f23 7769 #define RTC_BASE_ADDRS { RTC_BASE }
mbed_official 324:406fd2029f23 7770 /** Array initializer of RTC peripheral base pointers */
mbed_official 324:406fd2029f23 7771 #define RTC_BASE_PTRS { RTC }
mbed_official 324:406fd2029f23 7772 /** Interrupt vectors for the RTC peripheral type */
mbed_official 324:406fd2029f23 7773 #define RTC_IRQS { RTC_IRQn }
mbed_official 324:406fd2029f23 7774 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
mbed_official 324:406fd2029f23 7775
mbed_official 324:406fd2029f23 7776 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7777 -- RTC - Register accessor macros
mbed_official 324:406fd2029f23 7778 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7779
mbed_official 324:406fd2029f23 7780 /*!
mbed_official 324:406fd2029f23 7781 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 324:406fd2029f23 7782 * @{
mbed_official 324:406fd2029f23 7783 */
mbed_official 324:406fd2029f23 7784
mbed_official 324:406fd2029f23 7785
mbed_official 324:406fd2029f23 7786 /* RTC - Register instance definitions */
mbed_official 324:406fd2029f23 7787 /* RTC */
mbed_official 324:406fd2029f23 7788 #define RTC_TSR RTC_TSR_REG(RTC)
mbed_official 324:406fd2029f23 7789 #define RTC_TPR RTC_TPR_REG(RTC)
mbed_official 324:406fd2029f23 7790 #define RTC_TAR RTC_TAR_REG(RTC)
mbed_official 324:406fd2029f23 7791 #define RTC_TCR RTC_TCR_REG(RTC)
mbed_official 324:406fd2029f23 7792 #define RTC_CR RTC_CR_REG(RTC)
mbed_official 324:406fd2029f23 7793 #define RTC_SR RTC_SR_REG(RTC)
mbed_official 324:406fd2029f23 7794 #define RTC_LR RTC_LR_REG(RTC)
mbed_official 324:406fd2029f23 7795 #define RTC_IER RTC_IER_REG(RTC)
mbed_official 324:406fd2029f23 7796 #define RTC_WAR RTC_WAR_REG(RTC)
mbed_official 324:406fd2029f23 7797 #define RTC_RAR RTC_RAR_REG(RTC)
mbed_official 324:406fd2029f23 7798
mbed_official 324:406fd2029f23 7799 /*!
mbed_official 324:406fd2029f23 7800 * @}
mbed_official 324:406fd2029f23 7801 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7802
mbed_official 324:406fd2029f23 7803
mbed_official 324:406fd2029f23 7804 /*!
mbed_official 324:406fd2029f23 7805 * @}
mbed_official 324:406fd2029f23 7806 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 7807
mbed_official 324:406fd2029f23 7808
mbed_official 324:406fd2029f23 7809 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7810 -- SIM Peripheral Access Layer
mbed_official 324:406fd2029f23 7811 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7812
mbed_official 324:406fd2029f23 7813 /*!
mbed_official 324:406fd2029f23 7814 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 324:406fd2029f23 7815 * @{
mbed_official 324:406fd2029f23 7816 */
mbed_official 324:406fd2029f23 7817
mbed_official 324:406fd2029f23 7818 /** SIM - Register Layout Typedef */
mbed_official 324:406fd2029f23 7819 typedef struct {
mbed_official 324:406fd2029f23 7820 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 324:406fd2029f23 7821 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 324:406fd2029f23 7822 uint8_t RESERVED_0[4092];
mbed_official 324:406fd2029f23 7823 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 324:406fd2029f23 7824 uint8_t RESERVED_1[4];
mbed_official 324:406fd2029f23 7825 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 324:406fd2029f23 7826 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 324:406fd2029f23 7827 uint8_t RESERVED_2[4];
mbed_official 324:406fd2029f23 7828 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 324:406fd2029f23 7829 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
mbed_official 324:406fd2029f23 7830 uint8_t RESERVED_3[4];
mbed_official 324:406fd2029f23 7831 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 324:406fd2029f23 7832 uint8_t RESERVED_4[12];
mbed_official 324:406fd2029f23 7833 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 324:406fd2029f23 7834 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 324:406fd2029f23 7835 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 324:406fd2029f23 7836 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 324:406fd2029f23 7837 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 324:406fd2029f23 7838 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
mbed_official 324:406fd2029f23 7839 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 324:406fd2029f23 7840 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 324:406fd2029f23 7841 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
mbed_official 324:406fd2029f23 7842 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 324:406fd2029f23 7843 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 324:406fd2029f23 7844 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 324:406fd2029f23 7845 } SIM_Type, *SIM_MemMapPtr;
mbed_official 324:406fd2029f23 7846
mbed_official 324:406fd2029f23 7847 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7848 -- SIM - Register accessor macros
mbed_official 324:406fd2029f23 7849 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7850
mbed_official 324:406fd2029f23 7851 /*!
mbed_official 324:406fd2029f23 7852 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 324:406fd2029f23 7853 * @{
mbed_official 324:406fd2029f23 7854 */
mbed_official 324:406fd2029f23 7855
mbed_official 324:406fd2029f23 7856
mbed_official 324:406fd2029f23 7857 /* SIM - Register accessors */
mbed_official 324:406fd2029f23 7858 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
mbed_official 324:406fd2029f23 7859 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
mbed_official 324:406fd2029f23 7860 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
mbed_official 324:406fd2029f23 7861 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
mbed_official 324:406fd2029f23 7862 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
mbed_official 324:406fd2029f23 7863 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
mbed_official 324:406fd2029f23 7864 #define SIM_SOPT8_REG(base) ((base)->SOPT8)
mbed_official 324:406fd2029f23 7865 #define SIM_SDID_REG(base) ((base)->SDID)
mbed_official 324:406fd2029f23 7866 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
mbed_official 324:406fd2029f23 7867 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
mbed_official 324:406fd2029f23 7868 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
mbed_official 324:406fd2029f23 7869 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
mbed_official 324:406fd2029f23 7870 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
mbed_official 324:406fd2029f23 7871 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
mbed_official 324:406fd2029f23 7872 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
mbed_official 324:406fd2029f23 7873 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
mbed_official 324:406fd2029f23 7874 #define SIM_UIDH_REG(base) ((base)->UIDH)
mbed_official 324:406fd2029f23 7875 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
mbed_official 324:406fd2029f23 7876 #define SIM_UIDML_REG(base) ((base)->UIDML)
mbed_official 324:406fd2029f23 7877 #define SIM_UIDL_REG(base) ((base)->UIDL)
mbed_official 324:406fd2029f23 7878
mbed_official 324:406fd2029f23 7879 /*!
mbed_official 324:406fd2029f23 7880 * @}
mbed_official 324:406fd2029f23 7881 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 7882
mbed_official 324:406fd2029f23 7883
mbed_official 324:406fd2029f23 7884 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 7885 -- SIM Register Masks
mbed_official 324:406fd2029f23 7886 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 7887
mbed_official 324:406fd2029f23 7888 /*!
mbed_official 324:406fd2029f23 7889 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 324:406fd2029f23 7890 * @{
mbed_official 324:406fd2029f23 7891 */
mbed_official 324:406fd2029f23 7892
mbed_official 324:406fd2029f23 7893 /* SOPT1 Bit Fields */
mbed_official 324:406fd2029f23 7894 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
mbed_official 324:406fd2029f23 7895 #define SIM_SOPT1_RAMSIZE_SHIFT 12
mbed_official 324:406fd2029f23 7896 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
mbed_official 324:406fd2029f23 7897 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
mbed_official 324:406fd2029f23 7898 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
mbed_official 324:406fd2029f23 7899 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
mbed_official 324:406fd2029f23 7900 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 324:406fd2029f23 7901 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 324:406fd2029f23 7902 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 324:406fd2029f23 7903 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 324:406fd2029f23 7904 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 324:406fd2029f23 7905 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 324:406fd2029f23 7906 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 324:406fd2029f23 7907 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 324:406fd2029f23 7908 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 324:406fd2029f23 7909 /* SOPT1CFG Bit Fields */
mbed_official 324:406fd2029f23 7910 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 324:406fd2029f23 7911 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 324:406fd2029f23 7912 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 324:406fd2029f23 7913 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 324:406fd2029f23 7914 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 324:406fd2029f23 7915 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 324:406fd2029f23 7916 /* SOPT2 Bit Fields */
mbed_official 324:406fd2029f23 7917 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 324:406fd2029f23 7918 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 324:406fd2029f23 7919 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 324:406fd2029f23 7920 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 324:406fd2029f23 7921 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 324:406fd2029f23 7922 #define SIM_SOPT2_FBSL_MASK 0x300u
mbed_official 324:406fd2029f23 7923 #define SIM_SOPT2_FBSL_SHIFT 8
mbed_official 324:406fd2029f23 7924 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
mbed_official 324:406fd2029f23 7925 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
mbed_official 324:406fd2029f23 7926 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
mbed_official 324:406fd2029f23 7927 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
mbed_official 324:406fd2029f23 7928 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
mbed_official 324:406fd2029f23 7929 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
mbed_official 324:406fd2029f23 7930 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 324:406fd2029f23 7931 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 324:406fd2029f23 7932 #define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
mbed_official 324:406fd2029f23 7933 #define SIM_SOPT2_LPUARTSRC_SHIFT 26
mbed_official 324:406fd2029f23 7934 #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
mbed_official 324:406fd2029f23 7935 /* SOPT4 Bit Fields */
mbed_official 324:406fd2029f23 7936 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
mbed_official 324:406fd2029f23 7937 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
mbed_official 324:406fd2029f23 7938 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
mbed_official 324:406fd2029f23 7939 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
mbed_official 324:406fd2029f23 7940 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
mbed_official 324:406fd2029f23 7941 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
mbed_official 324:406fd2029f23 7942 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
mbed_official 324:406fd2029f23 7943 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
mbed_official 324:406fd2029f23 7944 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
mbed_official 324:406fd2029f23 7945 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
mbed_official 324:406fd2029f23 7946 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
mbed_official 324:406fd2029f23 7947 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
mbed_official 324:406fd2029f23 7948 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
mbed_official 324:406fd2029f23 7949 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
mbed_official 324:406fd2029f23 7950 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
mbed_official 324:406fd2029f23 7951 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
mbed_official 324:406fd2029f23 7952 #define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
mbed_official 324:406fd2029f23 7953 #define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
mbed_official 324:406fd2029f23 7954 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
mbed_official 324:406fd2029f23 7955 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
mbed_official 324:406fd2029f23 7956 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
mbed_official 324:406fd2029f23 7957 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
mbed_official 324:406fd2029f23 7958 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
mbed_official 324:406fd2029f23 7959 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
mbed_official 324:406fd2029f23 7960 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
mbed_official 324:406fd2029f23 7961 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
mbed_official 324:406fd2029f23 7962 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
mbed_official 324:406fd2029f23 7963 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
mbed_official 324:406fd2029f23 7964 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
mbed_official 324:406fd2029f23 7965 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
mbed_official 324:406fd2029f23 7966 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
mbed_official 324:406fd2029f23 7967 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
mbed_official 324:406fd2029f23 7968 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
mbed_official 324:406fd2029f23 7969 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
mbed_official 324:406fd2029f23 7970 /* SOPT5 Bit Fields */
mbed_official 324:406fd2029f23 7971 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
mbed_official 324:406fd2029f23 7972 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 324:406fd2029f23 7973 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
mbed_official 324:406fd2029f23 7974 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
mbed_official 324:406fd2029f23 7975 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 324:406fd2029f23 7976 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
mbed_official 324:406fd2029f23 7977 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
mbed_official 324:406fd2029f23 7978 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
mbed_official 324:406fd2029f23 7979 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
mbed_official 324:406fd2029f23 7980 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
mbed_official 324:406fd2029f23 7981 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
mbed_official 324:406fd2029f23 7982 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
mbed_official 324:406fd2029f23 7983 #define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
mbed_official 324:406fd2029f23 7984 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
mbed_official 324:406fd2029f23 7985 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
mbed_official 324:406fd2029f23 7986 /* SOPT7 Bit Fields */
mbed_official 324:406fd2029f23 7987 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 324:406fd2029f23 7988 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 324:406fd2029f23 7989 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 324:406fd2029f23 7990 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 324:406fd2029f23 7991 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 324:406fd2029f23 7992 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 324:406fd2029f23 7993 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 324:406fd2029f23 7994 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
mbed_official 324:406fd2029f23 7995 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
mbed_official 324:406fd2029f23 7996 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
mbed_official 324:406fd2029f23 7997 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
mbed_official 324:406fd2029f23 7998 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
mbed_official 324:406fd2029f23 7999 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
mbed_official 324:406fd2029f23 8000 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
mbed_official 324:406fd2029f23 8001 /* SOPT8 Bit Fields */
mbed_official 324:406fd2029f23 8002 #define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
mbed_official 324:406fd2029f23 8003 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
mbed_official 324:406fd2029f23 8004 #define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
mbed_official 324:406fd2029f23 8005 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
mbed_official 324:406fd2029f23 8006 #define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
mbed_official 324:406fd2029f23 8007 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
mbed_official 324:406fd2029f23 8008 #define SIM_SOPT8_FTM3SYNCBIT_MASK 0x8u
mbed_official 324:406fd2029f23 8009 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT 3
mbed_official 324:406fd2029f23 8010 #define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
mbed_official 324:406fd2029f23 8011 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
mbed_official 324:406fd2029f23 8012 #define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
mbed_official 324:406fd2029f23 8013 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
mbed_official 324:406fd2029f23 8014 #define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
mbed_official 324:406fd2029f23 8015 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
mbed_official 324:406fd2029f23 8016 #define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
mbed_official 324:406fd2029f23 8017 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
mbed_official 324:406fd2029f23 8018 #define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
mbed_official 324:406fd2029f23 8019 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
mbed_official 324:406fd2029f23 8020 #define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
mbed_official 324:406fd2029f23 8021 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
mbed_official 324:406fd2029f23 8022 #define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
mbed_official 324:406fd2029f23 8023 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
mbed_official 324:406fd2029f23 8024 #define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
mbed_official 324:406fd2029f23 8025 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
mbed_official 324:406fd2029f23 8026 #define SIM_SOPT8_FTM3OCH0SRC_MASK 0x1000000u
mbed_official 324:406fd2029f23 8027 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT 24
mbed_official 324:406fd2029f23 8028 #define SIM_SOPT8_FTM3OCH1SRC_MASK 0x2000000u
mbed_official 324:406fd2029f23 8029 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT 25
mbed_official 324:406fd2029f23 8030 #define SIM_SOPT8_FTM3OCH2SRC_MASK 0x4000000u
mbed_official 324:406fd2029f23 8031 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT 26
mbed_official 324:406fd2029f23 8032 #define SIM_SOPT8_FTM3OCH3SRC_MASK 0x8000000u
mbed_official 324:406fd2029f23 8033 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT 27
mbed_official 324:406fd2029f23 8034 #define SIM_SOPT8_FTM3OCH4SRC_MASK 0x10000000u
mbed_official 324:406fd2029f23 8035 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT 28
mbed_official 324:406fd2029f23 8036 #define SIM_SOPT8_FTM3OCH5SRC_MASK 0x20000000u
mbed_official 324:406fd2029f23 8037 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT 29
mbed_official 324:406fd2029f23 8038 #define SIM_SOPT8_FTM3OCH6SRC_MASK 0x40000000u
mbed_official 324:406fd2029f23 8039 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT 30
mbed_official 324:406fd2029f23 8040 #define SIM_SOPT8_FTM3OCH7SRC_MASK 0x80000000u
mbed_official 324:406fd2029f23 8041 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT 31
mbed_official 324:406fd2029f23 8042 /* SDID Bit Fields */
mbed_official 324:406fd2029f23 8043 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 324:406fd2029f23 8044 #define SIM_SDID_PINID_SHIFT 0
mbed_official 324:406fd2029f23 8045 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 324:406fd2029f23 8046 #define SIM_SDID_FAMID_MASK 0x70u
mbed_official 324:406fd2029f23 8047 #define SIM_SDID_FAMID_SHIFT 4
mbed_official 324:406fd2029f23 8048 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 324:406fd2029f23 8049 #define SIM_SDID_DIEID_MASK 0xF80u
mbed_official 324:406fd2029f23 8050 #define SIM_SDID_DIEID_SHIFT 7
mbed_official 324:406fd2029f23 8051 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mbed_official 324:406fd2029f23 8052 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 324:406fd2029f23 8053 #define SIM_SDID_REVID_SHIFT 12
mbed_official 324:406fd2029f23 8054 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 324:406fd2029f23 8055 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 324:406fd2029f23 8056 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 324:406fd2029f23 8057 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 324:406fd2029f23 8058 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 324:406fd2029f23 8059 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 324:406fd2029f23 8060 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 324:406fd2029f23 8061 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
mbed_official 324:406fd2029f23 8062 #define SIM_SDID_FAMILYID_SHIFT 28
mbed_official 324:406fd2029f23 8063 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
mbed_official 324:406fd2029f23 8064 /* SCGC4 Bit Fields */
mbed_official 324:406fd2029f23 8065 #define SIM_SCGC4_EWM_MASK 0x2u
mbed_official 324:406fd2029f23 8066 #define SIM_SCGC4_EWM_SHIFT 1
mbed_official 324:406fd2029f23 8067 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 324:406fd2029f23 8068 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 324:406fd2029f23 8069 #define SIM_SCGC4_I2C1_MASK 0x80u
mbed_official 324:406fd2029f23 8070 #define SIM_SCGC4_I2C1_SHIFT 7
mbed_official 324:406fd2029f23 8071 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 324:406fd2029f23 8072 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 324:406fd2029f23 8073 #define SIM_SCGC4_UART1_MASK 0x800u
mbed_official 324:406fd2029f23 8074 #define SIM_SCGC4_UART1_SHIFT 11
mbed_official 324:406fd2029f23 8075 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 324:406fd2029f23 8076 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 324:406fd2029f23 8077 #define SIM_SCGC4_USBOTG_MASK 0x40000u
mbed_official 324:406fd2029f23 8078 #define SIM_SCGC4_USBOTG_SHIFT 18
mbed_official 324:406fd2029f23 8079 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 324:406fd2029f23 8080 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 324:406fd2029f23 8081 #define SIM_SCGC4_VREF_MASK 0x100000u
mbed_official 324:406fd2029f23 8082 #define SIM_SCGC4_VREF_SHIFT 20
mbed_official 324:406fd2029f23 8083 /* SCGC5 Bit Fields */
mbed_official 324:406fd2029f23 8084 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 324:406fd2029f23 8085 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 324:406fd2029f23 8086 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 324:406fd2029f23 8087 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 324:406fd2029f23 8088 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 324:406fd2029f23 8089 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 324:406fd2029f23 8090 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 324:406fd2029f23 8091 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 324:406fd2029f23 8092 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 324:406fd2029f23 8093 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 324:406fd2029f23 8094 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 324:406fd2029f23 8095 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 324:406fd2029f23 8096 /* SCGC6 Bit Fields */
mbed_official 324:406fd2029f23 8097 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 324:406fd2029f23 8098 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 324:406fd2029f23 8099 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 324:406fd2029f23 8100 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 324:406fd2029f23 8101 #define SIM_SCGC6_FTM3_MASK 0x40u
mbed_official 324:406fd2029f23 8102 #define SIM_SCGC6_FTM3_SHIFT 6
mbed_official 324:406fd2029f23 8103 #define SIM_SCGC6_ADC1_MASK 0x80u
mbed_official 324:406fd2029f23 8104 #define SIM_SCGC6_ADC1_SHIFT 7
mbed_official 324:406fd2029f23 8105 #define SIM_SCGC6_DAC1_MASK 0x100u
mbed_official 324:406fd2029f23 8106 #define SIM_SCGC6_DAC1_SHIFT 8
mbed_official 324:406fd2029f23 8107 #define SIM_SCGC6_RNGA_MASK 0x200u
mbed_official 324:406fd2029f23 8108 #define SIM_SCGC6_RNGA_SHIFT 9
mbed_official 324:406fd2029f23 8109 #define SIM_SCGC6_LPUART0_MASK 0x400u
mbed_official 324:406fd2029f23 8110 #define SIM_SCGC6_LPUART0_SHIFT 10
mbed_official 324:406fd2029f23 8111 #define SIM_SCGC6_SPI0_MASK 0x1000u
mbed_official 324:406fd2029f23 8112 #define SIM_SCGC6_SPI0_SHIFT 12
mbed_official 324:406fd2029f23 8113 #define SIM_SCGC6_SPI1_MASK 0x2000u
mbed_official 324:406fd2029f23 8114 #define SIM_SCGC6_SPI1_SHIFT 13
mbed_official 324:406fd2029f23 8115 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 324:406fd2029f23 8116 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 324:406fd2029f23 8117 #define SIM_SCGC6_CRC_MASK 0x40000u
mbed_official 324:406fd2029f23 8118 #define SIM_SCGC6_CRC_SHIFT 18
mbed_official 324:406fd2029f23 8119 #define SIM_SCGC6_PDB_MASK 0x400000u
mbed_official 324:406fd2029f23 8120 #define SIM_SCGC6_PDB_SHIFT 22
mbed_official 324:406fd2029f23 8121 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 324:406fd2029f23 8122 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 324:406fd2029f23 8123 #define SIM_SCGC6_FTM0_MASK 0x1000000u
mbed_official 324:406fd2029f23 8124 #define SIM_SCGC6_FTM0_SHIFT 24
mbed_official 324:406fd2029f23 8125 #define SIM_SCGC6_FTM1_MASK 0x2000000u
mbed_official 324:406fd2029f23 8126 #define SIM_SCGC6_FTM1_SHIFT 25
mbed_official 324:406fd2029f23 8127 #define SIM_SCGC6_FTM2_MASK 0x4000000u
mbed_official 324:406fd2029f23 8128 #define SIM_SCGC6_FTM2_SHIFT 26
mbed_official 324:406fd2029f23 8129 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 324:406fd2029f23 8130 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 324:406fd2029f23 8131 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 324:406fd2029f23 8132 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 324:406fd2029f23 8133 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 324:406fd2029f23 8134 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 324:406fd2029f23 8135 /* SCGC7 Bit Fields */
mbed_official 324:406fd2029f23 8136 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
mbed_official 324:406fd2029f23 8137 #define SIM_SCGC7_FLEXBUS_SHIFT 0
mbed_official 324:406fd2029f23 8138 #define SIM_SCGC7_DMA_MASK 0x2u
mbed_official 324:406fd2029f23 8139 #define SIM_SCGC7_DMA_SHIFT 1
mbed_official 324:406fd2029f23 8140 /* CLKDIV1 Bit Fields */
mbed_official 324:406fd2029f23 8141 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
mbed_official 324:406fd2029f23 8142 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 324:406fd2029f23 8143 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 324:406fd2029f23 8144 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
mbed_official 324:406fd2029f23 8145 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
mbed_official 324:406fd2029f23 8146 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
mbed_official 324:406fd2029f23 8147 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
mbed_official 324:406fd2029f23 8148 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
mbed_official 324:406fd2029f23 8149 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
mbed_official 324:406fd2029f23 8150 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 324:406fd2029f23 8151 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 324:406fd2029f23 8152 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 324:406fd2029f23 8153 /* CLKDIV2 Bit Fields */
mbed_official 324:406fd2029f23 8154 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
mbed_official 324:406fd2029f23 8155 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
mbed_official 324:406fd2029f23 8156 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
mbed_official 324:406fd2029f23 8157 #define SIM_CLKDIV2_USBDIV_SHIFT 1
mbed_official 324:406fd2029f23 8158 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
mbed_official 324:406fd2029f23 8159 /* FCFG1 Bit Fields */
mbed_official 324:406fd2029f23 8160 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 324:406fd2029f23 8161 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 324:406fd2029f23 8162 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 324:406fd2029f23 8163 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 324:406fd2029f23 8164 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 324:406fd2029f23 8165 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 324:406fd2029f23 8166 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 324:406fd2029f23 8167 /* FCFG2 Bit Fields */
mbed_official 324:406fd2029f23 8168 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 324:406fd2029f23 8169 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 324:406fd2029f23 8170 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 324:406fd2029f23 8171 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 324:406fd2029f23 8172 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 324:406fd2029f23 8173 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 324:406fd2029f23 8174 /* UIDH Bit Fields */
mbed_official 324:406fd2029f23 8175 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8176 #define SIM_UIDH_UID_SHIFT 0
mbed_official 324:406fd2029f23 8177 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
mbed_official 324:406fd2029f23 8178 /* UIDMH Bit Fields */
mbed_official 324:406fd2029f23 8179 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8180 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 324:406fd2029f23 8181 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 324:406fd2029f23 8182 /* UIDML Bit Fields */
mbed_official 324:406fd2029f23 8183 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8184 #define SIM_UIDML_UID_SHIFT 0
mbed_official 324:406fd2029f23 8185 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 324:406fd2029f23 8186 /* UIDL Bit Fields */
mbed_official 324:406fd2029f23 8187 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8188 #define SIM_UIDL_UID_SHIFT 0
mbed_official 324:406fd2029f23 8189 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 324:406fd2029f23 8190
mbed_official 324:406fd2029f23 8191 /*!
mbed_official 324:406fd2029f23 8192 * @}
mbed_official 324:406fd2029f23 8193 */ /* end of group SIM_Register_Masks */
mbed_official 324:406fd2029f23 8194
mbed_official 324:406fd2029f23 8195
mbed_official 324:406fd2029f23 8196 /* SIM - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 8197 /** Peripheral SIM base address */
mbed_official 324:406fd2029f23 8198 #define SIM_BASE (0x40047000u)
mbed_official 324:406fd2029f23 8199 /** Peripheral SIM base pointer */
mbed_official 324:406fd2029f23 8200 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 324:406fd2029f23 8201 #define SIM_BASE_PTR (SIM)
mbed_official 324:406fd2029f23 8202 /** Array initializer of SIM peripheral base addresses */
mbed_official 324:406fd2029f23 8203 #define SIM_BASE_ADDRS { SIM_BASE }
mbed_official 324:406fd2029f23 8204 /** Array initializer of SIM peripheral base pointers */
mbed_official 324:406fd2029f23 8205 #define SIM_BASE_PTRS { SIM }
mbed_official 324:406fd2029f23 8206
mbed_official 324:406fd2029f23 8207 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8208 -- SIM - Register accessor macros
mbed_official 324:406fd2029f23 8209 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8210
mbed_official 324:406fd2029f23 8211 /*!
mbed_official 324:406fd2029f23 8212 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 324:406fd2029f23 8213 * @{
mbed_official 324:406fd2029f23 8214 */
mbed_official 324:406fd2029f23 8215
mbed_official 324:406fd2029f23 8216
mbed_official 324:406fd2029f23 8217 /* SIM - Register instance definitions */
mbed_official 324:406fd2029f23 8218 /* SIM */
mbed_official 324:406fd2029f23 8219 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
mbed_official 324:406fd2029f23 8220 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
mbed_official 324:406fd2029f23 8221 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
mbed_official 324:406fd2029f23 8222 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
mbed_official 324:406fd2029f23 8223 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
mbed_official 324:406fd2029f23 8224 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
mbed_official 324:406fd2029f23 8225 #define SIM_SOPT8 SIM_SOPT8_REG(SIM)
mbed_official 324:406fd2029f23 8226 #define SIM_SDID SIM_SDID_REG(SIM)
mbed_official 324:406fd2029f23 8227 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
mbed_official 324:406fd2029f23 8228 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
mbed_official 324:406fd2029f23 8229 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
mbed_official 324:406fd2029f23 8230 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
mbed_official 324:406fd2029f23 8231 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
mbed_official 324:406fd2029f23 8232 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
mbed_official 324:406fd2029f23 8233 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
mbed_official 324:406fd2029f23 8234 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
mbed_official 324:406fd2029f23 8235 #define SIM_UIDH SIM_UIDH_REG(SIM)
mbed_official 324:406fd2029f23 8236 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
mbed_official 324:406fd2029f23 8237 #define SIM_UIDML SIM_UIDML_REG(SIM)
mbed_official 324:406fd2029f23 8238 #define SIM_UIDL SIM_UIDL_REG(SIM)
mbed_official 324:406fd2029f23 8239
mbed_official 324:406fd2029f23 8240 /*!
mbed_official 324:406fd2029f23 8241 * @}
mbed_official 324:406fd2029f23 8242 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8243
mbed_official 324:406fd2029f23 8244
mbed_official 324:406fd2029f23 8245 /*!
mbed_official 324:406fd2029f23 8246 * @}
mbed_official 324:406fd2029f23 8247 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 8248
mbed_official 324:406fd2029f23 8249
mbed_official 324:406fd2029f23 8250 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8251 -- SMC Peripheral Access Layer
mbed_official 324:406fd2029f23 8252 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8253
mbed_official 324:406fd2029f23 8254 /*!
mbed_official 324:406fd2029f23 8255 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 324:406fd2029f23 8256 * @{
mbed_official 324:406fd2029f23 8257 */
mbed_official 324:406fd2029f23 8258
mbed_official 324:406fd2029f23 8259 /** SMC - Register Layout Typedef */
mbed_official 324:406fd2029f23 8260 typedef struct {
mbed_official 324:406fd2029f23 8261 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 324:406fd2029f23 8262 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 324:406fd2029f23 8263 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mbed_official 324:406fd2029f23 8264 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 324:406fd2029f23 8265 } SMC_Type, *SMC_MemMapPtr;
mbed_official 324:406fd2029f23 8266
mbed_official 324:406fd2029f23 8267 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8268 -- SMC - Register accessor macros
mbed_official 324:406fd2029f23 8269 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8270
mbed_official 324:406fd2029f23 8271 /*!
mbed_official 324:406fd2029f23 8272 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 324:406fd2029f23 8273 * @{
mbed_official 324:406fd2029f23 8274 */
mbed_official 324:406fd2029f23 8275
mbed_official 324:406fd2029f23 8276
mbed_official 324:406fd2029f23 8277 /* SMC - Register accessors */
mbed_official 324:406fd2029f23 8278 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
mbed_official 324:406fd2029f23 8279 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
mbed_official 324:406fd2029f23 8280 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
mbed_official 324:406fd2029f23 8281 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
mbed_official 324:406fd2029f23 8282
mbed_official 324:406fd2029f23 8283 /*!
mbed_official 324:406fd2029f23 8284 * @}
mbed_official 324:406fd2029f23 8285 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8286
mbed_official 324:406fd2029f23 8287
mbed_official 324:406fd2029f23 8288 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8289 -- SMC Register Masks
mbed_official 324:406fd2029f23 8290 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8291
mbed_official 324:406fd2029f23 8292 /*!
mbed_official 324:406fd2029f23 8293 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 324:406fd2029f23 8294 * @{
mbed_official 324:406fd2029f23 8295 */
mbed_official 324:406fd2029f23 8296
mbed_official 324:406fd2029f23 8297 /* PMPROT Bit Fields */
mbed_official 324:406fd2029f23 8298 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 324:406fd2029f23 8299 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 324:406fd2029f23 8300 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 324:406fd2029f23 8301 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 324:406fd2029f23 8302 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 324:406fd2029f23 8303 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 324:406fd2029f23 8304 #define SMC_PMPROT_AHSRUN_MASK 0x80u
mbed_official 324:406fd2029f23 8305 #define SMC_PMPROT_AHSRUN_SHIFT 7
mbed_official 324:406fd2029f23 8306 /* PMCTRL Bit Fields */
mbed_official 324:406fd2029f23 8307 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 324:406fd2029f23 8308 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 324:406fd2029f23 8309 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 324:406fd2029f23 8310 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 324:406fd2029f23 8311 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 324:406fd2029f23 8312 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 324:406fd2029f23 8313 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 324:406fd2029f23 8314 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 324:406fd2029f23 8315 /* STOPCTRL Bit Fields */
mbed_official 324:406fd2029f23 8316 #define SMC_STOPCTRL_LLSM_MASK 0x7u
mbed_official 324:406fd2029f23 8317 #define SMC_STOPCTRL_LLSM_SHIFT 0
mbed_official 324:406fd2029f23 8318 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
mbed_official 324:406fd2029f23 8319 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mbed_official 324:406fd2029f23 8320 #define SMC_STOPCTRL_PORPO_SHIFT 5
mbed_official 324:406fd2029f23 8321 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mbed_official 324:406fd2029f23 8322 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mbed_official 324:406fd2029f23 8323 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mbed_official 324:406fd2029f23 8324 /* PMSTAT Bit Fields */
mbed_official 324:406fd2029f23 8325 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
mbed_official 324:406fd2029f23 8326 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 324:406fd2029f23 8327 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 324:406fd2029f23 8328
mbed_official 324:406fd2029f23 8329 /*!
mbed_official 324:406fd2029f23 8330 * @}
mbed_official 324:406fd2029f23 8331 */ /* end of group SMC_Register_Masks */
mbed_official 324:406fd2029f23 8332
mbed_official 324:406fd2029f23 8333
mbed_official 324:406fd2029f23 8334 /* SMC - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 8335 /** Peripheral SMC base address */
mbed_official 324:406fd2029f23 8336 #define SMC_BASE (0x4007E000u)
mbed_official 324:406fd2029f23 8337 /** Peripheral SMC base pointer */
mbed_official 324:406fd2029f23 8338 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 324:406fd2029f23 8339 #define SMC_BASE_PTR (SMC)
mbed_official 324:406fd2029f23 8340 /** Array initializer of SMC peripheral base addresses */
mbed_official 324:406fd2029f23 8341 #define SMC_BASE_ADDRS { SMC_BASE }
mbed_official 324:406fd2029f23 8342 /** Array initializer of SMC peripheral base pointers */
mbed_official 324:406fd2029f23 8343 #define SMC_BASE_PTRS { SMC }
mbed_official 324:406fd2029f23 8344
mbed_official 324:406fd2029f23 8345 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8346 -- SMC - Register accessor macros
mbed_official 324:406fd2029f23 8347 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8348
mbed_official 324:406fd2029f23 8349 /*!
mbed_official 324:406fd2029f23 8350 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 324:406fd2029f23 8351 * @{
mbed_official 324:406fd2029f23 8352 */
mbed_official 324:406fd2029f23 8353
mbed_official 324:406fd2029f23 8354
mbed_official 324:406fd2029f23 8355 /* SMC - Register instance definitions */
mbed_official 324:406fd2029f23 8356 /* SMC */
mbed_official 324:406fd2029f23 8357 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
mbed_official 324:406fd2029f23 8358 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
mbed_official 324:406fd2029f23 8359 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
mbed_official 324:406fd2029f23 8360 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
mbed_official 324:406fd2029f23 8361
mbed_official 324:406fd2029f23 8362 /*!
mbed_official 324:406fd2029f23 8363 * @}
mbed_official 324:406fd2029f23 8364 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8365
mbed_official 324:406fd2029f23 8366
mbed_official 324:406fd2029f23 8367 /*!
mbed_official 324:406fd2029f23 8368 * @}
mbed_official 324:406fd2029f23 8369 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 8370
mbed_official 324:406fd2029f23 8371
mbed_official 324:406fd2029f23 8372 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8373 -- SPI Peripheral Access Layer
mbed_official 324:406fd2029f23 8374 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8375
mbed_official 324:406fd2029f23 8376 /*!
mbed_official 324:406fd2029f23 8377 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 324:406fd2029f23 8378 * @{
mbed_official 324:406fd2029f23 8379 */
mbed_official 324:406fd2029f23 8380
mbed_official 324:406fd2029f23 8381 /** SPI - Register Layout Typedef */
mbed_official 324:406fd2029f23 8382 typedef struct {
mbed_official 324:406fd2029f23 8383 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
mbed_official 324:406fd2029f23 8384 uint8_t RESERVED_0[4];
mbed_official 324:406fd2029f23 8385 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
mbed_official 324:406fd2029f23 8386 union { /* offset: 0xC */
mbed_official 324:406fd2029f23 8387 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
mbed_official 324:406fd2029f23 8388 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
mbed_official 324:406fd2029f23 8389 };
mbed_official 324:406fd2029f23 8390 uint8_t RESERVED_1[24];
mbed_official 324:406fd2029f23 8391 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
mbed_official 324:406fd2029f23 8392 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
mbed_official 324:406fd2029f23 8393 union { /* offset: 0x34 */
mbed_official 324:406fd2029f23 8394 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
mbed_official 324:406fd2029f23 8395 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
mbed_official 324:406fd2029f23 8396 };
mbed_official 324:406fd2029f23 8397 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
mbed_official 324:406fd2029f23 8398 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
mbed_official 324:406fd2029f23 8399 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
mbed_official 324:406fd2029f23 8400 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
mbed_official 324:406fd2029f23 8401 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
mbed_official 324:406fd2029f23 8402 uint8_t RESERVED_2[48];
mbed_official 324:406fd2029f23 8403 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
mbed_official 324:406fd2029f23 8404 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
mbed_official 324:406fd2029f23 8405 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
mbed_official 324:406fd2029f23 8406 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
mbed_official 324:406fd2029f23 8407 } SPI_Type, *SPI_MemMapPtr;
mbed_official 324:406fd2029f23 8408
mbed_official 324:406fd2029f23 8409 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8410 -- SPI - Register accessor macros
mbed_official 324:406fd2029f23 8411 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8412
mbed_official 324:406fd2029f23 8413 /*!
mbed_official 324:406fd2029f23 8414 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 324:406fd2029f23 8415 * @{
mbed_official 324:406fd2029f23 8416 */
mbed_official 324:406fd2029f23 8417
mbed_official 324:406fd2029f23 8418
mbed_official 324:406fd2029f23 8419 /* SPI - Register accessors */
mbed_official 324:406fd2029f23 8420 #define SPI_MCR_REG(base) ((base)->MCR)
mbed_official 324:406fd2029f23 8421 #define SPI_TCR_REG(base) ((base)->TCR)
mbed_official 324:406fd2029f23 8422 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
mbed_official 324:406fd2029f23 8423 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
mbed_official 324:406fd2029f23 8424 #define SPI_SR_REG(base) ((base)->SR)
mbed_official 324:406fd2029f23 8425 #define SPI_RSER_REG(base) ((base)->RSER)
mbed_official 324:406fd2029f23 8426 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
mbed_official 324:406fd2029f23 8427 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
mbed_official 324:406fd2029f23 8428 #define SPI_POPR_REG(base) ((base)->POPR)
mbed_official 324:406fd2029f23 8429 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
mbed_official 324:406fd2029f23 8430 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
mbed_official 324:406fd2029f23 8431 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
mbed_official 324:406fd2029f23 8432 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
mbed_official 324:406fd2029f23 8433 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
mbed_official 324:406fd2029f23 8434 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
mbed_official 324:406fd2029f23 8435 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
mbed_official 324:406fd2029f23 8436 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
mbed_official 324:406fd2029f23 8437
mbed_official 324:406fd2029f23 8438 /*!
mbed_official 324:406fd2029f23 8439 * @}
mbed_official 324:406fd2029f23 8440 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8441
mbed_official 324:406fd2029f23 8442
mbed_official 324:406fd2029f23 8443 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8444 -- SPI Register Masks
mbed_official 324:406fd2029f23 8445 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8446
mbed_official 324:406fd2029f23 8447 /*!
mbed_official 324:406fd2029f23 8448 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 324:406fd2029f23 8449 * @{
mbed_official 324:406fd2029f23 8450 */
mbed_official 324:406fd2029f23 8451
mbed_official 324:406fd2029f23 8452 /* MCR Bit Fields */
mbed_official 324:406fd2029f23 8453 #define SPI_MCR_HALT_MASK 0x1u
mbed_official 324:406fd2029f23 8454 #define SPI_MCR_HALT_SHIFT 0
mbed_official 324:406fd2029f23 8455 #define SPI_MCR_SMPL_PT_MASK 0x300u
mbed_official 324:406fd2029f23 8456 #define SPI_MCR_SMPL_PT_SHIFT 8
mbed_official 324:406fd2029f23 8457 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
mbed_official 324:406fd2029f23 8458 #define SPI_MCR_CLR_RXF_MASK 0x400u
mbed_official 324:406fd2029f23 8459 #define SPI_MCR_CLR_RXF_SHIFT 10
mbed_official 324:406fd2029f23 8460 #define SPI_MCR_CLR_TXF_MASK 0x800u
mbed_official 324:406fd2029f23 8461 #define SPI_MCR_CLR_TXF_SHIFT 11
mbed_official 324:406fd2029f23 8462 #define SPI_MCR_DIS_RXF_MASK 0x1000u
mbed_official 324:406fd2029f23 8463 #define SPI_MCR_DIS_RXF_SHIFT 12
mbed_official 324:406fd2029f23 8464 #define SPI_MCR_DIS_TXF_MASK 0x2000u
mbed_official 324:406fd2029f23 8465 #define SPI_MCR_DIS_TXF_SHIFT 13
mbed_official 324:406fd2029f23 8466 #define SPI_MCR_MDIS_MASK 0x4000u
mbed_official 324:406fd2029f23 8467 #define SPI_MCR_MDIS_SHIFT 14
mbed_official 324:406fd2029f23 8468 #define SPI_MCR_DOZE_MASK 0x8000u
mbed_official 324:406fd2029f23 8469 #define SPI_MCR_DOZE_SHIFT 15
mbed_official 324:406fd2029f23 8470 #define SPI_MCR_PCSIS_MASK 0x3F0000u
mbed_official 324:406fd2029f23 8471 #define SPI_MCR_PCSIS_SHIFT 16
mbed_official 324:406fd2029f23 8472 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
mbed_official 324:406fd2029f23 8473 #define SPI_MCR_ROOE_MASK 0x1000000u
mbed_official 324:406fd2029f23 8474 #define SPI_MCR_ROOE_SHIFT 24
mbed_official 324:406fd2029f23 8475 #define SPI_MCR_PCSSE_MASK 0x2000000u
mbed_official 324:406fd2029f23 8476 #define SPI_MCR_PCSSE_SHIFT 25
mbed_official 324:406fd2029f23 8477 #define SPI_MCR_MTFE_MASK 0x4000000u
mbed_official 324:406fd2029f23 8478 #define SPI_MCR_MTFE_SHIFT 26
mbed_official 324:406fd2029f23 8479 #define SPI_MCR_FRZ_MASK 0x8000000u
mbed_official 324:406fd2029f23 8480 #define SPI_MCR_FRZ_SHIFT 27
mbed_official 324:406fd2029f23 8481 #define SPI_MCR_DCONF_MASK 0x30000000u
mbed_official 324:406fd2029f23 8482 #define SPI_MCR_DCONF_SHIFT 28
mbed_official 324:406fd2029f23 8483 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
mbed_official 324:406fd2029f23 8484 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
mbed_official 324:406fd2029f23 8485 #define SPI_MCR_CONT_SCKE_SHIFT 30
mbed_official 324:406fd2029f23 8486 #define SPI_MCR_MSTR_MASK 0x80000000u
mbed_official 324:406fd2029f23 8487 #define SPI_MCR_MSTR_SHIFT 31
mbed_official 324:406fd2029f23 8488 /* TCR Bit Fields */
mbed_official 324:406fd2029f23 8489 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 8490 #define SPI_TCR_SPI_TCNT_SHIFT 16
mbed_official 324:406fd2029f23 8491 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
mbed_official 324:406fd2029f23 8492 /* CTAR Bit Fields */
mbed_official 324:406fd2029f23 8493 #define SPI_CTAR_BR_MASK 0xFu
mbed_official 324:406fd2029f23 8494 #define SPI_CTAR_BR_SHIFT 0
mbed_official 324:406fd2029f23 8495 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
mbed_official 324:406fd2029f23 8496 #define SPI_CTAR_DT_MASK 0xF0u
mbed_official 324:406fd2029f23 8497 #define SPI_CTAR_DT_SHIFT 4
mbed_official 324:406fd2029f23 8498 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
mbed_official 324:406fd2029f23 8499 #define SPI_CTAR_ASC_MASK 0xF00u
mbed_official 324:406fd2029f23 8500 #define SPI_CTAR_ASC_SHIFT 8
mbed_official 324:406fd2029f23 8501 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
mbed_official 324:406fd2029f23 8502 #define SPI_CTAR_CSSCK_MASK 0xF000u
mbed_official 324:406fd2029f23 8503 #define SPI_CTAR_CSSCK_SHIFT 12
mbed_official 324:406fd2029f23 8504 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
mbed_official 324:406fd2029f23 8505 #define SPI_CTAR_PBR_MASK 0x30000u
mbed_official 324:406fd2029f23 8506 #define SPI_CTAR_PBR_SHIFT 16
mbed_official 324:406fd2029f23 8507 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
mbed_official 324:406fd2029f23 8508 #define SPI_CTAR_PDT_MASK 0xC0000u
mbed_official 324:406fd2029f23 8509 #define SPI_CTAR_PDT_SHIFT 18
mbed_official 324:406fd2029f23 8510 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
mbed_official 324:406fd2029f23 8511 #define SPI_CTAR_PASC_MASK 0x300000u
mbed_official 324:406fd2029f23 8512 #define SPI_CTAR_PASC_SHIFT 20
mbed_official 324:406fd2029f23 8513 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
mbed_official 324:406fd2029f23 8514 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
mbed_official 324:406fd2029f23 8515 #define SPI_CTAR_PCSSCK_SHIFT 22
mbed_official 324:406fd2029f23 8516 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
mbed_official 324:406fd2029f23 8517 #define SPI_CTAR_LSBFE_MASK 0x1000000u
mbed_official 324:406fd2029f23 8518 #define SPI_CTAR_LSBFE_SHIFT 24
mbed_official 324:406fd2029f23 8519 #define SPI_CTAR_CPHA_MASK 0x2000000u
mbed_official 324:406fd2029f23 8520 #define SPI_CTAR_CPHA_SHIFT 25
mbed_official 324:406fd2029f23 8521 #define SPI_CTAR_CPOL_MASK 0x4000000u
mbed_official 324:406fd2029f23 8522 #define SPI_CTAR_CPOL_SHIFT 26
mbed_official 324:406fd2029f23 8523 #define SPI_CTAR_FMSZ_MASK 0x78000000u
mbed_official 324:406fd2029f23 8524 #define SPI_CTAR_FMSZ_SHIFT 27
mbed_official 324:406fd2029f23 8525 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
mbed_official 324:406fd2029f23 8526 #define SPI_CTAR_DBR_MASK 0x80000000u
mbed_official 324:406fd2029f23 8527 #define SPI_CTAR_DBR_SHIFT 31
mbed_official 324:406fd2029f23 8528 /* CTAR_SLAVE Bit Fields */
mbed_official 324:406fd2029f23 8529 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
mbed_official 324:406fd2029f23 8530 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
mbed_official 324:406fd2029f23 8531 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
mbed_official 324:406fd2029f23 8532 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
mbed_official 324:406fd2029f23 8533 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
mbed_official 324:406fd2029f23 8534 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
mbed_official 324:406fd2029f23 8535 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
mbed_official 324:406fd2029f23 8536 /* SR Bit Fields */
mbed_official 324:406fd2029f23 8537 #define SPI_SR_POPNXTPTR_MASK 0xFu
mbed_official 324:406fd2029f23 8538 #define SPI_SR_POPNXTPTR_SHIFT 0
mbed_official 324:406fd2029f23 8539 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
mbed_official 324:406fd2029f23 8540 #define SPI_SR_RXCTR_MASK 0xF0u
mbed_official 324:406fd2029f23 8541 #define SPI_SR_RXCTR_SHIFT 4
mbed_official 324:406fd2029f23 8542 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
mbed_official 324:406fd2029f23 8543 #define SPI_SR_TXNXTPTR_MASK 0xF00u
mbed_official 324:406fd2029f23 8544 #define SPI_SR_TXNXTPTR_SHIFT 8
mbed_official 324:406fd2029f23 8545 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
mbed_official 324:406fd2029f23 8546 #define SPI_SR_TXCTR_MASK 0xF000u
mbed_official 324:406fd2029f23 8547 #define SPI_SR_TXCTR_SHIFT 12
mbed_official 324:406fd2029f23 8548 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
mbed_official 324:406fd2029f23 8549 #define SPI_SR_RFDF_MASK 0x20000u
mbed_official 324:406fd2029f23 8550 #define SPI_SR_RFDF_SHIFT 17
mbed_official 324:406fd2029f23 8551 #define SPI_SR_RFOF_MASK 0x80000u
mbed_official 324:406fd2029f23 8552 #define SPI_SR_RFOF_SHIFT 19
mbed_official 324:406fd2029f23 8553 #define SPI_SR_TFFF_MASK 0x2000000u
mbed_official 324:406fd2029f23 8554 #define SPI_SR_TFFF_SHIFT 25
mbed_official 324:406fd2029f23 8555 #define SPI_SR_TFUF_MASK 0x8000000u
mbed_official 324:406fd2029f23 8556 #define SPI_SR_TFUF_SHIFT 27
mbed_official 324:406fd2029f23 8557 #define SPI_SR_EOQF_MASK 0x10000000u
mbed_official 324:406fd2029f23 8558 #define SPI_SR_EOQF_SHIFT 28
mbed_official 324:406fd2029f23 8559 #define SPI_SR_TXRXS_MASK 0x40000000u
mbed_official 324:406fd2029f23 8560 #define SPI_SR_TXRXS_SHIFT 30
mbed_official 324:406fd2029f23 8561 #define SPI_SR_TCF_MASK 0x80000000u
mbed_official 324:406fd2029f23 8562 #define SPI_SR_TCF_SHIFT 31
mbed_official 324:406fd2029f23 8563 /* RSER Bit Fields */
mbed_official 324:406fd2029f23 8564 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
mbed_official 324:406fd2029f23 8565 #define SPI_RSER_RFDF_DIRS_SHIFT 16
mbed_official 324:406fd2029f23 8566 #define SPI_RSER_RFDF_RE_MASK 0x20000u
mbed_official 324:406fd2029f23 8567 #define SPI_RSER_RFDF_RE_SHIFT 17
mbed_official 324:406fd2029f23 8568 #define SPI_RSER_RFOF_RE_MASK 0x80000u
mbed_official 324:406fd2029f23 8569 #define SPI_RSER_RFOF_RE_SHIFT 19
mbed_official 324:406fd2029f23 8570 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
mbed_official 324:406fd2029f23 8571 #define SPI_RSER_TFFF_DIRS_SHIFT 24
mbed_official 324:406fd2029f23 8572 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
mbed_official 324:406fd2029f23 8573 #define SPI_RSER_TFFF_RE_SHIFT 25
mbed_official 324:406fd2029f23 8574 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
mbed_official 324:406fd2029f23 8575 #define SPI_RSER_TFUF_RE_SHIFT 27
mbed_official 324:406fd2029f23 8576 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
mbed_official 324:406fd2029f23 8577 #define SPI_RSER_EOQF_RE_SHIFT 28
mbed_official 324:406fd2029f23 8578 #define SPI_RSER_TCF_RE_MASK 0x80000000u
mbed_official 324:406fd2029f23 8579 #define SPI_RSER_TCF_RE_SHIFT 31
mbed_official 324:406fd2029f23 8580 /* PUSHR Bit Fields */
mbed_official 324:406fd2029f23 8581 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
mbed_official 324:406fd2029f23 8582 #define SPI_PUSHR_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8583 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
mbed_official 324:406fd2029f23 8584 #define SPI_PUSHR_PCS_MASK 0x3F0000u
mbed_official 324:406fd2029f23 8585 #define SPI_PUSHR_PCS_SHIFT 16
mbed_official 324:406fd2029f23 8586 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
mbed_official 324:406fd2029f23 8587 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
mbed_official 324:406fd2029f23 8588 #define SPI_PUSHR_CTCNT_SHIFT 26
mbed_official 324:406fd2029f23 8589 #define SPI_PUSHR_EOQ_MASK 0x8000000u
mbed_official 324:406fd2029f23 8590 #define SPI_PUSHR_EOQ_SHIFT 27
mbed_official 324:406fd2029f23 8591 #define SPI_PUSHR_CTAS_MASK 0x70000000u
mbed_official 324:406fd2029f23 8592 #define SPI_PUSHR_CTAS_SHIFT 28
mbed_official 324:406fd2029f23 8593 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
mbed_official 324:406fd2029f23 8594 #define SPI_PUSHR_CONT_MASK 0x80000000u
mbed_official 324:406fd2029f23 8595 #define SPI_PUSHR_CONT_SHIFT 31
mbed_official 324:406fd2029f23 8596 /* PUSHR_SLAVE Bit Fields */
mbed_official 324:406fd2029f23 8597 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8598 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8599 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
mbed_official 324:406fd2029f23 8600 /* POPR Bit Fields */
mbed_official 324:406fd2029f23 8601 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8602 #define SPI_POPR_RXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8603 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
mbed_official 324:406fd2029f23 8604 /* TXFR0 Bit Fields */
mbed_official 324:406fd2029f23 8605 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
mbed_official 324:406fd2029f23 8606 #define SPI_TXFR0_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8607 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
mbed_official 324:406fd2029f23 8608 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 8609 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
mbed_official 324:406fd2029f23 8610 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
mbed_official 324:406fd2029f23 8611 /* TXFR1 Bit Fields */
mbed_official 324:406fd2029f23 8612 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
mbed_official 324:406fd2029f23 8613 #define SPI_TXFR1_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8614 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
mbed_official 324:406fd2029f23 8615 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 8616 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
mbed_official 324:406fd2029f23 8617 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
mbed_official 324:406fd2029f23 8618 /* TXFR2 Bit Fields */
mbed_official 324:406fd2029f23 8619 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
mbed_official 324:406fd2029f23 8620 #define SPI_TXFR2_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8621 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
mbed_official 324:406fd2029f23 8622 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 8623 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
mbed_official 324:406fd2029f23 8624 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
mbed_official 324:406fd2029f23 8625 /* TXFR3 Bit Fields */
mbed_official 324:406fd2029f23 8626 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
mbed_official 324:406fd2029f23 8627 #define SPI_TXFR3_TXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8628 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
mbed_official 324:406fd2029f23 8629 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
mbed_official 324:406fd2029f23 8630 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
mbed_official 324:406fd2029f23 8631 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
mbed_official 324:406fd2029f23 8632 /* RXFR0 Bit Fields */
mbed_official 324:406fd2029f23 8633 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8634 #define SPI_RXFR0_RXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8635 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
mbed_official 324:406fd2029f23 8636 /* RXFR1 Bit Fields */
mbed_official 324:406fd2029f23 8637 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8638 #define SPI_RXFR1_RXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8639 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
mbed_official 324:406fd2029f23 8640 /* RXFR2 Bit Fields */
mbed_official 324:406fd2029f23 8641 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8642 #define SPI_RXFR2_RXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8643 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
mbed_official 324:406fd2029f23 8644 /* RXFR3 Bit Fields */
mbed_official 324:406fd2029f23 8645 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
mbed_official 324:406fd2029f23 8646 #define SPI_RXFR3_RXDATA_SHIFT 0
mbed_official 324:406fd2029f23 8647 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
mbed_official 324:406fd2029f23 8648
mbed_official 324:406fd2029f23 8649 /*!
mbed_official 324:406fd2029f23 8650 * @}
mbed_official 324:406fd2029f23 8651 */ /* end of group SPI_Register_Masks */
mbed_official 324:406fd2029f23 8652
mbed_official 324:406fd2029f23 8653
mbed_official 324:406fd2029f23 8654 /* SPI - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 8655 /** Peripheral SPI0 base address */
mbed_official 324:406fd2029f23 8656 #define SPI0_BASE (0x4002C000u)
mbed_official 324:406fd2029f23 8657 /** Peripheral SPI0 base pointer */
mbed_official 324:406fd2029f23 8658 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 324:406fd2029f23 8659 #define SPI0_BASE_PTR (SPI0)
mbed_official 324:406fd2029f23 8660 /** Peripheral SPI1 base address */
mbed_official 324:406fd2029f23 8661 #define SPI1_BASE (0x4002D000u)
mbed_official 324:406fd2029f23 8662 /** Peripheral SPI1 base pointer */
mbed_official 324:406fd2029f23 8663 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 324:406fd2029f23 8664 #define SPI1_BASE_PTR (SPI1)
mbed_official 324:406fd2029f23 8665 /** Array initializer of SPI peripheral base addresses */
mbed_official 324:406fd2029f23 8666 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
mbed_official 324:406fd2029f23 8667 /** Array initializer of SPI peripheral base pointers */
mbed_official 324:406fd2029f23 8668 #define SPI_BASE_PTRS { SPI0, SPI1 }
mbed_official 324:406fd2029f23 8669 /** Interrupt vectors for the SPI peripheral type */
mbed_official 324:406fd2029f23 8670 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
mbed_official 324:406fd2029f23 8671
mbed_official 324:406fd2029f23 8672 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8673 -- SPI - Register accessor macros
mbed_official 324:406fd2029f23 8674 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8675
mbed_official 324:406fd2029f23 8676 /*!
mbed_official 324:406fd2029f23 8677 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 324:406fd2029f23 8678 * @{
mbed_official 324:406fd2029f23 8679 */
mbed_official 324:406fd2029f23 8680
mbed_official 324:406fd2029f23 8681
mbed_official 324:406fd2029f23 8682 /* SPI - Register instance definitions */
mbed_official 324:406fd2029f23 8683 /* SPI0 */
mbed_official 324:406fd2029f23 8684 #define SPI0_MCR SPI_MCR_REG(SPI0)
mbed_official 324:406fd2029f23 8685 #define SPI0_TCR SPI_TCR_REG(SPI0)
mbed_official 324:406fd2029f23 8686 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
mbed_official 324:406fd2029f23 8687 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
mbed_official 324:406fd2029f23 8688 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
mbed_official 324:406fd2029f23 8689 #define SPI0_SR SPI_SR_REG(SPI0)
mbed_official 324:406fd2029f23 8690 #define SPI0_RSER SPI_RSER_REG(SPI0)
mbed_official 324:406fd2029f23 8691 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
mbed_official 324:406fd2029f23 8692 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
mbed_official 324:406fd2029f23 8693 #define SPI0_POPR SPI_POPR_REG(SPI0)
mbed_official 324:406fd2029f23 8694 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
mbed_official 324:406fd2029f23 8695 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
mbed_official 324:406fd2029f23 8696 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
mbed_official 324:406fd2029f23 8697 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
mbed_official 324:406fd2029f23 8698 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
mbed_official 324:406fd2029f23 8699 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
mbed_official 324:406fd2029f23 8700 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
mbed_official 324:406fd2029f23 8701 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
mbed_official 324:406fd2029f23 8702 /* SPI1 */
mbed_official 324:406fd2029f23 8703 #define SPI1_MCR SPI_MCR_REG(SPI1)
mbed_official 324:406fd2029f23 8704 #define SPI1_TCR SPI_TCR_REG(SPI1)
mbed_official 324:406fd2029f23 8705 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
mbed_official 324:406fd2029f23 8706 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
mbed_official 324:406fd2029f23 8707 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
mbed_official 324:406fd2029f23 8708 #define SPI1_SR SPI_SR_REG(SPI1)
mbed_official 324:406fd2029f23 8709 #define SPI1_RSER SPI_RSER_REG(SPI1)
mbed_official 324:406fd2029f23 8710 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
mbed_official 324:406fd2029f23 8711 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
mbed_official 324:406fd2029f23 8712 #define SPI1_POPR SPI_POPR_REG(SPI1)
mbed_official 324:406fd2029f23 8713 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
mbed_official 324:406fd2029f23 8714 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
mbed_official 324:406fd2029f23 8715 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
mbed_official 324:406fd2029f23 8716 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
mbed_official 324:406fd2029f23 8717 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
mbed_official 324:406fd2029f23 8718 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
mbed_official 324:406fd2029f23 8719 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
mbed_official 324:406fd2029f23 8720 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
mbed_official 324:406fd2029f23 8721
mbed_official 324:406fd2029f23 8722 /* SPI - Register array accessors */
mbed_official 324:406fd2029f23 8723 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
mbed_official 324:406fd2029f23 8724 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
mbed_official 324:406fd2029f23 8725 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
mbed_official 324:406fd2029f23 8726 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
mbed_official 324:406fd2029f23 8727
mbed_official 324:406fd2029f23 8728 /*!
mbed_official 324:406fd2029f23 8729 * @}
mbed_official 324:406fd2029f23 8730 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8731
mbed_official 324:406fd2029f23 8732
mbed_official 324:406fd2029f23 8733 /*!
mbed_official 324:406fd2029f23 8734 * @}
mbed_official 324:406fd2029f23 8735 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 8736
mbed_official 324:406fd2029f23 8737
mbed_official 324:406fd2029f23 8738 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8739 -- UART Peripheral Access Layer
mbed_official 324:406fd2029f23 8740 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8741
mbed_official 324:406fd2029f23 8742 /*!
mbed_official 324:406fd2029f23 8743 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 324:406fd2029f23 8744 * @{
mbed_official 324:406fd2029f23 8745 */
mbed_official 324:406fd2029f23 8746
mbed_official 324:406fd2029f23 8747 /** UART - Register Layout Typedef */
mbed_official 324:406fd2029f23 8748 typedef struct {
mbed_official 324:406fd2029f23 8749 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
mbed_official 324:406fd2029f23 8750 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
mbed_official 324:406fd2029f23 8751 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 324:406fd2029f23 8752 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 324:406fd2029f23 8753 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 324:406fd2029f23 8754 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 324:406fd2029f23 8755 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 324:406fd2029f23 8756 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 324:406fd2029f23 8757 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 324:406fd2029f23 8758 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 324:406fd2029f23 8759 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 324:406fd2029f23 8760 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 324:406fd2029f23 8761 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
mbed_official 324:406fd2029f23 8762 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
mbed_official 324:406fd2029f23 8763 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
mbed_official 324:406fd2029f23 8764 uint8_t RESERVED_0[1];
mbed_official 324:406fd2029f23 8765 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
mbed_official 324:406fd2029f23 8766 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
mbed_official 324:406fd2029f23 8767 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
mbed_official 324:406fd2029f23 8768 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
mbed_official 324:406fd2029f23 8769 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
mbed_official 324:406fd2029f23 8770 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
mbed_official 324:406fd2029f23 8771 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
mbed_official 324:406fd2029f23 8772 uint8_t RESERVED_1[1];
mbed_official 324:406fd2029f23 8773 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
mbed_official 324:406fd2029f23 8774 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
mbed_official 324:406fd2029f23 8775 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
mbed_official 324:406fd2029f23 8776 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 324:406fd2029f23 8777 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
mbed_official 324:406fd2029f23 8778 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
mbed_official 324:406fd2029f23 8779 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
mbed_official 324:406fd2029f23 8780 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
mbed_official 324:406fd2029f23 8781 uint8_t RESERVED_2[26];
mbed_official 324:406fd2029f23 8782 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
mbed_official 324:406fd2029f23 8783 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
mbed_official 324:406fd2029f23 8784 union { /* offset: 0x3C */
mbed_official 324:406fd2029f23 8785 struct { /* offset: 0x3C */
mbed_official 324:406fd2029f23 8786 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
mbed_official 324:406fd2029f23 8787 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
mbed_official 324:406fd2029f23 8788 } TYPE0;
mbed_official 324:406fd2029f23 8789 struct { /* offset: 0x3C */
mbed_official 324:406fd2029f23 8790 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
mbed_official 324:406fd2029f23 8791 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
mbed_official 324:406fd2029f23 8792 } TYPE1;
mbed_official 324:406fd2029f23 8793 };
mbed_official 324:406fd2029f23 8794 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
mbed_official 324:406fd2029f23 8795 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
mbed_official 324:406fd2029f23 8796 } UART_Type, *UART_MemMapPtr;
mbed_official 324:406fd2029f23 8797
mbed_official 324:406fd2029f23 8798 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8799 -- UART - Register accessor macros
mbed_official 324:406fd2029f23 8800 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8801
mbed_official 324:406fd2029f23 8802 /*!
mbed_official 324:406fd2029f23 8803 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 324:406fd2029f23 8804 * @{
mbed_official 324:406fd2029f23 8805 */
mbed_official 324:406fd2029f23 8806
mbed_official 324:406fd2029f23 8807
mbed_official 324:406fd2029f23 8808 /* UART - Register accessors */
mbed_official 324:406fd2029f23 8809 #define UART_BDH_REG(base) ((base)->BDH)
mbed_official 324:406fd2029f23 8810 #define UART_BDL_REG(base) ((base)->BDL)
mbed_official 324:406fd2029f23 8811 #define UART_C1_REG(base) ((base)->C1)
mbed_official 324:406fd2029f23 8812 #define UART_C2_REG(base) ((base)->C2)
mbed_official 324:406fd2029f23 8813 #define UART_S1_REG(base) ((base)->S1)
mbed_official 324:406fd2029f23 8814 #define UART_S2_REG(base) ((base)->S2)
mbed_official 324:406fd2029f23 8815 #define UART_C3_REG(base) ((base)->C3)
mbed_official 324:406fd2029f23 8816 #define UART_D_REG(base) ((base)->D)
mbed_official 324:406fd2029f23 8817 #define UART_MA1_REG(base) ((base)->MA1)
mbed_official 324:406fd2029f23 8818 #define UART_MA2_REG(base) ((base)->MA2)
mbed_official 324:406fd2029f23 8819 #define UART_C4_REG(base) ((base)->C4)
mbed_official 324:406fd2029f23 8820 #define UART_C5_REG(base) ((base)->C5)
mbed_official 324:406fd2029f23 8821 #define UART_ED_REG(base) ((base)->ED)
mbed_official 324:406fd2029f23 8822 #define UART_MODEM_REG(base) ((base)->MODEM)
mbed_official 324:406fd2029f23 8823 #define UART_IR_REG(base) ((base)->IR)
mbed_official 324:406fd2029f23 8824 #define UART_PFIFO_REG(base) ((base)->PFIFO)
mbed_official 324:406fd2029f23 8825 #define UART_CFIFO_REG(base) ((base)->CFIFO)
mbed_official 324:406fd2029f23 8826 #define UART_SFIFO_REG(base) ((base)->SFIFO)
mbed_official 324:406fd2029f23 8827 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
mbed_official 324:406fd2029f23 8828 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
mbed_official 324:406fd2029f23 8829 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
mbed_official 324:406fd2029f23 8830 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
mbed_official 324:406fd2029f23 8831 #define UART_C7816_REG(base) ((base)->C7816)
mbed_official 324:406fd2029f23 8832 #define UART_IE7816_REG(base) ((base)->IE7816)
mbed_official 324:406fd2029f23 8833 #define UART_IS7816_REG(base) ((base)->IS7816)
mbed_official 324:406fd2029f23 8834 #define UART_WP7816_REG(base) ((base)->WP7816)
mbed_official 324:406fd2029f23 8835 #define UART_WN7816_REG(base) ((base)->WN7816)
mbed_official 324:406fd2029f23 8836 #define UART_WF7816_REG(base) ((base)->WF7816)
mbed_official 324:406fd2029f23 8837 #define UART_ET7816_REG(base) ((base)->ET7816)
mbed_official 324:406fd2029f23 8838 #define UART_TL7816_REG(base) ((base)->TL7816)
mbed_official 324:406fd2029f23 8839 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
mbed_official 324:406fd2029f23 8840 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
mbed_official 324:406fd2029f23 8841 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
mbed_official 324:406fd2029f23 8842 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
mbed_official 324:406fd2029f23 8843 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
mbed_official 324:406fd2029f23 8844 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
mbed_official 324:406fd2029f23 8845 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
mbed_official 324:406fd2029f23 8846 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
mbed_official 324:406fd2029f23 8847
mbed_official 324:406fd2029f23 8848 /*!
mbed_official 324:406fd2029f23 8849 * @}
mbed_official 324:406fd2029f23 8850 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 8851
mbed_official 324:406fd2029f23 8852
mbed_official 324:406fd2029f23 8853 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 8854 -- UART Register Masks
mbed_official 324:406fd2029f23 8855 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 8856
mbed_official 324:406fd2029f23 8857 /*!
mbed_official 324:406fd2029f23 8858 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 324:406fd2029f23 8859 * @{
mbed_official 324:406fd2029f23 8860 */
mbed_official 324:406fd2029f23 8861
mbed_official 324:406fd2029f23 8862 /* BDH Bit Fields */
mbed_official 324:406fd2029f23 8863 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 324:406fd2029f23 8864 #define UART_BDH_SBR_SHIFT 0
mbed_official 324:406fd2029f23 8865 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 324:406fd2029f23 8866 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 324:406fd2029f23 8867 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 324:406fd2029f23 8868 #define UART_BDH_LBKDIE_MASK 0x80u
mbed_official 324:406fd2029f23 8869 #define UART_BDH_LBKDIE_SHIFT 7
mbed_official 324:406fd2029f23 8870 /* BDL Bit Fields */
mbed_official 324:406fd2029f23 8871 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 324:406fd2029f23 8872 #define UART_BDL_SBR_SHIFT 0
mbed_official 324:406fd2029f23 8873 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 324:406fd2029f23 8874 /* C1 Bit Fields */
mbed_official 324:406fd2029f23 8875 #define UART_C1_PT_MASK 0x1u
mbed_official 324:406fd2029f23 8876 #define UART_C1_PT_SHIFT 0
mbed_official 324:406fd2029f23 8877 #define UART_C1_PE_MASK 0x2u
mbed_official 324:406fd2029f23 8878 #define UART_C1_PE_SHIFT 1
mbed_official 324:406fd2029f23 8879 #define UART_C1_ILT_MASK 0x4u
mbed_official 324:406fd2029f23 8880 #define UART_C1_ILT_SHIFT 2
mbed_official 324:406fd2029f23 8881 #define UART_C1_WAKE_MASK 0x8u
mbed_official 324:406fd2029f23 8882 #define UART_C1_WAKE_SHIFT 3
mbed_official 324:406fd2029f23 8883 #define UART_C1_M_MASK 0x10u
mbed_official 324:406fd2029f23 8884 #define UART_C1_M_SHIFT 4
mbed_official 324:406fd2029f23 8885 #define UART_C1_RSRC_MASK 0x20u
mbed_official 324:406fd2029f23 8886 #define UART_C1_RSRC_SHIFT 5
mbed_official 324:406fd2029f23 8887 #define UART_C1_UARTSWAI_MASK 0x40u
mbed_official 324:406fd2029f23 8888 #define UART_C1_UARTSWAI_SHIFT 6
mbed_official 324:406fd2029f23 8889 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 324:406fd2029f23 8890 #define UART_C1_LOOPS_SHIFT 7
mbed_official 324:406fd2029f23 8891 /* C2 Bit Fields */
mbed_official 324:406fd2029f23 8892 #define UART_C2_SBK_MASK 0x1u
mbed_official 324:406fd2029f23 8893 #define UART_C2_SBK_SHIFT 0
mbed_official 324:406fd2029f23 8894 #define UART_C2_RWU_MASK 0x2u
mbed_official 324:406fd2029f23 8895 #define UART_C2_RWU_SHIFT 1
mbed_official 324:406fd2029f23 8896 #define UART_C2_RE_MASK 0x4u
mbed_official 324:406fd2029f23 8897 #define UART_C2_RE_SHIFT 2
mbed_official 324:406fd2029f23 8898 #define UART_C2_TE_MASK 0x8u
mbed_official 324:406fd2029f23 8899 #define UART_C2_TE_SHIFT 3
mbed_official 324:406fd2029f23 8900 #define UART_C2_ILIE_MASK 0x10u
mbed_official 324:406fd2029f23 8901 #define UART_C2_ILIE_SHIFT 4
mbed_official 324:406fd2029f23 8902 #define UART_C2_RIE_MASK 0x20u
mbed_official 324:406fd2029f23 8903 #define UART_C2_RIE_SHIFT 5
mbed_official 324:406fd2029f23 8904 #define UART_C2_TCIE_MASK 0x40u
mbed_official 324:406fd2029f23 8905 #define UART_C2_TCIE_SHIFT 6
mbed_official 324:406fd2029f23 8906 #define UART_C2_TIE_MASK 0x80u
mbed_official 324:406fd2029f23 8907 #define UART_C2_TIE_SHIFT 7
mbed_official 324:406fd2029f23 8908 /* S1 Bit Fields */
mbed_official 324:406fd2029f23 8909 #define UART_S1_PF_MASK 0x1u
mbed_official 324:406fd2029f23 8910 #define UART_S1_PF_SHIFT 0
mbed_official 324:406fd2029f23 8911 #define UART_S1_FE_MASK 0x2u
mbed_official 324:406fd2029f23 8912 #define UART_S1_FE_SHIFT 1
mbed_official 324:406fd2029f23 8913 #define UART_S1_NF_MASK 0x4u
mbed_official 324:406fd2029f23 8914 #define UART_S1_NF_SHIFT 2
mbed_official 324:406fd2029f23 8915 #define UART_S1_OR_MASK 0x8u
mbed_official 324:406fd2029f23 8916 #define UART_S1_OR_SHIFT 3
mbed_official 324:406fd2029f23 8917 #define UART_S1_IDLE_MASK 0x10u
mbed_official 324:406fd2029f23 8918 #define UART_S1_IDLE_SHIFT 4
mbed_official 324:406fd2029f23 8919 #define UART_S1_RDRF_MASK 0x20u
mbed_official 324:406fd2029f23 8920 #define UART_S1_RDRF_SHIFT 5
mbed_official 324:406fd2029f23 8921 #define UART_S1_TC_MASK 0x40u
mbed_official 324:406fd2029f23 8922 #define UART_S1_TC_SHIFT 6
mbed_official 324:406fd2029f23 8923 #define UART_S1_TDRE_MASK 0x80u
mbed_official 324:406fd2029f23 8924 #define UART_S1_TDRE_SHIFT 7
mbed_official 324:406fd2029f23 8925 /* S2 Bit Fields */
mbed_official 324:406fd2029f23 8926 #define UART_S2_RAF_MASK 0x1u
mbed_official 324:406fd2029f23 8927 #define UART_S2_RAF_SHIFT 0
mbed_official 324:406fd2029f23 8928 #define UART_S2_LBKDE_MASK 0x2u
mbed_official 324:406fd2029f23 8929 #define UART_S2_LBKDE_SHIFT 1
mbed_official 324:406fd2029f23 8930 #define UART_S2_BRK13_MASK 0x4u
mbed_official 324:406fd2029f23 8931 #define UART_S2_BRK13_SHIFT 2
mbed_official 324:406fd2029f23 8932 #define UART_S2_RWUID_MASK 0x8u
mbed_official 324:406fd2029f23 8933 #define UART_S2_RWUID_SHIFT 3
mbed_official 324:406fd2029f23 8934 #define UART_S2_RXINV_MASK 0x10u
mbed_official 324:406fd2029f23 8935 #define UART_S2_RXINV_SHIFT 4
mbed_official 324:406fd2029f23 8936 #define UART_S2_MSBF_MASK 0x20u
mbed_official 324:406fd2029f23 8937 #define UART_S2_MSBF_SHIFT 5
mbed_official 324:406fd2029f23 8938 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 324:406fd2029f23 8939 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 324:406fd2029f23 8940 #define UART_S2_LBKDIF_MASK 0x80u
mbed_official 324:406fd2029f23 8941 #define UART_S2_LBKDIF_SHIFT 7
mbed_official 324:406fd2029f23 8942 /* C3 Bit Fields */
mbed_official 324:406fd2029f23 8943 #define UART_C3_PEIE_MASK 0x1u
mbed_official 324:406fd2029f23 8944 #define UART_C3_PEIE_SHIFT 0
mbed_official 324:406fd2029f23 8945 #define UART_C3_FEIE_MASK 0x2u
mbed_official 324:406fd2029f23 8946 #define UART_C3_FEIE_SHIFT 1
mbed_official 324:406fd2029f23 8947 #define UART_C3_NEIE_MASK 0x4u
mbed_official 324:406fd2029f23 8948 #define UART_C3_NEIE_SHIFT 2
mbed_official 324:406fd2029f23 8949 #define UART_C3_ORIE_MASK 0x8u
mbed_official 324:406fd2029f23 8950 #define UART_C3_ORIE_SHIFT 3
mbed_official 324:406fd2029f23 8951 #define UART_C3_TXINV_MASK 0x10u
mbed_official 324:406fd2029f23 8952 #define UART_C3_TXINV_SHIFT 4
mbed_official 324:406fd2029f23 8953 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 324:406fd2029f23 8954 #define UART_C3_TXDIR_SHIFT 5
mbed_official 324:406fd2029f23 8955 #define UART_C3_T8_MASK 0x40u
mbed_official 324:406fd2029f23 8956 #define UART_C3_T8_SHIFT 6
mbed_official 324:406fd2029f23 8957 #define UART_C3_R8_MASK 0x80u
mbed_official 324:406fd2029f23 8958 #define UART_C3_R8_SHIFT 7
mbed_official 324:406fd2029f23 8959 /* D Bit Fields */
mbed_official 324:406fd2029f23 8960 #define UART_D_RT_MASK 0xFFu
mbed_official 324:406fd2029f23 8961 #define UART_D_RT_SHIFT 0
mbed_official 324:406fd2029f23 8962 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
mbed_official 324:406fd2029f23 8963 /* MA1 Bit Fields */
mbed_official 324:406fd2029f23 8964 #define UART_MA1_MA_MASK 0xFFu
mbed_official 324:406fd2029f23 8965 #define UART_MA1_MA_SHIFT 0
mbed_official 324:406fd2029f23 8966 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
mbed_official 324:406fd2029f23 8967 /* MA2 Bit Fields */
mbed_official 324:406fd2029f23 8968 #define UART_MA2_MA_MASK 0xFFu
mbed_official 324:406fd2029f23 8969 #define UART_MA2_MA_SHIFT 0
mbed_official 324:406fd2029f23 8970 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
mbed_official 324:406fd2029f23 8971 /* C4 Bit Fields */
mbed_official 324:406fd2029f23 8972 #define UART_C4_BRFA_MASK 0x1Fu
mbed_official 324:406fd2029f23 8973 #define UART_C4_BRFA_SHIFT 0
mbed_official 324:406fd2029f23 8974 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
mbed_official 324:406fd2029f23 8975 #define UART_C4_M10_MASK 0x20u
mbed_official 324:406fd2029f23 8976 #define UART_C4_M10_SHIFT 5
mbed_official 324:406fd2029f23 8977 #define UART_C4_MAEN2_MASK 0x40u
mbed_official 324:406fd2029f23 8978 #define UART_C4_MAEN2_SHIFT 6
mbed_official 324:406fd2029f23 8979 #define UART_C4_MAEN1_MASK 0x80u
mbed_official 324:406fd2029f23 8980 #define UART_C4_MAEN1_SHIFT 7
mbed_official 324:406fd2029f23 8981 /* C5 Bit Fields */
mbed_official 324:406fd2029f23 8982 #define UART_C5_RDMAS_MASK 0x20u
mbed_official 324:406fd2029f23 8983 #define UART_C5_RDMAS_SHIFT 5
mbed_official 324:406fd2029f23 8984 #define UART_C5_TDMAS_MASK 0x80u
mbed_official 324:406fd2029f23 8985 #define UART_C5_TDMAS_SHIFT 7
mbed_official 324:406fd2029f23 8986 /* ED Bit Fields */
mbed_official 324:406fd2029f23 8987 #define UART_ED_PARITYE_MASK 0x40u
mbed_official 324:406fd2029f23 8988 #define UART_ED_PARITYE_SHIFT 6
mbed_official 324:406fd2029f23 8989 #define UART_ED_NOISY_MASK 0x80u
mbed_official 324:406fd2029f23 8990 #define UART_ED_NOISY_SHIFT 7
mbed_official 324:406fd2029f23 8991 /* MODEM Bit Fields */
mbed_official 324:406fd2029f23 8992 #define UART_MODEM_TXCTSE_MASK 0x1u
mbed_official 324:406fd2029f23 8993 #define UART_MODEM_TXCTSE_SHIFT 0
mbed_official 324:406fd2029f23 8994 #define UART_MODEM_TXRTSE_MASK 0x2u
mbed_official 324:406fd2029f23 8995 #define UART_MODEM_TXRTSE_SHIFT 1
mbed_official 324:406fd2029f23 8996 #define UART_MODEM_TXRTSPOL_MASK 0x4u
mbed_official 324:406fd2029f23 8997 #define UART_MODEM_TXRTSPOL_SHIFT 2
mbed_official 324:406fd2029f23 8998 #define UART_MODEM_RXRTSE_MASK 0x8u
mbed_official 324:406fd2029f23 8999 #define UART_MODEM_RXRTSE_SHIFT 3
mbed_official 324:406fd2029f23 9000 /* IR Bit Fields */
mbed_official 324:406fd2029f23 9001 #define UART_IR_TNP_MASK 0x3u
mbed_official 324:406fd2029f23 9002 #define UART_IR_TNP_SHIFT 0
mbed_official 324:406fd2029f23 9003 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
mbed_official 324:406fd2029f23 9004 #define UART_IR_IREN_MASK 0x4u
mbed_official 324:406fd2029f23 9005 #define UART_IR_IREN_SHIFT 2
mbed_official 324:406fd2029f23 9006 /* PFIFO Bit Fields */
mbed_official 324:406fd2029f23 9007 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
mbed_official 324:406fd2029f23 9008 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
mbed_official 324:406fd2029f23 9009 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
mbed_official 324:406fd2029f23 9010 #define UART_PFIFO_RXFE_MASK 0x8u
mbed_official 324:406fd2029f23 9011 #define UART_PFIFO_RXFE_SHIFT 3
mbed_official 324:406fd2029f23 9012 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
mbed_official 324:406fd2029f23 9013 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
mbed_official 324:406fd2029f23 9014 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
mbed_official 324:406fd2029f23 9015 #define UART_PFIFO_TXFE_MASK 0x80u
mbed_official 324:406fd2029f23 9016 #define UART_PFIFO_TXFE_SHIFT 7
mbed_official 324:406fd2029f23 9017 /* CFIFO Bit Fields */
mbed_official 324:406fd2029f23 9018 #define UART_CFIFO_RXUFE_MASK 0x1u
mbed_official 324:406fd2029f23 9019 #define UART_CFIFO_RXUFE_SHIFT 0
mbed_official 324:406fd2029f23 9020 #define UART_CFIFO_TXOFE_MASK 0x2u
mbed_official 324:406fd2029f23 9021 #define UART_CFIFO_TXOFE_SHIFT 1
mbed_official 324:406fd2029f23 9022 #define UART_CFIFO_RXOFE_MASK 0x4u
mbed_official 324:406fd2029f23 9023 #define UART_CFIFO_RXOFE_SHIFT 2
mbed_official 324:406fd2029f23 9024 #define UART_CFIFO_RXFLUSH_MASK 0x40u
mbed_official 324:406fd2029f23 9025 #define UART_CFIFO_RXFLUSH_SHIFT 6
mbed_official 324:406fd2029f23 9026 #define UART_CFIFO_TXFLUSH_MASK 0x80u
mbed_official 324:406fd2029f23 9027 #define UART_CFIFO_TXFLUSH_SHIFT 7
mbed_official 324:406fd2029f23 9028 /* SFIFO Bit Fields */
mbed_official 324:406fd2029f23 9029 #define UART_SFIFO_RXUF_MASK 0x1u
mbed_official 324:406fd2029f23 9030 #define UART_SFIFO_RXUF_SHIFT 0
mbed_official 324:406fd2029f23 9031 #define UART_SFIFO_TXOF_MASK 0x2u
mbed_official 324:406fd2029f23 9032 #define UART_SFIFO_TXOF_SHIFT 1
mbed_official 324:406fd2029f23 9033 #define UART_SFIFO_RXOF_MASK 0x4u
mbed_official 324:406fd2029f23 9034 #define UART_SFIFO_RXOF_SHIFT 2
mbed_official 324:406fd2029f23 9035 #define UART_SFIFO_RXEMPT_MASK 0x40u
mbed_official 324:406fd2029f23 9036 #define UART_SFIFO_RXEMPT_SHIFT 6
mbed_official 324:406fd2029f23 9037 #define UART_SFIFO_TXEMPT_MASK 0x80u
mbed_official 324:406fd2029f23 9038 #define UART_SFIFO_TXEMPT_SHIFT 7
mbed_official 324:406fd2029f23 9039 /* TWFIFO Bit Fields */
mbed_official 324:406fd2029f23 9040 #define UART_TWFIFO_TXWATER_MASK 0xFFu
mbed_official 324:406fd2029f23 9041 #define UART_TWFIFO_TXWATER_SHIFT 0
mbed_official 324:406fd2029f23 9042 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
mbed_official 324:406fd2029f23 9043 /* TCFIFO Bit Fields */
mbed_official 324:406fd2029f23 9044 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
mbed_official 324:406fd2029f23 9045 #define UART_TCFIFO_TXCOUNT_SHIFT 0
mbed_official 324:406fd2029f23 9046 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
mbed_official 324:406fd2029f23 9047 /* RWFIFO Bit Fields */
mbed_official 324:406fd2029f23 9048 #define UART_RWFIFO_RXWATER_MASK 0xFFu
mbed_official 324:406fd2029f23 9049 #define UART_RWFIFO_RXWATER_SHIFT 0
mbed_official 324:406fd2029f23 9050 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
mbed_official 324:406fd2029f23 9051 /* RCFIFO Bit Fields */
mbed_official 324:406fd2029f23 9052 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
mbed_official 324:406fd2029f23 9053 #define UART_RCFIFO_RXCOUNT_SHIFT 0
mbed_official 324:406fd2029f23 9054 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
mbed_official 324:406fd2029f23 9055 /* C7816 Bit Fields */
mbed_official 324:406fd2029f23 9056 #define UART_C7816_ISO_7816E_MASK 0x1u
mbed_official 324:406fd2029f23 9057 #define UART_C7816_ISO_7816E_SHIFT 0
mbed_official 324:406fd2029f23 9058 #define UART_C7816_TTYPE_MASK 0x2u
mbed_official 324:406fd2029f23 9059 #define UART_C7816_TTYPE_SHIFT 1
mbed_official 324:406fd2029f23 9060 #define UART_C7816_INIT_MASK 0x4u
mbed_official 324:406fd2029f23 9061 #define UART_C7816_INIT_SHIFT 2
mbed_official 324:406fd2029f23 9062 #define UART_C7816_ANACK_MASK 0x8u
mbed_official 324:406fd2029f23 9063 #define UART_C7816_ANACK_SHIFT 3
mbed_official 324:406fd2029f23 9064 #define UART_C7816_ONACK_MASK 0x10u
mbed_official 324:406fd2029f23 9065 #define UART_C7816_ONACK_SHIFT 4
mbed_official 324:406fd2029f23 9066 /* IE7816 Bit Fields */
mbed_official 324:406fd2029f23 9067 #define UART_IE7816_RXTE_MASK 0x1u
mbed_official 324:406fd2029f23 9068 #define UART_IE7816_RXTE_SHIFT 0
mbed_official 324:406fd2029f23 9069 #define UART_IE7816_TXTE_MASK 0x2u
mbed_official 324:406fd2029f23 9070 #define UART_IE7816_TXTE_SHIFT 1
mbed_official 324:406fd2029f23 9071 #define UART_IE7816_GTVE_MASK 0x4u
mbed_official 324:406fd2029f23 9072 #define UART_IE7816_GTVE_SHIFT 2
mbed_official 324:406fd2029f23 9073 #define UART_IE7816_ADTE_MASK 0x8u
mbed_official 324:406fd2029f23 9074 #define UART_IE7816_ADTE_SHIFT 3
mbed_official 324:406fd2029f23 9075 #define UART_IE7816_INITDE_MASK 0x10u
mbed_official 324:406fd2029f23 9076 #define UART_IE7816_INITDE_SHIFT 4
mbed_official 324:406fd2029f23 9077 #define UART_IE7816_BWTE_MASK 0x20u
mbed_official 324:406fd2029f23 9078 #define UART_IE7816_BWTE_SHIFT 5
mbed_official 324:406fd2029f23 9079 #define UART_IE7816_CWTE_MASK 0x40u
mbed_official 324:406fd2029f23 9080 #define UART_IE7816_CWTE_SHIFT 6
mbed_official 324:406fd2029f23 9081 #define UART_IE7816_WTE_MASK 0x80u
mbed_official 324:406fd2029f23 9082 #define UART_IE7816_WTE_SHIFT 7
mbed_official 324:406fd2029f23 9083 /* IS7816 Bit Fields */
mbed_official 324:406fd2029f23 9084 #define UART_IS7816_RXT_MASK 0x1u
mbed_official 324:406fd2029f23 9085 #define UART_IS7816_RXT_SHIFT 0
mbed_official 324:406fd2029f23 9086 #define UART_IS7816_TXT_MASK 0x2u
mbed_official 324:406fd2029f23 9087 #define UART_IS7816_TXT_SHIFT 1
mbed_official 324:406fd2029f23 9088 #define UART_IS7816_GTV_MASK 0x4u
mbed_official 324:406fd2029f23 9089 #define UART_IS7816_GTV_SHIFT 2
mbed_official 324:406fd2029f23 9090 #define UART_IS7816_ADT_MASK 0x8u
mbed_official 324:406fd2029f23 9091 #define UART_IS7816_ADT_SHIFT 3
mbed_official 324:406fd2029f23 9092 #define UART_IS7816_INITD_MASK 0x10u
mbed_official 324:406fd2029f23 9093 #define UART_IS7816_INITD_SHIFT 4
mbed_official 324:406fd2029f23 9094 #define UART_IS7816_BWT_MASK 0x20u
mbed_official 324:406fd2029f23 9095 #define UART_IS7816_BWT_SHIFT 5
mbed_official 324:406fd2029f23 9096 #define UART_IS7816_CWT_MASK 0x40u
mbed_official 324:406fd2029f23 9097 #define UART_IS7816_CWT_SHIFT 6
mbed_official 324:406fd2029f23 9098 #define UART_IS7816_WT_MASK 0x80u
mbed_official 324:406fd2029f23 9099 #define UART_IS7816_WT_SHIFT 7
mbed_official 324:406fd2029f23 9100 /* WP7816 Bit Fields */
mbed_official 324:406fd2029f23 9101 #define UART_WP7816_WTX_MASK 0xFFu
mbed_official 324:406fd2029f23 9102 #define UART_WP7816_WTX_SHIFT 0
mbed_official 324:406fd2029f23 9103 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
mbed_official 324:406fd2029f23 9104 /* WN7816 Bit Fields */
mbed_official 324:406fd2029f23 9105 #define UART_WN7816_GTN_MASK 0xFFu
mbed_official 324:406fd2029f23 9106 #define UART_WN7816_GTN_SHIFT 0
mbed_official 324:406fd2029f23 9107 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
mbed_official 324:406fd2029f23 9108 /* WF7816 Bit Fields */
mbed_official 324:406fd2029f23 9109 #define UART_WF7816_GTFD_MASK 0xFFu
mbed_official 324:406fd2029f23 9110 #define UART_WF7816_GTFD_SHIFT 0
mbed_official 324:406fd2029f23 9111 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
mbed_official 324:406fd2029f23 9112 /* ET7816 Bit Fields */
mbed_official 324:406fd2029f23 9113 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
mbed_official 324:406fd2029f23 9114 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
mbed_official 324:406fd2029f23 9115 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
mbed_official 324:406fd2029f23 9116 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
mbed_official 324:406fd2029f23 9117 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
mbed_official 324:406fd2029f23 9118 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
mbed_official 324:406fd2029f23 9119 /* TL7816 Bit Fields */
mbed_official 324:406fd2029f23 9120 #define UART_TL7816_TLEN_MASK 0xFFu
mbed_official 324:406fd2029f23 9121 #define UART_TL7816_TLEN_SHIFT 0
mbed_official 324:406fd2029f23 9122 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
mbed_official 324:406fd2029f23 9123 /* AP7816A_T0 Bit Fields */
mbed_official 324:406fd2029f23 9124 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
mbed_official 324:406fd2029f23 9125 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
mbed_official 324:406fd2029f23 9126 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
mbed_official 324:406fd2029f23 9127 /* AP7816B_T0 Bit Fields */
mbed_official 324:406fd2029f23 9128 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
mbed_official 324:406fd2029f23 9129 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
mbed_official 324:406fd2029f23 9130 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
mbed_official 324:406fd2029f23 9131 /* WP7816A_T0 Bit Fields */
mbed_official 324:406fd2029f23 9132 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
mbed_official 324:406fd2029f23 9133 #define UART_WP7816A_T0_WI_H_SHIFT 0
mbed_official 324:406fd2029f23 9134 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
mbed_official 324:406fd2029f23 9135 /* WP7816B_T0 Bit Fields */
mbed_official 324:406fd2029f23 9136 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
mbed_official 324:406fd2029f23 9137 #define UART_WP7816B_T0_WI_L_SHIFT 0
mbed_official 324:406fd2029f23 9138 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
mbed_official 324:406fd2029f23 9139 /* WP7816A_T1 Bit Fields */
mbed_official 324:406fd2029f23 9140 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
mbed_official 324:406fd2029f23 9141 #define UART_WP7816A_T1_BWI_H_SHIFT 0
mbed_official 324:406fd2029f23 9142 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
mbed_official 324:406fd2029f23 9143 /* WP7816B_T1 Bit Fields */
mbed_official 324:406fd2029f23 9144 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
mbed_official 324:406fd2029f23 9145 #define UART_WP7816B_T1_BWI_L_SHIFT 0
mbed_official 324:406fd2029f23 9146 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
mbed_official 324:406fd2029f23 9147 /* WGP7816_T1 Bit Fields */
mbed_official 324:406fd2029f23 9148 #define UART_WGP7816_T1_BGI_MASK 0xFu
mbed_official 324:406fd2029f23 9149 #define UART_WGP7816_T1_BGI_SHIFT 0
mbed_official 324:406fd2029f23 9150 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
mbed_official 324:406fd2029f23 9151 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
mbed_official 324:406fd2029f23 9152 #define UART_WGP7816_T1_CWI1_SHIFT 4
mbed_official 324:406fd2029f23 9153 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
mbed_official 324:406fd2029f23 9154 /* WP7816C_T1 Bit Fields */
mbed_official 324:406fd2029f23 9155 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
mbed_official 324:406fd2029f23 9156 #define UART_WP7816C_T1_CWI2_SHIFT 0
mbed_official 324:406fd2029f23 9157 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
mbed_official 324:406fd2029f23 9158
mbed_official 324:406fd2029f23 9159 /*!
mbed_official 324:406fd2029f23 9160 * @}
mbed_official 324:406fd2029f23 9161 */ /* end of group UART_Register_Masks */
mbed_official 324:406fd2029f23 9162
mbed_official 324:406fd2029f23 9163
mbed_official 324:406fd2029f23 9164 /* UART - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 9165 /** Peripheral UART0 base address */
mbed_official 324:406fd2029f23 9166 #define UART0_BASE (0x4006A000u)
mbed_official 324:406fd2029f23 9167 /** Peripheral UART0 base pointer */
mbed_official 324:406fd2029f23 9168 #define UART0 ((UART_Type *)UART0_BASE)
mbed_official 324:406fd2029f23 9169 #define UART0_BASE_PTR (UART0)
mbed_official 324:406fd2029f23 9170 /** Peripheral UART1 base address */
mbed_official 324:406fd2029f23 9171 #define UART1_BASE (0x4006B000u)
mbed_official 324:406fd2029f23 9172 /** Peripheral UART1 base pointer */
mbed_official 324:406fd2029f23 9173 #define UART1 ((UART_Type *)UART1_BASE)
mbed_official 324:406fd2029f23 9174 #define UART1_BASE_PTR (UART1)
mbed_official 324:406fd2029f23 9175 /** Peripheral UART2 base address */
mbed_official 324:406fd2029f23 9176 #define UART2_BASE (0x4006C000u)
mbed_official 324:406fd2029f23 9177 /** Peripheral UART2 base pointer */
mbed_official 324:406fd2029f23 9178 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 324:406fd2029f23 9179 #define UART2_BASE_PTR (UART2)
mbed_official 324:406fd2029f23 9180 /** Array initializer of UART peripheral base addresses */
mbed_official 324:406fd2029f23 9181 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
mbed_official 324:406fd2029f23 9182 /** Array initializer of UART peripheral base pointers */
mbed_official 324:406fd2029f23 9183 #define UART_BASE_PTRS { UART0, UART1, UART2 }
mbed_official 324:406fd2029f23 9184 /** Interrupt vectors for the UART peripheral type */
mbed_official 324:406fd2029f23 9185 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
mbed_official 324:406fd2029f23 9186 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
mbed_official 324:406fd2029f23 9187
mbed_official 324:406fd2029f23 9188 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9189 -- UART - Register accessor macros
mbed_official 324:406fd2029f23 9190 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9191
mbed_official 324:406fd2029f23 9192 /*!
mbed_official 324:406fd2029f23 9193 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 324:406fd2029f23 9194 * @{
mbed_official 324:406fd2029f23 9195 */
mbed_official 324:406fd2029f23 9196
mbed_official 324:406fd2029f23 9197
mbed_official 324:406fd2029f23 9198 /* UART - Register instance definitions */
mbed_official 324:406fd2029f23 9199 /* UART0 */
mbed_official 324:406fd2029f23 9200 #define UART0_BDH UART_BDH_REG(UART0)
mbed_official 324:406fd2029f23 9201 #define UART0_BDL UART_BDL_REG(UART0)
mbed_official 324:406fd2029f23 9202 #define UART0_C1 UART_C1_REG(UART0)
mbed_official 324:406fd2029f23 9203 #define UART0_C2 UART_C2_REG(UART0)
mbed_official 324:406fd2029f23 9204 #define UART0_S1 UART_S1_REG(UART0)
mbed_official 324:406fd2029f23 9205 #define UART0_S2 UART_S2_REG(UART0)
mbed_official 324:406fd2029f23 9206 #define UART0_C3 UART_C3_REG(UART0)
mbed_official 324:406fd2029f23 9207 #define UART0_D UART_D_REG(UART0)
mbed_official 324:406fd2029f23 9208 #define UART0_MA1 UART_MA1_REG(UART0)
mbed_official 324:406fd2029f23 9209 #define UART0_MA2 UART_MA2_REG(UART0)
mbed_official 324:406fd2029f23 9210 #define UART0_C4 UART_C4_REG(UART0)
mbed_official 324:406fd2029f23 9211 #define UART0_C5 UART_C5_REG(UART0)
mbed_official 324:406fd2029f23 9212 #define UART0_ED UART_ED_REG(UART0)
mbed_official 324:406fd2029f23 9213 #define UART0_MODEM UART_MODEM_REG(UART0)
mbed_official 324:406fd2029f23 9214 #define UART0_IR UART_IR_REG(UART0)
mbed_official 324:406fd2029f23 9215 #define UART0_PFIFO UART_PFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9216 #define UART0_CFIFO UART_CFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9217 #define UART0_SFIFO UART_SFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9218 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9219 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9220 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9221 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
mbed_official 324:406fd2029f23 9222 #define UART0_C7816 UART_C7816_REG(UART0)
mbed_official 324:406fd2029f23 9223 #define UART0_IE7816 UART_IE7816_REG(UART0)
mbed_official 324:406fd2029f23 9224 #define UART0_IS7816 UART_IS7816_REG(UART0)
mbed_official 324:406fd2029f23 9225 #define UART0_WP7816 UART_WP7816_REG(UART0)
mbed_official 324:406fd2029f23 9226 #define UART0_WN7816 UART_WN7816_REG(UART0)
mbed_official 324:406fd2029f23 9227 #define UART0_WF7816 UART_WF7816_REG(UART0)
mbed_official 324:406fd2029f23 9228 #define UART0_ET7816 UART_ET7816_REG(UART0)
mbed_official 324:406fd2029f23 9229 #define UART0_TL7816 UART_TL7816_REG(UART0)
mbed_official 324:406fd2029f23 9230 #define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
mbed_official 324:406fd2029f23 9231 #define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
mbed_official 324:406fd2029f23 9232 #define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
mbed_official 324:406fd2029f23 9233 #define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
mbed_official 324:406fd2029f23 9234 #define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
mbed_official 324:406fd2029f23 9235 #define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
mbed_official 324:406fd2029f23 9236 #define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
mbed_official 324:406fd2029f23 9237 #define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
mbed_official 324:406fd2029f23 9238 /* UART1 */
mbed_official 324:406fd2029f23 9239 #define UART1_BDH UART_BDH_REG(UART1)
mbed_official 324:406fd2029f23 9240 #define UART1_BDL UART_BDL_REG(UART1)
mbed_official 324:406fd2029f23 9241 #define UART1_C1 UART_C1_REG(UART1)
mbed_official 324:406fd2029f23 9242 #define UART1_C2 UART_C2_REG(UART1)
mbed_official 324:406fd2029f23 9243 #define UART1_S1 UART_S1_REG(UART1)
mbed_official 324:406fd2029f23 9244 #define UART1_S2 UART_S2_REG(UART1)
mbed_official 324:406fd2029f23 9245 #define UART1_C3 UART_C3_REG(UART1)
mbed_official 324:406fd2029f23 9246 #define UART1_D UART_D_REG(UART1)
mbed_official 324:406fd2029f23 9247 #define UART1_MA1 UART_MA1_REG(UART1)
mbed_official 324:406fd2029f23 9248 #define UART1_MA2 UART_MA2_REG(UART1)
mbed_official 324:406fd2029f23 9249 #define UART1_C4 UART_C4_REG(UART1)
mbed_official 324:406fd2029f23 9250 #define UART1_C5 UART_C5_REG(UART1)
mbed_official 324:406fd2029f23 9251 #define UART1_ED UART_ED_REG(UART1)
mbed_official 324:406fd2029f23 9252 #define UART1_MODEM UART_MODEM_REG(UART1)
mbed_official 324:406fd2029f23 9253 #define UART1_IR UART_IR_REG(UART1)
mbed_official 324:406fd2029f23 9254 #define UART1_PFIFO UART_PFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9255 #define UART1_CFIFO UART_CFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9256 #define UART1_SFIFO UART_SFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9257 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9258 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9259 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9260 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
mbed_official 324:406fd2029f23 9261 /* UART2 */
mbed_official 324:406fd2029f23 9262 #define UART2_BDH UART_BDH_REG(UART2)
mbed_official 324:406fd2029f23 9263 #define UART2_BDL UART_BDL_REG(UART2)
mbed_official 324:406fd2029f23 9264 #define UART2_C1 UART_C1_REG(UART2)
mbed_official 324:406fd2029f23 9265 #define UART2_C2 UART_C2_REG(UART2)
mbed_official 324:406fd2029f23 9266 #define UART2_S1 UART_S1_REG(UART2)
mbed_official 324:406fd2029f23 9267 #define UART2_S2 UART_S2_REG(UART2)
mbed_official 324:406fd2029f23 9268 #define UART2_C3 UART_C3_REG(UART2)
mbed_official 324:406fd2029f23 9269 #define UART2_D UART_D_REG(UART2)
mbed_official 324:406fd2029f23 9270 #define UART2_MA1 UART_MA1_REG(UART2)
mbed_official 324:406fd2029f23 9271 #define UART2_MA2 UART_MA2_REG(UART2)
mbed_official 324:406fd2029f23 9272 #define UART2_C4 UART_C4_REG(UART2)
mbed_official 324:406fd2029f23 9273 #define UART2_C5 UART_C5_REG(UART2)
mbed_official 324:406fd2029f23 9274 #define UART2_ED UART_ED_REG(UART2)
mbed_official 324:406fd2029f23 9275 #define UART2_MODEM UART_MODEM_REG(UART2)
mbed_official 324:406fd2029f23 9276 #define UART2_IR UART_IR_REG(UART2)
mbed_official 324:406fd2029f23 9277 #define UART2_PFIFO UART_PFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9278 #define UART2_CFIFO UART_CFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9279 #define UART2_SFIFO UART_SFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9280 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9281 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9282 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9283 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
mbed_official 324:406fd2029f23 9284
mbed_official 324:406fd2029f23 9285 /*!
mbed_official 324:406fd2029f23 9286 * @}
mbed_official 324:406fd2029f23 9287 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9288
mbed_official 324:406fd2029f23 9289
mbed_official 324:406fd2029f23 9290 /*!
mbed_official 324:406fd2029f23 9291 * @}
mbed_official 324:406fd2029f23 9292 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 9293
mbed_official 324:406fd2029f23 9294
mbed_official 324:406fd2029f23 9295 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9296 -- USB Peripheral Access Layer
mbed_official 324:406fd2029f23 9297 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9298
mbed_official 324:406fd2029f23 9299 /*!
mbed_official 324:406fd2029f23 9300 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 324:406fd2029f23 9301 * @{
mbed_official 324:406fd2029f23 9302 */
mbed_official 324:406fd2029f23 9303
mbed_official 324:406fd2029f23 9304 /** USB - Register Layout Typedef */
mbed_official 324:406fd2029f23 9305 typedef struct {
mbed_official 324:406fd2029f23 9306 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 324:406fd2029f23 9307 uint8_t RESERVED_0[3];
mbed_official 324:406fd2029f23 9308 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 324:406fd2029f23 9309 uint8_t RESERVED_1[3];
mbed_official 324:406fd2029f23 9310 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 324:406fd2029f23 9311 uint8_t RESERVED_2[3];
mbed_official 324:406fd2029f23 9312 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 324:406fd2029f23 9313 uint8_t RESERVED_3[3];
mbed_official 324:406fd2029f23 9314 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
mbed_official 324:406fd2029f23 9315 uint8_t RESERVED_4[3];
mbed_official 324:406fd2029f23 9316 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
mbed_official 324:406fd2029f23 9317 uint8_t RESERVED_5[3];
mbed_official 324:406fd2029f23 9318 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
mbed_official 324:406fd2029f23 9319 uint8_t RESERVED_6[3];
mbed_official 324:406fd2029f23 9320 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 324:406fd2029f23 9321 uint8_t RESERVED_7[99];
mbed_official 324:406fd2029f23 9322 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 324:406fd2029f23 9323 uint8_t RESERVED_8[3];
mbed_official 324:406fd2029f23 9324 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 324:406fd2029f23 9325 uint8_t RESERVED_9[3];
mbed_official 324:406fd2029f23 9326 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 324:406fd2029f23 9327 uint8_t RESERVED_10[3];
mbed_official 324:406fd2029f23 9328 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 324:406fd2029f23 9329 uint8_t RESERVED_11[3];
mbed_official 324:406fd2029f23 9330 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 324:406fd2029f23 9331 uint8_t RESERVED_12[3];
mbed_official 324:406fd2029f23 9332 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 324:406fd2029f23 9333 uint8_t RESERVED_13[3];
mbed_official 324:406fd2029f23 9334 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 324:406fd2029f23 9335 uint8_t RESERVED_14[3];
mbed_official 324:406fd2029f23 9336 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
mbed_official 324:406fd2029f23 9337 uint8_t RESERVED_15[3];
mbed_official 324:406fd2029f23 9338 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
mbed_official 324:406fd2029f23 9339 uint8_t RESERVED_16[3];
mbed_official 324:406fd2029f23 9340 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
mbed_official 324:406fd2029f23 9341 uint8_t RESERVED_17[3];
mbed_official 324:406fd2029f23 9342 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
mbed_official 324:406fd2029f23 9343 uint8_t RESERVED_18[3];
mbed_official 324:406fd2029f23 9344 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
mbed_official 324:406fd2029f23 9345 uint8_t RESERVED_19[3];
mbed_official 324:406fd2029f23 9346 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 324:406fd2029f23 9347 uint8_t RESERVED_20[3];
mbed_official 324:406fd2029f23 9348 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 324:406fd2029f23 9349 uint8_t RESERVED_21[11];
mbed_official 324:406fd2029f23 9350 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 324:406fd2029f23 9351 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 324:406fd2029f23 9352 uint8_t RESERVED_0[3];
mbed_official 324:406fd2029f23 9353 } ENDPOINT[16];
mbed_official 324:406fd2029f23 9354 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 324:406fd2029f23 9355 uint8_t RESERVED_22[3];
mbed_official 324:406fd2029f23 9356 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 324:406fd2029f23 9357 uint8_t RESERVED_23[3];
mbed_official 324:406fd2029f23 9358 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 324:406fd2029f23 9359 uint8_t RESERVED_24[3];
mbed_official 324:406fd2029f23 9360 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
mbed_official 324:406fd2029f23 9361 uint8_t RESERVED_25[7];
mbed_official 324:406fd2029f23 9362 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 324:406fd2029f23 9363 uint8_t RESERVED_26[43];
mbed_official 324:406fd2029f23 9364 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
mbed_official 324:406fd2029f23 9365 uint8_t RESERVED_27[3];
mbed_official 324:406fd2029f23 9366 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
mbed_official 324:406fd2029f23 9367 uint8_t RESERVED_28[23];
mbed_official 324:406fd2029f23 9368 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
mbed_official 324:406fd2029f23 9369 } USB_Type, *USB_MemMapPtr;
mbed_official 324:406fd2029f23 9370
mbed_official 324:406fd2029f23 9371 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9372 -- USB - Register accessor macros
mbed_official 324:406fd2029f23 9373 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9374
mbed_official 324:406fd2029f23 9375 /*!
mbed_official 324:406fd2029f23 9376 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 324:406fd2029f23 9377 * @{
mbed_official 324:406fd2029f23 9378 */
mbed_official 324:406fd2029f23 9379
mbed_official 324:406fd2029f23 9380
mbed_official 324:406fd2029f23 9381 /* USB - Register accessors */
mbed_official 324:406fd2029f23 9382 #define USB_PERID_REG(base) ((base)->PERID)
mbed_official 324:406fd2029f23 9383 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
mbed_official 324:406fd2029f23 9384 #define USB_REV_REG(base) ((base)->REV)
mbed_official 324:406fd2029f23 9385 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
mbed_official 324:406fd2029f23 9386 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
mbed_official 324:406fd2029f23 9387 #define USB_OTGICR_REG(base) ((base)->OTGICR)
mbed_official 324:406fd2029f23 9388 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
mbed_official 324:406fd2029f23 9389 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
mbed_official 324:406fd2029f23 9390 #define USB_ISTAT_REG(base) ((base)->ISTAT)
mbed_official 324:406fd2029f23 9391 #define USB_INTEN_REG(base) ((base)->INTEN)
mbed_official 324:406fd2029f23 9392 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
mbed_official 324:406fd2029f23 9393 #define USB_ERREN_REG(base) ((base)->ERREN)
mbed_official 324:406fd2029f23 9394 #define USB_STAT_REG(base) ((base)->STAT)
mbed_official 324:406fd2029f23 9395 #define USB_CTL_REG(base) ((base)->CTL)
mbed_official 324:406fd2029f23 9396 #define USB_ADDR_REG(base) ((base)->ADDR)
mbed_official 324:406fd2029f23 9397 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
mbed_official 324:406fd2029f23 9398 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
mbed_official 324:406fd2029f23 9399 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
mbed_official 324:406fd2029f23 9400 #define USB_TOKEN_REG(base) ((base)->TOKEN)
mbed_official 324:406fd2029f23 9401 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
mbed_official 324:406fd2029f23 9402 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
mbed_official 324:406fd2029f23 9403 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
mbed_official 324:406fd2029f23 9404 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
mbed_official 324:406fd2029f23 9405 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
mbed_official 324:406fd2029f23 9406 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
mbed_official 324:406fd2029f23 9407 #define USB_CONTROL_REG(base) ((base)->CONTROL)
mbed_official 324:406fd2029f23 9408 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
mbed_official 324:406fd2029f23 9409 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
mbed_official 324:406fd2029f23 9410 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
mbed_official 324:406fd2029f23 9411 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
mbed_official 324:406fd2029f23 9412 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
mbed_official 324:406fd2029f23 9413
mbed_official 324:406fd2029f23 9414 /*!
mbed_official 324:406fd2029f23 9415 * @}
mbed_official 324:406fd2029f23 9416 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9417
mbed_official 324:406fd2029f23 9418
mbed_official 324:406fd2029f23 9419 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9420 -- USB Register Masks
mbed_official 324:406fd2029f23 9421 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9422
mbed_official 324:406fd2029f23 9423 /*!
mbed_official 324:406fd2029f23 9424 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 324:406fd2029f23 9425 * @{
mbed_official 324:406fd2029f23 9426 */
mbed_official 324:406fd2029f23 9427
mbed_official 324:406fd2029f23 9428 /* PERID Bit Fields */
mbed_official 324:406fd2029f23 9429 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 324:406fd2029f23 9430 #define USB_PERID_ID_SHIFT 0
mbed_official 324:406fd2029f23 9431 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 324:406fd2029f23 9432 /* IDCOMP Bit Fields */
mbed_official 324:406fd2029f23 9433 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 324:406fd2029f23 9434 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 324:406fd2029f23 9435 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 324:406fd2029f23 9436 /* REV Bit Fields */
mbed_official 324:406fd2029f23 9437 #define USB_REV_REV_MASK 0xFFu
mbed_official 324:406fd2029f23 9438 #define USB_REV_REV_SHIFT 0
mbed_official 324:406fd2029f23 9439 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 324:406fd2029f23 9440 /* ADDINFO Bit Fields */
mbed_official 324:406fd2029f23 9441 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 324:406fd2029f23 9442 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 324:406fd2029f23 9443 /* OTGISTAT Bit Fields */
mbed_official 324:406fd2029f23 9444 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
mbed_official 324:406fd2029f23 9445 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
mbed_official 324:406fd2029f23 9446 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
mbed_official 324:406fd2029f23 9447 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
mbed_official 324:406fd2029f23 9448 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
mbed_official 324:406fd2029f23 9449 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
mbed_official 324:406fd2029f23 9450 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
mbed_official 324:406fd2029f23 9451 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
mbed_official 324:406fd2029f23 9452 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
mbed_official 324:406fd2029f23 9453 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
mbed_official 324:406fd2029f23 9454 #define USB_OTGISTAT_IDCHG_MASK 0x80u
mbed_official 324:406fd2029f23 9455 #define USB_OTGISTAT_IDCHG_SHIFT 7
mbed_official 324:406fd2029f23 9456 /* OTGICR Bit Fields */
mbed_official 324:406fd2029f23 9457 #define USB_OTGICR_AVBUSEN_MASK 0x1u
mbed_official 324:406fd2029f23 9458 #define USB_OTGICR_AVBUSEN_SHIFT 0
mbed_official 324:406fd2029f23 9459 #define USB_OTGICR_BSESSEN_MASK 0x4u
mbed_official 324:406fd2029f23 9460 #define USB_OTGICR_BSESSEN_SHIFT 2
mbed_official 324:406fd2029f23 9461 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
mbed_official 324:406fd2029f23 9462 #define USB_OTGICR_SESSVLDEN_SHIFT 3
mbed_official 324:406fd2029f23 9463 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
mbed_official 324:406fd2029f23 9464 #define USB_OTGICR_LINESTATEEN_SHIFT 5
mbed_official 324:406fd2029f23 9465 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
mbed_official 324:406fd2029f23 9466 #define USB_OTGICR_ONEMSECEN_SHIFT 6
mbed_official 324:406fd2029f23 9467 #define USB_OTGICR_IDEN_MASK 0x80u
mbed_official 324:406fd2029f23 9468 #define USB_OTGICR_IDEN_SHIFT 7
mbed_official 324:406fd2029f23 9469 /* OTGSTAT Bit Fields */
mbed_official 324:406fd2029f23 9470 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
mbed_official 324:406fd2029f23 9471 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
mbed_official 324:406fd2029f23 9472 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
mbed_official 324:406fd2029f23 9473 #define USB_OTGSTAT_BSESSEND_SHIFT 2
mbed_official 324:406fd2029f23 9474 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
mbed_official 324:406fd2029f23 9475 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
mbed_official 324:406fd2029f23 9476 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
mbed_official 324:406fd2029f23 9477 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
mbed_official 324:406fd2029f23 9478 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
mbed_official 324:406fd2029f23 9479 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
mbed_official 324:406fd2029f23 9480 #define USB_OTGSTAT_ID_MASK 0x80u
mbed_official 324:406fd2029f23 9481 #define USB_OTGSTAT_ID_SHIFT 7
mbed_official 324:406fd2029f23 9482 /* OTGCTL Bit Fields */
mbed_official 324:406fd2029f23 9483 #define USB_OTGCTL_OTGEN_MASK 0x4u
mbed_official 324:406fd2029f23 9484 #define USB_OTGCTL_OTGEN_SHIFT 2
mbed_official 324:406fd2029f23 9485 #define USB_OTGCTL_DMLOW_MASK 0x10u
mbed_official 324:406fd2029f23 9486 #define USB_OTGCTL_DMLOW_SHIFT 4
mbed_official 324:406fd2029f23 9487 #define USB_OTGCTL_DPLOW_MASK 0x20u
mbed_official 324:406fd2029f23 9488 #define USB_OTGCTL_DPLOW_SHIFT 5
mbed_official 324:406fd2029f23 9489 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 324:406fd2029f23 9490 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 324:406fd2029f23 9491 /* ISTAT Bit Fields */
mbed_official 324:406fd2029f23 9492 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 324:406fd2029f23 9493 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 324:406fd2029f23 9494 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 324:406fd2029f23 9495 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 324:406fd2029f23 9496 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 324:406fd2029f23 9497 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 324:406fd2029f23 9498 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 324:406fd2029f23 9499 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 324:406fd2029f23 9500 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 324:406fd2029f23 9501 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 324:406fd2029f23 9502 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 324:406fd2029f23 9503 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 324:406fd2029f23 9504 #define USB_ISTAT_ATTACH_MASK 0x40u
mbed_official 324:406fd2029f23 9505 #define USB_ISTAT_ATTACH_SHIFT 6
mbed_official 324:406fd2029f23 9506 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 324:406fd2029f23 9507 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 324:406fd2029f23 9508 /* INTEN Bit Fields */
mbed_official 324:406fd2029f23 9509 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 324:406fd2029f23 9510 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 324:406fd2029f23 9511 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 324:406fd2029f23 9512 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 324:406fd2029f23 9513 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 324:406fd2029f23 9514 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 324:406fd2029f23 9515 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 324:406fd2029f23 9516 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 324:406fd2029f23 9517 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 324:406fd2029f23 9518 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 324:406fd2029f23 9519 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 324:406fd2029f23 9520 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 324:406fd2029f23 9521 #define USB_INTEN_ATTACHEN_MASK 0x40u
mbed_official 324:406fd2029f23 9522 #define USB_INTEN_ATTACHEN_SHIFT 6
mbed_official 324:406fd2029f23 9523 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 324:406fd2029f23 9524 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 324:406fd2029f23 9525 /* ERRSTAT Bit Fields */
mbed_official 324:406fd2029f23 9526 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 324:406fd2029f23 9527 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 324:406fd2029f23 9528 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
mbed_official 324:406fd2029f23 9529 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
mbed_official 324:406fd2029f23 9530 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 324:406fd2029f23 9531 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 324:406fd2029f23 9532 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 324:406fd2029f23 9533 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 324:406fd2029f23 9534 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 324:406fd2029f23 9535 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 324:406fd2029f23 9536 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 324:406fd2029f23 9537 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 324:406fd2029f23 9538 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 324:406fd2029f23 9539 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 324:406fd2029f23 9540 /* ERREN Bit Fields */
mbed_official 324:406fd2029f23 9541 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 324:406fd2029f23 9542 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 324:406fd2029f23 9543 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 324:406fd2029f23 9544 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 324:406fd2029f23 9545 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 324:406fd2029f23 9546 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 324:406fd2029f23 9547 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 324:406fd2029f23 9548 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 324:406fd2029f23 9549 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 324:406fd2029f23 9550 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 324:406fd2029f23 9551 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 324:406fd2029f23 9552 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 324:406fd2029f23 9553 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 324:406fd2029f23 9554 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 324:406fd2029f23 9555 /* STAT Bit Fields */
mbed_official 324:406fd2029f23 9556 #define USB_STAT_ODD_MASK 0x4u
mbed_official 324:406fd2029f23 9557 #define USB_STAT_ODD_SHIFT 2
mbed_official 324:406fd2029f23 9558 #define USB_STAT_TX_MASK 0x8u
mbed_official 324:406fd2029f23 9559 #define USB_STAT_TX_SHIFT 3
mbed_official 324:406fd2029f23 9560 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 324:406fd2029f23 9561 #define USB_STAT_ENDP_SHIFT 4
mbed_official 324:406fd2029f23 9562 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 324:406fd2029f23 9563 /* CTL Bit Fields */
mbed_official 324:406fd2029f23 9564 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 324:406fd2029f23 9565 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 324:406fd2029f23 9566 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 324:406fd2029f23 9567 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 324:406fd2029f23 9568 #define USB_CTL_RESUME_MASK 0x4u
mbed_official 324:406fd2029f23 9569 #define USB_CTL_RESUME_SHIFT 2
mbed_official 324:406fd2029f23 9570 #define USB_CTL_HOSTMODEEN_MASK 0x8u
mbed_official 324:406fd2029f23 9571 #define USB_CTL_HOSTMODEEN_SHIFT 3
mbed_official 324:406fd2029f23 9572 #define USB_CTL_RESET_MASK 0x10u
mbed_official 324:406fd2029f23 9573 #define USB_CTL_RESET_SHIFT 4
mbed_official 324:406fd2029f23 9574 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 324:406fd2029f23 9575 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 324:406fd2029f23 9576 #define USB_CTL_SE0_MASK 0x40u
mbed_official 324:406fd2029f23 9577 #define USB_CTL_SE0_SHIFT 6
mbed_official 324:406fd2029f23 9578 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 324:406fd2029f23 9579 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 324:406fd2029f23 9580 /* ADDR Bit Fields */
mbed_official 324:406fd2029f23 9581 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 324:406fd2029f23 9582 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 324:406fd2029f23 9583 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 324:406fd2029f23 9584 #define USB_ADDR_LSEN_MASK 0x80u
mbed_official 324:406fd2029f23 9585 #define USB_ADDR_LSEN_SHIFT 7
mbed_official 324:406fd2029f23 9586 /* BDTPAGE1 Bit Fields */
mbed_official 324:406fd2029f23 9587 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 324:406fd2029f23 9588 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 324:406fd2029f23 9589 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 324:406fd2029f23 9590 /* FRMNUML Bit Fields */
mbed_official 324:406fd2029f23 9591 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 324:406fd2029f23 9592 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 324:406fd2029f23 9593 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 324:406fd2029f23 9594 /* FRMNUMH Bit Fields */
mbed_official 324:406fd2029f23 9595 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 324:406fd2029f23 9596 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 324:406fd2029f23 9597 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 324:406fd2029f23 9598 /* TOKEN Bit Fields */
mbed_official 324:406fd2029f23 9599 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
mbed_official 324:406fd2029f23 9600 #define USB_TOKEN_TOKENENDPT_SHIFT 0
mbed_official 324:406fd2029f23 9601 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
mbed_official 324:406fd2029f23 9602 #define USB_TOKEN_TOKENPID_MASK 0xF0u
mbed_official 324:406fd2029f23 9603 #define USB_TOKEN_TOKENPID_SHIFT 4
mbed_official 324:406fd2029f23 9604 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
mbed_official 324:406fd2029f23 9605 /* SOFTHLD Bit Fields */
mbed_official 324:406fd2029f23 9606 #define USB_SOFTHLD_CNT_MASK 0xFFu
mbed_official 324:406fd2029f23 9607 #define USB_SOFTHLD_CNT_SHIFT 0
mbed_official 324:406fd2029f23 9608 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
mbed_official 324:406fd2029f23 9609 /* BDTPAGE2 Bit Fields */
mbed_official 324:406fd2029f23 9610 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 324:406fd2029f23 9611 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 324:406fd2029f23 9612 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 324:406fd2029f23 9613 /* BDTPAGE3 Bit Fields */
mbed_official 324:406fd2029f23 9614 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 324:406fd2029f23 9615 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 324:406fd2029f23 9616 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 324:406fd2029f23 9617 /* ENDPT Bit Fields */
mbed_official 324:406fd2029f23 9618 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 324:406fd2029f23 9619 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 324:406fd2029f23 9620 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 324:406fd2029f23 9621 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 324:406fd2029f23 9622 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 324:406fd2029f23 9623 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 324:406fd2029f23 9624 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 324:406fd2029f23 9625 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 324:406fd2029f23 9626 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 324:406fd2029f23 9627 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 324:406fd2029f23 9628 #define USB_ENDPT_RETRYDIS_MASK 0x40u
mbed_official 324:406fd2029f23 9629 #define USB_ENDPT_RETRYDIS_SHIFT 6
mbed_official 324:406fd2029f23 9630 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
mbed_official 324:406fd2029f23 9631 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
mbed_official 324:406fd2029f23 9632 /* USBCTRL Bit Fields */
mbed_official 324:406fd2029f23 9633 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 324:406fd2029f23 9634 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 324:406fd2029f23 9635 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 324:406fd2029f23 9636 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 324:406fd2029f23 9637 /* OBSERVE Bit Fields */
mbed_official 324:406fd2029f23 9638 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 324:406fd2029f23 9639 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 324:406fd2029f23 9640 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 324:406fd2029f23 9641 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 324:406fd2029f23 9642 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 324:406fd2029f23 9643 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 324:406fd2029f23 9644 /* CONTROL Bit Fields */
mbed_official 324:406fd2029f23 9645 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 324:406fd2029f23 9646 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 324:406fd2029f23 9647 /* USBTRC0 Bit Fields */
mbed_official 324:406fd2029f23 9648 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 324:406fd2029f23 9649 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 324:406fd2029f23 9650 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 324:406fd2029f23 9651 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 324:406fd2029f23 9652 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
mbed_official 324:406fd2029f23 9653 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
mbed_official 324:406fd2029f23 9654 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 324:406fd2029f23 9655 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 324:406fd2029f23 9656 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 324:406fd2029f23 9657 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 324:406fd2029f23 9658 /* USBFRMADJUST Bit Fields */
mbed_official 324:406fd2029f23 9659 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 324:406fd2029f23 9660 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 324:406fd2029f23 9661 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 324:406fd2029f23 9662 /* CLK_RECOVER_CTRL Bit Fields */
mbed_official 324:406fd2029f23 9663 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
mbed_official 324:406fd2029f23 9664 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
mbed_official 324:406fd2029f23 9665 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
mbed_official 324:406fd2029f23 9666 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
mbed_official 324:406fd2029f23 9667 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
mbed_official 324:406fd2029f23 9668 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
mbed_official 324:406fd2029f23 9669 /* CLK_RECOVER_IRC_EN Bit Fields */
mbed_official 324:406fd2029f23 9670 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
mbed_official 324:406fd2029f23 9671 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
mbed_official 324:406fd2029f23 9672 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
mbed_official 324:406fd2029f23 9673 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
mbed_official 324:406fd2029f23 9674 /* CLK_RECOVER_INT_STATUS Bit Fields */
mbed_official 324:406fd2029f23 9675 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
mbed_official 324:406fd2029f23 9676 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
mbed_official 324:406fd2029f23 9677
mbed_official 324:406fd2029f23 9678 /*!
mbed_official 324:406fd2029f23 9679 * @}
mbed_official 324:406fd2029f23 9680 */ /* end of group USB_Register_Masks */
mbed_official 324:406fd2029f23 9681
mbed_official 324:406fd2029f23 9682
mbed_official 324:406fd2029f23 9683 /* USB - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 9684 /** Peripheral USB0 base address */
mbed_official 324:406fd2029f23 9685 #define USB0_BASE (0x40072000u)
mbed_official 324:406fd2029f23 9686 /** Peripheral USB0 base pointer */
mbed_official 324:406fd2029f23 9687 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 324:406fd2029f23 9688 #define USB0_BASE_PTR (USB0)
mbed_official 324:406fd2029f23 9689 /** Array initializer of USB peripheral base addresses */
mbed_official 324:406fd2029f23 9690 #define USB_BASE_ADDRS { USB0_BASE }
mbed_official 324:406fd2029f23 9691 /** Array initializer of USB peripheral base pointers */
mbed_official 324:406fd2029f23 9692 #define USB_BASE_PTRS { USB0 }
mbed_official 324:406fd2029f23 9693 /** Interrupt vectors for the USB peripheral type */
mbed_official 324:406fd2029f23 9694 #define USB_IRQS { USB0_IRQn }
mbed_official 324:406fd2029f23 9695
mbed_official 324:406fd2029f23 9696 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9697 -- USB - Register accessor macros
mbed_official 324:406fd2029f23 9698 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9699
mbed_official 324:406fd2029f23 9700 /*!
mbed_official 324:406fd2029f23 9701 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 324:406fd2029f23 9702 * @{
mbed_official 324:406fd2029f23 9703 */
mbed_official 324:406fd2029f23 9704
mbed_official 324:406fd2029f23 9705
mbed_official 324:406fd2029f23 9706 /* USB - Register instance definitions */
mbed_official 324:406fd2029f23 9707 /* USB0 */
mbed_official 324:406fd2029f23 9708 #define USB0_PERID USB_PERID_REG(USB0)
mbed_official 324:406fd2029f23 9709 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
mbed_official 324:406fd2029f23 9710 #define USB0_REV USB_REV_REG(USB0)
mbed_official 324:406fd2029f23 9711 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
mbed_official 324:406fd2029f23 9712 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
mbed_official 324:406fd2029f23 9713 #define USB0_OTGICR USB_OTGICR_REG(USB0)
mbed_official 324:406fd2029f23 9714 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
mbed_official 324:406fd2029f23 9715 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
mbed_official 324:406fd2029f23 9716 #define USB0_ISTAT USB_ISTAT_REG(USB0)
mbed_official 324:406fd2029f23 9717 #define USB0_INTEN USB_INTEN_REG(USB0)
mbed_official 324:406fd2029f23 9718 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
mbed_official 324:406fd2029f23 9719 #define USB0_ERREN USB_ERREN_REG(USB0)
mbed_official 324:406fd2029f23 9720 #define USB0_STAT USB_STAT_REG(USB0)
mbed_official 324:406fd2029f23 9721 #define USB0_CTL USB_CTL_REG(USB0)
mbed_official 324:406fd2029f23 9722 #define USB0_ADDR USB_ADDR_REG(USB0)
mbed_official 324:406fd2029f23 9723 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
mbed_official 324:406fd2029f23 9724 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
mbed_official 324:406fd2029f23 9725 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
mbed_official 324:406fd2029f23 9726 #define USB0_TOKEN USB_TOKEN_REG(USB0)
mbed_official 324:406fd2029f23 9727 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
mbed_official 324:406fd2029f23 9728 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
mbed_official 324:406fd2029f23 9729 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
mbed_official 324:406fd2029f23 9730 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
mbed_official 324:406fd2029f23 9731 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
mbed_official 324:406fd2029f23 9732 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
mbed_official 324:406fd2029f23 9733 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
mbed_official 324:406fd2029f23 9734 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
mbed_official 324:406fd2029f23 9735 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
mbed_official 324:406fd2029f23 9736 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
mbed_official 324:406fd2029f23 9737 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
mbed_official 324:406fd2029f23 9738 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
mbed_official 324:406fd2029f23 9739 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
mbed_official 324:406fd2029f23 9740 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
mbed_official 324:406fd2029f23 9741 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
mbed_official 324:406fd2029f23 9742 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
mbed_official 324:406fd2029f23 9743 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
mbed_official 324:406fd2029f23 9744 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
mbed_official 324:406fd2029f23 9745 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
mbed_official 324:406fd2029f23 9746 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
mbed_official 324:406fd2029f23 9747 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
mbed_official 324:406fd2029f23 9748 #define USB0_CONTROL USB_CONTROL_REG(USB0)
mbed_official 324:406fd2029f23 9749 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
mbed_official 324:406fd2029f23 9750 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
mbed_official 324:406fd2029f23 9751 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
mbed_official 324:406fd2029f23 9752 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
mbed_official 324:406fd2029f23 9753 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
mbed_official 324:406fd2029f23 9754
mbed_official 324:406fd2029f23 9755 /* USB - Register array accessors */
mbed_official 324:406fd2029f23 9756 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
mbed_official 324:406fd2029f23 9757
mbed_official 324:406fd2029f23 9758 /*!
mbed_official 324:406fd2029f23 9759 * @}
mbed_official 324:406fd2029f23 9760 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9761
mbed_official 324:406fd2029f23 9762
mbed_official 324:406fd2029f23 9763 /*!
mbed_official 324:406fd2029f23 9764 * @}
mbed_official 324:406fd2029f23 9765 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 9766
mbed_official 324:406fd2029f23 9767
mbed_official 324:406fd2029f23 9768 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9769 -- VREF Peripheral Access Layer
mbed_official 324:406fd2029f23 9770 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9771
mbed_official 324:406fd2029f23 9772 /*!
mbed_official 324:406fd2029f23 9773 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
mbed_official 324:406fd2029f23 9774 * @{
mbed_official 324:406fd2029f23 9775 */
mbed_official 324:406fd2029f23 9776
mbed_official 324:406fd2029f23 9777 /** VREF - Register Layout Typedef */
mbed_official 324:406fd2029f23 9778 typedef struct {
mbed_official 324:406fd2029f23 9779 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
mbed_official 324:406fd2029f23 9780 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
mbed_official 324:406fd2029f23 9781 } VREF_Type, *VREF_MemMapPtr;
mbed_official 324:406fd2029f23 9782
mbed_official 324:406fd2029f23 9783 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9784 -- VREF - Register accessor macros
mbed_official 324:406fd2029f23 9785 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9786
mbed_official 324:406fd2029f23 9787 /*!
mbed_official 324:406fd2029f23 9788 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 324:406fd2029f23 9789 * @{
mbed_official 324:406fd2029f23 9790 */
mbed_official 324:406fd2029f23 9791
mbed_official 324:406fd2029f23 9792
mbed_official 324:406fd2029f23 9793 /* VREF - Register accessors */
mbed_official 324:406fd2029f23 9794 #define VREF_TRM_REG(base) ((base)->TRM)
mbed_official 324:406fd2029f23 9795 #define VREF_SC_REG(base) ((base)->SC)
mbed_official 324:406fd2029f23 9796
mbed_official 324:406fd2029f23 9797 /*!
mbed_official 324:406fd2029f23 9798 * @}
mbed_official 324:406fd2029f23 9799 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9800
mbed_official 324:406fd2029f23 9801
mbed_official 324:406fd2029f23 9802 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9803 -- VREF Register Masks
mbed_official 324:406fd2029f23 9804 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9805
mbed_official 324:406fd2029f23 9806 /*!
mbed_official 324:406fd2029f23 9807 * @addtogroup VREF_Register_Masks VREF Register Masks
mbed_official 324:406fd2029f23 9808 * @{
mbed_official 324:406fd2029f23 9809 */
mbed_official 324:406fd2029f23 9810
mbed_official 324:406fd2029f23 9811 /* TRM Bit Fields */
mbed_official 324:406fd2029f23 9812 #define VREF_TRM_TRIM_MASK 0x3Fu
mbed_official 324:406fd2029f23 9813 #define VREF_TRM_TRIM_SHIFT 0
mbed_official 324:406fd2029f23 9814 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
mbed_official 324:406fd2029f23 9815 #define VREF_TRM_CHOPEN_MASK 0x40u
mbed_official 324:406fd2029f23 9816 #define VREF_TRM_CHOPEN_SHIFT 6
mbed_official 324:406fd2029f23 9817 /* SC Bit Fields */
mbed_official 324:406fd2029f23 9818 #define VREF_SC_MODE_LV_MASK 0x3u
mbed_official 324:406fd2029f23 9819 #define VREF_SC_MODE_LV_SHIFT 0
mbed_official 324:406fd2029f23 9820 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
mbed_official 324:406fd2029f23 9821 #define VREF_SC_VREFST_MASK 0x4u
mbed_official 324:406fd2029f23 9822 #define VREF_SC_VREFST_SHIFT 2
mbed_official 324:406fd2029f23 9823 #define VREF_SC_ICOMPEN_MASK 0x20u
mbed_official 324:406fd2029f23 9824 #define VREF_SC_ICOMPEN_SHIFT 5
mbed_official 324:406fd2029f23 9825 #define VREF_SC_REGEN_MASK 0x40u
mbed_official 324:406fd2029f23 9826 #define VREF_SC_REGEN_SHIFT 6
mbed_official 324:406fd2029f23 9827 #define VREF_SC_VREFEN_MASK 0x80u
mbed_official 324:406fd2029f23 9828 #define VREF_SC_VREFEN_SHIFT 7
mbed_official 324:406fd2029f23 9829
mbed_official 324:406fd2029f23 9830 /*!
mbed_official 324:406fd2029f23 9831 * @}
mbed_official 324:406fd2029f23 9832 */ /* end of group VREF_Register_Masks */
mbed_official 324:406fd2029f23 9833
mbed_official 324:406fd2029f23 9834
mbed_official 324:406fd2029f23 9835 /* VREF - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 9836 /** Peripheral VREF base address */
mbed_official 324:406fd2029f23 9837 #define VREF_BASE (0x40074000u)
mbed_official 324:406fd2029f23 9838 /** Peripheral VREF base pointer */
mbed_official 324:406fd2029f23 9839 #define VREF ((VREF_Type *)VREF_BASE)
mbed_official 324:406fd2029f23 9840 #define VREF_BASE_PTR (VREF)
mbed_official 324:406fd2029f23 9841 /** Array initializer of VREF peripheral base addresses */
mbed_official 324:406fd2029f23 9842 #define VREF_BASE_ADDRS { VREF_BASE }
mbed_official 324:406fd2029f23 9843 /** Array initializer of VREF peripheral base pointers */
mbed_official 324:406fd2029f23 9844 #define VREF_BASE_PTRS { VREF }
mbed_official 324:406fd2029f23 9845
mbed_official 324:406fd2029f23 9846 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9847 -- VREF - Register accessor macros
mbed_official 324:406fd2029f23 9848 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9849
mbed_official 324:406fd2029f23 9850 /*!
mbed_official 324:406fd2029f23 9851 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 324:406fd2029f23 9852 * @{
mbed_official 324:406fd2029f23 9853 */
mbed_official 324:406fd2029f23 9854
mbed_official 324:406fd2029f23 9855
mbed_official 324:406fd2029f23 9856 /* VREF - Register instance definitions */
mbed_official 324:406fd2029f23 9857 /* VREF */
mbed_official 324:406fd2029f23 9858 #define VREF_TRM VREF_TRM_REG(VREF)
mbed_official 324:406fd2029f23 9859 #define VREF_SC VREF_SC_REG(VREF)
mbed_official 324:406fd2029f23 9860
mbed_official 324:406fd2029f23 9861 /*!
mbed_official 324:406fd2029f23 9862 * @}
mbed_official 324:406fd2029f23 9863 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9864
mbed_official 324:406fd2029f23 9865
mbed_official 324:406fd2029f23 9866 /*!
mbed_official 324:406fd2029f23 9867 * @}
mbed_official 324:406fd2029f23 9868 */ /* end of group VREF_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 9869
mbed_official 324:406fd2029f23 9870
mbed_official 324:406fd2029f23 9871 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9872 -- WDOG Peripheral Access Layer
mbed_official 324:406fd2029f23 9873 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9874
mbed_official 324:406fd2029f23 9875 /*!
mbed_official 324:406fd2029f23 9876 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
mbed_official 324:406fd2029f23 9877 * @{
mbed_official 324:406fd2029f23 9878 */
mbed_official 324:406fd2029f23 9879
mbed_official 324:406fd2029f23 9880 /** WDOG - Register Layout Typedef */
mbed_official 324:406fd2029f23 9881 typedef struct {
mbed_official 324:406fd2029f23 9882 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
mbed_official 324:406fd2029f23 9883 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
mbed_official 324:406fd2029f23 9884 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
mbed_official 324:406fd2029f23 9885 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
mbed_official 324:406fd2029f23 9886 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
mbed_official 324:406fd2029f23 9887 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
mbed_official 324:406fd2029f23 9888 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
mbed_official 324:406fd2029f23 9889 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
mbed_official 324:406fd2029f23 9890 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
mbed_official 324:406fd2029f23 9891 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
mbed_official 324:406fd2029f23 9892 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
mbed_official 324:406fd2029f23 9893 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
mbed_official 324:406fd2029f23 9894 } WDOG_Type, *WDOG_MemMapPtr;
mbed_official 324:406fd2029f23 9895
mbed_official 324:406fd2029f23 9896 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9897 -- WDOG - Register accessor macros
mbed_official 324:406fd2029f23 9898 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9899
mbed_official 324:406fd2029f23 9900 /*!
mbed_official 324:406fd2029f23 9901 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
mbed_official 324:406fd2029f23 9902 * @{
mbed_official 324:406fd2029f23 9903 */
mbed_official 324:406fd2029f23 9904
mbed_official 324:406fd2029f23 9905
mbed_official 324:406fd2029f23 9906 /* WDOG - Register accessors */
mbed_official 324:406fd2029f23 9907 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
mbed_official 324:406fd2029f23 9908 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
mbed_official 324:406fd2029f23 9909 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
mbed_official 324:406fd2029f23 9910 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
mbed_official 324:406fd2029f23 9911 #define WDOG_WINH_REG(base) ((base)->WINH)
mbed_official 324:406fd2029f23 9912 #define WDOG_WINL_REG(base) ((base)->WINL)
mbed_official 324:406fd2029f23 9913 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
mbed_official 324:406fd2029f23 9914 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
mbed_official 324:406fd2029f23 9915 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
mbed_official 324:406fd2029f23 9916 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
mbed_official 324:406fd2029f23 9917 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
mbed_official 324:406fd2029f23 9918 #define WDOG_PRESC_REG(base) ((base)->PRESC)
mbed_official 324:406fd2029f23 9919
mbed_official 324:406fd2029f23 9920 /*!
mbed_official 324:406fd2029f23 9921 * @}
mbed_official 324:406fd2029f23 9922 */ /* end of group WDOG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 9923
mbed_official 324:406fd2029f23 9924
mbed_official 324:406fd2029f23 9925 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 9926 -- WDOG Register Masks
mbed_official 324:406fd2029f23 9927 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 9928
mbed_official 324:406fd2029f23 9929 /*!
mbed_official 324:406fd2029f23 9930 * @addtogroup WDOG_Register_Masks WDOG Register Masks
mbed_official 324:406fd2029f23 9931 * @{
mbed_official 324:406fd2029f23 9932 */
mbed_official 324:406fd2029f23 9933
mbed_official 324:406fd2029f23 9934 /* STCTRLH Bit Fields */
mbed_official 324:406fd2029f23 9935 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
mbed_official 324:406fd2029f23 9936 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
mbed_official 324:406fd2029f23 9937 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
mbed_official 324:406fd2029f23 9938 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
mbed_official 324:406fd2029f23 9939 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
mbed_official 324:406fd2029f23 9940 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
mbed_official 324:406fd2029f23 9941 #define WDOG_STCTRLH_WINEN_MASK 0x8u
mbed_official 324:406fd2029f23 9942 #define WDOG_STCTRLH_WINEN_SHIFT 3
mbed_official 324:406fd2029f23 9943 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
mbed_official 324:406fd2029f23 9944 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
mbed_official 324:406fd2029f23 9945 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
mbed_official 324:406fd2029f23 9946 #define WDOG_STCTRLH_DBGEN_SHIFT 5
mbed_official 324:406fd2029f23 9947 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
mbed_official 324:406fd2029f23 9948 #define WDOG_STCTRLH_STOPEN_SHIFT 6
mbed_official 324:406fd2029f23 9949 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
mbed_official 324:406fd2029f23 9950 #define WDOG_STCTRLH_WAITEN_SHIFT 7
mbed_official 324:406fd2029f23 9951 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
mbed_official 324:406fd2029f23 9952 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
mbed_official 324:406fd2029f23 9953 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
mbed_official 324:406fd2029f23 9954 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
mbed_official 324:406fd2029f23 9955 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
mbed_official 324:406fd2029f23 9956 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
mbed_official 324:406fd2029f23 9957 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
mbed_official 324:406fd2029f23 9958 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
mbed_official 324:406fd2029f23 9959 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
mbed_official 324:406fd2029f23 9960 /* STCTRLL Bit Fields */
mbed_official 324:406fd2029f23 9961 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
mbed_official 324:406fd2029f23 9962 #define WDOG_STCTRLL_INTFLG_SHIFT 15
mbed_official 324:406fd2029f23 9963 /* TOVALH Bit Fields */
mbed_official 324:406fd2029f23 9964 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9965 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
mbed_official 324:406fd2029f23 9966 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
mbed_official 324:406fd2029f23 9967 /* TOVALL Bit Fields */
mbed_official 324:406fd2029f23 9968 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9969 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
mbed_official 324:406fd2029f23 9970 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
mbed_official 324:406fd2029f23 9971 /* WINH Bit Fields */
mbed_official 324:406fd2029f23 9972 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9973 #define WDOG_WINH_WINHIGH_SHIFT 0
mbed_official 324:406fd2029f23 9974 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
mbed_official 324:406fd2029f23 9975 /* WINL Bit Fields */
mbed_official 324:406fd2029f23 9976 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9977 #define WDOG_WINL_WINLOW_SHIFT 0
mbed_official 324:406fd2029f23 9978 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
mbed_official 324:406fd2029f23 9979 /* REFRESH Bit Fields */
mbed_official 324:406fd2029f23 9980 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9981 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
mbed_official 324:406fd2029f23 9982 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
mbed_official 324:406fd2029f23 9983 /* UNLOCK Bit Fields */
mbed_official 324:406fd2029f23 9984 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9985 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
mbed_official 324:406fd2029f23 9986 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
mbed_official 324:406fd2029f23 9987 /* TMROUTH Bit Fields */
mbed_official 324:406fd2029f23 9988 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9989 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
mbed_official 324:406fd2029f23 9990 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
mbed_official 324:406fd2029f23 9991 /* TMROUTL Bit Fields */
mbed_official 324:406fd2029f23 9992 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9993 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
mbed_official 324:406fd2029f23 9994 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
mbed_official 324:406fd2029f23 9995 /* RSTCNT Bit Fields */
mbed_official 324:406fd2029f23 9996 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
mbed_official 324:406fd2029f23 9997 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
mbed_official 324:406fd2029f23 9998 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
mbed_official 324:406fd2029f23 9999 /* PRESC Bit Fields */
mbed_official 324:406fd2029f23 10000 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
mbed_official 324:406fd2029f23 10001 #define WDOG_PRESC_PRESCVAL_SHIFT 8
mbed_official 324:406fd2029f23 10002 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
mbed_official 324:406fd2029f23 10003
mbed_official 324:406fd2029f23 10004 /*!
mbed_official 324:406fd2029f23 10005 * @}
mbed_official 324:406fd2029f23 10006 */ /* end of group WDOG_Register_Masks */
mbed_official 324:406fd2029f23 10007
mbed_official 324:406fd2029f23 10008
mbed_official 324:406fd2029f23 10009 /* WDOG - Peripheral instance base addresses */
mbed_official 324:406fd2029f23 10010 /** Peripheral WDOG base address */
mbed_official 324:406fd2029f23 10011 #define WDOG_BASE (0x40052000u)
mbed_official 324:406fd2029f23 10012 /** Peripheral WDOG base pointer */
mbed_official 324:406fd2029f23 10013 #define WDOG ((WDOG_Type *)WDOG_BASE)
mbed_official 324:406fd2029f23 10014 #define WDOG_BASE_PTR (WDOG)
mbed_official 324:406fd2029f23 10015 /** Array initializer of WDOG peripheral base addresses */
mbed_official 324:406fd2029f23 10016 #define WDOG_BASE_ADDRS { WDOG_BASE }
mbed_official 324:406fd2029f23 10017 /** Array initializer of WDOG peripheral base pointers */
mbed_official 324:406fd2029f23 10018 #define WDOG_BASE_PTRS { WDOG }
mbed_official 324:406fd2029f23 10019 /** Interrupt vectors for the WDOG peripheral type */
mbed_official 324:406fd2029f23 10020 #define WDOG_IRQS { Watchdog_IRQn }
mbed_official 324:406fd2029f23 10021
mbed_official 324:406fd2029f23 10022 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 10023 -- WDOG - Register accessor macros
mbed_official 324:406fd2029f23 10024 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 10025
mbed_official 324:406fd2029f23 10026 /*!
mbed_official 324:406fd2029f23 10027 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
mbed_official 324:406fd2029f23 10028 * @{
mbed_official 324:406fd2029f23 10029 */
mbed_official 324:406fd2029f23 10030
mbed_official 324:406fd2029f23 10031
mbed_official 324:406fd2029f23 10032 /* WDOG - Register instance definitions */
mbed_official 324:406fd2029f23 10033 /* WDOG */
mbed_official 324:406fd2029f23 10034 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
mbed_official 324:406fd2029f23 10035 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
mbed_official 324:406fd2029f23 10036 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
mbed_official 324:406fd2029f23 10037 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
mbed_official 324:406fd2029f23 10038 #define WDOG_WINH WDOG_WINH_REG(WDOG)
mbed_official 324:406fd2029f23 10039 #define WDOG_WINL WDOG_WINL_REG(WDOG)
mbed_official 324:406fd2029f23 10040 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
mbed_official 324:406fd2029f23 10041 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
mbed_official 324:406fd2029f23 10042 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
mbed_official 324:406fd2029f23 10043 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
mbed_official 324:406fd2029f23 10044 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
mbed_official 324:406fd2029f23 10045 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
mbed_official 324:406fd2029f23 10046
mbed_official 324:406fd2029f23 10047 /*!
mbed_official 324:406fd2029f23 10048 * @}
mbed_official 324:406fd2029f23 10049 */ /* end of group WDOG_Register_Accessor_Macros */
mbed_official 324:406fd2029f23 10050
mbed_official 324:406fd2029f23 10051
mbed_official 324:406fd2029f23 10052 /*!
mbed_official 324:406fd2029f23 10053 * @}
mbed_official 324:406fd2029f23 10054 */ /* end of group WDOG_Peripheral_Access_Layer */
mbed_official 324:406fd2029f23 10055
mbed_official 324:406fd2029f23 10056
mbed_official 324:406fd2029f23 10057 /*
mbed_official 324:406fd2029f23 10058 ** End of section using anonymous unions
mbed_official 324:406fd2029f23 10059 */
mbed_official 324:406fd2029f23 10060
mbed_official 324:406fd2029f23 10061 #if defined(__ARMCC_VERSION)
mbed_official 324:406fd2029f23 10062 #pragma pop
mbed_official 324:406fd2029f23 10063 #elif defined(__CWCC__)
mbed_official 324:406fd2029f23 10064 #pragma pop
mbed_official 324:406fd2029f23 10065 #elif defined(__GNUC__)
mbed_official 324:406fd2029f23 10066 /* leave anonymous unions enabled */
mbed_official 324:406fd2029f23 10067 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 324:406fd2029f23 10068 #pragma language=default
mbed_official 324:406fd2029f23 10069 #else
mbed_official 324:406fd2029f23 10070 #error Not supported compiler type
mbed_official 324:406fd2029f23 10071 #endif
mbed_official 324:406fd2029f23 10072
mbed_official 324:406fd2029f23 10073 /*!
mbed_official 324:406fd2029f23 10074 * @}
mbed_official 324:406fd2029f23 10075 */ /* end of group Peripheral_access_layer */
mbed_official 324:406fd2029f23 10076
mbed_official 324:406fd2029f23 10077
mbed_official 324:406fd2029f23 10078 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 10079 -- Backward Compatibility
mbed_official 324:406fd2029f23 10080 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 10081
mbed_official 324:406fd2029f23 10082 /*!
mbed_official 324:406fd2029f23 10083 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 324:406fd2029f23 10084 * @{
mbed_official 324:406fd2029f23 10085 */
mbed_official 324:406fd2029f23 10086
mbed_official 324:406fd2029f23 10087 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
mbed_official 324:406fd2029f23 10088 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
mbed_official 324:406fd2029f23 10089 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
mbed_official 324:406fd2029f23 10090 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
mbed_official 324:406fd2029f23 10091 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
mbed_official 324:406fd2029f23 10092 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
mbed_official 324:406fd2029f23 10093 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
mbed_official 324:406fd2029f23 10094 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
mbed_official 324:406fd2029f23 10095 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
mbed_official 324:406fd2029f23 10096 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
mbed_official 324:406fd2029f23 10097 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
mbed_official 324:406fd2029f23 10098 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
mbed_official 324:406fd2029f23 10099 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
mbed_official 324:406fd2029f23 10100 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
mbed_official 324:406fd2029f23 10101 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
mbed_official 324:406fd2029f23 10102 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
mbed_official 324:406fd2029f23 10103 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
mbed_official 324:406fd2029f23 10104 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
mbed_official 324:406fd2029f23 10105 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
mbed_official 324:406fd2029f23 10106 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
mbed_official 324:406fd2029f23 10107 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
mbed_official 324:406fd2029f23 10108 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
mbed_official 324:406fd2029f23 10109 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
mbed_official 324:406fd2029f23 10110 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
mbed_official 324:406fd2029f23 10111 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
mbed_official 324:406fd2029f23 10112 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
mbed_official 324:406fd2029f23 10113 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
mbed_official 324:406fd2029f23 10114 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
mbed_official 324:406fd2029f23 10115 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
mbed_official 324:406fd2029f23 10116 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
mbed_official 324:406fd2029f23 10117 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
mbed_official 324:406fd2029f23 10118 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
mbed_official 324:406fd2029f23 10119 #define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
mbed_official 324:406fd2029f23 10120 #define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
mbed_official 324:406fd2029f23 10121 #define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
mbed_official 324:406fd2029f23 10122
mbed_official 324:406fd2029f23 10123 /*!
mbed_official 324:406fd2029f23 10124 * @}
mbed_official 324:406fd2029f23 10125 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 324:406fd2029f23 10126
mbed_official 324:406fd2029f23 10127
mbed_official 324:406fd2029f23 10128 #else /* #if !defined(MK22F51212_H_) */
mbed_official 324:406fd2029f23 10129 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
mbed_official 324:406fd2029f23 10130 #if (MCU_MEM_MAP_VERSION != 0x0200u)
mbed_official 324:406fd2029f23 10131 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
mbed_official 324:406fd2029f23 10132 #warning There are included two not compatible versions of memory maps. Please check possible differences.
mbed_official 324:406fd2029f23 10133 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
mbed_official 324:406fd2029f23 10134 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
mbed_official 324:406fd2029f23 10135 #endif /* #if !defined(MK22F51212_H_) */
mbed_official 324:406fd2029f23 10136
mbed_official 324:406fd2029f23 10137 /* MK22F51212.h, eof. */