Geremia G
- fix F411 F334 systeminit when HSI used - portinout always read IDR regardless of port direction
Fork of
mbed-src
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/system_stm32f4xx.c@235:685d5f11838f, 2014-06-23 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Jun 23 14:00:09 2014 +0100
- Revision:
- 235:685d5f11838f
- Child:
- 332:e299ae530e63
Synchronized with git revision 9728c76667962b289ee9c4c687ef9f115db48cd3
Full URL: https://github.com/mbedmicro/mbed/commit/9728c76667962b289ee9c4c687ef9f115db48cd3/
[NUCLEO_F411RE] Add all target files
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file system_stm32f4xx.c |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 235:685d5f11838f | 5 | * @version V2.1.0 |
| mbed_official | 235:685d5f11838f | 6 | * @date 19-June-2014 |
| mbed_official | 235:685d5f11838f | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| mbed_official | 235:685d5f11838f | 8 | * |
| mbed_official | 235:685d5f11838f | 9 | * This file provides two functions and one global variable to be called from |
| mbed_official | 235:685d5f11838f | 10 | * user application: |
| mbed_official | 235:685d5f11838f | 11 | * - SystemInit(): This function is called at startup just after reset and |
| mbed_official | 235:685d5f11838f | 12 | * before branch to main program. This call is made inside |
| mbed_official | 235:685d5f11838f | 13 | * the "startup_stm32f4xx.s" file. |
| mbed_official | 235:685d5f11838f | 14 | * |
| mbed_official | 235:685d5f11838f | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 235:685d5f11838f | 16 | * by the user application to setup the SysTick |
| mbed_official | 235:685d5f11838f | 17 | * timer or configure other parameters. |
| mbed_official | 235:685d5f11838f | 18 | * |
| mbed_official | 235:685d5f11838f | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 235:685d5f11838f | 20 | * be called whenever the core clock is changed |
| mbed_official | 235:685d5f11838f | 21 | * during program execution. |
| mbed_official | 235:685d5f11838f | 22 | * |
| mbed_official | 235:685d5f11838f | 23 | * This file configures the system clock as follows: |
| mbed_official | 235:685d5f11838f | 24 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| mbed_official | 235:685d5f11838f | 26 | * | (external 8 MHz clock) | (internal 16 MHz) |
| mbed_official | 235:685d5f11838f | 27 | * | 2- PLL_HSE_XTAL | |
| mbed_official | 235:685d5f11838f | 28 | * | (external 8 MHz xtal) | |
| mbed_official | 235:685d5f11838f | 29 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 30 | * SYSCLK(MHz) | 100 | 100 |
| mbed_official | 235:685d5f11838f | 31 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 32 | * AHBCLK (MHz) | 100 | 100 |
| mbed_official | 235:685d5f11838f | 33 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 34 | * APB1CLK (MHz) | 50 | 50 |
| mbed_official | 235:685d5f11838f | 35 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 36 | * APB2CLK (MHz) | 100 | 100 |
| mbed_official | 235:685d5f11838f | 37 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 38 | * USB capable (48 MHz precise clock) | NO | NO |
| mbed_official | 235:685d5f11838f | 39 | *----------------------------------------------------------------------------- |
| mbed_official | 235:685d5f11838f | 40 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 41 | * @attention |
| mbed_official | 235:685d5f11838f | 42 | * |
| mbed_official | 235:685d5f11838f | 43 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 44 | * |
| mbed_official | 235:685d5f11838f | 45 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 46 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 48 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 50 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 51 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 53 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 54 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 55 | * |
| mbed_official | 235:685d5f11838f | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 66 | * |
| mbed_official | 235:685d5f11838f | 67 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 68 | */ |
| mbed_official | 235:685d5f11838f | 69 | |
| mbed_official | 235:685d5f11838f | 70 | /** @addtogroup CMSIS |
| mbed_official | 235:685d5f11838f | 71 | * @{ |
| mbed_official | 235:685d5f11838f | 72 | */ |
| mbed_official | 235:685d5f11838f | 73 | |
| mbed_official | 235:685d5f11838f | 74 | /** @addtogroup stm32f4xx_system |
| mbed_official | 235:685d5f11838f | 75 | * @{ |
| mbed_official | 235:685d5f11838f | 76 | */ |
| mbed_official | 235:685d5f11838f | 77 | |
| mbed_official | 235:685d5f11838f | 78 | /** @addtogroup STM32F4xx_System_Private_Includes |
| mbed_official | 235:685d5f11838f | 79 | * @{ |
| mbed_official | 235:685d5f11838f | 80 | */ |
| mbed_official | 235:685d5f11838f | 81 | |
| mbed_official | 235:685d5f11838f | 82 | |
| mbed_official | 235:685d5f11838f | 83 | #include "stm32f4xx.h" |
| mbed_official | 235:685d5f11838f | 84 | #include "hal_tick.h" |
| mbed_official | 235:685d5f11838f | 85 | |
| mbed_official | 235:685d5f11838f | 86 | #if !defined (HSE_VALUE) |
| mbed_official | 235:685d5f11838f | 87 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ |
| mbed_official | 235:685d5f11838f | 88 | #endif /* HSE_VALUE */ |
| mbed_official | 235:685d5f11838f | 89 | |
| mbed_official | 235:685d5f11838f | 90 | #if !defined (HSI_VALUE) |
| mbed_official | 235:685d5f11838f | 91 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| mbed_official | 235:685d5f11838f | 92 | #endif /* HSI_VALUE */ |
| mbed_official | 235:685d5f11838f | 93 | |
| mbed_official | 235:685d5f11838f | 94 | /** |
| mbed_official | 235:685d5f11838f | 95 | * @} |
| mbed_official | 235:685d5f11838f | 96 | */ |
| mbed_official | 235:685d5f11838f | 97 | |
| mbed_official | 235:685d5f11838f | 98 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| mbed_official | 235:685d5f11838f | 99 | * @{ |
| mbed_official | 235:685d5f11838f | 100 | */ |
| mbed_official | 235:685d5f11838f | 101 | |
| mbed_official | 235:685d5f11838f | 102 | /** |
| mbed_official | 235:685d5f11838f | 103 | * @} |
| mbed_official | 235:685d5f11838f | 104 | */ |
| mbed_official | 235:685d5f11838f | 105 | |
| mbed_official | 235:685d5f11838f | 106 | /** @addtogroup STM32F4xx_System_Private_Defines |
| mbed_official | 235:685d5f11838f | 107 | * @{ |
| mbed_official | 235:685d5f11838f | 108 | */ |
| mbed_official | 235:685d5f11838f | 109 | |
| mbed_official | 235:685d5f11838f | 110 | /************************* Miscellaneous Configuration ************************/ |
| mbed_official | 235:685d5f11838f | 111 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted |
| mbed_official | 235:685d5f11838f | 112 | on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ |
| mbed_official | 235:685d5f11838f | 113 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 114 | /* #define DATA_IN_ExtSRAM */ |
| mbed_official | 235:685d5f11838f | 115 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 116 | |
| mbed_official | 235:685d5f11838f | 117 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 118 | /* #define DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 119 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 120 | |
| mbed_official | 235:685d5f11838f | 121 | #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) |
| mbed_official | 235:685d5f11838f | 122 | #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " |
| mbed_official | 235:685d5f11838f | 123 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 124 | |
| mbed_official | 235:685d5f11838f | 125 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| mbed_official | 235:685d5f11838f | 126 | Internal SRAM. */ |
| mbed_official | 235:685d5f11838f | 127 | /* #define VECT_TAB_SRAM */ |
| mbed_official | 235:685d5f11838f | 128 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| mbed_official | 235:685d5f11838f | 129 | This value must be a multiple of 0x200. */ |
| mbed_official | 235:685d5f11838f | 130 | /******************************************************************************/ |
| mbed_official | 235:685d5f11838f | 131 | |
| mbed_official | 235:685d5f11838f | 132 | /** |
| mbed_official | 235:685d5f11838f | 133 | * @} |
| mbed_official | 235:685d5f11838f | 134 | */ |
| mbed_official | 235:685d5f11838f | 135 | |
| mbed_official | 235:685d5f11838f | 136 | /** @addtogroup STM32F4xx_System_Private_Macros |
| mbed_official | 235:685d5f11838f | 137 | * @{ |
| mbed_official | 235:685d5f11838f | 138 | */ |
| mbed_official | 235:685d5f11838f | 139 | |
| mbed_official | 235:685d5f11838f | 140 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| mbed_official | 235:685d5f11838f | 141 | #define USE_PLL_HSE_EXTC (1) /* Use external clock */ |
| mbed_official | 235:685d5f11838f | 142 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| mbed_official | 235:685d5f11838f | 143 | |
| mbed_official | 235:685d5f11838f | 144 | /** |
| mbed_official | 235:685d5f11838f | 145 | * @} |
| mbed_official | 235:685d5f11838f | 146 | */ |
| mbed_official | 235:685d5f11838f | 147 | |
| mbed_official | 235:685d5f11838f | 148 | /** @addtogroup STM32F4xx_System_Private_Variables |
| mbed_official | 235:685d5f11838f | 149 | * @{ |
| mbed_official | 235:685d5f11838f | 150 | */ |
| mbed_official | 235:685d5f11838f | 151 | /* This variable is updated in three ways: |
| mbed_official | 235:685d5f11838f | 152 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| mbed_official | 235:685d5f11838f | 153 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| mbed_official | 235:685d5f11838f | 154 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| mbed_official | 235:685d5f11838f | 155 | Note: If you use this function to configure the system clock; then there |
| mbed_official | 235:685d5f11838f | 156 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| mbed_official | 235:685d5f11838f | 157 | variable is updated automatically. |
| mbed_official | 235:685d5f11838f | 158 | */ |
| mbed_official | 235:685d5f11838f | 159 | uint32_t SystemCoreClock = 16000000; |
| mbed_official | 235:685d5f11838f | 160 | __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 235:685d5f11838f | 161 | |
| mbed_official | 235:685d5f11838f | 162 | /** |
| mbed_official | 235:685d5f11838f | 163 | * @} |
| mbed_official | 235:685d5f11838f | 164 | */ |
| mbed_official | 235:685d5f11838f | 165 | |
| mbed_official | 235:685d5f11838f | 166 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| mbed_official | 235:685d5f11838f | 167 | * @{ |
| mbed_official | 235:685d5f11838f | 168 | */ |
| mbed_official | 235:685d5f11838f | 169 | |
| mbed_official | 235:685d5f11838f | 170 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 235:685d5f11838f | 171 | static void SystemInit_ExtMemCtl(void); |
| mbed_official | 235:685d5f11838f | 172 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 173 | |
| mbed_official | 235:685d5f11838f | 174 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 235:685d5f11838f | 175 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| mbed_official | 235:685d5f11838f | 176 | #endif |
| mbed_official | 235:685d5f11838f | 177 | |
| mbed_official | 235:685d5f11838f | 178 | uint8_t SetSysClock_PLL_HSI(void); |
| mbed_official | 235:685d5f11838f | 179 | |
| mbed_official | 235:685d5f11838f | 180 | /** |
| mbed_official | 235:685d5f11838f | 181 | * @} |
| mbed_official | 235:685d5f11838f | 182 | */ |
| mbed_official | 235:685d5f11838f | 183 | |
| mbed_official | 235:685d5f11838f | 184 | /** @addtogroup STM32F4xx_System_Private_Functions |
| mbed_official | 235:685d5f11838f | 185 | * @{ |
| mbed_official | 235:685d5f11838f | 186 | */ |
| mbed_official | 235:685d5f11838f | 187 | |
| mbed_official | 235:685d5f11838f | 188 | /** |
| mbed_official | 235:685d5f11838f | 189 | * @brief Setup the microcontroller system |
| mbed_official | 235:685d5f11838f | 190 | * Initialize the FPU setting, vector table location and External memory |
| mbed_official | 235:685d5f11838f | 191 | * configuration. |
| mbed_official | 235:685d5f11838f | 192 | * @param None |
| mbed_official | 235:685d5f11838f | 193 | * @retval None |
| mbed_official | 235:685d5f11838f | 194 | */ |
| mbed_official | 235:685d5f11838f | 195 | void SystemInit(void) |
| mbed_official | 235:685d5f11838f | 196 | { |
| mbed_official | 235:685d5f11838f | 197 | /* FPU settings ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 198 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| mbed_official | 235:685d5f11838f | 199 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| mbed_official | 235:685d5f11838f | 200 | #endif |
| mbed_official | 235:685d5f11838f | 201 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| mbed_official | 235:685d5f11838f | 202 | /* Set HSION bit */ |
| mbed_official | 235:685d5f11838f | 203 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 235:685d5f11838f | 204 | |
| mbed_official | 235:685d5f11838f | 205 | /* Reset CFGR register */ |
| mbed_official | 235:685d5f11838f | 206 | RCC->CFGR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 207 | |
| mbed_official | 235:685d5f11838f | 208 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 235:685d5f11838f | 209 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 235:685d5f11838f | 210 | |
| mbed_official | 235:685d5f11838f | 211 | /* Reset PLLCFGR register */ |
| mbed_official | 235:685d5f11838f | 212 | RCC->PLLCFGR = 0x24003010; |
| mbed_official | 235:685d5f11838f | 213 | |
| mbed_official | 235:685d5f11838f | 214 | /* Reset HSEBYP bit */ |
| mbed_official | 235:685d5f11838f | 215 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 235:685d5f11838f | 216 | |
| mbed_official | 235:685d5f11838f | 217 | /* Disable all interrupts */ |
| mbed_official | 235:685d5f11838f | 218 | RCC->CIR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 219 | |
| mbed_official | 235:685d5f11838f | 220 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 235:685d5f11838f | 221 | SystemInit_ExtMemCtl(); |
| mbed_official | 235:685d5f11838f | 222 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 223 | |
| mbed_official | 235:685d5f11838f | 224 | /* Configure the Vector Table location add offset address ------------------*/ |
| mbed_official | 235:685d5f11838f | 225 | #ifdef VECT_TAB_SRAM |
| mbed_official | 235:685d5f11838f | 226 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| mbed_official | 235:685d5f11838f | 227 | #else |
| mbed_official | 235:685d5f11838f | 228 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| mbed_official | 235:685d5f11838f | 229 | #endif |
| mbed_official | 235:685d5f11838f | 230 | |
| mbed_official | 235:685d5f11838f | 231 | /* Configure the Cube driver */ |
| mbed_official | 235:685d5f11838f | 232 | SystemCoreClock = 16000000; // At this stage the HSI is used as system clock |
| mbed_official | 235:685d5f11838f | 233 | HAL_Init(); |
| mbed_official | 235:685d5f11838f | 234 | |
| mbed_official | 235:685d5f11838f | 235 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 235:685d5f11838f | 236 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 235:685d5f11838f | 237 | SetSysClock(); |
| mbed_official | 235:685d5f11838f | 238 | |
| mbed_official | 235:685d5f11838f | 239 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 235:685d5f11838f | 240 | TIM_MST_RESET_ON; |
| mbed_official | 235:685d5f11838f | 241 | TIM_MST_RESET_OFF; |
| mbed_official | 235:685d5f11838f | 242 | } |
| mbed_official | 235:685d5f11838f | 243 | |
| mbed_official | 235:685d5f11838f | 244 | /** |
| mbed_official | 235:685d5f11838f | 245 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 235:685d5f11838f | 246 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 235:685d5f11838f | 247 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 235:685d5f11838f | 248 | * other parameters. |
| mbed_official | 235:685d5f11838f | 249 | * |
| mbed_official | 235:685d5f11838f | 250 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 235:685d5f11838f | 251 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 235:685d5f11838f | 252 | * based on this variable will be incorrect. |
| mbed_official | 235:685d5f11838f | 253 | * |
| mbed_official | 235:685d5f11838f | 254 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 235:685d5f11838f | 255 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 235:685d5f11838f | 256 | * constant and the selected clock source: |
| mbed_official | 235:685d5f11838f | 257 | * |
| mbed_official | 235:685d5f11838f | 258 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 235:685d5f11838f | 259 | * |
| mbed_official | 235:685d5f11838f | 260 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 235:685d5f11838f | 261 | * |
| mbed_official | 235:685d5f11838f | 262 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 235:685d5f11838f | 263 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| mbed_official | 235:685d5f11838f | 264 | * |
| mbed_official | 235:685d5f11838f | 265 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| mbed_official | 235:685d5f11838f | 266 | * 16 MHz) but the real value may vary depending on the variations |
| mbed_official | 235:685d5f11838f | 267 | * in voltage and temperature. |
| mbed_official | 235:685d5f11838f | 268 | * |
| mbed_official | 235:685d5f11838f | 269 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| mbed_official | 235:685d5f11838f | 270 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| mbed_official | 235:685d5f11838f | 271 | * is same as the real frequency of the crystal used. Otherwise, this function |
| mbed_official | 235:685d5f11838f | 272 | * may have wrong result. |
| mbed_official | 235:685d5f11838f | 273 | * |
| mbed_official | 235:685d5f11838f | 274 | * - The result of this function could be not correct when using fractional |
| mbed_official | 235:685d5f11838f | 275 | * value for HSE crystal. |
| mbed_official | 235:685d5f11838f | 276 | * |
| mbed_official | 235:685d5f11838f | 277 | * @param None |
| mbed_official | 235:685d5f11838f | 278 | * @retval None |
| mbed_official | 235:685d5f11838f | 279 | */ |
| mbed_official | 235:685d5f11838f | 280 | void SystemCoreClockUpdate(void) |
| mbed_official | 235:685d5f11838f | 281 | { |
| mbed_official | 235:685d5f11838f | 282 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| mbed_official | 235:685d5f11838f | 283 | |
| mbed_official | 235:685d5f11838f | 284 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 285 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 235:685d5f11838f | 286 | |
| mbed_official | 235:685d5f11838f | 287 | switch (tmp) |
| mbed_official | 235:685d5f11838f | 288 | { |
| mbed_official | 235:685d5f11838f | 289 | case 0x00: /* HSI used as system clock source */ |
| mbed_official | 235:685d5f11838f | 290 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 235:685d5f11838f | 291 | break; |
| mbed_official | 235:685d5f11838f | 292 | case 0x04: /* HSE used as system clock source */ |
| mbed_official | 235:685d5f11838f | 293 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 235:685d5f11838f | 294 | break; |
| mbed_official | 235:685d5f11838f | 295 | case 0x08: /* PLL used as system clock source */ |
| mbed_official | 235:685d5f11838f | 296 | |
| mbed_official | 235:685d5f11838f | 297 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| mbed_official | 235:685d5f11838f | 298 | SYSCLK = PLL_VCO / PLL_P |
| mbed_official | 235:685d5f11838f | 299 | */ |
| mbed_official | 235:685d5f11838f | 300 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| mbed_official | 235:685d5f11838f | 301 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| mbed_official | 235:685d5f11838f | 302 | |
| mbed_official | 235:685d5f11838f | 303 | if (pllsource != 0) |
| mbed_official | 235:685d5f11838f | 304 | { |
| mbed_official | 235:685d5f11838f | 305 | /* HSE used as PLL clock source */ |
| mbed_official | 235:685d5f11838f | 306 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 235:685d5f11838f | 307 | } |
| mbed_official | 235:685d5f11838f | 308 | else |
| mbed_official | 235:685d5f11838f | 309 | { |
| mbed_official | 235:685d5f11838f | 310 | /* HSI used as PLL clock source */ |
| mbed_official | 235:685d5f11838f | 311 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 235:685d5f11838f | 312 | } |
| mbed_official | 235:685d5f11838f | 313 | |
| mbed_official | 235:685d5f11838f | 314 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| mbed_official | 235:685d5f11838f | 315 | SystemCoreClock = pllvco/pllp; |
| mbed_official | 235:685d5f11838f | 316 | break; |
| mbed_official | 235:685d5f11838f | 317 | default: |
| mbed_official | 235:685d5f11838f | 318 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 235:685d5f11838f | 319 | break; |
| mbed_official | 235:685d5f11838f | 320 | } |
| mbed_official | 235:685d5f11838f | 321 | /* Compute HCLK frequency --------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 322 | /* Get HCLK prescaler */ |
| mbed_official | 235:685d5f11838f | 323 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 235:685d5f11838f | 324 | /* HCLK frequency */ |
| mbed_official | 235:685d5f11838f | 325 | SystemCoreClock >>= tmp; |
| mbed_official | 235:685d5f11838f | 326 | } |
| mbed_official | 235:685d5f11838f | 327 | |
| mbed_official | 235:685d5f11838f | 328 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 235:685d5f11838f | 329 | /** |
| mbed_official | 235:685d5f11838f | 330 | * @brief Setup the external memory controller. |
| mbed_official | 235:685d5f11838f | 331 | * Called in startup_stm32f4xx.s before jump to main. |
| mbed_official | 235:685d5f11838f | 332 | * This function configures the external memories (SRAM/SDRAM) |
| mbed_official | 235:685d5f11838f | 333 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| mbed_official | 235:685d5f11838f | 334 | * @param None |
| mbed_official | 235:685d5f11838f | 335 | * @retval None |
| mbed_official | 235:685d5f11838f | 336 | */ |
| mbed_official | 235:685d5f11838f | 337 | void SystemInit_ExtMemCtl(void) |
| mbed_official | 235:685d5f11838f | 338 | { |
| mbed_official | 235:685d5f11838f | 339 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 340 | #if defined (DATA_IN_ExtSDRAM) |
| mbed_official | 235:685d5f11838f | 341 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| mbed_official | 235:685d5f11838f | 342 | register uint32_t index; |
| mbed_official | 235:685d5f11838f | 343 | |
| mbed_official | 235:685d5f11838f | 344 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| mbed_official | 235:685d5f11838f | 345 | clock */ |
| mbed_official | 235:685d5f11838f | 346 | RCC->AHB1ENR |= 0x000001F8; |
| mbed_official | 235:685d5f11838f | 347 | |
| mbed_official | 235:685d5f11838f | 348 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 349 | GPIOD->AFR[0] = 0x000000CC; |
| mbed_official | 235:685d5f11838f | 350 | GPIOD->AFR[1] = 0xCC000CCC; |
| mbed_official | 235:685d5f11838f | 351 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 352 | GPIOD->MODER = 0xA02A000A; |
| mbed_official | 235:685d5f11838f | 353 | /* Configure PDx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 354 | GPIOD->OSPEEDR = 0xA02A000A; |
| mbed_official | 235:685d5f11838f | 355 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 356 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 357 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 235:685d5f11838f | 358 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 359 | |
| mbed_official | 235:685d5f11838f | 360 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 361 | GPIOE->AFR[0] = 0xC00000CC; |
| mbed_official | 235:685d5f11838f | 362 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 363 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 364 | GPIOE->MODER = 0xAAAA800A; |
| mbed_official | 235:685d5f11838f | 365 | /* Configure PEx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 366 | GPIOE->OSPEEDR = 0xAAAA800A; |
| mbed_official | 235:685d5f11838f | 367 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 368 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 369 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 235:685d5f11838f | 370 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 371 | |
| mbed_official | 235:685d5f11838f | 372 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 373 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 374 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 375 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 376 | GPIOF->MODER = 0xAA800AAA; |
| mbed_official | 235:685d5f11838f | 377 | /* Configure PFx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 378 | GPIOF->OSPEEDR = 0xAA800AAA; |
| mbed_official | 235:685d5f11838f | 379 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 380 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 381 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 235:685d5f11838f | 382 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 383 | |
| mbed_official | 235:685d5f11838f | 384 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 385 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 386 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 387 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 388 | GPIOG->MODER = 0xAAAAAAAA; |
| mbed_official | 235:685d5f11838f | 389 | /* Configure PGx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 390 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| mbed_official | 235:685d5f11838f | 391 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 392 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 393 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 235:685d5f11838f | 394 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 395 | |
| mbed_official | 235:685d5f11838f | 396 | /* Connect PHx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 397 | GPIOH->AFR[0] = 0x00C0CC00; |
| mbed_official | 235:685d5f11838f | 398 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 399 | /* Configure PHx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 400 | GPIOH->MODER = 0xAAAA08A0; |
| mbed_official | 235:685d5f11838f | 401 | /* Configure PHx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 402 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| mbed_official | 235:685d5f11838f | 403 | /* Configure PHx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 404 | GPIOH->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 405 | /* No pull-up, pull-down for PHx pins */ |
| mbed_official | 235:685d5f11838f | 406 | GPIOH->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 407 | |
| mbed_official | 235:685d5f11838f | 408 | /* Connect PIx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 409 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 410 | GPIOI->AFR[1] = 0x00000CC0; |
| mbed_official | 235:685d5f11838f | 411 | /* Configure PIx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 412 | GPIOI->MODER = 0x0028AAAA; |
| mbed_official | 235:685d5f11838f | 413 | /* Configure PIx pins speed to 50 MHz */ |
| mbed_official | 235:685d5f11838f | 414 | GPIOI->OSPEEDR = 0x0028AAAA; |
| mbed_official | 235:685d5f11838f | 415 | /* Configure PIx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 416 | GPIOI->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 417 | /* No pull-up, pull-down for PIx pins */ |
| mbed_official | 235:685d5f11838f | 418 | GPIOI->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 419 | |
| mbed_official | 235:685d5f11838f | 420 | /*-- FMC Configuration ------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 421 | /* Enable the FMC interface clock */ |
| mbed_official | 235:685d5f11838f | 422 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 235:685d5f11838f | 423 | |
| mbed_official | 235:685d5f11838f | 424 | /* Configure and enable SDRAM bank1 */ |
| mbed_official | 235:685d5f11838f | 425 | FMC_Bank5_6->SDCR[0] = 0x000019E0; |
| mbed_official | 235:685d5f11838f | 426 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| mbed_official | 235:685d5f11838f | 427 | |
| mbed_official | 235:685d5f11838f | 428 | /* SDRAM initialization sequence */ |
| mbed_official | 235:685d5f11838f | 429 | /* Clock enable command */ |
| mbed_official | 235:685d5f11838f | 430 | FMC_Bank5_6->SDCMR = 0x00000011; |
| mbed_official | 235:685d5f11838f | 431 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 235:685d5f11838f | 432 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 235:685d5f11838f | 433 | { |
| mbed_official | 235:685d5f11838f | 434 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 235:685d5f11838f | 435 | } |
| mbed_official | 235:685d5f11838f | 436 | |
| mbed_official | 235:685d5f11838f | 437 | /* Delay */ |
| mbed_official | 235:685d5f11838f | 438 | for (index = 0; index<1000; index++); |
| mbed_official | 235:685d5f11838f | 439 | |
| mbed_official | 235:685d5f11838f | 440 | /* PALL command */ |
| mbed_official | 235:685d5f11838f | 441 | FMC_Bank5_6->SDCMR = 0x00000012; |
| mbed_official | 235:685d5f11838f | 442 | timeout = 0xFFFF; |
| mbed_official | 235:685d5f11838f | 443 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 235:685d5f11838f | 444 | { |
| mbed_official | 235:685d5f11838f | 445 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 235:685d5f11838f | 446 | } |
| mbed_official | 235:685d5f11838f | 447 | |
| mbed_official | 235:685d5f11838f | 448 | /* Auto refresh command */ |
| mbed_official | 235:685d5f11838f | 449 | FMC_Bank5_6->SDCMR = 0x00000073; |
| mbed_official | 235:685d5f11838f | 450 | timeout = 0xFFFF; |
| mbed_official | 235:685d5f11838f | 451 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 235:685d5f11838f | 452 | { |
| mbed_official | 235:685d5f11838f | 453 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 235:685d5f11838f | 454 | } |
| mbed_official | 235:685d5f11838f | 455 | |
| mbed_official | 235:685d5f11838f | 456 | /* MRD register program */ |
| mbed_official | 235:685d5f11838f | 457 | FMC_Bank5_6->SDCMR = 0x00046014; |
| mbed_official | 235:685d5f11838f | 458 | timeout = 0xFFFF; |
| mbed_official | 235:685d5f11838f | 459 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 235:685d5f11838f | 460 | { |
| mbed_official | 235:685d5f11838f | 461 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 235:685d5f11838f | 462 | } |
| mbed_official | 235:685d5f11838f | 463 | |
| mbed_official | 235:685d5f11838f | 464 | /* Set refresh count */ |
| mbed_official | 235:685d5f11838f | 465 | tmpreg = FMC_Bank5_6->SDRTR; |
| mbed_official | 235:685d5f11838f | 466 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| mbed_official | 235:685d5f11838f | 467 | |
| mbed_official | 235:685d5f11838f | 468 | /* Disable write protection */ |
| mbed_official | 235:685d5f11838f | 469 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| mbed_official | 235:685d5f11838f | 470 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| mbed_official | 235:685d5f11838f | 471 | #endif /* DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 472 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 473 | |
| mbed_official | 235:685d5f11838f | 474 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 475 | #if defined(DATA_IN_ExtSRAM) |
| mbed_official | 235:685d5f11838f | 476 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 477 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| mbed_official | 235:685d5f11838f | 478 | RCC->AHB1ENR |= 0x00000078; |
| mbed_official | 235:685d5f11838f | 479 | |
| mbed_official | 235:685d5f11838f | 480 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 481 | GPIOD->AFR[0] = 0x00CCC0CC; |
| mbed_official | 235:685d5f11838f | 482 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 483 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 484 | GPIOD->MODER = 0xAAAA0A8A; |
| mbed_official | 235:685d5f11838f | 485 | /* Configure PDx pins speed to 100 MHz */ |
| mbed_official | 235:685d5f11838f | 486 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| mbed_official | 235:685d5f11838f | 487 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 488 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 489 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 235:685d5f11838f | 490 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 491 | |
| mbed_official | 235:685d5f11838f | 492 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 493 | GPIOE->AFR[0] = 0xC00CC0CC; |
| mbed_official | 235:685d5f11838f | 494 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 235:685d5f11838f | 495 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 496 | GPIOE->MODER = 0xAAAA828A; |
| mbed_official | 235:685d5f11838f | 497 | /* Configure PEx pins speed to 100 MHz */ |
| mbed_official | 235:685d5f11838f | 498 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| mbed_official | 235:685d5f11838f | 499 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 500 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 501 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 235:685d5f11838f | 502 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 503 | |
| mbed_official | 235:685d5f11838f | 504 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 505 | GPIOF->AFR[0] = 0x00CCCCCC; |
| mbed_official | 235:685d5f11838f | 506 | GPIOF->AFR[1] = 0xCCCC0000; |
| mbed_official | 235:685d5f11838f | 507 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 508 | GPIOF->MODER = 0xAA000AAA; |
| mbed_official | 235:685d5f11838f | 509 | /* Configure PFx pins speed to 100 MHz */ |
| mbed_official | 235:685d5f11838f | 510 | GPIOF->OSPEEDR = 0xFF000FFF; |
| mbed_official | 235:685d5f11838f | 511 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 512 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 513 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 235:685d5f11838f | 514 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 515 | |
| mbed_official | 235:685d5f11838f | 516 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 235:685d5f11838f | 517 | GPIOG->AFR[0] = 0x00CCCCCC; |
| mbed_official | 235:685d5f11838f | 518 | GPIOG->AFR[1] = 0x000000C0; |
| mbed_official | 235:685d5f11838f | 519 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 235:685d5f11838f | 520 | GPIOG->MODER = 0x00085AAA; |
| mbed_official | 235:685d5f11838f | 521 | /* Configure PGx pins speed to 100 MHz */ |
| mbed_official | 235:685d5f11838f | 522 | GPIOG->OSPEEDR = 0x000CAFFF; |
| mbed_official | 235:685d5f11838f | 523 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 235:685d5f11838f | 524 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 235:685d5f11838f | 525 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 235:685d5f11838f | 526 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 527 | |
| mbed_official | 235:685d5f11838f | 528 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 529 | /* Enable the FMC/FSMC interface clock */ |
| mbed_official | 235:685d5f11838f | 530 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 235:685d5f11838f | 531 | |
| mbed_official | 235:685d5f11838f | 532 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 235:685d5f11838f | 533 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 235:685d5f11838f | 534 | FMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 235:685d5f11838f | 535 | FMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 235:685d5f11838f | 536 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| mbed_official | 235:685d5f11838f | 537 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 538 | |
| mbed_official | 235:685d5f11838f | 539 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 235:685d5f11838f | 540 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 235:685d5f11838f | 541 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 235:685d5f11838f | 542 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 235:685d5f11838f | 543 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| mbed_official | 235:685d5f11838f | 544 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| mbed_official | 235:685d5f11838f | 545 | |
| mbed_official | 235:685d5f11838f | 546 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 235:685d5f11838f | 547 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 548 | } |
| mbed_official | 235:685d5f11838f | 549 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 235:685d5f11838f | 550 | |
| mbed_official | 235:685d5f11838f | 551 | /** |
| mbed_official | 235:685d5f11838f | 552 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 235:685d5f11838f | 553 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 235:685d5f11838f | 554 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 235:685d5f11838f | 555 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 235:685d5f11838f | 556 | * @param None |
| mbed_official | 235:685d5f11838f | 557 | * @retval None |
| mbed_official | 235:685d5f11838f | 558 | */ |
| mbed_official | 235:685d5f11838f | 559 | void SetSysClock(void) |
| mbed_official | 235:685d5f11838f | 560 | { |
| mbed_official | 235:685d5f11838f | 561 | /* 1- Try to start with HSE and external clock */ |
| mbed_official | 235:685d5f11838f | 562 | #if USE_PLL_HSE_EXTC != 0 |
| mbed_official | 235:685d5f11838f | 563 | if (SetSysClock_PLL_HSE(1) == 0) |
| mbed_official | 235:685d5f11838f | 564 | #endif |
| mbed_official | 235:685d5f11838f | 565 | { |
| mbed_official | 235:685d5f11838f | 566 | /* 2- If fail try to start with HSE and external xtal */ |
| mbed_official | 235:685d5f11838f | 567 | #if USE_PLL_HSE_XTAL != 0 |
| mbed_official | 235:685d5f11838f | 568 | if (SetSysClock_PLL_HSE(0) == 0) |
| mbed_official | 235:685d5f11838f | 569 | #endif |
| mbed_official | 235:685d5f11838f | 570 | { |
| mbed_official | 235:685d5f11838f | 571 | /* 3- If fail start with HSI clock */ |
| mbed_official | 235:685d5f11838f | 572 | if (SetSysClock_PLL_HSI() == 0) |
| mbed_official | 235:685d5f11838f | 573 | { |
| mbed_official | 235:685d5f11838f | 574 | while(1) |
| mbed_official | 235:685d5f11838f | 575 | { |
| mbed_official | 235:685d5f11838f | 576 | // [TODO] Put something here to tell the user that a problem occured... |
| mbed_official | 235:685d5f11838f | 577 | } |
| mbed_official | 235:685d5f11838f | 578 | } |
| mbed_official | 235:685d5f11838f | 579 | } |
| mbed_official | 235:685d5f11838f | 580 | } |
| mbed_official | 235:685d5f11838f | 581 | |
| mbed_official | 235:685d5f11838f | 582 | /* Output clock on MCO2 pin(PC9) for debugging purpose */ |
| mbed_official | 235:685d5f11838f | 583 | //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz |
| mbed_official | 235:685d5f11838f | 584 | } |
| mbed_official | 235:685d5f11838f | 585 | |
| mbed_official | 235:685d5f11838f | 586 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| mbed_official | 235:685d5f11838f | 587 | /******************************************************************************/ |
| mbed_official | 235:685d5f11838f | 588 | /* PLL (clocked by HSE) used as System clock source */ |
| mbed_official | 235:685d5f11838f | 589 | /******************************************************************************/ |
| mbed_official | 235:685d5f11838f | 590 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| mbed_official | 235:685d5f11838f | 591 | { |
| mbed_official | 235:685d5f11838f | 592 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 235:685d5f11838f | 593 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 235:685d5f11838f | 594 | |
| mbed_official | 235:685d5f11838f | 595 | /* The voltage scaling allows optimizing the power consumption when the device is |
| mbed_official | 235:685d5f11838f | 596 | clocked below the maximum system frequency, to update the voltage scaling value |
| mbed_official | 235:685d5f11838f | 597 | regarding system frequency refer to product datasheet. */ |
| mbed_official | 235:685d5f11838f | 598 | __PWR_CLK_ENABLE(); |
| mbed_official | 235:685d5f11838f | 599 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); |
| mbed_official | 235:685d5f11838f | 600 | |
| mbed_official | 235:685d5f11838f | 601 | /* Enable HSE oscillator and activate PLL with HSE as source */ |
| mbed_official | 235:685d5f11838f | 602 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 235:685d5f11838f | 603 | if (bypass == 0) |
| mbed_official | 235:685d5f11838f | 604 | { |
| mbed_official | 235:685d5f11838f | 605 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
| mbed_official | 235:685d5f11838f | 606 | } |
| mbed_official | 235:685d5f11838f | 607 | else |
| mbed_official | 235:685d5f11838f | 608 | { |
| mbed_official | 235:685d5f11838f | 609 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
| mbed_official | 235:685d5f11838f | 610 | } |
| mbed_official | 235:685d5f11838f | 611 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 235:685d5f11838f | 612 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 235:685d5f11838f | 613 | //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8) |
| mbed_official | 235:685d5f11838f | 614 | //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) |
| mbed_official | 235:685d5f11838f | 615 | RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4) |
| mbed_official | 235:685d5f11838f | 616 | RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) |
| mbed_official | 235:685d5f11838f | 617 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) |
| mbed_official | 235:685d5f11838f | 618 | RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB |
| mbed_official | 235:685d5f11838f | 619 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 235:685d5f11838f | 620 | { |
| mbed_official | 235:685d5f11838f | 621 | return 0; // FAIL |
| mbed_official | 235:685d5f11838f | 622 | } |
| mbed_official | 235:685d5f11838f | 623 | |
| mbed_official | 235:685d5f11838f | 624 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 235:685d5f11838f | 625 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 235:685d5f11838f | 626 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz |
| mbed_official | 235:685d5f11838f | 627 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz |
| mbed_official | 235:685d5f11838f | 628 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz |
| mbed_official | 235:685d5f11838f | 629 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz |
| mbed_official | 235:685d5f11838f | 630 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) |
| mbed_official | 235:685d5f11838f | 631 | { |
| mbed_official | 235:685d5f11838f | 632 | return 0; // FAIL |
| mbed_official | 235:685d5f11838f | 633 | } |
| mbed_official | 235:685d5f11838f | 634 | |
| mbed_official | 235:685d5f11838f | 635 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 235:685d5f11838f | 636 | |
| mbed_official | 235:685d5f11838f | 637 | //if (bypass == 0) |
| mbed_official | 235:685d5f11838f | 638 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal |
| mbed_official | 235:685d5f11838f | 639 | //else |
| mbed_official | 235:685d5f11838f | 640 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock |
| mbed_official | 235:685d5f11838f | 641 | |
| mbed_official | 235:685d5f11838f | 642 | return 1; // OK |
| mbed_official | 235:685d5f11838f | 643 | } |
| mbed_official | 235:685d5f11838f | 644 | #endif |
| mbed_official | 235:685d5f11838f | 645 | |
| mbed_official | 235:685d5f11838f | 646 | /******************************************************************************/ |
| mbed_official | 235:685d5f11838f | 647 | /* PLL (clocked by HSI) used as System clock source */ |
| mbed_official | 235:685d5f11838f | 648 | /******************************************************************************/ |
| mbed_official | 235:685d5f11838f | 649 | uint8_t SetSysClock_PLL_HSI(void) |
| mbed_official | 235:685d5f11838f | 650 | { |
| mbed_official | 235:685d5f11838f | 651 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 235:685d5f11838f | 652 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 235:685d5f11838f | 653 | |
| mbed_official | 235:685d5f11838f | 654 | /* The voltage scaling allows optimizing the power consumption when the device is |
| mbed_official | 235:685d5f11838f | 655 | clocked below the maximum system frequency, to update the voltage scaling value |
| mbed_official | 235:685d5f11838f | 656 | regarding system frequency refer to product datasheet. */ |
| mbed_official | 235:685d5f11838f | 657 | __PWR_CLK_ENABLE(); |
| mbed_official | 235:685d5f11838f | 658 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); |
| mbed_official | 235:685d5f11838f | 659 | |
| mbed_official | 235:685d5f11838f | 660 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
| mbed_official | 235:685d5f11838f | 661 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 235:685d5f11838f | 662 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| mbed_official | 235:685d5f11838f | 663 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| mbed_official | 235:685d5f11838f | 664 | RCC_OscInitStruct.HSICalibrationValue = 16; |
| mbed_official | 235:685d5f11838f | 665 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 235:685d5f11838f | 666 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
| mbed_official | 235:685d5f11838f | 667 | //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) |
| mbed_official | 235:685d5f11838f | 668 | //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400) |
| mbed_official | 235:685d5f11838f | 669 | RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8) |
| mbed_official | 235:685d5f11838f | 670 | RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200) |
| mbed_official | 235:685d5f11838f | 671 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4) |
| mbed_official | 235:685d5f11838f | 672 | RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB |
| mbed_official | 235:685d5f11838f | 673 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| mbed_official | 235:685d5f11838f | 674 | { |
| mbed_official | 235:685d5f11838f | 675 | return 0; // FAIL |
| mbed_official | 235:685d5f11838f | 676 | } |
| mbed_official | 235:685d5f11838f | 677 | |
| mbed_official | 235:685d5f11838f | 678 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| mbed_official | 235:685d5f11838f | 679 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| mbed_official | 235:685d5f11838f | 680 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz |
| mbed_official | 235:685d5f11838f | 681 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz |
| mbed_official | 235:685d5f11838f | 682 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz |
| mbed_official | 235:685d5f11838f | 683 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz |
| mbed_official | 235:685d5f11838f | 684 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) |
| mbed_official | 235:685d5f11838f | 685 | { |
| mbed_official | 235:685d5f11838f | 686 | return 0; // FAIL |
| mbed_official | 235:685d5f11838f | 687 | } |
| mbed_official | 235:685d5f11838f | 688 | |
| mbed_official | 235:685d5f11838f | 689 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| mbed_official | 235:685d5f11838f | 690 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
| mbed_official | 235:685d5f11838f | 691 | |
| mbed_official | 235:685d5f11838f | 692 | return 1; // OK |
| mbed_official | 235:685d5f11838f | 693 | } |
| mbed_official | 235:685d5f11838f | 694 | |
| mbed_official | 235:685d5f11838f | 695 | /** |
| mbed_official | 235:685d5f11838f | 696 | * @} |
| mbed_official | 235:685d5f11838f | 697 | */ |
| mbed_official | 235:685d5f11838f | 698 | |
| mbed_official | 235:685d5f11838f | 699 | /** |
| mbed_official | 235:685d5f11838f | 700 | * @} |
| mbed_official | 235:685d5f11838f | 701 | */ |
| mbed_official | 235:685d5f11838f | 702 | |
| mbed_official | 235:685d5f11838f | 703 | /** |
| mbed_official | 235:685d5f11838f | 704 | * @} |
| mbed_official | 235:685d5f11838f | 705 | */ |
| mbed_official | 235:685d5f11838f | 706 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |