Giorgos Tsapparellas / SX1272Lib

Driver for the SX1272 RF Transceiver

Dependents:   LoRaWAN_mbed_lmic_agriculture_app

Fork of SX1272Lib by Semtech

registers/sx1272Regs-LoRa.h@8:60c42278731e, 2018-04-02 (annotated)

Committer:
GTsapparellas
Date:
Mon Apr 02 12:06:02 2018 +0000
Revision:
8:60c42278731e
Parent:
0:45c4f0364ca4 
SX1272MB2xAS LoRa shield attached on FRDM-K64F ARM mbed board.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: SX1272 LoRa modem registers and bits definitions
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainer: Miguel Luis and Gregory Cristian
GTsapparellas 8:60c42278731e 14 /////////////////////////////////////////////////////////////////////////////
GTsapparellas 8:60c42278731e 15
GTsapparellas 8:60c42278731e 16 Used by Giorgos Tsapparellas for Internet of Things (IoT) smart monitoring
GTsapparellas 8:60c42278731e 17 device for agriculture using LoRaWAN technology.
GTsapparellas 8:60c42278731e 18
GTsapparellas 8:60c42278731e 19 Date of issued copy: 20 January 2018
GTsapparellas 8:60c42278731e 20
GTsapparellas 8:60c42278731e 21 Modifications:
GTsapparellas 8:60c42278731e 22 - No external modifications of the existing "AS IT IS" software.
mluis 0:45c4f0364ca4 23 */
mluis 0:45c4f0364ca4 24 #ifndef __SX1272_REGS_LORA_H__
mluis 0:45c4f0364ca4 25 #define __SX1272_REGS_LORA_H__
mluis 0:45c4f0364ca4 26
mluis 0:45c4f0364ca4 27 /*!
mluis 0:45c4f0364ca4 28 * ============================================================================
mluis 0:45c4f0364ca4 29 * SX1272 Internal registers Address
mluis 0:45c4f0364ca4 30 * ============================================================================
mluis 0:45c4f0364ca4 31 */
mluis 0:45c4f0364ca4 32 #define REG_LR_FIFO 0x00
mluis 0:45c4f0364ca4 33 // Common settings
mluis 0:45c4f0364ca4 34 #define REG_LR_OPMODE 0x01
mluis 0:45c4f0364ca4 35 #define REG_LR_FRFMSB 0x06
mluis 0:45c4f0364ca4 36 #define REG_LR_FRFMID 0x07
mluis 0:45c4f0364ca4 37 #define REG_LR_FRFLSB 0x08
mluis 0:45c4f0364ca4 38 // Tx settings
mluis 0:45c4f0364ca4 39 #define REG_LR_PACONFIG 0x09
mluis 0:45c4f0364ca4 40 #define REG_LR_PARAMP 0x0A
mluis 0:45c4f0364ca4 41 #define REG_LR_OCP 0x0B
mluis 0:45c4f0364ca4 42 // Rx settings
mluis 0:45c4f0364ca4 43 #define REG_LR_LNA 0x0C
mluis 0:45c4f0364ca4 44 // LoRa registers
mluis 0:45c4f0364ca4 45 #define REG_LR_FIFOADDRPTR 0x0D
mluis 0:45c4f0364ca4 46 #define REG_LR_FIFOTXBASEADDR 0x0E
mluis 0:45c4f0364ca4 47 #define REG_LR_FIFORXBASEADDR 0x0F
mluis 0:45c4f0364ca4 48 #define REG_LR_FIFORXCURRENTADDR 0x10
mluis 0:45c4f0364ca4 49 #define REG_LR_IRQFLAGSMASK 0x11
mluis 0:45c4f0364ca4 50 #define REG_LR_IRQFLAGS 0x12
mluis 0:45c4f0364ca4 51 #define REG_LR_RXNBBYTES 0x13
mluis 0:45c4f0364ca4 52 #define REG_LR_RXHEADERCNTVALUEMSB 0x14
mluis 0:45c4f0364ca4 53 #define REG_LR_RXHEADERCNTVALUELSB 0x15
mluis 0:45c4f0364ca4 54 #define REG_LR_RXPACKETCNTVALUEMSB 0x16
mluis 0:45c4f0364ca4 55 #define REG_LR_RXPACKETCNTVALUELSB 0x17
mluis 0:45c4f0364ca4 56 #define REG_LR_MODEMSTAT 0x18
mluis 0:45c4f0364ca4 57 #define REG_LR_PKTSNRVALUE 0x19
mluis 0:45c4f0364ca4 58 #define REG_LR_PKTRSSIVALUE 0x1A
mluis 0:45c4f0364ca4 59 #define REG_LR_RSSIVALUE 0x1B
mluis 0:45c4f0364ca4 60 #define REG_LR_HOPCHANNEL 0x1C
mluis 0:45c4f0364ca4 61 #define REG_LR_MODEMCONFIG1 0x1D
mluis 0:45c4f0364ca4 62 #define REG_LR_MODEMCONFIG2 0x1E
mluis 0:45c4f0364ca4 63 #define REG_LR_SYMBTIMEOUTLSB 0x1F
mluis 0:45c4f0364ca4 64 #define REG_LR_PREAMBLEMSB 0x20
mluis 0:45c4f0364ca4 65 #define REG_LR_PREAMBLELSB 0x21
mluis 0:45c4f0364ca4 66 #define REG_LR_PAYLOADLENGTH 0x22
mluis 0:45c4f0364ca4 67 #define REG_LR_PAYLOADMAXLENGTH 0x23
mluis 0:45c4f0364ca4 68 #define REG_LR_HOPPERIOD 0x24
mluis 0:45c4f0364ca4 69 #define REG_LR_FIFORXBYTEADDR 0x25
mluis 0:45c4f0364ca4 70 #define REG_LR_FEIMSB 0x28
mluis 0:45c4f0364ca4 71 #define REG_LR_FEIMID 0x29
mluis 0:45c4f0364ca4 72 #define REG_LR_FEILSB 0x2A
mluis 0:45c4f0364ca4 73 #define REG_LR_RSSIWIDEBAND 0x2C
mluis 0:45c4f0364ca4 74 #define REG_LR_DETECTOPTIMIZE 0x31
mluis 0:45c4f0364ca4 75 #define REG_LR_INVERTIQ 0x33
mluis 0:45c4f0364ca4 76 #define REG_LR_DETECTIONTHRESHOLD 0x37
mluis 0:45c4f0364ca4 77 #define REG_LR_SYNCWORD 0x39
mluis 0:45c4f0364ca4 78 #define REG_LR_INVERTIQ2 0x3B
mluis 0:45c4f0364ca4 79
mluis 0:45c4f0364ca4 80 // end of documented register in datasheet
mluis 0:45c4f0364ca4 81 // I/O settings
mluis 0:45c4f0364ca4 82 #define REG_LR_DIOMAPPING1 0x40
mluis 0:45c4f0364ca4 83 #define REG_LR_DIOMAPPING2 0x41
mluis 0:45c4f0364ca4 84 // Version
mluis 0:45c4f0364ca4 85 #define REG_LR_VERSION 0x42
mluis 0:45c4f0364ca4 86 // Additional settings
mluis 0:45c4f0364ca4 87 #define REG_LR_AGCREF 0x43
mluis 0:45c4f0364ca4 88 #define REG_LR_AGCTHRESH1 0x44
mluis 0:45c4f0364ca4 89 #define REG_LR_AGCTHRESH2 0x45
mluis 0:45c4f0364ca4 90 #define REG_LR_AGCTHRESH3 0x46
mluis 0:45c4f0364ca4 91 #define REG_LR_PLLHOP 0x4B
mluis 0:45c4f0364ca4 92 #define REG_LR_TCXO 0x58
mluis 0:45c4f0364ca4 93 #define REG_LR_PADAC 0x5A
mluis 0:45c4f0364ca4 94 #define REG_LR_PLL 0x5C
mluis 0:45c4f0364ca4 95 #define REG_LR_PLLLOWPN 0x5E
mluis 0:45c4f0364ca4 96 #define REG_LR_FORMERTEMP 0x6C
mluis 0:45c4f0364ca4 97
mluis 0:45c4f0364ca4 98 /*!
mluis 0:45c4f0364ca4 99 * ============================================================================
mluis 0:45c4f0364ca4 100 * SX1272 LoRa bits control definition
mluis 0:45c4f0364ca4 101 * ============================================================================
mluis 0:45c4f0364ca4 102 */
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 /*!
mluis 0:45c4f0364ca4 105 * RegFifo
mluis 0:45c4f0364ca4 106 */
mluis 0:45c4f0364ca4 107
mluis 0:45c4f0364ca4 108 /*!
mluis 0:45c4f0364ca4 109 * RegOpMode
mluis 0:45c4f0364ca4 110 */
mluis 0:45c4f0364ca4 111 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F
mluis 0:45c4f0364ca4 112 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default
mluis 0:45c4f0364ca4 113 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80
mluis 0:45c4f0364ca4 114
mluis 0:45c4f0364ca4 115 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF
mluis 0:45c4f0364ca4 116 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40
mluis 0:45c4f0364ca4 117 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default
mluis 0:45c4f0364ca4 118
mluis 0:45c4f0364ca4 119 #define RFLR_OPMODE_MASK 0xF8
mluis 0:45c4f0364ca4 120 #define RFLR_OPMODE_SLEEP 0x00
mluis 0:45c4f0364ca4 121 #define RFLR_OPMODE_STANDBY 0x01 // Default
mluis 0:45c4f0364ca4 122 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02
mluis 0:45c4f0364ca4 123 #define RFLR_OPMODE_TRANSMITTER 0x03
mluis 0:45c4f0364ca4 124 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04
mluis 0:45c4f0364ca4 125 #define RFLR_OPMODE_RECEIVER 0x05
mluis 0:45c4f0364ca4 126 // LoRa specific modes
mluis 0:45c4f0364ca4 127 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06
mluis 0:45c4f0364ca4 128 #define RFLR_OPMODE_CAD 0x07
mluis 0:45c4f0364ca4 129
mluis 0:45c4f0364ca4 130 /*!
mluis 0:45c4f0364ca4 131 * RegFrf (MHz)
mluis 0:45c4f0364ca4 132 */
mluis 0:45c4f0364ca4 133 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default
mluis 0:45c4f0364ca4 134 #define RFLR_FRFMID_915_MHZ 0xC0 // Default
mluis 0:45c4f0364ca4 135 #define RFLR_FRFLSB_915_MHZ 0x00 // Default
mluis 0:45c4f0364ca4 136
mluis 0:45c4f0364ca4 137 /*!
mluis 0:45c4f0364ca4 138 * RegPaConfig
mluis 0:45c4f0364ca4 139 */
mluis 0:45c4f0364ca4 140 #define RFLR_PACONFIG_PASELECT_MASK 0x7F
mluis 0:45c4f0364ca4 141 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80
mluis 0:45c4f0364ca4 142 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default
mluis 0:45c4f0364ca4 143
mluis 0:45c4f0364ca4 144 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0
mluis 0:45c4f0364ca4 145
mluis 0:45c4f0364ca4 146 /*!
mluis 0:45c4f0364ca4 147 * RegPaRamp
mluis 0:45c4f0364ca4 148 */
mluis 0:45c4f0364ca4 149 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0
mluis 0:45c4f0364ca4 150 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default
mluis 0:45c4f0364ca4 151 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00
mluis 0:45c4f0364ca4 152
mluis 0:45c4f0364ca4 153 #define RFLR_PARAMP_MASK 0xF0
mluis 0:45c4f0364ca4 154 #define RFLR_PARAMP_3400_US 0x00
mluis 0:45c4f0364ca4 155 #define RFLR_PARAMP_2000_US 0x01
mluis 0:45c4f0364ca4 156 #define RFLR_PARAMP_1000_US 0x02
mluis 0:45c4f0364ca4 157 #define RFLR_PARAMP_0500_US 0x03
mluis 0:45c4f0364ca4 158 #define RFLR_PARAMP_0250_US 0x04
mluis 0:45c4f0364ca4 159 #define RFLR_PARAMP_0125_US 0x05
mluis 0:45c4f0364ca4 160 #define RFLR_PARAMP_0100_US 0x06
mluis 0:45c4f0364ca4 161 #define RFLR_PARAMP_0062_US 0x07
mluis 0:45c4f0364ca4 162 #define RFLR_PARAMP_0050_US 0x08
mluis 0:45c4f0364ca4 163 #define RFLR_PARAMP_0040_US 0x09 // Default
mluis 0:45c4f0364ca4 164 #define RFLR_PARAMP_0031_US 0x0A
mluis 0:45c4f0364ca4 165 #define RFLR_PARAMP_0025_US 0x0B
mluis 0:45c4f0364ca4 166 #define RFLR_PARAMP_0020_US 0x0C
mluis 0:45c4f0364ca4 167 #define RFLR_PARAMP_0015_US 0x0D
mluis 0:45c4f0364ca4 168 #define RFLR_PARAMP_0012_US 0x0E
mluis 0:45c4f0364ca4 169 #define RFLR_PARAMP_0010_US 0x0F
mluis 0:45c4f0364ca4 170
mluis 0:45c4f0364ca4 171 /*!
mluis 0:45c4f0364ca4 172 * RegOcp
mluis 0:45c4f0364ca4 173 */
mluis 0:45c4f0364ca4 174 #define RFLR_OCP_MASK 0xDF
mluis 0:45c4f0364ca4 175 #define RFLR_OCP_ON 0x20 // Default
mluis 0:45c4f0364ca4 176 #define RFLR_OCP_OFF 0x00
mluis 0:45c4f0364ca4 177
mluis 0:45c4f0364ca4 178 #define RFLR_OCP_TRIM_MASK 0xE0
mluis 0:45c4f0364ca4 179 #define RFLR_OCP_TRIM_045_MA 0x00
mluis 0:45c4f0364ca4 180 #define RFLR_OCP_TRIM_050_MA 0x01
mluis 0:45c4f0364ca4 181 #define RFLR_OCP_TRIM_055_MA 0x02
mluis 0:45c4f0364ca4 182 #define RFLR_OCP_TRIM_060_MA 0x03
mluis 0:45c4f0364ca4 183 #define RFLR_OCP_TRIM_065_MA 0x04
mluis 0:45c4f0364ca4 184 #define RFLR_OCP_TRIM_070_MA 0x05
mluis 0:45c4f0364ca4 185 #define RFLR_OCP_TRIM_075_MA 0x06
mluis 0:45c4f0364ca4 186 #define RFLR_OCP_TRIM_080_MA 0x07
mluis 0:45c4f0364ca4 187 #define RFLR_OCP_TRIM_085_MA 0x08
mluis 0:45c4f0364ca4 188 #define RFLR_OCP_TRIM_090_MA 0x09
mluis 0:45c4f0364ca4 189 #define RFLR_OCP_TRIM_095_MA 0x0A
mluis 0:45c4f0364ca4 190 #define RFLR_OCP_TRIM_100_MA 0x0B // Default
mluis 0:45c4f0364ca4 191 #define RFLR_OCP_TRIM_105_MA 0x0C
mluis 0:45c4f0364ca4 192 #define RFLR_OCP_TRIM_110_MA 0x0D
mluis 0:45c4f0364ca4 193 #define RFLR_OCP_TRIM_115_MA 0x0E
mluis 0:45c4f0364ca4 194 #define RFLR_OCP_TRIM_120_MA 0x0F
mluis 0:45c4f0364ca4 195 #define RFLR_OCP_TRIM_130_MA 0x10
mluis 0:45c4f0364ca4 196 #define RFLR_OCP_TRIM_140_MA 0x11
mluis 0:45c4f0364ca4 197 #define RFLR_OCP_TRIM_150_MA 0x12
mluis 0:45c4f0364ca4 198 #define RFLR_OCP_TRIM_160_MA 0x13
mluis 0:45c4f0364ca4 199 #define RFLR_OCP_TRIM_170_MA 0x14
mluis 0:45c4f0364ca4 200 #define RFLR_OCP_TRIM_180_MA 0x15
mluis 0:45c4f0364ca4 201 #define RFLR_OCP_TRIM_190_MA 0x16
mluis 0:45c4f0364ca4 202 #define RFLR_OCP_TRIM_200_MA 0x17
mluis 0:45c4f0364ca4 203 #define RFLR_OCP_TRIM_210_MA 0x18
mluis 0:45c4f0364ca4 204 #define RFLR_OCP_TRIM_220_MA 0x19
mluis 0:45c4f0364ca4 205 #define RFLR_OCP_TRIM_230_MA 0x1A
mluis 0:45c4f0364ca4 206 #define RFLR_OCP_TRIM_240_MA 0x1B
mluis 0:45c4f0364ca4 207
mluis 0:45c4f0364ca4 208 /*!
mluis 0:45c4f0364ca4 209 * RegLna
mluis 0:45c4f0364ca4 210 */
mluis 0:45c4f0364ca4 211 #define RFLR_LNA_GAIN_MASK 0x1F
mluis 0:45c4f0364ca4 212 #define RFLR_LNA_GAIN_G1 0x20 // Default
mluis 0:45c4f0364ca4 213 #define RFLR_LNA_GAIN_G2 0x40
mluis 0:45c4f0364ca4 214 #define RFLR_LNA_GAIN_G3 0x60
mluis 0:45c4f0364ca4 215 #define RFLR_LNA_GAIN_G4 0x80
mluis 0:45c4f0364ca4 216 #define RFLR_LNA_GAIN_G5 0xA0
mluis 0:45c4f0364ca4 217 #define RFLR_LNA_GAIN_G6 0xC0
mluis 0:45c4f0364ca4 218
mluis 0:45c4f0364ca4 219 #define RFLR_LNA_BOOST_MASK 0xFC
mluis 0:45c4f0364ca4 220 #define RFLR_LNA_BOOST_OFF 0x00 // Default
mluis 0:45c4f0364ca4 221 #define RFLR_LNA_BOOST_ON 0x03
mluis 0:45c4f0364ca4 222
mluis 0:45c4f0364ca4 223 /*!
mluis 0:45c4f0364ca4 224 * RegFifoAddrPtr
mluis 0:45c4f0364ca4 225 */
mluis 0:45c4f0364ca4 226 #define RFLR_FIFOADDRPTR 0x00 // Default
mluis 0:45c4f0364ca4 227
mluis 0:45c4f0364ca4 228 /*!
mluis 0:45c4f0364ca4 229 * RegFifoTxBaseAddr
mluis 0:45c4f0364ca4 230 */
mluis 0:45c4f0364ca4 231 #define RFLR_FIFOTXBASEADDR 0x80 // Default
mluis 0:45c4f0364ca4 232
mluis 0:45c4f0364ca4 233 /*!
mluis 0:45c4f0364ca4 234 * RegFifoTxBaseAddr
mluis 0:45c4f0364ca4 235 */
mluis 0:45c4f0364ca4 236 #define RFLR_FIFORXBASEADDR 0x00 // Default
mluis 0:45c4f0364ca4 237
mluis 0:45c4f0364ca4 238 /*!
mluis 0:45c4f0364ca4 239 * RegFifoRxCurrentAddr (Read Only)
mluis 0:45c4f0364ca4 240 */
mluis 0:45c4f0364ca4 241
mluis 0:45c4f0364ca4 242 /*!
mluis 0:45c4f0364ca4 243 * RegIrqFlagsMask
mluis 0:45c4f0364ca4 244 */
mluis 0:45c4f0364ca4 245 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80
mluis 0:45c4f0364ca4 246 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40
mluis 0:45c4f0364ca4 247 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20
mluis 0:45c4f0364ca4 248 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10
mluis 0:45c4f0364ca4 249 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08
mluis 0:45c4f0364ca4 250 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04
mluis 0:45c4f0364ca4 251 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02
mluis 0:45c4f0364ca4 252 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01
mluis 0:45c4f0364ca4 253
mluis 0:45c4f0364ca4 254 /*!
mluis 0:45c4f0364ca4 255 * RegIrqFlags
mluis 0:45c4f0364ca4 256 */
mluis 0:45c4f0364ca4 257 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80
mluis 0:45c4f0364ca4 258 #define RFLR_IRQFLAGS_RXDONE 0x40
mluis 0:45c4f0364ca4 259 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20
mluis 0:45c4f0364ca4 260 #define RFLR_IRQFLAGS_VALIDHEADER 0x10
mluis 0:45c4f0364ca4 261 #define RFLR_IRQFLAGS_TXDONE 0x08
mluis 0:45c4f0364ca4 262 #define RFLR_IRQFLAGS_CADDONE 0x04
mluis 0:45c4f0364ca4 263 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02
mluis 0:45c4f0364ca4 264 #define RFLR_IRQFLAGS_CADDETECTED 0x01
mluis 0:45c4f0364ca4 265
mluis 0:45c4f0364ca4 266 /*!
mluis 0:45c4f0364ca4 267 * RegFifoRxNbBytes (Read Only)
mluis 0:45c4f0364ca4 268 */
mluis 0:45c4f0364ca4 269
mluis 0:45c4f0364ca4 270 /*!
mluis 0:45c4f0364ca4 271 * RegRxHeaderCntValueMsb (Read Only)
mluis 0:45c4f0364ca4 272 */
mluis 0:45c4f0364ca4 273
mluis 0:45c4f0364ca4 274 /*!
mluis 0:45c4f0364ca4 275 * RegRxHeaderCntValueLsb (Read Only)
mluis 0:45c4f0364ca4 276 */
mluis 0:45c4f0364ca4 277
mluis 0:45c4f0364ca4 278 /*!
mluis 0:45c4f0364ca4 279 * RegRxPacketCntValueMsb (Read Only)
mluis 0:45c4f0364ca4 280 */
mluis 0:45c4f0364ca4 281
mluis 0:45c4f0364ca4 282 /*!
mluis 0:45c4f0364ca4 283 * RegRxPacketCntValueLsb (Read Only)
mluis 0:45c4f0364ca4 284 */
mluis 0:45c4f0364ca4 285
mluis 0:45c4f0364ca4 286 /*!
mluis 0:45c4f0364ca4 287 * RegModemStat (Read Only)
mluis 0:45c4f0364ca4 288 */
mluis 0:45c4f0364ca4 289 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F
mluis 0:45c4f0364ca4 290 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0
mluis 0:45c4f0364ca4 291
mluis 0:45c4f0364ca4 292 /*!
mluis 0:45c4f0364ca4 293 * RegPktSnrValue (Read Only)
mluis 0:45c4f0364ca4 294 */
mluis 0:45c4f0364ca4 295
mluis 0:45c4f0364ca4 296 /*!
mluis 0:45c4f0364ca4 297 * RegPktRssiValue (Read Only)
mluis 0:45c4f0364ca4 298 */
mluis 0:45c4f0364ca4 299
mluis 0:45c4f0364ca4 300 /*!
mluis 0:45c4f0364ca4 301 * RegRssiValue (Read Only)
mluis 0:45c4f0364ca4 302 */
mluis 0:45c4f0364ca4 303
mluis 0:45c4f0364ca4 304 /*!
mluis 0:45c4f0364ca4 305 * RegHopChannel (Read Only)
mluis 0:45c4f0364ca4 306 */
mluis 0:45c4f0364ca4 307 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F
mluis 0:45c4f0364ca4 308 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80
mluis 0:45c4f0364ca4 309 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default
mluis 0:45c4f0364ca4 310
mluis 0:45c4f0364ca4 311 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF
mluis 0:45c4f0364ca4 312 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40
mluis 0:45c4f0364ca4 313 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default
mluis 0:45c4f0364ca4 314
mluis 0:45c4f0364ca4 315 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F
mluis 0:45c4f0364ca4 316
mluis 0:45c4f0364ca4 317 /*!
mluis 0:45c4f0364ca4 318 * RegModemConfig1
mluis 0:45c4f0364ca4 319 */
mluis 0:45c4f0364ca4 320 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F
mluis 0:45c4f0364ca4 321 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default
mluis 0:45c4f0364ca4 322 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40
mluis 0:45c4f0364ca4 323 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80
mluis 0:45c4f0364ca4 324
mluis 0:45c4f0364ca4 325 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7
mluis 0:45c4f0364ca4 326 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08
mluis 0:45c4f0364ca4 327 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default
mluis 0:45c4f0364ca4 328 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18
mluis 0:45c4f0364ca4 329 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20
mluis 0:45c4f0364ca4 330
mluis 0:45c4f0364ca4 331 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB
mluis 0:45c4f0364ca4 332 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04
mluis 0:45c4f0364ca4 333 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default
mluis 0:45c4f0364ca4 334
mluis 0:45c4f0364ca4 335 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD
mluis 0:45c4f0364ca4 336 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02
mluis 0:45c4f0364ca4 337 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default
mluis 0:45c4f0364ca4 338
mluis 0:45c4f0364ca4 339 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE
mluis 0:45c4f0364ca4 340 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01
mluis 0:45c4f0364ca4 341 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default
mluis 0:45c4f0364ca4 342
mluis 0:45c4f0364ca4 343 /*!
mluis 0:45c4f0364ca4 344 * RegModemConfig2
mluis 0:45c4f0364ca4 345 */
mluis 0:45c4f0364ca4 346 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F
mluis 0:45c4f0364ca4 347 #define RFLR_MODEMCONFIG2_SF_6 0x60
mluis 0:45c4f0364ca4 348 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default
mluis 0:45c4f0364ca4 349 #define RFLR_MODEMCONFIG2_SF_8 0x80
mluis 0:45c4f0364ca4 350 #define RFLR_MODEMCONFIG2_SF_9 0x90
mluis 0:45c4f0364ca4 351 #define RFLR_MODEMCONFIG2_SF_10 0xA0
mluis 0:45c4f0364ca4 352 #define RFLR_MODEMCONFIG2_SF_11 0xB0
mluis 0:45c4f0364ca4 353 #define RFLR_MODEMCONFIG2_SF_12 0xC0
mluis 0:45c4f0364ca4 354
mluis 0:45c4f0364ca4 355 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7
mluis 0:45c4f0364ca4 356 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08
mluis 0:45c4f0364ca4 357 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00
mluis 0:45c4f0364ca4 358
mluis 0:45c4f0364ca4 359 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB
mluis 0:45c4f0364ca4 360 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default
mluis 0:45c4f0364ca4 361 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00
mluis 0:45c4f0364ca4 362
mluis 0:45c4f0364ca4 363 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC
mluis 0:45c4f0364ca4 364 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default
mluis 0:45c4f0364ca4 365
mluis 0:45c4f0364ca4 366 /*!
mluis 0:45c4f0364ca4 367 * RegSymbTimeoutLsb
mluis 0:45c4f0364ca4 368 */
mluis 0:45c4f0364ca4 369 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default
mluis 0:45c4f0364ca4 370
mluis 0:45c4f0364ca4 371 /*!
mluis 0:45c4f0364ca4 372 * RegPreambleLengthMsb
mluis 0:45c4f0364ca4 373 */
mluis 0:45c4f0364ca4 374 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default
mluis 0:45c4f0364ca4 375
mluis 0:45c4f0364ca4 376 /*!
mluis 0:45c4f0364ca4 377 * RegPreambleLengthLsb
mluis 0:45c4f0364ca4 378 */
mluis 0:45c4f0364ca4 379 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default
mluis 0:45c4f0364ca4 380
mluis 0:45c4f0364ca4 381 /*!
mluis 0:45c4f0364ca4 382 * RegPayloadLength
mluis 0:45c4f0364ca4 383 */
mluis 0:45c4f0364ca4 384 #define RFLR_PAYLOADLENGTH 0x0E // Default
mluis 0:45c4f0364ca4 385
mluis 0:45c4f0364ca4 386 /*!
mluis 0:45c4f0364ca4 387 * RegPayloadMaxLength
mluis 0:45c4f0364ca4 388 */
mluis 0:45c4f0364ca4 389 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default
mluis 0:45c4f0364ca4 390
mluis 0:45c4f0364ca4 391 /*!
mluis 0:45c4f0364ca4 392 * RegHopPeriod
mluis 0:45c4f0364ca4 393 */
mluis 0:45c4f0364ca4 394 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default
mluis 0:45c4f0364ca4 395
mluis 0:45c4f0364ca4 396 /*!
mluis 0:45c4f0364ca4 397 * RegFifoRxByteAddr (Read Only)
mluis 0:45c4f0364ca4 398 */
mluis 0:45c4f0364ca4 399
mluis 0:45c4f0364ca4 400 /*!
mluis 0:45c4f0364ca4 401 * RegFeiMsb (Read Only)
mluis 0:45c4f0364ca4 402 */
mluis 0:45c4f0364ca4 403
mluis 0:45c4f0364ca4 404 /*!
mluis 0:45c4f0364ca4 405 * RegFeiMid (Read Only)
mluis 0:45c4f0364ca4 406 */
mluis 0:45c4f0364ca4 407
mluis 0:45c4f0364ca4 408 /*!
mluis 0:45c4f0364ca4 409 * RegFeiLsb (Read Only)
mluis 0:45c4f0364ca4 410 */
mluis 0:45c4f0364ca4 411
mluis 0:45c4f0364ca4 412 /*!
mluis 0:45c4f0364ca4 413 * RegRssiWideband (Read Only)
mluis 0:45c4f0364ca4 414 */
mluis 0:45c4f0364ca4 415
mluis 0:45c4f0364ca4 416 /*!
mluis 0:45c4f0364ca4 417 * RegDetectOptimize
mluis 0:45c4f0364ca4 418 */
mluis 0:45c4f0364ca4 419 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8
mluis 0:45c4f0364ca4 420 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default
mluis 0:45c4f0364ca4 421 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05
mluis 0:45c4f0364ca4 422
mluis 0:45c4f0364ca4 423 /*!
mluis 0:45c4f0364ca4 424 * RegInvertIQ
mluis 0:45c4f0364ca4 425 */
mluis 0:45c4f0364ca4 426 #define RFLR_INVERTIQ_RX_MASK 0xBF
mluis 0:45c4f0364ca4 427 #define RFLR_INVERTIQ_RX_OFF 0x00
mluis 0:45c4f0364ca4 428 #define RFLR_INVERTIQ_RX_ON 0x40
mluis 0:45c4f0364ca4 429 #define RFLR_INVERTIQ_TX_MASK 0xFE
mluis 0:45c4f0364ca4 430 #define RFLR_INVERTIQ_TX_OFF 0x01
mluis 0:45c4f0364ca4 431 #define RFLR_INVERTIQ_TX_ON 0x00
mluis 0:45c4f0364ca4 432
mluis 0:45c4f0364ca4 433 /*!
mluis 0:45c4f0364ca4 434 * RegDetectionThreshold
mluis 0:45c4f0364ca4 435 */
mluis 0:45c4f0364ca4 436 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default
mluis 0:45c4f0364ca4 437 #define RFLR_DETECTIONTHRESH_SF6 0x0C
mluis 0:45c4f0364ca4 438
mluis 0:45c4f0364ca4 439 /*!
mluis 0:45c4f0364ca4 440 * RegInvertIQ2
mluis 0:45c4f0364ca4 441 */
mluis 0:45c4f0364ca4 442 #define RFLR_INVERTIQ2_ON 0x19
mluis 0:45c4f0364ca4 443 #define RFLR_INVERTIQ2_OFF 0x1D
mluis 0:45c4f0364ca4 444
mluis 0:45c4f0364ca4 445 /*!
mluis 0:45c4f0364ca4 446 * RegDioMapping1
mluis 0:45c4f0364ca4 447 */
mluis 0:45c4f0364ca4 448 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F
mluis 0:45c4f0364ca4 449 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default
mluis 0:45c4f0364ca4 450 #define RFLR_DIOMAPPING1_DIO0_01 0x40
mluis 0:45c4f0364ca4 451 #define RFLR_DIOMAPPING1_DIO0_10 0x80
mluis 0:45c4f0364ca4 452 #define RFLR_DIOMAPPING1_DIO0_11 0xC0
mluis 0:45c4f0364ca4 453
mluis 0:45c4f0364ca4 454 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF
mluis 0:45c4f0364ca4 455 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default
mluis 0:45c4f0364ca4 456 #define RFLR_DIOMAPPING1_DIO1_01 0x10
mluis 0:45c4f0364ca4 457 #define RFLR_DIOMAPPING1_DIO1_10 0x20
mluis 0:45c4f0364ca4 458 #define RFLR_DIOMAPPING1_DIO1_11 0x30
mluis 0:45c4f0364ca4 459
mluis 0:45c4f0364ca4 460 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3
mluis 0:45c4f0364ca4 461 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default
mluis 0:45c4f0364ca4 462 #define RFLR_DIOMAPPING1_DIO2_01 0x04
mluis 0:45c4f0364ca4 463 #define RFLR_DIOMAPPING1_DIO2_10 0x08
mluis 0:45c4f0364ca4 464 #define RFLR_DIOMAPPING1_DIO2_11 0x0C
mluis 0:45c4f0364ca4 465
mluis 0:45c4f0364ca4 466 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC
mluis 0:45c4f0364ca4 467 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default
mluis 0:45c4f0364ca4 468 #define RFLR_DIOMAPPING1_DIO3_01 0x01
mluis 0:45c4f0364ca4 469 #define RFLR_DIOMAPPING1_DIO3_10 0x02
mluis 0:45c4f0364ca4 470 #define RFLR_DIOMAPPING1_DIO3_11 0x03
mluis 0:45c4f0364ca4 471
mluis 0:45c4f0364ca4 472 /*!
mluis 0:45c4f0364ca4 473 * RegDioMapping2
mluis 0:45c4f0364ca4 474 */
mluis 0:45c4f0364ca4 475 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F
mluis 0:45c4f0364ca4 476 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default
mluis 0:45c4f0364ca4 477 #define RFLR_DIOMAPPING2_DIO4_01 0x40
mluis 0:45c4f0364ca4 478 #define RFLR_DIOMAPPING2_DIO4_10 0x80
mluis 0:45c4f0364ca4 479 #define RFLR_DIOMAPPING2_DIO4_11 0xC0
mluis 0:45c4f0364ca4 480
mluis 0:45c4f0364ca4 481 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF
mluis 0:45c4f0364ca4 482 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default
mluis 0:45c4f0364ca4 483 #define RFLR_DIOMAPPING2_DIO5_01 0x10
mluis 0:45c4f0364ca4 484 #define RFLR_DIOMAPPING2_DIO5_10 0x20
mluis 0:45c4f0364ca4 485 #define RFLR_DIOMAPPING2_DIO5_11 0x30
mluis 0:45c4f0364ca4 486
mluis 0:45c4f0364ca4 487 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE
mluis 0:45c4f0364ca4 488 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01
mluis 0:45c4f0364ca4 489 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default
mluis 0:45c4f0364ca4 490
mluis 0:45c4f0364ca4 491 /*!
mluis 0:45c4f0364ca4 492 * RegVersion (Read Only)
mluis 0:45c4f0364ca4 493 */
mluis 0:45c4f0364ca4 494
mluis 0:45c4f0364ca4 495 /*!
mluis 0:45c4f0364ca4 496 * RegAgcRef
mluis 0:45c4f0364ca4 497 */
mluis 0:45c4f0364ca4 498
mluis 0:45c4f0364ca4 499 /*!
mluis 0:45c4f0364ca4 500 * RegAgcThresh1
mluis 0:45c4f0364ca4 501 */
mluis 0:45c4f0364ca4 502
mluis 0:45c4f0364ca4 503 /*!
mluis 0:45c4f0364ca4 504 * RegAgcThresh2
mluis 0:45c4f0364ca4 505 */
mluis 0:45c4f0364ca4 506
mluis 0:45c4f0364ca4 507 /*!
mluis 0:45c4f0364ca4 508 * RegAgcThresh3
mluis 0:45c4f0364ca4 509 */
mluis 0:45c4f0364ca4 510
mluis 0:45c4f0364ca4 511 /*!
mluis 0:45c4f0364ca4 512 * RegPllHop
mluis 0:45c4f0364ca4 513 */
mluis 0:45c4f0364ca4 514 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F
mluis 0:45c4f0364ca4 515 #define RFLR_PLLHOP_FASTHOP_ON 0x80
mluis 0:45c4f0364ca4 516 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default
mluis 0:45c4f0364ca4 517
mluis 0:45c4f0364ca4 518 /*!
mluis 0:45c4f0364ca4 519 * RegTcxo
mluis 0:45c4f0364ca4 520 */
mluis 0:45c4f0364ca4 521 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF
mluis 0:45c4f0364ca4 522 #define RFLR_TCXO_TCXOINPUT_ON 0x10
mluis 0:45c4f0364ca4 523 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default
mluis 0:45c4f0364ca4 524
mluis 0:45c4f0364ca4 525 /*!
mluis 0:45c4f0364ca4 526 * RegPaDac
mluis 0:45c4f0364ca4 527 */
mluis 0:45c4f0364ca4 528 #define RFLR_PADAC_20DBM_MASK 0xF8
mluis 0:45c4f0364ca4 529 #define RFLR_PADAC_20DBM_ON 0x07
mluis 0:45c4f0364ca4 530 #define RFLR_PADAC_20DBM_OFF 0x04 // Default
mluis 0:45c4f0364ca4 531
mluis 0:45c4f0364ca4 532 /*!
mluis 0:45c4f0364ca4 533 * RegPll
mluis 0:45c4f0364ca4 534 */
mluis 0:45c4f0364ca4 535 #define RFLR_PLL_BANDWIDTH_MASK 0x3F
mluis 0:45c4f0364ca4 536 #define RFLR_PLL_BANDWIDTH_75 0x00
mluis 0:45c4f0364ca4 537 #define RFLR_PLL_BANDWIDTH_150 0x40
mluis 0:45c4f0364ca4 538 #define RFLR_PLL_BANDWIDTH_225 0x80
mluis 0:45c4f0364ca4 539 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default
mluis 0:45c4f0364ca4 540
mluis 0:45c4f0364ca4 541 /*!
mluis 0:45c4f0364ca4 542 * RegPllLowPn
mluis 0:45c4f0364ca4 543 */
mluis 0:45c4f0364ca4 544 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F
mluis 0:45c4f0364ca4 545 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00
mluis 0:45c4f0364ca4 546 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40
mluis 0:45c4f0364ca4 547 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80
mluis 0:45c4f0364ca4 548 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default
mluis 0:45c4f0364ca4 549
mluis 0:45c4f0364ca4 550 /*!
mluis 0:45c4f0364ca4 551 * RegFormerTemp
mluis 0:45c4f0364ca4 552 */
mluis 0:45c4f0364ca4 553
mluis 0:45c4f0364ca4 554 #endif // __SX1272_REGS_LORA_H__