Jean-Louis VERN / FastSPI

je ne sais plus

BurstSPI_LPC_X.cpp@0:3787bbf77ca8, 2015-06-17 (annotated)

Committer:
FreeControl
Date:
Wed Jun 17 13:49:54 2015 +0000
Revision:
0:3787bbf77ca8
je ne sais plus

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FreeControl 0:3787bbf77ca8 1 #if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24) || defined(TARGET_LPC13XX)
FreeControl 0:3787bbf77ca8 2 #include "FastSPI.h"
FreeControl 0:3787bbf77ca8 3
FreeControl 0:3787bbf77ca8 4 void FastSPI::fastWrite(int data) {
FreeControl 0:3787bbf77ca8 5 //Wait until FIFO has space
FreeControl 0:3787bbf77ca8 6 while(((_spi.spi->SR) & 0x02) == 0);
FreeControl 0:3787bbf77ca8 7
FreeControl 0:3787bbf77ca8 8 //transmit data
FreeControl 0:3787bbf77ca8 9 _spi.spi->DR = data;
FreeControl 0:3787bbf77ca8 10 }
FreeControl 0:3787bbf77ca8 11
FreeControl 0:3787bbf77ca8 12 void FastSPI::clearRX( void ) {
FreeControl 0:3787bbf77ca8 13 //Do it while either data in RX buffer, or while it is busy
FreeControl 0:3787bbf77ca8 14 while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) {
FreeControl 0:3787bbf77ca8 15 //Wait until data in RX buffer
FreeControl 0:3787bbf77ca8 16 while(((_spi.spi->SR) & (1<<2)) == 0);
FreeControl 0:3787bbf77ca8 17 int dummy = _spi.spi->DR;
FreeControl 0:3787bbf77ca8 18 }
FreeControl 0:3787bbf77ca8 19 }
FreeControl 0:3787bbf77ca8 20 #endif