Frederick Huang / mbed-STM32L452

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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_wwdg.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_wwdg.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.7.1
AnnaBridge 167:e84263d55307 6 * @date 21-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of WWDG LL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 167:e84263d55307 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_LL_WWDG_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_LL_WWDG_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined (WWDG)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup WWDG_LL WWDG
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 67 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 68 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
<> 144:ef7eb2e8f9f7 69 * @{
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /** @defgroup WWDG_LL_EC_IT IT Defines
<> 144:ef7eb2e8f9f7 74 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
<> 144:ef7eb2e8f9f7 75 * @{
<> 144:ef7eb2e8f9f7 76 */
<> 144:ef7eb2e8f9f7 77 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
AnnaBridge 167:e84263d55307 85 #define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
<> 144:ef7eb2e8f9f7 86 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
<> 144:ef7eb2e8f9f7 87 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
<> 144:ef7eb2e8f9f7 88 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
<> 144:ef7eb2e8f9f7 89 /**
<> 144:ef7eb2e8f9f7 90 * @}
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /**
<> 144:ef7eb2e8f9f7 94 * @}
<> 144:ef7eb2e8f9f7 95 */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @brief Write a value in WWDG register
<> 144:ef7eb2e8f9f7 106 * @param __INSTANCE__ WWDG Instance
<> 144:ef7eb2e8f9f7 107 * @param __REG__ Register to be written
<> 144:ef7eb2e8f9f7 108 * @param __VALUE__ Value to be written in the register
<> 144:ef7eb2e8f9f7 109 * @retval None
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /**
<> 144:ef7eb2e8f9f7 114 * @brief Read a value in WWDG register
<> 144:ef7eb2e8f9f7 115 * @param __INSTANCE__ WWDG Instance
<> 144:ef7eb2e8f9f7 116 * @param __REG__ Register to be read
<> 144:ef7eb2e8f9f7 117 * @retval Register value
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @}
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @}
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 130 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup WWDG_LL_EF_Configuration Configuration
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 /**
<> 144:ef7eb2e8f9f7 138 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
<> 144:ef7eb2e8f9f7 139 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
<> 144:ef7eb2e8f9f7 140 * then it cannot be disabled again except by a reset.
<> 144:ef7eb2e8f9f7 141 * This bit is set by software and only cleared by hardware after a reset.
<> 144:ef7eb2e8f9f7 142 * When WDGA = 1, the watchdog can generate a reset.
<> 144:ef7eb2e8f9f7 143 * @rmtoll CR WDGA LL_WWDG_Enable
<> 144:ef7eb2e8f9f7 144 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 145 * @retval None
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 148 {
<> 144:ef7eb2e8f9f7 149 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief Checks if Window Watchdog is enabled
<> 144:ef7eb2e8f9f7 154 * @rmtoll CR WDGA LL_WWDG_IsEnabled
<> 144:ef7eb2e8f9f7 155 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 156 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
<> 144:ef7eb2e8f9f7 161 }
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
<> 144:ef7eb2e8f9f7 165 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
<> 144:ef7eb2e8f9f7 166 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 144:ef7eb2e8f9f7 167 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
<> 144:ef7eb2e8f9f7 168 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
<> 144:ef7eb2e8f9f7 169 * @rmtoll CR T LL_WWDG_SetCounter
<> 144:ef7eb2e8f9f7 170 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 171 * @param Counter 0..0x7F (7 bit counter value)
<> 144:ef7eb2e8f9f7 172 * @retval None
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Return current Watchdog Counter Value (7 bits counter value)
<> 144:ef7eb2e8f9f7 181 * @rmtoll CR T LL_WWDG_GetCounter
<> 144:ef7eb2e8f9f7 182 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 183 * @retval 7 bit Watchdog Counter value
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Set the time base of the prescaler (WDGTB).
<> 144:ef7eb2e8f9f7 192 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
<> 144:ef7eb2e8f9f7 193 * is decremented every (4096 x 2expWDGTB) PCLK cycles
<> 144:ef7eb2e8f9f7 194 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
<> 144:ef7eb2e8f9f7 195 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 196 * @param Prescaler This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 197 * @arg @ref LL_WWDG_PRESCALER_1
<> 144:ef7eb2e8f9f7 198 * @arg @ref LL_WWDG_PRESCALER_2
<> 144:ef7eb2e8f9f7 199 * @arg @ref LL_WWDG_PRESCALER_4
<> 144:ef7eb2e8f9f7 200 * @arg @ref LL_WWDG_PRESCALER_8
<> 144:ef7eb2e8f9f7 201 * @retval None
<> 144:ef7eb2e8f9f7 202 */
<> 144:ef7eb2e8f9f7 203 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
<> 144:ef7eb2e8f9f7 206 }
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @brief Return current Watchdog Prescaler Value
<> 144:ef7eb2e8f9f7 210 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
<> 144:ef7eb2e8f9f7 211 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 212 * @retval Returned value can be one of the following values:
<> 144:ef7eb2e8f9f7 213 * @arg @ref LL_WWDG_PRESCALER_1
<> 144:ef7eb2e8f9f7 214 * @arg @ref LL_WWDG_PRESCALER_2
<> 144:ef7eb2e8f9f7 215 * @arg @ref LL_WWDG_PRESCALER_4
<> 144:ef7eb2e8f9f7 216 * @arg @ref LL_WWDG_PRESCALER_8
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 219 {
<> 144:ef7eb2e8f9f7 220 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
<> 144:ef7eb2e8f9f7 221 }
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
<> 144:ef7eb2e8f9f7 225 * @note This window value defines when write in the WWDG_CR register
<> 144:ef7eb2e8f9f7 226 * to program Watchdog counter is allowed.
<> 144:ef7eb2e8f9f7 227 * Watchdog counter value update must occur only when the counter value
<> 144:ef7eb2e8f9f7 228 * is lower than the Watchdog window register value.
<> 144:ef7eb2e8f9f7 229 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
<> 144:ef7eb2e8f9f7 230 * (in the control register) is refreshed before the downcounter has reached
<> 144:ef7eb2e8f9f7 231 * the watchdog window register value.
<> 144:ef7eb2e8f9f7 232 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
<> 144:ef7eb2e8f9f7 233 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
<> 144:ef7eb2e8f9f7 234 * @rmtoll CFR W LL_WWDG_SetWindow
<> 144:ef7eb2e8f9f7 235 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 236 * @param Window 0x00..0x7F (7 bit Window value)
<> 144:ef7eb2e8f9f7 237 * @retval None
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
<> 144:ef7eb2e8f9f7 242 }
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @brief Return current Watchdog Window Value (7 bits value)
<> 144:ef7eb2e8f9f7 246 * @rmtoll CFR W LL_WWDG_GetWindow
<> 144:ef7eb2e8f9f7 247 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 248 * @retval 7 bit Watchdog Window value
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /**
<> 144:ef7eb2e8f9f7 256 * @}
<> 144:ef7eb2e8f9f7 257 */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
<> 144:ef7eb2e8f9f7 260 * @{
<> 144:ef7eb2e8f9f7 261 */
<> 144:ef7eb2e8f9f7 262 /**
<> 144:ef7eb2e8f9f7 263 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
<> 144:ef7eb2e8f9f7 264 * @note This bit is set by hardware when the counter has reached the value 0x40.
<> 144:ef7eb2e8f9f7 265 * It must be cleared by software by writing 0.
<> 144:ef7eb2e8f9f7 266 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
<> 144:ef7eb2e8f9f7 267 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
<> 144:ef7eb2e8f9f7 268 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 269 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
<> 144:ef7eb2e8f9f7 278 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
<> 144:ef7eb2e8f9f7 279 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 280 * @retval None
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 283 {
<> 144:ef7eb2e8f9f7 284 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
<> 144:ef7eb2e8f9f7 285 }
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /**
<> 144:ef7eb2e8f9f7 288 * @}
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294 /**
<> 144:ef7eb2e8f9f7 295 * @brief Enable the Early Wakeup Interrupt.
<> 144:ef7eb2e8f9f7 296 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
<> 144:ef7eb2e8f9f7 297 * This interrupt is only cleared by hardware after a reset
<> 144:ef7eb2e8f9f7 298 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
<> 144:ef7eb2e8f9f7 299 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 300 * @retval None
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 303 {
<> 144:ef7eb2e8f9f7 304 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief Check if Early Wakeup Interrupt is enabled
<> 144:ef7eb2e8f9f7 309 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
<> 144:ef7eb2e8f9f7 310 * @param WWDGx WWDG Instance
<> 144:ef7eb2e8f9f7 311 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 312 */
<> 144:ef7eb2e8f9f7 313 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /**
<> 144:ef7eb2e8f9f7 319 * @}
<> 144:ef7eb2e8f9f7 320 */
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /**
<> 144:ef7eb2e8f9f7 327 * @}
<> 144:ef7eb2e8f9f7 328 */
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 #endif /* WWDG */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /**
<> 144:ef7eb2e8f9f7 333 * @}
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 #endif
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 #endif /* __STM32L4xx_LL_WWDG_H */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/