Frederick Huang / mbed-STM32L452

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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_cortex.h
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @version V1.2.0
<> 161:2cc1468da177 6 * @date 30-December-2016
<> 161:2cc1468da177 7 * @brief Header file of CORTEX LL module.
<> 161:2cc1468da177 8 @verbatim
<> 161:2cc1468da177 9 ==============================================================================
<> 161:2cc1468da177 10 ##### How to use this driver #####
<> 161:2cc1468da177 11 ==============================================================================
<> 161:2cc1468da177 12 [..]
<> 161:2cc1468da177 13 The LL CORTEX driver contains a set of generic APIs that can be
<> 161:2cc1468da177 14 used by user:
<> 161:2cc1468da177 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
<> 161:2cc1468da177 16 functions
<> 161:2cc1468da177 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
<> 161:2cc1468da177 18 (+) MPU API to configure and enable regions
<> 161:2cc1468da177 19 (+) API to access to MCU info (CPUID register)
<> 161:2cc1468da177 20 (+) API to enable fault handler (SHCSR accesses)
<> 161:2cc1468da177 21
<> 161:2cc1468da177 22 @endverbatim
<> 161:2cc1468da177 23 ******************************************************************************
<> 161:2cc1468da177 24 * @attention
<> 161:2cc1468da177 25 *
<> 161:2cc1468da177 26 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 27 *
<> 161:2cc1468da177 28 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 29 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 30 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 31 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 33 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 34 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 36 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 37 * without specific prior written permission.
<> 161:2cc1468da177 38 *
<> 161:2cc1468da177 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 49 *
<> 161:2cc1468da177 50 ******************************************************************************
<> 161:2cc1468da177 51 */
<> 161:2cc1468da177 52
<> 161:2cc1468da177 53 /* Define to prevent recursive inclusion -------------------------------------*/
<> 161:2cc1468da177 54 #ifndef __STM32F7xx_LL_CORTEX_H
<> 161:2cc1468da177 55 #define __STM32F7xx_LL_CORTEX_H
<> 161:2cc1468da177 56
<> 161:2cc1468da177 57 #ifdef __cplusplus
<> 161:2cc1468da177 58 extern "C" {
<> 161:2cc1468da177 59 #endif
<> 161:2cc1468da177 60
<> 161:2cc1468da177 61 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 62 #include "stm32f7xx.h"
<> 161:2cc1468da177 63
<> 161:2cc1468da177 64 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 65 * @{
<> 161:2cc1468da177 66 */
<> 161:2cc1468da177 67
<> 161:2cc1468da177 68 /** @defgroup CORTEX_LL CORTEX
<> 161:2cc1468da177 69 * @{
<> 161:2cc1468da177 70 */
<> 161:2cc1468da177 71
<> 161:2cc1468da177 72 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 73 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 74
<> 161:2cc1468da177 75 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 76
<> 161:2cc1468da177 77 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 78
<> 161:2cc1468da177 79 /* Exported types ------------------------------------------------------------*/
<> 161:2cc1468da177 80 /* Exported constants --------------------------------------------------------*/
<> 161:2cc1468da177 81 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
<> 161:2cc1468da177 82 * @{
<> 161:2cc1468da177 83 */
<> 161:2cc1468da177 84
<> 161:2cc1468da177 85 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
<> 161:2cc1468da177 86 * @{
<> 161:2cc1468da177 87 */
<> 161:2cc1468da177 88 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
<> 161:2cc1468da177 89 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
<> 161:2cc1468da177 90 /**
<> 161:2cc1468da177 91 * @}
<> 161:2cc1468da177 92 */
<> 161:2cc1468da177 93
<> 161:2cc1468da177 94 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
<> 161:2cc1468da177 95 * @{
<> 161:2cc1468da177 96 */
<> 161:2cc1468da177 97 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
<> 161:2cc1468da177 98 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
<> 161:2cc1468da177 99 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
<> 161:2cc1468da177 100 /**
<> 161:2cc1468da177 101 * @}
<> 161:2cc1468da177 102 */
<> 161:2cc1468da177 103
<> 161:2cc1468da177 104 #if __MPU_PRESENT
<> 161:2cc1468da177 105
<> 161:2cc1468da177 106 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
<> 161:2cc1468da177 107 * @{
<> 161:2cc1468da177 108 */
<> 161:2cc1468da177 109 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
<> 161:2cc1468da177 110 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
<> 161:2cc1468da177 111 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
<> 161:2cc1468da177 112 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
<> 161:2cc1468da177 113 /**
<> 161:2cc1468da177 114 * @}
<> 161:2cc1468da177 115 */
<> 161:2cc1468da177 116
<> 161:2cc1468da177 117 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
<> 161:2cc1468da177 118 * @{
<> 161:2cc1468da177 119 */
<> 161:2cc1468da177 120 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
<> 161:2cc1468da177 121 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
<> 161:2cc1468da177 122 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
<> 161:2cc1468da177 123 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
<> 161:2cc1468da177 124 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
<> 161:2cc1468da177 125 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
<> 161:2cc1468da177 126 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
<> 161:2cc1468da177 127 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
<> 161:2cc1468da177 128 /**
<> 161:2cc1468da177 129 * @}
<> 161:2cc1468da177 130 */
<> 161:2cc1468da177 131
<> 161:2cc1468da177 132 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
<> 161:2cc1468da177 133 * @{
<> 161:2cc1468da177 134 */
<> 161:2cc1468da177 135 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
<> 161:2cc1468da177 136 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
<> 161:2cc1468da177 137 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
<> 161:2cc1468da177 138 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
<> 161:2cc1468da177 139 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
<> 161:2cc1468da177 140 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
<> 161:2cc1468da177 141 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
<> 161:2cc1468da177 142 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
<> 161:2cc1468da177 143 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
<> 161:2cc1468da177 144 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
<> 161:2cc1468da177 145 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
<> 161:2cc1468da177 146 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
<> 161:2cc1468da177 147 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
<> 161:2cc1468da177 148 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
<> 161:2cc1468da177 149 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
<> 161:2cc1468da177 150 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
<> 161:2cc1468da177 151 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
<> 161:2cc1468da177 152 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
<> 161:2cc1468da177 153 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
<> 161:2cc1468da177 154 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
<> 161:2cc1468da177 155 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
<> 161:2cc1468da177 156 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
<> 161:2cc1468da177 157 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
<> 161:2cc1468da177 158 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
<> 161:2cc1468da177 159 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
<> 161:2cc1468da177 160 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
<> 161:2cc1468da177 161 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
<> 161:2cc1468da177 162 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
<> 161:2cc1468da177 163 /**
<> 161:2cc1468da177 164 * @}
<> 161:2cc1468da177 165 */
<> 161:2cc1468da177 166
<> 161:2cc1468da177 167 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
<> 161:2cc1468da177 168 * @{
<> 161:2cc1468da177 169 */
<> 161:2cc1468da177 170 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
<> 161:2cc1468da177 171 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
<> 161:2cc1468da177 172 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
<> 161:2cc1468da177 173 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
<> 161:2cc1468da177 174 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
<> 161:2cc1468da177 175 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
<> 161:2cc1468da177 176 /**
<> 161:2cc1468da177 177 * @}
<> 161:2cc1468da177 178 */
<> 161:2cc1468da177 179
<> 161:2cc1468da177 180 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
<> 161:2cc1468da177 181 * @{
<> 161:2cc1468da177 182 */
<> 161:2cc1468da177 183 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
<> 161:2cc1468da177 184 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
<> 161:2cc1468da177 185 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
<> 161:2cc1468da177 186 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
<> 161:2cc1468da177 187 /**
<> 161:2cc1468da177 188 * @}
<> 161:2cc1468da177 189 */
<> 161:2cc1468da177 190
<> 161:2cc1468da177 191 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
<> 161:2cc1468da177 192 * @{
<> 161:2cc1468da177 193 */
<> 161:2cc1468da177 194 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
<> 161:2cc1468da177 195 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
<> 161:2cc1468da177 196 /**
<> 161:2cc1468da177 197 * @}
<> 161:2cc1468da177 198 */
<> 161:2cc1468da177 199
<> 161:2cc1468da177 200 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
<> 161:2cc1468da177 201 * @{
<> 161:2cc1468da177 202 */
<> 161:2cc1468da177 203 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
<> 161:2cc1468da177 204 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
<> 161:2cc1468da177 205 /**
<> 161:2cc1468da177 206 * @}
<> 161:2cc1468da177 207 */
<> 161:2cc1468da177 208
<> 161:2cc1468da177 209 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
<> 161:2cc1468da177 210 * @{
<> 161:2cc1468da177 211 */
<> 161:2cc1468da177 212 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
<> 161:2cc1468da177 213 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
<> 161:2cc1468da177 214 /**
<> 161:2cc1468da177 215 * @}
<> 161:2cc1468da177 216 */
<> 161:2cc1468da177 217
<> 161:2cc1468da177 218 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
<> 161:2cc1468da177 219 * @{
<> 161:2cc1468da177 220 */
<> 161:2cc1468da177 221 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
<> 161:2cc1468da177 222 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
<> 161:2cc1468da177 223 /**
<> 161:2cc1468da177 224 * @}
<> 161:2cc1468da177 225 */
<> 161:2cc1468da177 226 #endif /* __MPU_PRESENT */
<> 161:2cc1468da177 227 /**
<> 161:2cc1468da177 228 * @}
<> 161:2cc1468da177 229 */
<> 161:2cc1468da177 230
<> 161:2cc1468da177 231 /* Exported macro ------------------------------------------------------------*/
<> 161:2cc1468da177 232
<> 161:2cc1468da177 233 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 234 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
<> 161:2cc1468da177 235 * @{
<> 161:2cc1468da177 236 */
<> 161:2cc1468da177 237
<> 161:2cc1468da177 238 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
<> 161:2cc1468da177 239 * @{
<> 161:2cc1468da177 240 */
<> 161:2cc1468da177 241
<> 161:2cc1468da177 242 /**
<> 161:2cc1468da177 243 * @brief This function checks if the Systick counter flag is active or not.
<> 161:2cc1468da177 244 * @note It can be used in timeout function on application side.
<> 161:2cc1468da177 245 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
<> 161:2cc1468da177 246 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 247 */
<> 161:2cc1468da177 248 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
<> 161:2cc1468da177 249 {
<> 161:2cc1468da177 250 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
<> 161:2cc1468da177 251 }
<> 161:2cc1468da177 252
<> 161:2cc1468da177 253 /**
<> 161:2cc1468da177 254 * @brief Configures the SysTick clock source
<> 161:2cc1468da177 255 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
<> 161:2cc1468da177 256 * @param Source This parameter can be one of the following values:
<> 161:2cc1468da177 257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 161:2cc1468da177 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 161:2cc1468da177 259 * @retval None
<> 161:2cc1468da177 260 */
<> 161:2cc1468da177 261 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
<> 161:2cc1468da177 262 {
<> 161:2cc1468da177 263 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
<> 161:2cc1468da177 264 {
<> 161:2cc1468da177 265 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 161:2cc1468da177 266 }
<> 161:2cc1468da177 267 else
<> 161:2cc1468da177 268 {
<> 161:2cc1468da177 269 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 161:2cc1468da177 270 }
<> 161:2cc1468da177 271 }
<> 161:2cc1468da177 272
<> 161:2cc1468da177 273 /**
<> 161:2cc1468da177 274 * @brief Get the SysTick clock source
<> 161:2cc1468da177 275 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
<> 161:2cc1468da177 276 * @retval Returned value can be one of the following values:
<> 161:2cc1468da177 277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
<> 161:2cc1468da177 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
<> 161:2cc1468da177 279 */
<> 161:2cc1468da177 280 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
<> 161:2cc1468da177 281 {
<> 161:2cc1468da177 282 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
<> 161:2cc1468da177 283 }
<> 161:2cc1468da177 284
<> 161:2cc1468da177 285 /**
<> 161:2cc1468da177 286 * @brief Enable SysTick exception request
<> 161:2cc1468da177 287 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
<> 161:2cc1468da177 288 * @retval None
<> 161:2cc1468da177 289 */
<> 161:2cc1468da177 290 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
<> 161:2cc1468da177 291 {
<> 161:2cc1468da177 292 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 161:2cc1468da177 293 }
<> 161:2cc1468da177 294
<> 161:2cc1468da177 295 /**
<> 161:2cc1468da177 296 * @brief Disable SysTick exception request
<> 161:2cc1468da177 297 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
<> 161:2cc1468da177 298 * @retval None
<> 161:2cc1468da177 299 */
<> 161:2cc1468da177 300 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
<> 161:2cc1468da177 301 {
<> 161:2cc1468da177 302 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
<> 161:2cc1468da177 303 }
<> 161:2cc1468da177 304
<> 161:2cc1468da177 305 /**
<> 161:2cc1468da177 306 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
<> 161:2cc1468da177 307 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
<> 161:2cc1468da177 308 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 309 */
<> 161:2cc1468da177 310 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
<> 161:2cc1468da177 311 {
<> 161:2cc1468da177 312 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
<> 161:2cc1468da177 313 }
<> 161:2cc1468da177 314
<> 161:2cc1468da177 315 /**
<> 161:2cc1468da177 316 * @}
<> 161:2cc1468da177 317 */
<> 161:2cc1468da177 318
<> 161:2cc1468da177 319 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
<> 161:2cc1468da177 320 * @{
<> 161:2cc1468da177 321 */
<> 161:2cc1468da177 322
<> 161:2cc1468da177 323 /**
<> 161:2cc1468da177 324 * @brief Processor uses sleep as its low power mode
<> 161:2cc1468da177 325 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
<> 161:2cc1468da177 326 * @retval None
<> 161:2cc1468da177 327 */
<> 161:2cc1468da177 328 __STATIC_INLINE void LL_LPM_EnableSleep(void)
<> 161:2cc1468da177 329 {
<> 161:2cc1468da177 330 /* Clear SLEEPDEEP bit of Cortex System Control Register */
<> 161:2cc1468da177 331 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 161:2cc1468da177 332 }
<> 161:2cc1468da177 333
<> 161:2cc1468da177 334 /**
<> 161:2cc1468da177 335 * @brief Processor uses deep sleep as its low power mode
<> 161:2cc1468da177 336 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
<> 161:2cc1468da177 337 * @retval None
<> 161:2cc1468da177 338 */
<> 161:2cc1468da177 339 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
<> 161:2cc1468da177 340 {
<> 161:2cc1468da177 341 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 161:2cc1468da177 342 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 161:2cc1468da177 343 }
<> 161:2cc1468da177 344
<> 161:2cc1468da177 345 /**
<> 161:2cc1468da177 346 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
<> 161:2cc1468da177 347 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
<> 161:2cc1468da177 348 * empty main application.
<> 161:2cc1468da177 349 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
<> 161:2cc1468da177 350 * @retval None
<> 161:2cc1468da177 351 */
<> 161:2cc1468da177 352 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
<> 161:2cc1468da177 353 {
<> 161:2cc1468da177 354 /* Set SLEEPONEXIT bit of Cortex System Control Register */
<> 161:2cc1468da177 355 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 161:2cc1468da177 356 }
<> 161:2cc1468da177 357
<> 161:2cc1468da177 358 /**
<> 161:2cc1468da177 359 * @brief Do not sleep when returning to Thread mode.
<> 161:2cc1468da177 360 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
<> 161:2cc1468da177 361 * @retval None
<> 161:2cc1468da177 362 */
<> 161:2cc1468da177 363 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
<> 161:2cc1468da177 364 {
<> 161:2cc1468da177 365 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
<> 161:2cc1468da177 366 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
<> 161:2cc1468da177 367 }
<> 161:2cc1468da177 368
<> 161:2cc1468da177 369 /**
<> 161:2cc1468da177 370 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
<> 161:2cc1468da177 371 * processor.
<> 161:2cc1468da177 372 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
<> 161:2cc1468da177 373 * @retval None
<> 161:2cc1468da177 374 */
<> 161:2cc1468da177 375 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
<> 161:2cc1468da177 376 {
<> 161:2cc1468da177 377 /* Set SEVEONPEND bit of Cortex System Control Register */
<> 161:2cc1468da177 378 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 161:2cc1468da177 379 }
<> 161:2cc1468da177 380
<> 161:2cc1468da177 381 /**
<> 161:2cc1468da177 382 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
<> 161:2cc1468da177 383 * excluded
<> 161:2cc1468da177 384 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
<> 161:2cc1468da177 385 * @retval None
<> 161:2cc1468da177 386 */
<> 161:2cc1468da177 387 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
<> 161:2cc1468da177 388 {
<> 161:2cc1468da177 389 /* Clear SEVEONPEND bit of Cortex System Control Register */
<> 161:2cc1468da177 390 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
<> 161:2cc1468da177 391 }
<> 161:2cc1468da177 392
<> 161:2cc1468da177 393 /**
<> 161:2cc1468da177 394 * @}
<> 161:2cc1468da177 395 */
<> 161:2cc1468da177 396
<> 161:2cc1468da177 397 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
<> 161:2cc1468da177 398 * @{
<> 161:2cc1468da177 399 */
<> 161:2cc1468da177 400
<> 161:2cc1468da177 401 /**
<> 161:2cc1468da177 402 * @brief Enable a fault in System handler control register (SHCSR)
<> 161:2cc1468da177 403 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
<> 161:2cc1468da177 404 * @param Fault This parameter can be a combination of the following values:
<> 161:2cc1468da177 405 * @arg @ref LL_HANDLER_FAULT_USG
<> 161:2cc1468da177 406 * @arg @ref LL_HANDLER_FAULT_BUS
<> 161:2cc1468da177 407 * @arg @ref LL_HANDLER_FAULT_MEM
<> 161:2cc1468da177 408 * @retval None
<> 161:2cc1468da177 409 */
<> 161:2cc1468da177 410 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
<> 161:2cc1468da177 411 {
<> 161:2cc1468da177 412 /* Enable the system handler fault */
<> 161:2cc1468da177 413 SET_BIT(SCB->SHCSR, Fault);
<> 161:2cc1468da177 414 }
<> 161:2cc1468da177 415
<> 161:2cc1468da177 416 /**
<> 161:2cc1468da177 417 * @brief Disable a fault in System handler control register (SHCSR)
<> 161:2cc1468da177 418 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
<> 161:2cc1468da177 419 * @param Fault This parameter can be a combination of the following values:
<> 161:2cc1468da177 420 * @arg @ref LL_HANDLER_FAULT_USG
<> 161:2cc1468da177 421 * @arg @ref LL_HANDLER_FAULT_BUS
<> 161:2cc1468da177 422 * @arg @ref LL_HANDLER_FAULT_MEM
<> 161:2cc1468da177 423 * @retval None
<> 161:2cc1468da177 424 */
<> 161:2cc1468da177 425 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
<> 161:2cc1468da177 426 {
<> 161:2cc1468da177 427 /* Disable the system handler fault */
<> 161:2cc1468da177 428 CLEAR_BIT(SCB->SHCSR, Fault);
<> 161:2cc1468da177 429 }
<> 161:2cc1468da177 430
<> 161:2cc1468da177 431 /**
<> 161:2cc1468da177 432 * @}
<> 161:2cc1468da177 433 */
<> 161:2cc1468da177 434
<> 161:2cc1468da177 435 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
<> 161:2cc1468da177 436 * @{
<> 161:2cc1468da177 437 */
<> 161:2cc1468da177 438
<> 161:2cc1468da177 439 /**
<> 161:2cc1468da177 440 * @brief Get Implementer code
<> 161:2cc1468da177 441 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
<> 161:2cc1468da177 442 * @retval Value should be equal to 0x41 for ARM
<> 161:2cc1468da177 443 */
<> 161:2cc1468da177 444 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
<> 161:2cc1468da177 445 {
<> 161:2cc1468da177 446 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
<> 161:2cc1468da177 447 }
<> 161:2cc1468da177 448
<> 161:2cc1468da177 449 /**
<> 161:2cc1468da177 450 * @brief Get Variant number (The r value in the rnpn product revision identifier)
<> 161:2cc1468da177 451 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
<> 161:2cc1468da177 452 * @retval Value between 0 and 255 (0x0: revision 0)
<> 161:2cc1468da177 453 */
<> 161:2cc1468da177 454 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
<> 161:2cc1468da177 455 {
<> 161:2cc1468da177 456 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
<> 161:2cc1468da177 457 }
<> 161:2cc1468da177 458
<> 161:2cc1468da177 459 /**
<> 161:2cc1468da177 460 * @brief Get Constant number
<> 161:2cc1468da177 461 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
<> 161:2cc1468da177 462 * @retval Value should be equal to 0xF for Cortex-M7 devices
<> 161:2cc1468da177 463 */
<> 161:2cc1468da177 464 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
<> 161:2cc1468da177 465 {
<> 161:2cc1468da177 466 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
<> 161:2cc1468da177 467 }
<> 161:2cc1468da177 468
<> 161:2cc1468da177 469 /**
<> 161:2cc1468da177 470 * @brief Get Part number
<> 161:2cc1468da177 471 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
<> 161:2cc1468da177 472 * @retval Value should be equal to 0xC27 for Cortex-M7
<> 161:2cc1468da177 473 */
<> 161:2cc1468da177 474 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
<> 161:2cc1468da177 475 {
<> 161:2cc1468da177 476 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
<> 161:2cc1468da177 477 }
<> 161:2cc1468da177 478
<> 161:2cc1468da177 479 /**
<> 161:2cc1468da177 480 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
<> 161:2cc1468da177 481 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
<> 161:2cc1468da177 482 * @retval Value between 0 and 255 (0x1: patch 1)
<> 161:2cc1468da177 483 */
<> 161:2cc1468da177 484 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
<> 161:2cc1468da177 485 {
<> 161:2cc1468da177 486 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
<> 161:2cc1468da177 487 }
<> 161:2cc1468da177 488
<> 161:2cc1468da177 489 /**
<> 161:2cc1468da177 490 * @}
<> 161:2cc1468da177 491 */
<> 161:2cc1468da177 492
<> 161:2cc1468da177 493 #if __MPU_PRESENT
<> 161:2cc1468da177 494 /** @defgroup CORTEX_LL_EF_MPU MPU
<> 161:2cc1468da177 495 * @{
<> 161:2cc1468da177 496 */
<> 161:2cc1468da177 497
<> 161:2cc1468da177 498 /**
<> 161:2cc1468da177 499 * @brief Enable MPU with input options
<> 161:2cc1468da177 500 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
<> 161:2cc1468da177 501 * @param Options This parameter can be one of the following values:
<> 161:2cc1468da177 502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
<> 161:2cc1468da177 503 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
<> 161:2cc1468da177 504 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
<> 161:2cc1468da177 505 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
<> 161:2cc1468da177 506 * @retval None
<> 161:2cc1468da177 507 */
<> 161:2cc1468da177 508 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
<> 161:2cc1468da177 509 {
<> 161:2cc1468da177 510 /* Enable the MPU*/
<> 161:2cc1468da177 511 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
<> 161:2cc1468da177 512 /* Ensure MPU settings take effects */
<> 161:2cc1468da177 513 __DSB();
<> 161:2cc1468da177 514 /* Sequence instruction fetches using update settings */
<> 161:2cc1468da177 515 __ISB();
<> 161:2cc1468da177 516 }
<> 161:2cc1468da177 517
<> 161:2cc1468da177 518 /**
<> 161:2cc1468da177 519 * @brief Disable MPU
<> 161:2cc1468da177 520 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
<> 161:2cc1468da177 521 * @retval None
<> 161:2cc1468da177 522 */
<> 161:2cc1468da177 523 __STATIC_INLINE void LL_MPU_Disable(void)
<> 161:2cc1468da177 524 {
<> 161:2cc1468da177 525 /* Make sure outstanding transfers are done */
<> 161:2cc1468da177 526 __DMB();
<> 161:2cc1468da177 527 /* Disable MPU*/
<> 161:2cc1468da177 528 WRITE_REG(MPU->CTRL, 0U);
<> 161:2cc1468da177 529 }
<> 161:2cc1468da177 530
<> 161:2cc1468da177 531 /**
<> 161:2cc1468da177 532 * @brief Check if MPU is enabled or not
<> 161:2cc1468da177 533 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
<> 161:2cc1468da177 534 * @retval State of bit (1 or 0).
<> 161:2cc1468da177 535 */
<> 161:2cc1468da177 536 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
<> 161:2cc1468da177 537 {
<> 161:2cc1468da177 538 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
<> 161:2cc1468da177 539 }
<> 161:2cc1468da177 540
<> 161:2cc1468da177 541 /**
<> 161:2cc1468da177 542 * @brief Enable a MPU region
<> 161:2cc1468da177 543 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
<> 161:2cc1468da177 544 * @param Region This parameter can be one of the following values:
<> 161:2cc1468da177 545 * @arg @ref LL_MPU_REGION_NUMBER0
<> 161:2cc1468da177 546 * @arg @ref LL_MPU_REGION_NUMBER1
<> 161:2cc1468da177 547 * @arg @ref LL_MPU_REGION_NUMBER2
<> 161:2cc1468da177 548 * @arg @ref LL_MPU_REGION_NUMBER3
<> 161:2cc1468da177 549 * @arg @ref LL_MPU_REGION_NUMBER4
<> 161:2cc1468da177 550 * @arg @ref LL_MPU_REGION_NUMBER5
<> 161:2cc1468da177 551 * @arg @ref LL_MPU_REGION_NUMBER6
<> 161:2cc1468da177 552 * @arg @ref LL_MPU_REGION_NUMBER7
<> 161:2cc1468da177 553 * @retval None
<> 161:2cc1468da177 554 */
<> 161:2cc1468da177 555 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
<> 161:2cc1468da177 556 {
<> 161:2cc1468da177 557 /* Set Region number */
<> 161:2cc1468da177 558 WRITE_REG(MPU->RNR, Region);
<> 161:2cc1468da177 559 /* Enable the MPU region */
<> 161:2cc1468da177 560 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 161:2cc1468da177 561 }
<> 161:2cc1468da177 562
<> 161:2cc1468da177 563 /**
<> 161:2cc1468da177 564 * @brief Configure and enable a region
<> 161:2cc1468da177 565 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 566 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 567 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 568 * MPU_RASR XN LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 569 * MPU_RASR AP LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 570 * MPU_RASR S LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 571 * MPU_RASR C LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 572 * MPU_RASR B LL_MPU_ConfigRegion\n
<> 161:2cc1468da177 573 * MPU_RASR SIZE LL_MPU_ConfigRegion
<> 161:2cc1468da177 574 * @param Region This parameter can be one of the following values:
<> 161:2cc1468da177 575 * @arg @ref LL_MPU_REGION_NUMBER0
<> 161:2cc1468da177 576 * @arg @ref LL_MPU_REGION_NUMBER1
<> 161:2cc1468da177 577 * @arg @ref LL_MPU_REGION_NUMBER2
<> 161:2cc1468da177 578 * @arg @ref LL_MPU_REGION_NUMBER3
<> 161:2cc1468da177 579 * @arg @ref LL_MPU_REGION_NUMBER4
<> 161:2cc1468da177 580 * @arg @ref LL_MPU_REGION_NUMBER5
<> 161:2cc1468da177 581 * @arg @ref LL_MPU_REGION_NUMBER6
<> 161:2cc1468da177 582 * @arg @ref LL_MPU_REGION_NUMBER7
<> 161:2cc1468da177 583 * @param Address Value of region base address
<> 161:2cc1468da177 584 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
<> 161:2cc1468da177 585 * @param Attributes This parameter can be a combination of the following values:
<> 161:2cc1468da177 586 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
<> 161:2cc1468da177 587 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
<> 161:2cc1468da177 588 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
<> 161:2cc1468da177 589 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
<> 161:2cc1468da177 590 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
<> 161:2cc1468da177 591 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
<> 161:2cc1468da177 592 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
<> 161:2cc1468da177 593 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
<> 161:2cc1468da177 594 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
<> 161:2cc1468da177 595 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
<> 161:2cc1468da177 596 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
<> 161:2cc1468da177 597 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
<> 161:2cc1468da177 598 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
<> 161:2cc1468da177 599 * @retval None
<> 161:2cc1468da177 600 */
<> 161:2cc1468da177 601 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
<> 161:2cc1468da177 602 {
<> 161:2cc1468da177 603 /* Set Region number */
<> 161:2cc1468da177 604 WRITE_REG(MPU->RNR, Region);
<> 161:2cc1468da177 605 /* Set base address */
<> 161:2cc1468da177 606 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
<> 161:2cc1468da177 607 /* Configure MPU */
<> 161:2cc1468da177 608 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
<> 161:2cc1468da177 609 }
<> 161:2cc1468da177 610
<> 161:2cc1468da177 611 /**
<> 161:2cc1468da177 612 * @brief Disable a region
<> 161:2cc1468da177 613 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
<> 161:2cc1468da177 614 * MPU_RASR ENABLE LL_MPU_DisableRegion
<> 161:2cc1468da177 615 * @param Region This parameter can be one of the following values:
<> 161:2cc1468da177 616 * @arg @ref LL_MPU_REGION_NUMBER0
<> 161:2cc1468da177 617 * @arg @ref LL_MPU_REGION_NUMBER1
<> 161:2cc1468da177 618 * @arg @ref LL_MPU_REGION_NUMBER2
<> 161:2cc1468da177 619 * @arg @ref LL_MPU_REGION_NUMBER3
<> 161:2cc1468da177 620 * @arg @ref LL_MPU_REGION_NUMBER4
<> 161:2cc1468da177 621 * @arg @ref LL_MPU_REGION_NUMBER5
<> 161:2cc1468da177 622 * @arg @ref LL_MPU_REGION_NUMBER6
<> 161:2cc1468da177 623 * @arg @ref LL_MPU_REGION_NUMBER7
<> 161:2cc1468da177 624 * @retval None
<> 161:2cc1468da177 625 */
<> 161:2cc1468da177 626 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
<> 161:2cc1468da177 627 {
<> 161:2cc1468da177 628 /* Set Region number */
<> 161:2cc1468da177 629 WRITE_REG(MPU->RNR, Region);
<> 161:2cc1468da177 630 /* Disable the MPU region */
<> 161:2cc1468da177 631 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
<> 161:2cc1468da177 632 }
<> 161:2cc1468da177 633
<> 161:2cc1468da177 634 /**
<> 161:2cc1468da177 635 * @}
<> 161:2cc1468da177 636 */
<> 161:2cc1468da177 637
<> 161:2cc1468da177 638 #endif /* __MPU_PRESENT */
<> 161:2cc1468da177 639 /**
<> 161:2cc1468da177 640 * @}
<> 161:2cc1468da177 641 */
<> 161:2cc1468da177 642
<> 161:2cc1468da177 643 /**
<> 161:2cc1468da177 644 * @}
<> 161:2cc1468da177 645 */
<> 161:2cc1468da177 646
<> 161:2cc1468da177 647 /**
<> 161:2cc1468da177 648 * @}
<> 161:2cc1468da177 649 */
<> 161:2cc1468da177 650
<> 161:2cc1468da177 651 #ifdef __cplusplus
<> 161:2cc1468da177 652 }
<> 161:2cc1468da177 653 #endif
<> 161:2cc1468da177 654
<> 161:2cc1468da177 655 #endif /* __STM32F7xx_LL_CORTEX_H */
<> 161:2cc1468da177 656
<> 161:2cc1468da177 657 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/