Francesco Pavoni
/
BLE_Nano_Central_hrs_c_01
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nrf51.h
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00001 00002 /****************************************************************************************************//** 00003 * @file nrf51.h 00004 * 00005 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for 00006 * nrf51 from Nordic Semiconductor. 00007 * 00008 * @version V522 00009 * @date 23. February 2016 00010 * 00011 * @note Generated with SVDConv V2.81d 00012 * from CMSIS SVD File 'nrf51.svd' Version 522, 00013 * 00014 * @par Copyright (c) 2013, Nordic Semiconductor ASA 00015 * All rights reserved. 00016 * 00017 * Redistribution and use in source and binary forms, with or without 00018 * modification, are permitted provided that the following conditions are met: 00019 * 00020 * * Redistributions of source code must retain the above copyright notice, this 00021 * list of conditions and the following disclaimer. 00022 * 00023 * * Redistributions in binary form must reproduce the above copyright notice, 00024 * this list of conditions and the following disclaimer in the documentation 00025 * and/or other materials provided with the distribution. 00026 * 00027 * * Neither the name of Nordic Semiconductor ASA nor the names of its 00028 * contributors may be used to endorse or promote products derived from 00029 * this software without specific prior written permission. 00030 * 00031 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00032 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00033 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00034 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00035 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00036 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00037 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00038 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00039 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00040 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00041 * 00042 * 00043 *******************************************************************************************************/ 00044 00045 00046 00047 /** @addtogroup Nordic Semiconductor 00048 * @{ 00049 */ 00050 00051 /** @addtogroup nrf51 00052 * @{ 00053 */ 00054 00055 #ifndef NRF51_H 00056 #define NRF51_H 00057 00058 #ifdef __cplusplus 00059 extern "C" { 00060 #endif 00061 00062 00063 /* ------------------------- Interrupt Number Definition ------------------------ */ 00064 00065 typedef enum { 00066 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ 00067 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00068 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 00069 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00070 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 00071 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 00072 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 00073 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 00074 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ 00075 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ 00076 RADIO_IRQn = 1, /*!< 1 RADIO */ 00077 UART0_IRQn = 2, /*!< 2 UART0 */ 00078 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ 00079 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ 00080 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ 00081 ADC_IRQn = 7, /*!< 7 ADC */ 00082 TIMER0_IRQn = 8, /*!< 8 TIMER0 */ 00083 TIMER1_IRQn = 9, /*!< 9 TIMER1 */ 00084 TIMER2_IRQn = 10, /*!< 10 TIMER2 */ 00085 RTC0_IRQn = 11, /*!< 11 RTC0 */ 00086 TEMP_IRQn = 12, /*!< 12 TEMP */ 00087 RNG_IRQn = 13, /*!< 13 RNG */ 00088 ECB_IRQn = 14, /*!< 14 ECB */ 00089 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ 00090 WDT_IRQn = 16, /*!< 16 WDT */ 00091 RTC1_IRQn = 17, /*!< 17 RTC1 */ 00092 QDEC_IRQn = 18, /*!< 18 QDEC */ 00093 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ 00094 SWI0_IRQn = 20, /*!< 20 SWI0 */ 00095 SWI1_IRQn = 21, /*!< 21 SWI1 */ 00096 SWI2_IRQn = 22, /*!< 22 SWI2 */ 00097 SWI3_IRQn = 23, /*!< 23 SWI3 */ 00098 SWI4_IRQn = 24, /*!< 24 SWI4 */ 00099 SWI5_IRQn = 25 /*!< 25 SWI5 */ 00100 } IRQn_Type ; 00101 00102 00103 /** @addtogroup Configuration_of_CMSIS 00104 * @{ 00105 */ 00106 00107 00108 /* ================================================================================ */ 00109 /* ================ Processor and Core Peripheral Section ================ */ 00110 /* ================================================================================ */ 00111 00112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ 00113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ 00114 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ 00116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00117 /** @} */ /* End of group Configuration_of_CMSIS */ 00118 00119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ 00120 #include "system_nrf51.h" /*!< nrf51 System */ 00121 00122 00123 /* ================================================================================ */ 00124 /* ================ Device Specific Peripheral Section ================ */ 00125 /* ================================================================================ */ 00126 00127 00128 /** @addtogroup Device_Peripheral_Registers 00129 * @{ 00130 */ 00131 00132 00133 /* ------------------- Start of section using anonymous unions ------------------ */ 00134 #if defined(__CC_ARM) 00135 #pragma push 00136 #pragma anon_unions 00137 #elif defined(__ICCARM__) 00138 #pragma language=extended 00139 #elif defined(__GNUC__) 00140 /* anonymous unions are enabled by default */ 00141 #elif defined(__TMS470__) 00142 /* anonymous unions are enabled by default */ 00143 #elif defined(__TASKING__) 00144 #pragma warning 586 00145 #else 00146 #warning Not supported compiler type 00147 #endif 00148 00149 00150 typedef struct { 00151 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ 00152 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ 00153 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ 00154 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ 00155 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ 00156 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ 00157 } AMLI_RAMPRI_Type; 00158 00159 typedef struct { 00160 __IO uint32_t SCK; /*!< Pin select for SCK. */ 00161 __IO uint32_t MOSI; /*!< Pin select for MOSI. */ 00162 __IO uint32_t MISO; /*!< Pin select for MISO. */ 00163 } SPIM_PSEL_Type; 00164 00165 typedef struct { 00166 __IO uint32_t PTR; /*!< Data pointer. */ 00167 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ 00168 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ 00169 } SPIM_RXD_Type; 00170 00171 typedef struct { 00172 __IO uint32_t PTR; /*!< Data pointer. */ 00173 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ 00174 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ 00175 } SPIM_TXD_Type; 00176 00177 typedef struct { 00178 __O uint32_t EN; /*!< Enable channel group. */ 00179 __O uint32_t DIS; /*!< Disable channel group. */ 00180 } PPI_TASKS_CHG_Type; 00181 00182 typedef struct { 00183 __IO uint32_t EEP; /*!< Channel event end-point. */ 00184 __IO uint32_t TEP; /*!< Channel task end-point. */ 00185 } PPI_CH_Type; 00186 00187 00188 /* ================================================================================ */ 00189 /* ================ POWER ================ */ 00190 /* ================================================================================ */ 00191 00192 00193 /** 00194 * @brief Power Control. (POWER) 00195 */ 00196 00197 typedef struct { /*!< POWER Structure */ 00198 __I uint32_t RESERVED0[30]; 00199 __O uint32_t TASKS_CONSTLAT ; /*!< Enable constant latency mode. */ 00200 __O uint32_t TASKS_LOWPWR ; /*!< Enable low power mode (variable latency). */ 00201 __I uint32_t RESERVED1[34]; 00202 __IO uint32_t EVENTS_POFWARN ; /*!< Power failure warning. */ 00203 __I uint32_t RESERVED2[126]; 00204 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00205 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00206 __I uint32_t RESERVED3[61]; 00207 __IO uint32_t RESETREAS ; /*!< Reset reason. */ 00208 __I uint32_t RESERVED4[9]; 00209 __I uint32_t RAMSTATUS ; /*!< Ram status register. */ 00210 __I uint32_t RESERVED5[53]; 00211 __O uint32_t SYSTEMOFF ; /*!< System off register. */ 00212 __I uint32_t RESERVED6[3]; 00213 __IO uint32_t POFCON ; /*!< Power failure configuration. */ 00214 __I uint32_t RESERVED7[2]; 00215 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained 00216 register. */ 00217 __I uint32_t RESERVED8; 00218 __IO uint32_t RAMON ; /*!< Ram on/off. */ 00219 __I uint32_t RESERVED9[7]; 00220 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register 00221 is a retained register. */ 00222 __I uint32_t RESERVED10[3]; 00223 __IO uint32_t RAMONB ; /*!< Ram on/off. */ 00224 __I uint32_t RESERVED11[8]; 00225 __IO uint32_t DCDCEN ; /*!< DCDC converter enable configuration register. */ 00226 __I uint32_t RESERVED12[291]; 00227 __IO uint32_t DCDCFORCE ; /*!< DCDC power-up force register. */ 00228 } NRF_POWER_Type; 00229 00230 00231 /* ================================================================================ */ 00232 /* ================ CLOCK ================ */ 00233 /* ================================================================================ */ 00234 00235 00236 /** 00237 * @brief Clock control. (CLOCK) 00238 */ 00239 00240 typedef struct { /*!< CLOCK Structure */ 00241 __O uint32_t TASKS_HFCLKSTART ; /*!< Start HFCLK clock source. */ 00242 __O uint32_t TASKS_HFCLKSTOP ; /*!< Stop HFCLK clock source. */ 00243 __O uint32_t TASKS_LFCLKSTART ; /*!< Start LFCLK clock source. */ 00244 __O uint32_t TASKS_LFCLKSTOP ; /*!< Stop LFCLK clock source. */ 00245 __O uint32_t TASKS_CAL ; /*!< Start calibration of LFCLK RC oscillator. */ 00246 __O uint32_t TASKS_CTSTART ; /*!< Start calibration timer. */ 00247 __O uint32_t TASKS_CTSTOP ; /*!< Stop calibration timer. */ 00248 __I uint32_t RESERVED0[57]; 00249 __IO uint32_t EVENTS_HFCLKSTARTED ; /*!< HFCLK oscillator started. */ 00250 __IO uint32_t EVENTS_LFCLKSTARTED ; /*!< LFCLK oscillator started. */ 00251 __I uint32_t RESERVED1; 00252 __IO uint32_t EVENTS_DONE ; /*!< Calibration of LFCLK RC oscillator completed. */ 00253 __IO uint32_t EVENTS_CTTO ; /*!< Calibration timer timeout. */ 00254 __I uint32_t RESERVED2[124]; 00255 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00256 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00257 __I uint32_t RESERVED3[63]; 00258 __I uint32_t HFCLKRUN ; /*!< Task HFCLKSTART trigger status. */ 00259 __I uint32_t HFCLKSTAT ; /*!< High frequency clock status. */ 00260 __I uint32_t RESERVED4; 00261 __I uint32_t LFCLKRUN ; /*!< Task LFCLKSTART triggered status. */ 00262 __I uint32_t LFCLKSTAT ; /*!< Low frequency clock status. */ 00263 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is 00264 triggered. */ 00265 __I uint32_t RESERVED5[62]; 00266 __IO uint32_t LFCLKSRC ; /*!< Clock source for the LFCLK clock. */ 00267 __I uint32_t RESERVED6[7]; 00268 __IO uint32_t CTIV ; /*!< Calibration timer interval. */ 00269 __I uint32_t RESERVED7[5]; 00270 __IO uint32_t XTALFREQ ; /*!< Crystal frequency. */ 00271 } NRF_CLOCK_Type; 00272 00273 00274 /* ================================================================================ */ 00275 /* ================ MPU ================ */ 00276 /* ================================================================================ */ 00277 00278 00279 /** 00280 * @brief Memory Protection Unit. (MPU) 00281 */ 00282 00283 typedef struct { /*!< MPU Structure */ 00284 __I uint32_t RESERVED0[330]; 00285 __IO uint32_t PERR0 ; /*!< Configuration of peripherals in mpu regions. */ 00286 __IO uint32_t RLENR0 ; /*!< Length of RAM region 0. */ 00287 __I uint32_t RESERVED1[52]; 00288 __IO uint32_t PROTENSET0 ; /*!< Erase and write protection bit enable set register. */ 00289 __IO uint32_t PROTENSET1 ; /*!< Erase and write protection bit enable set register. */ 00290 __IO uint32_t DISABLEINDEBUG ; /*!< Disable erase and write protection mechanism in debug mode. */ 00291 __IO uint32_t PROTBLOCKSIZE ; /*!< Erase and write protection block size. */ 00292 } NRF_MPU_Type; 00293 00294 00295 /* ================================================================================ */ 00296 /* ================ AMLI ================ */ 00297 /* ================================================================================ */ 00298 00299 00300 /** 00301 * @brief AHB Multi-Layer Interface. (AMLI) 00302 */ 00303 00304 typedef struct { /*!< AMLI Structure */ 00305 __I uint32_t RESERVED0[896]; 00306 AMLI_RAMPRI_Type RAMPRI ; /*!< RAM configurable priority configuration structure. */ 00307 } NRF_AMLI_Type; 00308 00309 00310 /* ================================================================================ */ 00311 /* ================ RADIO ================ */ 00312 /* ================================================================================ */ 00313 00314 00315 /** 00316 * @brief The radio. (RADIO) 00317 */ 00318 00319 typedef struct { /*!< RADIO Structure */ 00320 __O uint32_t TASKS_TXEN ; /*!< Enable radio in TX mode. */ 00321 __O uint32_t TASKS_RXEN ; /*!< Enable radio in RX mode. */ 00322 __O uint32_t TASKS_START ; /*!< Start radio. */ 00323 __O uint32_t TASKS_STOP ; /*!< Stop radio. */ 00324 __O uint32_t TASKS_DISABLE ; /*!< Disable radio. */ 00325 __O uint32_t TASKS_RSSISTART ; /*!< Start the RSSI and take one sample of the receive signal strength. */ 00326 __O uint32_t TASKS_RSSISTOP ; /*!< Stop the RSSI measurement. */ 00327 __O uint32_t TASKS_BCSTART ; /*!< Start the bit counter. */ 00328 __O uint32_t TASKS_BCSTOP ; /*!< Stop the bit counter. */ 00329 __I uint32_t RESERVED0[55]; 00330 __IO uint32_t EVENTS_READY ; /*!< Ready event. */ 00331 __IO uint32_t EVENTS_ADDRESS ; /*!< Address event. */ 00332 __IO uint32_t EVENTS_PAYLOAD ; /*!< Payload event. */ 00333 __IO uint32_t EVENTS_END ; /*!< End event. */ 00334 __IO uint32_t EVENTS_DISABLED ; /*!< Disable event. */ 00335 __IO uint32_t EVENTS_DEVMATCH ; /*!< A device address match occurred on the last received packet. */ 00336 __IO uint32_t EVENTS_DEVMISS ; /*!< No device address match occurred on the last received packet. */ 00337 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI 00338 sample is ready for readout at the RSSISAMPLE register. */ 00339 __I uint32_t RESERVED1[2]; 00340 __IO uint32_t EVENTS_BCMATCH ; /*!< Bit counter reached bit count value specified in BCC register. */ 00341 __I uint32_t RESERVED2[53]; 00342 __IO uint32_t SHORTS ; /*!< Shortcuts for the radio. */ 00343 __I uint32_t RESERVED3[64]; 00344 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00345 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00346 __I uint32_t RESERVED4[61]; 00347 __I uint32_t CRCSTATUS ; /*!< CRC status of received packet. */ 00348 __I uint32_t RESERVED5; 00349 __I uint32_t RXMATCH ; /*!< Received address. */ 00350 __I uint32_t RXCRC ; /*!< Received CRC. */ 00351 __I uint32_t DAI ; /*!< Device address match index. */ 00352 __I uint32_t RESERVED6[60]; 00353 __IO uint32_t PACKETPTR ; /*!< Packet pointer. Decision point: START task. */ 00354 __IO uint32_t FREQUENCY ; /*!< Frequency. */ 00355 __IO uint32_t TXPOWER ; /*!< Output power. */ 00356 __IO uint32_t MODE ; /*!< Data rate and modulation. */ 00357 __IO uint32_t PCNF0 ; /*!< Packet configuration 0. */ 00358 __IO uint32_t PCNF1 ; /*!< Packet configuration 1. */ 00359 __IO uint32_t BASE0 ; /*!< Radio base address 0. Decision point: START task. */ 00360 __IO uint32_t BASE1 ; /*!< Radio base address 1. Decision point: START task. */ 00361 __IO uint32_t PREFIX0 ; /*!< Prefixes bytes for logical addresses 0 to 3. */ 00362 __IO uint32_t PREFIX1 ; /*!< Prefixes bytes for logical addresses 4 to 7. */ 00363 __IO uint32_t TXADDRESS ; /*!< Transmit address select. */ 00364 __IO uint32_t RXADDRESSES ; /*!< Receive address select. */ 00365 __IO uint32_t CRCCNF ; /*!< CRC configuration. */ 00366 __IO uint32_t CRCPOLY ; /*!< CRC polynomial. */ 00367 __IO uint32_t CRCINIT ; /*!< CRC initial value. */ 00368 __IO uint32_t TEST ; /*!< Test features enable register. */ 00369 __IO uint32_t TIFS ; /*!< Inter Frame Spacing in microseconds. */ 00370 __I uint32_t RSSISAMPLE ; /*!< RSSI sample. */ 00371 __I uint32_t RESERVED7; 00372 __I uint32_t STATE ; /*!< Current radio state. */ 00373 __IO uint32_t DATAWHITEIV ; /*!< Data whitening initial value. */ 00374 __I uint32_t RESERVED8[2]; 00375 __IO uint32_t BCC ; /*!< Bit counter compare. */ 00376 __I uint32_t RESERVED9[39]; 00377 __IO uint32_t DAB[8]; /*!< Device address base segment. */ 00378 __IO uint32_t DAP[8]; /*!< Device address prefix. */ 00379 __IO uint32_t DACNF ; /*!< Device address match configuration. */ 00380 __I uint32_t RESERVED10[56]; 00381 __IO uint32_t OVERRIDE0 ; /*!< Trim value override register 0. */ 00382 __IO uint32_t OVERRIDE1 ; /*!< Trim value override register 1. */ 00383 __IO uint32_t OVERRIDE2 ; /*!< Trim value override register 2. */ 00384 __IO uint32_t OVERRIDE3 ; /*!< Trim value override register 3. */ 00385 __IO uint32_t OVERRIDE4 ; /*!< Trim value override register 4. */ 00386 __I uint32_t RESERVED11[561]; 00387 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00388 } NRF_RADIO_Type; 00389 00390 00391 /* ================================================================================ */ 00392 /* ================ UART ================ */ 00393 /* ================================================================================ */ 00394 00395 00396 /** 00397 * @brief Universal Asynchronous Receiver/Transmitter. (UART) 00398 */ 00399 00400 typedef struct { /*!< UART Structure */ 00401 __O uint32_t TASKS_STARTRX ; /*!< Start UART receiver. */ 00402 __O uint32_t TASKS_STOPRX ; /*!< Stop UART receiver. */ 00403 __O uint32_t TASKS_STARTTX ; /*!< Start UART transmitter. */ 00404 __O uint32_t TASKS_STOPTX ; /*!< Stop UART transmitter. */ 00405 __I uint32_t RESERVED0[3]; 00406 __O uint32_t TASKS_SUSPEND ; /*!< Suspend UART. */ 00407 __I uint32_t RESERVED1[56]; 00408 __IO uint32_t EVENTS_CTS ; /*!< CTS activated. */ 00409 __IO uint32_t EVENTS_NCTS ; /*!< CTS deactivated. */ 00410 __IO uint32_t EVENTS_RXDRDY ; /*!< Data received in RXD. */ 00411 __I uint32_t RESERVED2[4]; 00412 __IO uint32_t EVENTS_TXDRDY ; /*!< Data sent from TXD. */ 00413 __I uint32_t RESERVED3; 00414 __IO uint32_t EVENTS_ERROR ; /*!< Error detected. */ 00415 __I uint32_t RESERVED4[7]; 00416 __IO uint32_t EVENTS_RXTO ; /*!< Receiver timeout. */ 00417 __I uint32_t RESERVED5[46]; 00418 __IO uint32_t SHORTS ; /*!< Shortcuts for UART. */ 00419 __I uint32_t RESERVED6[64]; 00420 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00421 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00422 __I uint32_t RESERVED7[93]; 00423 __IO uint32_t ERRORSRC ; /*!< Error source. Write error field to 1 to clear error. */ 00424 __I uint32_t RESERVED8[31]; 00425 __IO uint32_t ENABLE ; /*!< Enable UART and acquire IOs. */ 00426 __I uint32_t RESERVED9; 00427 __IO uint32_t PSELRTS ; /*!< Pin select for RTS. */ 00428 __IO uint32_t PSELTXD ; /*!< Pin select for TXD. */ 00429 __IO uint32_t PSELCTS ; /*!< Pin select for CTS. */ 00430 __IO uint32_t PSELRXD ; /*!< Pin select for RXD. */ 00431 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. 00432 Once read the character is consumed. If read when no character 00433 available, the UART will stop working. */ 00434 __O uint32_t TXD ; /*!< TXD register. */ 00435 __I uint32_t RESERVED10; 00436 __IO uint32_t BAUDRATE ; /*!< UART Baudrate. */ 00437 __I uint32_t RESERVED11[17]; 00438 __IO uint32_t CONFIG ; /*!< Configuration of parity and hardware flow control register. */ 00439 __I uint32_t RESERVED12[675]; 00440 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00441 } NRF_UART_Type; 00442 00443 00444 /* ================================================================================ */ 00445 /* ================ SPI ================ */ 00446 /* ================================================================================ */ 00447 00448 00449 /** 00450 * @brief SPI master 0. (SPI) 00451 */ 00452 00453 typedef struct { /*!< SPI Structure */ 00454 __I uint32_t RESERVED0[66]; 00455 __IO uint32_t EVENTS_READY ; /*!< TXD byte sent and RXD byte received. */ 00456 __I uint32_t RESERVED1[126]; 00457 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00458 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00459 __I uint32_t RESERVED2[125]; 00460 __IO uint32_t ENABLE ; /*!< Enable SPI. */ 00461 __I uint32_t RESERVED3; 00462 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00463 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00464 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00465 __I uint32_t RESERVED4; 00466 __I uint32_t RXD ; /*!< RX data. */ 00467 __IO uint32_t TXD ; /*!< TX data. */ 00468 __I uint32_t RESERVED5; 00469 __IO uint32_t FREQUENCY ; /*!< SPI frequency */ 00470 __I uint32_t RESERVED6[11]; 00471 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00472 __I uint32_t RESERVED7[681]; 00473 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00474 } NRF_SPI_Type; 00475 00476 00477 /* ================================================================================ */ 00478 /* ================ TWI ================ */ 00479 /* ================================================================================ */ 00480 00481 00482 /** 00483 * @brief Two-wire interface master 0. (TWI) 00484 */ 00485 00486 typedef struct { /*!< TWI Structure */ 00487 __O uint32_t TASKS_STARTRX ; /*!< Start 2-Wire master receive sequence. */ 00488 __I uint32_t RESERVED0; 00489 __O uint32_t TASKS_STARTTX ; /*!< Start 2-Wire master transmit sequence. */ 00490 __I uint32_t RESERVED1[2]; 00491 __O uint32_t TASKS_STOP ; /*!< Stop 2-Wire transaction. */ 00492 __I uint32_t RESERVED2; 00493 __O uint32_t TASKS_SUSPEND ; /*!< Suspend 2-Wire transaction. */ 00494 __O uint32_t TASKS_RESUME ; /*!< Resume 2-Wire transaction. */ 00495 __I uint32_t RESERVED3[56]; 00496 __IO uint32_t EVENTS_STOPPED ; /*!< Two-wire stopped. */ 00497 __IO uint32_t EVENTS_RXDREADY ; /*!< Two-wire ready to deliver new RXD byte received. */ 00498 __I uint32_t RESERVED4[4]; 00499 __IO uint32_t EVENTS_TXDSENT ; /*!< Two-wire finished sending last TXD byte. */ 00500 __I uint32_t RESERVED5; 00501 __IO uint32_t EVENTS_ERROR ; /*!< Two-wire error detected. */ 00502 __I uint32_t RESERVED6[4]; 00503 __IO uint32_t EVENTS_BB ; /*!< Two-wire byte boundary. */ 00504 __I uint32_t RESERVED7[3]; 00505 __IO uint32_t EVENTS_SUSPENDED ; /*!< Two-wire suspended. */ 00506 __I uint32_t RESERVED8[45]; 00507 __IO uint32_t SHORTS ; /*!< Shortcuts for TWI. */ 00508 __I uint32_t RESERVED9[64]; 00509 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00510 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00511 __I uint32_t RESERVED10[110]; 00512 __IO uint32_t ERRORSRC ; /*!< Two-wire error source. Write error field to 1 to clear error. */ 00513 __I uint32_t RESERVED11[14]; 00514 __IO uint32_t ENABLE ; /*!< Enable two-wire master. */ 00515 __I uint32_t RESERVED12; 00516 __IO uint32_t PSELSCL ; /*!< Pin select for SCL. */ 00517 __IO uint32_t PSELSDA ; /*!< Pin select for SDA. */ 00518 __I uint32_t RESERVED13[2]; 00519 __I uint32_t RXD ; /*!< RX data register. */ 00520 __IO uint32_t TXD ; /*!< TX data register. */ 00521 __I uint32_t RESERVED14; 00522 __IO uint32_t FREQUENCY ; /*!< Two-wire frequency. */ 00523 __I uint32_t RESERVED15[24]; 00524 __IO uint32_t ADDRESS ; /*!< Address used in the two-wire transfer. */ 00525 __I uint32_t RESERVED16[668]; 00526 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00527 } NRF_TWI_Type; 00528 00529 00530 /* ================================================================================ */ 00531 /* ================ SPIS ================ */ 00532 /* ================================================================================ */ 00533 00534 00535 /** 00536 * @brief SPI slave 1. (SPIS) 00537 */ 00538 00539 typedef struct { /*!< SPIS Structure */ 00540 __I uint32_t RESERVED0[9]; 00541 __O uint32_t TASKS_ACQUIRE ; /*!< Acquire SPI semaphore. */ 00542 __O uint32_t TASKS_RELEASE ; /*!< Release SPI semaphore. */ 00543 __I uint32_t RESERVED1[54]; 00544 __IO uint32_t EVENTS_END ; /*!< Granted transaction completed. */ 00545 __I uint32_t RESERVED2[2]; 00546 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached */ 00547 __I uint32_t RESERVED3[5]; 00548 __IO uint32_t EVENTS_ACQUIRED ; /*!< Semaphore acquired. */ 00549 __I uint32_t RESERVED4[53]; 00550 __IO uint32_t SHORTS ; /*!< Shortcuts for SPIS. */ 00551 __I uint32_t RESERVED5[64]; 00552 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00553 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00554 __I uint32_t RESERVED6[61]; 00555 __I uint32_t SEMSTAT ; /*!< Semaphore status. */ 00556 __I uint32_t RESERVED7[15]; 00557 __IO uint32_t STATUS ; /*!< Status from last transaction. */ 00558 __I uint32_t RESERVED8[47]; 00559 __IO uint32_t ENABLE ; /*!< Enable SPIS. */ 00560 __I uint32_t RESERVED9; 00561 __IO uint32_t PSELSCK ; /*!< Pin select for SCK. */ 00562 __IO uint32_t PSELMISO ; /*!< Pin select for MISO. */ 00563 __IO uint32_t PSELMOSI ; /*!< Pin select for MOSI. */ 00564 __IO uint32_t PSELCSN ; /*!< Pin select for CSN. */ 00565 __I uint32_t RESERVED10[7]; 00566 __IO uint32_t RXDPTR ; /*!< RX data pointer. */ 00567 __IO uint32_t MAXRX ; /*!< Maximum number of bytes in the receive buffer. */ 00568 __I uint32_t AMOUNTRX ; /*!< Number of bytes received in last granted transaction. */ 00569 __I uint32_t RESERVED11; 00570 __IO uint32_t TXDPTR ; /*!< TX data pointer. */ 00571 __IO uint32_t MAXTX ; /*!< Maximum number of bytes in the transmit buffer. */ 00572 __I uint32_t AMOUNTTX ; /*!< Number of bytes transmitted in last granted transaction. */ 00573 __I uint32_t RESERVED12; 00574 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00575 __I uint32_t RESERVED13; 00576 __IO uint32_t DEF ; /*!< Default character. */ 00577 __I uint32_t RESERVED14[24]; 00578 __IO uint32_t ORC ; /*!< Over-read character. */ 00579 __I uint32_t RESERVED15[654]; 00580 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00581 } NRF_SPIS_Type; 00582 00583 00584 /* ================================================================================ */ 00585 /* ================ SPIM ================ */ 00586 /* ================================================================================ */ 00587 00588 00589 /** 00590 * @brief SPI master with easyDMA 1. (SPIM) 00591 */ 00592 00593 typedef struct { /*!< SPIM Structure */ 00594 __I uint32_t RESERVED0[4]; 00595 __O uint32_t TASKS_START ; /*!< Start SPI transaction. */ 00596 __O uint32_t TASKS_STOP ; /*!< Stop SPI transaction. */ 00597 __I uint32_t RESERVED1; 00598 __O uint32_t TASKS_SUSPEND ; /*!< Suspend SPI transaction. */ 00599 __O uint32_t TASKS_RESUME ; /*!< Resume SPI transaction. */ 00600 __I uint32_t RESERVED2[56]; 00601 __IO uint32_t EVENTS_STOPPED ; /*!< SPI transaction has stopped. */ 00602 __I uint32_t RESERVED3[2]; 00603 __IO uint32_t EVENTS_ENDRX ; /*!< End of RXD buffer reached. */ 00604 __I uint32_t RESERVED4[3]; 00605 __IO uint32_t EVENTS_ENDTX ; /*!< End of TXD buffer reached. */ 00606 __I uint32_t RESERVED5[10]; 00607 __IO uint32_t EVENTS_STARTED ; /*!< Transaction started. */ 00608 __I uint32_t RESERVED6[109]; 00609 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00610 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00611 __I uint32_t RESERVED7[125]; 00612 __IO uint32_t ENABLE ; /*!< Enable SPIM. */ 00613 __I uint32_t RESERVED8; 00614 SPIM_PSEL_Type PSEL ; /*!< Pin select configuration. */ 00615 __I uint32_t RESERVED9[4]; 00616 __IO uint32_t FREQUENCY ; /*!< SPI frequency. */ 00617 __I uint32_t RESERVED10[3]; 00618 SPIM_RXD_Type RXD ; /*!< RXD EasyDMA configuration and status. */ 00619 __I uint32_t RESERVED11; 00620 SPIM_TXD_Type TXD ; /*!< TXD EasyDMA configuration and status. */ 00621 __I uint32_t RESERVED12; 00622 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00623 __I uint32_t RESERVED13[26]; 00624 __IO uint32_t ORC ; /*!< Over-read character. */ 00625 __I uint32_t RESERVED14[654]; 00626 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00627 } NRF_SPIM_Type; 00628 00629 00630 /* ================================================================================ */ 00631 /* ================ GPIOTE ================ */ 00632 /* ================================================================================ */ 00633 00634 00635 /** 00636 * @brief GPIO tasks and events. (GPIOTE) 00637 */ 00638 00639 typedef struct { /*!< GPIOTE Structure */ 00640 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00641 __I uint32_t RESERVED0[60]; 00642 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ 00643 __I uint32_t RESERVED1[27]; 00644 __IO uint32_t EVENTS_PORT ; /*!< Event generated from multiple pins. */ 00645 __I uint32_t RESERVED2[97]; 00646 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00647 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00648 __I uint32_t RESERVED3[129]; 00649 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ 00650 __I uint32_t RESERVED4[695]; 00651 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00652 } NRF_GPIOTE_Type; 00653 00654 00655 /* ================================================================================ */ 00656 /* ================ ADC ================ */ 00657 /* ================================================================================ */ 00658 00659 00660 /** 00661 * @brief Analog to digital converter. (ADC) 00662 */ 00663 00664 typedef struct { /*!< ADC Structure */ 00665 __O uint32_t TASKS_START ; /*!< Start an ADC conversion. */ 00666 __O uint32_t TASKS_STOP ; /*!< Stop ADC. */ 00667 __I uint32_t RESERVED0[62]; 00668 __IO uint32_t EVENTS_END ; /*!< ADC conversion complete. */ 00669 __I uint32_t RESERVED1[128]; 00670 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00671 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00672 __I uint32_t RESERVED2[61]; 00673 __I uint32_t BUSY ; /*!< ADC busy register. */ 00674 __I uint32_t RESERVED3[63]; 00675 __IO uint32_t ENABLE ; /*!< ADC enable. */ 00676 __IO uint32_t CONFIG ; /*!< ADC configuration register. */ 00677 __I uint32_t RESULT ; /*!< Result of ADC conversion. */ 00678 __I uint32_t RESERVED4[700]; 00679 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00680 } NRF_ADC_Type; 00681 00682 00683 /* ================================================================================ */ 00684 /* ================ TIMER ================ */ 00685 /* ================================================================================ */ 00686 00687 00688 /** 00689 * @brief Timer 0. (TIMER) 00690 */ 00691 00692 typedef struct { /*!< TIMER Structure */ 00693 __O uint32_t TASKS_START ; /*!< Start Timer. */ 00694 __O uint32_t TASKS_STOP ; /*!< Stop Timer. */ 00695 __O uint32_t TASKS_COUNT ; /*!< Increment Timer (In counter mode). */ 00696 __O uint32_t TASKS_CLEAR ; /*!< Clear timer. */ 00697 __O uint32_t TASKS_SHUTDOWN ; /*!< Shutdown timer. */ 00698 __I uint32_t RESERVED0[11]; 00699 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ 00700 __I uint32_t RESERVED1[60]; 00701 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00702 __I uint32_t RESERVED2[44]; 00703 __IO uint32_t SHORTS ; /*!< Shortcuts for Timer. */ 00704 __I uint32_t RESERVED3[64]; 00705 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00706 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00707 __I uint32_t RESERVED4[126]; 00708 __IO uint32_t MODE ; /*!< Timer Mode selection. */ 00709 __IO uint32_t BITMODE ; /*!< Sets timer behaviour. */ 00710 __I uint32_t RESERVED5; 00711 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source 00712 clock frequency is divided by 2^SCALE. */ 00713 __I uint32_t RESERVED6[11]; 00714 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00715 __I uint32_t RESERVED7[683]; 00716 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00717 } NRF_TIMER_Type; 00718 00719 00720 /* ================================================================================ */ 00721 /* ================ RTC ================ */ 00722 /* ================================================================================ */ 00723 00724 00725 /** 00726 * @brief Real time counter 0. (RTC) 00727 */ 00728 00729 typedef struct { /*!< RTC Structure */ 00730 __O uint32_t TASKS_START ; /*!< Start RTC Counter. */ 00731 __O uint32_t TASKS_STOP ; /*!< Stop RTC Counter. */ 00732 __O uint32_t TASKS_CLEAR ; /*!< Clear RTC Counter. */ 00733 __O uint32_t TASKS_TRIGOVRFLW ; /*!< Set COUNTER to 0xFFFFFFF0. */ 00734 __I uint32_t RESERVED0[60]; 00735 __IO uint32_t EVENTS_TICK ; /*!< Event on COUNTER increment. */ 00736 __IO uint32_t EVENTS_OVRFLW ; /*!< Event on COUNTER overflow. */ 00737 __I uint32_t RESERVED1[14]; 00738 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ 00739 __I uint32_t RESERVED2[109]; 00740 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00741 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00742 __I uint32_t RESERVED3[13]; 00743 __IO uint32_t EVTEN ; /*!< Configures event enable routing to PPI for each RTC event. */ 00744 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives 00745 the value of EVTEN. */ 00746 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register 00747 gives the value of EVTEN. */ 00748 __I uint32_t RESERVED4[110]; 00749 __I uint32_t COUNTER ; /*!< Current COUNTER value. */ 00750 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). 00751 Must be written when RTC is STOPed. */ 00752 __I uint32_t RESERVED5[13]; 00753 __IO uint32_t CC[4]; /*!< Capture/compare registers. */ 00754 __I uint32_t RESERVED6[683]; 00755 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00756 } NRF_RTC_Type; 00757 00758 00759 /* ================================================================================ */ 00760 /* ================ TEMP ================ */ 00761 /* ================================================================================ */ 00762 00763 00764 /** 00765 * @brief Temperature Sensor. (TEMP) 00766 */ 00767 00768 typedef struct { /*!< TEMP Structure */ 00769 __O uint32_t TASKS_START ; /*!< Start temperature measurement. */ 00770 __O uint32_t TASKS_STOP ; /*!< Stop temperature measurement. */ 00771 __I uint32_t RESERVED0[62]; 00772 __IO uint32_t EVENTS_DATARDY ; /*!< Temperature measurement complete, data ready event. */ 00773 __I uint32_t RESERVED1[128]; 00774 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00775 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00776 __I uint32_t RESERVED2[127]; 00777 __I int32_t TEMP ; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ 00778 __I uint32_t RESERVED3[700]; 00779 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00780 } NRF_TEMP_Type; 00781 00782 00783 /* ================================================================================ */ 00784 /* ================ RNG ================ */ 00785 /* ================================================================================ */ 00786 00787 00788 /** 00789 * @brief Random Number Generator. (RNG) 00790 */ 00791 00792 typedef struct { /*!< RNG Structure */ 00793 __O uint32_t TASKS_START ; /*!< Start the random number generator. */ 00794 __O uint32_t TASKS_STOP ; /*!< Stop the random number generator. */ 00795 __I uint32_t RESERVED0[62]; 00796 __IO uint32_t EVENTS_VALRDY ; /*!< New random number generated and written to VALUE register. */ 00797 __I uint32_t RESERVED1[63]; 00798 __IO uint32_t SHORTS ; /*!< Shortcuts for the RNG. */ 00799 __I uint32_t RESERVED2[64]; 00800 __IO uint32_t INTENSET ; /*!< Interrupt enable set register */ 00801 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register */ 00802 __I uint32_t RESERVED3[126]; 00803 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00804 __I uint32_t VALUE ; /*!< RNG random number. */ 00805 __I uint32_t RESERVED4[700]; 00806 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00807 } NRF_RNG_Type; 00808 00809 00810 /* ================================================================================ */ 00811 /* ================ ECB ================ */ 00812 /* ================================================================================ */ 00813 00814 00815 /** 00816 * @brief AES ECB Mode Encryption. (ECB) 00817 */ 00818 00819 typedef struct { /*!< ECB Structure */ 00820 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this 00821 will not initiate a new encryption and the ERRORECB event will 00822 be triggered. */ 00823 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, 00824 this will will trigger the ERRORECB event. */ 00825 __I uint32_t RESERVED0[62]; 00826 __IO uint32_t EVENTS_ENDECB ; /*!< ECB block encrypt complete. */ 00827 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an 00828 error. */ 00829 __I uint32_t RESERVED1[127]; 00830 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00831 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00832 __I uint32_t RESERVED2[126]; 00833 __IO uint32_t ECBDATAPTR ; /*!< ECB block encrypt memory pointer. */ 00834 __I uint32_t RESERVED3[701]; 00835 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00836 } NRF_ECB_Type; 00837 00838 00839 /* ================================================================================ */ 00840 /* ================ AAR ================ */ 00841 /* ================================================================================ */ 00842 00843 00844 /** 00845 * @brief Accelerated Address Resolver. (AAR) 00846 */ 00847 00848 typedef struct { /*!< AAR Structure */ 00849 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK 00850 data structure. */ 00851 __I uint32_t RESERVED0; 00852 __O uint32_t TASKS_STOP ; /*!< Stop resolving addresses. */ 00853 __I uint32_t RESERVED1[61]; 00854 __IO uint32_t EVENTS_END ; /*!< Address resolution procedure completed. */ 00855 __IO uint32_t EVENTS_RESOLVED ; /*!< Address resolved. */ 00856 __IO uint32_t EVENTS_NOTRESOLVED ; /*!< Address not resolved. */ 00857 __I uint32_t RESERVED2[126]; 00858 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00859 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00860 __I uint32_t RESERVED3[61]; 00861 __I uint32_t STATUS ; /*!< Resolution status. */ 00862 __I uint32_t RESERVED4[63]; 00863 __IO uint32_t ENABLE ; /*!< Enable AAR. */ 00864 __IO uint32_t NIRK ; /*!< Number of Identity root Keys in the IRK data structure. */ 00865 __IO uint32_t IRKPTR ; /*!< Pointer to the IRK data structure. */ 00866 __I uint32_t RESERVED5; 00867 __IO uint32_t ADDRPTR ; /*!< Pointer to the resolvable address (6 bytes). */ 00868 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during 00869 resolution. A minimum of 3 bytes must be reserved. */ 00870 __I uint32_t RESERVED6[697]; 00871 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00872 } NRF_AAR_Type; 00873 00874 00875 /* ================================================================================ */ 00876 /* ================ CCM ================ */ 00877 /* ================================================================================ */ 00878 00879 00880 /** 00881 * @brief AES CCM Mode Encryption. (CCM) 00882 */ 00883 00884 typedef struct { /*!< CCM Structure */ 00885 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by 00886 itself when completed. */ 00887 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when 00888 completed. */ 00889 __O uint32_t TASKS_STOP ; /*!< Stop encrypt/decrypt. */ 00890 __I uint32_t RESERVED0[61]; 00891 __IO uint32_t EVENTS_ENDKSGEN ; /*!< Keystream generation completed. */ 00892 __IO uint32_t EVENTS_ENDCRYPT ; /*!< Encrypt/decrypt completed. */ 00893 __IO uint32_t EVENTS_ERROR ; /*!< Error happened. */ 00894 __I uint32_t RESERVED1[61]; 00895 __IO uint32_t SHORTS ; /*!< Shortcuts for the CCM. */ 00896 __I uint32_t RESERVED2[64]; 00897 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00898 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00899 __I uint32_t RESERVED3[61]; 00900 __I uint32_t MICSTATUS ; /*!< CCM RX MIC check result. */ 00901 __I uint32_t RESERVED4[63]; 00902 __IO uint32_t ENABLE ; /*!< CCM enable. */ 00903 __IO uint32_t MODE ; /*!< Operation mode. */ 00904 __IO uint32_t CNFPTR ; /*!< Pointer to a data structure holding AES key and NONCE vector. */ 00905 __IO uint32_t INPTR ; /*!< Pointer to the input packet. */ 00906 __IO uint32_t OUTPTR ; /*!< Pointer to the output packet. */ 00907 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during 00908 resolution. A minimum of 43 bytes must be reserved. */ 00909 __I uint32_t RESERVED5[697]; 00910 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00911 } NRF_CCM_Type; 00912 00913 00914 /* ================================================================================ */ 00915 /* ================ WDT ================ */ 00916 /* ================================================================================ */ 00917 00918 00919 /** 00920 * @brief Watchdog Timer. (WDT) 00921 */ 00922 00923 typedef struct { /*!< WDT Structure */ 00924 __O uint32_t TASKS_START ; /*!< Start the watchdog. */ 00925 __I uint32_t RESERVED0[63]; 00926 __IO uint32_t EVENTS_TIMEOUT ; /*!< Watchdog timeout. */ 00927 __I uint32_t RESERVED1[128]; 00928 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00929 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00930 __I uint32_t RESERVED2[61]; 00931 __I uint32_t RUNSTATUS ; /*!< Watchdog running status. */ 00932 __I uint32_t REQSTATUS ; /*!< Request status. */ 00933 __I uint32_t RESERVED3[63]; 00934 __IO uint32_t CRV ; /*!< Counter reload value in number of 32kiHz clock cycles. */ 00935 __IO uint32_t RREN ; /*!< Reload request enable. */ 00936 __IO uint32_t CONFIG ; /*!< Configuration register. */ 00937 __I uint32_t RESERVED4[60]; 00938 __O uint32_t RR[8]; /*!< Reload requests registers. */ 00939 __I uint32_t RESERVED5[631]; 00940 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00941 } NRF_WDT_Type; 00942 00943 00944 /* ================================================================================ */ 00945 /* ================ QDEC ================ */ 00946 /* ================================================================================ */ 00947 00948 00949 /** 00950 * @brief Rotary decoder. (QDEC) 00951 */ 00952 00953 typedef struct { /*!< QDEC Structure */ 00954 __O uint32_t TASKS_START ; /*!< Start the quadrature decoder. */ 00955 __O uint32_t TASKS_STOP ; /*!< Stop the quadrature decoder. */ 00956 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, 00957 and clears the ACC registers. */ 00958 __I uint32_t RESERVED0[61]; 00959 __IO uint32_t EVENTS_SAMPLERDY ; /*!< A new sample is written to the sample register. */ 00960 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and 00961 ACC register different than zero. */ 00962 __IO uint32_t EVENTS_ACCOF ; /*!< ACC or ACCDBL register overflow. */ 00963 __I uint32_t RESERVED1[61]; 00964 __IO uint32_t SHORTS ; /*!< Shortcuts for the QDEC. */ 00965 __I uint32_t RESERVED2[64]; 00966 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 00967 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 00968 __I uint32_t RESERVED3[125]; 00969 __IO uint32_t ENABLE ; /*!< Enable the QDEC. */ 00970 __IO uint32_t LEDPOL ; /*!< LED output pin polarity. */ 00971 __IO uint32_t SAMPLEPER ; /*!< Sample period. */ 00972 __I int32_t SAMPLE ; /*!< Motion sample value. */ 00973 __IO uint32_t REPORTPER ; /*!< Number of samples to generate an EVENT_REPORTRDY. */ 00974 __I int32_t ACC ; /*!< Accumulated valid transitions register. */ 00975 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC 00976 task. */ 00977 __IO uint32_t PSELLED ; /*!< Pin select for LED output. */ 00978 __IO uint32_t PSELA ; /*!< Pin select for phase A input. */ 00979 __IO uint32_t PSELB ; /*!< Pin select for phase B input. */ 00980 __IO uint32_t DBFEN ; /*!< Enable debouncer input filters. */ 00981 __I uint32_t RESERVED4[5]; 00982 __IO uint32_t LEDPRE ; /*!< Time LED is switched ON before the sample. */ 00983 __I uint32_t ACCDBL ; /*!< Accumulated double (error) transitions register. */ 00984 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC 00985 task. */ 00986 __I uint32_t RESERVED5[684]; 00987 __IO uint32_t POWER ; /*!< Peripheral power control. */ 00988 } NRF_QDEC_Type; 00989 00990 00991 /* ================================================================================ */ 00992 /* ================ LPCOMP ================ */ 00993 /* ================================================================================ */ 00994 00995 00996 /** 00997 * @brief Low power comparator. (LPCOMP) 00998 */ 00999 01000 typedef struct { /*!< LPCOMP Structure */ 01001 __O uint32_t TASKS_START ; /*!< Start the comparator. */ 01002 __O uint32_t TASKS_STOP ; /*!< Stop the comparator. */ 01003 __O uint32_t TASKS_SAMPLE ; /*!< Sample comparator value. */ 01004 __I uint32_t RESERVED0[61]; 01005 __IO uint32_t EVENTS_READY ; /*!< LPCOMP is ready and output is valid. */ 01006 __IO uint32_t EVENTS_DOWN ; /*!< Input voltage crossed the threshold going down. */ 01007 __IO uint32_t EVENTS_UP ; /*!< Input voltage crossed the threshold going up. */ 01008 __IO uint32_t EVENTS_CROSS ; /*!< Input voltage crossed the threshold in any direction. */ 01009 __I uint32_t RESERVED1[60]; 01010 __IO uint32_t SHORTS ; /*!< Shortcuts for the LPCOMP. */ 01011 __I uint32_t RESERVED2[64]; 01012 __IO uint32_t INTENSET ; /*!< Interrupt enable set register. */ 01013 __IO uint32_t INTENCLR ; /*!< Interrupt enable clear register. */ 01014 __I uint32_t RESERVED3[61]; 01015 __I uint32_t RESULT ; /*!< Result of last compare. */ 01016 __I uint32_t RESERVED4[63]; 01017 __IO uint32_t ENABLE ; /*!< Enable the LPCOMP. */ 01018 __IO uint32_t PSEL ; /*!< Input pin select. */ 01019 __IO uint32_t REFSEL ; /*!< Reference select. */ 01020 __IO uint32_t EXTREFSEL ; /*!< External reference select. */ 01021 __I uint32_t RESERVED5[4]; 01022 __IO uint32_t ANADETECT ; /*!< Analog detect configuration. */ 01023 __I uint32_t RESERVED6[694]; 01024 __IO uint32_t POWER ; /*!< Peripheral power control. */ 01025 } NRF_LPCOMP_Type; 01026 01027 01028 /* ================================================================================ */ 01029 /* ================ SWI ================ */ 01030 /* ================================================================================ */ 01031 01032 01033 /** 01034 * @brief SW Interrupts. (SWI) 01035 */ 01036 01037 typedef struct { /*!< SWI Structure */ 01038 __I uint32_t UNUSED ; /*!< Unused. */ 01039 } NRF_SWI_Type; 01040 01041 01042 /* ================================================================================ */ 01043 /* ================ NVMC ================ */ 01044 /* ================================================================================ */ 01045 01046 01047 /** 01048 * @brief Non Volatile Memory Controller. (NVMC) 01049 */ 01050 01051 typedef struct { /*!< NVMC Structure */ 01052 __I uint32_t RESERVED0[256]; 01053 __I uint32_t READY ; /*!< Ready flag. */ 01054 __I uint32_t RESERVED1[64]; 01055 __IO uint32_t CONFIG ; /*!< Configuration register. */ 01056 01057 union { 01058 __IO uint32_t ERASEPCR1 ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01059 __IO uint32_t ERASEPAGE ; /*!< Register for erasing a non-protected non-volatile memory page. */ 01060 }; 01061 __IO uint32_t ERASEALL ; /*!< Register for erasing all non-volatile user memory. */ 01062 __IO uint32_t ERASEPCR0 ; /*!< Register for erasing a protected non-volatile memory page. */ 01063 __IO uint32_t ERASEUICR ; /*!< Register for start erasing User Information Congfiguration Registers. */ 01064 } NRF_NVMC_Type; 01065 01066 01067 /* ================================================================================ */ 01068 /* ================ PPI ================ */ 01069 /* ================================================================================ */ 01070 01071 01072 /** 01073 * @brief PPI controller. (PPI) 01074 */ 01075 01076 typedef struct { /*!< PPI Structure */ 01077 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ 01078 __I uint32_t RESERVED0[312]; 01079 __IO uint32_t CHEN ; /*!< Channel enable. */ 01080 __IO uint32_t CHENSET ; /*!< Channel enable set. */ 01081 __IO uint32_t CHENCLR ; /*!< Channel enable clear. */ 01082 __I uint32_t RESERVED1; 01083 PPI_CH_Type CH[16]; /*!< PPI Channel. */ 01084 __I uint32_t RESERVED2[156]; 01085 __IO uint32_t CHG[4]; /*!< Channel group configuration. */ 01086 } NRF_PPI_Type; 01087 01088 01089 /* ================================================================================ */ 01090 /* ================ FICR ================ */ 01091 /* ================================================================================ */ 01092 01093 01094 /** 01095 * @brief Factory Information Configuration. (FICR) 01096 */ 01097 01098 typedef struct { /*!< FICR Structure */ 01099 __I uint32_t RESERVED0[4]; 01100 __I uint32_t CODEPAGESIZE ; /*!< Code memory page size in bytes. */ 01101 __I uint32_t CODESIZE ; /*!< Code memory size in pages. */ 01102 __I uint32_t RESERVED1[4]; 01103 __I uint32_t CLENR0 ; /*!< Length of code region 0 in bytes. */ 01104 __I uint32_t PPFC ; /*!< Pre-programmed factory code present. */ 01105 __I uint32_t RESERVED2; 01106 __I uint32_t NUMRAMBLOCK ; /*!< Number of individualy controllable RAM blocks. */ 01107 01108 union { 01109 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is 01110 kept for backward compatinility purposes. Use SIZERAMBLOCKS 01111 instead. */ 01112 __I uint32_t SIZERAMBLOCKS ; /*!< Size of RAM blocks in bytes. */ 01113 }; 01114 __I uint32_t RESERVED3[5]; 01115 __I uint32_t CONFIGID ; /*!< Configuration identifier. */ 01116 __I uint32_t DEVICEID[2]; /*!< Device identifier. */ 01117 __I uint32_t RESERVED4[6]; 01118 __I uint32_t ER[4]; /*!< Encryption root. */ 01119 __I uint32_t IR[4]; /*!< Identity root. */ 01120 __I uint32_t DEVICEADDRTYPE ; /*!< Device address type. */ 01121 __I uint32_t DEVICEADDR[2]; /*!< Device address. */ 01122 __I uint32_t OVERRIDEEN ; /*!< Radio calibration override enable. */ 01123 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit 01124 mode. */ 01125 __I uint32_t RESERVED5[10]; 01126 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit 01127 mode. */ 01128 } NRF_FICR_Type; 01129 01130 01131 /* ================================================================================ */ 01132 /* ================ UICR ================ */ 01133 /* ================================================================================ */ 01134 01135 01136 /** 01137 * @brief User Information Configuration. (UICR) 01138 */ 01139 01140 typedef struct { /*!< UICR Structure */ 01141 __IO uint32_t CLENR0 ; /*!< Length of code region 0. */ 01142 __IO uint32_t RBPCONF ; /*!< Readback protection configuration. */ 01143 __IO uint32_t XTALFREQ ; /*!< Reset value for CLOCK XTALFREQ register. */ 01144 __I uint32_t RESERVED0; 01145 __I uint32_t FWID ; /*!< Firmware ID. */ 01146 01147 union { 01148 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ 01149 __IO uint32_t BOOTLOADERADDR ; /*!< Bootloader start address. */ 01150 }; 01151 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ 01152 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ 01153 } NRF_UICR_Type; 01154 01155 01156 /* ================================================================================ */ 01157 /* ================ GPIO ================ */ 01158 /* ================================================================================ */ 01159 01160 01161 /** 01162 * @brief General purpose input and output. (GPIO) 01163 */ 01164 01165 typedef struct { /*!< GPIO Structure */ 01166 __I uint32_t RESERVED0[321]; 01167 __IO uint32_t OUT ; /*!< Write GPIO port. */ 01168 __IO uint32_t OUTSET ; /*!< Set individual bits in GPIO port. */ 01169 __IO uint32_t OUTCLR ; /*!< Clear individual bits in GPIO port. */ 01170 __I uint32_t IN ; /*!< Read GPIO port. */ 01171 __IO uint32_t DIR ; /*!< Direction of GPIO pins. */ 01172 __IO uint32_t DIRSET ; /*!< DIR set register. */ 01173 __IO uint32_t DIRCLR ; /*!< DIR clear register. */ 01174 __I uint32_t RESERVED1[120]; 01175 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ 01176 } NRF_GPIO_Type; 01177 01178 01179 /* -------------------- End of section using anonymous unions ------------------- */ 01180 #if defined(__CC_ARM) 01181 #pragma pop 01182 #elif defined(__ICCARM__) 01183 /* leave anonymous unions enabled */ 01184 #elif defined(__GNUC__) 01185 /* anonymous unions are enabled by default */ 01186 #elif defined(__TMS470__) 01187 /* anonymous unions are enabled by default */ 01188 #elif defined(__TASKING__) 01189 #pragma warning restore 01190 #else 01191 #warning Not supported compiler type 01192 #endif 01193 01194 01195 01196 01197 /* ================================================================================ */ 01198 /* ================ Peripheral memory map ================ */ 01199 /* ================================================================================ */ 01200 01201 #define NRF_POWER_BASE 0x40000000UL 01202 #define NRF_CLOCK_BASE 0x40000000UL 01203 #define NRF_MPU_BASE 0x40000000UL 01204 #define NRF_AMLI_BASE 0x40000000UL 01205 #define NRF_RADIO_BASE 0x40001000UL 01206 #define NRF_UART0_BASE 0x40002000UL 01207 #define NRF_SPI0_BASE 0x40003000UL 01208 #define NRF_TWI0_BASE 0x40003000UL 01209 #define NRF_SPI1_BASE 0x40004000UL 01210 #define NRF_TWI1_BASE 0x40004000UL 01211 #define NRF_SPIS1_BASE 0x40004000UL 01212 #define NRF_SPIM1_BASE 0x40004000UL 01213 #define NRF_GPIOTE_BASE 0x40006000UL 01214 #define NRF_ADC_BASE 0x40007000UL 01215 #define NRF_TIMER0_BASE 0x40008000UL 01216 #define NRF_TIMER1_BASE 0x40009000UL 01217 #define NRF_TIMER2_BASE 0x4000A000UL 01218 #define NRF_RTC0_BASE 0x4000B000UL 01219 #define NRF_TEMP_BASE 0x4000C000UL 01220 #define NRF_RNG_BASE 0x4000D000UL 01221 #define NRF_ECB_BASE 0x4000E000UL 01222 #define NRF_AAR_BASE 0x4000F000UL 01223 #define NRF_CCM_BASE 0x4000F000UL 01224 #define NRF_WDT_BASE 0x40010000UL 01225 #define NRF_RTC1_BASE 0x40011000UL 01226 #define NRF_QDEC_BASE 0x40012000UL 01227 #define NRF_LPCOMP_BASE 0x40013000UL 01228 #define NRF_SWI_BASE 0x40014000UL 01229 #define NRF_NVMC_BASE 0x4001E000UL 01230 #define NRF_PPI_BASE 0x4001F000UL 01231 #define NRF_FICR_BASE 0x10000000UL 01232 #define NRF_UICR_BASE 0x10001000UL 01233 #define NRF_GPIO_BASE 0x50000000UL 01234 01235 01236 /* ================================================================================ */ 01237 /* ================ Peripheral declaration ================ */ 01238 /* ================================================================================ */ 01239 01240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) 01241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) 01242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) 01243 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) 01244 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) 01245 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) 01246 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) 01247 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) 01248 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) 01249 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) 01250 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) 01251 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) 01252 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) 01253 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) 01254 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) 01255 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) 01256 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) 01257 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) 01258 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) 01259 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) 01260 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) 01261 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) 01262 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) 01263 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) 01264 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) 01265 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) 01266 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) 01267 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) 01268 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) 01269 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) 01270 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) 01271 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) 01272 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) 01273 01274 01275 /** @} */ /* End of group Device_Peripheral_Registers */ 01276 /** @} */ /* End of group nrf51 */ 01277 /** @} */ /* End of group Nordic Semiconductor */ 01278 01279 #ifdef __cplusplus 01280 } 01281 #endif 01282 01283 01284 #endif /* nrf51_H */ 01285 01286
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