Francesco Pavoni
BLE_Nano nRF51 Central heart rate
nRF51_SDK_11/components/toolchain/CMSIS/Include/core_cm0.h@0:2b9b5764efb5, 2016-05-26 (annotated)
- Committer:
- FranKP2138
- Date:
- Thu May 26 10:12:27 2016 +0000
- Revision:
- 0:2b9b5764efb5
RedBearLab BLE_Nano Central role for heart rate
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| FranKP2138 | 0:2b9b5764efb5 | 1 | /**************************************************************************//** |
| FranKP2138 | 0:2b9b5764efb5 | 2 | * @file core_cm0.h |
| FranKP2138 | 0:2b9b5764efb5 | 3 | * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File |
| FranKP2138 | 0:2b9b5764efb5 | 4 | * @version V4.30 |
| FranKP2138 | 0:2b9b5764efb5 | 5 | * @date 20. October 2015 |
| FranKP2138 | 0:2b9b5764efb5 | 6 | ******************************************************************************/ |
| FranKP2138 | 0:2b9b5764efb5 | 7 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
| FranKP2138 | 0:2b9b5764efb5 | 8 | |
| FranKP2138 | 0:2b9b5764efb5 | 9 | All rights reserved. |
| FranKP2138 | 0:2b9b5764efb5 | 10 | Redistribution and use in source and binary forms, with or without |
| FranKP2138 | 0:2b9b5764efb5 | 11 | modification, are permitted provided that the following conditions are met: |
| FranKP2138 | 0:2b9b5764efb5 | 12 | - Redistributions of source code must retain the above copyright |
| FranKP2138 | 0:2b9b5764efb5 | 13 | notice, this list of conditions and the following disclaimer. |
| FranKP2138 | 0:2b9b5764efb5 | 14 | - Redistributions in binary form must reproduce the above copyright |
| FranKP2138 | 0:2b9b5764efb5 | 15 | notice, this list of conditions and the following disclaimer in the |
| FranKP2138 | 0:2b9b5764efb5 | 16 | documentation and/or other materials provided with the distribution. |
| FranKP2138 | 0:2b9b5764efb5 | 17 | - Neither the name of ARM nor the names of its contributors may be used |
| FranKP2138 | 0:2b9b5764efb5 | 18 | to endorse or promote products derived from this software without |
| FranKP2138 | 0:2b9b5764efb5 | 19 | specific prior written permission. |
| FranKP2138 | 0:2b9b5764efb5 | 20 | * |
| FranKP2138 | 0:2b9b5764efb5 | 21 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| FranKP2138 | 0:2b9b5764efb5 | 22 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| FranKP2138 | 0:2b9b5764efb5 | 23 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| FranKP2138 | 0:2b9b5764efb5 | 24 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
| FranKP2138 | 0:2b9b5764efb5 | 25 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| FranKP2138 | 0:2b9b5764efb5 | 26 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| FranKP2138 | 0:2b9b5764efb5 | 27 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| FranKP2138 | 0:2b9b5764efb5 | 28 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| FranKP2138 | 0:2b9b5764efb5 | 29 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| FranKP2138 | 0:2b9b5764efb5 | 30 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| FranKP2138 | 0:2b9b5764efb5 | 31 | POSSIBILITY OF SUCH DAMAGE. |
| FranKP2138 | 0:2b9b5764efb5 | 32 | ---------------------------------------------------------------------------*/ |
| FranKP2138 | 0:2b9b5764efb5 | 33 | |
| FranKP2138 | 0:2b9b5764efb5 | 34 | |
| FranKP2138 | 0:2b9b5764efb5 | 35 | #if defined ( __ICCARM__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 36 | #pragma system_include /* treat file as system include file for MISRA check */ |
| FranKP2138 | 0:2b9b5764efb5 | 37 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| FranKP2138 | 0:2b9b5764efb5 | 38 | #pragma clang system_header /* treat file as system include file */ |
| FranKP2138 | 0:2b9b5764efb5 | 39 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 40 | |
| FranKP2138 | 0:2b9b5764efb5 | 41 | #ifndef __CORE_CM0_H_GENERIC |
| FranKP2138 | 0:2b9b5764efb5 | 42 | #define __CORE_CM0_H_GENERIC |
| FranKP2138 | 0:2b9b5764efb5 | 43 | |
| FranKP2138 | 0:2b9b5764efb5 | 44 | #include <stdint.h> |
| FranKP2138 | 0:2b9b5764efb5 | 45 | |
| FranKP2138 | 0:2b9b5764efb5 | 46 | #ifdef __cplusplus |
| FranKP2138 | 0:2b9b5764efb5 | 47 | extern "C" { |
| FranKP2138 | 0:2b9b5764efb5 | 48 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 49 | |
| FranKP2138 | 0:2b9b5764efb5 | 50 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 51 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
| FranKP2138 | 0:2b9b5764efb5 | 52 | CMSIS violates the following MISRA-C:2004 rules: |
| FranKP2138 | 0:2b9b5764efb5 | 53 | |
| FranKP2138 | 0:2b9b5764efb5 | 54 | \li Required Rule 8.5, object/function definition in header file.<br> |
| FranKP2138 | 0:2b9b5764efb5 | 55 | Function definitions in header files are used to allow 'inlining'. |
| FranKP2138 | 0:2b9b5764efb5 | 56 | |
| FranKP2138 | 0:2b9b5764efb5 | 57 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
| FranKP2138 | 0:2b9b5764efb5 | 58 | Unions are used for effective representation of core registers. |
| FranKP2138 | 0:2b9b5764efb5 | 59 | |
| FranKP2138 | 0:2b9b5764efb5 | 60 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
| FranKP2138 | 0:2b9b5764efb5 | 61 | Function-like macros are used to allow more efficient code. |
| FranKP2138 | 0:2b9b5764efb5 | 62 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 63 | |
| FranKP2138 | 0:2b9b5764efb5 | 64 | |
| FranKP2138 | 0:2b9b5764efb5 | 65 | /******************************************************************************* |
| FranKP2138 | 0:2b9b5764efb5 | 66 | * CMSIS definitions |
| FranKP2138 | 0:2b9b5764efb5 | 67 | ******************************************************************************/ |
| FranKP2138 | 0:2b9b5764efb5 | 68 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 69 | \ingroup Cortex_M0 |
| FranKP2138 | 0:2b9b5764efb5 | 70 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 71 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 72 | |
| FranKP2138 | 0:2b9b5764efb5 | 73 | /* CMSIS CM0 definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 74 | #define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ |
| FranKP2138 | 0:2b9b5764efb5 | 75 | #define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ |
| FranKP2138 | 0:2b9b5764efb5 | 76 | #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ |
| FranKP2138 | 0:2b9b5764efb5 | 77 | __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ |
| FranKP2138 | 0:2b9b5764efb5 | 78 | |
| FranKP2138 | 0:2b9b5764efb5 | 79 | #define __CORTEX_M (0x00U) /*!< Cortex-M Core */ |
| FranKP2138 | 0:2b9b5764efb5 | 80 | |
| FranKP2138 | 0:2b9b5764efb5 | 81 | |
| FranKP2138 | 0:2b9b5764efb5 | 82 | #if defined ( __CC_ARM ) |
| FranKP2138 | 0:2b9b5764efb5 | 83 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 84 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 85 | #define __STATIC_INLINE static __inline |
| FranKP2138 | 0:2b9b5764efb5 | 86 | |
| FranKP2138 | 0:2b9b5764efb5 | 87 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| FranKP2138 | 0:2b9b5764efb5 | 88 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 89 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 90 | #define __STATIC_INLINE static __inline |
| FranKP2138 | 0:2b9b5764efb5 | 91 | |
| FranKP2138 | 0:2b9b5764efb5 | 92 | #elif defined ( __GNUC__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 93 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 94 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 95 | #define __STATIC_INLINE static inline |
| FranKP2138 | 0:2b9b5764efb5 | 96 | |
| FranKP2138 | 0:2b9b5764efb5 | 97 | #elif defined ( __ICCARM__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 98 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 99 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
| FranKP2138 | 0:2b9b5764efb5 | 100 | #define __STATIC_INLINE static inline |
| FranKP2138 | 0:2b9b5764efb5 | 101 | |
| FranKP2138 | 0:2b9b5764efb5 | 102 | #elif defined ( __TMS470__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 103 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 104 | #define __STATIC_INLINE static inline |
| FranKP2138 | 0:2b9b5764efb5 | 105 | |
| FranKP2138 | 0:2b9b5764efb5 | 106 | #elif defined ( __TASKING__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 107 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 108 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 109 | #define __STATIC_INLINE static inline |
| FranKP2138 | 0:2b9b5764efb5 | 110 | |
| FranKP2138 | 0:2b9b5764efb5 | 111 | #elif defined ( __CSMC__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 112 | #define __packed |
| FranKP2138 | 0:2b9b5764efb5 | 113 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
| FranKP2138 | 0:2b9b5764efb5 | 114 | #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ |
| FranKP2138 | 0:2b9b5764efb5 | 115 | #define __STATIC_INLINE static inline |
| FranKP2138 | 0:2b9b5764efb5 | 116 | |
| FranKP2138 | 0:2b9b5764efb5 | 117 | #else |
| FranKP2138 | 0:2b9b5764efb5 | 118 | #error Unknown compiler |
| FranKP2138 | 0:2b9b5764efb5 | 119 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 120 | |
| FranKP2138 | 0:2b9b5764efb5 | 121 | /** __FPU_USED indicates whether an FPU is used or not. |
| FranKP2138 | 0:2b9b5764efb5 | 122 | This core does not support an FPU at all |
| FranKP2138 | 0:2b9b5764efb5 | 123 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 124 | #define __FPU_USED 0U |
| FranKP2138 | 0:2b9b5764efb5 | 125 | |
| FranKP2138 | 0:2b9b5764efb5 | 126 | #if defined ( __CC_ARM ) |
| FranKP2138 | 0:2b9b5764efb5 | 127 | #if defined __TARGET_FPU_VFP |
| FranKP2138 | 0:2b9b5764efb5 | 128 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 129 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 130 | |
| FranKP2138 | 0:2b9b5764efb5 | 131 | #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
| FranKP2138 | 0:2b9b5764efb5 | 132 | #if defined __ARM_PCS_VFP |
| FranKP2138 | 0:2b9b5764efb5 | 133 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 134 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 135 | |
| FranKP2138 | 0:2b9b5764efb5 | 136 | #elif defined ( __GNUC__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 137 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
| FranKP2138 | 0:2b9b5764efb5 | 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 139 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 140 | |
| FranKP2138 | 0:2b9b5764efb5 | 141 | #elif defined ( __ICCARM__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 142 | #if defined __ARMVFP__ |
| FranKP2138 | 0:2b9b5764efb5 | 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 144 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 145 | |
| FranKP2138 | 0:2b9b5764efb5 | 146 | #elif defined ( __TMS470__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 147 | #if defined __TI_VFP_SUPPORT__ |
| FranKP2138 | 0:2b9b5764efb5 | 148 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 149 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 150 | |
| FranKP2138 | 0:2b9b5764efb5 | 151 | #elif defined ( __TASKING__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 152 | #if defined __FPU_VFP__ |
| FranKP2138 | 0:2b9b5764efb5 | 153 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 154 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 155 | |
| FranKP2138 | 0:2b9b5764efb5 | 156 | #elif defined ( __CSMC__ ) |
| FranKP2138 | 0:2b9b5764efb5 | 157 | #if ( __CSMC__ & 0x400U) |
| FranKP2138 | 0:2b9b5764efb5 | 158 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
| FranKP2138 | 0:2b9b5764efb5 | 159 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 160 | |
| FranKP2138 | 0:2b9b5764efb5 | 161 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 162 | |
| FranKP2138 | 0:2b9b5764efb5 | 163 | #include "core_cmInstr.h" /* Core Instruction Access */ |
| FranKP2138 | 0:2b9b5764efb5 | 164 | #include "core_cmFunc.h" /* Core Function Access */ |
| FranKP2138 | 0:2b9b5764efb5 | 165 | |
| FranKP2138 | 0:2b9b5764efb5 | 166 | #ifdef __cplusplus |
| FranKP2138 | 0:2b9b5764efb5 | 167 | } |
| FranKP2138 | 0:2b9b5764efb5 | 168 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 169 | |
| FranKP2138 | 0:2b9b5764efb5 | 170 | #endif /* __CORE_CM0_H_GENERIC */ |
| FranKP2138 | 0:2b9b5764efb5 | 171 | |
| FranKP2138 | 0:2b9b5764efb5 | 172 | #ifndef __CMSIS_GENERIC |
| FranKP2138 | 0:2b9b5764efb5 | 173 | |
| FranKP2138 | 0:2b9b5764efb5 | 174 | #ifndef __CORE_CM0_H_DEPENDANT |
| FranKP2138 | 0:2b9b5764efb5 | 175 | #define __CORE_CM0_H_DEPENDANT |
| FranKP2138 | 0:2b9b5764efb5 | 176 | |
| FranKP2138 | 0:2b9b5764efb5 | 177 | #ifdef __cplusplus |
| FranKP2138 | 0:2b9b5764efb5 | 178 | extern "C" { |
| FranKP2138 | 0:2b9b5764efb5 | 179 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 180 | |
| FranKP2138 | 0:2b9b5764efb5 | 181 | /* check device defines and use defaults */ |
| FranKP2138 | 0:2b9b5764efb5 | 182 | #if defined __CHECK_DEVICE_DEFINES |
| FranKP2138 | 0:2b9b5764efb5 | 183 | #ifndef __CM0_REV |
| FranKP2138 | 0:2b9b5764efb5 | 184 | #define __CM0_REV 0x0000U |
| FranKP2138 | 0:2b9b5764efb5 | 185 | #warning "__CM0_REV not defined in device header file; using default!" |
| FranKP2138 | 0:2b9b5764efb5 | 186 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 187 | |
| FranKP2138 | 0:2b9b5764efb5 | 188 | #ifndef __NVIC_PRIO_BITS |
| FranKP2138 | 0:2b9b5764efb5 | 189 | #define __NVIC_PRIO_BITS 2U |
| FranKP2138 | 0:2b9b5764efb5 | 190 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
| FranKP2138 | 0:2b9b5764efb5 | 191 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 192 | |
| FranKP2138 | 0:2b9b5764efb5 | 193 | #ifndef __Vendor_SysTickConfig |
| FranKP2138 | 0:2b9b5764efb5 | 194 | #define __Vendor_SysTickConfig 0U |
| FranKP2138 | 0:2b9b5764efb5 | 195 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
| FranKP2138 | 0:2b9b5764efb5 | 196 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 197 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 198 | |
| FranKP2138 | 0:2b9b5764efb5 | 199 | /* IO definitions (access restrictions to peripheral registers) */ |
| FranKP2138 | 0:2b9b5764efb5 | 200 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 201 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
| FranKP2138 | 0:2b9b5764efb5 | 202 | |
| FranKP2138 | 0:2b9b5764efb5 | 203 | <strong>IO Type Qualifiers</strong> are used |
| FranKP2138 | 0:2b9b5764efb5 | 204 | \li to specify the access to peripheral variables. |
| FranKP2138 | 0:2b9b5764efb5 | 205 | \li for automatic generation of peripheral register debug information. |
| FranKP2138 | 0:2b9b5764efb5 | 206 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 207 | #ifdef __cplusplus |
| FranKP2138 | 0:2b9b5764efb5 | 208 | #define __I volatile /*!< Defines 'read only' permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 209 | #else |
| FranKP2138 | 0:2b9b5764efb5 | 210 | #define __I volatile const /*!< Defines 'read only' permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 211 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 212 | #define __O volatile /*!< Defines 'write only' permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 213 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 214 | |
| FranKP2138 | 0:2b9b5764efb5 | 215 | /* following defines should be used for structure members */ |
| FranKP2138 | 0:2b9b5764efb5 | 216 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 217 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 218 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
| FranKP2138 | 0:2b9b5764efb5 | 219 | |
| FranKP2138 | 0:2b9b5764efb5 | 220 | /*@} end of group Cortex_M0 */ |
| FranKP2138 | 0:2b9b5764efb5 | 221 | |
| FranKP2138 | 0:2b9b5764efb5 | 222 | |
| FranKP2138 | 0:2b9b5764efb5 | 223 | |
| FranKP2138 | 0:2b9b5764efb5 | 224 | /******************************************************************************* |
| FranKP2138 | 0:2b9b5764efb5 | 225 | * Register Abstraction |
| FranKP2138 | 0:2b9b5764efb5 | 226 | Core Register contain: |
| FranKP2138 | 0:2b9b5764efb5 | 227 | - Core Register |
| FranKP2138 | 0:2b9b5764efb5 | 228 | - Core NVIC Register |
| FranKP2138 | 0:2b9b5764efb5 | 229 | - Core SCB Register |
| FranKP2138 | 0:2b9b5764efb5 | 230 | - Core SysTick Register |
| FranKP2138 | 0:2b9b5764efb5 | 231 | ******************************************************************************/ |
| FranKP2138 | 0:2b9b5764efb5 | 232 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 233 | \defgroup CMSIS_core_register Defines and Type Definitions |
| FranKP2138 | 0:2b9b5764efb5 | 234 | \brief Type definitions and defines for Cortex-M processor based devices. |
| FranKP2138 | 0:2b9b5764efb5 | 235 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 236 | |
| FranKP2138 | 0:2b9b5764efb5 | 237 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 238 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 239 | \defgroup CMSIS_CORE Status and Control Registers |
| FranKP2138 | 0:2b9b5764efb5 | 240 | \brief Core Register type definitions. |
| FranKP2138 | 0:2b9b5764efb5 | 241 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 242 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 243 | |
| FranKP2138 | 0:2b9b5764efb5 | 244 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 245 | \brief Union type to access the Application Program Status Register (APSR). |
| FranKP2138 | 0:2b9b5764efb5 | 246 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 247 | typedef union |
| FranKP2138 | 0:2b9b5764efb5 | 248 | { |
| FranKP2138 | 0:2b9b5764efb5 | 249 | struct |
| FranKP2138 | 0:2b9b5764efb5 | 250 | { |
| FranKP2138 | 0:2b9b5764efb5 | 251 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 252 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 253 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 254 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 255 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 256 | } b; /*!< Structure used for bit access */ |
| FranKP2138 | 0:2b9b5764efb5 | 257 | uint32_t w; /*!< Type used for word access */ |
| FranKP2138 | 0:2b9b5764efb5 | 258 | } APSR_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 259 | |
| FranKP2138 | 0:2b9b5764efb5 | 260 | /* APSR Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 261 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 262 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 263 | |
| FranKP2138 | 0:2b9b5764efb5 | 264 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 265 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 266 | |
| FranKP2138 | 0:2b9b5764efb5 | 267 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 268 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 269 | |
| FranKP2138 | 0:2b9b5764efb5 | 270 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 271 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 272 | |
| FranKP2138 | 0:2b9b5764efb5 | 273 | |
| FranKP2138 | 0:2b9b5764efb5 | 274 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 275 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
| FranKP2138 | 0:2b9b5764efb5 | 276 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 277 | typedef union |
| FranKP2138 | 0:2b9b5764efb5 | 278 | { |
| FranKP2138 | 0:2b9b5764efb5 | 279 | struct |
| FranKP2138 | 0:2b9b5764efb5 | 280 | { |
| FranKP2138 | 0:2b9b5764efb5 | 281 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| FranKP2138 | 0:2b9b5764efb5 | 282 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 283 | } b; /*!< Structure used for bit access */ |
| FranKP2138 | 0:2b9b5764efb5 | 284 | uint32_t w; /*!< Type used for word access */ |
| FranKP2138 | 0:2b9b5764efb5 | 285 | } IPSR_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 286 | |
| FranKP2138 | 0:2b9b5764efb5 | 287 | /* IPSR Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 288 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 289 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 290 | |
| FranKP2138 | 0:2b9b5764efb5 | 291 | |
| FranKP2138 | 0:2b9b5764efb5 | 292 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 293 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
| FranKP2138 | 0:2b9b5764efb5 | 294 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 295 | typedef union |
| FranKP2138 | 0:2b9b5764efb5 | 296 | { |
| FranKP2138 | 0:2b9b5764efb5 | 297 | struct |
| FranKP2138 | 0:2b9b5764efb5 | 298 | { |
| FranKP2138 | 0:2b9b5764efb5 | 299 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
| FranKP2138 | 0:2b9b5764efb5 | 300 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 301 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
| FranKP2138 | 0:2b9b5764efb5 | 302 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 303 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 304 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 305 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 306 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
| FranKP2138 | 0:2b9b5764efb5 | 307 | } b; /*!< Structure used for bit access */ |
| FranKP2138 | 0:2b9b5764efb5 | 308 | uint32_t w; /*!< Type used for word access */ |
| FranKP2138 | 0:2b9b5764efb5 | 309 | } xPSR_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 310 | |
| FranKP2138 | 0:2b9b5764efb5 | 311 | /* xPSR Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 312 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 313 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 314 | |
| FranKP2138 | 0:2b9b5764efb5 | 315 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 316 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 317 | |
| FranKP2138 | 0:2b9b5764efb5 | 318 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 319 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 320 | |
| FranKP2138 | 0:2b9b5764efb5 | 321 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 322 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 323 | |
| FranKP2138 | 0:2b9b5764efb5 | 324 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 325 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 326 | |
| FranKP2138 | 0:2b9b5764efb5 | 327 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 328 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 329 | |
| FranKP2138 | 0:2b9b5764efb5 | 330 | |
| FranKP2138 | 0:2b9b5764efb5 | 331 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 332 | \brief Union type to access the Control Registers (CONTROL). |
| FranKP2138 | 0:2b9b5764efb5 | 333 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 334 | typedef union |
| FranKP2138 | 0:2b9b5764efb5 | 335 | { |
| FranKP2138 | 0:2b9b5764efb5 | 336 | struct |
| FranKP2138 | 0:2b9b5764efb5 | 337 | { |
| FranKP2138 | 0:2b9b5764efb5 | 338 | uint32_t _reserved0:1; /*!< bit: 0 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 339 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
| FranKP2138 | 0:2b9b5764efb5 | 340 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
| FranKP2138 | 0:2b9b5764efb5 | 341 | } b; /*!< Structure used for bit access */ |
| FranKP2138 | 0:2b9b5764efb5 | 342 | uint32_t w; /*!< Type used for word access */ |
| FranKP2138 | 0:2b9b5764efb5 | 343 | } CONTROL_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 344 | |
| FranKP2138 | 0:2b9b5764efb5 | 345 | /* CONTROL Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 346 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 347 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 348 | |
| FranKP2138 | 0:2b9b5764efb5 | 349 | /*@} end of group CMSIS_CORE */ |
| FranKP2138 | 0:2b9b5764efb5 | 350 | |
| FranKP2138 | 0:2b9b5764efb5 | 351 | |
| FranKP2138 | 0:2b9b5764efb5 | 352 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 353 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 354 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
| FranKP2138 | 0:2b9b5764efb5 | 355 | \brief Type definitions for the NVIC Registers |
| FranKP2138 | 0:2b9b5764efb5 | 356 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 357 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 358 | |
| FranKP2138 | 0:2b9b5764efb5 | 359 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 360 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
| FranKP2138 | 0:2b9b5764efb5 | 361 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 362 | typedef struct |
| FranKP2138 | 0:2b9b5764efb5 | 363 | { |
| FranKP2138 | 0:2b9b5764efb5 | 364 | __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 365 | uint32_t RESERVED0[31U]; |
| FranKP2138 | 0:2b9b5764efb5 | 366 | __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 367 | uint32_t RSERVED1[31U]; |
| FranKP2138 | 0:2b9b5764efb5 | 368 | __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 369 | uint32_t RESERVED2[31U]; |
| FranKP2138 | 0:2b9b5764efb5 | 370 | __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 371 | uint32_t RESERVED3[31U]; |
| FranKP2138 | 0:2b9b5764efb5 | 372 | uint32_t RESERVED4[64U]; |
| FranKP2138 | 0:2b9b5764efb5 | 373 | __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 374 | } NVIC_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 375 | |
| FranKP2138 | 0:2b9b5764efb5 | 376 | /*@} end of group CMSIS_NVIC */ |
| FranKP2138 | 0:2b9b5764efb5 | 377 | |
| FranKP2138 | 0:2b9b5764efb5 | 378 | |
| FranKP2138 | 0:2b9b5764efb5 | 379 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 380 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 381 | \defgroup CMSIS_SCB System Control Block (SCB) |
| FranKP2138 | 0:2b9b5764efb5 | 382 | \brief Type definitions for the System Control Block Registers |
| FranKP2138 | 0:2b9b5764efb5 | 383 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 384 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 385 | |
| FranKP2138 | 0:2b9b5764efb5 | 386 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 387 | \brief Structure type to access the System Control Block (SCB). |
| FranKP2138 | 0:2b9b5764efb5 | 388 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 389 | typedef struct |
| FranKP2138 | 0:2b9b5764efb5 | 390 | { |
| FranKP2138 | 0:2b9b5764efb5 | 391 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 392 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 393 | uint32_t RESERVED0; |
| FranKP2138 | 0:2b9b5764efb5 | 394 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 395 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 396 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 397 | uint32_t RESERVED1; |
| FranKP2138 | 0:2b9b5764efb5 | 398 | __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
| FranKP2138 | 0:2b9b5764efb5 | 399 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 400 | } SCB_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 401 | |
| FranKP2138 | 0:2b9b5764efb5 | 402 | /* SCB CPUID Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 403 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 404 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 405 | |
| FranKP2138 | 0:2b9b5764efb5 | 406 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 407 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 408 | |
| FranKP2138 | 0:2b9b5764efb5 | 409 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 410 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 411 | |
| FranKP2138 | 0:2b9b5764efb5 | 412 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 413 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 414 | |
| FranKP2138 | 0:2b9b5764efb5 | 415 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 416 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 417 | |
| FranKP2138 | 0:2b9b5764efb5 | 418 | /* SCB Interrupt Control State Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 419 | #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 420 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 421 | |
| FranKP2138 | 0:2b9b5764efb5 | 422 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 423 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 424 | |
| FranKP2138 | 0:2b9b5764efb5 | 425 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 426 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 427 | |
| FranKP2138 | 0:2b9b5764efb5 | 428 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 429 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 430 | |
| FranKP2138 | 0:2b9b5764efb5 | 431 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 432 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 433 | |
| FranKP2138 | 0:2b9b5764efb5 | 434 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 435 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 436 | |
| FranKP2138 | 0:2b9b5764efb5 | 437 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 438 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 439 | |
| FranKP2138 | 0:2b9b5764efb5 | 440 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 441 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 442 | |
| FranKP2138 | 0:2b9b5764efb5 | 443 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 444 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 445 | |
| FranKP2138 | 0:2b9b5764efb5 | 446 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 447 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 448 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 449 | |
| FranKP2138 | 0:2b9b5764efb5 | 450 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 451 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 452 | |
| FranKP2138 | 0:2b9b5764efb5 | 453 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 454 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 455 | |
| FranKP2138 | 0:2b9b5764efb5 | 456 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 457 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 458 | |
| FranKP2138 | 0:2b9b5764efb5 | 459 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 460 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 461 | |
| FranKP2138 | 0:2b9b5764efb5 | 462 | /* SCB System Control Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 463 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 464 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 465 | |
| FranKP2138 | 0:2b9b5764efb5 | 466 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 467 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 468 | |
| FranKP2138 | 0:2b9b5764efb5 | 469 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 470 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 471 | |
| FranKP2138 | 0:2b9b5764efb5 | 472 | /* SCB Configuration Control Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 473 | #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 474 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 475 | |
| FranKP2138 | 0:2b9b5764efb5 | 476 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 477 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 478 | |
| FranKP2138 | 0:2b9b5764efb5 | 479 | /* SCB System Handler Control and State Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 480 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 481 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 482 | |
| FranKP2138 | 0:2b9b5764efb5 | 483 | /*@} end of group CMSIS_SCB */ |
| FranKP2138 | 0:2b9b5764efb5 | 484 | |
| FranKP2138 | 0:2b9b5764efb5 | 485 | |
| FranKP2138 | 0:2b9b5764efb5 | 486 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 487 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 488 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
| FranKP2138 | 0:2b9b5764efb5 | 489 | \brief Type definitions for the System Timer Registers. |
| FranKP2138 | 0:2b9b5764efb5 | 490 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 491 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 492 | |
| FranKP2138 | 0:2b9b5764efb5 | 493 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 494 | \brief Structure type to access the System Timer (SysTick). |
| FranKP2138 | 0:2b9b5764efb5 | 495 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 496 | typedef struct |
| FranKP2138 | 0:2b9b5764efb5 | 497 | { |
| FranKP2138 | 0:2b9b5764efb5 | 498 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 499 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 500 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 501 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
| FranKP2138 | 0:2b9b5764efb5 | 502 | } SysTick_Type; |
| FranKP2138 | 0:2b9b5764efb5 | 503 | |
| FranKP2138 | 0:2b9b5764efb5 | 504 | /* SysTick Control / Status Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 505 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 506 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 507 | |
| FranKP2138 | 0:2b9b5764efb5 | 508 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 509 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 510 | |
| FranKP2138 | 0:2b9b5764efb5 | 511 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 512 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 513 | |
| FranKP2138 | 0:2b9b5764efb5 | 514 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 515 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 516 | |
| FranKP2138 | 0:2b9b5764efb5 | 517 | /* SysTick Reload Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 518 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 519 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 520 | |
| FranKP2138 | 0:2b9b5764efb5 | 521 | /* SysTick Current Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 522 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 523 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 524 | |
| FranKP2138 | 0:2b9b5764efb5 | 525 | /* SysTick Calibration Register Definitions */ |
| FranKP2138 | 0:2b9b5764efb5 | 526 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 527 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 528 | |
| FranKP2138 | 0:2b9b5764efb5 | 529 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 530 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 531 | |
| FranKP2138 | 0:2b9b5764efb5 | 532 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
| FranKP2138 | 0:2b9b5764efb5 | 533 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
| FranKP2138 | 0:2b9b5764efb5 | 534 | |
| FranKP2138 | 0:2b9b5764efb5 | 535 | /*@} end of group CMSIS_SysTick */ |
| FranKP2138 | 0:2b9b5764efb5 | 536 | |
| FranKP2138 | 0:2b9b5764efb5 | 537 | |
| FranKP2138 | 0:2b9b5764efb5 | 538 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 539 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 540 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
| FranKP2138 | 0:2b9b5764efb5 | 541 | \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. |
| FranKP2138 | 0:2b9b5764efb5 | 542 | Therefore they are not covered by the Cortex-M0 header file. |
| FranKP2138 | 0:2b9b5764efb5 | 543 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 544 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 545 | /*@} end of group CMSIS_CoreDebug */ |
| FranKP2138 | 0:2b9b5764efb5 | 546 | |
| FranKP2138 | 0:2b9b5764efb5 | 547 | |
| FranKP2138 | 0:2b9b5764efb5 | 548 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 549 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 550 | \defgroup CMSIS_core_bitfield Core register bit field macros |
| FranKP2138 | 0:2b9b5764efb5 | 551 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
| FranKP2138 | 0:2b9b5764efb5 | 552 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 553 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 554 | |
| FranKP2138 | 0:2b9b5764efb5 | 555 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 556 | \brief Mask and shift a bit field value for use in a register bit range. |
| FranKP2138 | 0:2b9b5764efb5 | 557 | \param[in] field Name of the register bit field. |
| FranKP2138 | 0:2b9b5764efb5 | 558 | \param[in] value Value of the bit field. |
| FranKP2138 | 0:2b9b5764efb5 | 559 | \return Masked and shifted value. |
| FranKP2138 | 0:2b9b5764efb5 | 560 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 561 | #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) |
| FranKP2138 | 0:2b9b5764efb5 | 562 | |
| FranKP2138 | 0:2b9b5764efb5 | 563 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 564 | \brief Mask and shift a register value to extract a bit filed value. |
| FranKP2138 | 0:2b9b5764efb5 | 565 | \param[in] field Name of the register bit field. |
| FranKP2138 | 0:2b9b5764efb5 | 566 | \param[in] value Value of register. |
| FranKP2138 | 0:2b9b5764efb5 | 567 | \return Masked and shifted bit field value. |
| FranKP2138 | 0:2b9b5764efb5 | 568 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 569 | #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) |
| FranKP2138 | 0:2b9b5764efb5 | 570 | |
| FranKP2138 | 0:2b9b5764efb5 | 571 | /*@} end of group CMSIS_core_bitfield */ |
| FranKP2138 | 0:2b9b5764efb5 | 572 | |
| FranKP2138 | 0:2b9b5764efb5 | 573 | |
| FranKP2138 | 0:2b9b5764efb5 | 574 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 575 | \ingroup CMSIS_core_register |
| FranKP2138 | 0:2b9b5764efb5 | 576 | \defgroup CMSIS_core_base Core Definitions |
| FranKP2138 | 0:2b9b5764efb5 | 577 | \brief Definitions for base addresses, unions, and structures. |
| FranKP2138 | 0:2b9b5764efb5 | 578 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 579 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 580 | |
| FranKP2138 | 0:2b9b5764efb5 | 581 | /* Memory mapping of Cortex-M0 Hardware */ |
| FranKP2138 | 0:2b9b5764efb5 | 582 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
| FranKP2138 | 0:2b9b5764efb5 | 583 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
| FranKP2138 | 0:2b9b5764efb5 | 584 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
| FranKP2138 | 0:2b9b5764efb5 | 585 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
| FranKP2138 | 0:2b9b5764efb5 | 586 | |
| FranKP2138 | 0:2b9b5764efb5 | 587 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
| FranKP2138 | 0:2b9b5764efb5 | 588 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
| FranKP2138 | 0:2b9b5764efb5 | 589 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
| FranKP2138 | 0:2b9b5764efb5 | 590 | |
| FranKP2138 | 0:2b9b5764efb5 | 591 | |
| FranKP2138 | 0:2b9b5764efb5 | 592 | /*@} */ |
| FranKP2138 | 0:2b9b5764efb5 | 593 | |
| FranKP2138 | 0:2b9b5764efb5 | 594 | |
| FranKP2138 | 0:2b9b5764efb5 | 595 | |
| FranKP2138 | 0:2b9b5764efb5 | 596 | /******************************************************************************* |
| FranKP2138 | 0:2b9b5764efb5 | 597 | * Hardware Abstraction Layer |
| FranKP2138 | 0:2b9b5764efb5 | 598 | Core Function Interface contains: |
| FranKP2138 | 0:2b9b5764efb5 | 599 | - Core NVIC Functions |
| FranKP2138 | 0:2b9b5764efb5 | 600 | - Core SysTick Functions |
| FranKP2138 | 0:2b9b5764efb5 | 601 | - Core Register Access Functions |
| FranKP2138 | 0:2b9b5764efb5 | 602 | ******************************************************************************/ |
| FranKP2138 | 0:2b9b5764efb5 | 603 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 604 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
| FranKP2138 | 0:2b9b5764efb5 | 605 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 606 | |
| FranKP2138 | 0:2b9b5764efb5 | 607 | |
| FranKP2138 | 0:2b9b5764efb5 | 608 | |
| FranKP2138 | 0:2b9b5764efb5 | 609 | /* ########################## NVIC functions #################################### */ |
| FranKP2138 | 0:2b9b5764efb5 | 610 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 611 | \ingroup CMSIS_Core_FunctionInterface |
| FranKP2138 | 0:2b9b5764efb5 | 612 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
| FranKP2138 | 0:2b9b5764efb5 | 613 | \brief Functions that manage interrupts and exceptions via the NVIC. |
| FranKP2138 | 0:2b9b5764efb5 | 614 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 615 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 616 | |
| FranKP2138 | 0:2b9b5764efb5 | 617 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
| FranKP2138 | 0:2b9b5764efb5 | 618 | /* The following MACROS handle generation of the register offset and byte masks */ |
| FranKP2138 | 0:2b9b5764efb5 | 619 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
| FranKP2138 | 0:2b9b5764efb5 | 620 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
| FranKP2138 | 0:2b9b5764efb5 | 621 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
| FranKP2138 | 0:2b9b5764efb5 | 622 | |
| FranKP2138 | 0:2b9b5764efb5 | 623 | |
| FranKP2138 | 0:2b9b5764efb5 | 624 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 625 | \brief Enable External Interrupt |
| FranKP2138 | 0:2b9b5764efb5 | 626 | \details Enables a device-specific interrupt in the NVIC interrupt controller. |
| FranKP2138 | 0:2b9b5764efb5 | 627 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| FranKP2138 | 0:2b9b5764efb5 | 628 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 629 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 630 | { |
| FranKP2138 | 0:2b9b5764efb5 | 631 | NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| FranKP2138 | 0:2b9b5764efb5 | 632 | } |
| FranKP2138 | 0:2b9b5764efb5 | 633 | |
| FranKP2138 | 0:2b9b5764efb5 | 634 | |
| FranKP2138 | 0:2b9b5764efb5 | 635 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 636 | \brief Disable External Interrupt |
| FranKP2138 | 0:2b9b5764efb5 | 637 | \details Disables a device-specific interrupt in the NVIC interrupt controller. |
| FranKP2138 | 0:2b9b5764efb5 | 638 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| FranKP2138 | 0:2b9b5764efb5 | 639 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 640 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 641 | { |
| FranKP2138 | 0:2b9b5764efb5 | 642 | NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| FranKP2138 | 0:2b9b5764efb5 | 643 | } |
| FranKP2138 | 0:2b9b5764efb5 | 644 | |
| FranKP2138 | 0:2b9b5764efb5 | 645 | |
| FranKP2138 | 0:2b9b5764efb5 | 646 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 647 | \brief Get Pending Interrupt |
| FranKP2138 | 0:2b9b5764efb5 | 648 | \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 649 | \param [in] IRQn Interrupt number. |
| FranKP2138 | 0:2b9b5764efb5 | 650 | \return 0 Interrupt status is not pending. |
| FranKP2138 | 0:2b9b5764efb5 | 651 | \return 1 Interrupt status is pending. |
| FranKP2138 | 0:2b9b5764efb5 | 652 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 653 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 654 | { |
| FranKP2138 | 0:2b9b5764efb5 | 655 | return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
| FranKP2138 | 0:2b9b5764efb5 | 656 | } |
| FranKP2138 | 0:2b9b5764efb5 | 657 | |
| FranKP2138 | 0:2b9b5764efb5 | 658 | |
| FranKP2138 | 0:2b9b5764efb5 | 659 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 660 | \brief Set Pending Interrupt |
| FranKP2138 | 0:2b9b5764efb5 | 661 | \details Sets the pending bit of an external interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 662 | \param [in] IRQn Interrupt number. Value cannot be negative. |
| FranKP2138 | 0:2b9b5764efb5 | 663 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 664 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 665 | { |
| FranKP2138 | 0:2b9b5764efb5 | 666 | NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| FranKP2138 | 0:2b9b5764efb5 | 667 | } |
| FranKP2138 | 0:2b9b5764efb5 | 668 | |
| FranKP2138 | 0:2b9b5764efb5 | 669 | |
| FranKP2138 | 0:2b9b5764efb5 | 670 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 671 | \brief Clear Pending Interrupt |
| FranKP2138 | 0:2b9b5764efb5 | 672 | \details Clears the pending bit of an external interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 673 | \param [in] IRQn External interrupt number. Value cannot be negative. |
| FranKP2138 | 0:2b9b5764efb5 | 674 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 675 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 676 | { |
| FranKP2138 | 0:2b9b5764efb5 | 677 | NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
| FranKP2138 | 0:2b9b5764efb5 | 678 | } |
| FranKP2138 | 0:2b9b5764efb5 | 679 | |
| FranKP2138 | 0:2b9b5764efb5 | 680 | |
| FranKP2138 | 0:2b9b5764efb5 | 681 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 682 | \brief Set Interrupt Priority |
| FranKP2138 | 0:2b9b5764efb5 | 683 | \details Sets the priority of an interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 684 | \note The priority cannot be set for every core interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 685 | \param [in] IRQn Interrupt number. |
| FranKP2138 | 0:2b9b5764efb5 | 686 | \param [in] priority Priority to set. |
| FranKP2138 | 0:2b9b5764efb5 | 687 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 688 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
| FranKP2138 | 0:2b9b5764efb5 | 689 | { |
| FranKP2138 | 0:2b9b5764efb5 | 690 | if ((int32_t)(IRQn) < 0) |
| FranKP2138 | 0:2b9b5764efb5 | 691 | { |
| FranKP2138 | 0:2b9b5764efb5 | 692 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| FranKP2138 | 0:2b9b5764efb5 | 693 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| FranKP2138 | 0:2b9b5764efb5 | 694 | } |
| FranKP2138 | 0:2b9b5764efb5 | 695 | else |
| FranKP2138 | 0:2b9b5764efb5 | 696 | { |
| FranKP2138 | 0:2b9b5764efb5 | 697 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
| FranKP2138 | 0:2b9b5764efb5 | 698 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
| FranKP2138 | 0:2b9b5764efb5 | 699 | } |
| FranKP2138 | 0:2b9b5764efb5 | 700 | } |
| FranKP2138 | 0:2b9b5764efb5 | 701 | |
| FranKP2138 | 0:2b9b5764efb5 | 702 | |
| FranKP2138 | 0:2b9b5764efb5 | 703 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 704 | \brief Get Interrupt Priority |
| FranKP2138 | 0:2b9b5764efb5 | 705 | \details Reads the priority of an interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 706 | The interrupt number can be positive to specify an external (device specific) interrupt, |
| FranKP2138 | 0:2b9b5764efb5 | 707 | or negative to specify an internal (core) interrupt. |
| FranKP2138 | 0:2b9b5764efb5 | 708 | \param [in] IRQn Interrupt number. |
| FranKP2138 | 0:2b9b5764efb5 | 709 | \return Interrupt Priority. |
| FranKP2138 | 0:2b9b5764efb5 | 710 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
| FranKP2138 | 0:2b9b5764efb5 | 711 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 712 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
| FranKP2138 | 0:2b9b5764efb5 | 713 | { |
| FranKP2138 | 0:2b9b5764efb5 | 714 | |
| FranKP2138 | 0:2b9b5764efb5 | 715 | if ((int32_t)(IRQn) < 0) |
| FranKP2138 | 0:2b9b5764efb5 | 716 | { |
| FranKP2138 | 0:2b9b5764efb5 | 717 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| FranKP2138 | 0:2b9b5764efb5 | 718 | } |
| FranKP2138 | 0:2b9b5764efb5 | 719 | else |
| FranKP2138 | 0:2b9b5764efb5 | 720 | { |
| FranKP2138 | 0:2b9b5764efb5 | 721 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
| FranKP2138 | 0:2b9b5764efb5 | 722 | } |
| FranKP2138 | 0:2b9b5764efb5 | 723 | } |
| FranKP2138 | 0:2b9b5764efb5 | 724 | |
| FranKP2138 | 0:2b9b5764efb5 | 725 | |
| FranKP2138 | 0:2b9b5764efb5 | 726 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 727 | \brief System Reset |
| FranKP2138 | 0:2b9b5764efb5 | 728 | \details Initiates a system reset request to reset the MCU. |
| FranKP2138 | 0:2b9b5764efb5 | 729 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 730 | __STATIC_INLINE void NVIC_SystemReset(void) |
| FranKP2138 | 0:2b9b5764efb5 | 731 | { |
| FranKP2138 | 0:2b9b5764efb5 | 732 | __DSB(); /* Ensure all outstanding memory accesses included |
| FranKP2138 | 0:2b9b5764efb5 | 733 | buffered write are completed before reset */ |
| FranKP2138 | 0:2b9b5764efb5 | 734 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
| FranKP2138 | 0:2b9b5764efb5 | 735 | SCB_AIRCR_SYSRESETREQ_Msk); |
| FranKP2138 | 0:2b9b5764efb5 | 736 | __DSB(); /* Ensure completion of memory access */ |
| FranKP2138 | 0:2b9b5764efb5 | 737 | |
| FranKP2138 | 0:2b9b5764efb5 | 738 | for(;;) /* wait until reset */ |
| FranKP2138 | 0:2b9b5764efb5 | 739 | { |
| FranKP2138 | 0:2b9b5764efb5 | 740 | __NOP(); |
| FranKP2138 | 0:2b9b5764efb5 | 741 | } |
| FranKP2138 | 0:2b9b5764efb5 | 742 | } |
| FranKP2138 | 0:2b9b5764efb5 | 743 | |
| FranKP2138 | 0:2b9b5764efb5 | 744 | /*@} end of CMSIS_Core_NVICFunctions */ |
| FranKP2138 | 0:2b9b5764efb5 | 745 | |
| FranKP2138 | 0:2b9b5764efb5 | 746 | |
| FranKP2138 | 0:2b9b5764efb5 | 747 | |
| FranKP2138 | 0:2b9b5764efb5 | 748 | /* ################################## SysTick function ############################################ */ |
| FranKP2138 | 0:2b9b5764efb5 | 749 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 750 | \ingroup CMSIS_Core_FunctionInterface |
| FranKP2138 | 0:2b9b5764efb5 | 751 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
| FranKP2138 | 0:2b9b5764efb5 | 752 | \brief Functions that configure the System. |
| FranKP2138 | 0:2b9b5764efb5 | 753 | @{ |
| FranKP2138 | 0:2b9b5764efb5 | 754 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 755 | |
| FranKP2138 | 0:2b9b5764efb5 | 756 | #if (__Vendor_SysTickConfig == 0U) |
| FranKP2138 | 0:2b9b5764efb5 | 757 | |
| FranKP2138 | 0:2b9b5764efb5 | 758 | /** |
| FranKP2138 | 0:2b9b5764efb5 | 759 | \brief System Tick Configuration |
| FranKP2138 | 0:2b9b5764efb5 | 760 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
| FranKP2138 | 0:2b9b5764efb5 | 761 | Counter is in free running mode to generate periodic interrupts. |
| FranKP2138 | 0:2b9b5764efb5 | 762 | \param [in] ticks Number of ticks between two interrupts. |
| FranKP2138 | 0:2b9b5764efb5 | 763 | \return 0 Function succeeded. |
| FranKP2138 | 0:2b9b5764efb5 | 764 | \return 1 Function failed. |
| FranKP2138 | 0:2b9b5764efb5 | 765 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
| FranKP2138 | 0:2b9b5764efb5 | 766 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
| FranKP2138 | 0:2b9b5764efb5 | 767 | must contain a vendor-specific implementation of this function. |
| FranKP2138 | 0:2b9b5764efb5 | 768 | */ |
| FranKP2138 | 0:2b9b5764efb5 | 769 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
| FranKP2138 | 0:2b9b5764efb5 | 770 | { |
| FranKP2138 | 0:2b9b5764efb5 | 771 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
| FranKP2138 | 0:2b9b5764efb5 | 772 | { |
| FranKP2138 | 0:2b9b5764efb5 | 773 | return (1UL); /* Reload value impossible */ |
| FranKP2138 | 0:2b9b5764efb5 | 774 | } |
| FranKP2138 | 0:2b9b5764efb5 | 775 | |
| FranKP2138 | 0:2b9b5764efb5 | 776 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
| FranKP2138 | 0:2b9b5764efb5 | 777 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
| FranKP2138 | 0:2b9b5764efb5 | 778 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
| FranKP2138 | 0:2b9b5764efb5 | 779 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
| FranKP2138 | 0:2b9b5764efb5 | 780 | SysTick_CTRL_TICKINT_Msk | |
| FranKP2138 | 0:2b9b5764efb5 | 781 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
| FranKP2138 | 0:2b9b5764efb5 | 782 | return (0UL); /* Function successful */ |
| FranKP2138 | 0:2b9b5764efb5 | 783 | } |
| FranKP2138 | 0:2b9b5764efb5 | 784 | |
| FranKP2138 | 0:2b9b5764efb5 | 785 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 786 | |
| FranKP2138 | 0:2b9b5764efb5 | 787 | /*@} end of CMSIS_Core_SysTickFunctions */ |
| FranKP2138 | 0:2b9b5764efb5 | 788 | |
| FranKP2138 | 0:2b9b5764efb5 | 789 | |
| FranKP2138 | 0:2b9b5764efb5 | 790 | |
| FranKP2138 | 0:2b9b5764efb5 | 791 | |
| FranKP2138 | 0:2b9b5764efb5 | 792 | #ifdef __cplusplus |
| FranKP2138 | 0:2b9b5764efb5 | 793 | } |
| FranKP2138 | 0:2b9b5764efb5 | 794 | #endif |
| FranKP2138 | 0:2b9b5764efb5 | 795 | |
| FranKP2138 | 0:2b9b5764efb5 | 796 | #endif /* __CORE_CM0_H_DEPENDANT */ |
| FranKP2138 | 0:2b9b5764efb5 | 797 | |
| FranKP2138 | 0:2b9b5764efb5 | 798 | #endif /* __CMSIS_GENERIC */ |
| FranKP2138 | 0:2b9b5764efb5 | 799 |