BLE_Nano nRF51 Central heart rate

Committer:
FranKP2138
Date:
Thu May 26 10:12:27 2016 +0000
Revision:
0:2b9b5764efb5
RedBearLab BLE_Nano Central role for heart rate

Who changed what in which revision?

UserRevisionLine numberNew contents of line
FranKP2138 0:2b9b5764efb5 1 /**************************************************************************//**
FranKP2138 0:2b9b5764efb5 2 * @file cmsis_armcc.h
FranKP2138 0:2b9b5764efb5 3 * @brief CMSIS Cortex-M Core Function/Instruction Header File
FranKP2138 0:2b9b5764efb5 4 * @version V4.30
FranKP2138 0:2b9b5764efb5 5 * @date 20. October 2015
FranKP2138 0:2b9b5764efb5 6 ******************************************************************************/
FranKP2138 0:2b9b5764efb5 7 /* Copyright (c) 2009 - 2015 ARM LIMITED
FranKP2138 0:2b9b5764efb5 8
FranKP2138 0:2b9b5764efb5 9 All rights reserved.
FranKP2138 0:2b9b5764efb5 10 Redistribution and use in source and binary forms, with or without
FranKP2138 0:2b9b5764efb5 11 modification, are permitted provided that the following conditions are met:
FranKP2138 0:2b9b5764efb5 12 - Redistributions of source code must retain the above copyright
FranKP2138 0:2b9b5764efb5 13 notice, this list of conditions and the following disclaimer.
FranKP2138 0:2b9b5764efb5 14 - Redistributions in binary form must reproduce the above copyright
FranKP2138 0:2b9b5764efb5 15 notice, this list of conditions and the following disclaimer in the
FranKP2138 0:2b9b5764efb5 16 documentation and/or other materials provided with the distribution.
FranKP2138 0:2b9b5764efb5 17 - Neither the name of ARM nor the names of its contributors may be used
FranKP2138 0:2b9b5764efb5 18 to endorse or promote products derived from this software without
FranKP2138 0:2b9b5764efb5 19 specific prior written permission.
FranKP2138 0:2b9b5764efb5 20 *
FranKP2138 0:2b9b5764efb5 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
FranKP2138 0:2b9b5764efb5 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
FranKP2138 0:2b9b5764efb5 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
FranKP2138 0:2b9b5764efb5 24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
FranKP2138 0:2b9b5764efb5 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
FranKP2138 0:2b9b5764efb5 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
FranKP2138 0:2b9b5764efb5 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
FranKP2138 0:2b9b5764efb5 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
FranKP2138 0:2b9b5764efb5 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
FranKP2138 0:2b9b5764efb5 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
FranKP2138 0:2b9b5764efb5 31 POSSIBILITY OF SUCH DAMAGE.
FranKP2138 0:2b9b5764efb5 32 ---------------------------------------------------------------------------*/
FranKP2138 0:2b9b5764efb5 33
FranKP2138 0:2b9b5764efb5 34
FranKP2138 0:2b9b5764efb5 35 #ifndef __CMSIS_ARMCC_H
FranKP2138 0:2b9b5764efb5 36 #define __CMSIS_ARMCC_H
FranKP2138 0:2b9b5764efb5 37
FranKP2138 0:2b9b5764efb5 38
FranKP2138 0:2b9b5764efb5 39 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
FranKP2138 0:2b9b5764efb5 40 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
FranKP2138 0:2b9b5764efb5 41 #endif
FranKP2138 0:2b9b5764efb5 42
FranKP2138 0:2b9b5764efb5 43 /* ########################### Core Function Access ########################### */
FranKP2138 0:2b9b5764efb5 44 /** \ingroup CMSIS_Core_FunctionInterface
FranKP2138 0:2b9b5764efb5 45 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
FranKP2138 0:2b9b5764efb5 46 @{
FranKP2138 0:2b9b5764efb5 47 */
FranKP2138 0:2b9b5764efb5 48
FranKP2138 0:2b9b5764efb5 49 /* intrinsic void __enable_irq(); */
FranKP2138 0:2b9b5764efb5 50 /* intrinsic void __disable_irq(); */
FranKP2138 0:2b9b5764efb5 51
FranKP2138 0:2b9b5764efb5 52 /**
FranKP2138 0:2b9b5764efb5 53 \brief Get Control Register
FranKP2138 0:2b9b5764efb5 54 \details Returns the content of the Control Register.
FranKP2138 0:2b9b5764efb5 55 \return Control Register value
FranKP2138 0:2b9b5764efb5 56 */
FranKP2138 0:2b9b5764efb5 57 __STATIC_INLINE uint32_t __get_CONTROL(void)
FranKP2138 0:2b9b5764efb5 58 {
FranKP2138 0:2b9b5764efb5 59 register uint32_t __regControl __ASM("control");
FranKP2138 0:2b9b5764efb5 60 return(__regControl);
FranKP2138 0:2b9b5764efb5 61 }
FranKP2138 0:2b9b5764efb5 62
FranKP2138 0:2b9b5764efb5 63
FranKP2138 0:2b9b5764efb5 64 /**
FranKP2138 0:2b9b5764efb5 65 \brief Set Control Register
FranKP2138 0:2b9b5764efb5 66 \details Writes the given value to the Control Register.
FranKP2138 0:2b9b5764efb5 67 \param [in] control Control Register value to set
FranKP2138 0:2b9b5764efb5 68 */
FranKP2138 0:2b9b5764efb5 69 __STATIC_INLINE void __set_CONTROL(uint32_t control)
FranKP2138 0:2b9b5764efb5 70 {
FranKP2138 0:2b9b5764efb5 71 register uint32_t __regControl __ASM("control");
FranKP2138 0:2b9b5764efb5 72 __regControl = control;
FranKP2138 0:2b9b5764efb5 73 }
FranKP2138 0:2b9b5764efb5 74
FranKP2138 0:2b9b5764efb5 75
FranKP2138 0:2b9b5764efb5 76 /**
FranKP2138 0:2b9b5764efb5 77 \brief Get IPSR Register
FranKP2138 0:2b9b5764efb5 78 \details Returns the content of the IPSR Register.
FranKP2138 0:2b9b5764efb5 79 \return IPSR Register value
FranKP2138 0:2b9b5764efb5 80 */
FranKP2138 0:2b9b5764efb5 81 __STATIC_INLINE uint32_t __get_IPSR(void)
FranKP2138 0:2b9b5764efb5 82 {
FranKP2138 0:2b9b5764efb5 83 register uint32_t __regIPSR __ASM("ipsr");
FranKP2138 0:2b9b5764efb5 84 return(__regIPSR);
FranKP2138 0:2b9b5764efb5 85 }
FranKP2138 0:2b9b5764efb5 86
FranKP2138 0:2b9b5764efb5 87
FranKP2138 0:2b9b5764efb5 88 /**
FranKP2138 0:2b9b5764efb5 89 \brief Get APSR Register
FranKP2138 0:2b9b5764efb5 90 \details Returns the content of the APSR Register.
FranKP2138 0:2b9b5764efb5 91 \return APSR Register value
FranKP2138 0:2b9b5764efb5 92 */
FranKP2138 0:2b9b5764efb5 93 __STATIC_INLINE uint32_t __get_APSR(void)
FranKP2138 0:2b9b5764efb5 94 {
FranKP2138 0:2b9b5764efb5 95 register uint32_t __regAPSR __ASM("apsr");
FranKP2138 0:2b9b5764efb5 96 return(__regAPSR);
FranKP2138 0:2b9b5764efb5 97 }
FranKP2138 0:2b9b5764efb5 98
FranKP2138 0:2b9b5764efb5 99
FranKP2138 0:2b9b5764efb5 100 /**
FranKP2138 0:2b9b5764efb5 101 \brief Get xPSR Register
FranKP2138 0:2b9b5764efb5 102 \details Returns the content of the xPSR Register.
FranKP2138 0:2b9b5764efb5 103 \return xPSR Register value
FranKP2138 0:2b9b5764efb5 104 */
FranKP2138 0:2b9b5764efb5 105 __STATIC_INLINE uint32_t __get_xPSR(void)
FranKP2138 0:2b9b5764efb5 106 {
FranKP2138 0:2b9b5764efb5 107 register uint32_t __regXPSR __ASM("xpsr");
FranKP2138 0:2b9b5764efb5 108 return(__regXPSR);
FranKP2138 0:2b9b5764efb5 109 }
FranKP2138 0:2b9b5764efb5 110
FranKP2138 0:2b9b5764efb5 111
FranKP2138 0:2b9b5764efb5 112 /**
FranKP2138 0:2b9b5764efb5 113 \brief Get Process Stack Pointer
FranKP2138 0:2b9b5764efb5 114 \details Returns the current value of the Process Stack Pointer (PSP).
FranKP2138 0:2b9b5764efb5 115 \return PSP Register value
FranKP2138 0:2b9b5764efb5 116 */
FranKP2138 0:2b9b5764efb5 117 __STATIC_INLINE uint32_t __get_PSP(void)
FranKP2138 0:2b9b5764efb5 118 {
FranKP2138 0:2b9b5764efb5 119 register uint32_t __regProcessStackPointer __ASM("psp");
FranKP2138 0:2b9b5764efb5 120 return(__regProcessStackPointer);
FranKP2138 0:2b9b5764efb5 121 }
FranKP2138 0:2b9b5764efb5 122
FranKP2138 0:2b9b5764efb5 123
FranKP2138 0:2b9b5764efb5 124 /**
FranKP2138 0:2b9b5764efb5 125 \brief Set Process Stack Pointer
FranKP2138 0:2b9b5764efb5 126 \details Assigns the given value to the Process Stack Pointer (PSP).
FranKP2138 0:2b9b5764efb5 127 \param [in] topOfProcStack Process Stack Pointer value to set
FranKP2138 0:2b9b5764efb5 128 */
FranKP2138 0:2b9b5764efb5 129 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
FranKP2138 0:2b9b5764efb5 130 {
FranKP2138 0:2b9b5764efb5 131 register uint32_t __regProcessStackPointer __ASM("psp");
FranKP2138 0:2b9b5764efb5 132 __regProcessStackPointer = topOfProcStack;
FranKP2138 0:2b9b5764efb5 133 }
FranKP2138 0:2b9b5764efb5 134
FranKP2138 0:2b9b5764efb5 135
FranKP2138 0:2b9b5764efb5 136 /**
FranKP2138 0:2b9b5764efb5 137 \brief Get Main Stack Pointer
FranKP2138 0:2b9b5764efb5 138 \details Returns the current value of the Main Stack Pointer (MSP).
FranKP2138 0:2b9b5764efb5 139 \return MSP Register value
FranKP2138 0:2b9b5764efb5 140 */
FranKP2138 0:2b9b5764efb5 141 __STATIC_INLINE uint32_t __get_MSP(void)
FranKP2138 0:2b9b5764efb5 142 {
FranKP2138 0:2b9b5764efb5 143 register uint32_t __regMainStackPointer __ASM("msp");
FranKP2138 0:2b9b5764efb5 144 return(__regMainStackPointer);
FranKP2138 0:2b9b5764efb5 145 }
FranKP2138 0:2b9b5764efb5 146
FranKP2138 0:2b9b5764efb5 147
FranKP2138 0:2b9b5764efb5 148 /**
FranKP2138 0:2b9b5764efb5 149 \brief Set Main Stack Pointer
FranKP2138 0:2b9b5764efb5 150 \details Assigns the given value to the Main Stack Pointer (MSP).
FranKP2138 0:2b9b5764efb5 151 \param [in] topOfMainStack Main Stack Pointer value to set
FranKP2138 0:2b9b5764efb5 152 */
FranKP2138 0:2b9b5764efb5 153 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
FranKP2138 0:2b9b5764efb5 154 {
FranKP2138 0:2b9b5764efb5 155 register uint32_t __regMainStackPointer __ASM("msp");
FranKP2138 0:2b9b5764efb5 156 __regMainStackPointer = topOfMainStack;
FranKP2138 0:2b9b5764efb5 157 }
FranKP2138 0:2b9b5764efb5 158
FranKP2138 0:2b9b5764efb5 159
FranKP2138 0:2b9b5764efb5 160 /**
FranKP2138 0:2b9b5764efb5 161 \brief Get Priority Mask
FranKP2138 0:2b9b5764efb5 162 \details Returns the current state of the priority mask bit from the Priority Mask Register.
FranKP2138 0:2b9b5764efb5 163 \return Priority Mask value
FranKP2138 0:2b9b5764efb5 164 */
FranKP2138 0:2b9b5764efb5 165 __STATIC_INLINE uint32_t __get_PRIMASK(void)
FranKP2138 0:2b9b5764efb5 166 {
FranKP2138 0:2b9b5764efb5 167 register uint32_t __regPriMask __ASM("primask");
FranKP2138 0:2b9b5764efb5 168 return(__regPriMask);
FranKP2138 0:2b9b5764efb5 169 }
FranKP2138 0:2b9b5764efb5 170
FranKP2138 0:2b9b5764efb5 171
FranKP2138 0:2b9b5764efb5 172 /**
FranKP2138 0:2b9b5764efb5 173 \brief Set Priority Mask
FranKP2138 0:2b9b5764efb5 174 \details Assigns the given value to the Priority Mask Register.
FranKP2138 0:2b9b5764efb5 175 \param [in] priMask Priority Mask
FranKP2138 0:2b9b5764efb5 176 */
FranKP2138 0:2b9b5764efb5 177 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
FranKP2138 0:2b9b5764efb5 178 {
FranKP2138 0:2b9b5764efb5 179 register uint32_t __regPriMask __ASM("primask");
FranKP2138 0:2b9b5764efb5 180 __regPriMask = (priMask);
FranKP2138 0:2b9b5764efb5 181 }
FranKP2138 0:2b9b5764efb5 182
FranKP2138 0:2b9b5764efb5 183
FranKP2138 0:2b9b5764efb5 184 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
FranKP2138 0:2b9b5764efb5 185
FranKP2138 0:2b9b5764efb5 186 /**
FranKP2138 0:2b9b5764efb5 187 \brief Enable FIQ
FranKP2138 0:2b9b5764efb5 188 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
FranKP2138 0:2b9b5764efb5 189 Can only be executed in Privileged modes.
FranKP2138 0:2b9b5764efb5 190 */
FranKP2138 0:2b9b5764efb5 191 #define __enable_fault_irq __enable_fiq
FranKP2138 0:2b9b5764efb5 192
FranKP2138 0:2b9b5764efb5 193
FranKP2138 0:2b9b5764efb5 194 /**
FranKP2138 0:2b9b5764efb5 195 \brief Disable FIQ
FranKP2138 0:2b9b5764efb5 196 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
FranKP2138 0:2b9b5764efb5 197 Can only be executed in Privileged modes.
FranKP2138 0:2b9b5764efb5 198 */
FranKP2138 0:2b9b5764efb5 199 #define __disable_fault_irq __disable_fiq
FranKP2138 0:2b9b5764efb5 200
FranKP2138 0:2b9b5764efb5 201
FranKP2138 0:2b9b5764efb5 202 /**
FranKP2138 0:2b9b5764efb5 203 \brief Get Base Priority
FranKP2138 0:2b9b5764efb5 204 \details Returns the current value of the Base Priority register.
FranKP2138 0:2b9b5764efb5 205 \return Base Priority register value
FranKP2138 0:2b9b5764efb5 206 */
FranKP2138 0:2b9b5764efb5 207 __STATIC_INLINE uint32_t __get_BASEPRI(void)
FranKP2138 0:2b9b5764efb5 208 {
FranKP2138 0:2b9b5764efb5 209 register uint32_t __regBasePri __ASM("basepri");
FranKP2138 0:2b9b5764efb5 210 return(__regBasePri);
FranKP2138 0:2b9b5764efb5 211 }
FranKP2138 0:2b9b5764efb5 212
FranKP2138 0:2b9b5764efb5 213
FranKP2138 0:2b9b5764efb5 214 /**
FranKP2138 0:2b9b5764efb5 215 \brief Set Base Priority
FranKP2138 0:2b9b5764efb5 216 \details Assigns the given value to the Base Priority register.
FranKP2138 0:2b9b5764efb5 217 \param [in] basePri Base Priority value to set
FranKP2138 0:2b9b5764efb5 218 */
FranKP2138 0:2b9b5764efb5 219 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
FranKP2138 0:2b9b5764efb5 220 {
FranKP2138 0:2b9b5764efb5 221 register uint32_t __regBasePri __ASM("basepri");
FranKP2138 0:2b9b5764efb5 222 __regBasePri = (basePri & 0xFFU);
FranKP2138 0:2b9b5764efb5 223 }
FranKP2138 0:2b9b5764efb5 224
FranKP2138 0:2b9b5764efb5 225
FranKP2138 0:2b9b5764efb5 226 /**
FranKP2138 0:2b9b5764efb5 227 \brief Set Base Priority with condition
FranKP2138 0:2b9b5764efb5 228 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
FranKP2138 0:2b9b5764efb5 229 or the new value increases the BASEPRI priority level.
FranKP2138 0:2b9b5764efb5 230 \param [in] basePri Base Priority value to set
FranKP2138 0:2b9b5764efb5 231 */
FranKP2138 0:2b9b5764efb5 232 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
FranKP2138 0:2b9b5764efb5 233 {
FranKP2138 0:2b9b5764efb5 234 register uint32_t __regBasePriMax __ASM("basepri_max");
FranKP2138 0:2b9b5764efb5 235 __regBasePriMax = (basePri & 0xFFU);
FranKP2138 0:2b9b5764efb5 236 }
FranKP2138 0:2b9b5764efb5 237
FranKP2138 0:2b9b5764efb5 238
FranKP2138 0:2b9b5764efb5 239 /**
FranKP2138 0:2b9b5764efb5 240 \brief Get Fault Mask
FranKP2138 0:2b9b5764efb5 241 \details Returns the current value of the Fault Mask register.
FranKP2138 0:2b9b5764efb5 242 \return Fault Mask register value
FranKP2138 0:2b9b5764efb5 243 */
FranKP2138 0:2b9b5764efb5 244 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
FranKP2138 0:2b9b5764efb5 245 {
FranKP2138 0:2b9b5764efb5 246 register uint32_t __regFaultMask __ASM("faultmask");
FranKP2138 0:2b9b5764efb5 247 return(__regFaultMask);
FranKP2138 0:2b9b5764efb5 248 }
FranKP2138 0:2b9b5764efb5 249
FranKP2138 0:2b9b5764efb5 250
FranKP2138 0:2b9b5764efb5 251 /**
FranKP2138 0:2b9b5764efb5 252 \brief Set Fault Mask
FranKP2138 0:2b9b5764efb5 253 \details Assigns the given value to the Fault Mask register.
FranKP2138 0:2b9b5764efb5 254 \param [in] faultMask Fault Mask value to set
FranKP2138 0:2b9b5764efb5 255 */
FranKP2138 0:2b9b5764efb5 256 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
FranKP2138 0:2b9b5764efb5 257 {
FranKP2138 0:2b9b5764efb5 258 register uint32_t __regFaultMask __ASM("faultmask");
FranKP2138 0:2b9b5764efb5 259 __regFaultMask = (faultMask & (uint32_t)1);
FranKP2138 0:2b9b5764efb5 260 }
FranKP2138 0:2b9b5764efb5 261
FranKP2138 0:2b9b5764efb5 262 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
FranKP2138 0:2b9b5764efb5 263
FranKP2138 0:2b9b5764efb5 264
FranKP2138 0:2b9b5764efb5 265 #if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
FranKP2138 0:2b9b5764efb5 266
FranKP2138 0:2b9b5764efb5 267 /**
FranKP2138 0:2b9b5764efb5 268 \brief Get FPSCR
FranKP2138 0:2b9b5764efb5 269 \details Returns the current value of the Floating Point Status/Control register.
FranKP2138 0:2b9b5764efb5 270 \return Floating Point Status/Control register value
FranKP2138 0:2b9b5764efb5 271 */
FranKP2138 0:2b9b5764efb5 272 __STATIC_INLINE uint32_t __get_FPSCR(void)
FranKP2138 0:2b9b5764efb5 273 {
FranKP2138 0:2b9b5764efb5 274 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
FranKP2138 0:2b9b5764efb5 275 register uint32_t __regfpscr __ASM("fpscr");
FranKP2138 0:2b9b5764efb5 276 return(__regfpscr);
FranKP2138 0:2b9b5764efb5 277 #else
FranKP2138 0:2b9b5764efb5 278 return(0U);
FranKP2138 0:2b9b5764efb5 279 #endif
FranKP2138 0:2b9b5764efb5 280 }
FranKP2138 0:2b9b5764efb5 281
FranKP2138 0:2b9b5764efb5 282
FranKP2138 0:2b9b5764efb5 283 /**
FranKP2138 0:2b9b5764efb5 284 \brief Set FPSCR
FranKP2138 0:2b9b5764efb5 285 \details Assigns the given value to the Floating Point Status/Control register.
FranKP2138 0:2b9b5764efb5 286 \param [in] fpscr Floating Point Status/Control value to set
FranKP2138 0:2b9b5764efb5 287 */
FranKP2138 0:2b9b5764efb5 288 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
FranKP2138 0:2b9b5764efb5 289 {
FranKP2138 0:2b9b5764efb5 290 #if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
FranKP2138 0:2b9b5764efb5 291 register uint32_t __regfpscr __ASM("fpscr");
FranKP2138 0:2b9b5764efb5 292 __regfpscr = (fpscr);
FranKP2138 0:2b9b5764efb5 293 #endif
FranKP2138 0:2b9b5764efb5 294 }
FranKP2138 0:2b9b5764efb5 295
FranKP2138 0:2b9b5764efb5 296 #endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
FranKP2138 0:2b9b5764efb5 297
FranKP2138 0:2b9b5764efb5 298
FranKP2138 0:2b9b5764efb5 299
FranKP2138 0:2b9b5764efb5 300 /*@} end of CMSIS_Core_RegAccFunctions */
FranKP2138 0:2b9b5764efb5 301
FranKP2138 0:2b9b5764efb5 302
FranKP2138 0:2b9b5764efb5 303 /* ########################## Core Instruction Access ######################### */
FranKP2138 0:2b9b5764efb5 304 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
FranKP2138 0:2b9b5764efb5 305 Access to dedicated instructions
FranKP2138 0:2b9b5764efb5 306 @{
FranKP2138 0:2b9b5764efb5 307 */
FranKP2138 0:2b9b5764efb5 308
FranKP2138 0:2b9b5764efb5 309 /**
FranKP2138 0:2b9b5764efb5 310 \brief No Operation
FranKP2138 0:2b9b5764efb5 311 \details No Operation does nothing. This instruction can be used for code alignment purposes.
FranKP2138 0:2b9b5764efb5 312 */
FranKP2138 0:2b9b5764efb5 313 #define __NOP __nop
FranKP2138 0:2b9b5764efb5 314
FranKP2138 0:2b9b5764efb5 315
FranKP2138 0:2b9b5764efb5 316 /**
FranKP2138 0:2b9b5764efb5 317 \brief Wait For Interrupt
FranKP2138 0:2b9b5764efb5 318 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
FranKP2138 0:2b9b5764efb5 319 */
FranKP2138 0:2b9b5764efb5 320 #define __WFI __wfi
FranKP2138 0:2b9b5764efb5 321
FranKP2138 0:2b9b5764efb5 322
FranKP2138 0:2b9b5764efb5 323 /**
FranKP2138 0:2b9b5764efb5 324 \brief Wait For Event
FranKP2138 0:2b9b5764efb5 325 \details Wait For Event is a hint instruction that permits the processor to enter
FranKP2138 0:2b9b5764efb5 326 a low-power state until one of a number of events occurs.
FranKP2138 0:2b9b5764efb5 327 */
FranKP2138 0:2b9b5764efb5 328 #define __WFE __wfe
FranKP2138 0:2b9b5764efb5 329
FranKP2138 0:2b9b5764efb5 330
FranKP2138 0:2b9b5764efb5 331 /**
FranKP2138 0:2b9b5764efb5 332 \brief Send Event
FranKP2138 0:2b9b5764efb5 333 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
FranKP2138 0:2b9b5764efb5 334 */
FranKP2138 0:2b9b5764efb5 335 #define __SEV __sev
FranKP2138 0:2b9b5764efb5 336
FranKP2138 0:2b9b5764efb5 337
FranKP2138 0:2b9b5764efb5 338 /**
FranKP2138 0:2b9b5764efb5 339 \brief Instruction Synchronization Barrier
FranKP2138 0:2b9b5764efb5 340 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
FranKP2138 0:2b9b5764efb5 341 so that all instructions following the ISB are fetched from cache or memory,
FranKP2138 0:2b9b5764efb5 342 after the instruction has been completed.
FranKP2138 0:2b9b5764efb5 343 */
FranKP2138 0:2b9b5764efb5 344 #define __ISB() do {\
FranKP2138 0:2b9b5764efb5 345 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 346 __isb(0xF);\
FranKP2138 0:2b9b5764efb5 347 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 348 } while (0U)
FranKP2138 0:2b9b5764efb5 349
FranKP2138 0:2b9b5764efb5 350 /**
FranKP2138 0:2b9b5764efb5 351 \brief Data Synchronization Barrier
FranKP2138 0:2b9b5764efb5 352 \details Acts as a special kind of Data Memory Barrier.
FranKP2138 0:2b9b5764efb5 353 It completes when all explicit memory accesses before this instruction complete.
FranKP2138 0:2b9b5764efb5 354 */
FranKP2138 0:2b9b5764efb5 355 #define __DSB() do {\
FranKP2138 0:2b9b5764efb5 356 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 357 __dsb(0xF);\
FranKP2138 0:2b9b5764efb5 358 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 359 } while (0U)
FranKP2138 0:2b9b5764efb5 360
FranKP2138 0:2b9b5764efb5 361 /**
FranKP2138 0:2b9b5764efb5 362 \brief Data Memory Barrier
FranKP2138 0:2b9b5764efb5 363 \details Ensures the apparent order of the explicit memory operations before
FranKP2138 0:2b9b5764efb5 364 and after the instruction, without ensuring their completion.
FranKP2138 0:2b9b5764efb5 365 */
FranKP2138 0:2b9b5764efb5 366 #define __DMB() do {\
FranKP2138 0:2b9b5764efb5 367 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 368 __dmb(0xF);\
FranKP2138 0:2b9b5764efb5 369 __schedule_barrier();\
FranKP2138 0:2b9b5764efb5 370 } while (0U)
FranKP2138 0:2b9b5764efb5 371
FranKP2138 0:2b9b5764efb5 372 /**
FranKP2138 0:2b9b5764efb5 373 \brief Reverse byte order (32 bit)
FranKP2138 0:2b9b5764efb5 374 \details Reverses the byte order in integer value.
FranKP2138 0:2b9b5764efb5 375 \param [in] value Value to reverse
FranKP2138 0:2b9b5764efb5 376 \return Reversed value
FranKP2138 0:2b9b5764efb5 377 */
FranKP2138 0:2b9b5764efb5 378 #define __REV __rev
FranKP2138 0:2b9b5764efb5 379
FranKP2138 0:2b9b5764efb5 380
FranKP2138 0:2b9b5764efb5 381 /**
FranKP2138 0:2b9b5764efb5 382 \brief Reverse byte order (16 bit)
FranKP2138 0:2b9b5764efb5 383 \details Reverses the byte order in two unsigned short values.
FranKP2138 0:2b9b5764efb5 384 \param [in] value Value to reverse
FranKP2138 0:2b9b5764efb5 385 \return Reversed value
FranKP2138 0:2b9b5764efb5 386 */
FranKP2138 0:2b9b5764efb5 387 #ifndef __NO_EMBEDDED_ASM
FranKP2138 0:2b9b5764efb5 388 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
FranKP2138 0:2b9b5764efb5 389 {
FranKP2138 0:2b9b5764efb5 390 rev16 r0, r0
FranKP2138 0:2b9b5764efb5 391 bx lr
FranKP2138 0:2b9b5764efb5 392 }
FranKP2138 0:2b9b5764efb5 393 #endif
FranKP2138 0:2b9b5764efb5 394
FranKP2138 0:2b9b5764efb5 395 /**
FranKP2138 0:2b9b5764efb5 396 \brief Reverse byte order in signed short value
FranKP2138 0:2b9b5764efb5 397 \details Reverses the byte order in a signed short value with sign extension to integer.
FranKP2138 0:2b9b5764efb5 398 \param [in] value Value to reverse
FranKP2138 0:2b9b5764efb5 399 \return Reversed value
FranKP2138 0:2b9b5764efb5 400 */
FranKP2138 0:2b9b5764efb5 401 #ifndef __NO_EMBEDDED_ASM
FranKP2138 0:2b9b5764efb5 402 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
FranKP2138 0:2b9b5764efb5 403 {
FranKP2138 0:2b9b5764efb5 404 revsh r0, r0
FranKP2138 0:2b9b5764efb5 405 bx lr
FranKP2138 0:2b9b5764efb5 406 }
FranKP2138 0:2b9b5764efb5 407 #endif
FranKP2138 0:2b9b5764efb5 408
FranKP2138 0:2b9b5764efb5 409
FranKP2138 0:2b9b5764efb5 410 /**
FranKP2138 0:2b9b5764efb5 411 \brief Rotate Right in unsigned value (32 bit)
FranKP2138 0:2b9b5764efb5 412 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
FranKP2138 0:2b9b5764efb5 413 \param [in] value Value to rotate
FranKP2138 0:2b9b5764efb5 414 \param [in] value Number of Bits to rotate
FranKP2138 0:2b9b5764efb5 415 \return Rotated value
FranKP2138 0:2b9b5764efb5 416 */
FranKP2138 0:2b9b5764efb5 417 #define __ROR __ror
FranKP2138 0:2b9b5764efb5 418
FranKP2138 0:2b9b5764efb5 419
FranKP2138 0:2b9b5764efb5 420 /**
FranKP2138 0:2b9b5764efb5 421 \brief Breakpoint
FranKP2138 0:2b9b5764efb5 422 \details Causes the processor to enter Debug state.
FranKP2138 0:2b9b5764efb5 423 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
FranKP2138 0:2b9b5764efb5 424 \param [in] value is ignored by the processor.
FranKP2138 0:2b9b5764efb5 425 If required, a debugger can use it to store additional information about the breakpoint.
FranKP2138 0:2b9b5764efb5 426 */
FranKP2138 0:2b9b5764efb5 427 #define __BKPT(value) __breakpoint(value)
FranKP2138 0:2b9b5764efb5 428
FranKP2138 0:2b9b5764efb5 429
FranKP2138 0:2b9b5764efb5 430 /**
FranKP2138 0:2b9b5764efb5 431 \brief Reverse bit order of value
FranKP2138 0:2b9b5764efb5 432 \details Reverses the bit order of the given value.
FranKP2138 0:2b9b5764efb5 433 \param [in] value Value to reverse
FranKP2138 0:2b9b5764efb5 434 \return Reversed value
FranKP2138 0:2b9b5764efb5 435 */
FranKP2138 0:2b9b5764efb5 436 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
FranKP2138 0:2b9b5764efb5 437 #define __RBIT __rbit
FranKP2138 0:2b9b5764efb5 438 #else
FranKP2138 0:2b9b5764efb5 439 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
FranKP2138 0:2b9b5764efb5 440 {
FranKP2138 0:2b9b5764efb5 441 uint32_t result;
FranKP2138 0:2b9b5764efb5 442 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
FranKP2138 0:2b9b5764efb5 443
FranKP2138 0:2b9b5764efb5 444 result = value; /* r will be reversed bits of v; first get LSB of v */
FranKP2138 0:2b9b5764efb5 445 for (value >>= 1U; value; value >>= 1U)
FranKP2138 0:2b9b5764efb5 446 {
FranKP2138 0:2b9b5764efb5 447 result <<= 1U;
FranKP2138 0:2b9b5764efb5 448 result |= value & 1U;
FranKP2138 0:2b9b5764efb5 449 s--;
FranKP2138 0:2b9b5764efb5 450 }
FranKP2138 0:2b9b5764efb5 451 result <<= s; /* shift when v's highest bits are zero */
FranKP2138 0:2b9b5764efb5 452 return(result);
FranKP2138 0:2b9b5764efb5 453 }
FranKP2138 0:2b9b5764efb5 454 #endif
FranKP2138 0:2b9b5764efb5 455
FranKP2138 0:2b9b5764efb5 456
FranKP2138 0:2b9b5764efb5 457 /**
FranKP2138 0:2b9b5764efb5 458 \brief Count leading zeros
FranKP2138 0:2b9b5764efb5 459 \details Counts the number of leading zeros of a data value.
FranKP2138 0:2b9b5764efb5 460 \param [in] value Value to count the leading zeros
FranKP2138 0:2b9b5764efb5 461 \return number of leading zeros in value
FranKP2138 0:2b9b5764efb5 462 */
FranKP2138 0:2b9b5764efb5 463 #define __CLZ __clz
FranKP2138 0:2b9b5764efb5 464
FranKP2138 0:2b9b5764efb5 465
FranKP2138 0:2b9b5764efb5 466 #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
FranKP2138 0:2b9b5764efb5 467
FranKP2138 0:2b9b5764efb5 468 /**
FranKP2138 0:2b9b5764efb5 469 \brief LDR Exclusive (8 bit)
FranKP2138 0:2b9b5764efb5 470 \details Executes a exclusive LDR instruction for 8 bit value.
FranKP2138 0:2b9b5764efb5 471 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 472 \return value of type uint8_t at (*ptr)
FranKP2138 0:2b9b5764efb5 473 */
FranKP2138 0:2b9b5764efb5 474 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 475 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
FranKP2138 0:2b9b5764efb5 476 #else
FranKP2138 0:2b9b5764efb5 477 #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 478 #endif
FranKP2138 0:2b9b5764efb5 479
FranKP2138 0:2b9b5764efb5 480
FranKP2138 0:2b9b5764efb5 481 /**
FranKP2138 0:2b9b5764efb5 482 \brief LDR Exclusive (16 bit)
FranKP2138 0:2b9b5764efb5 483 \details Executes a exclusive LDR instruction for 16 bit values.
FranKP2138 0:2b9b5764efb5 484 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 485 \return value of type uint16_t at (*ptr)
FranKP2138 0:2b9b5764efb5 486 */
FranKP2138 0:2b9b5764efb5 487 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 488 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
FranKP2138 0:2b9b5764efb5 489 #else
FranKP2138 0:2b9b5764efb5 490 #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 491 #endif
FranKP2138 0:2b9b5764efb5 492
FranKP2138 0:2b9b5764efb5 493
FranKP2138 0:2b9b5764efb5 494 /**
FranKP2138 0:2b9b5764efb5 495 \brief LDR Exclusive (32 bit)
FranKP2138 0:2b9b5764efb5 496 \details Executes a exclusive LDR instruction for 32 bit values.
FranKP2138 0:2b9b5764efb5 497 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 498 \return value of type uint32_t at (*ptr)
FranKP2138 0:2b9b5764efb5 499 */
FranKP2138 0:2b9b5764efb5 500 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 501 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
FranKP2138 0:2b9b5764efb5 502 #else
FranKP2138 0:2b9b5764efb5 503 #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 504 #endif
FranKP2138 0:2b9b5764efb5 505
FranKP2138 0:2b9b5764efb5 506
FranKP2138 0:2b9b5764efb5 507 /**
FranKP2138 0:2b9b5764efb5 508 \brief STR Exclusive (8 bit)
FranKP2138 0:2b9b5764efb5 509 \details Executes a exclusive STR instruction for 8 bit values.
FranKP2138 0:2b9b5764efb5 510 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 511 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 512 \return 0 Function succeeded
FranKP2138 0:2b9b5764efb5 513 \return 1 Function failed
FranKP2138 0:2b9b5764efb5 514 */
FranKP2138 0:2b9b5764efb5 515 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 516 #define __STREXB(value, ptr) __strex(value, ptr)
FranKP2138 0:2b9b5764efb5 517 #else
FranKP2138 0:2b9b5764efb5 518 #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 519 #endif
FranKP2138 0:2b9b5764efb5 520
FranKP2138 0:2b9b5764efb5 521
FranKP2138 0:2b9b5764efb5 522 /**
FranKP2138 0:2b9b5764efb5 523 \brief STR Exclusive (16 bit)
FranKP2138 0:2b9b5764efb5 524 \details Executes a exclusive STR instruction for 16 bit values.
FranKP2138 0:2b9b5764efb5 525 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 526 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 527 \return 0 Function succeeded
FranKP2138 0:2b9b5764efb5 528 \return 1 Function failed
FranKP2138 0:2b9b5764efb5 529 */
FranKP2138 0:2b9b5764efb5 530 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 531 #define __STREXH(value, ptr) __strex(value, ptr)
FranKP2138 0:2b9b5764efb5 532 #else
FranKP2138 0:2b9b5764efb5 533 #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 534 #endif
FranKP2138 0:2b9b5764efb5 535
FranKP2138 0:2b9b5764efb5 536
FranKP2138 0:2b9b5764efb5 537 /**
FranKP2138 0:2b9b5764efb5 538 \brief STR Exclusive (32 bit)
FranKP2138 0:2b9b5764efb5 539 \details Executes a exclusive STR instruction for 32 bit values.
FranKP2138 0:2b9b5764efb5 540 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 541 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 542 \return 0 Function succeeded
FranKP2138 0:2b9b5764efb5 543 \return 1 Function failed
FranKP2138 0:2b9b5764efb5 544 */
FranKP2138 0:2b9b5764efb5 545 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
FranKP2138 0:2b9b5764efb5 546 #define __STREXW(value, ptr) __strex(value, ptr)
FranKP2138 0:2b9b5764efb5 547 #else
FranKP2138 0:2b9b5764efb5 548 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
FranKP2138 0:2b9b5764efb5 549 #endif
FranKP2138 0:2b9b5764efb5 550
FranKP2138 0:2b9b5764efb5 551
FranKP2138 0:2b9b5764efb5 552 /**
FranKP2138 0:2b9b5764efb5 553 \brief Remove the exclusive lock
FranKP2138 0:2b9b5764efb5 554 \details Removes the exclusive lock which is created by LDREX.
FranKP2138 0:2b9b5764efb5 555 */
FranKP2138 0:2b9b5764efb5 556 #define __CLREX __clrex
FranKP2138 0:2b9b5764efb5 557
FranKP2138 0:2b9b5764efb5 558
FranKP2138 0:2b9b5764efb5 559 /**
FranKP2138 0:2b9b5764efb5 560 \brief Signed Saturate
FranKP2138 0:2b9b5764efb5 561 \details Saturates a signed value.
FranKP2138 0:2b9b5764efb5 562 \param [in] value Value to be saturated
FranKP2138 0:2b9b5764efb5 563 \param [in] sat Bit position to saturate to (1..32)
FranKP2138 0:2b9b5764efb5 564 \return Saturated value
FranKP2138 0:2b9b5764efb5 565 */
FranKP2138 0:2b9b5764efb5 566 #define __SSAT __ssat
FranKP2138 0:2b9b5764efb5 567
FranKP2138 0:2b9b5764efb5 568
FranKP2138 0:2b9b5764efb5 569 /**
FranKP2138 0:2b9b5764efb5 570 \brief Unsigned Saturate
FranKP2138 0:2b9b5764efb5 571 \details Saturates an unsigned value.
FranKP2138 0:2b9b5764efb5 572 \param [in] value Value to be saturated
FranKP2138 0:2b9b5764efb5 573 \param [in] sat Bit position to saturate to (0..31)
FranKP2138 0:2b9b5764efb5 574 \return Saturated value
FranKP2138 0:2b9b5764efb5 575 */
FranKP2138 0:2b9b5764efb5 576 #define __USAT __usat
FranKP2138 0:2b9b5764efb5 577
FranKP2138 0:2b9b5764efb5 578
FranKP2138 0:2b9b5764efb5 579 /**
FranKP2138 0:2b9b5764efb5 580 \brief Rotate Right with Extend (32 bit)
FranKP2138 0:2b9b5764efb5 581 \details Moves each bit of a bitstring right by one bit.
FranKP2138 0:2b9b5764efb5 582 The carry input is shifted in at the left end of the bitstring.
FranKP2138 0:2b9b5764efb5 583 \param [in] value Value to rotate
FranKP2138 0:2b9b5764efb5 584 \return Rotated value
FranKP2138 0:2b9b5764efb5 585 */
FranKP2138 0:2b9b5764efb5 586 #ifndef __NO_EMBEDDED_ASM
FranKP2138 0:2b9b5764efb5 587 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
FranKP2138 0:2b9b5764efb5 588 {
FranKP2138 0:2b9b5764efb5 589 rrx r0, r0
FranKP2138 0:2b9b5764efb5 590 bx lr
FranKP2138 0:2b9b5764efb5 591 }
FranKP2138 0:2b9b5764efb5 592 #endif
FranKP2138 0:2b9b5764efb5 593
FranKP2138 0:2b9b5764efb5 594
FranKP2138 0:2b9b5764efb5 595 /**
FranKP2138 0:2b9b5764efb5 596 \brief LDRT Unprivileged (8 bit)
FranKP2138 0:2b9b5764efb5 597 \details Executes a Unprivileged LDRT instruction for 8 bit value.
FranKP2138 0:2b9b5764efb5 598 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 599 \return value of type uint8_t at (*ptr)
FranKP2138 0:2b9b5764efb5 600 */
FranKP2138 0:2b9b5764efb5 601 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
FranKP2138 0:2b9b5764efb5 602
FranKP2138 0:2b9b5764efb5 603
FranKP2138 0:2b9b5764efb5 604 /**
FranKP2138 0:2b9b5764efb5 605 \brief LDRT Unprivileged (16 bit)
FranKP2138 0:2b9b5764efb5 606 \details Executes a Unprivileged LDRT instruction for 16 bit values.
FranKP2138 0:2b9b5764efb5 607 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 608 \return value of type uint16_t at (*ptr)
FranKP2138 0:2b9b5764efb5 609 */
FranKP2138 0:2b9b5764efb5 610 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
FranKP2138 0:2b9b5764efb5 611
FranKP2138 0:2b9b5764efb5 612
FranKP2138 0:2b9b5764efb5 613 /**
FranKP2138 0:2b9b5764efb5 614 \brief LDRT Unprivileged (32 bit)
FranKP2138 0:2b9b5764efb5 615 \details Executes a Unprivileged LDRT instruction for 32 bit values.
FranKP2138 0:2b9b5764efb5 616 \param [in] ptr Pointer to data
FranKP2138 0:2b9b5764efb5 617 \return value of type uint32_t at (*ptr)
FranKP2138 0:2b9b5764efb5 618 */
FranKP2138 0:2b9b5764efb5 619 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
FranKP2138 0:2b9b5764efb5 620
FranKP2138 0:2b9b5764efb5 621
FranKP2138 0:2b9b5764efb5 622 /**
FranKP2138 0:2b9b5764efb5 623 \brief STRT Unprivileged (8 bit)
FranKP2138 0:2b9b5764efb5 624 \details Executes a Unprivileged STRT instruction for 8 bit values.
FranKP2138 0:2b9b5764efb5 625 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 626 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 627 */
FranKP2138 0:2b9b5764efb5 628 #define __STRBT(value, ptr) __strt(value, ptr)
FranKP2138 0:2b9b5764efb5 629
FranKP2138 0:2b9b5764efb5 630
FranKP2138 0:2b9b5764efb5 631 /**
FranKP2138 0:2b9b5764efb5 632 \brief STRT Unprivileged (16 bit)
FranKP2138 0:2b9b5764efb5 633 \details Executes a Unprivileged STRT instruction for 16 bit values.
FranKP2138 0:2b9b5764efb5 634 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 635 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 636 */
FranKP2138 0:2b9b5764efb5 637 #define __STRHT(value, ptr) __strt(value, ptr)
FranKP2138 0:2b9b5764efb5 638
FranKP2138 0:2b9b5764efb5 639
FranKP2138 0:2b9b5764efb5 640 /**
FranKP2138 0:2b9b5764efb5 641 \brief STRT Unprivileged (32 bit)
FranKP2138 0:2b9b5764efb5 642 \details Executes a Unprivileged STRT instruction for 32 bit values.
FranKP2138 0:2b9b5764efb5 643 \param [in] value Value to store
FranKP2138 0:2b9b5764efb5 644 \param [in] ptr Pointer to location
FranKP2138 0:2b9b5764efb5 645 */
FranKP2138 0:2b9b5764efb5 646 #define __STRT(value, ptr) __strt(value, ptr)
FranKP2138 0:2b9b5764efb5 647
FranKP2138 0:2b9b5764efb5 648 #endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
FranKP2138 0:2b9b5764efb5 649
FranKP2138 0:2b9b5764efb5 650 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
FranKP2138 0:2b9b5764efb5 651
FranKP2138 0:2b9b5764efb5 652
FranKP2138 0:2b9b5764efb5 653 /* ################### Compiler specific Intrinsics ########################### */
FranKP2138 0:2b9b5764efb5 654 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
FranKP2138 0:2b9b5764efb5 655 Access to dedicated SIMD instructions
FranKP2138 0:2b9b5764efb5 656 @{
FranKP2138 0:2b9b5764efb5 657 */
FranKP2138 0:2b9b5764efb5 658
FranKP2138 0:2b9b5764efb5 659 #if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
FranKP2138 0:2b9b5764efb5 660
FranKP2138 0:2b9b5764efb5 661 #define __SADD8 __sadd8
FranKP2138 0:2b9b5764efb5 662 #define __QADD8 __qadd8
FranKP2138 0:2b9b5764efb5 663 #define __SHADD8 __shadd8
FranKP2138 0:2b9b5764efb5 664 #define __UADD8 __uadd8
FranKP2138 0:2b9b5764efb5 665 #define __UQADD8 __uqadd8
FranKP2138 0:2b9b5764efb5 666 #define __UHADD8 __uhadd8
FranKP2138 0:2b9b5764efb5 667 #define __SSUB8 __ssub8
FranKP2138 0:2b9b5764efb5 668 #define __QSUB8 __qsub8
FranKP2138 0:2b9b5764efb5 669 #define __SHSUB8 __shsub8
FranKP2138 0:2b9b5764efb5 670 #define __USUB8 __usub8
FranKP2138 0:2b9b5764efb5 671 #define __UQSUB8 __uqsub8
FranKP2138 0:2b9b5764efb5 672 #define __UHSUB8 __uhsub8
FranKP2138 0:2b9b5764efb5 673 #define __SADD16 __sadd16
FranKP2138 0:2b9b5764efb5 674 #define __QADD16 __qadd16
FranKP2138 0:2b9b5764efb5 675 #define __SHADD16 __shadd16
FranKP2138 0:2b9b5764efb5 676 #define __UADD16 __uadd16
FranKP2138 0:2b9b5764efb5 677 #define __UQADD16 __uqadd16
FranKP2138 0:2b9b5764efb5 678 #define __UHADD16 __uhadd16
FranKP2138 0:2b9b5764efb5 679 #define __SSUB16 __ssub16
FranKP2138 0:2b9b5764efb5 680 #define __QSUB16 __qsub16
FranKP2138 0:2b9b5764efb5 681 #define __SHSUB16 __shsub16
FranKP2138 0:2b9b5764efb5 682 #define __USUB16 __usub16
FranKP2138 0:2b9b5764efb5 683 #define __UQSUB16 __uqsub16
FranKP2138 0:2b9b5764efb5 684 #define __UHSUB16 __uhsub16
FranKP2138 0:2b9b5764efb5 685 #define __SASX __sasx
FranKP2138 0:2b9b5764efb5 686 #define __QASX __qasx
FranKP2138 0:2b9b5764efb5 687 #define __SHASX __shasx
FranKP2138 0:2b9b5764efb5 688 #define __UASX __uasx
FranKP2138 0:2b9b5764efb5 689 #define __UQASX __uqasx
FranKP2138 0:2b9b5764efb5 690 #define __UHASX __uhasx
FranKP2138 0:2b9b5764efb5 691 #define __SSAX __ssax
FranKP2138 0:2b9b5764efb5 692 #define __QSAX __qsax
FranKP2138 0:2b9b5764efb5 693 #define __SHSAX __shsax
FranKP2138 0:2b9b5764efb5 694 #define __USAX __usax
FranKP2138 0:2b9b5764efb5 695 #define __UQSAX __uqsax
FranKP2138 0:2b9b5764efb5 696 #define __UHSAX __uhsax
FranKP2138 0:2b9b5764efb5 697 #define __USAD8 __usad8
FranKP2138 0:2b9b5764efb5 698 #define __USADA8 __usada8
FranKP2138 0:2b9b5764efb5 699 #define __SSAT16 __ssat16
FranKP2138 0:2b9b5764efb5 700 #define __USAT16 __usat16
FranKP2138 0:2b9b5764efb5 701 #define __UXTB16 __uxtb16
FranKP2138 0:2b9b5764efb5 702 #define __UXTAB16 __uxtab16
FranKP2138 0:2b9b5764efb5 703 #define __SXTB16 __sxtb16
FranKP2138 0:2b9b5764efb5 704 #define __SXTAB16 __sxtab16
FranKP2138 0:2b9b5764efb5 705 #define __SMUAD __smuad
FranKP2138 0:2b9b5764efb5 706 #define __SMUADX __smuadx
FranKP2138 0:2b9b5764efb5 707 #define __SMLAD __smlad
FranKP2138 0:2b9b5764efb5 708 #define __SMLADX __smladx
FranKP2138 0:2b9b5764efb5 709 #define __SMLALD __smlald
FranKP2138 0:2b9b5764efb5 710 #define __SMLALDX __smlaldx
FranKP2138 0:2b9b5764efb5 711 #define __SMUSD __smusd
FranKP2138 0:2b9b5764efb5 712 #define __SMUSDX __smusdx
FranKP2138 0:2b9b5764efb5 713 #define __SMLSD __smlsd
FranKP2138 0:2b9b5764efb5 714 #define __SMLSDX __smlsdx
FranKP2138 0:2b9b5764efb5 715 #define __SMLSLD __smlsld
FranKP2138 0:2b9b5764efb5 716 #define __SMLSLDX __smlsldx
FranKP2138 0:2b9b5764efb5 717 #define __SEL __sel
FranKP2138 0:2b9b5764efb5 718 #define __QADD __qadd
FranKP2138 0:2b9b5764efb5 719 #define __QSUB __qsub
FranKP2138 0:2b9b5764efb5 720
FranKP2138 0:2b9b5764efb5 721 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
FranKP2138 0:2b9b5764efb5 722 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
FranKP2138 0:2b9b5764efb5 723
FranKP2138 0:2b9b5764efb5 724 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
FranKP2138 0:2b9b5764efb5 725 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
FranKP2138 0:2b9b5764efb5 726
FranKP2138 0:2b9b5764efb5 727 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
FranKP2138 0:2b9b5764efb5 728 ((int64_t)(ARG3) << 32U) ) >> 32U))
FranKP2138 0:2b9b5764efb5 729
FranKP2138 0:2b9b5764efb5 730 #endif /* (__CORTEX_M >= 0x04) */
FranKP2138 0:2b9b5764efb5 731 /*@} end of group CMSIS_SIMD_intrinsics */
FranKP2138 0:2b9b5764efb5 732
FranKP2138 0:2b9b5764efb5 733
FranKP2138 0:2b9b5764efb5 734 #endif /* __CMSIS_ARMCC_H */
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