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targets/cmsis/core_cm7.h@636:83983d65f9e7, 2015-11-12 (annotated)

Committer:
EricLew
Date:
Thu Nov 12 20:51:01 2015 +0000
Revision:
636:83983d65f9e7
Parent:
573:ad23fe03a082 
deleted other targets than disco board

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mbed_official 573:ad23fe03a082 1 /**************************************************************************//**
mbed_official 573:ad23fe03a082 2 * @file core_cm7.h
mbed_official 573:ad23fe03a082 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
mbed_official 573:ad23fe03a082 4 * @version V4.10
mbed_official 573:ad23fe03a082 5 * @date 18. March 2015
mbed_official 573:ad23fe03a082 6 *
mbed_official 573:ad23fe03a082 7 * @note
mbed_official 573:ad23fe03a082 8 *
mbed_official 573:ad23fe03a082 9 ******************************************************************************/
mbed_official 573:ad23fe03a082 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mbed_official 573:ad23fe03a082 11
mbed_official 573:ad23fe03a082 12 All rights reserved.
mbed_official 573:ad23fe03a082 13 Redistribution and use in source and binary forms, with or without
mbed_official 573:ad23fe03a082 14 modification, are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 15 - Redistributions of source code must retain the above copyright
mbed_official 573:ad23fe03a082 16 notice, this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 573:ad23fe03a082 18 notice, this list of conditions and the following disclaimer in the
mbed_official 573:ad23fe03a082 19 documentation and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 573:ad23fe03a082 21 to endorse or promote products derived from this software without
mbed_official 573:ad23fe03a082 22 specific prior written permission.
mbed_official 573:ad23fe03a082 23 *
mbed_official 573:ad23fe03a082 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 573:ad23fe03a082 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 573:ad23fe03a082 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 573:ad23fe03a082 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 573:ad23fe03a082 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 573:ad23fe03a082 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 573:ad23fe03a082 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 573:ad23fe03a082 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 573:ad23fe03a082 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 35 ---------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 36
mbed_official 573:ad23fe03a082 37
mbed_official 573:ad23fe03a082 38 #if defined ( __ICCARM__ )
mbed_official 573:ad23fe03a082 39 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 573:ad23fe03a082 40 #endif
mbed_official 573:ad23fe03a082 41
mbed_official 573:ad23fe03a082 42 #ifndef __CORE_CM7_H_GENERIC
mbed_official 573:ad23fe03a082 43 #define __CORE_CM7_H_GENERIC
mbed_official 573:ad23fe03a082 44
mbed_official 573:ad23fe03a082 45 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 46 extern "C" {
mbed_official 573:ad23fe03a082 47 #endif
mbed_official 573:ad23fe03a082 48
mbed_official 573:ad23fe03a082 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 573:ad23fe03a082 50 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 573:ad23fe03a082 51
mbed_official 573:ad23fe03a082 52 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 573:ad23fe03a082 53 Function definitions in header files are used to allow 'inlining'.
mbed_official 573:ad23fe03a082 54
mbed_official 573:ad23fe03a082 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 573:ad23fe03a082 56 Unions are used for effective representation of core registers.
mbed_official 573:ad23fe03a082 57
mbed_official 573:ad23fe03a082 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 573:ad23fe03a082 59 Function-like macros are used to allow more efficient code.
mbed_official 573:ad23fe03a082 60 */
mbed_official 573:ad23fe03a082 61
mbed_official 573:ad23fe03a082 62
mbed_official 573:ad23fe03a082 63 /*******************************************************************************
mbed_official 573:ad23fe03a082 64 * CMSIS definitions
mbed_official 573:ad23fe03a082 65 ******************************************************************************/
mbed_official 573:ad23fe03a082 66 /** \ingroup Cortex_M7
mbed_official 573:ad23fe03a082 67 @{
mbed_official 573:ad23fe03a082 68 */
mbed_official 573:ad23fe03a082 69
mbed_official 573:ad23fe03a082 70 /* CMSIS CM7 definitions */
mbed_official 573:ad23fe03a082 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mbed_official 573:ad23fe03a082 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mbed_official 573:ad23fe03a082 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
mbed_official 573:ad23fe03a082 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 573:ad23fe03a082 75
mbed_official 573:ad23fe03a082 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
mbed_official 573:ad23fe03a082 77
mbed_official 573:ad23fe03a082 78
mbed_official 573:ad23fe03a082 79 #if defined ( __CC_ARM )
mbed_official 573:ad23fe03a082 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mbed_official 573:ad23fe03a082 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mbed_official 573:ad23fe03a082 82 #define __STATIC_INLINE static __inline
mbed_official 573:ad23fe03a082 83
mbed_official 573:ad23fe03a082 84 #elif defined ( __GNUC__ )
mbed_official 573:ad23fe03a082 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbed_official 573:ad23fe03a082 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbed_official 573:ad23fe03a082 87 #define __STATIC_INLINE static inline
mbed_official 573:ad23fe03a082 88
mbed_official 573:ad23fe03a082 89 #elif defined ( __ICCARM__ )
mbed_official 573:ad23fe03a082 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mbed_official 573:ad23fe03a082 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mbed_official 573:ad23fe03a082 92 #define __STATIC_INLINE static inline
mbed_official 573:ad23fe03a082 93
mbed_official 573:ad23fe03a082 94 #elif defined ( __TMS470__ )
mbed_official 573:ad23fe03a082 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mbed_official 573:ad23fe03a082 96 #define __STATIC_INLINE static inline
mbed_official 573:ad23fe03a082 97
mbed_official 573:ad23fe03a082 98 #elif defined ( __TASKING__ )
mbed_official 573:ad23fe03a082 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mbed_official 573:ad23fe03a082 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mbed_official 573:ad23fe03a082 101 #define __STATIC_INLINE static inline
mbed_official 573:ad23fe03a082 102
mbed_official 573:ad23fe03a082 103 #elif defined ( __CSMC__ )
mbed_official 573:ad23fe03a082 104 #define __packed
mbed_official 573:ad23fe03a082 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mbed_official 573:ad23fe03a082 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mbed_official 573:ad23fe03a082 107 #define __STATIC_INLINE static inline
mbed_official 573:ad23fe03a082 108
mbed_official 573:ad23fe03a082 109 #endif
mbed_official 573:ad23fe03a082 110
mbed_official 573:ad23fe03a082 111 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 573:ad23fe03a082 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
mbed_official 573:ad23fe03a082 113 */
mbed_official 573:ad23fe03a082 114 #if defined ( __CC_ARM )
mbed_official 573:ad23fe03a082 115 #if defined __TARGET_FPU_VFP
mbed_official 573:ad23fe03a082 116 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 117 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 118 #else
mbed_official 573:ad23fe03a082 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 120 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 121 #endif
mbed_official 573:ad23fe03a082 122 #else
mbed_official 573:ad23fe03a082 123 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 124 #endif
mbed_official 573:ad23fe03a082 125
mbed_official 573:ad23fe03a082 126 #elif defined ( __GNUC__ )
mbed_official 573:ad23fe03a082 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 573:ad23fe03a082 128 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 129 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 130 #else
mbed_official 573:ad23fe03a082 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 132 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 133 #endif
mbed_official 573:ad23fe03a082 134 #else
mbed_official 573:ad23fe03a082 135 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 136 #endif
mbed_official 573:ad23fe03a082 137
mbed_official 573:ad23fe03a082 138 #elif defined ( __ICCARM__ )
mbed_official 573:ad23fe03a082 139 #if defined __ARMVFP__
mbed_official 573:ad23fe03a082 140 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 141 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 142 #else
mbed_official 573:ad23fe03a082 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 144 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 145 #endif
mbed_official 573:ad23fe03a082 146 #else
mbed_official 573:ad23fe03a082 147 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 148 #endif
mbed_official 573:ad23fe03a082 149
mbed_official 573:ad23fe03a082 150 #elif defined ( __TMS470__ )
mbed_official 573:ad23fe03a082 151 #if defined __TI_VFP_SUPPORT__
mbed_official 573:ad23fe03a082 152 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 153 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 154 #else
mbed_official 573:ad23fe03a082 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 156 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 157 #endif
mbed_official 573:ad23fe03a082 158 #else
mbed_official 573:ad23fe03a082 159 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 160 #endif
mbed_official 573:ad23fe03a082 161
mbed_official 573:ad23fe03a082 162 #elif defined ( __TASKING__ )
mbed_official 573:ad23fe03a082 163 #if defined __FPU_VFP__
mbed_official 573:ad23fe03a082 164 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 165 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 166 #else
mbed_official 573:ad23fe03a082 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 168 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 169 #endif
mbed_official 573:ad23fe03a082 170 #else
mbed_official 573:ad23fe03a082 171 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 172 #endif
mbed_official 573:ad23fe03a082 173
mbed_official 573:ad23fe03a082 174 #elif defined ( __CSMC__ ) /* Cosmic */
mbed_official 573:ad23fe03a082 175 #if ( __CSMC__ & 0x400) // FPU present for parser
mbed_official 573:ad23fe03a082 176 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 177 #define __FPU_USED 1
mbed_official 573:ad23fe03a082 178 #else
mbed_official 573:ad23fe03a082 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 573:ad23fe03a082 180 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 181 #endif
mbed_official 573:ad23fe03a082 182 #else
mbed_official 573:ad23fe03a082 183 #define __FPU_USED 0
mbed_official 573:ad23fe03a082 184 #endif
mbed_official 573:ad23fe03a082 185 #endif
mbed_official 573:ad23fe03a082 186
mbed_official 573:ad23fe03a082 187 #include <stdint.h> /* standard types definitions */
mbed_official 573:ad23fe03a082 188 #include <core_cmInstr.h> /* Core Instruction Access */
mbed_official 573:ad23fe03a082 189 #include <core_cmFunc.h> /* Core Function Access */
mbed_official 573:ad23fe03a082 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
mbed_official 573:ad23fe03a082 191
mbed_official 573:ad23fe03a082 192 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 193 }
mbed_official 573:ad23fe03a082 194 #endif
mbed_official 573:ad23fe03a082 195
mbed_official 573:ad23fe03a082 196 #endif /* __CORE_CM7_H_GENERIC */
mbed_official 573:ad23fe03a082 197
mbed_official 573:ad23fe03a082 198 #ifndef __CMSIS_GENERIC
mbed_official 573:ad23fe03a082 199
mbed_official 573:ad23fe03a082 200 #ifndef __CORE_CM7_H_DEPENDANT
mbed_official 573:ad23fe03a082 201 #define __CORE_CM7_H_DEPENDANT
mbed_official 573:ad23fe03a082 202
mbed_official 573:ad23fe03a082 203 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 204 extern "C" {
mbed_official 573:ad23fe03a082 205 #endif
mbed_official 573:ad23fe03a082 206
mbed_official 573:ad23fe03a082 207 /* check device defines and use defaults */
mbed_official 573:ad23fe03a082 208 #if defined __CHECK_DEVICE_DEFINES
mbed_official 573:ad23fe03a082 209 #ifndef __CM7_REV
mbed_official 573:ad23fe03a082 210 #define __CM7_REV 0x0000
mbed_official 573:ad23fe03a082 211 #warning "__CM7_REV not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 212 #endif
mbed_official 573:ad23fe03a082 213
mbed_official 573:ad23fe03a082 214 #ifndef __FPU_PRESENT
mbed_official 573:ad23fe03a082 215 #define __FPU_PRESENT 0
mbed_official 573:ad23fe03a082 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 217 #endif
mbed_official 573:ad23fe03a082 218
mbed_official 573:ad23fe03a082 219 #ifndef __MPU_PRESENT
mbed_official 573:ad23fe03a082 220 #define __MPU_PRESENT 0
mbed_official 573:ad23fe03a082 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 222 #endif
mbed_official 573:ad23fe03a082 223
mbed_official 573:ad23fe03a082 224 #ifndef __ICACHE_PRESENT
mbed_official 573:ad23fe03a082 225 #define __ICACHE_PRESENT 0
mbed_official 573:ad23fe03a082 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 227 #endif
mbed_official 573:ad23fe03a082 228
mbed_official 573:ad23fe03a082 229 #ifndef __DCACHE_PRESENT
mbed_official 573:ad23fe03a082 230 #define __DCACHE_PRESENT 0
mbed_official 573:ad23fe03a082 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 232 #endif
mbed_official 573:ad23fe03a082 233
mbed_official 573:ad23fe03a082 234 #ifndef __DTCM_PRESENT
mbed_official 573:ad23fe03a082 235 #define __DTCM_PRESENT 0
mbed_official 573:ad23fe03a082 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 237 #endif
mbed_official 573:ad23fe03a082 238
mbed_official 573:ad23fe03a082 239 #ifndef __NVIC_PRIO_BITS
mbed_official 573:ad23fe03a082 240 #define __NVIC_PRIO_BITS 3
mbed_official 573:ad23fe03a082 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 242 #endif
mbed_official 573:ad23fe03a082 243
mbed_official 573:ad23fe03a082 244 #ifndef __Vendor_SysTickConfig
mbed_official 573:ad23fe03a082 245 #define __Vendor_SysTickConfig 0
mbed_official 573:ad23fe03a082 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 573:ad23fe03a082 247 #endif
mbed_official 573:ad23fe03a082 248 #endif
mbed_official 573:ad23fe03a082 249
mbed_official 573:ad23fe03a082 250 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 573:ad23fe03a082 251 /**
mbed_official 573:ad23fe03a082 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 573:ad23fe03a082 253
mbed_official 573:ad23fe03a082 254 <strong>IO Type Qualifiers</strong> are used
mbed_official 573:ad23fe03a082 255 \li to specify the access to peripheral variables.
mbed_official 573:ad23fe03a082 256 \li for automatic generation of peripheral register debug information.
mbed_official 573:ad23fe03a082 257 */
mbed_official 573:ad23fe03a082 258 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 259 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 573:ad23fe03a082 260 #else
mbed_official 573:ad23fe03a082 261 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 573:ad23fe03a082 262 #endif
mbed_official 573:ad23fe03a082 263 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 573:ad23fe03a082 264 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 573:ad23fe03a082 265
mbed_official 573:ad23fe03a082 266 /*@} end of group Cortex_M7 */
mbed_official 573:ad23fe03a082 267
mbed_official 573:ad23fe03a082 268
mbed_official 573:ad23fe03a082 269
mbed_official 573:ad23fe03a082 270 /*******************************************************************************
mbed_official 573:ad23fe03a082 271 * Register Abstraction
mbed_official 573:ad23fe03a082 272 Core Register contain:
mbed_official 573:ad23fe03a082 273 - Core Register
mbed_official 573:ad23fe03a082 274 - Core NVIC Register
mbed_official 573:ad23fe03a082 275 - Core SCB Register
mbed_official 573:ad23fe03a082 276 - Core SysTick Register
mbed_official 573:ad23fe03a082 277 - Core Debug Register
mbed_official 573:ad23fe03a082 278 - Core MPU Register
mbed_official 573:ad23fe03a082 279 - Core FPU Register
mbed_official 573:ad23fe03a082 280 ******************************************************************************/
mbed_official 573:ad23fe03a082 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 573:ad23fe03a082 282 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 573:ad23fe03a082 283 */
mbed_official 573:ad23fe03a082 284
mbed_official 573:ad23fe03a082 285 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 286 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 573:ad23fe03a082 287 \brief Core Register type definitions.
mbed_official 573:ad23fe03a082 288 @{
mbed_official 573:ad23fe03a082 289 */
mbed_official 573:ad23fe03a082 290
mbed_official 573:ad23fe03a082 291 /** \brief Union type to access the Application Program Status Register (APSR).
mbed_official 573:ad23fe03a082 292 */
mbed_official 573:ad23fe03a082 293 typedef union
mbed_official 573:ad23fe03a082 294 {
mbed_official 573:ad23fe03a082 295 struct
mbed_official 573:ad23fe03a082 296 {
mbed_official 573:ad23fe03a082 297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
mbed_official 573:ad23fe03a082 298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbed_official 573:ad23fe03a082 299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
mbed_official 573:ad23fe03a082 300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 573:ad23fe03a082 301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 573:ad23fe03a082 302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 573:ad23fe03a082 303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 573:ad23fe03a082 304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 573:ad23fe03a082 305 } b; /*!< Structure used for bit access */
mbed_official 573:ad23fe03a082 306 uint32_t w; /*!< Type used for word access */
mbed_official 573:ad23fe03a082 307 } APSR_Type;
mbed_official 573:ad23fe03a082 308
mbed_official 573:ad23fe03a082 309 /* APSR Register Definitions */
mbed_official 573:ad23fe03a082 310 #define APSR_N_Pos 31 /*!< APSR: N Position */
mbed_official 573:ad23fe03a082 311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 573:ad23fe03a082 312
mbed_official 573:ad23fe03a082 313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mbed_official 573:ad23fe03a082 314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 573:ad23fe03a082 315
mbed_official 573:ad23fe03a082 316 #define APSR_C_Pos 29 /*!< APSR: C Position */
mbed_official 573:ad23fe03a082 317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 573:ad23fe03a082 318
mbed_official 573:ad23fe03a082 319 #define APSR_V_Pos 28 /*!< APSR: V Position */
mbed_official 573:ad23fe03a082 320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 573:ad23fe03a082 321
mbed_official 573:ad23fe03a082 322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
mbed_official 573:ad23fe03a082 323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
mbed_official 573:ad23fe03a082 324
mbed_official 573:ad23fe03a082 325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
mbed_official 573:ad23fe03a082 326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
mbed_official 573:ad23fe03a082 327
mbed_official 573:ad23fe03a082 328
mbed_official 573:ad23fe03a082 329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 573:ad23fe03a082 330 */
mbed_official 573:ad23fe03a082 331 typedef union
mbed_official 573:ad23fe03a082 332 {
mbed_official 573:ad23fe03a082 333 struct
mbed_official 573:ad23fe03a082 334 {
mbed_official 573:ad23fe03a082 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 573:ad23fe03a082 336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 573:ad23fe03a082 337 } b; /*!< Structure used for bit access */
mbed_official 573:ad23fe03a082 338 uint32_t w; /*!< Type used for word access */
mbed_official 573:ad23fe03a082 339 } IPSR_Type;
mbed_official 573:ad23fe03a082 340
mbed_official 573:ad23fe03a082 341 /* IPSR Register Definitions */
mbed_official 573:ad23fe03a082 342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mbed_official 573:ad23fe03a082 343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 573:ad23fe03a082 344
mbed_official 573:ad23fe03a082 345
mbed_official 573:ad23fe03a082 346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 573:ad23fe03a082 347 */
mbed_official 573:ad23fe03a082 348 typedef union
mbed_official 573:ad23fe03a082 349 {
mbed_official 573:ad23fe03a082 350 struct
mbed_official 573:ad23fe03a082 351 {
mbed_official 573:ad23fe03a082 352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 573:ad23fe03a082 353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
mbed_official 573:ad23fe03a082 354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
mbed_official 573:ad23fe03a082 355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
mbed_official 573:ad23fe03a082 356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 573:ad23fe03a082 357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mbed_official 573:ad23fe03a082 358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 573:ad23fe03a082 359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 573:ad23fe03a082 360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 573:ad23fe03a082 361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 573:ad23fe03a082 362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 573:ad23fe03a082 363 } b; /*!< Structure used for bit access */
mbed_official 573:ad23fe03a082 364 uint32_t w; /*!< Type used for word access */
mbed_official 573:ad23fe03a082 365 } xPSR_Type;
mbed_official 573:ad23fe03a082 366
mbed_official 573:ad23fe03a082 367 /* xPSR Register Definitions */
mbed_official 573:ad23fe03a082 368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mbed_official 573:ad23fe03a082 369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 573:ad23fe03a082 370
mbed_official 573:ad23fe03a082 371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mbed_official 573:ad23fe03a082 372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 573:ad23fe03a082 373
mbed_official 573:ad23fe03a082 374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mbed_official 573:ad23fe03a082 375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 573:ad23fe03a082 376
mbed_official 573:ad23fe03a082 377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mbed_official 573:ad23fe03a082 378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 573:ad23fe03a082 379
mbed_official 573:ad23fe03a082 380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
mbed_official 573:ad23fe03a082 381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
mbed_official 573:ad23fe03a082 382
mbed_official 573:ad23fe03a082 383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
mbed_official 573:ad23fe03a082 384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
mbed_official 573:ad23fe03a082 385
mbed_official 573:ad23fe03a082 386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mbed_official 573:ad23fe03a082 387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 573:ad23fe03a082 388
mbed_official 573:ad23fe03a082 389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
mbed_official 573:ad23fe03a082 390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
mbed_official 573:ad23fe03a082 391
mbed_official 573:ad23fe03a082 392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mbed_official 573:ad23fe03a082 393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 573:ad23fe03a082 394
mbed_official 573:ad23fe03a082 395
mbed_official 573:ad23fe03a082 396 /** \brief Union type to access the Control Registers (CONTROL).
mbed_official 573:ad23fe03a082 397 */
mbed_official 573:ad23fe03a082 398 typedef union
mbed_official 573:ad23fe03a082 399 {
mbed_official 573:ad23fe03a082 400 struct
mbed_official 573:ad23fe03a082 401 {
mbed_official 573:ad23fe03a082 402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbed_official 573:ad23fe03a082 403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 573:ad23fe03a082 404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
mbed_official 573:ad23fe03a082 405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
mbed_official 573:ad23fe03a082 406 } b; /*!< Structure used for bit access */
mbed_official 573:ad23fe03a082 407 uint32_t w; /*!< Type used for word access */
mbed_official 573:ad23fe03a082 408 } CONTROL_Type;
mbed_official 573:ad23fe03a082 409
mbed_official 573:ad23fe03a082 410 /* CONTROL Register Definitions */
mbed_official 573:ad23fe03a082 411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
mbed_official 573:ad23fe03a082 412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
mbed_official 573:ad23fe03a082 413
mbed_official 573:ad23fe03a082 414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mbed_official 573:ad23fe03a082 415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 573:ad23fe03a082 416
mbed_official 573:ad23fe03a082 417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
mbed_official 573:ad23fe03a082 418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 573:ad23fe03a082 419
mbed_official 573:ad23fe03a082 420 /*@} end of group CMSIS_CORE */
mbed_official 573:ad23fe03a082 421
mbed_official 573:ad23fe03a082 422
mbed_official 573:ad23fe03a082 423 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 573:ad23fe03a082 425 \brief Type definitions for the NVIC Registers
mbed_official 573:ad23fe03a082 426 @{
mbed_official 573:ad23fe03a082 427 */
mbed_official 573:ad23fe03a082 428
mbed_official 573:ad23fe03a082 429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 573:ad23fe03a082 430 */
mbed_official 573:ad23fe03a082 431 typedef struct
mbed_official 573:ad23fe03a082 432 {
mbed_official 573:ad23fe03a082 433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 573:ad23fe03a082 434 uint32_t RESERVED0[24];
mbed_official 573:ad23fe03a082 435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 573:ad23fe03a082 436 uint32_t RSERVED1[24];
mbed_official 573:ad23fe03a082 437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 573:ad23fe03a082 438 uint32_t RESERVED2[24];
mbed_official 573:ad23fe03a082 439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 573:ad23fe03a082 440 uint32_t RESERVED3[24];
mbed_official 573:ad23fe03a082 441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mbed_official 573:ad23fe03a082 442 uint32_t RESERVED4[56];
mbed_official 573:ad23fe03a082 443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mbed_official 573:ad23fe03a082 444 uint32_t RESERVED5[644];
mbed_official 573:ad23fe03a082 445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mbed_official 573:ad23fe03a082 446 } NVIC_Type;
mbed_official 573:ad23fe03a082 447
mbed_official 573:ad23fe03a082 448 /* Software Triggered Interrupt Register Definitions */
mbed_official 573:ad23fe03a082 449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mbed_official 573:ad23fe03a082 450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
mbed_official 573:ad23fe03a082 451
mbed_official 573:ad23fe03a082 452 /*@} end of group CMSIS_NVIC */
mbed_official 573:ad23fe03a082 453
mbed_official 573:ad23fe03a082 454
mbed_official 573:ad23fe03a082 455 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 456 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 573:ad23fe03a082 457 \brief Type definitions for the System Control Block Registers
mbed_official 573:ad23fe03a082 458 @{
mbed_official 573:ad23fe03a082 459 */
mbed_official 573:ad23fe03a082 460
mbed_official 573:ad23fe03a082 461 /** \brief Structure type to access the System Control Block (SCB).
mbed_official 573:ad23fe03a082 462 */
mbed_official 573:ad23fe03a082 463 typedef struct
mbed_official 573:ad23fe03a082 464 {
mbed_official 573:ad23fe03a082 465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 573:ad23fe03a082 466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 573:ad23fe03a082 467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbed_official 573:ad23fe03a082 468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 573:ad23fe03a082 469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 573:ad23fe03a082 470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 573:ad23fe03a082 471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mbed_official 573:ad23fe03a082 472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 573:ad23fe03a082 473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mbed_official 573:ad23fe03a082 474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mbed_official 573:ad23fe03a082 475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mbed_official 573:ad23fe03a082 476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mbed_official 573:ad23fe03a082 477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mbed_official 573:ad23fe03a082 478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mbed_official 573:ad23fe03a082 479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mbed_official 573:ad23fe03a082 480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mbed_official 573:ad23fe03a082 481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mbed_official 573:ad23fe03a082 482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mbed_official 573:ad23fe03a082 483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mbed_official 573:ad23fe03a082 484 uint32_t RESERVED0[1];
mbed_official 573:ad23fe03a082 485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
mbed_official 573:ad23fe03a082 486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
mbed_official 573:ad23fe03a082 487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
mbed_official 573:ad23fe03a082 488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
mbed_official 573:ad23fe03a082 489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mbed_official 573:ad23fe03a082 490 uint32_t RESERVED3[93];
mbed_official 573:ad23fe03a082 491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
mbed_official 573:ad23fe03a082 492 uint32_t RESERVED4[15];
mbed_official 573:ad23fe03a082 493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
mbed_official 573:ad23fe03a082 494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
mbed_official 573:ad23fe03a082 495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
mbed_official 573:ad23fe03a082 496 uint32_t RESERVED5[1];
mbed_official 573:ad23fe03a082 497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
mbed_official 573:ad23fe03a082 498 uint32_t RESERVED6[1];
mbed_official 573:ad23fe03a082 499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
mbed_official 573:ad23fe03a082 500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
mbed_official 573:ad23fe03a082 501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
mbed_official 573:ad23fe03a082 502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
mbed_official 573:ad23fe03a082 503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
mbed_official 573:ad23fe03a082 504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
mbed_official 573:ad23fe03a082 505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
mbed_official 573:ad23fe03a082 506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
mbed_official 573:ad23fe03a082 507 uint32_t RESERVED7[6];
mbed_official 573:ad23fe03a082 508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
mbed_official 573:ad23fe03a082 509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
mbed_official 573:ad23fe03a082 510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
mbed_official 573:ad23fe03a082 511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
mbed_official 573:ad23fe03a082 512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
mbed_official 573:ad23fe03a082 513 uint32_t RESERVED8[1];
mbed_official 573:ad23fe03a082 514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
mbed_official 573:ad23fe03a082 515 } SCB_Type;
mbed_official 573:ad23fe03a082 516
mbed_official 573:ad23fe03a082 517 /* SCB CPUID Register Definitions */
mbed_official 573:ad23fe03a082 518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 573:ad23fe03a082 519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 573:ad23fe03a082 520
mbed_official 573:ad23fe03a082 521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mbed_official 573:ad23fe03a082 522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 573:ad23fe03a082 523
mbed_official 573:ad23fe03a082 524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 573:ad23fe03a082 525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 573:ad23fe03a082 526
mbed_official 573:ad23fe03a082 527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mbed_official 573:ad23fe03a082 528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 573:ad23fe03a082 529
mbed_official 573:ad23fe03a082 530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbed_official 573:ad23fe03a082 531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 573:ad23fe03a082 532
mbed_official 573:ad23fe03a082 533 /* SCB Interrupt Control State Register Definitions */
mbed_official 573:ad23fe03a082 534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 573:ad23fe03a082 535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 573:ad23fe03a082 536
mbed_official 573:ad23fe03a082 537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mbed_official 573:ad23fe03a082 538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 573:ad23fe03a082 539
mbed_official 573:ad23fe03a082 540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 573:ad23fe03a082 541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 573:ad23fe03a082 542
mbed_official 573:ad23fe03a082 543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mbed_official 573:ad23fe03a082 544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 573:ad23fe03a082 545
mbed_official 573:ad23fe03a082 546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 573:ad23fe03a082 547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 573:ad23fe03a082 548
mbed_official 573:ad23fe03a082 549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 573:ad23fe03a082 550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 573:ad23fe03a082 551
mbed_official 573:ad23fe03a082 552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mbed_official 573:ad23fe03a082 553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 573:ad23fe03a082 554
mbed_official 573:ad23fe03a082 555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mbed_official 573:ad23fe03a082 556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 573:ad23fe03a082 557
mbed_official 573:ad23fe03a082 558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
mbed_official 573:ad23fe03a082 559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mbed_official 573:ad23fe03a082 560
mbed_official 573:ad23fe03a082 561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 573:ad23fe03a082 562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 573:ad23fe03a082 563
mbed_official 573:ad23fe03a082 564 /* SCB Vector Table Offset Register Definitions */
mbed_official 573:ad23fe03a082 565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mbed_official 573:ad23fe03a082 566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 573:ad23fe03a082 567
mbed_official 573:ad23fe03a082 568 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 573:ad23fe03a082 569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mbed_official 573:ad23fe03a082 570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 573:ad23fe03a082 571
mbed_official 573:ad23fe03a082 572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 573:ad23fe03a082 573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 573:ad23fe03a082 574
mbed_official 573:ad23fe03a082 575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 573:ad23fe03a082 576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 573:ad23fe03a082 577
mbed_official 573:ad23fe03a082 578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
mbed_official 573:ad23fe03a082 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mbed_official 573:ad23fe03a082 580
mbed_official 573:ad23fe03a082 581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 573:ad23fe03a082 582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 573:ad23fe03a082 583
mbed_official 573:ad23fe03a082 584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 573:ad23fe03a082 585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 573:ad23fe03a082 586
mbed_official 573:ad23fe03a082 587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mbed_official 573:ad23fe03a082 588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
mbed_official 573:ad23fe03a082 589
mbed_official 573:ad23fe03a082 590 /* SCB System Control Register Definitions */
mbed_official 573:ad23fe03a082 591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mbed_official 573:ad23fe03a082 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 573:ad23fe03a082 593
mbed_official 573:ad23fe03a082 594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 573:ad23fe03a082 595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 573:ad23fe03a082 596
mbed_official 573:ad23fe03a082 597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 573:ad23fe03a082 598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 573:ad23fe03a082 599
mbed_official 573:ad23fe03a082 600 /* SCB Configuration Control Register Definitions */
mbed_official 573:ad23fe03a082 601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
mbed_official 573:ad23fe03a082 602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
mbed_official 573:ad23fe03a082 603
mbed_official 573:ad23fe03a082 604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
mbed_official 573:ad23fe03a082 605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
mbed_official 573:ad23fe03a082 606
mbed_official 573:ad23fe03a082 607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
mbed_official 573:ad23fe03a082 608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
mbed_official 573:ad23fe03a082 609
mbed_official 573:ad23fe03a082 610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mbed_official 573:ad23fe03a082 611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 573:ad23fe03a082 612
mbed_official 573:ad23fe03a082 613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
mbed_official 573:ad23fe03a082 614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mbed_official 573:ad23fe03a082 615
mbed_official 573:ad23fe03a082 616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
mbed_official 573:ad23fe03a082 617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mbed_official 573:ad23fe03a082 618
mbed_official 573:ad23fe03a082 619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 573:ad23fe03a082 620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 573:ad23fe03a082 621
mbed_official 573:ad23fe03a082 622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
mbed_official 573:ad23fe03a082 623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mbed_official 573:ad23fe03a082 624
mbed_official 573:ad23fe03a082 625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mbed_official 573:ad23fe03a082 626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
mbed_official 573:ad23fe03a082 627
mbed_official 573:ad23fe03a082 628 /* SCB System Handler Control and State Register Definitions */
mbed_official 573:ad23fe03a082 629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
mbed_official 573:ad23fe03a082 630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mbed_official 573:ad23fe03a082 631
mbed_official 573:ad23fe03a082 632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
mbed_official 573:ad23fe03a082 633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mbed_official 573:ad23fe03a082 634
mbed_official 573:ad23fe03a082 635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
mbed_official 573:ad23fe03a082 636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mbed_official 573:ad23fe03a082 637
mbed_official 573:ad23fe03a082 638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 573:ad23fe03a082 639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 573:ad23fe03a082 640
mbed_official 573:ad23fe03a082 641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
mbed_official 573:ad23fe03a082 642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mbed_official 573:ad23fe03a082 643
mbed_official 573:ad23fe03a082 644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
mbed_official 573:ad23fe03a082 645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mbed_official 573:ad23fe03a082 646
mbed_official 573:ad23fe03a082 647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
mbed_official 573:ad23fe03a082 648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mbed_official 573:ad23fe03a082 649
mbed_official 573:ad23fe03a082 650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
mbed_official 573:ad23fe03a082 651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mbed_official 573:ad23fe03a082 652
mbed_official 573:ad23fe03a082 653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
mbed_official 573:ad23fe03a082 654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mbed_official 573:ad23fe03a082 655
mbed_official 573:ad23fe03a082 656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
mbed_official 573:ad23fe03a082 657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mbed_official 573:ad23fe03a082 658
mbed_official 573:ad23fe03a082 659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
mbed_official 573:ad23fe03a082 660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mbed_official 573:ad23fe03a082 661
mbed_official 573:ad23fe03a082 662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
mbed_official 573:ad23fe03a082 663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mbed_official 573:ad23fe03a082 664
mbed_official 573:ad23fe03a082 665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
mbed_official 573:ad23fe03a082 666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mbed_official 573:ad23fe03a082 667
mbed_official 573:ad23fe03a082 668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mbed_official 573:ad23fe03a082 669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
mbed_official 573:ad23fe03a082 670
mbed_official 573:ad23fe03a082 671 /* SCB Configurable Fault Status Registers Definitions */
mbed_official 573:ad23fe03a082 672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
mbed_official 573:ad23fe03a082 673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mbed_official 573:ad23fe03a082 674
mbed_official 573:ad23fe03a082 675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
mbed_official 573:ad23fe03a082 676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mbed_official 573:ad23fe03a082 677
mbed_official 573:ad23fe03a082 678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mbed_official 573:ad23fe03a082 679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mbed_official 573:ad23fe03a082 680
mbed_official 573:ad23fe03a082 681 /* SCB Hard Fault Status Registers Definitions */
mbed_official 573:ad23fe03a082 682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
mbed_official 573:ad23fe03a082 683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mbed_official 573:ad23fe03a082 684
mbed_official 573:ad23fe03a082 685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
mbed_official 573:ad23fe03a082 686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mbed_official 573:ad23fe03a082 687
mbed_official 573:ad23fe03a082 688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
mbed_official 573:ad23fe03a082 689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mbed_official 573:ad23fe03a082 690
mbed_official 573:ad23fe03a082 691 /* SCB Debug Fault Status Register Definitions */
mbed_official 573:ad23fe03a082 692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
mbed_official 573:ad23fe03a082 693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mbed_official 573:ad23fe03a082 694
mbed_official 573:ad23fe03a082 695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
mbed_official 573:ad23fe03a082 696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mbed_official 573:ad23fe03a082 697
mbed_official 573:ad23fe03a082 698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
mbed_official 573:ad23fe03a082 699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mbed_official 573:ad23fe03a082 700
mbed_official 573:ad23fe03a082 701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
mbed_official 573:ad23fe03a082 702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mbed_official 573:ad23fe03a082 703
mbed_official 573:ad23fe03a082 704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mbed_official 573:ad23fe03a082 705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
mbed_official 573:ad23fe03a082 706
mbed_official 573:ad23fe03a082 707 /* Cache Level ID register */
mbed_official 573:ad23fe03a082 708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
mbed_official 573:ad23fe03a082 709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
mbed_official 573:ad23fe03a082 710
mbed_official 573:ad23fe03a082 711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
mbed_official 573:ad23fe03a082 712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
mbed_official 573:ad23fe03a082 713
mbed_official 573:ad23fe03a082 714 /* Cache Type register */
mbed_official 573:ad23fe03a082 715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
mbed_official 573:ad23fe03a082 716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
mbed_official 573:ad23fe03a082 717
mbed_official 573:ad23fe03a082 718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
mbed_official 573:ad23fe03a082 719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
mbed_official 573:ad23fe03a082 720
mbed_official 573:ad23fe03a082 721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
mbed_official 573:ad23fe03a082 722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
mbed_official 573:ad23fe03a082 723
mbed_official 573:ad23fe03a082 724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
mbed_official 573:ad23fe03a082 725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
mbed_official 573:ad23fe03a082 726
mbed_official 573:ad23fe03a082 727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
mbed_official 573:ad23fe03a082 728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
mbed_official 573:ad23fe03a082 729
mbed_official 573:ad23fe03a082 730 /* Cache Size ID Register */
mbed_official 573:ad23fe03a082 731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
mbed_official 573:ad23fe03a082 732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
mbed_official 573:ad23fe03a082 733
mbed_official 573:ad23fe03a082 734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
mbed_official 573:ad23fe03a082 735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
mbed_official 573:ad23fe03a082 736
mbed_official 573:ad23fe03a082 737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
mbed_official 573:ad23fe03a082 738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
mbed_official 573:ad23fe03a082 739
mbed_official 573:ad23fe03a082 740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
mbed_official 573:ad23fe03a082 741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
mbed_official 573:ad23fe03a082 742
mbed_official 573:ad23fe03a082 743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
mbed_official 573:ad23fe03a082 744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
mbed_official 573:ad23fe03a082 745
mbed_official 573:ad23fe03a082 746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
mbed_official 573:ad23fe03a082 747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
mbed_official 573:ad23fe03a082 748
mbed_official 573:ad23fe03a082 749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
mbed_official 573:ad23fe03a082 750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
mbed_official 573:ad23fe03a082 751
mbed_official 573:ad23fe03a082 752 /* Cache Size Selection Register */
mbed_official 573:ad23fe03a082 753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
mbed_official 573:ad23fe03a082 754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
mbed_official 573:ad23fe03a082 755
mbed_official 573:ad23fe03a082 756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
mbed_official 573:ad23fe03a082 757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
mbed_official 573:ad23fe03a082 758
mbed_official 573:ad23fe03a082 759 /* SCB Software Triggered Interrupt Register */
mbed_official 573:ad23fe03a082 760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
mbed_official 573:ad23fe03a082 761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
mbed_official 573:ad23fe03a082 762
mbed_official 573:ad23fe03a082 763 /* Instruction Tightly-Coupled Memory Control Register*/
mbed_official 573:ad23fe03a082 764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
mbed_official 573:ad23fe03a082 765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
mbed_official 573:ad23fe03a082 766
mbed_official 573:ad23fe03a082 767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
mbed_official 573:ad23fe03a082 768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
mbed_official 573:ad23fe03a082 769
mbed_official 573:ad23fe03a082 770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
mbed_official 573:ad23fe03a082 771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
mbed_official 573:ad23fe03a082 772
mbed_official 573:ad23fe03a082 773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
mbed_official 573:ad23fe03a082 774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
mbed_official 573:ad23fe03a082 775
mbed_official 573:ad23fe03a082 776 /* Data Tightly-Coupled Memory Control Registers */
mbed_official 573:ad23fe03a082 777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
mbed_official 573:ad23fe03a082 778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
mbed_official 573:ad23fe03a082 779
mbed_official 573:ad23fe03a082 780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
mbed_official 573:ad23fe03a082 781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
mbed_official 573:ad23fe03a082 782
mbed_official 573:ad23fe03a082 783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
mbed_official 573:ad23fe03a082 784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
mbed_official 573:ad23fe03a082 785
mbed_official 573:ad23fe03a082 786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
mbed_official 573:ad23fe03a082 787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
mbed_official 573:ad23fe03a082 788
mbed_official 573:ad23fe03a082 789 /* AHBP Control Register */
mbed_official 573:ad23fe03a082 790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
mbed_official 573:ad23fe03a082 791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
mbed_official 573:ad23fe03a082 792
mbed_official 573:ad23fe03a082 793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
mbed_official 573:ad23fe03a082 794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
mbed_official 573:ad23fe03a082 795
mbed_official 573:ad23fe03a082 796 /* L1 Cache Control Register */
mbed_official 573:ad23fe03a082 797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
mbed_official 573:ad23fe03a082 798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
mbed_official 573:ad23fe03a082 799
mbed_official 573:ad23fe03a082 800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
mbed_official 573:ad23fe03a082 801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
mbed_official 573:ad23fe03a082 802
mbed_official 573:ad23fe03a082 803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
mbed_official 573:ad23fe03a082 804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
mbed_official 573:ad23fe03a082 805
mbed_official 573:ad23fe03a082 806 /* AHBS control register */
mbed_official 573:ad23fe03a082 807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
mbed_official 573:ad23fe03a082 808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
mbed_official 573:ad23fe03a082 809
mbed_official 573:ad23fe03a082 810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
mbed_official 573:ad23fe03a082 811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
mbed_official 573:ad23fe03a082 812
mbed_official 573:ad23fe03a082 813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
mbed_official 573:ad23fe03a082 814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
mbed_official 573:ad23fe03a082 815
mbed_official 573:ad23fe03a082 816 /* Auxiliary Bus Fault Status Register */
mbed_official 573:ad23fe03a082 817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
mbed_official 573:ad23fe03a082 818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
mbed_official 573:ad23fe03a082 819
mbed_official 573:ad23fe03a082 820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
mbed_official 573:ad23fe03a082 821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
mbed_official 573:ad23fe03a082 822
mbed_official 573:ad23fe03a082 823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
mbed_official 573:ad23fe03a082 824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
mbed_official 573:ad23fe03a082 825
mbed_official 573:ad23fe03a082 826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
mbed_official 573:ad23fe03a082 827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
mbed_official 573:ad23fe03a082 828
mbed_official 573:ad23fe03a082 829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
mbed_official 573:ad23fe03a082 830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
mbed_official 573:ad23fe03a082 831
mbed_official 573:ad23fe03a082 832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
mbed_official 573:ad23fe03a082 833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
mbed_official 573:ad23fe03a082 834
mbed_official 573:ad23fe03a082 835 /*@} end of group CMSIS_SCB */
mbed_official 573:ad23fe03a082 836
mbed_official 573:ad23fe03a082 837
mbed_official 573:ad23fe03a082 838 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mbed_official 573:ad23fe03a082 840 \brief Type definitions for the System Control and ID Register not in the SCB
mbed_official 573:ad23fe03a082 841 @{
mbed_official 573:ad23fe03a082 842 */
mbed_official 573:ad23fe03a082 843
mbed_official 573:ad23fe03a082 844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official 573:ad23fe03a082 845 */
mbed_official 573:ad23fe03a082 846 typedef struct
mbed_official 573:ad23fe03a082 847 {
mbed_official 573:ad23fe03a082 848 uint32_t RESERVED0[1];
mbed_official 573:ad23fe03a082 849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mbed_official 573:ad23fe03a082 850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
mbed_official 573:ad23fe03a082 851 } SCnSCB_Type;
mbed_official 573:ad23fe03a082 852
mbed_official 573:ad23fe03a082 853 /* Interrupt Controller Type Register Definitions */
mbed_official 573:ad23fe03a082 854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mbed_official 573:ad23fe03a082 855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
mbed_official 573:ad23fe03a082 856
mbed_official 573:ad23fe03a082 857 /* Auxiliary Control Register Definitions */
mbed_official 573:ad23fe03a082 858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
mbed_official 573:ad23fe03a082 859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
mbed_official 573:ad23fe03a082 860
mbed_official 573:ad23fe03a082 861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
mbed_official 573:ad23fe03a082 862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
mbed_official 573:ad23fe03a082 863
mbed_official 573:ad23fe03a082 864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
mbed_official 573:ad23fe03a082 865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
mbed_official 573:ad23fe03a082 866
mbed_official 573:ad23fe03a082 867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
mbed_official 573:ad23fe03a082 868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
mbed_official 573:ad23fe03a082 869
mbed_official 573:ad23fe03a082 870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
mbed_official 573:ad23fe03a082 871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
mbed_official 573:ad23fe03a082 872
mbed_official 573:ad23fe03a082 873 /*@} end of group CMSIS_SCnotSCB */
mbed_official 573:ad23fe03a082 874
mbed_official 573:ad23fe03a082 875
mbed_official 573:ad23fe03a082 876 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 573:ad23fe03a082 878 \brief Type definitions for the System Timer Registers.
mbed_official 573:ad23fe03a082 879 @{
mbed_official 573:ad23fe03a082 880 */
mbed_official 573:ad23fe03a082 881
mbed_official 573:ad23fe03a082 882 /** \brief Structure type to access the System Timer (SysTick).
mbed_official 573:ad23fe03a082 883 */
mbed_official 573:ad23fe03a082 884 typedef struct
mbed_official 573:ad23fe03a082 885 {
mbed_official 573:ad23fe03a082 886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 573:ad23fe03a082 887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 573:ad23fe03a082 888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 573:ad23fe03a082 889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 573:ad23fe03a082 890 } SysTick_Type;
mbed_official 573:ad23fe03a082 891
mbed_official 573:ad23fe03a082 892 /* SysTick Control / Status Register Definitions */
mbed_official 573:ad23fe03a082 893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 573:ad23fe03a082 894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 573:ad23fe03a082 895
mbed_official 573:ad23fe03a082 896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 573:ad23fe03a082 897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 573:ad23fe03a082 898
mbed_official 573:ad23fe03a082 899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mbed_official 573:ad23fe03a082 900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 573:ad23fe03a082 901
mbed_official 573:ad23fe03a082 902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbed_official 573:ad23fe03a082 903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 573:ad23fe03a082 904
mbed_official 573:ad23fe03a082 905 /* SysTick Reload Register Definitions */
mbed_official 573:ad23fe03a082 906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbed_official 573:ad23fe03a082 907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 573:ad23fe03a082 908
mbed_official 573:ad23fe03a082 909 /* SysTick Current Register Definitions */
mbed_official 573:ad23fe03a082 910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbed_official 573:ad23fe03a082 911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 573:ad23fe03a082 912
mbed_official 573:ad23fe03a082 913 /* SysTick Calibration Register Definitions */
mbed_official 573:ad23fe03a082 914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mbed_official 573:ad23fe03a082 915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 573:ad23fe03a082 916
mbed_official 573:ad23fe03a082 917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mbed_official 573:ad23fe03a082 918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 573:ad23fe03a082 919
mbed_official 573:ad23fe03a082 920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbed_official 573:ad23fe03a082 921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 573:ad23fe03a082 922
mbed_official 573:ad23fe03a082 923 /*@} end of group CMSIS_SysTick */
mbed_official 573:ad23fe03a082 924
mbed_official 573:ad23fe03a082 925
mbed_official 573:ad23fe03a082 926 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mbed_official 573:ad23fe03a082 928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mbed_official 573:ad23fe03a082 929 @{
mbed_official 573:ad23fe03a082 930 */
mbed_official 573:ad23fe03a082 931
mbed_official 573:ad23fe03a082 932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mbed_official 573:ad23fe03a082 933 */
mbed_official 573:ad23fe03a082 934 typedef struct
mbed_official 573:ad23fe03a082 935 {
mbed_official 573:ad23fe03a082 936 __O union
mbed_official 573:ad23fe03a082 937 {
mbed_official 573:ad23fe03a082 938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mbed_official 573:ad23fe03a082 939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mbed_official 573:ad23fe03a082 940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mbed_official 573:ad23fe03a082 941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mbed_official 573:ad23fe03a082 942 uint32_t RESERVED0[864];
mbed_official 573:ad23fe03a082 943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mbed_official 573:ad23fe03a082 944 uint32_t RESERVED1[15];
mbed_official 573:ad23fe03a082 945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mbed_official 573:ad23fe03a082 946 uint32_t RESERVED2[15];
mbed_official 573:ad23fe03a082 947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mbed_official 573:ad23fe03a082 948 uint32_t RESERVED3[29];
mbed_official 573:ad23fe03a082 949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mbed_official 573:ad23fe03a082 950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mbed_official 573:ad23fe03a082 951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mbed_official 573:ad23fe03a082 952 uint32_t RESERVED4[43];
mbed_official 573:ad23fe03a082 953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mbed_official 573:ad23fe03a082 954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mbed_official 573:ad23fe03a082 955 uint32_t RESERVED5[6];
mbed_official 573:ad23fe03a082 956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mbed_official 573:ad23fe03a082 957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mbed_official 573:ad23fe03a082 958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mbed_official 573:ad23fe03a082 959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mbed_official 573:ad23fe03a082 960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mbed_official 573:ad23fe03a082 961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mbed_official 573:ad23fe03a082 962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mbed_official 573:ad23fe03a082 963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mbed_official 573:ad23fe03a082 964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mbed_official 573:ad23fe03a082 965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mbed_official 573:ad23fe03a082 966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mbed_official 573:ad23fe03a082 967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mbed_official 573:ad23fe03a082 968 } ITM_Type;
mbed_official 573:ad23fe03a082 969
mbed_official 573:ad23fe03a082 970 /* ITM Trace Privilege Register Definitions */
mbed_official 573:ad23fe03a082 971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mbed_official 573:ad23fe03a082 972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
mbed_official 573:ad23fe03a082 973
mbed_official 573:ad23fe03a082 974 /* ITM Trace Control Register Definitions */
mbed_official 573:ad23fe03a082 975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
mbed_official 573:ad23fe03a082 976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mbed_official 573:ad23fe03a082 977
mbed_official 573:ad23fe03a082 978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
mbed_official 573:ad23fe03a082 979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
mbed_official 573:ad23fe03a082 980
mbed_official 573:ad23fe03a082 981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
mbed_official 573:ad23fe03a082 982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mbed_official 573:ad23fe03a082 983
mbed_official 573:ad23fe03a082 984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
mbed_official 573:ad23fe03a082 985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
mbed_official 573:ad23fe03a082 986
mbed_official 573:ad23fe03a082 987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
mbed_official 573:ad23fe03a082 988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mbed_official 573:ad23fe03a082 989
mbed_official 573:ad23fe03a082 990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
mbed_official 573:ad23fe03a082 991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mbed_official 573:ad23fe03a082 992
mbed_official 573:ad23fe03a082 993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
mbed_official 573:ad23fe03a082 994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mbed_official 573:ad23fe03a082 995
mbed_official 573:ad23fe03a082 996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
mbed_official 573:ad23fe03a082 997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mbed_official 573:ad23fe03a082 998
mbed_official 573:ad23fe03a082 999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mbed_official 573:ad23fe03a082 1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
mbed_official 573:ad23fe03a082 1001
mbed_official 573:ad23fe03a082 1002 /* ITM Integration Write Register Definitions */
mbed_official 573:ad23fe03a082 1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mbed_official 573:ad23fe03a082 1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
mbed_official 573:ad23fe03a082 1005
mbed_official 573:ad23fe03a082 1006 /* ITM Integration Read Register Definitions */
mbed_official 573:ad23fe03a082 1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mbed_official 573:ad23fe03a082 1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
mbed_official 573:ad23fe03a082 1009
mbed_official 573:ad23fe03a082 1010 /* ITM Integration Mode Control Register Definitions */
mbed_official 573:ad23fe03a082 1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mbed_official 573:ad23fe03a082 1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
mbed_official 573:ad23fe03a082 1013
mbed_official 573:ad23fe03a082 1014 /* ITM Lock Status Register Definitions */
mbed_official 573:ad23fe03a082 1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
mbed_official 573:ad23fe03a082 1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mbed_official 573:ad23fe03a082 1017
mbed_official 573:ad23fe03a082 1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
mbed_official 573:ad23fe03a082 1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mbed_official 573:ad23fe03a082 1020
mbed_official 573:ad23fe03a082 1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mbed_official 573:ad23fe03a082 1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
mbed_official 573:ad23fe03a082 1023
mbed_official 573:ad23fe03a082 1024 /*@}*/ /* end of group CMSIS_ITM */
mbed_official 573:ad23fe03a082 1025
mbed_official 573:ad23fe03a082 1026
mbed_official 573:ad23fe03a082 1027 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mbed_official 573:ad23fe03a082 1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official 573:ad23fe03a082 1030 @{
mbed_official 573:ad23fe03a082 1031 */
mbed_official 573:ad23fe03a082 1032
mbed_official 573:ad23fe03a082 1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official 573:ad23fe03a082 1034 */
mbed_official 573:ad23fe03a082 1035 typedef struct
mbed_official 573:ad23fe03a082 1036 {
mbed_official 573:ad23fe03a082 1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mbed_official 573:ad23fe03a082 1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mbed_official 573:ad23fe03a082 1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mbed_official 573:ad23fe03a082 1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mbed_official 573:ad23fe03a082 1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mbed_official 573:ad23fe03a082 1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mbed_official 573:ad23fe03a082 1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mbed_official 573:ad23fe03a082 1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mbed_official 573:ad23fe03a082 1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mbed_official 573:ad23fe03a082 1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
mbed_official 573:ad23fe03a082 1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mbed_official 573:ad23fe03a082 1048 uint32_t RESERVED0[1];
mbed_official 573:ad23fe03a082 1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mbed_official 573:ad23fe03a082 1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
mbed_official 573:ad23fe03a082 1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mbed_official 573:ad23fe03a082 1052 uint32_t RESERVED1[1];
mbed_official 573:ad23fe03a082 1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mbed_official 573:ad23fe03a082 1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
mbed_official 573:ad23fe03a082 1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mbed_official 573:ad23fe03a082 1056 uint32_t RESERVED2[1];
mbed_official 573:ad23fe03a082 1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mbed_official 573:ad23fe03a082 1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
mbed_official 573:ad23fe03a082 1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mbed_official 573:ad23fe03a082 1060 uint32_t RESERVED3[981];
mbed_official 573:ad23fe03a082 1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
mbed_official 573:ad23fe03a082 1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
mbed_official 573:ad23fe03a082 1063 } DWT_Type;
mbed_official 573:ad23fe03a082 1064
mbed_official 573:ad23fe03a082 1065 /* DWT Control Register Definitions */
mbed_official 573:ad23fe03a082 1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
mbed_official 573:ad23fe03a082 1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mbed_official 573:ad23fe03a082 1068
mbed_official 573:ad23fe03a082 1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
mbed_official 573:ad23fe03a082 1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mbed_official 573:ad23fe03a082 1071
mbed_official 573:ad23fe03a082 1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
mbed_official 573:ad23fe03a082 1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mbed_official 573:ad23fe03a082 1074
mbed_official 573:ad23fe03a082 1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
mbed_official 573:ad23fe03a082 1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mbed_official 573:ad23fe03a082 1077
mbed_official 573:ad23fe03a082 1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
mbed_official 573:ad23fe03a082 1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mbed_official 573:ad23fe03a082 1080
mbed_official 573:ad23fe03a082 1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
mbed_official 573:ad23fe03a082 1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mbed_official 573:ad23fe03a082 1083
mbed_official 573:ad23fe03a082 1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
mbed_official 573:ad23fe03a082 1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mbed_official 573:ad23fe03a082 1086
mbed_official 573:ad23fe03a082 1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
mbed_official 573:ad23fe03a082 1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mbed_official 573:ad23fe03a082 1089
mbed_official 573:ad23fe03a082 1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
mbed_official 573:ad23fe03a082 1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mbed_official 573:ad23fe03a082 1092
mbed_official 573:ad23fe03a082 1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
mbed_official 573:ad23fe03a082 1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mbed_official 573:ad23fe03a082 1095
mbed_official 573:ad23fe03a082 1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
mbed_official 573:ad23fe03a082 1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mbed_official 573:ad23fe03a082 1098
mbed_official 573:ad23fe03a082 1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
mbed_official 573:ad23fe03a082 1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mbed_official 573:ad23fe03a082 1101
mbed_official 573:ad23fe03a082 1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
mbed_official 573:ad23fe03a082 1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mbed_official 573:ad23fe03a082 1104
mbed_official 573:ad23fe03a082 1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
mbed_official 573:ad23fe03a082 1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mbed_official 573:ad23fe03a082 1107
mbed_official 573:ad23fe03a082 1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
mbed_official 573:ad23fe03a082 1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mbed_official 573:ad23fe03a082 1110
mbed_official 573:ad23fe03a082 1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
mbed_official 573:ad23fe03a082 1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mbed_official 573:ad23fe03a082 1113
mbed_official 573:ad23fe03a082 1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
mbed_official 573:ad23fe03a082 1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mbed_official 573:ad23fe03a082 1116
mbed_official 573:ad23fe03a082 1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mbed_official 573:ad23fe03a082 1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
mbed_official 573:ad23fe03a082 1119
mbed_official 573:ad23fe03a082 1120 /* DWT CPI Count Register Definitions */
mbed_official 573:ad23fe03a082 1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mbed_official 573:ad23fe03a082 1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
mbed_official 573:ad23fe03a082 1123
mbed_official 573:ad23fe03a082 1124 /* DWT Exception Overhead Count Register Definitions */
mbed_official 573:ad23fe03a082 1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mbed_official 573:ad23fe03a082 1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
mbed_official 573:ad23fe03a082 1127
mbed_official 573:ad23fe03a082 1128 /* DWT Sleep Count Register Definitions */
mbed_official 573:ad23fe03a082 1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mbed_official 573:ad23fe03a082 1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mbed_official 573:ad23fe03a082 1131
mbed_official 573:ad23fe03a082 1132 /* DWT LSU Count Register Definitions */
mbed_official 573:ad23fe03a082 1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mbed_official 573:ad23fe03a082 1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
mbed_official 573:ad23fe03a082 1135
mbed_official 573:ad23fe03a082 1136 /* DWT Folded-instruction Count Register Definitions */
mbed_official 573:ad23fe03a082 1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mbed_official 573:ad23fe03a082 1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
mbed_official 573:ad23fe03a082 1139
mbed_official 573:ad23fe03a082 1140 /* DWT Comparator Mask Register Definitions */
mbed_official 573:ad23fe03a082 1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mbed_official 573:ad23fe03a082 1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
mbed_official 573:ad23fe03a082 1143
mbed_official 573:ad23fe03a082 1144 /* DWT Comparator Function Register Definitions */
mbed_official 573:ad23fe03a082 1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
mbed_official 573:ad23fe03a082 1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mbed_official 573:ad23fe03a082 1147
mbed_official 573:ad23fe03a082 1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
mbed_official 573:ad23fe03a082 1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
mbed_official 573:ad23fe03a082 1150
mbed_official 573:ad23fe03a082 1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
mbed_official 573:ad23fe03a082 1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
mbed_official 573:ad23fe03a082 1153
mbed_official 573:ad23fe03a082 1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
mbed_official 573:ad23fe03a082 1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mbed_official 573:ad23fe03a082 1156
mbed_official 573:ad23fe03a082 1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
mbed_official 573:ad23fe03a082 1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
mbed_official 573:ad23fe03a082 1159
mbed_official 573:ad23fe03a082 1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
mbed_official 573:ad23fe03a082 1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
mbed_official 573:ad23fe03a082 1162
mbed_official 573:ad23fe03a082 1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
mbed_official 573:ad23fe03a082 1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
mbed_official 573:ad23fe03a082 1165
mbed_official 573:ad23fe03a082 1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
mbed_official 573:ad23fe03a082 1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
mbed_official 573:ad23fe03a082 1168
mbed_official 573:ad23fe03a082 1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mbed_official 573:ad23fe03a082 1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
mbed_official 573:ad23fe03a082 1171
mbed_official 573:ad23fe03a082 1172 /*@}*/ /* end of group CMSIS_DWT */
mbed_official 573:ad23fe03a082 1173
mbed_official 573:ad23fe03a082 1174
mbed_official 573:ad23fe03a082 1175 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mbed_official 573:ad23fe03a082 1177 \brief Type definitions for the Trace Port Interface (TPI)
mbed_official 573:ad23fe03a082 1178 @{
mbed_official 573:ad23fe03a082 1179 */
mbed_official 573:ad23fe03a082 1180
mbed_official 573:ad23fe03a082 1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official 573:ad23fe03a082 1182 */
mbed_official 573:ad23fe03a082 1183 typedef struct
mbed_official 573:ad23fe03a082 1184 {
mbed_official 573:ad23fe03a082 1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mbed_official 573:ad23fe03a082 1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mbed_official 573:ad23fe03a082 1187 uint32_t RESERVED0[2];
mbed_official 573:ad23fe03a082 1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mbed_official 573:ad23fe03a082 1189 uint32_t RESERVED1[55];
mbed_official 573:ad23fe03a082 1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mbed_official 573:ad23fe03a082 1191 uint32_t RESERVED2[131];
mbed_official 573:ad23fe03a082 1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mbed_official 573:ad23fe03a082 1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mbed_official 573:ad23fe03a082 1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mbed_official 573:ad23fe03a082 1195 uint32_t RESERVED3[759];
mbed_official 573:ad23fe03a082 1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mbed_official 573:ad23fe03a082 1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mbed_official 573:ad23fe03a082 1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mbed_official 573:ad23fe03a082 1199 uint32_t RESERVED4[1];
mbed_official 573:ad23fe03a082 1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mbed_official 573:ad23fe03a082 1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mbed_official 573:ad23fe03a082 1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mbed_official 573:ad23fe03a082 1203 uint32_t RESERVED5[39];
mbed_official 573:ad23fe03a082 1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mbed_official 573:ad23fe03a082 1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mbed_official 573:ad23fe03a082 1206 uint32_t RESERVED7[8];
mbed_official 573:ad23fe03a082 1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mbed_official 573:ad23fe03a082 1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mbed_official 573:ad23fe03a082 1209 } TPI_Type;
mbed_official 573:ad23fe03a082 1210
mbed_official 573:ad23fe03a082 1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
mbed_official 573:ad23fe03a082 1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mbed_official 573:ad23fe03a082 1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
mbed_official 573:ad23fe03a082 1214
mbed_official 573:ad23fe03a082 1215 /* TPI Selected Pin Protocol Register Definitions */
mbed_official 573:ad23fe03a082 1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mbed_official 573:ad23fe03a082 1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
mbed_official 573:ad23fe03a082 1218
mbed_official 573:ad23fe03a082 1219 /* TPI Formatter and Flush Status Register Definitions */
mbed_official 573:ad23fe03a082 1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
mbed_official 573:ad23fe03a082 1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mbed_official 573:ad23fe03a082 1222
mbed_official 573:ad23fe03a082 1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
mbed_official 573:ad23fe03a082 1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mbed_official 573:ad23fe03a082 1225
mbed_official 573:ad23fe03a082 1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
mbed_official 573:ad23fe03a082 1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mbed_official 573:ad23fe03a082 1228
mbed_official 573:ad23fe03a082 1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mbed_official 573:ad23fe03a082 1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
mbed_official 573:ad23fe03a082 1231
mbed_official 573:ad23fe03a082 1232 /* TPI Formatter and Flush Control Register Definitions */
mbed_official 573:ad23fe03a082 1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
mbed_official 573:ad23fe03a082 1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mbed_official 573:ad23fe03a082 1235
mbed_official 573:ad23fe03a082 1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
mbed_official 573:ad23fe03a082 1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mbed_official 573:ad23fe03a082 1238
mbed_official 573:ad23fe03a082 1239 /* TPI TRIGGER Register Definitions */
mbed_official 573:ad23fe03a082 1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mbed_official 573:ad23fe03a082 1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
mbed_official 573:ad23fe03a082 1242
mbed_official 573:ad23fe03a082 1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mbed_official 573:ad23fe03a082 1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
mbed_official 573:ad23fe03a082 1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mbed_official 573:ad23fe03a082 1246
mbed_official 573:ad23fe03a082 1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
mbed_official 573:ad23fe03a082 1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mbed_official 573:ad23fe03a082 1249
mbed_official 573:ad23fe03a082 1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
mbed_official 573:ad23fe03a082 1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mbed_official 573:ad23fe03a082 1252
mbed_official 573:ad23fe03a082 1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
mbed_official 573:ad23fe03a082 1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mbed_official 573:ad23fe03a082 1255
mbed_official 573:ad23fe03a082 1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
mbed_official 573:ad23fe03a082 1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mbed_official 573:ad23fe03a082 1258
mbed_official 573:ad23fe03a082 1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
mbed_official 573:ad23fe03a082 1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mbed_official 573:ad23fe03a082 1261
mbed_official 573:ad23fe03a082 1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mbed_official 573:ad23fe03a082 1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
mbed_official 573:ad23fe03a082 1264
mbed_official 573:ad23fe03a082 1265 /* TPI ITATBCTR2 Register Definitions */
mbed_official 573:ad23fe03a082 1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mbed_official 573:ad23fe03a082 1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
mbed_official 573:ad23fe03a082 1268
mbed_official 573:ad23fe03a082 1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mbed_official 573:ad23fe03a082 1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
mbed_official 573:ad23fe03a082 1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mbed_official 573:ad23fe03a082 1272
mbed_official 573:ad23fe03a082 1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
mbed_official 573:ad23fe03a082 1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mbed_official 573:ad23fe03a082 1275
mbed_official 573:ad23fe03a082 1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
mbed_official 573:ad23fe03a082 1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mbed_official 573:ad23fe03a082 1278
mbed_official 573:ad23fe03a082 1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
mbed_official 573:ad23fe03a082 1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mbed_official 573:ad23fe03a082 1281
mbed_official 573:ad23fe03a082 1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
mbed_official 573:ad23fe03a082 1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mbed_official 573:ad23fe03a082 1284
mbed_official 573:ad23fe03a082 1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
mbed_official 573:ad23fe03a082 1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mbed_official 573:ad23fe03a082 1287
mbed_official 573:ad23fe03a082 1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mbed_official 573:ad23fe03a082 1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
mbed_official 573:ad23fe03a082 1290
mbed_official 573:ad23fe03a082 1291 /* TPI ITATBCTR0 Register Definitions */
mbed_official 573:ad23fe03a082 1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mbed_official 573:ad23fe03a082 1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
mbed_official 573:ad23fe03a082 1294
mbed_official 573:ad23fe03a082 1295 /* TPI Integration Mode Control Register Definitions */
mbed_official 573:ad23fe03a082 1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mbed_official 573:ad23fe03a082 1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
mbed_official 573:ad23fe03a082 1298
mbed_official 573:ad23fe03a082 1299 /* TPI DEVID Register Definitions */
mbed_official 573:ad23fe03a082 1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
mbed_official 573:ad23fe03a082 1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mbed_official 573:ad23fe03a082 1302
mbed_official 573:ad23fe03a082 1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
mbed_official 573:ad23fe03a082 1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mbed_official 573:ad23fe03a082 1305
mbed_official 573:ad23fe03a082 1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
mbed_official 573:ad23fe03a082 1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mbed_official 573:ad23fe03a082 1308
mbed_official 573:ad23fe03a082 1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
mbed_official 573:ad23fe03a082 1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mbed_official 573:ad23fe03a082 1311
mbed_official 573:ad23fe03a082 1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
mbed_official 573:ad23fe03a082 1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mbed_official 573:ad23fe03a082 1314
mbed_official 573:ad23fe03a082 1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mbed_official 573:ad23fe03a082 1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
mbed_official 573:ad23fe03a082 1317
mbed_official 573:ad23fe03a082 1318 /* TPI DEVTYPE Register Definitions */
mbed_official 573:ad23fe03a082 1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
mbed_official 573:ad23fe03a082 1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mbed_official 573:ad23fe03a082 1321
mbed_official 573:ad23fe03a082 1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mbed_official 573:ad23fe03a082 1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
mbed_official 573:ad23fe03a082 1324
mbed_official 573:ad23fe03a082 1325 /*@}*/ /* end of group CMSIS_TPI */
mbed_official 573:ad23fe03a082 1326
mbed_official 573:ad23fe03a082 1327
mbed_official 573:ad23fe03a082 1328 #if (__MPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 1329 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official 573:ad23fe03a082 1331 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 573:ad23fe03a082 1332 @{
mbed_official 573:ad23fe03a082 1333 */
mbed_official 573:ad23fe03a082 1334
mbed_official 573:ad23fe03a082 1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 573:ad23fe03a082 1336 */
mbed_official 573:ad23fe03a082 1337 typedef struct
mbed_official 573:ad23fe03a082 1338 {
mbed_official 573:ad23fe03a082 1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbed_official 573:ad23fe03a082 1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbed_official 573:ad23fe03a082 1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mbed_official 573:ad23fe03a082 1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbed_official 573:ad23fe03a082 1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbed_official 573:ad23fe03a082 1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
mbed_official 573:ad23fe03a082 1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
mbed_official 573:ad23fe03a082 1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
mbed_official 573:ad23fe03a082 1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
mbed_official 573:ad23fe03a082 1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
mbed_official 573:ad23fe03a082 1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
mbed_official 573:ad23fe03a082 1350 } MPU_Type;
mbed_official 573:ad23fe03a082 1351
mbed_official 573:ad23fe03a082 1352 /* MPU Type Register */
mbed_official 573:ad23fe03a082 1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mbed_official 573:ad23fe03a082 1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 573:ad23fe03a082 1355
mbed_official 573:ad23fe03a082 1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mbed_official 573:ad23fe03a082 1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 573:ad23fe03a082 1358
mbed_official 573:ad23fe03a082 1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbed_official 573:ad23fe03a082 1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 573:ad23fe03a082 1361
mbed_official 573:ad23fe03a082 1362 /* MPU Control Register */
mbed_official 573:ad23fe03a082 1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 573:ad23fe03a082 1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 573:ad23fe03a082 1365
mbed_official 573:ad23fe03a082 1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mbed_official 573:ad23fe03a082 1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 573:ad23fe03a082 1368
mbed_official 573:ad23fe03a082 1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbed_official 573:ad23fe03a082 1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 573:ad23fe03a082 1371
mbed_official 573:ad23fe03a082 1372 /* MPU Region Number Register */
mbed_official 573:ad23fe03a082 1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbed_official 573:ad23fe03a082 1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 573:ad23fe03a082 1375
mbed_official 573:ad23fe03a082 1376 /* MPU Region Base Address Register */
mbed_official 573:ad23fe03a082 1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
mbed_official 573:ad23fe03a082 1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 573:ad23fe03a082 1379
mbed_official 573:ad23fe03a082 1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mbed_official 573:ad23fe03a082 1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbed_official 573:ad23fe03a082 1382
mbed_official 573:ad23fe03a082 1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbed_official 573:ad23fe03a082 1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mbed_official 573:ad23fe03a082 1385
mbed_official 573:ad23fe03a082 1386 /* MPU Region Attribute and Size Register */
mbed_official 573:ad23fe03a082 1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mbed_official 573:ad23fe03a082 1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbed_official 573:ad23fe03a082 1389
mbed_official 573:ad23fe03a082 1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mbed_official 573:ad23fe03a082 1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbed_official 573:ad23fe03a082 1392
mbed_official 573:ad23fe03a082 1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mbed_official 573:ad23fe03a082 1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbed_official 573:ad23fe03a082 1395
mbed_official 573:ad23fe03a082 1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mbed_official 573:ad23fe03a082 1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbed_official 573:ad23fe03a082 1398
mbed_official 573:ad23fe03a082 1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mbed_official 573:ad23fe03a082 1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbed_official 573:ad23fe03a082 1401
mbed_official 573:ad23fe03a082 1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mbed_official 573:ad23fe03a082 1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbed_official 573:ad23fe03a082 1404
mbed_official 573:ad23fe03a082 1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mbed_official 573:ad23fe03a082 1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbed_official 573:ad23fe03a082 1407
mbed_official 573:ad23fe03a082 1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mbed_official 573:ad23fe03a082 1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbed_official 573:ad23fe03a082 1410
mbed_official 573:ad23fe03a082 1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mbed_official 573:ad23fe03a082 1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbed_official 573:ad23fe03a082 1413
mbed_official 573:ad23fe03a082 1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbed_official 573:ad23fe03a082 1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mbed_official 573:ad23fe03a082 1416
mbed_official 573:ad23fe03a082 1417 /*@} end of group CMSIS_MPU */
mbed_official 573:ad23fe03a082 1418 #endif
mbed_official 573:ad23fe03a082 1419
mbed_official 573:ad23fe03a082 1420
mbed_official 573:ad23fe03a082 1421 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 1422 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
mbed_official 573:ad23fe03a082 1424 \brief Type definitions for the Floating Point Unit (FPU)
mbed_official 573:ad23fe03a082 1425 @{
mbed_official 573:ad23fe03a082 1426 */
mbed_official 573:ad23fe03a082 1427
mbed_official 573:ad23fe03a082 1428 /** \brief Structure type to access the Floating Point Unit (FPU).
mbed_official 573:ad23fe03a082 1429 */
mbed_official 573:ad23fe03a082 1430 typedef struct
mbed_official 573:ad23fe03a082 1431 {
mbed_official 573:ad23fe03a082 1432 uint32_t RESERVED0[1];
mbed_official 573:ad23fe03a082 1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
mbed_official 573:ad23fe03a082 1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
mbed_official 573:ad23fe03a082 1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
mbed_official 573:ad23fe03a082 1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
mbed_official 573:ad23fe03a082 1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
mbed_official 573:ad23fe03a082 1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
mbed_official 573:ad23fe03a082 1439 } FPU_Type;
mbed_official 573:ad23fe03a082 1440
mbed_official 573:ad23fe03a082 1441 /* Floating-Point Context Control Register */
mbed_official 573:ad23fe03a082 1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
mbed_official 573:ad23fe03a082 1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
mbed_official 573:ad23fe03a082 1444
mbed_official 573:ad23fe03a082 1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
mbed_official 573:ad23fe03a082 1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
mbed_official 573:ad23fe03a082 1447
mbed_official 573:ad23fe03a082 1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
mbed_official 573:ad23fe03a082 1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
mbed_official 573:ad23fe03a082 1450
mbed_official 573:ad23fe03a082 1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
mbed_official 573:ad23fe03a082 1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
mbed_official 573:ad23fe03a082 1453
mbed_official 573:ad23fe03a082 1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
mbed_official 573:ad23fe03a082 1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
mbed_official 573:ad23fe03a082 1456
mbed_official 573:ad23fe03a082 1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
mbed_official 573:ad23fe03a082 1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
mbed_official 573:ad23fe03a082 1459
mbed_official 573:ad23fe03a082 1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
mbed_official 573:ad23fe03a082 1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
mbed_official 573:ad23fe03a082 1462
mbed_official 573:ad23fe03a082 1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
mbed_official 573:ad23fe03a082 1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
mbed_official 573:ad23fe03a082 1465
mbed_official 573:ad23fe03a082 1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
mbed_official 573:ad23fe03a082 1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
mbed_official 573:ad23fe03a082 1468
mbed_official 573:ad23fe03a082 1469 /* Floating-Point Context Address Register */
mbed_official 573:ad23fe03a082 1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
mbed_official 573:ad23fe03a082 1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
mbed_official 573:ad23fe03a082 1472
mbed_official 573:ad23fe03a082 1473 /* Floating-Point Default Status Control Register */
mbed_official 573:ad23fe03a082 1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
mbed_official 573:ad23fe03a082 1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
mbed_official 573:ad23fe03a082 1476
mbed_official 573:ad23fe03a082 1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
mbed_official 573:ad23fe03a082 1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
mbed_official 573:ad23fe03a082 1479
mbed_official 573:ad23fe03a082 1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
mbed_official 573:ad23fe03a082 1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
mbed_official 573:ad23fe03a082 1482
mbed_official 573:ad23fe03a082 1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
mbed_official 573:ad23fe03a082 1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
mbed_official 573:ad23fe03a082 1485
mbed_official 573:ad23fe03a082 1486 /* Media and FP Feature Register 0 */
mbed_official 573:ad23fe03a082 1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
mbed_official 573:ad23fe03a082 1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
mbed_official 573:ad23fe03a082 1489
mbed_official 573:ad23fe03a082 1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
mbed_official 573:ad23fe03a082 1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
mbed_official 573:ad23fe03a082 1492
mbed_official 573:ad23fe03a082 1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
mbed_official 573:ad23fe03a082 1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
mbed_official 573:ad23fe03a082 1495
mbed_official 573:ad23fe03a082 1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
mbed_official 573:ad23fe03a082 1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
mbed_official 573:ad23fe03a082 1498
mbed_official 573:ad23fe03a082 1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
mbed_official 573:ad23fe03a082 1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
mbed_official 573:ad23fe03a082 1501
mbed_official 573:ad23fe03a082 1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
mbed_official 573:ad23fe03a082 1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
mbed_official 573:ad23fe03a082 1504
mbed_official 573:ad23fe03a082 1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
mbed_official 573:ad23fe03a082 1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
mbed_official 573:ad23fe03a082 1507
mbed_official 573:ad23fe03a082 1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
mbed_official 573:ad23fe03a082 1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
mbed_official 573:ad23fe03a082 1510
mbed_official 573:ad23fe03a082 1511 /* Media and FP Feature Register 1 */
mbed_official 573:ad23fe03a082 1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
mbed_official 573:ad23fe03a082 1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
mbed_official 573:ad23fe03a082 1514
mbed_official 573:ad23fe03a082 1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
mbed_official 573:ad23fe03a082 1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
mbed_official 573:ad23fe03a082 1517
mbed_official 573:ad23fe03a082 1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
mbed_official 573:ad23fe03a082 1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
mbed_official 573:ad23fe03a082 1520
mbed_official 573:ad23fe03a082 1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
mbed_official 573:ad23fe03a082 1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
mbed_official 573:ad23fe03a082 1523
mbed_official 573:ad23fe03a082 1524 /* Media and FP Feature Register 2 */
mbed_official 573:ad23fe03a082 1525
mbed_official 573:ad23fe03a082 1526 /*@} end of group CMSIS_FPU */
mbed_official 573:ad23fe03a082 1527 #endif
mbed_official 573:ad23fe03a082 1528
mbed_official 573:ad23fe03a082 1529
mbed_official 573:ad23fe03a082 1530 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 573:ad23fe03a082 1532 \brief Type definitions for the Core Debug Registers
mbed_official 573:ad23fe03a082 1533 @{
mbed_official 573:ad23fe03a082 1534 */
mbed_official 573:ad23fe03a082 1535
mbed_official 573:ad23fe03a082 1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official 573:ad23fe03a082 1537 */
mbed_official 573:ad23fe03a082 1538 typedef struct
mbed_official 573:ad23fe03a082 1539 {
mbed_official 573:ad23fe03a082 1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mbed_official 573:ad23fe03a082 1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mbed_official 573:ad23fe03a082 1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mbed_official 573:ad23fe03a082 1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mbed_official 573:ad23fe03a082 1544 } CoreDebug_Type;
mbed_official 573:ad23fe03a082 1545
mbed_official 573:ad23fe03a082 1546 /* Debug Halting Control and Status Register */
mbed_official 573:ad23fe03a082 1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
mbed_official 573:ad23fe03a082 1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mbed_official 573:ad23fe03a082 1549
mbed_official 573:ad23fe03a082 1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
mbed_official 573:ad23fe03a082 1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mbed_official 573:ad23fe03a082 1552
mbed_official 573:ad23fe03a082 1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mbed_official 573:ad23fe03a082 1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mbed_official 573:ad23fe03a082 1555
mbed_official 573:ad23fe03a082 1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
mbed_official 573:ad23fe03a082 1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mbed_official 573:ad23fe03a082 1558
mbed_official 573:ad23fe03a082 1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
mbed_official 573:ad23fe03a082 1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mbed_official 573:ad23fe03a082 1561
mbed_official 573:ad23fe03a082 1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
mbed_official 573:ad23fe03a082 1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mbed_official 573:ad23fe03a082 1564
mbed_official 573:ad23fe03a082 1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
mbed_official 573:ad23fe03a082 1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mbed_official 573:ad23fe03a082 1567
mbed_official 573:ad23fe03a082 1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mbed_official 573:ad23fe03a082 1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mbed_official 573:ad23fe03a082 1570
mbed_official 573:ad23fe03a082 1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
mbed_official 573:ad23fe03a082 1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mbed_official 573:ad23fe03a082 1573
mbed_official 573:ad23fe03a082 1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
mbed_official 573:ad23fe03a082 1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mbed_official 573:ad23fe03a082 1576
mbed_official 573:ad23fe03a082 1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
mbed_official 573:ad23fe03a082 1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mbed_official 573:ad23fe03a082 1579
mbed_official 573:ad23fe03a082 1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mbed_official 573:ad23fe03a082 1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mbed_official 573:ad23fe03a082 1582
mbed_official 573:ad23fe03a082 1583 /* Debug Core Register Selector Register */
mbed_official 573:ad23fe03a082 1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
mbed_official 573:ad23fe03a082 1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mbed_official 573:ad23fe03a082 1586
mbed_official 573:ad23fe03a082 1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mbed_official 573:ad23fe03a082 1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
mbed_official 573:ad23fe03a082 1589
mbed_official 573:ad23fe03a082 1590 /* Debug Exception and Monitor Control Register */
mbed_official 573:ad23fe03a082 1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
mbed_official 573:ad23fe03a082 1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mbed_official 573:ad23fe03a082 1593
mbed_official 573:ad23fe03a082 1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
mbed_official 573:ad23fe03a082 1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mbed_official 573:ad23fe03a082 1596
mbed_official 573:ad23fe03a082 1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
mbed_official 573:ad23fe03a082 1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mbed_official 573:ad23fe03a082 1599
mbed_official 573:ad23fe03a082 1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
mbed_official 573:ad23fe03a082 1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mbed_official 573:ad23fe03a082 1602
mbed_official 573:ad23fe03a082 1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
mbed_official 573:ad23fe03a082 1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mbed_official 573:ad23fe03a082 1605
mbed_official 573:ad23fe03a082 1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
mbed_official 573:ad23fe03a082 1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mbed_official 573:ad23fe03a082 1608
mbed_official 573:ad23fe03a082 1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
mbed_official 573:ad23fe03a082 1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mbed_official 573:ad23fe03a082 1611
mbed_official 573:ad23fe03a082 1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
mbed_official 573:ad23fe03a082 1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mbed_official 573:ad23fe03a082 1614
mbed_official 573:ad23fe03a082 1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
mbed_official 573:ad23fe03a082 1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mbed_official 573:ad23fe03a082 1617
mbed_official 573:ad23fe03a082 1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
mbed_official 573:ad23fe03a082 1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mbed_official 573:ad23fe03a082 1620
mbed_official 573:ad23fe03a082 1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mbed_official 573:ad23fe03a082 1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mbed_official 573:ad23fe03a082 1623
mbed_official 573:ad23fe03a082 1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
mbed_official 573:ad23fe03a082 1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mbed_official 573:ad23fe03a082 1626
mbed_official 573:ad23fe03a082 1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mbed_official 573:ad23fe03a082 1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mbed_official 573:ad23fe03a082 1629
mbed_official 573:ad23fe03a082 1630 /*@} end of group CMSIS_CoreDebug */
mbed_official 573:ad23fe03a082 1631
mbed_official 573:ad23fe03a082 1632
mbed_official 573:ad23fe03a082 1633 /** \ingroup CMSIS_core_register
mbed_official 573:ad23fe03a082 1634 \defgroup CMSIS_core_base Core Definitions
mbed_official 573:ad23fe03a082 1635 \brief Definitions for base addresses, unions, and structures.
mbed_official 573:ad23fe03a082 1636 @{
mbed_official 573:ad23fe03a082 1637 */
mbed_official 573:ad23fe03a082 1638
mbed_official 573:ad23fe03a082 1639 /* Memory mapping of Cortex-M4 Hardware */
mbed_official 573:ad23fe03a082 1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 573:ad23fe03a082 1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mbed_official 573:ad23fe03a082 1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mbed_official 573:ad23fe03a082 1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mbed_official 573:ad23fe03a082 1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mbed_official 573:ad23fe03a082 1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 573:ad23fe03a082 1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 573:ad23fe03a082 1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 573:ad23fe03a082 1648
mbed_official 573:ad23fe03a082 1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mbed_official 573:ad23fe03a082 1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 573:ad23fe03a082 1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 573:ad23fe03a082 1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 573:ad23fe03a082 1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mbed_official 573:ad23fe03a082 1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mbed_official 573:ad23fe03a082 1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mbed_official 573:ad23fe03a082 1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
mbed_official 573:ad23fe03a082 1657
mbed_official 573:ad23fe03a082 1658 #if (__MPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbed_official 573:ad23fe03a082 1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 573:ad23fe03a082 1661 #endif
mbed_official 573:ad23fe03a082 1662
mbed_official 573:ad23fe03a082 1663 #if (__FPU_PRESENT == 1)
mbed_official 573:ad23fe03a082 1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
mbed_official 573:ad23fe03a082 1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
mbed_official 573:ad23fe03a082 1666 #endif
mbed_official 573:ad23fe03a082 1667
mbed_official 573:ad23fe03a082 1668 /*@} */
mbed_official 573:ad23fe03a082 1669
mbed_official 573:ad23fe03a082 1670
mbed_official 573:ad23fe03a082 1671
mbed_official 573:ad23fe03a082 1672 /*******************************************************************************
mbed_official 573:ad23fe03a082 1673 * Hardware Abstraction Layer
mbed_official 573:ad23fe03a082 1674 Core Function Interface contains:
mbed_official 573:ad23fe03a082 1675 - Core NVIC Functions
mbed_official 573:ad23fe03a082 1676 - Core SysTick Functions
mbed_official 573:ad23fe03a082 1677 - Core Debug Functions
mbed_official 573:ad23fe03a082 1678 - Core Register Access Functions
mbed_official 573:ad23fe03a082 1679 ******************************************************************************/
mbed_official 573:ad23fe03a082 1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 573:ad23fe03a082 1681 */
mbed_official 573:ad23fe03a082 1682
mbed_official 573:ad23fe03a082 1683
mbed_official 573:ad23fe03a082 1684
mbed_official 573:ad23fe03a082 1685 /* ########################## NVIC functions #################################### */
mbed_official 573:ad23fe03a082 1686 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 573:ad23fe03a082 1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 573:ad23fe03a082 1688 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 573:ad23fe03a082 1689 @{
mbed_official 573:ad23fe03a082 1690 */
mbed_official 573:ad23fe03a082 1691
mbed_official 573:ad23fe03a082 1692 /** \brief Set Priority Grouping
mbed_official 573:ad23fe03a082 1693
mbed_official 573:ad23fe03a082 1694 The function sets the priority grouping field using the required unlock sequence.
mbed_official 573:ad23fe03a082 1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mbed_official 573:ad23fe03a082 1696 Only values from 0..7 are used.
mbed_official 573:ad23fe03a082 1697 In case of a conflict between priority grouping and available
mbed_official 573:ad23fe03a082 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 573:ad23fe03a082 1699
mbed_official 573:ad23fe03a082 1700 \param [in] PriorityGroup Priority grouping field.
mbed_official 573:ad23fe03a082 1701 */
mbed_official 573:ad23fe03a082 1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mbed_official 573:ad23fe03a082 1703 {
mbed_official 573:ad23fe03a082 1704 uint32_t reg_value;
mbed_official 573:ad23fe03a082 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 573:ad23fe03a082 1706
mbed_official 573:ad23fe03a082 1707 reg_value = SCB->AIRCR; /* read old register configuration */
mbed_official 573:ad23fe03a082 1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official 573:ad23fe03a082 1709 reg_value = (reg_value |
mbed_official 573:ad23fe03a082 1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 573:ad23fe03a082 1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
mbed_official 573:ad23fe03a082 1712 SCB->AIRCR = reg_value;
mbed_official 573:ad23fe03a082 1713 }
mbed_official 573:ad23fe03a082 1714
mbed_official 573:ad23fe03a082 1715
mbed_official 573:ad23fe03a082 1716 /** \brief Get Priority Grouping
mbed_official 573:ad23fe03a082 1717
mbed_official 573:ad23fe03a082 1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
mbed_official 573:ad23fe03a082 1719
mbed_official 573:ad23fe03a082 1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official 573:ad23fe03a082 1721 */
mbed_official 573:ad23fe03a082 1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mbed_official 573:ad23fe03a082 1723 {
mbed_official 573:ad23fe03a082 1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official 573:ad23fe03a082 1725 }
mbed_official 573:ad23fe03a082 1726
mbed_official 573:ad23fe03a082 1727
mbed_official 573:ad23fe03a082 1728 /** \brief Enable External Interrupt
mbed_official 573:ad23fe03a082 1729
mbed_official 573:ad23fe03a082 1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 573:ad23fe03a082 1731
mbed_official 573:ad23fe03a082 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 573:ad23fe03a082 1733 */
mbed_official 573:ad23fe03a082 1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1735 {
mbed_official 573:ad23fe03a082 1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 573:ad23fe03a082 1737 }
mbed_official 573:ad23fe03a082 1738
mbed_official 573:ad23fe03a082 1739
mbed_official 573:ad23fe03a082 1740 /** \brief Disable External Interrupt
mbed_official 573:ad23fe03a082 1741
mbed_official 573:ad23fe03a082 1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 573:ad23fe03a082 1743
mbed_official 573:ad23fe03a082 1744 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 573:ad23fe03a082 1745 */
mbed_official 573:ad23fe03a082 1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1747 {
mbed_official 573:ad23fe03a082 1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 573:ad23fe03a082 1749 }
mbed_official 573:ad23fe03a082 1750
mbed_official 573:ad23fe03a082 1751
mbed_official 573:ad23fe03a082 1752 /** \brief Get Pending Interrupt
mbed_official 573:ad23fe03a082 1753
mbed_official 573:ad23fe03a082 1754 The function reads the pending register in the NVIC and returns the pending bit
mbed_official 573:ad23fe03a082 1755 for the specified interrupt.
mbed_official 573:ad23fe03a082 1756
mbed_official 573:ad23fe03a082 1757 \param [in] IRQn Interrupt number.
mbed_official 573:ad23fe03a082 1758
mbed_official 573:ad23fe03a082 1759 \return 0 Interrupt status is not pending.
mbed_official 573:ad23fe03a082 1760 \return 1 Interrupt status is pending.
mbed_official 573:ad23fe03a082 1761 */
mbed_official 573:ad23fe03a082 1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1763 {
mbed_official 573:ad23fe03a082 1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 573:ad23fe03a082 1765 }
mbed_official 573:ad23fe03a082 1766
mbed_official 573:ad23fe03a082 1767
mbed_official 573:ad23fe03a082 1768 /** \brief Set Pending Interrupt
mbed_official 573:ad23fe03a082 1769
mbed_official 573:ad23fe03a082 1770 The function sets the pending bit of an external interrupt.
mbed_official 573:ad23fe03a082 1771
mbed_official 573:ad23fe03a082 1772 \param [in] IRQn Interrupt number. Value cannot be negative.
mbed_official 573:ad23fe03a082 1773 */
mbed_official 573:ad23fe03a082 1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1775 {
mbed_official 573:ad23fe03a082 1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 573:ad23fe03a082 1777 }
mbed_official 573:ad23fe03a082 1778
mbed_official 573:ad23fe03a082 1779
mbed_official 573:ad23fe03a082 1780 /** \brief Clear Pending Interrupt
mbed_official 573:ad23fe03a082 1781
mbed_official 573:ad23fe03a082 1782 The function clears the pending bit of an external interrupt.
mbed_official 573:ad23fe03a082 1783
mbed_official 573:ad23fe03a082 1784 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 573:ad23fe03a082 1785 */
mbed_official 573:ad23fe03a082 1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1787 {
mbed_official 573:ad23fe03a082 1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 573:ad23fe03a082 1789 }
mbed_official 573:ad23fe03a082 1790
mbed_official 573:ad23fe03a082 1791
mbed_official 573:ad23fe03a082 1792 /** \brief Get Active Interrupt
mbed_official 573:ad23fe03a082 1793
mbed_official 573:ad23fe03a082 1794 The function reads the active register in NVIC and returns the active bit.
mbed_official 573:ad23fe03a082 1795
mbed_official 573:ad23fe03a082 1796 \param [in] IRQn Interrupt number.
mbed_official 573:ad23fe03a082 1797
mbed_official 573:ad23fe03a082 1798 \return 0 Interrupt status is not active.
mbed_official 573:ad23fe03a082 1799 \return 1 Interrupt status is active.
mbed_official 573:ad23fe03a082 1800 */
mbed_official 573:ad23fe03a082 1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1802 {
mbed_official 573:ad23fe03a082 1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 573:ad23fe03a082 1804 }
mbed_official 573:ad23fe03a082 1805
mbed_official 573:ad23fe03a082 1806
mbed_official 573:ad23fe03a082 1807 /** \brief Set Interrupt Priority
mbed_official 573:ad23fe03a082 1808
mbed_official 573:ad23fe03a082 1809 The function sets the priority of an interrupt.
mbed_official 573:ad23fe03a082 1810
mbed_official 573:ad23fe03a082 1811 \note The priority cannot be set for every core interrupt.
mbed_official 573:ad23fe03a082 1812
mbed_official 573:ad23fe03a082 1813 \param [in] IRQn Interrupt number.
mbed_official 573:ad23fe03a082 1814 \param [in] priority Priority to set.
mbed_official 573:ad23fe03a082 1815 */
mbed_official 573:ad23fe03a082 1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 573:ad23fe03a082 1817 {
mbed_official 573:ad23fe03a082 1818 if((int32_t)IRQn < 0) {
mbed_official 573:ad23fe03a082 1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 573:ad23fe03a082 1820 }
mbed_official 573:ad23fe03a082 1821 else {
mbed_official 573:ad23fe03a082 1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 573:ad23fe03a082 1823 }
mbed_official 573:ad23fe03a082 1824 }
mbed_official 573:ad23fe03a082 1825
mbed_official 573:ad23fe03a082 1826
mbed_official 573:ad23fe03a082 1827 /** \brief Get Interrupt Priority
mbed_official 573:ad23fe03a082 1828
mbed_official 573:ad23fe03a082 1829 The function reads the priority of an interrupt. The interrupt
mbed_official 573:ad23fe03a082 1830 number can be positive to specify an external (device specific)
mbed_official 573:ad23fe03a082 1831 interrupt, or negative to specify an internal (core) interrupt.
mbed_official 573:ad23fe03a082 1832
mbed_official 573:ad23fe03a082 1833
mbed_official 573:ad23fe03a082 1834 \param [in] IRQn Interrupt number.
mbed_official 573:ad23fe03a082 1835 \return Interrupt Priority. Value is aligned automatically to the implemented
mbed_official 573:ad23fe03a082 1836 priority bits of the microcontroller.
mbed_official 573:ad23fe03a082 1837 */
mbed_official 573:ad23fe03a082 1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 573:ad23fe03a082 1839 {
mbed_official 573:ad23fe03a082 1840
mbed_official 573:ad23fe03a082 1841 if((int32_t)IRQn < 0) {
mbed_official 573:ad23fe03a082 1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 573:ad23fe03a082 1843 }
mbed_official 573:ad23fe03a082 1844 else {
mbed_official 573:ad23fe03a082 1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 573:ad23fe03a082 1846 }
mbed_official 573:ad23fe03a082 1847 }
mbed_official 573:ad23fe03a082 1848
mbed_official 573:ad23fe03a082 1849
mbed_official 573:ad23fe03a082 1850 /** \brief Encode Priority
mbed_official 573:ad23fe03a082 1851
mbed_official 573:ad23fe03a082 1852 The function encodes the priority for an interrupt with the given priority group,
mbed_official 573:ad23fe03a082 1853 preemptive priority value, and subpriority value.
mbed_official 573:ad23fe03a082 1854 In case of a conflict between priority grouping and available
mbed_official 573:ad23fe03a082 1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 573:ad23fe03a082 1856
mbed_official 573:ad23fe03a082 1857 \param [in] PriorityGroup Used priority group.
mbed_official 573:ad23fe03a082 1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mbed_official 573:ad23fe03a082 1859 \param [in] SubPriority Subpriority value (starting from 0).
mbed_official 573:ad23fe03a082 1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mbed_official 573:ad23fe03a082 1861 */
mbed_official 573:ad23fe03a082 1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mbed_official 573:ad23fe03a082 1863 {
mbed_official 573:ad23fe03a082 1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 573:ad23fe03a082 1865 uint32_t PreemptPriorityBits;
mbed_official 573:ad23fe03a082 1866 uint32_t SubPriorityBits;
mbed_official 573:ad23fe03a082 1867
mbed_official 573:ad23fe03a082 1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 573:ad23fe03a082 1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 573:ad23fe03a082 1870
mbed_official 573:ad23fe03a082 1871 return (
mbed_official 573:ad23fe03a082 1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
mbed_official 573:ad23fe03a082 1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mbed_official 573:ad23fe03a082 1874 );
mbed_official 573:ad23fe03a082 1875 }
mbed_official 573:ad23fe03a082 1876
mbed_official 573:ad23fe03a082 1877
mbed_official 573:ad23fe03a082 1878 /** \brief Decode Priority
mbed_official 573:ad23fe03a082 1879
mbed_official 573:ad23fe03a082 1880 The function decodes an interrupt priority value with a given priority group to
mbed_official 573:ad23fe03a082 1881 preemptive priority value and subpriority value.
mbed_official 573:ad23fe03a082 1882 In case of a conflict between priority grouping and available
mbed_official 573:ad23fe03a082 1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mbed_official 573:ad23fe03a082 1884
mbed_official 573:ad23fe03a082 1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mbed_official 573:ad23fe03a082 1886 \param [in] PriorityGroup Used priority group.
mbed_official 573:ad23fe03a082 1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mbed_official 573:ad23fe03a082 1888 \param [out] pSubPriority Subpriority value (starting from 0).
mbed_official 573:ad23fe03a082 1889 */
mbed_official 573:ad23fe03a082 1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mbed_official 573:ad23fe03a082 1891 {
mbed_official 573:ad23fe03a082 1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 573:ad23fe03a082 1893 uint32_t PreemptPriorityBits;
mbed_official 573:ad23fe03a082 1894 uint32_t SubPriorityBits;
mbed_official 573:ad23fe03a082 1895
mbed_official 573:ad23fe03a082 1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 573:ad23fe03a082 1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 573:ad23fe03a082 1898
mbed_official 573:ad23fe03a082 1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official 573:ad23fe03a082 1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mbed_official 573:ad23fe03a082 1901 }
mbed_official 573:ad23fe03a082 1902
mbed_official 573:ad23fe03a082 1903
mbed_official 573:ad23fe03a082 1904 /** \brief System Reset
mbed_official 573:ad23fe03a082 1905
mbed_official 573:ad23fe03a082 1906 The function initiates a system reset request to reset the MCU.
mbed_official 573:ad23fe03a082 1907 */
mbed_official 573:ad23fe03a082 1908 __STATIC_INLINE void NVIC_SystemReset(void)
mbed_official 573:ad23fe03a082 1909 {
mbed_official 573:ad23fe03a082 1910 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 573:ad23fe03a082 1911 buffered write are completed before reset */
mbed_official 573:ad23fe03a082 1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 573:ad23fe03a082 1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mbed_official 573:ad23fe03a082 1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official 573:ad23fe03a082 1915 __DSB(); /* Ensure completion of memory access */
mbed_official 573:ad23fe03a082 1916 while(1) { __NOP(); } /* wait until reset */
mbed_official 573:ad23fe03a082 1917 }
mbed_official 573:ad23fe03a082 1918
mbed_official 573:ad23fe03a082 1919 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 573:ad23fe03a082 1920
mbed_official 573:ad23fe03a082 1921
mbed_official 573:ad23fe03a082 1922 /* ########################## FPU functions #################################### */
mbed_official 573:ad23fe03a082 1923 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 573:ad23fe03a082 1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
mbed_official 573:ad23fe03a082 1925 \brief Function that provides FPU type.
mbed_official 573:ad23fe03a082 1926 @{
mbed_official 573:ad23fe03a082 1927 */
mbed_official 573:ad23fe03a082 1928
mbed_official 573:ad23fe03a082 1929 /**
mbed_official 573:ad23fe03a082 1930 \fn uint32_t SCB_GetFPUType(void)
mbed_official 573:ad23fe03a082 1931 \brief get FPU type
mbed_official 573:ad23fe03a082 1932 \returns
mbed_official 573:ad23fe03a082 1933 - \b 0: No FPU
mbed_official 573:ad23fe03a082 1934 - \b 1: Single precision FPU
mbed_official 573:ad23fe03a082 1935 - \b 2: Double + Single precision FPU
mbed_official 573:ad23fe03a082 1936 */
mbed_official 573:ad23fe03a082 1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
mbed_official 573:ad23fe03a082 1938 {
mbed_official 573:ad23fe03a082 1939 uint32_t mvfr0;
mbed_official 573:ad23fe03a082 1940
mbed_official 573:ad23fe03a082 1941 mvfr0 = SCB->MVFR0;
mbed_official 573:ad23fe03a082 1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
mbed_official 573:ad23fe03a082 1943 return 2UL; // Double + Single precision FPU
mbed_official 573:ad23fe03a082 1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
mbed_official 573:ad23fe03a082 1945 return 1UL; // Single precision FPU
mbed_official 573:ad23fe03a082 1946 } else {
mbed_official 573:ad23fe03a082 1947 return 0UL; // No FPU
mbed_official 573:ad23fe03a082 1948 }
mbed_official 573:ad23fe03a082 1949 }
mbed_official 573:ad23fe03a082 1950
mbed_official 573:ad23fe03a082 1951
mbed_official 573:ad23fe03a082 1952 /*@} end of CMSIS_Core_FpuFunctions */
mbed_official 573:ad23fe03a082 1953
mbed_official 573:ad23fe03a082 1954
mbed_official 573:ad23fe03a082 1955
mbed_official 573:ad23fe03a082 1956 /* ########################## Cache functions #################################### */
mbed_official 573:ad23fe03a082 1957 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 573:ad23fe03a082 1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
mbed_official 573:ad23fe03a082 1959 \brief Functions that configure Instruction and Data cache.
mbed_official 573:ad23fe03a082 1960 @{
mbed_official 573:ad23fe03a082 1961 */
mbed_official 573:ad23fe03a082 1962
mbed_official 573:ad23fe03a082 1963 /* Cache Size ID Register Macros */
mbed_official 573:ad23fe03a082 1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
mbed_official 573:ad23fe03a082 1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
mbed_official 573:ad23fe03a082 1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
mbed_official 573:ad23fe03a082 1967
mbed_official 573:ad23fe03a082 1968
mbed_official 573:ad23fe03a082 1969 /** \brief Enable I-Cache
mbed_official 573:ad23fe03a082 1970
mbed_official 573:ad23fe03a082 1971 The function turns on I-Cache
mbed_official 573:ad23fe03a082 1972 */
mbed_official 573:ad23fe03a082 1973 __STATIC_INLINE void SCB_EnableICache (void)
mbed_official 573:ad23fe03a082 1974 {
mbed_official 573:ad23fe03a082 1975 #if (__ICACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 1976 __DSB();
mbed_official 573:ad23fe03a082 1977 __ISB();
mbed_official 573:ad23fe03a082 1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
mbed_official 573:ad23fe03a082 1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
mbed_official 573:ad23fe03a082 1980 __DSB();
mbed_official 573:ad23fe03a082 1981 __ISB();
mbed_official 573:ad23fe03a082 1982 #endif
mbed_official 573:ad23fe03a082 1983 }
mbed_official 573:ad23fe03a082 1984
mbed_official 573:ad23fe03a082 1985
mbed_official 573:ad23fe03a082 1986 /** \brief Disable I-Cache
mbed_official 573:ad23fe03a082 1987
mbed_official 573:ad23fe03a082 1988 The function turns off I-Cache
mbed_official 573:ad23fe03a082 1989 */
mbed_official 573:ad23fe03a082 1990 __STATIC_INLINE void SCB_DisableICache (void)
mbed_official 573:ad23fe03a082 1991 {
mbed_official 573:ad23fe03a082 1992 #if (__ICACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 1993 __DSB();
mbed_official 573:ad23fe03a082 1994 __ISB();
mbed_official 573:ad23fe03a082 1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
mbed_official 573:ad23fe03a082 1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
mbed_official 573:ad23fe03a082 1997 __DSB();
mbed_official 573:ad23fe03a082 1998 __ISB();
mbed_official 573:ad23fe03a082 1999 #endif
mbed_official 573:ad23fe03a082 2000 }
mbed_official 573:ad23fe03a082 2001
mbed_official 573:ad23fe03a082 2002
mbed_official 573:ad23fe03a082 2003 /** \brief Invalidate I-Cache
mbed_official 573:ad23fe03a082 2004
mbed_official 573:ad23fe03a082 2005 The function invalidates I-Cache
mbed_official 573:ad23fe03a082 2006 */
mbed_official 573:ad23fe03a082 2007 __STATIC_INLINE void SCB_InvalidateICache (void)
mbed_official 573:ad23fe03a082 2008 {
mbed_official 573:ad23fe03a082 2009 #if (__ICACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2010 __DSB();
mbed_official 573:ad23fe03a082 2011 __ISB();
mbed_official 573:ad23fe03a082 2012 SCB->ICIALLU = 0UL;
mbed_official 573:ad23fe03a082 2013 __DSB();
mbed_official 573:ad23fe03a082 2014 __ISB();
mbed_official 573:ad23fe03a082 2015 #endif
mbed_official 573:ad23fe03a082 2016 }
mbed_official 573:ad23fe03a082 2017
mbed_official 573:ad23fe03a082 2018
mbed_official 573:ad23fe03a082 2019 /** \brief Enable D-Cache
mbed_official 573:ad23fe03a082 2020
mbed_official 573:ad23fe03a082 2021 The function turns on D-Cache
mbed_official 573:ad23fe03a082 2022 */
mbed_official 573:ad23fe03a082 2023 __STATIC_INLINE void SCB_EnableDCache (void)
mbed_official 573:ad23fe03a082 2024 {
mbed_official 573:ad23fe03a082 2025 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2026 uint32_t ccsidr, sshift, wshift, sw;
mbed_official 573:ad23fe03a082 2027 uint32_t sets, ways;
mbed_official 573:ad23fe03a082 2028
mbed_official 573:ad23fe03a082 2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
mbed_official 573:ad23fe03a082 2030 ccsidr = SCB->CCSIDR;
mbed_official 573:ad23fe03a082 2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
mbed_official 573:ad23fe03a082 2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
mbed_official 573:ad23fe03a082 2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
mbed_official 573:ad23fe03a082 2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
mbed_official 573:ad23fe03a082 2035
mbed_official 573:ad23fe03a082 2036 __DSB();
mbed_official 573:ad23fe03a082 2037
mbed_official 573:ad23fe03a082 2038 do { // invalidate D-Cache
mbed_official 573:ad23fe03a082 2039 uint32_t tmpways = ways;
mbed_official 573:ad23fe03a082 2040 do {
mbed_official 573:ad23fe03a082 2041 sw = ((tmpways << wshift) | (sets << sshift));
mbed_official 573:ad23fe03a082 2042 SCB->DCISW = sw;
mbed_official 573:ad23fe03a082 2043 } while(tmpways--);
mbed_official 573:ad23fe03a082 2044 } while(sets--);
mbed_official 573:ad23fe03a082 2045 __DSB();
mbed_official 573:ad23fe03a082 2046
mbed_official 573:ad23fe03a082 2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
mbed_official 573:ad23fe03a082 2048
mbed_official 573:ad23fe03a082 2049 __DSB();
mbed_official 573:ad23fe03a082 2050 __ISB();
mbed_official 573:ad23fe03a082 2051 #endif
mbed_official 573:ad23fe03a082 2052 }
mbed_official 573:ad23fe03a082 2053
mbed_official 573:ad23fe03a082 2054
mbed_official 573:ad23fe03a082 2055 /** \brief Disable D-Cache
mbed_official 573:ad23fe03a082 2056
mbed_official 573:ad23fe03a082 2057 The function turns off D-Cache
mbed_official 573:ad23fe03a082 2058 */
mbed_official 573:ad23fe03a082 2059 __STATIC_INLINE void SCB_DisableDCache (void)
mbed_official 573:ad23fe03a082 2060 {
mbed_official 573:ad23fe03a082 2061 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2062 uint32_t ccsidr, sshift, wshift, sw;
mbed_official 573:ad23fe03a082 2063 uint32_t sets, ways;
mbed_official 573:ad23fe03a082 2064
mbed_official 573:ad23fe03a082 2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
mbed_official 573:ad23fe03a082 2066 ccsidr = SCB->CCSIDR;
mbed_official 573:ad23fe03a082 2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
mbed_official 573:ad23fe03a082 2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
mbed_official 573:ad23fe03a082 2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
mbed_official 573:ad23fe03a082 2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
mbed_official 573:ad23fe03a082 2071
mbed_official 573:ad23fe03a082 2072 __DSB();
mbed_official 573:ad23fe03a082 2073
mbed_official 573:ad23fe03a082 2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
mbed_official 573:ad23fe03a082 2075
mbed_official 573:ad23fe03a082 2076 do { // clean & invalidate D-Cache
mbed_official 573:ad23fe03a082 2077 uint32_t tmpways = ways;
mbed_official 573:ad23fe03a082 2078 do {
mbed_official 573:ad23fe03a082 2079 sw = ((tmpways << wshift) | (sets << sshift));
mbed_official 573:ad23fe03a082 2080 SCB->DCCISW = sw;
mbed_official 573:ad23fe03a082 2081 } while(tmpways--);
mbed_official 573:ad23fe03a082 2082 } while(sets--);
mbed_official 573:ad23fe03a082 2083
mbed_official 573:ad23fe03a082 2084
mbed_official 573:ad23fe03a082 2085 __DSB();
mbed_official 573:ad23fe03a082 2086 __ISB();
mbed_official 573:ad23fe03a082 2087 #endif
mbed_official 573:ad23fe03a082 2088 }
mbed_official 573:ad23fe03a082 2089
mbed_official 573:ad23fe03a082 2090
mbed_official 573:ad23fe03a082 2091 /** \brief Invalidate D-Cache
mbed_official 573:ad23fe03a082 2092
mbed_official 573:ad23fe03a082 2093 The function invalidates D-Cache
mbed_official 573:ad23fe03a082 2094 */
mbed_official 573:ad23fe03a082 2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
mbed_official 573:ad23fe03a082 2096 {
mbed_official 573:ad23fe03a082 2097 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2098 uint32_t ccsidr, sshift, wshift, sw;
mbed_official 573:ad23fe03a082 2099 uint32_t sets, ways;
mbed_official 573:ad23fe03a082 2100
mbed_official 573:ad23fe03a082 2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
mbed_official 573:ad23fe03a082 2102 ccsidr = SCB->CCSIDR;
mbed_official 573:ad23fe03a082 2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
mbed_official 573:ad23fe03a082 2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
mbed_official 573:ad23fe03a082 2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
mbed_official 573:ad23fe03a082 2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
mbed_official 573:ad23fe03a082 2107
mbed_official 573:ad23fe03a082 2108 __DSB();
mbed_official 573:ad23fe03a082 2109
mbed_official 573:ad23fe03a082 2110 do { // invalidate D-Cache
mbed_official 573:ad23fe03a082 2111 uint32_t tmpways = ways;
mbed_official 573:ad23fe03a082 2112 do {
mbed_official 573:ad23fe03a082 2113 sw = ((tmpways << wshift) | (sets << sshift));
mbed_official 573:ad23fe03a082 2114 SCB->DCISW = sw;
mbed_official 573:ad23fe03a082 2115 } while(tmpways--);
mbed_official 573:ad23fe03a082 2116 } while(sets--);
mbed_official 573:ad23fe03a082 2117
mbed_official 573:ad23fe03a082 2118 __DSB();
mbed_official 573:ad23fe03a082 2119 __ISB();
mbed_official 573:ad23fe03a082 2120 #endif
mbed_official 573:ad23fe03a082 2121 }
mbed_official 573:ad23fe03a082 2122
mbed_official 573:ad23fe03a082 2123
mbed_official 573:ad23fe03a082 2124 /** \brief Clean D-Cache
mbed_official 573:ad23fe03a082 2125
mbed_official 573:ad23fe03a082 2126 The function cleans D-Cache
mbed_official 573:ad23fe03a082 2127 */
mbed_official 573:ad23fe03a082 2128 __STATIC_INLINE void SCB_CleanDCache (void)
mbed_official 573:ad23fe03a082 2129 {
mbed_official 573:ad23fe03a082 2130 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2131 uint32_t ccsidr, sshift, wshift, sw;
mbed_official 573:ad23fe03a082 2132 uint32_t sets, ways;
mbed_official 573:ad23fe03a082 2133
mbed_official 573:ad23fe03a082 2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
mbed_official 573:ad23fe03a082 2135 ccsidr = SCB->CCSIDR;
mbed_official 573:ad23fe03a082 2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
mbed_official 573:ad23fe03a082 2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
mbed_official 573:ad23fe03a082 2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
mbed_official 573:ad23fe03a082 2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
mbed_official 573:ad23fe03a082 2140
mbed_official 573:ad23fe03a082 2141 __DSB();
mbed_official 573:ad23fe03a082 2142
mbed_official 573:ad23fe03a082 2143 do { // clean D-Cache
mbed_official 573:ad23fe03a082 2144 uint32_t tmpways = ways;
mbed_official 573:ad23fe03a082 2145 do {
mbed_official 573:ad23fe03a082 2146 sw = ((tmpways << wshift) | (sets << sshift));
mbed_official 573:ad23fe03a082 2147 SCB->DCCSW = sw;
mbed_official 573:ad23fe03a082 2148 } while(tmpways--);
mbed_official 573:ad23fe03a082 2149 } while(sets--);
mbed_official 573:ad23fe03a082 2150
mbed_official 573:ad23fe03a082 2151 __DSB();
mbed_official 573:ad23fe03a082 2152 __ISB();
mbed_official 573:ad23fe03a082 2153 #endif
mbed_official 573:ad23fe03a082 2154 }
mbed_official 573:ad23fe03a082 2155
mbed_official 573:ad23fe03a082 2156
mbed_official 573:ad23fe03a082 2157 /** \brief Clean & Invalidate D-Cache
mbed_official 573:ad23fe03a082 2158
mbed_official 573:ad23fe03a082 2159 The function cleans and Invalidates D-Cache
mbed_official 573:ad23fe03a082 2160 */
mbed_official 573:ad23fe03a082 2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
mbed_official 573:ad23fe03a082 2162 {
mbed_official 573:ad23fe03a082 2163 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2164 uint32_t ccsidr, sshift, wshift, sw;
mbed_official 573:ad23fe03a082 2165 uint32_t sets, ways;
mbed_official 573:ad23fe03a082 2166
mbed_official 573:ad23fe03a082 2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
mbed_official 573:ad23fe03a082 2168 ccsidr = SCB->CCSIDR;
mbed_official 573:ad23fe03a082 2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
mbed_official 573:ad23fe03a082 2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
mbed_official 573:ad23fe03a082 2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
mbed_official 573:ad23fe03a082 2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
mbed_official 573:ad23fe03a082 2173
mbed_official 573:ad23fe03a082 2174 __DSB();
mbed_official 573:ad23fe03a082 2175
mbed_official 573:ad23fe03a082 2176 do { // clean & invalidate D-Cache
mbed_official 573:ad23fe03a082 2177 uint32_t tmpways = ways;
mbed_official 573:ad23fe03a082 2178 do {
mbed_official 573:ad23fe03a082 2179 sw = ((tmpways << wshift) | (sets << sshift));
mbed_official 573:ad23fe03a082 2180 SCB->DCCISW = sw;
mbed_official 573:ad23fe03a082 2181 } while(tmpways--);
mbed_official 573:ad23fe03a082 2182 } while(sets--);
mbed_official 573:ad23fe03a082 2183
mbed_official 573:ad23fe03a082 2184 __DSB();
mbed_official 573:ad23fe03a082 2185 __ISB();
mbed_official 573:ad23fe03a082 2186 #endif
mbed_official 573:ad23fe03a082 2187 }
mbed_official 573:ad23fe03a082 2188
mbed_official 573:ad23fe03a082 2189
mbed_official 573:ad23fe03a082 2190 /**
mbed_official 573:ad23fe03a082 2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2192 \brief D-Cache Invalidate by address
mbed_official 573:ad23fe03a082 2193 \param[in] addr address (aligned to 32-byte boundary)
mbed_official 573:ad23fe03a082 2194 \param[in] dsize size of memory block (in number of bytes)
mbed_official 573:ad23fe03a082 2195 */
mbed_official 573:ad23fe03a082 2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2197 {
mbed_official 573:ad23fe03a082 2198 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2199 int32_t op_size = dsize;
mbed_official 573:ad23fe03a082 2200 uint32_t op_addr = (uint32_t)addr;
mbed_official 573:ad23fe03a082 2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
mbed_official 573:ad23fe03a082 2202
mbed_official 573:ad23fe03a082 2203 __DSB();
mbed_official 573:ad23fe03a082 2204
mbed_official 573:ad23fe03a082 2205 while (op_size > 0) {
mbed_official 573:ad23fe03a082 2206 SCB->DCIMVAC = op_addr;
mbed_official 573:ad23fe03a082 2207 op_addr += linesize;
mbed_official 573:ad23fe03a082 2208 op_size -= (int32_t)linesize;
mbed_official 573:ad23fe03a082 2209 }
mbed_official 573:ad23fe03a082 2210
mbed_official 573:ad23fe03a082 2211 __DSB();
mbed_official 573:ad23fe03a082 2212 __ISB();
mbed_official 573:ad23fe03a082 2213 #endif
mbed_official 573:ad23fe03a082 2214 }
mbed_official 573:ad23fe03a082 2215
mbed_official 573:ad23fe03a082 2216
mbed_official 573:ad23fe03a082 2217 /**
mbed_official 573:ad23fe03a082 2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2219 \brief D-Cache Clean by address
mbed_official 573:ad23fe03a082 2220 \param[in] addr address (aligned to 32-byte boundary)
mbed_official 573:ad23fe03a082 2221 \param[in] dsize size of memory block (in number of bytes)
mbed_official 573:ad23fe03a082 2222 */
mbed_official 573:ad23fe03a082 2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2224 {
mbed_official 573:ad23fe03a082 2225 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2226 int32_t op_size = dsize;
mbed_official 573:ad23fe03a082 2227 uint32_t op_addr = (uint32_t) addr;
mbed_official 573:ad23fe03a082 2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
mbed_official 573:ad23fe03a082 2229
mbed_official 573:ad23fe03a082 2230 __DSB();
mbed_official 573:ad23fe03a082 2231
mbed_official 573:ad23fe03a082 2232 while (op_size > 0) {
mbed_official 573:ad23fe03a082 2233 SCB->DCCMVAC = op_addr;
mbed_official 573:ad23fe03a082 2234 op_addr += linesize;
mbed_official 573:ad23fe03a082 2235 op_size -= (int32_t)linesize;
mbed_official 573:ad23fe03a082 2236 }
mbed_official 573:ad23fe03a082 2237
mbed_official 573:ad23fe03a082 2238 __DSB();
mbed_official 573:ad23fe03a082 2239 __ISB();
mbed_official 573:ad23fe03a082 2240 #endif
mbed_official 573:ad23fe03a082 2241 }
mbed_official 573:ad23fe03a082 2242
mbed_official 573:ad23fe03a082 2243
mbed_official 573:ad23fe03a082 2244 /**
mbed_official 573:ad23fe03a082 2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2246 \brief D-Cache Clean and Invalidate by address
mbed_official 573:ad23fe03a082 2247 \param[in] addr address (aligned to 32-byte boundary)
mbed_official 573:ad23fe03a082 2248 \param[in] dsize size of memory block (in number of bytes)
mbed_official 573:ad23fe03a082 2249 */
mbed_official 573:ad23fe03a082 2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
mbed_official 573:ad23fe03a082 2251 {
mbed_official 573:ad23fe03a082 2252 #if (__DCACHE_PRESENT == 1)
mbed_official 573:ad23fe03a082 2253 int32_t op_size = dsize;
mbed_official 573:ad23fe03a082 2254 uint32_t op_addr = (uint32_t) addr;
mbed_official 573:ad23fe03a082 2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
mbed_official 573:ad23fe03a082 2256
mbed_official 573:ad23fe03a082 2257 __DSB();
mbed_official 573:ad23fe03a082 2258
mbed_official 573:ad23fe03a082 2259 while (op_size > 0) {
mbed_official 573:ad23fe03a082 2260 SCB->DCCIMVAC = op_addr;
mbed_official 573:ad23fe03a082 2261 op_addr += linesize;
mbed_official 573:ad23fe03a082 2262 op_size -= (int32_t)linesize;
mbed_official 573:ad23fe03a082 2263 }
mbed_official 573:ad23fe03a082 2264
mbed_official 573:ad23fe03a082 2265 __DSB();
mbed_official 573:ad23fe03a082 2266 __ISB();
mbed_official 573:ad23fe03a082 2267 #endif
mbed_official 573:ad23fe03a082 2268 }
mbed_official 573:ad23fe03a082 2269
mbed_official 573:ad23fe03a082 2270
mbed_official 573:ad23fe03a082 2271 /*@} end of CMSIS_Core_CacheFunctions */
mbed_official 573:ad23fe03a082 2272
mbed_official 573:ad23fe03a082 2273
mbed_official 573:ad23fe03a082 2274
mbed_official 573:ad23fe03a082 2275 /* ################################## SysTick function ############################################ */
mbed_official 573:ad23fe03a082 2276 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 573:ad23fe03a082 2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 573:ad23fe03a082 2278 \brief Functions that configure the System.
mbed_official 573:ad23fe03a082 2279 @{
mbed_official 573:ad23fe03a082 2280 */
mbed_official 573:ad23fe03a082 2281
mbed_official 573:ad23fe03a082 2282 #if (__Vendor_SysTickConfig == 0)
mbed_official 573:ad23fe03a082 2283
mbed_official 573:ad23fe03a082 2284 /** \brief System Tick Configuration
mbed_official 573:ad23fe03a082 2285
mbed_official 573:ad23fe03a082 2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 573:ad23fe03a082 2287 Counter is in free running mode to generate periodic interrupts.
mbed_official 573:ad23fe03a082 2288
mbed_official 573:ad23fe03a082 2289 \param [in] ticks Number of ticks between two interrupts.
mbed_official 573:ad23fe03a082 2290
mbed_official 573:ad23fe03a082 2291 \return 0 Function succeeded.
mbed_official 573:ad23fe03a082 2292 \return 1 Function failed.
mbed_official 573:ad23fe03a082 2293
mbed_official 573:ad23fe03a082 2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 573:ad23fe03a082 2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 573:ad23fe03a082 2296 must contain a vendor-specific implementation of this function.
mbed_official 573:ad23fe03a082 2297
mbed_official 573:ad23fe03a082 2298 */
mbed_official 573:ad23fe03a082 2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 573:ad23fe03a082 2300 {
mbed_official 573:ad23fe03a082 2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mbed_official 573:ad23fe03a082 2302
mbed_official 573:ad23fe03a082 2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 573:ad23fe03a082 2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 573:ad23fe03a082 2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 573:ad23fe03a082 2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 573:ad23fe03a082 2307 SysTick_CTRL_TICKINT_Msk |
mbed_official 573:ad23fe03a082 2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 573:ad23fe03a082 2309 return (0UL); /* Function successful */
mbed_official 573:ad23fe03a082 2310 }
mbed_official 573:ad23fe03a082 2311
mbed_official 573:ad23fe03a082 2312 #endif
mbed_official 573:ad23fe03a082 2313
mbed_official 573:ad23fe03a082 2314 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 573:ad23fe03a082 2315
mbed_official 573:ad23fe03a082 2316
mbed_official 573:ad23fe03a082 2317
mbed_official 573:ad23fe03a082 2318 /* ##################################### Debug In/Output function ########################################### */
mbed_official 573:ad23fe03a082 2319 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 573:ad23fe03a082 2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
mbed_official 573:ad23fe03a082 2321 \brief Functions that access the ITM debug interface.
mbed_official 573:ad23fe03a082 2322 @{
mbed_official 573:ad23fe03a082 2323 */
mbed_official 573:ad23fe03a082 2324
mbed_official 573:ad23fe03a082 2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mbed_official 573:ad23fe03a082 2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mbed_official 573:ad23fe03a082 2327
mbed_official 573:ad23fe03a082 2328
mbed_official 573:ad23fe03a082 2329 /** \brief ITM Send Character
mbed_official 573:ad23fe03a082 2330
mbed_official 573:ad23fe03a082 2331 The function transmits a character via the ITM channel 0, and
mbed_official 573:ad23fe03a082 2332 \li Just returns when no debugger is connected that has booked the output.
mbed_official 573:ad23fe03a082 2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mbed_official 573:ad23fe03a082 2334
mbed_official 573:ad23fe03a082 2335 \param [in] ch Character to transmit.
mbed_official 573:ad23fe03a082 2336
mbed_official 573:ad23fe03a082 2337 \returns Character to transmit.
mbed_official 573:ad23fe03a082 2338 */
mbed_official 573:ad23fe03a082 2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mbed_official 573:ad23fe03a082 2340 {
mbed_official 573:ad23fe03a082 2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official 573:ad23fe03a082 2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mbed_official 573:ad23fe03a082 2343 {
mbed_official 573:ad23fe03a082 2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mbed_official 573:ad23fe03a082 2345 ITM->PORT[0].u8 = (uint8_t)ch;
mbed_official 573:ad23fe03a082 2346 }
mbed_official 573:ad23fe03a082 2347 return (ch);
mbed_official 573:ad23fe03a082 2348 }
mbed_official 573:ad23fe03a082 2349
mbed_official 573:ad23fe03a082 2350
mbed_official 573:ad23fe03a082 2351 /** \brief ITM Receive Character
mbed_official 573:ad23fe03a082 2352
mbed_official 573:ad23fe03a082 2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
mbed_official 573:ad23fe03a082 2354
mbed_official 573:ad23fe03a082 2355 \return Received character.
mbed_official 573:ad23fe03a082 2356 \return -1 No character pending.
mbed_official 573:ad23fe03a082 2357 */
mbed_official 573:ad23fe03a082 2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mbed_official 573:ad23fe03a082 2359 int32_t ch = -1; /* no character available */
mbed_official 573:ad23fe03a082 2360
mbed_official 573:ad23fe03a082 2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mbed_official 573:ad23fe03a082 2362 ch = ITM_RxBuffer;
mbed_official 573:ad23fe03a082 2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mbed_official 573:ad23fe03a082 2364 }
mbed_official 573:ad23fe03a082 2365
mbed_official 573:ad23fe03a082 2366 return (ch);
mbed_official 573:ad23fe03a082 2367 }
mbed_official 573:ad23fe03a082 2368
mbed_official 573:ad23fe03a082 2369
mbed_official 573:ad23fe03a082 2370 /** \brief ITM Check Character
mbed_official 573:ad23fe03a082 2371
mbed_official 573:ad23fe03a082 2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mbed_official 573:ad23fe03a082 2373
mbed_official 573:ad23fe03a082 2374 \return 0 No character available.
mbed_official 573:ad23fe03a082 2375 \return 1 Character available.
mbed_official 573:ad23fe03a082 2376 */
mbed_official 573:ad23fe03a082 2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
mbed_official 573:ad23fe03a082 2378
mbed_official 573:ad23fe03a082 2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mbed_official 573:ad23fe03a082 2380 return (0); /* no character available */
mbed_official 573:ad23fe03a082 2381 } else {
mbed_official 573:ad23fe03a082 2382 return (1); /* character available */
mbed_official 573:ad23fe03a082 2383 }
mbed_official 573:ad23fe03a082 2384 }
mbed_official 573:ad23fe03a082 2385
mbed_official 573:ad23fe03a082 2386 /*@} end of CMSIS_core_DebugFunctions */
mbed_official 573:ad23fe03a082 2387
mbed_official 573:ad23fe03a082 2388
mbed_official 573:ad23fe03a082 2389
mbed_official 573:ad23fe03a082 2390
mbed_official 573:ad23fe03a082 2391 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 2392 }
mbed_official 573:ad23fe03a082 2393 #endif
mbed_official 573:ad23fe03a082 2394
mbed_official 573:ad23fe03a082 2395 #endif /* __CORE_CM7_H_DEPENDANT */
mbed_official 573:ad23fe03a082 2396
mbed_official 573:ad23fe03a082 2397 #endif /* __CMSIS_GENERIC */