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targets/cmsis/core_caFunc.h@636:83983d65f9e7, 2015-11-12 (annotated)

Committer:
EricLew
Date:
Thu Nov 12 20:51:01 2015 +0000
Revision:
636:83983d65f9e7
Parent:
626:ba773d547214 
deleted other targets than disco board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file core_caFunc.h
mbed_official 390:35c2c1cf29cd 3 * @brief CMSIS Cortex-A Core Function Access Header File
mbed_official 390:35c2c1cf29cd 4 * @version V3.10
mbed_official 626:ba773d547214 5 * @date 30 Oct 2013
mbed_official 390:35c2c1cf29cd 6 *
mbed_official 390:35c2c1cf29cd 7 * @note
mbed_official 390:35c2c1cf29cd 8 *
mbed_official 390:35c2c1cf29cd 9 ******************************************************************************/
mbed_official 626:ba773d547214 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
mbed_official 390:35c2c1cf29cd 11
mbed_official 390:35c2c1cf29cd 12 All rights reserved.
mbed_official 390:35c2c1cf29cd 13 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 14 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 15 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 16 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 18 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 19 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 21 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 22 specific prior written permission.
mbed_official 390:35c2c1cf29cd 23 *
mbed_official 390:35c2c1cf29cd 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 35 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 36
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38 #ifndef __CORE_CAFUNC_H__
mbed_official 390:35c2c1cf29cd 39 #define __CORE_CAFUNC_H__
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41
mbed_official 390:35c2c1cf29cd 42 /* ########################### Core Function Access ########################### */
mbed_official 390:35c2c1cf29cd 43 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 390:35c2c1cf29cd 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mbed_official 390:35c2c1cf29cd 45 @{
mbed_official 390:35c2c1cf29cd 46 */
mbed_official 390:35c2c1cf29cd 47
mbed_official 390:35c2c1cf29cd 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mbed_official 390:35c2c1cf29cd 49 /* ARM armcc specific functions */
mbed_official 390:35c2c1cf29cd 50
mbed_official 390:35c2c1cf29cd 51 #if (__ARMCC_VERSION < 400677)
mbed_official 390:35c2c1cf29cd 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mbed_official 390:35c2c1cf29cd 53 #endif
mbed_official 390:35c2c1cf29cd 54
mbed_official 390:35c2c1cf29cd 55 #define MODE_USR 0x10
mbed_official 390:35c2c1cf29cd 56 #define MODE_FIQ 0x11
mbed_official 390:35c2c1cf29cd 57 #define MODE_IRQ 0x12
mbed_official 390:35c2c1cf29cd 58 #define MODE_SVC 0x13
mbed_official 390:35c2c1cf29cd 59 #define MODE_MON 0x16
mbed_official 390:35c2c1cf29cd 60 #define MODE_ABT 0x17
mbed_official 390:35c2c1cf29cd 61 #define MODE_HYP 0x1A
mbed_official 390:35c2c1cf29cd 62 #define MODE_UND 0x1B
mbed_official 390:35c2c1cf29cd 63 #define MODE_SYS 0x1F
mbed_official 390:35c2c1cf29cd 64
mbed_official 390:35c2c1cf29cd 65 /** \brief Get APSR Register
mbed_official 390:35c2c1cf29cd 66
mbed_official 390:35c2c1cf29cd 67 This function returns the content of the APSR Register.
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 \return APSR Register value
mbed_official 390:35c2c1cf29cd 70 */
mbed_official 390:35c2c1cf29cd 71 __STATIC_INLINE uint32_t __get_APSR(void)
mbed_official 390:35c2c1cf29cd 72 {
mbed_official 390:35c2c1cf29cd 73 register uint32_t __regAPSR __ASM("apsr");
mbed_official 390:35c2c1cf29cd 74 return(__regAPSR);
mbed_official 390:35c2c1cf29cd 75 }
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77
mbed_official 390:35c2c1cf29cd 78 /** \brief Get CPSR Register
mbed_official 390:35c2c1cf29cd 79
mbed_official 390:35c2c1cf29cd 80 This function returns the content of the CPSR Register.
mbed_official 390:35c2c1cf29cd 81
mbed_official 390:35c2c1cf29cd 82 \return CPSR Register value
mbed_official 390:35c2c1cf29cd 83 */
mbed_official 390:35c2c1cf29cd 84 __STATIC_INLINE uint32_t __get_CPSR(void)
mbed_official 390:35c2c1cf29cd 85 {
mbed_official 390:35c2c1cf29cd 86 register uint32_t __regCPSR __ASM("cpsr");
mbed_official 390:35c2c1cf29cd 87 return(__regCPSR);
mbed_official 390:35c2c1cf29cd 88 }
mbed_official 390:35c2c1cf29cd 89
mbed_official 390:35c2c1cf29cd 90 /** \brief Set Stack Pointer
mbed_official 390:35c2c1cf29cd 91
mbed_official 390:35c2c1cf29cd 92 This function assigns the given value to the current stack pointer.
mbed_official 390:35c2c1cf29cd 93
mbed_official 390:35c2c1cf29cd 94 \param [in] topOfStack Stack Pointer value to set
mbed_official 390:35c2c1cf29cd 95 */
mbed_official 390:35c2c1cf29cd 96 register uint32_t __regSP __ASM("sp");
mbed_official 390:35c2c1cf29cd 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mbed_official 390:35c2c1cf29cd 98 {
mbed_official 390:35c2c1cf29cd 99 __regSP = topOfStack;
mbed_official 390:35c2c1cf29cd 100 }
mbed_official 390:35c2c1cf29cd 101
mbed_official 390:35c2c1cf29cd 102
mbed_official 390:35c2c1cf29cd 103 /** \brief Get link register
mbed_official 390:35c2c1cf29cd 104
mbed_official 390:35c2c1cf29cd 105 This function returns the value of the link register
mbed_official 390:35c2c1cf29cd 106
mbed_official 390:35c2c1cf29cd 107 \return Value of link register
mbed_official 390:35c2c1cf29cd 108 */
mbed_official 390:35c2c1cf29cd 109 register uint32_t __reglr __ASM("lr");
mbed_official 390:35c2c1cf29cd 110 __STATIC_INLINE uint32_t __get_LR(void)
mbed_official 390:35c2c1cf29cd 111 {
mbed_official 390:35c2c1cf29cd 112 return(__reglr);
mbed_official 390:35c2c1cf29cd 113 }
mbed_official 390:35c2c1cf29cd 114
mbed_official 390:35c2c1cf29cd 115 /** \brief Set link register
mbed_official 390:35c2c1cf29cd 116
mbed_official 390:35c2c1cf29cd 117 This function sets the value of the link register
mbed_official 390:35c2c1cf29cd 118
mbed_official 390:35c2c1cf29cd 119 \param [in] lr LR value to set
mbed_official 390:35c2c1cf29cd 120 */
mbed_official 390:35c2c1cf29cd 121 __STATIC_INLINE void __set_LR(uint32_t lr)
mbed_official 390:35c2c1cf29cd 122 {
mbed_official 390:35c2c1cf29cd 123 __reglr = lr;
mbed_official 390:35c2c1cf29cd 124 }
mbed_official 390:35c2c1cf29cd 125
mbed_official 390:35c2c1cf29cd 126 /** \brief Set Process Stack Pointer
mbed_official 390:35c2c1cf29cd 127
mbed_official 390:35c2c1cf29cd 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mbed_official 390:35c2c1cf29cd 129
mbed_official 390:35c2c1cf29cd 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbed_official 390:35c2c1cf29cd 131 */
mbed_official 390:35c2c1cf29cd 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
mbed_official 390:35c2c1cf29cd 133 {
mbed_official 390:35c2c1cf29cd 134 ARM
mbed_official 390:35c2c1cf29cd 135 PRESERVE8
mbed_official 390:35c2c1cf29cd 136
mbed_official 390:35c2c1cf29cd 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
mbed_official 390:35c2c1cf29cd 138 MRS R1, CPSR
mbed_official 390:35c2c1cf29cd 139 CPS #MODE_SYS ;no effect in USR mode
mbed_official 390:35c2c1cf29cd 140 MOV SP, R0
mbed_official 390:35c2c1cf29cd 141 MSR CPSR_c, R1 ;no effect in USR mode
mbed_official 390:35c2c1cf29cd 142 ISB
mbed_official 390:35c2c1cf29cd 143 BX LR
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 }
mbed_official 390:35c2c1cf29cd 146
mbed_official 390:35c2c1cf29cd 147 /** \brief Set User Mode
mbed_official 390:35c2c1cf29cd 148
mbed_official 390:35c2c1cf29cd 149 This function changes the processor state to User Mode
mbed_official 390:35c2c1cf29cd 150 */
mbed_official 390:35c2c1cf29cd 151 __STATIC_ASM void __set_CPS_USR(void)
mbed_official 390:35c2c1cf29cd 152 {
mbed_official 390:35c2c1cf29cd 153 ARM
mbed_official 390:35c2c1cf29cd 154
mbed_official 390:35c2c1cf29cd 155 CPS #MODE_USR
mbed_official 390:35c2c1cf29cd 156 BX LR
mbed_official 390:35c2c1cf29cd 157 }
mbed_official 390:35c2c1cf29cd 158
mbed_official 390:35c2c1cf29cd 159
mbed_official 390:35c2c1cf29cd 160 /** \brief Enable FIQ
mbed_official 390:35c2c1cf29cd 161
mbed_official 390:35c2c1cf29cd 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mbed_official 390:35c2c1cf29cd 163 Can only be executed in Privileged modes.
mbed_official 390:35c2c1cf29cd 164 */
mbed_official 390:35c2c1cf29cd 165 #define __enable_fault_irq __enable_fiq
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167
mbed_official 390:35c2c1cf29cd 168 /** \brief Disable FIQ
mbed_official 390:35c2c1cf29cd 169
mbed_official 390:35c2c1cf29cd 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mbed_official 390:35c2c1cf29cd 171 Can only be executed in Privileged modes.
mbed_official 390:35c2c1cf29cd 172 */
mbed_official 390:35c2c1cf29cd 173 #define __disable_fault_irq __disable_fiq
mbed_official 390:35c2c1cf29cd 174
mbed_official 390:35c2c1cf29cd 175
mbed_official 390:35c2c1cf29cd 176 /** \brief Get FPSCR
mbed_official 390:35c2c1cf29cd 177
mbed_official 390:35c2c1cf29cd 178 This function returns the current value of the Floating Point Status/Control register.
mbed_official 390:35c2c1cf29cd 179
mbed_official 390:35c2c1cf29cd 180 \return Floating Point Status/Control register value
mbed_official 390:35c2c1cf29cd 181 */
mbed_official 390:35c2c1cf29cd 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
mbed_official 390:35c2c1cf29cd 183 {
mbed_official 390:35c2c1cf29cd 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 390:35c2c1cf29cd 185 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 390:35c2c1cf29cd 186 return(__regfpscr);
mbed_official 390:35c2c1cf29cd 187 #else
mbed_official 390:35c2c1cf29cd 188 return(0);
mbed_official 390:35c2c1cf29cd 189 #endif
mbed_official 390:35c2c1cf29cd 190 }
mbed_official 390:35c2c1cf29cd 191
mbed_official 390:35c2c1cf29cd 192
mbed_official 390:35c2c1cf29cd 193 /** \brief Set FPSCR
mbed_official 390:35c2c1cf29cd 194
mbed_official 390:35c2c1cf29cd 195 This function assigns the given value to the Floating Point Status/Control register.
mbed_official 390:35c2c1cf29cd 196
mbed_official 390:35c2c1cf29cd 197 \param [in] fpscr Floating Point Status/Control value to set
mbed_official 390:35c2c1cf29cd 198 */
mbed_official 390:35c2c1cf29cd 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mbed_official 390:35c2c1cf29cd 200 {
mbed_official 390:35c2c1cf29cd 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 390:35c2c1cf29cd 202 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 390:35c2c1cf29cd 203 __regfpscr = (fpscr);
mbed_official 390:35c2c1cf29cd 204 #endif
mbed_official 390:35c2c1cf29cd 205 }
mbed_official 390:35c2c1cf29cd 206
mbed_official 390:35c2c1cf29cd 207 /** \brief Get FPEXC
mbed_official 390:35c2c1cf29cd 208
mbed_official 390:35c2c1cf29cd 209 This function returns the current value of the Floating Point Exception Control register.
mbed_official 390:35c2c1cf29cd 210
mbed_official 390:35c2c1cf29cd 211 \return Floating Point Exception Control register value
mbed_official 390:35c2c1cf29cd 212 */
mbed_official 390:35c2c1cf29cd 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
mbed_official 390:35c2c1cf29cd 214 {
mbed_official 390:35c2c1cf29cd 215 #if (__FPU_PRESENT == 1)
mbed_official 390:35c2c1cf29cd 216 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 390:35c2c1cf29cd 217 return(__regfpexc);
mbed_official 390:35c2c1cf29cd 218 #else
mbed_official 390:35c2c1cf29cd 219 return(0);
mbed_official 390:35c2c1cf29cd 220 #endif
mbed_official 390:35c2c1cf29cd 221 }
mbed_official 390:35c2c1cf29cd 222
mbed_official 390:35c2c1cf29cd 223
mbed_official 390:35c2c1cf29cd 224 /** \brief Set FPEXC
mbed_official 390:35c2c1cf29cd 225
mbed_official 390:35c2c1cf29cd 226 This function assigns the given value to the Floating Point Exception Control register.
mbed_official 390:35c2c1cf29cd 227
mbed_official 390:35c2c1cf29cd 228 \param [in] fpscr Floating Point Exception Control value to set
mbed_official 390:35c2c1cf29cd 229 */
mbed_official 390:35c2c1cf29cd 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mbed_official 390:35c2c1cf29cd 231 {
mbed_official 390:35c2c1cf29cd 232 #if (__FPU_PRESENT == 1)
mbed_official 390:35c2c1cf29cd 233 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 390:35c2c1cf29cd 234 __regfpexc = (fpexc);
mbed_official 390:35c2c1cf29cd 235 #endif
mbed_official 390:35c2c1cf29cd 236 }
mbed_official 390:35c2c1cf29cd 237
mbed_official 390:35c2c1cf29cd 238 /** \brief Get CPACR
mbed_official 390:35c2c1cf29cd 239
mbed_official 390:35c2c1cf29cd 240 This function returns the current value of the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 241
mbed_official 390:35c2c1cf29cd 242 \return Coprocessor Access Control register value
mbed_official 390:35c2c1cf29cd 243 */
mbed_official 390:35c2c1cf29cd 244 __STATIC_INLINE uint32_t __get_CPACR(void)
mbed_official 390:35c2c1cf29cd 245 {
mbed_official 390:35c2c1cf29cd 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 390:35c2c1cf29cd 247 return __regCPACR;
mbed_official 390:35c2c1cf29cd 248 }
mbed_official 390:35c2c1cf29cd 249
mbed_official 390:35c2c1cf29cd 250 /** \brief Set CPACR
mbed_official 390:35c2c1cf29cd 251
mbed_official 390:35c2c1cf29cd 252 This function assigns the given value to the Coprocessor Access Control register.
mbed_official 390:35c2c1cf29cd 253
mbed_official 626:ba773d547214 254 \param [in] cpacr Coprocessor Acccess Control value to set
mbed_official 390:35c2c1cf29cd 255 */
mbed_official 390:35c2c1cf29cd 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mbed_official 390:35c2c1cf29cd 257 {
mbed_official 390:35c2c1cf29cd 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 390:35c2c1cf29cd 259 __regCPACR = cpacr;
mbed_official 390:35c2c1cf29cd 260 __ISB();
mbed_official 390:35c2c1cf29cd 261 }
mbed_official 390:35c2c1cf29cd 262
mbed_official 390:35c2c1cf29cd 263 /** \brief Get CBAR
mbed_official 390:35c2c1cf29cd 264
mbed_official 390:35c2c1cf29cd 265 This function returns the value of the Configuration Base Address register.
mbed_official 390:35c2c1cf29cd 266
mbed_official 390:35c2c1cf29cd 267 \return Configuration Base Address register value
mbed_official 390:35c2c1cf29cd 268 */
mbed_official 390:35c2c1cf29cd 269 __STATIC_INLINE uint32_t __get_CBAR() {
mbed_official 390:35c2c1cf29cd 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mbed_official 390:35c2c1cf29cd 271 return(__regCBAR);
mbed_official 390:35c2c1cf29cd 272 }
mbed_official 390:35c2c1cf29cd 273
mbed_official 390:35c2c1cf29cd 274 /** \brief Get TTBR0
mbed_official 390:35c2c1cf29cd 275
mbed_official 626:ba773d547214 276 This function returns the value of the Translation Table Base Register 0.
mbed_official 390:35c2c1cf29cd 277
mbed_official 390:35c2c1cf29cd 278 \return Translation Table Base Register 0 value
mbed_official 390:35c2c1cf29cd 279 */
mbed_official 390:35c2c1cf29cd 280 __STATIC_INLINE uint32_t __get_TTBR0() {
mbed_official 390:35c2c1cf29cd 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 390:35c2c1cf29cd 282 return(__regTTBR0);
mbed_official 390:35c2c1cf29cd 283 }
mbed_official 390:35c2c1cf29cd 284
mbed_official 390:35c2c1cf29cd 285 /** \brief Set TTBR0
mbed_official 390:35c2c1cf29cd 286
mbed_official 626:ba773d547214 287 This function assigns the given value to the Translation Table Base Register 0.
mbed_official 390:35c2c1cf29cd 288
mbed_official 390:35c2c1cf29cd 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
mbed_official 390:35c2c1cf29cd 290 */
mbed_official 390:35c2c1cf29cd 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mbed_official 390:35c2c1cf29cd 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 390:35c2c1cf29cd 293 __regTTBR0 = ttbr0;
mbed_official 390:35c2c1cf29cd 294 __ISB();
mbed_official 390:35c2c1cf29cd 295 }
mbed_official 390:35c2c1cf29cd 296
mbed_official 390:35c2c1cf29cd 297 /** \brief Get DACR
mbed_official 390:35c2c1cf29cd 298
mbed_official 390:35c2c1cf29cd 299 This function returns the value of the Domain Access Control Register.
mbed_official 390:35c2c1cf29cd 300
mbed_official 390:35c2c1cf29cd 301 \return Domain Access Control Register value
mbed_official 390:35c2c1cf29cd 302 */
mbed_official 390:35c2c1cf29cd 303 __STATIC_INLINE uint32_t __get_DACR() {
mbed_official 390:35c2c1cf29cd 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 390:35c2c1cf29cd 305 return(__regDACR);
mbed_official 390:35c2c1cf29cd 306 }
mbed_official 390:35c2c1cf29cd 307
mbed_official 390:35c2c1cf29cd 308 /** \brief Set DACR
mbed_official 390:35c2c1cf29cd 309
mbed_official 626:ba773d547214 310 This function assigns the given value to the Domain Access Control Register.
mbed_official 390:35c2c1cf29cd 311
mbed_official 390:35c2c1cf29cd 312 \param [in] dacr Domain Access Control Register value to set
mbed_official 390:35c2c1cf29cd 313 */
mbed_official 390:35c2c1cf29cd 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mbed_official 390:35c2c1cf29cd 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 390:35c2c1cf29cd 316 __regDACR = dacr;
mbed_official 390:35c2c1cf29cd 317 __ISB();
mbed_official 390:35c2c1cf29cd 318 }
mbed_official 390:35c2c1cf29cd 319
mbed_official 390:35c2c1cf29cd 320 /******************************** Cache and BTAC enable ****************************************************/
mbed_official 390:35c2c1cf29cd 321
mbed_official 390:35c2c1cf29cd 322 /** \brief Set SCTLR
mbed_official 390:35c2c1cf29cd 323
mbed_official 390:35c2c1cf29cd 324 This function assigns the given value to the System Control Register.
mbed_official 390:35c2c1cf29cd 325
mbed_official 626:ba773d547214 326 \param [in] sctlr System Control Register value to set
mbed_official 390:35c2c1cf29cd 327 */
mbed_official 390:35c2c1cf29cd 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mbed_official 390:35c2c1cf29cd 329 {
mbed_official 390:35c2c1cf29cd 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 390:35c2c1cf29cd 331 __regSCTLR = sctlr;
mbed_official 390:35c2c1cf29cd 332 }
mbed_official 390:35c2c1cf29cd 333
mbed_official 390:35c2c1cf29cd 334 /** \brief Get SCTLR
mbed_official 390:35c2c1cf29cd 335
mbed_official 390:35c2c1cf29cd 336 This function returns the value of the System Control Register.
mbed_official 390:35c2c1cf29cd 337
mbed_official 390:35c2c1cf29cd 338 \return System Control Register value
mbed_official 390:35c2c1cf29cd 339 */
mbed_official 390:35c2c1cf29cd 340 __STATIC_INLINE uint32_t __get_SCTLR() {
mbed_official 390:35c2c1cf29cd 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 390:35c2c1cf29cd 342 return(__regSCTLR);
mbed_official 390:35c2c1cf29cd 343 }
mbed_official 390:35c2c1cf29cd 344
mbed_official 390:35c2c1cf29cd 345 /** \brief Enable Caches
mbed_official 390:35c2c1cf29cd 346
mbed_official 390:35c2c1cf29cd 347 Enable Caches
mbed_official 390:35c2c1cf29cd 348 */
mbed_official 390:35c2c1cf29cd 349 __STATIC_INLINE void __enable_caches(void) {
mbed_official 390:35c2c1cf29cd 350 // Set I bit 12 to enable I Cache
mbed_official 390:35c2c1cf29cd 351 // Set C bit 2 to enable D Cache
mbed_official 390:35c2c1cf29cd 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mbed_official 390:35c2c1cf29cd 353 }
mbed_official 390:35c2c1cf29cd 354
mbed_official 390:35c2c1cf29cd 355 /** \brief Disable Caches
mbed_official 390:35c2c1cf29cd 356
mbed_official 390:35c2c1cf29cd 357 Disable Caches
mbed_official 390:35c2c1cf29cd 358 */
mbed_official 390:35c2c1cf29cd 359 __STATIC_INLINE void __disable_caches(void) {
mbed_official 390:35c2c1cf29cd 360 // Clear I bit 12 to disable I Cache
mbed_official 390:35c2c1cf29cd 361 // Clear C bit 2 to disable D Cache
mbed_official 390:35c2c1cf29cd 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mbed_official 390:35c2c1cf29cd 363 __ISB();
mbed_official 390:35c2c1cf29cd 364 }
mbed_official 390:35c2c1cf29cd 365
mbed_official 390:35c2c1cf29cd 366 /** \brief Enable BTAC
mbed_official 390:35c2c1cf29cd 367
mbed_official 390:35c2c1cf29cd 368 Enable BTAC
mbed_official 390:35c2c1cf29cd 369 */
mbed_official 390:35c2c1cf29cd 370 __STATIC_INLINE void __enable_btac(void) {
mbed_official 390:35c2c1cf29cd 371 // Set Z bit 11 to enable branch prediction
mbed_official 390:35c2c1cf29cd 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
mbed_official 390:35c2c1cf29cd 373 __ISB();
mbed_official 390:35c2c1cf29cd 374 }
mbed_official 390:35c2c1cf29cd 375
mbed_official 390:35c2c1cf29cd 376 /** \brief Disable BTAC
mbed_official 390:35c2c1cf29cd 377
mbed_official 390:35c2c1cf29cd 378 Disable BTAC
mbed_official 390:35c2c1cf29cd 379 */
mbed_official 390:35c2c1cf29cd 380 __STATIC_INLINE void __disable_btac(void) {
mbed_official 390:35c2c1cf29cd 381 // Clear Z bit 11 to disable branch prediction
mbed_official 390:35c2c1cf29cd 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mbed_official 390:35c2c1cf29cd 383 }
mbed_official 390:35c2c1cf29cd 384
mbed_official 390:35c2c1cf29cd 385
mbed_official 390:35c2c1cf29cd 386 /** \brief Enable MMU
mbed_official 390:35c2c1cf29cd 387
mbed_official 390:35c2c1cf29cd 388 Enable MMU
mbed_official 390:35c2c1cf29cd 389 */
mbed_official 390:35c2c1cf29cd 390 __STATIC_INLINE void __enable_mmu(void) {
mbed_official 390:35c2c1cf29cd 391 // Set M bit 0 to enable the MMU
mbed_official 390:35c2c1cf29cd 392 // Set AFE bit to enable simplified access permissions model
mbed_official 390:35c2c1cf29cd 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mbed_official 390:35c2c1cf29cd 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mbed_official 390:35c2c1cf29cd 395 __ISB();
mbed_official 390:35c2c1cf29cd 396 }
mbed_official 390:35c2c1cf29cd 397
mbed_official 626:ba773d547214 398 /** \brief Disable MMU
mbed_official 390:35c2c1cf29cd 399
mbed_official 626:ba773d547214 400 Disable MMU
mbed_official 390:35c2c1cf29cd 401 */
mbed_official 390:35c2c1cf29cd 402 __STATIC_INLINE void __disable_mmu(void) {
mbed_official 390:35c2c1cf29cd 403 // Clear M bit 0 to disable the MMU
mbed_official 390:35c2c1cf29cd 404 __set_SCTLR( __get_SCTLR() & ~1);
mbed_official 390:35c2c1cf29cd 405 __ISB();
mbed_official 390:35c2c1cf29cd 406 }
mbed_official 390:35c2c1cf29cd 407
mbed_official 390:35c2c1cf29cd 408 /******************************** TLB maintenance operations ************************************************/
mbed_official 390:35c2c1cf29cd 409 /** \brief Invalidate the whole tlb
mbed_official 390:35c2c1cf29cd 410
mbed_official 390:35c2c1cf29cd 411 TLBIALL. Invalidate the whole tlb
mbed_official 390:35c2c1cf29cd 412 */
mbed_official 390:35c2c1cf29cd 413
mbed_official 390:35c2c1cf29cd 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mbed_official 390:35c2c1cf29cd 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mbed_official 390:35c2c1cf29cd 416 __TLBIALL = 0;
mbed_official 390:35c2c1cf29cd 417 __DSB();
mbed_official 390:35c2c1cf29cd 418 __ISB();
mbed_official 390:35c2c1cf29cd 419 }
mbed_official 390:35c2c1cf29cd 420
mbed_official 390:35c2c1cf29cd 421 /******************************** BTB maintenance operations ************************************************/
mbed_official 390:35c2c1cf29cd 422 /** \brief Invalidate entire branch predictor array
mbed_official 390:35c2c1cf29cd 423
mbed_official 390:35c2c1cf29cd 424 BPIALL. Branch Predictor Invalidate All.
mbed_official 390:35c2c1cf29cd 425 */
mbed_official 390:35c2c1cf29cd 426
mbed_official 390:35c2c1cf29cd 427 __STATIC_INLINE void __v7_inv_btac(void) {
mbed_official 390:35c2c1cf29cd 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mbed_official 390:35c2c1cf29cd 429 __BPIALL = 0;
mbed_official 390:35c2c1cf29cd 430 __DSB(); //ensure completion of the invalidation
mbed_official 390:35c2c1cf29cd 431 __ISB(); //ensure instruction fetch path sees new state
mbed_official 390:35c2c1cf29cd 432 }
mbed_official 390:35c2c1cf29cd 433
mbed_official 390:35c2c1cf29cd 434
mbed_official 390:35c2c1cf29cd 435 /******************************** L1 cache operations ******************************************************/
mbed_official 390:35c2c1cf29cd 436
mbed_official 390:35c2c1cf29cd 437 /** \brief Invalidate the whole I$
mbed_official 390:35c2c1cf29cd 438
mbed_official 390:35c2c1cf29cd 439 ICIALLU. Instruction Cache Invalidate All to PoU
mbed_official 390:35c2c1cf29cd 440 */
mbed_official 390:35c2c1cf29cd 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
mbed_official 390:35c2c1cf29cd 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mbed_official 390:35c2c1cf29cd 443 __ICIALLU = 0;
mbed_official 390:35c2c1cf29cd 444 __DSB(); //ensure completion of the invalidation
mbed_official 390:35c2c1cf29cd 445 __ISB(); //ensure instruction fetch path sees new I cache state
mbed_official 390:35c2c1cf29cd 446 }
mbed_official 390:35c2c1cf29cd 447
mbed_official 390:35c2c1cf29cd 448 /** \brief Clean D$ by MVA
mbed_official 390:35c2c1cf29cd 449
mbed_official 390:35c2c1cf29cd 450 DCCMVAC. Data cache clean by MVA to PoC
mbed_official 390:35c2c1cf29cd 451 */
mbed_official 390:35c2c1cf29cd 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mbed_official 390:35c2c1cf29cd 454 __DCCMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 456 }
mbed_official 390:35c2c1cf29cd 457
mbed_official 390:35c2c1cf29cd 458 /** \brief Invalidate D$ by MVA
mbed_official 390:35c2c1cf29cd 459
mbed_official 390:35c2c1cf29cd 460 DCIMVAC. Data cache invalidate by MVA to PoC
mbed_official 390:35c2c1cf29cd 461 */
mbed_official 390:35c2c1cf29cd 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mbed_official 390:35c2c1cf29cd 464 __DCIMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 466 }
mbed_official 390:35c2c1cf29cd 467
mbed_official 390:35c2c1cf29cd 468 /** \brief Clean and Invalidate D$ by MVA
mbed_official 390:35c2c1cf29cd 469
mbed_official 390:35c2c1cf29cd 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mbed_official 390:35c2c1cf29cd 471 */
mbed_official 390:35c2c1cf29cd 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mbed_official 390:35c2c1cf29cd 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mbed_official 390:35c2c1cf29cd 474 __DCCIMVAC = (uint32_t)va;
mbed_official 390:35c2c1cf29cd 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 390:35c2c1cf29cd 476 }
mbed_official 390:35c2c1cf29cd 477
mbed_official 626:ba773d547214 478 /** \brief Clean and Invalidate the entire data or unified cache
mbed_official 626:ba773d547214 479
mbed_official 626:ba773d547214 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mbed_official 390:35c2c1cf29cd 481 */
mbed_official 390:35c2c1cf29cd 482 #pragma push
mbed_official 390:35c2c1cf29cd 483 #pragma arm
mbed_official 390:35c2c1cf29cd 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
mbed_official 390:35c2c1cf29cd 485 ARM
mbed_official 390:35c2c1cf29cd 486
mbed_official 390:35c2c1cf29cd 487 PUSH {R4-R11}
mbed_official 390:35c2c1cf29cd 488
mbed_official 390:35c2c1cf29cd 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
mbed_official 390:35c2c1cf29cd 490 ANDS R3, R6, #0x07000000 // Extract coherency level
mbed_official 390:35c2c1cf29cd 491 MOV R3, R3, LSR #23 // Total cache levels << 1
mbed_official 390:35c2c1cf29cd 492 BEQ Finished // If 0, no need to clean
mbed_official 390:35c2c1cf29cd 493
mbed_official 390:35c2c1cf29cd 494 MOV R10, #0 // R10 holds current cache level << 1
mbed_official 390:35c2c1cf29cd 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
mbed_official 390:35c2c1cf29cd 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
mbed_official 390:35c2c1cf29cd 497 AND R1, R1, #7 // Isolate those lower 3 bits
mbed_official 390:35c2c1cf29cd 498 CMP R1, #2
mbed_official 390:35c2c1cf29cd 499 BLT Skip // No cache or only instruction cache at this level
mbed_official 390:35c2c1cf29cd 500
mbed_official 390:35c2c1cf29cd 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
mbed_official 390:35c2c1cf29cd 502 ISB // ISB to sync the change to the CacheSizeID reg
mbed_official 390:35c2c1cf29cd 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
mbed_official 390:35c2c1cf29cd 504 AND R2, R1, #7 // Extract the line length field
mbed_official 390:35c2c1cf29cd 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
mbed_official 390:35c2c1cf29cd 506 LDR R4, =0x3FF
mbed_official 390:35c2c1cf29cd 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
mbed_official 390:35c2c1cf29cd 508 CLZ R5, R4 // R5 is the bit position of the way size increment
mbed_official 390:35c2c1cf29cd 509 LDR R7, =0x7FFF
mbed_official 390:35c2c1cf29cd 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
mbed_official 390:35c2c1cf29cd 511
mbed_official 390:35c2c1cf29cd 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
mbed_official 390:35c2c1cf29cd 513
mbed_official 390:35c2c1cf29cd 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
mbed_official 390:35c2c1cf29cd 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
mbed_official 390:35c2c1cf29cd 516 CMP R0, #0
mbed_official 390:35c2c1cf29cd 517 BNE Dccsw
mbed_official 390:35c2c1cf29cd 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 519 B cont
mbed_official 390:35c2c1cf29cd 520 Dccsw CMP R0, #1
mbed_official 390:35c2c1cf29cd 521 BNE Dccisw
mbed_official 390:35c2c1cf29cd 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
mbed_official 390:35c2c1cf29cd 523 B cont
mbed_official 626:ba773d547214 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 525 cont SUBS R9, R9, #1 // Decrement the Way number
mbed_official 390:35c2c1cf29cd 526 BGE Loop3
mbed_official 390:35c2c1cf29cd 527 SUBS R7, R7, #1 // Decrement the Set number
mbed_official 390:35c2c1cf29cd 528 BGE Loop2
mbed_official 626:ba773d547214 529 Skip ADD R10, R10, #2 // Increment the cache number
mbed_official 390:35c2c1cf29cd 530 CMP R3, R10
mbed_official 390:35c2c1cf29cd 531 BGT Loop1
mbed_official 390:35c2c1cf29cd 532
mbed_official 390:35c2c1cf29cd 533 Finished
mbed_official 390:35c2c1cf29cd 534 DSB
mbed_official 390:35c2c1cf29cd 535 POP {R4-R11}
mbed_official 390:35c2c1cf29cd 536 BX lr
mbed_official 390:35c2c1cf29cd 537
mbed_official 390:35c2c1cf29cd 538 }
mbed_official 390:35c2c1cf29cd 539 #pragma pop
mbed_official 390:35c2c1cf29cd 540
mbed_official 390:35c2c1cf29cd 541
mbed_official 390:35c2c1cf29cd 542 /** \brief Invalidate the whole D$
mbed_official 390:35c2c1cf29cd 543
mbed_official 390:35c2c1cf29cd 544 DCISW. Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 545 */
mbed_official 390:35c2c1cf29cd 546
mbed_official 390:35c2c1cf29cd 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 548 __v7_all_cache(0);
mbed_official 390:35c2c1cf29cd 549 }
mbed_official 390:35c2c1cf29cd 550
mbed_official 390:35c2c1cf29cd 551 /** \brief Clean the whole D$
mbed_official 390:35c2c1cf29cd 552
mbed_official 390:35c2c1cf29cd 553 DCCSW. Clean by Set/Way
mbed_official 390:35c2c1cf29cd 554 */
mbed_official 390:35c2c1cf29cd 555
mbed_official 390:35c2c1cf29cd 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 557 __v7_all_cache(1);
mbed_official 390:35c2c1cf29cd 558 }
mbed_official 390:35c2c1cf29cd 559
mbed_official 390:35c2c1cf29cd 560 /** \brief Clean and invalidate the whole D$
mbed_official 390:35c2c1cf29cd 561
mbed_official 390:35c2c1cf29cd 562 DCCISW. Clean and Invalidate by Set/Way
mbed_official 390:35c2c1cf29cd 563 */
mbed_official 390:35c2c1cf29cd 564
mbed_official 390:35c2c1cf29cd 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mbed_official 390:35c2c1cf29cd 566 __v7_all_cache(2);
mbed_official 390:35c2c1cf29cd 567 }
mbed_official 390:35c2c1cf29cd 568
mbed_official 390:35c2c1cf29cd 569 #include "core_ca_mmu.h"
mbed_official 390:35c2c1cf29cd 570
mbed_official 390:35c2c1cf29cd 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
mbed_official 390:35c2c1cf29cd 572
mbed_official 390:35c2c1cf29cd 573 #error IAR Compiler support not implemented for Cortex-A
mbed_official 390:35c2c1cf29cd 574
mbed_official 390:35c2c1cf29cd 575 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
mbed_official 482:d9a48e768ce0 576 /* GNU gcc specific functions */
mbed_official 482:d9a48e768ce0 577
mbed_official 482:d9a48e768ce0 578 #define MODE_USR 0x10
mbed_official 482:d9a48e768ce0 579 #define MODE_FIQ 0x11
mbed_official 482:d9a48e768ce0 580 #define MODE_IRQ 0x12
mbed_official 482:d9a48e768ce0 581 #define MODE_SVC 0x13
mbed_official 482:d9a48e768ce0 582 #define MODE_MON 0x16
mbed_official 482:d9a48e768ce0 583 #define MODE_ABT 0x17
mbed_official 482:d9a48e768ce0 584 #define MODE_HYP 0x1A
mbed_official 482:d9a48e768ce0 585 #define MODE_UND 0x1B
mbed_official 482:d9a48e768ce0 586 #define MODE_SYS 0x1F
mbed_official 482:d9a48e768ce0 587
mbed_official 482:d9a48e768ce0 588
mbed_official 482:d9a48e768ce0 589 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mbed_official 482:d9a48e768ce0 590 {
mbed_official 482:d9a48e768ce0 591 __ASM volatile ("cpsie i");
mbed_official 482:d9a48e768ce0 592 }
mbed_official 482:d9a48e768ce0 593
mbed_official 482:d9a48e768ce0 594 /** \brief Disable IRQ Interrupts
mbed_official 482:d9a48e768ce0 595
mbed_official 482:d9a48e768ce0 596 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mbed_official 482:d9a48e768ce0 597 Can only be executed in Privileged modes.
mbed_official 482:d9a48e768ce0 598 */
mbed_official 482:d9a48e768ce0 599 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
mbed_official 482:d9a48e768ce0 600 {
mbed_official 482:d9a48e768ce0 601 uint32_t result;
mbed_official 482:d9a48e768ce0 602
mbed_official 482:d9a48e768ce0 603 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
mbed_official 482:d9a48e768ce0 604 __ASM volatile ("cpsid i");
mbed_official 482:d9a48e768ce0 605 return(result & 0x80);
mbed_official 482:d9a48e768ce0 606 }
mbed_official 482:d9a48e768ce0 607
mbed_official 482:d9a48e768ce0 608
mbed_official 482:d9a48e768ce0 609 /** \brief Get APSR Register
mbed_official 482:d9a48e768ce0 610
mbed_official 482:d9a48e768ce0 611 This function returns the content of the APSR Register.
mbed_official 482:d9a48e768ce0 612
mbed_official 482:d9a48e768ce0 613 \return APSR Register value
mbed_official 482:d9a48e768ce0 614 */
mbed_official 482:d9a48e768ce0 615 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mbed_official 482:d9a48e768ce0 616 {
mbed_official 482:d9a48e768ce0 617 #if 1
mbed_official 626:ba773d547214 618 register uint32_t __regAPSR;
mbed_official 626:ba773d547214 619 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
mbed_official 482:d9a48e768ce0 620 #else
mbed_official 482:d9a48e768ce0 621 register uint32_t __regAPSR __ASM("apsr");
mbed_official 626:ba773d547214 622 #endif
mbed_official 482:d9a48e768ce0 623 return(__regAPSR);
mbed_official 482:d9a48e768ce0 624 }
mbed_official 482:d9a48e768ce0 625
mbed_official 482:d9a48e768ce0 626
mbed_official 482:d9a48e768ce0 627 /** \brief Get CPSR Register
mbed_official 482:d9a48e768ce0 628
mbed_official 482:d9a48e768ce0 629 This function returns the content of the CPSR Register.
mbed_official 482:d9a48e768ce0 630
mbed_official 482:d9a48e768ce0 631 \return CPSR Register value
mbed_official 482:d9a48e768ce0 632 */
mbed_official 482:d9a48e768ce0 633 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
mbed_official 482:d9a48e768ce0 634 {
mbed_official 482:d9a48e768ce0 635 #if 1
mbed_official 482:d9a48e768ce0 636 register uint32_t __regCPSR;
mbed_official 482:d9a48e768ce0 637 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
mbed_official 482:d9a48e768ce0 638 #else
mbed_official 482:d9a48e768ce0 639 register uint32_t __regCPSR __ASM("cpsr");
mbed_official 482:d9a48e768ce0 640 #endif
mbed_official 482:d9a48e768ce0 641 return(__regCPSR);
mbed_official 482:d9a48e768ce0 642 }
mbed_official 482:d9a48e768ce0 643
mbed_official 482:d9a48e768ce0 644 #if 0
mbed_official 482:d9a48e768ce0 645 /** \brief Set Stack Pointer
mbed_official 482:d9a48e768ce0 646
mbed_official 482:d9a48e768ce0 647 This function assigns the given value to the current stack pointer.
mbed_official 482:d9a48e768ce0 648
mbed_official 482:d9a48e768ce0 649 \param [in] topOfStack Stack Pointer value to set
mbed_official 482:d9a48e768ce0 650 */
mbed_official 482:d9a48e768ce0 651 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
mbed_official 482:d9a48e768ce0 652 {
mbed_official 482:d9a48e768ce0 653 register uint32_t __regSP __ASM("sp");
mbed_official 482:d9a48e768ce0 654 __regSP = topOfStack;
mbed_official 482:d9a48e768ce0 655 }
mbed_official 482:d9a48e768ce0 656 #endif
mbed_official 482:d9a48e768ce0 657
mbed_official 482:d9a48e768ce0 658 /** \brief Get link register
mbed_official 482:d9a48e768ce0 659
mbed_official 482:d9a48e768ce0 660 This function returns the value of the link register
mbed_official 482:d9a48e768ce0 661
mbed_official 482:d9a48e768ce0 662 \return Value of link register
mbed_official 482:d9a48e768ce0 663 */
mbed_official 482:d9a48e768ce0 664 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
mbed_official 482:d9a48e768ce0 665 {
mbed_official 482:d9a48e768ce0 666 register uint32_t __reglr __ASM("lr");
mbed_official 482:d9a48e768ce0 667 return(__reglr);
mbed_official 482:d9a48e768ce0 668 }
mbed_official 482:d9a48e768ce0 669
mbed_official 482:d9a48e768ce0 670 #if 0
mbed_official 482:d9a48e768ce0 671 /** \brief Set link register
mbed_official 482:d9a48e768ce0 672
mbed_official 482:d9a48e768ce0 673 This function sets the value of the link register
mbed_official 482:d9a48e768ce0 674
mbed_official 482:d9a48e768ce0 675 \param [in] lr LR value to set
mbed_official 482:d9a48e768ce0 676 */
mbed_official 482:d9a48e768ce0 677 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
mbed_official 482:d9a48e768ce0 678 {
mbed_official 482:d9a48e768ce0 679 register uint32_t __reglr __ASM("lr");
mbed_official 482:d9a48e768ce0 680 __reglr = lr;
mbed_official 482:d9a48e768ce0 681 }
mbed_official 482:d9a48e768ce0 682 #endif
mbed_official 482:d9a48e768ce0 683
mbed_official 482:d9a48e768ce0 684 /** \brief Set Process Stack Pointer
mbed_official 482:d9a48e768ce0 685
mbed_official 482:d9a48e768ce0 686 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
mbed_official 482:d9a48e768ce0 687
mbed_official 482:d9a48e768ce0 688 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
mbed_official 482:d9a48e768ce0 689 */
mbed_official 626:ba773d547214 690 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mbed_official 626:ba773d547214 691 {
mbed_official 626:ba773d547214 692 __asm__ volatile (
mbed_official 626:ba773d547214 693 ".ARM;"
mbed_official 626:ba773d547214 694 ".eabi_attribute Tag_ABI_align8_preserved,1;"
mbed_official 626:ba773d547214 695
mbed_official 626:ba773d547214 696 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
mbed_official 626:ba773d547214 697 "MRS R1, CPSR;"
mbed_official 626:ba773d547214 698 "CPS %0;" /* ;no effect in USR mode */
mbed_official 626:ba773d547214 699 "MOV SP, R0;"
mbed_official 626:ba773d547214 700 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
mbed_official 626:ba773d547214 701 "ISB;"
mbed_official 626:ba773d547214 702 //"BX LR;"
mbed_official 626:ba773d547214 703 :
mbed_official 626:ba773d547214 704 : "i"(MODE_SYS)
mbed_official 626:ba773d547214 705 : "r0", "r1");
mbed_official 626:ba773d547214 706 return;
mbed_official 626:ba773d547214 707 }
mbed_official 482:d9a48e768ce0 708
mbed_official 482:d9a48e768ce0 709 /** \brief Set User Mode
mbed_official 482:d9a48e768ce0 710
mbed_official 482:d9a48e768ce0 711 This function changes the processor state to User Mode
mbed_official 626:ba773d547214 712 */
mbed_official 626:ba773d547214 713 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
mbed_official 626:ba773d547214 714 {
mbed_official 626:ba773d547214 715 __asm__ volatile (
mbed_official 626:ba773d547214 716 ".ARM;"
mbed_official 482:d9a48e768ce0 717
mbed_official 626:ba773d547214 718 "CPS %0;"
mbed_official 626:ba773d547214 719 //"BX LR;"
mbed_official 626:ba773d547214 720 :
mbed_official 626:ba773d547214 721 : "i"(MODE_USR)
mbed_official 626:ba773d547214 722 : );
mbed_official 626:ba773d547214 723 return;
mbed_official 626:ba773d547214 724 }
mbed_official 626:ba773d547214 725
mbed_official 482:d9a48e768ce0 726
mbed_official 482:d9a48e768ce0 727 /** \brief Enable FIQ
mbed_official 482:d9a48e768ce0 728
mbed_official 482:d9a48e768ce0 729 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mbed_official 482:d9a48e768ce0 730 Can only be executed in Privileged modes.
mbed_official 482:d9a48e768ce0 731 */
mbed_official 626:ba773d547214 732 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
mbed_official 482:d9a48e768ce0 733
mbed_official 482:d9a48e768ce0 734
mbed_official 482:d9a48e768ce0 735 /** \brief Disable FIQ
mbed_official 482:d9a48e768ce0 736
mbed_official 482:d9a48e768ce0 737 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mbed_official 482:d9a48e768ce0 738 Can only be executed in Privileged modes.
mbed_official 482:d9a48e768ce0 739 */
mbed_official 626:ba773d547214 740 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
mbed_official 482:d9a48e768ce0 741
mbed_official 482:d9a48e768ce0 742
mbed_official 482:d9a48e768ce0 743 /** \brief Get FPSCR
mbed_official 482:d9a48e768ce0 744
mbed_official 482:d9a48e768ce0 745 This function returns the current value of the Floating Point Status/Control register.
mbed_official 482:d9a48e768ce0 746
mbed_official 482:d9a48e768ce0 747 \return Floating Point Status/Control register value
mbed_official 482:d9a48e768ce0 748 */
mbed_official 482:d9a48e768ce0 749 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mbed_official 482:d9a48e768ce0 750 {
mbed_official 482:d9a48e768ce0 751 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 482:d9a48e768ce0 752 #if 1
mbed_official 482:d9a48e768ce0 753 uint32_t result;
mbed_official 482:d9a48e768ce0 754
mbed_official 482:d9a48e768ce0 755 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
mbed_official 482:d9a48e768ce0 756 return (result);
mbed_official 482:d9a48e768ce0 757 #else
mbed_official 482:d9a48e768ce0 758 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 482:d9a48e768ce0 759 return(__regfpscr);
mbed_official 482:d9a48e768ce0 760 #endif
mbed_official 482:d9a48e768ce0 761 #else
mbed_official 482:d9a48e768ce0 762 return(0);
mbed_official 482:d9a48e768ce0 763 #endif
mbed_official 482:d9a48e768ce0 764 }
mbed_official 482:d9a48e768ce0 765
mbed_official 482:d9a48e768ce0 766
mbed_official 482:d9a48e768ce0 767 /** \brief Set FPSCR
mbed_official 482:d9a48e768ce0 768
mbed_official 482:d9a48e768ce0 769 This function assigns the given value to the Floating Point Status/Control register.
mbed_official 482:d9a48e768ce0 770
mbed_official 482:d9a48e768ce0 771 \param [in] fpscr Floating Point Status/Control value to set
mbed_official 482:d9a48e768ce0 772 */
mbed_official 482:d9a48e768ce0 773 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mbed_official 482:d9a48e768ce0 774 {
mbed_official 482:d9a48e768ce0 775 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 482:d9a48e768ce0 776 #if 1
mbed_official 482:d9a48e768ce0 777 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
mbed_official 482:d9a48e768ce0 778 #else
mbed_official 482:d9a48e768ce0 779 register uint32_t __regfpscr __ASM("fpscr");
mbed_official 482:d9a48e768ce0 780 __regfpscr = (fpscr);
mbed_official 482:d9a48e768ce0 781 #endif
mbed_official 482:d9a48e768ce0 782 #endif
mbed_official 482:d9a48e768ce0 783 }
mbed_official 482:d9a48e768ce0 784
mbed_official 482:d9a48e768ce0 785 /** \brief Get FPEXC
mbed_official 482:d9a48e768ce0 786
mbed_official 482:d9a48e768ce0 787 This function returns the current value of the Floating Point Exception Control register.
mbed_official 482:d9a48e768ce0 788
mbed_official 482:d9a48e768ce0 789 \return Floating Point Exception Control register value
mbed_official 482:d9a48e768ce0 790 */
mbed_official 482:d9a48e768ce0 791 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
mbed_official 482:d9a48e768ce0 792 {
mbed_official 482:d9a48e768ce0 793 #if (__FPU_PRESENT == 1)
mbed_official 482:d9a48e768ce0 794 #if 1
mbed_official 482:d9a48e768ce0 795 uint32_t result;
mbed_official 482:d9a48e768ce0 796
mbed_official 482:d9a48e768ce0 797 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
mbed_official 482:d9a48e768ce0 798 return (result);
mbed_official 482:d9a48e768ce0 799 #else
mbed_official 482:d9a48e768ce0 800 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 482:d9a48e768ce0 801 return(__regfpexc);
mbed_official 482:d9a48e768ce0 802 #endif
mbed_official 482:d9a48e768ce0 803 #else
mbed_official 482:d9a48e768ce0 804 return(0);
mbed_official 482:d9a48e768ce0 805 #endif
mbed_official 482:d9a48e768ce0 806 }
mbed_official 482:d9a48e768ce0 807
mbed_official 482:d9a48e768ce0 808
mbed_official 482:d9a48e768ce0 809 /** \brief Set FPEXC
mbed_official 482:d9a48e768ce0 810
mbed_official 482:d9a48e768ce0 811 This function assigns the given value to the Floating Point Exception Control register.
mbed_official 482:d9a48e768ce0 812
mbed_official 482:d9a48e768ce0 813 \param [in] fpscr Floating Point Exception Control value to set
mbed_official 482:d9a48e768ce0 814 */
mbed_official 482:d9a48e768ce0 815 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
mbed_official 482:d9a48e768ce0 816 {
mbed_official 482:d9a48e768ce0 817 #if (__FPU_PRESENT == 1)
mbed_official 482:d9a48e768ce0 818 #if 1
mbed_official 482:d9a48e768ce0 819 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
mbed_official 482:d9a48e768ce0 820 #else
mbed_official 482:d9a48e768ce0 821 register uint32_t __regfpexc __ASM("fpexc");
mbed_official 482:d9a48e768ce0 822 __regfpexc = (fpexc);
mbed_official 482:d9a48e768ce0 823 #endif
mbed_official 482:d9a48e768ce0 824 #endif
mbed_official 482:d9a48e768ce0 825 }
mbed_official 482:d9a48e768ce0 826
mbed_official 482:d9a48e768ce0 827 /** \brief Get CPACR
mbed_official 482:d9a48e768ce0 828
mbed_official 482:d9a48e768ce0 829 This function returns the current value of the Coprocessor Access Control register.
mbed_official 482:d9a48e768ce0 830
mbed_official 482:d9a48e768ce0 831 \return Coprocessor Access Control register value
mbed_official 482:d9a48e768ce0 832 */
mbed_official 482:d9a48e768ce0 833 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
mbed_official 482:d9a48e768ce0 834 {
mbed_official 482:d9a48e768ce0 835 #if 1
mbed_official 482:d9a48e768ce0 836 register uint32_t __regCPACR;
mbed_official 482:d9a48e768ce0 837 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
mbed_official 482:d9a48e768ce0 838 #else
mbed_official 482:d9a48e768ce0 839 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 482:d9a48e768ce0 840 #endif
mbed_official 482:d9a48e768ce0 841 return __regCPACR;
mbed_official 482:d9a48e768ce0 842 }
mbed_official 482:d9a48e768ce0 843
mbed_official 482:d9a48e768ce0 844 /** \brief Set CPACR
mbed_official 482:d9a48e768ce0 845
mbed_official 482:d9a48e768ce0 846 This function assigns the given value to the Coprocessor Access Control register.
mbed_official 482:d9a48e768ce0 847
mbed_official 626:ba773d547214 848 \param [in] cpacr Coprocessor Acccess Control value to set
mbed_official 482:d9a48e768ce0 849 */
mbed_official 482:d9a48e768ce0 850 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
mbed_official 482:d9a48e768ce0 851 {
mbed_official 482:d9a48e768ce0 852 #if 1
mbed_official 482:d9a48e768ce0 853 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
mbed_official 482:d9a48e768ce0 854 #else
mbed_official 482:d9a48e768ce0 855 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
mbed_official 482:d9a48e768ce0 856 __regCPACR = cpacr;
mbed_official 482:d9a48e768ce0 857 #endif
mbed_official 482:d9a48e768ce0 858 __ISB();
mbed_official 482:d9a48e768ce0 859 }
mbed_official 482:d9a48e768ce0 860
mbed_official 482:d9a48e768ce0 861 /** \brief Get CBAR
mbed_official 482:d9a48e768ce0 862
mbed_official 482:d9a48e768ce0 863 This function returns the value of the Configuration Base Address register.
mbed_official 482:d9a48e768ce0 864
mbed_official 482:d9a48e768ce0 865 \return Configuration Base Address register value
mbed_official 482:d9a48e768ce0 866 */
mbed_official 482:d9a48e768ce0 867 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
mbed_official 482:d9a48e768ce0 868 #if 1
mbed_official 482:d9a48e768ce0 869 register uint32_t __regCBAR;
mbed_official 482:d9a48e768ce0 870 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
mbed_official 482:d9a48e768ce0 871 #else
mbed_official 482:d9a48e768ce0 872 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
mbed_official 482:d9a48e768ce0 873 #endif
mbed_official 482:d9a48e768ce0 874 return(__regCBAR);
mbed_official 482:d9a48e768ce0 875 }
mbed_official 482:d9a48e768ce0 876
mbed_official 482:d9a48e768ce0 877 /** \brief Get TTBR0
mbed_official 482:d9a48e768ce0 878
mbed_official 626:ba773d547214 879 This function returns the value of the Translation Table Base Register 0.
mbed_official 482:d9a48e768ce0 880
mbed_official 482:d9a48e768ce0 881 \return Translation Table Base Register 0 value
mbed_official 482:d9a48e768ce0 882 */
mbed_official 482:d9a48e768ce0 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
mbed_official 482:d9a48e768ce0 884 #if 1
mbed_official 482:d9a48e768ce0 885 register uint32_t __regTTBR0;
mbed_official 482:d9a48e768ce0 886 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
mbed_official 482:d9a48e768ce0 887 #else
mbed_official 482:d9a48e768ce0 888 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 482:d9a48e768ce0 889 #endif
mbed_official 482:d9a48e768ce0 890 return(__regTTBR0);
mbed_official 482:d9a48e768ce0 891 }
mbed_official 482:d9a48e768ce0 892
mbed_official 482:d9a48e768ce0 893 /** \brief Set TTBR0
mbed_official 482:d9a48e768ce0 894
mbed_official 626:ba773d547214 895 This function assigns the given value to the Translation Table Base Register 0.
mbed_official 482:d9a48e768ce0 896
mbed_official 482:d9a48e768ce0 897 \param [in] ttbr0 Translation Table Base Register 0 value to set
mbed_official 482:d9a48e768ce0 898 */
mbed_official 482:d9a48e768ce0 899 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
mbed_official 482:d9a48e768ce0 900 #if 1
mbed_official 482:d9a48e768ce0 901 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
mbed_official 482:d9a48e768ce0 902 #else
mbed_official 482:d9a48e768ce0 903 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
mbed_official 482:d9a48e768ce0 904 __regTTBR0 = ttbr0;
mbed_official 482:d9a48e768ce0 905 #endif
mbed_official 482:d9a48e768ce0 906 __ISB();
mbed_official 482:d9a48e768ce0 907 }
mbed_official 482:d9a48e768ce0 908
mbed_official 482:d9a48e768ce0 909 /** \brief Get DACR
mbed_official 482:d9a48e768ce0 910
mbed_official 482:d9a48e768ce0 911 This function returns the value of the Domain Access Control Register.
mbed_official 482:d9a48e768ce0 912
mbed_official 482:d9a48e768ce0 913 \return Domain Access Control Register value
mbed_official 482:d9a48e768ce0 914 */
mbed_official 482:d9a48e768ce0 915 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
mbed_official 482:d9a48e768ce0 916 #if 1
mbed_official 482:d9a48e768ce0 917 register uint32_t __regDACR;
mbed_official 482:d9a48e768ce0 918 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
mbed_official 482:d9a48e768ce0 919 #else
mbed_official 482:d9a48e768ce0 920 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 482:d9a48e768ce0 921 #endif
mbed_official 482:d9a48e768ce0 922 return(__regDACR);
mbed_official 482:d9a48e768ce0 923 }
mbed_official 482:d9a48e768ce0 924
mbed_official 482:d9a48e768ce0 925 /** \brief Set DACR
mbed_official 482:d9a48e768ce0 926
mbed_official 626:ba773d547214 927 This function assigns the given value to the Domain Access Control Register.
mbed_official 482:d9a48e768ce0 928
mbed_official 482:d9a48e768ce0 929 \param [in] dacr Domain Access Control Register value to set
mbed_official 482:d9a48e768ce0 930 */
mbed_official 482:d9a48e768ce0 931 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
mbed_official 482:d9a48e768ce0 932 #if 1
mbed_official 482:d9a48e768ce0 933 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
mbed_official 482:d9a48e768ce0 934 #else
mbed_official 482:d9a48e768ce0 935 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
mbed_official 482:d9a48e768ce0 936 __regDACR = dacr;
mbed_official 482:d9a48e768ce0 937 #endif
mbed_official 482:d9a48e768ce0 938 __ISB();
mbed_official 482:d9a48e768ce0 939 }
mbed_official 482:d9a48e768ce0 940
mbed_official 482:d9a48e768ce0 941 /******************************** Cache and BTAC enable ****************************************************/
mbed_official 482:d9a48e768ce0 942
mbed_official 482:d9a48e768ce0 943 /** \brief Set SCTLR
mbed_official 482:d9a48e768ce0 944
mbed_official 482:d9a48e768ce0 945 This function assigns the given value to the System Control Register.
mbed_official 482:d9a48e768ce0 946
mbed_official 626:ba773d547214 947 \param [in] sctlr System Control Register value to set
mbed_official 482:d9a48e768ce0 948 */
mbed_official 482:d9a48e768ce0 949 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
mbed_official 482:d9a48e768ce0 950 {
mbed_official 482:d9a48e768ce0 951 #if 1
mbed_official 482:d9a48e768ce0 952 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
mbed_official 482:d9a48e768ce0 953 #else
mbed_official 482:d9a48e768ce0 954 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 482:d9a48e768ce0 955 __regSCTLR = sctlr;
mbed_official 482:d9a48e768ce0 956 #endif
mbed_official 482:d9a48e768ce0 957 }
mbed_official 482:d9a48e768ce0 958
mbed_official 482:d9a48e768ce0 959 /** \brief Get SCTLR
mbed_official 482:d9a48e768ce0 960
mbed_official 482:d9a48e768ce0 961 This function returns the value of the System Control Register.
mbed_official 482:d9a48e768ce0 962
mbed_official 482:d9a48e768ce0 963 \return System Control Register value
mbed_official 482:d9a48e768ce0 964 */
mbed_official 482:d9a48e768ce0 965 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
mbed_official 482:d9a48e768ce0 966 #if 1
mbed_official 482:d9a48e768ce0 967 register uint32_t __regSCTLR;
mbed_official 482:d9a48e768ce0 968 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
mbed_official 482:d9a48e768ce0 969 #else
mbed_official 482:d9a48e768ce0 970 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
mbed_official 482:d9a48e768ce0 971 #endif
mbed_official 482:d9a48e768ce0 972 return(__regSCTLR);
mbed_official 482:d9a48e768ce0 973 }
mbed_official 482:d9a48e768ce0 974
mbed_official 482:d9a48e768ce0 975 /** \brief Enable Caches
mbed_official 482:d9a48e768ce0 976
mbed_official 482:d9a48e768ce0 977 Enable Caches
mbed_official 482:d9a48e768ce0 978 */
mbed_official 482:d9a48e768ce0 979 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
mbed_official 482:d9a48e768ce0 980 // Set I bit 12 to enable I Cache
mbed_official 482:d9a48e768ce0 981 // Set C bit 2 to enable D Cache
mbed_official 482:d9a48e768ce0 982 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
mbed_official 482:d9a48e768ce0 983 }
mbed_official 482:d9a48e768ce0 984
mbed_official 482:d9a48e768ce0 985 /** \brief Disable Caches
mbed_official 482:d9a48e768ce0 986
mbed_official 482:d9a48e768ce0 987 Disable Caches
mbed_official 482:d9a48e768ce0 988 */
mbed_official 482:d9a48e768ce0 989 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
mbed_official 482:d9a48e768ce0 990 // Clear I bit 12 to disable I Cache
mbed_official 482:d9a48e768ce0 991 // Clear C bit 2 to disable D Cache
mbed_official 482:d9a48e768ce0 992 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
mbed_official 482:d9a48e768ce0 993 __ISB();
mbed_official 482:d9a48e768ce0 994 }
mbed_official 482:d9a48e768ce0 995
mbed_official 482:d9a48e768ce0 996 /** \brief Enable BTAC
mbed_official 482:d9a48e768ce0 997
mbed_official 482:d9a48e768ce0 998 Enable BTAC
mbed_official 482:d9a48e768ce0 999 */
mbed_official 482:d9a48e768ce0 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
mbed_official 482:d9a48e768ce0 1001 // Set Z bit 11 to enable branch prediction
mbed_official 482:d9a48e768ce0 1002 __set_SCTLR( __get_SCTLR() | (1 << 11));
mbed_official 482:d9a48e768ce0 1003 __ISB();
mbed_official 482:d9a48e768ce0 1004 }
mbed_official 482:d9a48e768ce0 1005
mbed_official 482:d9a48e768ce0 1006 /** \brief Disable BTAC
mbed_official 482:d9a48e768ce0 1007
mbed_official 482:d9a48e768ce0 1008 Disable BTAC
mbed_official 482:d9a48e768ce0 1009 */
mbed_official 482:d9a48e768ce0 1010 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
mbed_official 482:d9a48e768ce0 1011 // Clear Z bit 11 to disable branch prediction
mbed_official 482:d9a48e768ce0 1012 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
mbed_official 482:d9a48e768ce0 1013 }
mbed_official 482:d9a48e768ce0 1014
mbed_official 482:d9a48e768ce0 1015
mbed_official 482:d9a48e768ce0 1016 /** \brief Enable MMU
mbed_official 482:d9a48e768ce0 1017
mbed_official 482:d9a48e768ce0 1018 Enable MMU
mbed_official 482:d9a48e768ce0 1019 */
mbed_official 482:d9a48e768ce0 1020 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
mbed_official 482:d9a48e768ce0 1021 // Set M bit 0 to enable the MMU
mbed_official 482:d9a48e768ce0 1022 // Set AFE bit to enable simplified access permissions model
mbed_official 482:d9a48e768ce0 1023 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
mbed_official 482:d9a48e768ce0 1024 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
mbed_official 482:d9a48e768ce0 1025 __ISB();
mbed_official 482:d9a48e768ce0 1026 }
mbed_official 482:d9a48e768ce0 1027
mbed_official 626:ba773d547214 1028 /** \brief Disable MMU
mbed_official 482:d9a48e768ce0 1029
mbed_official 626:ba773d547214 1030 Disable MMU
mbed_official 482:d9a48e768ce0 1031 */
mbed_official 482:d9a48e768ce0 1032 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
mbed_official 482:d9a48e768ce0 1033 // Clear M bit 0 to disable the MMU
mbed_official 482:d9a48e768ce0 1034 __set_SCTLR( __get_SCTLR() & ~1);
mbed_official 482:d9a48e768ce0 1035 __ISB();
mbed_official 482:d9a48e768ce0 1036 }
mbed_official 482:d9a48e768ce0 1037
mbed_official 482:d9a48e768ce0 1038 /******************************** TLB maintenance operations ************************************************/
mbed_official 482:d9a48e768ce0 1039 /** \brief Invalidate the whole tlb
mbed_official 482:d9a48e768ce0 1040
mbed_official 482:d9a48e768ce0 1041 TLBIALL. Invalidate the whole tlb
mbed_official 482:d9a48e768ce0 1042 */
mbed_official 482:d9a48e768ce0 1043
mbed_official 482:d9a48e768ce0 1044 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
mbed_official 482:d9a48e768ce0 1045 #if 1
mbed_official 482:d9a48e768ce0 1046 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
mbed_official 482:d9a48e768ce0 1047 #else
mbed_official 482:d9a48e768ce0 1048 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
mbed_official 482:d9a48e768ce0 1049 __TLBIALL = 0;
mbed_official 482:d9a48e768ce0 1050 #endif
mbed_official 482:d9a48e768ce0 1051 __DSB();
mbed_official 482:d9a48e768ce0 1052 __ISB();
mbed_official 482:d9a48e768ce0 1053 }
mbed_official 482:d9a48e768ce0 1054
mbed_official 482:d9a48e768ce0 1055 /******************************** BTB maintenance operations ************************************************/
mbed_official 482:d9a48e768ce0 1056 /** \brief Invalidate entire branch predictor array
mbed_official 482:d9a48e768ce0 1057
mbed_official 482:d9a48e768ce0 1058 BPIALL. Branch Predictor Invalidate All.
mbed_official 482:d9a48e768ce0 1059 */
mbed_official 482:d9a48e768ce0 1060
mbed_official 482:d9a48e768ce0 1061 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
mbed_official 482:d9a48e768ce0 1062 #if 1
mbed_official 482:d9a48e768ce0 1063 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
mbed_official 482:d9a48e768ce0 1064 #else
mbed_official 482:d9a48e768ce0 1065 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
mbed_official 482:d9a48e768ce0 1066 __BPIALL = 0;
mbed_official 482:d9a48e768ce0 1067 #endif
mbed_official 482:d9a48e768ce0 1068 __DSB(); //ensure completion of the invalidation
mbed_official 482:d9a48e768ce0 1069 __ISB(); //ensure instruction fetch path sees new state
mbed_official 482:d9a48e768ce0 1070 }
mbed_official 482:d9a48e768ce0 1071
mbed_official 482:d9a48e768ce0 1072
mbed_official 482:d9a48e768ce0 1073 /******************************** L1 cache operations ******************************************************/
mbed_official 482:d9a48e768ce0 1074
mbed_official 482:d9a48e768ce0 1075 /** \brief Invalidate the whole I$
mbed_official 482:d9a48e768ce0 1076
mbed_official 482:d9a48e768ce0 1077 ICIALLU. Instruction Cache Invalidate All to PoU
mbed_official 482:d9a48e768ce0 1078 */
mbed_official 482:d9a48e768ce0 1079 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
mbed_official 482:d9a48e768ce0 1080 #if 1
mbed_official 482:d9a48e768ce0 1081 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
mbed_official 482:d9a48e768ce0 1082 #else
mbed_official 482:d9a48e768ce0 1083 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
mbed_official 482:d9a48e768ce0 1084 __ICIALLU = 0;
mbed_official 482:d9a48e768ce0 1085 #endif
mbed_official 482:d9a48e768ce0 1086 __DSB(); //ensure completion of the invalidation
mbed_official 482:d9a48e768ce0 1087 __ISB(); //ensure instruction fetch path sees new I cache state
mbed_official 482:d9a48e768ce0 1088 }
mbed_official 482:d9a48e768ce0 1089
mbed_official 482:d9a48e768ce0 1090 /** \brief Clean D$ by MVA
mbed_official 482:d9a48e768ce0 1091
mbed_official 482:d9a48e768ce0 1092 DCCMVAC. Data cache clean by MVA to PoC
mbed_official 482:d9a48e768ce0 1093 */
mbed_official 482:d9a48e768ce0 1094 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
mbed_official 482:d9a48e768ce0 1095 #if 1
mbed_official 482:d9a48e768ce0 1096 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
mbed_official 482:d9a48e768ce0 1097 #else
mbed_official 482:d9a48e768ce0 1098 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
mbed_official 482:d9a48e768ce0 1099 __DCCMVAC = (uint32_t)va;
mbed_official 482:d9a48e768ce0 1100 #endif
mbed_official 482:d9a48e768ce0 1101 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 482:d9a48e768ce0 1102 }
mbed_official 482:d9a48e768ce0 1103
mbed_official 482:d9a48e768ce0 1104 /** \brief Invalidate D$ by MVA
mbed_official 482:d9a48e768ce0 1105
mbed_official 482:d9a48e768ce0 1106 DCIMVAC. Data cache invalidate by MVA to PoC
mbed_official 482:d9a48e768ce0 1107 */
mbed_official 482:d9a48e768ce0 1108 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
mbed_official 482:d9a48e768ce0 1109 #if 1
mbed_official 482:d9a48e768ce0 1110 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
mbed_official 482:d9a48e768ce0 1111 #else
mbed_official 482:d9a48e768ce0 1112 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
mbed_official 482:d9a48e768ce0 1113 __DCIMVAC = (uint32_t)va;
mbed_official 482:d9a48e768ce0 1114 #endif
mbed_official 482:d9a48e768ce0 1115 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 482:d9a48e768ce0 1116 }
mbed_official 482:d9a48e768ce0 1117
mbed_official 482:d9a48e768ce0 1118 /** \brief Clean and Invalidate D$ by MVA
mbed_official 482:d9a48e768ce0 1119
mbed_official 482:d9a48e768ce0 1120 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
mbed_official 482:d9a48e768ce0 1121 */
mbed_official 482:d9a48e768ce0 1122 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
mbed_official 482:d9a48e768ce0 1123 #if 1
mbed_official 482:d9a48e768ce0 1124 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
mbed_official 482:d9a48e768ce0 1125 #else
mbed_official 482:d9a48e768ce0 1126 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
mbed_official 482:d9a48e768ce0 1127 __DCCIMVAC = (uint32_t)va;
mbed_official 482:d9a48e768ce0 1128 #endif
mbed_official 482:d9a48e768ce0 1129 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
mbed_official 482:d9a48e768ce0 1130 }
mbed_official 482:d9a48e768ce0 1131
mbed_official 626:ba773d547214 1132 /** \brief Clean and Invalidate the entire data or unified cache
mbed_official 482:d9a48e768ce0 1133
mbed_official 626:ba773d547214 1134 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
mbed_official 482:d9a48e768ce0 1135 */
mbed_official 482:d9a48e768ce0 1136 extern void __v7_all_cache(uint32_t op);
mbed_official 482:d9a48e768ce0 1137
mbed_official 482:d9a48e768ce0 1138
mbed_official 482:d9a48e768ce0 1139 /** \brief Invalidate the whole D$
mbed_official 482:d9a48e768ce0 1140
mbed_official 482:d9a48e768ce0 1141 DCISW. Invalidate by Set/Way
mbed_official 482:d9a48e768ce0 1142 */
mbed_official 482:d9a48e768ce0 1143
mbed_official 482:d9a48e768ce0 1144 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
mbed_official 482:d9a48e768ce0 1145 __v7_all_cache(0);
mbed_official 482:d9a48e768ce0 1146 }
mbed_official 482:d9a48e768ce0 1147
mbed_official 482:d9a48e768ce0 1148 /** \brief Clean the whole D$
mbed_official 482:d9a48e768ce0 1149
mbed_official 482:d9a48e768ce0 1150 DCCSW. Clean by Set/Way
mbed_official 482:d9a48e768ce0 1151 */
mbed_official 482:d9a48e768ce0 1152
mbed_official 482:d9a48e768ce0 1153 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
mbed_official 482:d9a48e768ce0 1154 __v7_all_cache(1);
mbed_official 482:d9a48e768ce0 1155 }
mbed_official 482:d9a48e768ce0 1156
mbed_official 482:d9a48e768ce0 1157 /** \brief Clean and invalidate the whole D$
mbed_official 482:d9a48e768ce0 1158
mbed_official 482:d9a48e768ce0 1159 DCCISW. Clean and Invalidate by Set/Way
mbed_official 482:d9a48e768ce0 1160 */
mbed_official 482:d9a48e768ce0 1161
mbed_official 482:d9a48e768ce0 1162 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
mbed_official 482:d9a48e768ce0 1163 __v7_all_cache(2);
mbed_official 482:d9a48e768ce0 1164 }
mbed_official 482:d9a48e768ce0 1165
mbed_official 482:d9a48e768ce0 1166 #include "core_ca_mmu.h"
mbed_official 390:35c2c1cf29cd 1167
mbed_official 390:35c2c1cf29cd 1168 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
mbed_official 390:35c2c1cf29cd 1169
mbed_official 390:35c2c1cf29cd 1170 #error TASKING Compiler support not implemented for Cortex-A
mbed_official 390:35c2c1cf29cd 1171
mbed_official 390:35c2c1cf29cd 1172 #endif
mbed_official 390:35c2c1cf29cd 1173
mbed_official 390:35c2c1cf29cd 1174 /*@} end of CMSIS_Core_RegAccFunctions */
mbed_official 390:35c2c1cf29cd 1175
mbed_official 390:35c2c1cf29cd 1176
mbed_official 390:35c2c1cf29cd 1177 #endif /* __CORE_CAFUNC_H__ */