STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_rcc.h@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:: EricLew
Date:: Mon Nov 02 19:37:23 2015 +0000
Revision:: 0:80ee8f3b695e

Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_rcc.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of RCC LL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_LL_RCC_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_LL_RCC_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	#if defined(RCC)
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	/** @defgroup RCC_LL RCC
EricLew	0:80ee8f3b695e	56	* @{
EricLew	0:80ee8f3b695e	57	*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
EricLew	0:80ee8f3b695e	62	* @{
EricLew	0:80ee8f3b695e	63	*/
EricLew	0:80ee8f3b695e	64
EricLew	0:80ee8f3b695e	65	static const uint8_t aRCC_APBAHBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
EricLew	0:80ee8f3b695e	66
EricLew	0:80ee8f3b695e	67	/**
EricLew	0:80ee8f3b695e	68	* @}
EricLew	0:80ee8f3b695e	69	*/
EricLew	0:80ee8f3b695e	70
EricLew	0:80ee8f3b695e	71	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
EricLew	0:80ee8f3b695e	73	* @{
EricLew	0:80ee8f3b695e	74	*/
EricLew	0:80ee8f3b695e	75
EricLew	0:80ee8f3b695e	76	/* Defines used for the bit position in the register and perform offsets*/
EricLew	0:80ee8f3b695e	77	#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)
EricLew	0:80ee8f3b695e	78	#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)
EricLew	0:80ee8f3b695e	79	#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)
EricLew	0:80ee8f3b695e	80	#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)
EricLew	0:80ee8f3b695e	81	#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)
EricLew	0:80ee8f3b695e	82	#define RCC_POSITION_MSICAL (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)
EricLew	0:80ee8f3b695e	83	#define RCC_POSITION_MSITRIM (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM)
EricLew	0:80ee8f3b695e	84	#define RCC_POSITION_PLLN (uint32_t)POSITION_VAL(RCC_PLLCFGR_PLLN)
EricLew	0:80ee8f3b695e	85	#define RCC_POSITION_PLLSAI1N (uint32_t)POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)
EricLew	0:80ee8f3b695e	86	#define RCC_POSITION_PLLSAI2N (uint32_t)POSITION_VAL(RCC_PLLSAI2CFGR_PLLSAI2N)
EricLew	0:80ee8f3b695e	87
EricLew	0:80ee8f3b695e	88	/**
EricLew	0:80ee8f3b695e	89	* @}
EricLew	0:80ee8f3b695e	90	*/
EricLew	0:80ee8f3b695e	91
EricLew	0:80ee8f3b695e	92	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	93
EricLew	0:80ee8f3b695e	94	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	95	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	96	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
EricLew	0:80ee8f3b695e	97	* @{
EricLew	0:80ee8f3b695e	98	*/
EricLew	0:80ee8f3b695e	99
EricLew	0:80ee8f3b695e	100	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
EricLew	0:80ee8f3b695e	101	* @brief Flags defines which can be used with LL_RCC_WriteReg function
EricLew	0:80ee8f3b695e	102	* @{
EricLew	0:80ee8f3b695e	103	*/
EricLew	0:80ee8f3b695e	104	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC
EricLew	0:80ee8f3b695e	105	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC
EricLew	0:80ee8f3b695e	106	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC
EricLew	0:80ee8f3b695e	107	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC
EricLew	0:80ee8f3b695e	108	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC
EricLew	0:80ee8f3b695e	109	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC
EricLew	0:80ee8f3b695e	110	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC
EricLew	0:80ee8f3b695e	111	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC
EricLew	0:80ee8f3b695e	112	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC
EricLew	0:80ee8f3b695e	113	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC
EricLew	0:80ee8f3b695e	114	/**
EricLew	0:80ee8f3b695e	115	* @}
EricLew	0:80ee8f3b695e	116	*/
EricLew	0:80ee8f3b695e	117
EricLew	0:80ee8f3b695e	118	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
EricLew	0:80ee8f3b695e	119	* @brief Flags defines which can be used with LL_RCC_ReadReg function
EricLew	0:80ee8f3b695e	120	* @{
EricLew	0:80ee8f3b695e	121	*/
EricLew	0:80ee8f3b695e	122	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF
EricLew	0:80ee8f3b695e	123	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF
EricLew	0:80ee8f3b695e	124	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF
EricLew	0:80ee8f3b695e	125	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF
EricLew	0:80ee8f3b695e	126	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF
EricLew	0:80ee8f3b695e	127	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF
EricLew	0:80ee8f3b695e	128	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF
EricLew	0:80ee8f3b695e	129	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF
EricLew	0:80ee8f3b695e	130	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF
EricLew	0:80ee8f3b695e	131	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF
EricLew	0:80ee8f3b695e	132	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF
EricLew	0:80ee8f3b695e	133	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
EricLew	0:80ee8f3b695e	134	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
EricLew	0:80ee8f3b695e	135	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF
EricLew	0:80ee8f3b695e	136	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
EricLew	0:80ee8f3b695e	137	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
EricLew	0:80ee8f3b695e	138	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
EricLew	0:80ee8f3b695e	139	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
EricLew	0:80ee8f3b695e	140	/**
EricLew	0:80ee8f3b695e	141	* @}
EricLew	0:80ee8f3b695e	142	*/
EricLew	0:80ee8f3b695e	143
EricLew	0:80ee8f3b695e	144	/** @defgroup RCC_LL_EC_IT IT Defines
EricLew	0:80ee8f3b695e	145	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
EricLew	0:80ee8f3b695e	146	* @{
EricLew	0:80ee8f3b695e	147	*/
EricLew	0:80ee8f3b695e	148	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE
EricLew	0:80ee8f3b695e	149	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE
EricLew	0:80ee8f3b695e	150	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE
EricLew	0:80ee8f3b695e	151	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE
EricLew	0:80ee8f3b695e	152	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE
EricLew	0:80ee8f3b695e	153	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE
EricLew	0:80ee8f3b695e	154	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE
EricLew	0:80ee8f3b695e	155	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE
EricLew	0:80ee8f3b695e	156	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE
EricLew	0:80ee8f3b695e	157	/**
EricLew	0:80ee8f3b695e	158	* @}
EricLew	0:80ee8f3b695e	159	*/
EricLew	0:80ee8f3b695e	160
EricLew	0:80ee8f3b695e	161	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
EricLew	0:80ee8f3b695e	162	* @{
EricLew	0:80ee8f3b695e	163	*/
EricLew	0:80ee8f3b695e	164	#define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) /!< Xtal mode lower driving capability /
EricLew	0:80ee8f3b695e	165	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
EricLew	0:80ee8f3b695e	166	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
EricLew	0:80ee8f3b695e	167	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
EricLew	0:80ee8f3b695e	168	/**
EricLew	0:80ee8f3b695e	169	* @}
EricLew	0:80ee8f3b695e	170	*/
EricLew	0:80ee8f3b695e	171
EricLew	0:80ee8f3b695e	172	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
EricLew	0:80ee8f3b695e	173	* @{
EricLew	0:80ee8f3b695e	174	*/
EricLew	0:80ee8f3b695e	175	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
EricLew	0:80ee8f3b695e	176	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
EricLew	0:80ee8f3b695e	177	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
EricLew	0:80ee8f3b695e	178	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
EricLew	0:80ee8f3b695e	179	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
EricLew	0:80ee8f3b695e	180	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
EricLew	0:80ee8f3b695e	181	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
EricLew	0:80ee8f3b695e	182	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
EricLew	0:80ee8f3b695e	183	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
EricLew	0:80ee8f3b695e	184	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
EricLew	0:80ee8f3b695e	185	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
EricLew	0:80ee8f3b695e	186	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
EricLew	0:80ee8f3b695e	187	/**
EricLew	0:80ee8f3b695e	188	* @}
EricLew	0:80ee8f3b695e	189	*/
EricLew	0:80ee8f3b695e	190
EricLew	0:80ee8f3b695e	191	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
EricLew	0:80ee8f3b695e	192	* @{
EricLew	0:80ee8f3b695e	193	*/
EricLew	0:80ee8f3b695e	194	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
EricLew	0:80ee8f3b695e	195	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
EricLew	0:80ee8f3b695e	196	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
EricLew	0:80ee8f3b695e	197	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
EricLew	0:80ee8f3b695e	198	/**
EricLew	0:80ee8f3b695e	199	* @}
EricLew	0:80ee8f3b695e	200	*/
EricLew	0:80ee8f3b695e	201
EricLew	0:80ee8f3b695e	202	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
EricLew	0:80ee8f3b695e	203	* @{
EricLew	0:80ee8f3b695e	204	*/
EricLew	0:80ee8f3b695e	205	#define LL_RCC_LSCO_CLKSOURCE_LSI (uint32_t)0x00000000 /!< LSI selection for low speed clock /
EricLew	0:80ee8f3b695e	206	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
EricLew	0:80ee8f3b695e	207	/**
EricLew	0:80ee8f3b695e	208	* @}
EricLew	0:80ee8f3b695e	209	*/
EricLew	0:80ee8f3b695e	210
EricLew	0:80ee8f3b695e	211	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
EricLew	0:80ee8f3b695e	212	* @{
EricLew	0:80ee8f3b695e	213	*/
EricLew	0:80ee8f3b695e	214	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
EricLew	0:80ee8f3b695e	215	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
EricLew	0:80ee8f3b695e	216	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
EricLew	0:80ee8f3b695e	217	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
EricLew	0:80ee8f3b695e	218	/**
EricLew	0:80ee8f3b695e	219	* @}
EricLew	0:80ee8f3b695e	220	*/
EricLew	0:80ee8f3b695e	221
EricLew	0:80ee8f3b695e	222	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
EricLew	0:80ee8f3b695e	223	* @{
EricLew	0:80ee8f3b695e	224	*/
EricLew	0:80ee8f3b695e	225	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
EricLew	0:80ee8f3b695e	226	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
EricLew	0:80ee8f3b695e	227	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
EricLew	0:80ee8f3b695e	228	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
EricLew	0:80ee8f3b695e	229	/**
EricLew	0:80ee8f3b695e	230	* @}
EricLew	0:80ee8f3b695e	231	*/
EricLew	0:80ee8f3b695e	232
EricLew	0:80ee8f3b695e	233	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
EricLew	0:80ee8f3b695e	234	* @{
EricLew	0:80ee8f3b695e	235	*/
EricLew	0:80ee8f3b695e	236	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
EricLew	0:80ee8f3b695e	237	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
EricLew	0:80ee8f3b695e	238	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
EricLew	0:80ee8f3b695e	239	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
EricLew	0:80ee8f3b695e	240	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
EricLew	0:80ee8f3b695e	241	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
EricLew	0:80ee8f3b695e	242	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
EricLew	0:80ee8f3b695e	243	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
EricLew	0:80ee8f3b695e	244	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
EricLew	0:80ee8f3b695e	245	/**
EricLew	0:80ee8f3b695e	246	* @}
EricLew	0:80ee8f3b695e	247	*/
EricLew	0:80ee8f3b695e	248
EricLew	0:80ee8f3b695e	249	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
EricLew	0:80ee8f3b695e	250	* @{
EricLew	0:80ee8f3b695e	251	*/
EricLew	0:80ee8f3b695e	252	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
EricLew	0:80ee8f3b695e	253	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
EricLew	0:80ee8f3b695e	254	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
EricLew	0:80ee8f3b695e	255	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
EricLew	0:80ee8f3b695e	256	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
EricLew	0:80ee8f3b695e	257	/**
EricLew	0:80ee8f3b695e	258	* @}
EricLew	0:80ee8f3b695e	259	*/
EricLew	0:80ee8f3b695e	260
EricLew	0:80ee8f3b695e	261	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
EricLew	0:80ee8f3b695e	262	* @{
EricLew	0:80ee8f3b695e	263	*/
EricLew	0:80ee8f3b695e	264	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
EricLew	0:80ee8f3b695e	265	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
EricLew	0:80ee8f3b695e	266	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
EricLew	0:80ee8f3b695e	267	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
EricLew	0:80ee8f3b695e	268	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
EricLew	0:80ee8f3b695e	269	/**
EricLew	0:80ee8f3b695e	270	* @}
EricLew	0:80ee8f3b695e	271	*/
EricLew	0:80ee8f3b695e	272
EricLew	0:80ee8f3b695e	273	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
EricLew	0:80ee8f3b695e	274	* @{
EricLew	0:80ee8f3b695e	275	*/
EricLew	0:80ee8f3b695e	276	#define LL_RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000) /!< MSI selection after wake-up from STOP /
EricLew	0:80ee8f3b695e	277	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
EricLew	0:80ee8f3b695e	278	/**
EricLew	0:80ee8f3b695e	279	* @}
EricLew	0:80ee8f3b695e	280	*/
EricLew	0:80ee8f3b695e	281
EricLew	0:80ee8f3b695e	282	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
EricLew	0:80ee8f3b695e	283	* @{
EricLew	0:80ee8f3b695e	284	*/
EricLew	0:80ee8f3b695e	285	#define LL_RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000) /!< MCO output disabled, no clock on MCO /
EricLew	0:80ee8f3b695e	286	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
EricLew	0:80ee8f3b695e	287	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	288	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	289	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
EricLew	0:80ee8f3b695e	290	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< PLLCLK selection as MCO1 source /
EricLew	0:80ee8f3b695e	291	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
EricLew	0:80ee8f3b695e	292	#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL /!< LSE selection as MCO1 source /
EricLew	0:80ee8f3b695e	293	/**
EricLew	0:80ee8f3b695e	294	* @}
EricLew	0:80ee8f3b695e	295	*/
EricLew	0:80ee8f3b695e	296
EricLew	0:80ee8f3b695e	297	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
EricLew	0:80ee8f3b695e	298	* @{
EricLew	0:80ee8f3b695e	299	*/
EricLew	0:80ee8f3b695e	300	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCO_PRE_1 /!< MCO not divided /
EricLew	0:80ee8f3b695e	301	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCO_PRE_2 /!< MCO divided by 2 /
EricLew	0:80ee8f3b695e	302	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCO_PRE_4 /!< MCO divided by 4 /
EricLew	0:80ee8f3b695e	303	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCO_PRE_8 /!< MCO divided by 8 /
EricLew	0:80ee8f3b695e	304	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCO_PRE_16 /!< MCO divided by 16 /
EricLew	0:80ee8f3b695e	305	/**
EricLew	0:80ee8f3b695e	306	* @}
EricLew	0:80ee8f3b695e	307	*/
EricLew	0:80ee8f3b695e	308
EricLew	0:80ee8f3b695e	309	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
EricLew	0:80ee8f3b695e	310	* @{
EricLew	0:80ee8f3b695e	311	*/
EricLew	0:80ee8f3b695e	312	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| 0x00000000)
EricLew	0:80ee8f3b695e	313	#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL_0)
EricLew	0:80ee8f3b695e	314	#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL_1)
EricLew	0:80ee8f3b695e	315	#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16) \| RCC_CCIPR_USART1SEL)
EricLew	0:80ee8f3b695e	316	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| 0x00000000)
EricLew	0:80ee8f3b695e	317	#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL_0)
EricLew	0:80ee8f3b695e	318	#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL_1)
EricLew	0:80ee8f3b695e	319	#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16) \| RCC_CCIPR_USART2SEL)
EricLew	0:80ee8f3b695e	320	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| 0x00000000)
EricLew	0:80ee8f3b695e	321	#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL_0)
EricLew	0:80ee8f3b695e	322	#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL_1)
EricLew	0:80ee8f3b695e	323	#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART3SEL << 16) \| RCC_CCIPR_USART3SEL)
EricLew	0:80ee8f3b695e	324	/**
EricLew	0:80ee8f3b695e	325	* @}
EricLew	0:80ee8f3b695e	326	*/
EricLew	0:80ee8f3b695e	327
EricLew	0:80ee8f3b695e	328	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
EricLew	0:80ee8f3b695e	329	* @{
EricLew	0:80ee8f3b695e	330	*/
EricLew	0:80ee8f3b695e	331	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| 0x00000000)
EricLew	0:80ee8f3b695e	332	#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL_0)
EricLew	0:80ee8f3b695e	333	#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL_1)
EricLew	0:80ee8f3b695e	334	#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART4SEL << 16) \| RCC_CCIPR_UART4SEL)
EricLew	0:80ee8f3b695e	335	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| 0x00000000)
EricLew	0:80ee8f3b695e	336	#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL_0)
EricLew	0:80ee8f3b695e	337	#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL_1)
EricLew	0:80ee8f3b695e	338	#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_UART5SEL << 16) \| RCC_CCIPR_UART5SEL)
EricLew	0:80ee8f3b695e	339	/**
EricLew	0:80ee8f3b695e	340	* @}
EricLew	0:80ee8f3b695e	341	*/
EricLew	0:80ee8f3b695e	342
EricLew	0:80ee8f3b695e	343	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
EricLew	0:80ee8f3b695e	344	* @{
EricLew	0:80ee8f3b695e	345	*/
EricLew	0:80ee8f3b695e	346	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 (uint32_t)0x00000000
EricLew	0:80ee8f3b695e	347	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
EricLew	0:80ee8f3b695e	348	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
EricLew	0:80ee8f3b695e	349	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL
EricLew	0:80ee8f3b695e	350	/**
EricLew	0:80ee8f3b695e	351	* @}
EricLew	0:80ee8f3b695e	352	*/
EricLew	0:80ee8f3b695e	353
EricLew	0:80ee8f3b695e	354	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
EricLew	0:80ee8f3b695e	355	* @{
EricLew	0:80ee8f3b695e	356	*/
EricLew	0:80ee8f3b695e	357	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (0x00000000 >> 4))
EricLew	0:80ee8f3b695e	358	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (RCC_CCIPR_I2C1SEL_0 >> 4))
EricLew	0:80ee8f3b695e	359	#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4) \| (RCC_CCIPR_I2C1SEL_1 >> 4))
EricLew	0:80ee8f3b695e	360	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (0x00000000 >> 4))
EricLew	0:80ee8f3b695e	361	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (RCC_CCIPR_I2C2SEL_0 >> 4))
EricLew	0:80ee8f3b695e	362	#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C2SEL << 4) \| (RCC_CCIPR_I2C2SEL_1 >> 4))
EricLew	0:80ee8f3b695e	363	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (0x00000000 >> 4))
EricLew	0:80ee8f3b695e	364	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (RCC_CCIPR_I2C3SEL_0 >> 4))
EricLew	0:80ee8f3b695e	365	#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4) \| (RCC_CCIPR_I2C3SEL_1 >> 4))
EricLew	0:80ee8f3b695e	366	/**
EricLew	0:80ee8f3b695e	367	* @}
EricLew	0:80ee8f3b695e	368	*/
EricLew	0:80ee8f3b695e	369
EricLew	0:80ee8f3b695e	370	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
EricLew	0:80ee8f3b695e	371	* @{
EricLew	0:80ee8f3b695e	372	*/
EricLew	0:80ee8f3b695e	373	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (0x00000000 >> 16))
EricLew	0:80ee8f3b695e	374	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16))
EricLew	0:80ee8f3b695e	375	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16))
EricLew	0:80ee8f3b695e	376	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16))
EricLew	0:80ee8f3b695e	377	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (0x00000000 >> 16))
EricLew	0:80ee8f3b695e	378	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16))
EricLew	0:80ee8f3b695e	379	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16))
EricLew	0:80ee8f3b695e	380	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (uint32_t)(RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16))
EricLew	0:80ee8f3b695e	381	/**
EricLew	0:80ee8f3b695e	382	* @}
EricLew	0:80ee8f3b695e	383	*/
EricLew	0:80ee8f3b695e	384
EricLew	0:80ee8f3b695e	385	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
EricLew	0:80ee8f3b695e	386	* @{
EricLew	0:80ee8f3b695e	387	*/
EricLew	0:80ee8f3b695e	388	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI1SEL \| (0x00000000 >> 16))
EricLew	0:80ee8f3b695e	389	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16))
EricLew	0:80ee8f3b695e	390	#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16))
EricLew	0:80ee8f3b695e	391	#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16))
EricLew	0:80ee8f3b695e	392	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_SAI2SEL \| (0x00000000 >> 16))
EricLew	0:80ee8f3b695e	393	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16))
EricLew	0:80ee8f3b695e	394	#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16))
EricLew	0:80ee8f3b695e	395	#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16))
EricLew	0:80ee8f3b695e	396	/**
EricLew	0:80ee8f3b695e	397	* @}
EricLew	0:80ee8f3b695e	398	*/
EricLew	0:80ee8f3b695e	399
EricLew	0:80ee8f3b695e	400	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
EricLew	0:80ee8f3b695e	401	* @{
EricLew	0:80ee8f3b695e	402	*/
EricLew	0:80ee8f3b695e	403	#define LL_RCC_SDMMC1_CLKSOURCE_NONE (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	404	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
EricLew	0:80ee8f3b695e	405	#define LL_RCC_SDMMC1_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
EricLew	0:80ee8f3b695e	406	#define LL_RCC_SDMMC1_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
EricLew	0:80ee8f3b695e	407	/**
EricLew	0:80ee8f3b695e	408	* @}
EricLew	0:80ee8f3b695e	409	*/
EricLew	0:80ee8f3b695e	410
EricLew	0:80ee8f3b695e	411	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
EricLew	0:80ee8f3b695e	412	* @{
EricLew	0:80ee8f3b695e	413	*/
EricLew	0:80ee8f3b695e	414	#define LL_RCC_RNG_CLKSOURCE_NONE (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	415	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
EricLew	0:80ee8f3b695e	416	#define LL_RCC_RNG_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
EricLew	0:80ee8f3b695e	417	#define LL_RCC_RNG_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
EricLew	0:80ee8f3b695e	418	/**
EricLew	0:80ee8f3b695e	419	* @}
EricLew	0:80ee8f3b695e	420	*/
EricLew	0:80ee8f3b695e	421
EricLew	0:80ee8f3b695e	422	#if defined(USB_OTG_FS)
EricLew	0:80ee8f3b695e	423	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
EricLew	0:80ee8f3b695e	424	* @{
EricLew	0:80ee8f3b695e	425	*/
EricLew	0:80ee8f3b695e	426	#define LL_RCC_USB_CLKSOURCE_NONE (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	427	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_CLK48SEL_0)
EricLew	0:80ee8f3b695e	428	#define LL_RCC_USB_CLKSOURCE_PLL (uint32_t)(RCC_CCIPR_CLK48SEL_1)
EricLew	0:80ee8f3b695e	429	#define LL_RCC_USB_CLKSOURCE_MSI (uint32_t)(RCC_CCIPR_CLK48SEL)
EricLew	0:80ee8f3b695e	430	/**
EricLew	0:80ee8f3b695e	431	* @}
EricLew	0:80ee8f3b695e	432	*/
EricLew	0:80ee8f3b695e	433
EricLew	0:80ee8f3b695e	434	#endif /* USB_OTG_FS */
EricLew	0:80ee8f3b695e	435
EricLew	0:80ee8f3b695e	436	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
EricLew	0:80ee8f3b695e	437	* @{
EricLew	0:80ee8f3b695e	438	*/
EricLew	0:80ee8f3b695e	439	#define LL_RCC_ADC_CLKSOURCE_NONE (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	440	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 (uint32_t)(RCC_CCIPR_ADCSEL_0)
EricLew	0:80ee8f3b695e	441	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 (uint32_t)(RCC_CCIPR_ADCSEL_1)
EricLew	0:80ee8f3b695e	442	#define LL_RCC_ADC_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_ADCSEL)
EricLew	0:80ee8f3b695e	443	/**
EricLew	0:80ee8f3b695e	444	* @}
EricLew	0:80ee8f3b695e	445	*/
EricLew	0:80ee8f3b695e	446
EricLew	0:80ee8f3b695e	447	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI clock source selection
EricLew	0:80ee8f3b695e	448	* @{
EricLew	0:80ee8f3b695e	449	*/
EricLew	0:80ee8f3b695e	450	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	451	#define LL_RCC_SWPMI1_CLKSOURCE_HSI (uint32_t)(RCC_CCIPR_SWPMI1SEL)
EricLew	0:80ee8f3b695e	452	/**
EricLew	0:80ee8f3b695e	453	* @}
EricLew	0:80ee8f3b695e	454	*/
EricLew	0:80ee8f3b695e	455
EricLew	0:80ee8f3b695e	456	/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
EricLew	0:80ee8f3b695e	457	* @{
EricLew	0:80ee8f3b695e	458	*/
EricLew	0:80ee8f3b695e	459	#define LL_RCC_DFSDM_CLKSOURCE_PCLK (uint32_t)(0x00000000)
EricLew	0:80ee8f3b695e	460	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK (uint32_t)(RCC_CCIPR_DFSDMSEL)
EricLew	0:80ee8f3b695e	461	/**
EricLew	0:80ee8f3b695e	462	* @}
EricLew	0:80ee8f3b695e	463	*/
EricLew	0:80ee8f3b695e	464
EricLew	0:80ee8f3b695e	465	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
EricLew	0:80ee8f3b695e	466	* @{
EricLew	0:80ee8f3b695e	467	*/
EricLew	0:80ee8f3b695e	468	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL
EricLew	0:80ee8f3b695e	469	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL
EricLew	0:80ee8f3b695e	470	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL
EricLew	0:80ee8f3b695e	471	/**
EricLew	0:80ee8f3b695e	472	* @}
EricLew	0:80ee8f3b695e	473	*/
EricLew	0:80ee8f3b695e	474
EricLew	0:80ee8f3b695e	475	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
EricLew	0:80ee8f3b695e	476	* @{
EricLew	0:80ee8f3b695e	477	*/
EricLew	0:80ee8f3b695e	478	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL
EricLew	0:80ee8f3b695e	479	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL
EricLew	0:80ee8f3b695e	480	/**
EricLew	0:80ee8f3b695e	481	* @}
EricLew	0:80ee8f3b695e	482	*/
EricLew	0:80ee8f3b695e	483
EricLew	0:80ee8f3b695e	484	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
EricLew	0:80ee8f3b695e	485	* @{
EricLew	0:80ee8f3b695e	486	*/
EricLew	0:80ee8f3b695e	487	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL
EricLew	0:80ee8f3b695e	488	/**
EricLew	0:80ee8f3b695e	489	* @}
EricLew	0:80ee8f3b695e	490	*/
EricLew	0:80ee8f3b695e	491
EricLew	0:80ee8f3b695e	492	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
EricLew	0:80ee8f3b695e	493	* @{
EricLew	0:80ee8f3b695e	494	*/
EricLew	0:80ee8f3b695e	495	#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL
EricLew	0:80ee8f3b695e	496	#define LL_RCC_I2C2_CLKSOURCE RCC_CCIPR_I2C2SEL
EricLew	0:80ee8f3b695e	497	#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL
EricLew	0:80ee8f3b695e	498	/**
EricLew	0:80ee8f3b695e	499	* @}
EricLew	0:80ee8f3b695e	500	*/
EricLew	0:80ee8f3b695e	501
EricLew	0:80ee8f3b695e	502	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
EricLew	0:80ee8f3b695e	503	* @{
EricLew	0:80ee8f3b695e	504	*/
EricLew	0:80ee8f3b695e	505	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL
EricLew	0:80ee8f3b695e	506	/**
EricLew	0:80ee8f3b695e	507	* @}
EricLew	0:80ee8f3b695e	508	*/
EricLew	0:80ee8f3b695e	509
EricLew	0:80ee8f3b695e	510	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
EricLew	0:80ee8f3b695e	511	* @{
EricLew	0:80ee8f3b695e	512	*/
EricLew	0:80ee8f3b695e	513	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL
EricLew	0:80ee8f3b695e	514	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL
EricLew	0:80ee8f3b695e	515	/**
EricLew	0:80ee8f3b695e	516	* @}
EricLew	0:80ee8f3b695e	517	*/
EricLew	0:80ee8f3b695e	518
EricLew	0:80ee8f3b695e	519	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
EricLew	0:80ee8f3b695e	520	* @{
EricLew	0:80ee8f3b695e	521	*/
EricLew	0:80ee8f3b695e	522	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	523	/**
EricLew	0:80ee8f3b695e	524	* @}
EricLew	0:80ee8f3b695e	525	*/
EricLew	0:80ee8f3b695e	526
EricLew	0:80ee8f3b695e	527	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
EricLew	0:80ee8f3b695e	528	* @{
EricLew	0:80ee8f3b695e	529	*/
EricLew	0:80ee8f3b695e	530	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	531	/**
EricLew	0:80ee8f3b695e	532	* @}
EricLew	0:80ee8f3b695e	533	*/
EricLew	0:80ee8f3b695e	534
EricLew	0:80ee8f3b695e	535	#if defined(USB_OTG_FS)
EricLew	0:80ee8f3b695e	536	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
EricLew	0:80ee8f3b695e	537	* @{
EricLew	0:80ee8f3b695e	538	*/
EricLew	0:80ee8f3b695e	539	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	540	/**
EricLew	0:80ee8f3b695e	541	* @}
EricLew	0:80ee8f3b695e	542	*/
EricLew	0:80ee8f3b695e	543
EricLew	0:80ee8f3b695e	544	#endif /* USB_OTG_FS */
EricLew	0:80ee8f3b695e	545
EricLew	0:80ee8f3b695e	546	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
EricLew	0:80ee8f3b695e	547	* @{
EricLew	0:80ee8f3b695e	548	*/
EricLew	0:80ee8f3b695e	549	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL
EricLew	0:80ee8f3b695e	550	/**
EricLew	0:80ee8f3b695e	551	* @}
EricLew	0:80ee8f3b695e	552	*/
EricLew	0:80ee8f3b695e	553
EricLew	0:80ee8f3b695e	554	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI get clock source
EricLew	0:80ee8f3b695e	555	* @{
EricLew	0:80ee8f3b695e	556	*/
EricLew	0:80ee8f3b695e	557	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL
EricLew	0:80ee8f3b695e	558	/**
EricLew	0:80ee8f3b695e	559	* @}
EricLew	0:80ee8f3b695e	560	*/
EricLew	0:80ee8f3b695e	561
EricLew	0:80ee8f3b695e	562	/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
EricLew	0:80ee8f3b695e	563	* @{
EricLew	0:80ee8f3b695e	564	*/
EricLew	0:80ee8f3b695e	565	#define LL_RCC_DFSDM_CLKSOURCE RCC_CCIPR_DFSDMSEL
EricLew	0:80ee8f3b695e	566	/**
EricLew	0:80ee8f3b695e	567	* @}
EricLew	0:80ee8f3b695e	568	*/
EricLew	0:80ee8f3b695e	569
EricLew	0:80ee8f3b695e	570	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
EricLew	0:80ee8f3b695e	571	* @{
EricLew	0:80ee8f3b695e	572	*/
EricLew	0:80ee8f3b695e	573	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000) /!< No clock used as RTC clock /
EricLew	0:80ee8f3b695e	574	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
EricLew	0:80ee8f3b695e	575	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
EricLew	0:80ee8f3b695e	576	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
EricLew	0:80ee8f3b695e	577	/**
EricLew	0:80ee8f3b695e	578	* @}
EricLew	0:80ee8f3b695e	579	*/
EricLew	0:80ee8f3b695e	580
EricLew	0:80ee8f3b695e	581	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
EricLew	0:80ee8f3b695e	582	* @{
EricLew	0:80ee8f3b695e	583	*/
EricLew	0:80ee8f3b695e	584	#define LL_RCC_PLLSOURCE_NONE (uint32_t)0x00000000 /!< No clock /
EricLew	0:80ee8f3b695e	585	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	586	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	587	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
EricLew	0:80ee8f3b695e	588	/**
EricLew	0:80ee8f3b695e	589	* @}
EricLew	0:80ee8f3b695e	590	*/
EricLew	0:80ee8f3b695e	591
EricLew	0:80ee8f3b695e	592	/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLSAI1 and PLLSAI2 division factor
EricLew	0:80ee8f3b695e	593	* @{
EricLew	0:80ee8f3b695e	594	*/
EricLew	0:80ee8f3b695e	595	#define LL_RCC_PLLM_DIV_1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	596	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0)
EricLew	0:80ee8f3b695e	597	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1)
EricLew	0:80ee8f3b695e	598	#define LL_RCC_PLLM_DIV_4 ((RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0))
EricLew	0:80ee8f3b695e	599	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2)
EricLew	0:80ee8f3b695e	600	#define LL_RCC_PLLM_DIV_6 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0))
EricLew	0:80ee8f3b695e	601	#define LL_RCC_PLLM_DIV_7 ((RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1))
EricLew	0:80ee8f3b695e	602	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM)
EricLew	0:80ee8f3b695e	603	/**
EricLew	0:80ee8f3b695e	604	* @}
EricLew	0:80ee8f3b695e	605	*/
EricLew	0:80ee8f3b695e	606
EricLew	0:80ee8f3b695e	607	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
EricLew	0:80ee8f3b695e	608	* @{
EricLew	0:80ee8f3b695e	609	*/
EricLew	0:80ee8f3b695e	610	#define LL_RCC_PLLR_DIV_2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	611	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0)
EricLew	0:80ee8f3b695e	612	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1)
EricLew	0:80ee8f3b695e	613	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR)
EricLew	0:80ee8f3b695e	614	/**
EricLew	0:80ee8f3b695e	615	* @}
EricLew	0:80ee8f3b695e	616	*/
EricLew	0:80ee8f3b695e	617
EricLew	0:80ee8f3b695e	618	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
EricLew	0:80ee8f3b695e	619	* @{
EricLew	0:80ee8f3b695e	620	*/
EricLew	0:80ee8f3b695e	621	#define LL_RCC_PLLP_DIV_7 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	622	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP)
EricLew	0:80ee8f3b695e	623	/**
EricLew	0:80ee8f3b695e	624	* @}
EricLew	0:80ee8f3b695e	625	*/
EricLew	0:80ee8f3b695e	626
EricLew	0:80ee8f3b695e	627	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
EricLew	0:80ee8f3b695e	628	* @{
EricLew	0:80ee8f3b695e	629	*/
EricLew	0:80ee8f3b695e	630	#define LL_RCC_PLLQ_DIV_2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	631	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0)
EricLew	0:80ee8f3b695e	632	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1)
EricLew	0:80ee8f3b695e	633	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ)
EricLew	0:80ee8f3b695e	634	/**
EricLew	0:80ee8f3b695e	635	* @}
EricLew	0:80ee8f3b695e	636	*/
EricLew	0:80ee8f3b695e	637
EricLew	0:80ee8f3b695e	638	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
EricLew	0:80ee8f3b695e	639	* @{
EricLew	0:80ee8f3b695e	640	*/
EricLew	0:80ee8f3b695e	641	#define LL_RCC_PLLSAI1Q_DIV2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	642	#define LL_RCC_PLLSAI1Q_DIV4 ((uint32_t)0x00200000)
EricLew	0:80ee8f3b695e	643	#define LL_RCC_PLLSAI1Q_DIV6 ((uint32_t)0x00400000)
EricLew	0:80ee8f3b695e	644	#define LL_RCC_PLLSAI1Q_DIV8 (RCC_PLLSAI1CFGR_PLLSAI1Q)
EricLew	0:80ee8f3b695e	645	/**
EricLew	0:80ee8f3b695e	646	* @}
EricLew	0:80ee8f3b695e	647	*/
EricLew	0:80ee8f3b695e	648
EricLew	0:80ee8f3b695e	649	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
EricLew	0:80ee8f3b695e	650	* @{
EricLew	0:80ee8f3b695e	651	*/
EricLew	0:80ee8f3b695e	652	#define LL_RCC_PLLSAI1P_DIV7 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	653	#define LL_RCC_PLLSAI1P_DIV17 (RCC_PLLSAI1CFGR_PLLSAI1P)
EricLew	0:80ee8f3b695e	654	/**
EricLew	0:80ee8f3b695e	655	* @}
EricLew	0:80ee8f3b695e	656	*/
EricLew	0:80ee8f3b695e	657
EricLew	0:80ee8f3b695e	658	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
EricLew	0:80ee8f3b695e	659	* @{
EricLew	0:80ee8f3b695e	660	*/
EricLew	0:80ee8f3b695e	661	#define LL_RCC_PLLSAI1R_DIV2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	662	#define LL_RCC_PLLSAI1R_DIV4 ((uint32_t)0x02000000)
EricLew	0:80ee8f3b695e	663	#define LL_RCC_PLLSAI1R_DIV6 ((uint32_t)0x04000000)
EricLew	0:80ee8f3b695e	664	#define LL_RCC_PLLSAI1R_DIV8 (RCC_PLLSAI1CFGR_PLLSAI1R)
EricLew	0:80ee8f3b695e	665	/**
EricLew	0:80ee8f3b695e	666	* @}
EricLew	0:80ee8f3b695e	667	*/
EricLew	0:80ee8f3b695e	668
EricLew	0:80ee8f3b695e	669	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
EricLew	0:80ee8f3b695e	670	* @{
EricLew	0:80ee8f3b695e	671	*/
EricLew	0:80ee8f3b695e	672	#define LL_RCC_PLLSAI2P_DIV7 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	673	#define LL_RCC_PLLSAI2P_DIV17 (RCC_PLLSAI2CFGR_PLLSAI2P)
EricLew	0:80ee8f3b695e	674	/**
EricLew	0:80ee8f3b695e	675	* @}
EricLew	0:80ee8f3b695e	676	*/
EricLew	0:80ee8f3b695e	677
EricLew	0:80ee8f3b695e	678	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
EricLew	0:80ee8f3b695e	679	* @{
EricLew	0:80ee8f3b695e	680	*/
EricLew	0:80ee8f3b695e	681	#define LL_RCC_PLLSAI2R_DIV2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	682	#define LL_RCC_PLLSAI2R_DIV4 (((uint32_t)0x02000000))
EricLew	0:80ee8f3b695e	683	#define LL_RCC_PLLSAI2R_DIV6 (((uint32_t)0x04000000))
EricLew	0:80ee8f3b695e	684	#define LL_RCC_PLLSAI2R_DIV8 (RCC_PLLSAI2CFGR_PLLSAI2R)
EricLew	0:80ee8f3b695e	685	/**
EricLew	0:80ee8f3b695e	686	* @}
EricLew	0:80ee8f3b695e	687	*/
EricLew	0:80ee8f3b695e	688
EricLew	0:80ee8f3b695e	689	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
EricLew	0:80ee8f3b695e	690	* @{
EricLew	0:80ee8f3b695e	691	*/
EricLew	0:80ee8f3b695e	692	#define LL_RCC_MSIRANGESEL_STANDBY (uint32_t)0 /!< MSI Range is provided by MSISRANGE /
EricLew	0:80ee8f3b695e	693	#define LL_RCC_MSIRANGESEL_RUN (uint32_t)1 /!< MSI Range is provided by MSIRANGE /
EricLew	0:80ee8f3b695e	694	/**
EricLew	0:80ee8f3b695e	695	* @}
EricLew	0:80ee8f3b695e	696	*/
EricLew	0:80ee8f3b695e	697
EricLew	0:80ee8f3b695e	698	/**
EricLew	0:80ee8f3b695e	699	* @}
EricLew	0:80ee8f3b695e	700	*/
EricLew	0:80ee8f3b695e	701
EricLew	0:80ee8f3b695e	702	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	703	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
EricLew	0:80ee8f3b695e	704	* @{
EricLew	0:80ee8f3b695e	705	*/
EricLew	0:80ee8f3b695e	706
EricLew	0:80ee8f3b695e	707	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
EricLew	0:80ee8f3b695e	708	* @{
EricLew	0:80ee8f3b695e	709	*/
EricLew	0:80ee8f3b695e	710
EricLew	0:80ee8f3b695e	711	/**
EricLew	0:80ee8f3b695e	712	* @brief Write a value in RCC register
EricLew	0:80ee8f3b695e	713	* @param __REG__ Register to be written
EricLew	0:80ee8f3b695e	714	* @param __VALUE__ Value to be written in the register
EricLew	0:80ee8f3b695e	715	* @retval None
EricLew	0:80ee8f3b695e	716	*/
EricLew	0:80ee8f3b695e	717	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
EricLew	0:80ee8f3b695e	718
EricLew	0:80ee8f3b695e	719	/**
EricLew	0:80ee8f3b695e	720	* @brief Read a value in RCC register
EricLew	0:80ee8f3b695e	721	* @param __REG__ Register to be read
EricLew	0:80ee8f3b695e	722	* @retval Register value
EricLew	0:80ee8f3b695e	723	*/
EricLew	0:80ee8f3b695e	724	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
EricLew	0:80ee8f3b695e	725	/**
EricLew	0:80ee8f3b695e	726	* @}
EricLew	0:80ee8f3b695e	727	*/
EricLew	0:80ee8f3b695e	728
EricLew	0:80ee8f3b695e	729	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
EricLew	0:80ee8f3b695e	730	* @{
EricLew	0:80ee8f3b695e	731	*/
EricLew	0:80ee8f3b695e	732
EricLew	0:80ee8f3b695e	733	/**
EricLew	0:80ee8f3b695e	734	* @brief Helper macro to calculate the PLLCLK frequency
EricLew	0:80ee8f3b695e	735	* @note ex: __LL_RCC_CALC_PLLCLK_FREQ(HSE_VALUE,LL_RCC_PLL_GetDivider(),
EricLew	0:80ee8f3b695e	736	* LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
EricLew	0:80ee8f3b695e	737	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
EricLew	0:80ee8f3b695e	738	* @param __PLLM__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	739	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	740	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	741	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	742	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	743	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	744	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	745	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	746	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	747	* @param __PLLN__ Between 8 and 86
EricLew	0:80ee8f3b695e	748	* @param __PLLR__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	749	* @arg @ref LL_RCC_PLLR_DIV_2
EricLew	0:80ee8f3b695e	750	* @arg @ref LL_RCC_PLLR_DIV_4
EricLew	0:80ee8f3b695e	751	* @arg @ref LL_RCC_PLLR_DIV_6
EricLew	0:80ee8f3b695e	752	* @arg @ref LL_RCC_PLLR_DIV_8
EricLew	0:80ee8f3b695e	753	* @retval PLL clock frequency (in Hz)
EricLew	0:80ee8f3b695e	754	*/
EricLew	0:80ee8f3b695e	755	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> 4) + 1)) * (__PLLN__) / \
EricLew	0:80ee8f3b695e	756	((((__PLLR__) >> 25 ) + 1 ) * 2))
EricLew	0:80ee8f3b695e	757
EricLew	0:80ee8f3b695e	758	/**
EricLew	0:80ee8f3b695e	759	* @brief Helper macro to calculate the HCLK frequency
EricLew	0:80ee8f3b695e	760	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
EricLew	0:80ee8f3b695e	761	* @param __AHBPRESCALER__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	762	* @arg @ref LL_RCC_SYSCLK_DIV_1
EricLew	0:80ee8f3b695e	763	* @arg @ref LL_RCC_SYSCLK_DIV_2
EricLew	0:80ee8f3b695e	764	* @arg @ref LL_RCC_SYSCLK_DIV_4
EricLew	0:80ee8f3b695e	765	* @arg @ref LL_RCC_SYSCLK_DIV_8
EricLew	0:80ee8f3b695e	766	* @arg @ref LL_RCC_SYSCLK_DIV_16
EricLew	0:80ee8f3b695e	767	* @arg @ref LL_RCC_SYSCLK_DIV_64
EricLew	0:80ee8f3b695e	768	* @arg @ref LL_RCC_SYSCLK_DIV_128
EricLew	0:80ee8f3b695e	769	* @arg @ref LL_RCC_SYSCLK_DIV_256
EricLew	0:80ee8f3b695e	770	* @arg @ref LL_RCC_SYSCLK_DIV_512
EricLew	0:80ee8f3b695e	771	* @retval HCLK clock frequency (in Hz)
EricLew	0:80ee8f3b695e	772	*/
EricLew	0:80ee8f3b695e	773	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[(__AHBPRESCALER__) >> RCC_POSITION_HPRE])
EricLew	0:80ee8f3b695e	774
EricLew	0:80ee8f3b695e	775	/**
EricLew	0:80ee8f3b695e	776	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
EricLew	0:80ee8f3b695e	777	* @param __HCLKFREQ__ HCLK frequency
EricLew	0:80ee8f3b695e	778	* @param __APB1PRESCALER__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	779	* @arg @ref LL_RCC_APB1_DIV_1
EricLew	0:80ee8f3b695e	780	* @arg @ref LL_RCC_APB1_DIV_2
EricLew	0:80ee8f3b695e	781	* @arg @ref LL_RCC_APB1_DIV_4
EricLew	0:80ee8f3b695e	782	* @arg @ref LL_RCC_APB1_DIV_8
EricLew	0:80ee8f3b695e	783	* @arg @ref LL_RCC_APB1_DIV_16
EricLew	0:80ee8f3b695e	784	* @retval PCLK1 clock frequency (in Hz)
EricLew	0:80ee8f3b695e	785	*/
EricLew	0:80ee8f3b695e	786	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
EricLew	0:80ee8f3b695e	787
EricLew	0:80ee8f3b695e	788	/**
EricLew	0:80ee8f3b695e	789	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
EricLew	0:80ee8f3b695e	790	* @param __HCLKFREQ__ HCLK frequency
EricLew	0:80ee8f3b695e	791	* @param __APB2PRESCALER__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	792	* @arg @ref LL_RCC_APB2_DIV_1
EricLew	0:80ee8f3b695e	793	* @arg @ref LL_RCC_APB2_DIV_2
EricLew	0:80ee8f3b695e	794	* @arg @ref LL_RCC_APB2_DIV_4
EricLew	0:80ee8f3b695e	795	* @arg @ref LL_RCC_APB2_DIV_8
EricLew	0:80ee8f3b695e	796	* @arg @ref LL_RCC_APB2_DIV_16
EricLew	0:80ee8f3b695e	797	* @retval PCLK2 clock frequency (in Hz)
EricLew	0:80ee8f3b695e	798	*/
EricLew	0:80ee8f3b695e	799	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> aRCC_APBAHBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
EricLew	0:80ee8f3b695e	800
EricLew	0:80ee8f3b695e	801	/**
EricLew	0:80ee8f3b695e	802	* @brief Helper macro to calculate the MSI frequency (in Hz)
EricLew	0:80ee8f3b695e	803	* @note: __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect
EricLew	0:80ee8f3b695e	804	* @note: if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
EricLew	0:80ee8f3b695e	805	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby
EricLew	0:80ee8f3b695e	806	* else by LL_RCC_MSI_GetRange
EricLew	0:80ee8f3b695e	807	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
EricLew	0:80ee8f3b695e	808	* (LL_RCC_MSI_IsEnabledRangeSelect()?
EricLew	0:80ee8f3b695e	809	* LL_RCC_MSI_GetRange():
EricLew	0:80ee8f3b695e	810	* LL_RCC_MSI_GetRangeAfterStandby())
EricLew	0:80ee8f3b695e	811	* @param __MSISEL__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	812	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
EricLew	0:80ee8f3b695e	813	* @arg @ref LL_RCC_MSIRANGESEL_RUN
EricLew	0:80ee8f3b695e	814	* @param __MSIRANGE__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	815	* @arg @ref LL_RCC_MSIRANGE_0
EricLew	0:80ee8f3b695e	816	* @arg @ref LL_RCC_MSIRANGE_1
EricLew	0:80ee8f3b695e	817	* @arg @ref LL_RCC_MSIRANGE_2
EricLew	0:80ee8f3b695e	818	* @arg @ref LL_RCC_MSIRANGE_3
EricLew	0:80ee8f3b695e	819	* @arg @ref LL_RCC_MSIRANGE_4
EricLew	0:80ee8f3b695e	820	* @arg @ref LL_RCC_MSIRANGE_5
EricLew	0:80ee8f3b695e	821	* @arg @ref LL_RCC_MSIRANGE_6
EricLew	0:80ee8f3b695e	822	* @arg @ref LL_RCC_MSIRANGE_7
EricLew	0:80ee8f3b695e	823	* @arg @ref LL_RCC_MSIRANGE_8
EricLew	0:80ee8f3b695e	824	* @arg @ref LL_RCC_MSIRANGE_9
EricLew	0:80ee8f3b695e	825	* @arg @ref LL_RCC_MSIRANGE_10
EricLew	0:80ee8f3b695e	826	* @arg @ref LL_RCC_MSIRANGE_11
EricLew	0:80ee8f3b695e	827	* @arg @ref LL_RCC_MSISRANGE_4
EricLew	0:80ee8f3b695e	828	* @arg @ref LL_RCC_MSISRANGE_5
EricLew	0:80ee8f3b695e	829	* @arg @ref LL_RCC_MSISRANGE_6
EricLew	0:80ee8f3b695e	830	* @arg @ref LL_RCC_MSISRANGE_7
EricLew	0:80ee8f3b695e	831	* @retval MSI clock frequency (in Hz)
EricLew	0:80ee8f3b695e	832	*/
EricLew	0:80ee8f3b695e	833	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
EricLew	0:80ee8f3b695e	834	(MSIRangeTable[(__MSIRANGE__) >> 8]) : \
EricLew	0:80ee8f3b695e	835	(MSIRangeTable[(__MSIRANGE__) >> 4]))
EricLew	0:80ee8f3b695e	836
EricLew	0:80ee8f3b695e	837	/**
EricLew	0:80ee8f3b695e	838	* @}
EricLew	0:80ee8f3b695e	839	*/
EricLew	0:80ee8f3b695e	840
EricLew	0:80ee8f3b695e	841	/**
EricLew	0:80ee8f3b695e	842	* @}
EricLew	0:80ee8f3b695e	843	*/
EricLew	0:80ee8f3b695e	844
EricLew	0:80ee8f3b695e	845	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	846	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
EricLew	0:80ee8f3b695e	847	* @{
EricLew	0:80ee8f3b695e	848	*/
EricLew	0:80ee8f3b695e	849	/** @defgroup RCC_LL_EF_HSE HSE
EricLew	0:80ee8f3b695e	850	* @{
EricLew	0:80ee8f3b695e	851	*/
EricLew	0:80ee8f3b695e	852
EricLew	0:80ee8f3b695e	853	/**
EricLew	0:80ee8f3b695e	854	* @brief Enable the Clock Security System.
EricLew	0:80ee8f3b695e	855	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
EricLew	0:80ee8f3b695e	856	* @retval None
EricLew	0:80ee8f3b695e	857	*/
EricLew	0:80ee8f3b695e	858	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
EricLew	0:80ee8f3b695e	859	{
EricLew	0:80ee8f3b695e	860	SET_BIT(RCC->CR, RCC_CR_CSSON);
EricLew	0:80ee8f3b695e	861	}
EricLew	0:80ee8f3b695e	862
EricLew	0:80ee8f3b695e	863	/**
EricLew	0:80ee8f3b695e	864	* @brief Enable HSE external oscillator (HSE Bypass)
EricLew	0:80ee8f3b695e	865	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
EricLew	0:80ee8f3b695e	866	* @retval None
EricLew	0:80ee8f3b695e	867	*/
EricLew	0:80ee8f3b695e	868	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
EricLew	0:80ee8f3b695e	869	{
EricLew	0:80ee8f3b695e	870	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
EricLew	0:80ee8f3b695e	871	}
EricLew	0:80ee8f3b695e	872
EricLew	0:80ee8f3b695e	873	/**
EricLew	0:80ee8f3b695e	874	* @brief Disable HSE external oscillator (HSE Bypass)
EricLew	0:80ee8f3b695e	875	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
EricLew	0:80ee8f3b695e	876	* @retval None
EricLew	0:80ee8f3b695e	877	*/
EricLew	0:80ee8f3b695e	878	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
EricLew	0:80ee8f3b695e	879	{
EricLew	0:80ee8f3b695e	880	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
EricLew	0:80ee8f3b695e	881	}
EricLew	0:80ee8f3b695e	882
EricLew	0:80ee8f3b695e	883	/**
EricLew	0:80ee8f3b695e	884	* @brief Enable HSE crystal oscillator (HSE ON)
EricLew	0:80ee8f3b695e	885	* @rmtoll CR HSEON LL_RCC_HSE_Enable
EricLew	0:80ee8f3b695e	886	* @retval None
EricLew	0:80ee8f3b695e	887	*/
EricLew	0:80ee8f3b695e	888	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
EricLew	0:80ee8f3b695e	889	{
EricLew	0:80ee8f3b695e	890	SET_BIT(RCC->CR, RCC_CR_HSEON);
EricLew	0:80ee8f3b695e	891	}
EricLew	0:80ee8f3b695e	892
EricLew	0:80ee8f3b695e	893	/**
EricLew	0:80ee8f3b695e	894	* @brief Disable HSE crystal oscillator (HSE ON)
EricLew	0:80ee8f3b695e	895	* @rmtoll CR HSEON LL_RCC_HSE_Disable
EricLew	0:80ee8f3b695e	896	* @retval None
EricLew	0:80ee8f3b695e	897	*/
EricLew	0:80ee8f3b695e	898	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
EricLew	0:80ee8f3b695e	899	{
EricLew	0:80ee8f3b695e	900	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
EricLew	0:80ee8f3b695e	901	}
EricLew	0:80ee8f3b695e	902
EricLew	0:80ee8f3b695e	903	/**
EricLew	0:80ee8f3b695e	904	* @brief Check if HSE oscillator Ready
EricLew	0:80ee8f3b695e	905	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
EricLew	0:80ee8f3b695e	906	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	907	*/
EricLew	0:80ee8f3b695e	908	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
EricLew	0:80ee8f3b695e	909	{
EricLew	0:80ee8f3b695e	910	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
EricLew	0:80ee8f3b695e	911	}
EricLew	0:80ee8f3b695e	912
EricLew	0:80ee8f3b695e	913	/**
EricLew	0:80ee8f3b695e	914	* @}
EricLew	0:80ee8f3b695e	915	*/
EricLew	0:80ee8f3b695e	916
EricLew	0:80ee8f3b695e	917	/** @defgroup RCC_LL_EF_HSI HSI
EricLew	0:80ee8f3b695e	918	* @{
EricLew	0:80ee8f3b695e	919	*/
EricLew	0:80ee8f3b695e	920
EricLew	0:80ee8f3b695e	921	/**
EricLew	0:80ee8f3b695e	922	* @brief Enable HSI even in stop mode
EricLew	0:80ee8f3b695e	923	* @note HSI oscillator is forced ON even in Stop mode
EricLew	0:80ee8f3b695e	924	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
EricLew	0:80ee8f3b695e	925	* @retval None
EricLew	0:80ee8f3b695e	926	*/
EricLew	0:80ee8f3b695e	927	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
EricLew	0:80ee8f3b695e	928	{
EricLew	0:80ee8f3b695e	929	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
EricLew	0:80ee8f3b695e	930	}
EricLew	0:80ee8f3b695e	931
EricLew	0:80ee8f3b695e	932	/**
EricLew	0:80ee8f3b695e	933	* @brief Disable HSI in stop mode
EricLew	0:80ee8f3b695e	934	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
EricLew	0:80ee8f3b695e	935	* @retval None
EricLew	0:80ee8f3b695e	936	*/
EricLew	0:80ee8f3b695e	937	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
EricLew	0:80ee8f3b695e	938	{
EricLew	0:80ee8f3b695e	939	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
EricLew	0:80ee8f3b695e	940	}
EricLew	0:80ee8f3b695e	941
EricLew	0:80ee8f3b695e	942	/**
EricLew	0:80ee8f3b695e	943	* @brief Enable HSI oscillator
EricLew	0:80ee8f3b695e	944	* @rmtoll CR HSION LL_RCC_HSI_Enable
EricLew	0:80ee8f3b695e	945	* @retval None
EricLew	0:80ee8f3b695e	946	*/
EricLew	0:80ee8f3b695e	947	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
EricLew	0:80ee8f3b695e	948	{
EricLew	0:80ee8f3b695e	949	SET_BIT(RCC->CR, RCC_CR_HSION);
EricLew	0:80ee8f3b695e	950	}
EricLew	0:80ee8f3b695e	951
EricLew	0:80ee8f3b695e	952	/**
EricLew	0:80ee8f3b695e	953	* @brief Disable HSI oscillator
EricLew	0:80ee8f3b695e	954	* @rmtoll CR HSION LL_RCC_HSI_Disable
EricLew	0:80ee8f3b695e	955	* @retval None
EricLew	0:80ee8f3b695e	956	*/
EricLew	0:80ee8f3b695e	957	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
EricLew	0:80ee8f3b695e	958	{
EricLew	0:80ee8f3b695e	959	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
EricLew	0:80ee8f3b695e	960	}
EricLew	0:80ee8f3b695e	961
EricLew	0:80ee8f3b695e	962	/**
EricLew	0:80ee8f3b695e	963	* @brief Check if HSI clock divided by 4
EricLew	0:80ee8f3b695e	964	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
EricLew	0:80ee8f3b695e	965	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	966	*/
EricLew	0:80ee8f3b695e	967	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
EricLew	0:80ee8f3b695e	968	{
EricLew	0:80ee8f3b695e	969	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
EricLew	0:80ee8f3b695e	970	}
EricLew	0:80ee8f3b695e	971
EricLew	0:80ee8f3b695e	972	/**
EricLew	0:80ee8f3b695e	973	* @brief Enable HSI Automatic from stop mode
EricLew	0:80ee8f3b695e	974	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
EricLew	0:80ee8f3b695e	975	* @retval None
EricLew	0:80ee8f3b695e	976	*/
EricLew	0:80ee8f3b695e	977	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
EricLew	0:80ee8f3b695e	978	{
EricLew	0:80ee8f3b695e	979	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
EricLew	0:80ee8f3b695e	980	}
EricLew	0:80ee8f3b695e	981
EricLew	0:80ee8f3b695e	982	/**
EricLew	0:80ee8f3b695e	983	* @brief Disable HSI Automatic from stop mode
EricLew	0:80ee8f3b695e	984	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
EricLew	0:80ee8f3b695e	985	* @retval None
EricLew	0:80ee8f3b695e	986	*/
EricLew	0:80ee8f3b695e	987	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
EricLew	0:80ee8f3b695e	988	{
EricLew	0:80ee8f3b695e	989	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
EricLew	0:80ee8f3b695e	990	}
EricLew	0:80ee8f3b695e	991
EricLew	0:80ee8f3b695e	992	/**
EricLew	0:80ee8f3b695e	993	* @brief Get HSI Calibration value
EricLew	0:80ee8f3b695e	994	* @note When HSITRIM is written, HSICAL is updated with the sum of
EricLew	0:80ee8f3b695e	995	* HSITRIM and the factory trim value
EricLew	0:80ee8f3b695e	996	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
EricLew	0:80ee8f3b695e	997	* @retval Between 0x00 and 0xFF
EricLew	0:80ee8f3b695e	998	*/
EricLew	0:80ee8f3b695e	999	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
EricLew	0:80ee8f3b695e	1000	{
EricLew	0:80ee8f3b695e	1001	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
EricLew	0:80ee8f3b695e	1002	}
EricLew	0:80ee8f3b695e	1003
EricLew	0:80ee8f3b695e	1004	/**
EricLew	0:80ee8f3b695e	1005	* @brief Set HSI Calibration trimming
EricLew	0:80ee8f3b695e	1006	* @note user-programmable trimming value that is added to the HSICAL
EricLew	0:80ee8f3b695e	1007	* @note Default value is 16, which, when added to the HSICAL value,
EricLew	0:80ee8f3b695e	1008	* should trim the HSI to 16 MHz +/- 1 %
EricLew	0:80ee8f3b695e	1009	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
EricLew	0:80ee8f3b695e	1010	* @param Value Between 0 and 31
EricLew	0:80ee8f3b695e	1011	* @retval None
EricLew	0:80ee8f3b695e	1012	*/
EricLew	0:80ee8f3b695e	1013	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
EricLew	0:80ee8f3b695e	1014	{
EricLew	0:80ee8f3b695e	1015	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
EricLew	0:80ee8f3b695e	1016	}
EricLew	0:80ee8f3b695e	1017
EricLew	0:80ee8f3b695e	1018	/**
EricLew	0:80ee8f3b695e	1019	* @brief Get HSI Calibration trimming
EricLew	0:80ee8f3b695e	1020	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
EricLew	0:80ee8f3b695e	1021	* @retval Between 0 and 31
EricLew	0:80ee8f3b695e	1022	*/
EricLew	0:80ee8f3b695e	1023	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
EricLew	0:80ee8f3b695e	1024	{
EricLew	0:80ee8f3b695e	1025	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
EricLew	0:80ee8f3b695e	1026	}
EricLew	0:80ee8f3b695e	1027
EricLew	0:80ee8f3b695e	1028	/**
EricLew	0:80ee8f3b695e	1029	* @}
EricLew	0:80ee8f3b695e	1030	*/
EricLew	0:80ee8f3b695e	1031
EricLew	0:80ee8f3b695e	1032	/** @defgroup RCC_LL_EF_LSE LSE
EricLew	0:80ee8f3b695e	1033	* @{
EricLew	0:80ee8f3b695e	1034	*/
EricLew	0:80ee8f3b695e	1035
EricLew	0:80ee8f3b695e	1036	/**
EricLew	0:80ee8f3b695e	1037	* @brief Enable Low Speed External (LSE) crystal.
EricLew	0:80ee8f3b695e	1038	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
EricLew	0:80ee8f3b695e	1039	* @retval None
EricLew	0:80ee8f3b695e	1040	*/
EricLew	0:80ee8f3b695e	1041	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
EricLew	0:80ee8f3b695e	1042	{
EricLew	0:80ee8f3b695e	1043	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
EricLew	0:80ee8f3b695e	1044	}
EricLew	0:80ee8f3b695e	1045
EricLew	0:80ee8f3b695e	1046	/**
EricLew	0:80ee8f3b695e	1047	* @brief Disable Low Speed External (LSE) crystal.
EricLew	0:80ee8f3b695e	1048	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
EricLew	0:80ee8f3b695e	1049	* @retval None
EricLew	0:80ee8f3b695e	1050	*/
EricLew	0:80ee8f3b695e	1051	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
EricLew	0:80ee8f3b695e	1052	{
EricLew	0:80ee8f3b695e	1053	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
EricLew	0:80ee8f3b695e	1054	}
EricLew	0:80ee8f3b695e	1055
EricLew	0:80ee8f3b695e	1056	/**
EricLew	0:80ee8f3b695e	1057	* @brief Enable external clock source (LSE bypass).
EricLew	0:80ee8f3b695e	1058	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
EricLew	0:80ee8f3b695e	1059	* @retval None
EricLew	0:80ee8f3b695e	1060	*/
EricLew	0:80ee8f3b695e	1061	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
EricLew	0:80ee8f3b695e	1062	{
EricLew	0:80ee8f3b695e	1063	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
EricLew	0:80ee8f3b695e	1064	}
EricLew	0:80ee8f3b695e	1065
EricLew	0:80ee8f3b695e	1066	/**
EricLew	0:80ee8f3b695e	1067	* @brief Disable external clock source (LSE bypass).
EricLew	0:80ee8f3b695e	1068	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
EricLew	0:80ee8f3b695e	1069	* @retval None
EricLew	0:80ee8f3b695e	1070	*/
EricLew	0:80ee8f3b695e	1071	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
EricLew	0:80ee8f3b695e	1072	{
EricLew	0:80ee8f3b695e	1073	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
EricLew	0:80ee8f3b695e	1074	}
EricLew	0:80ee8f3b695e	1075
EricLew	0:80ee8f3b695e	1076	/**
EricLew	0:80ee8f3b695e	1077	* @brief Set LSE oscillator drive capability
EricLew	0:80ee8f3b695e	1078	* @note The oscillator is in Xtal mode when it is not in bypass mode.
EricLew	0:80ee8f3b695e	1079	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
EricLew	0:80ee8f3b695e	1080	* @param LSEDrive This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1081	* @arg @ref LL_RCC_LSEDRIVE_LOW
EricLew	0:80ee8f3b695e	1082	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
EricLew	0:80ee8f3b695e	1083	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
EricLew	0:80ee8f3b695e	1084	* @arg @ref LL_RCC_LSEDRIVE_HIGH
EricLew	0:80ee8f3b695e	1085	* @retval None
EricLew	0:80ee8f3b695e	1086	*/
EricLew	0:80ee8f3b695e	1087	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
EricLew	0:80ee8f3b695e	1088	{
EricLew	0:80ee8f3b695e	1089	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
EricLew	0:80ee8f3b695e	1090	}
EricLew	0:80ee8f3b695e	1091
EricLew	0:80ee8f3b695e	1092	/**
EricLew	0:80ee8f3b695e	1093	* @brief Get LSE oscillator drive capability
EricLew	0:80ee8f3b695e	1094	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
EricLew	0:80ee8f3b695e	1095	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1096	* @arg @ref LL_RCC_LSEDRIVE_LOW
EricLew	0:80ee8f3b695e	1097	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
EricLew	0:80ee8f3b695e	1098	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
EricLew	0:80ee8f3b695e	1099	* @arg @ref LL_RCC_LSEDRIVE_HIGH
EricLew	0:80ee8f3b695e	1100	*/
EricLew	0:80ee8f3b695e	1101	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
EricLew	0:80ee8f3b695e	1102	{
EricLew	0:80ee8f3b695e	1103	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
EricLew	0:80ee8f3b695e	1104	}
EricLew	0:80ee8f3b695e	1105
EricLew	0:80ee8f3b695e	1106	/**
EricLew	0:80ee8f3b695e	1107	* @brief Enable Clock security system on LSE.
EricLew	0:80ee8f3b695e	1108	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
EricLew	0:80ee8f3b695e	1109	* @retval None
EricLew	0:80ee8f3b695e	1110	*/
EricLew	0:80ee8f3b695e	1111	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
EricLew	0:80ee8f3b695e	1112	{
EricLew	0:80ee8f3b695e	1113	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
EricLew	0:80ee8f3b695e	1114	}
EricLew	0:80ee8f3b695e	1115
EricLew	0:80ee8f3b695e	1116	/**
EricLew	0:80ee8f3b695e	1117	* @brief Check if LSE oscillator Ready
EricLew	0:80ee8f3b695e	1118	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
EricLew	0:80ee8f3b695e	1119	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1120	*/
EricLew	0:80ee8f3b695e	1121	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
EricLew	0:80ee8f3b695e	1122	{
EricLew	0:80ee8f3b695e	1123	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
EricLew	0:80ee8f3b695e	1124	}
EricLew	0:80ee8f3b695e	1125
EricLew	0:80ee8f3b695e	1126	/**
EricLew	0:80ee8f3b695e	1127	* @brief Check if CSS on LSE failure Detection
EricLew	0:80ee8f3b695e	1128	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
EricLew	0:80ee8f3b695e	1129	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1130	*/
EricLew	0:80ee8f3b695e	1131	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
EricLew	0:80ee8f3b695e	1132	{
EricLew	0:80ee8f3b695e	1133	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
EricLew	0:80ee8f3b695e	1134	}
EricLew	0:80ee8f3b695e	1135
EricLew	0:80ee8f3b695e	1136	/**
EricLew	0:80ee8f3b695e	1137	* @}
EricLew	0:80ee8f3b695e	1138	*/
EricLew	0:80ee8f3b695e	1139
EricLew	0:80ee8f3b695e	1140	/** @defgroup RCC_LL_EF_LSI LSI
EricLew	0:80ee8f3b695e	1141	* @{
EricLew	0:80ee8f3b695e	1142	*/
EricLew	0:80ee8f3b695e	1143
EricLew	0:80ee8f3b695e	1144	/**
EricLew	0:80ee8f3b695e	1145	* @brief Enable LSI Oscillator
EricLew	0:80ee8f3b695e	1146	* @rmtoll CSR LSION LL_RCC_LSI_Enable
EricLew	0:80ee8f3b695e	1147	* @retval None
EricLew	0:80ee8f3b695e	1148	*/
EricLew	0:80ee8f3b695e	1149	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
EricLew	0:80ee8f3b695e	1150	{
EricLew	0:80ee8f3b695e	1151	SET_BIT(RCC->CSR, RCC_CSR_LSION);
EricLew	0:80ee8f3b695e	1152	}
EricLew	0:80ee8f3b695e	1153
EricLew	0:80ee8f3b695e	1154	/**
EricLew	0:80ee8f3b695e	1155	* @brief Disable LSI Oscillator
EricLew	0:80ee8f3b695e	1156	* @rmtoll CSR LSION LL_RCC_LSI_Disable
EricLew	0:80ee8f3b695e	1157	* @retval None
EricLew	0:80ee8f3b695e	1158	*/
EricLew	0:80ee8f3b695e	1159	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
EricLew	0:80ee8f3b695e	1160	{
EricLew	0:80ee8f3b695e	1161	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
EricLew	0:80ee8f3b695e	1162	}
EricLew	0:80ee8f3b695e	1163
EricLew	0:80ee8f3b695e	1164	/**
EricLew	0:80ee8f3b695e	1165	* @brief Check if LSI is Ready
EricLew	0:80ee8f3b695e	1166	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
EricLew	0:80ee8f3b695e	1167	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1168	*/
EricLew	0:80ee8f3b695e	1169	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
EricLew	0:80ee8f3b695e	1170	{
EricLew	0:80ee8f3b695e	1171	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
EricLew	0:80ee8f3b695e	1172	}
EricLew	0:80ee8f3b695e	1173
EricLew	0:80ee8f3b695e	1174	/**
EricLew	0:80ee8f3b695e	1175	* @}
EricLew	0:80ee8f3b695e	1176	*/
EricLew	0:80ee8f3b695e	1177
EricLew	0:80ee8f3b695e	1178	/** @defgroup RCC_LL_EF_MSI MSI
EricLew	0:80ee8f3b695e	1179	* @{
EricLew	0:80ee8f3b695e	1180	*/
EricLew	0:80ee8f3b695e	1181
EricLew	0:80ee8f3b695e	1182	/**
EricLew	0:80ee8f3b695e	1183	* @brief Enable MSI oscillator
EricLew	0:80ee8f3b695e	1184	* @rmtoll CR MSION LL_RCC_MSI_Enable
EricLew	0:80ee8f3b695e	1185	* @retval None
EricLew	0:80ee8f3b695e	1186	*/
EricLew	0:80ee8f3b695e	1187	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
EricLew	0:80ee8f3b695e	1188	{
EricLew	0:80ee8f3b695e	1189	SET_BIT(RCC->CR, RCC_CR_MSION);
EricLew	0:80ee8f3b695e	1190	}
EricLew	0:80ee8f3b695e	1191
EricLew	0:80ee8f3b695e	1192	/**
EricLew	0:80ee8f3b695e	1193	* @brief Disable MSI oscillator
EricLew	0:80ee8f3b695e	1194	* @rmtoll CR MSION LL_RCC_MSI_Disable
EricLew	0:80ee8f3b695e	1195	* @retval None
EricLew	0:80ee8f3b695e	1196	*/
EricLew	0:80ee8f3b695e	1197	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
EricLew	0:80ee8f3b695e	1198	{
EricLew	0:80ee8f3b695e	1199	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
EricLew	0:80ee8f3b695e	1200	}
EricLew	0:80ee8f3b695e	1201
EricLew	0:80ee8f3b695e	1202	/**
EricLew	0:80ee8f3b695e	1203	* @brief Check if MSI oscillator Ready
EricLew	0:80ee8f3b695e	1204	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
EricLew	0:80ee8f3b695e	1205	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1206	*/
EricLew	0:80ee8f3b695e	1207	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
EricLew	0:80ee8f3b695e	1208	{
EricLew	0:80ee8f3b695e	1209	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
EricLew	0:80ee8f3b695e	1210	}
EricLew	0:80ee8f3b695e	1211
EricLew	0:80ee8f3b695e	1212	/**
EricLew	0:80ee8f3b695e	1213	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
EricLew	0:80ee8f3b695e	1214	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
EricLew	0:80ee8f3b695e	1215	* and ready (LSERDY set by hardware)
EricLew	0:80ee8f3b695e	1216	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
EricLew	0:80ee8f3b695e	1217	* ready
EricLew	0:80ee8f3b695e	1218	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
EricLew	0:80ee8f3b695e	1219	* @retval None
EricLew	0:80ee8f3b695e	1220	*/
EricLew	0:80ee8f3b695e	1221	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
EricLew	0:80ee8f3b695e	1222	{
EricLew	0:80ee8f3b695e	1223	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
EricLew	0:80ee8f3b695e	1224	}
EricLew	0:80ee8f3b695e	1225
EricLew	0:80ee8f3b695e	1226	/**
EricLew	0:80ee8f3b695e	1227	* @brief Disable MSI-PLL mode
EricLew	0:80ee8f3b695e	1228	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
EricLew	0:80ee8f3b695e	1229	* the Clock Security System on LSE detects a LSE failure
EricLew	0:80ee8f3b695e	1230	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
EricLew	0:80ee8f3b695e	1231	* @retval None
EricLew	0:80ee8f3b695e	1232	*/
EricLew	0:80ee8f3b695e	1233	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
EricLew	0:80ee8f3b695e	1234	{
EricLew	0:80ee8f3b695e	1235	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
EricLew	0:80ee8f3b695e	1236	}
EricLew	0:80ee8f3b695e	1237
EricLew	0:80ee8f3b695e	1238	/**
EricLew	0:80ee8f3b695e	1239	* @brief Enable MSI clock range selection with MSIRANGE register
EricLew	0:80ee8f3b695e	1240	* @note Write 0 has no effect. After a standby or a reset
EricLew	0:80ee8f3b695e	1241	* MSIRGSEL is at 0 and the MSI range value is provided by
EricLew	0:80ee8f3b695e	1242	* MSISRANGE
EricLew	0:80ee8f3b695e	1243	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
EricLew	0:80ee8f3b695e	1244	* @retval None
EricLew	0:80ee8f3b695e	1245	*/
EricLew	0:80ee8f3b695e	1246	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
EricLew	0:80ee8f3b695e	1247	{
EricLew	0:80ee8f3b695e	1248	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
EricLew	0:80ee8f3b695e	1249	}
EricLew	0:80ee8f3b695e	1250
EricLew	0:80ee8f3b695e	1251	/**
EricLew	0:80ee8f3b695e	1252	* @brief Check if MSI clock range is selected with MSIRANGE register
EricLew	0:80ee8f3b695e	1253	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
EricLew	0:80ee8f3b695e	1254	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1255	*/
EricLew	0:80ee8f3b695e	1256	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
EricLew	0:80ee8f3b695e	1257	{
EricLew	0:80ee8f3b695e	1258	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
EricLew	0:80ee8f3b695e	1259	}
EricLew	0:80ee8f3b695e	1260
EricLew	0:80ee8f3b695e	1261	/**
EricLew	0:80ee8f3b695e	1262	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
EricLew	0:80ee8f3b695e	1263	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
EricLew	0:80ee8f3b695e	1264	* @param Range This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1265	* @arg @ref LL_RCC_MSIRANGE_0
EricLew	0:80ee8f3b695e	1266	* @arg @ref LL_RCC_MSIRANGE_1
EricLew	0:80ee8f3b695e	1267	* @arg @ref LL_RCC_MSIRANGE_2
EricLew	0:80ee8f3b695e	1268	* @arg @ref LL_RCC_MSIRANGE_3
EricLew	0:80ee8f3b695e	1269	* @arg @ref LL_RCC_MSIRANGE_4
EricLew	0:80ee8f3b695e	1270	* @arg @ref LL_RCC_MSIRANGE_5
EricLew	0:80ee8f3b695e	1271	* @arg @ref LL_RCC_MSIRANGE_6
EricLew	0:80ee8f3b695e	1272	* @arg @ref LL_RCC_MSIRANGE_7
EricLew	0:80ee8f3b695e	1273	* @arg @ref LL_RCC_MSIRANGE_8
EricLew	0:80ee8f3b695e	1274	* @arg @ref LL_RCC_MSIRANGE_9
EricLew	0:80ee8f3b695e	1275	* @arg @ref LL_RCC_MSIRANGE_10
EricLew	0:80ee8f3b695e	1276	* @arg @ref LL_RCC_MSIRANGE_11
EricLew	0:80ee8f3b695e	1277	* @retval None
EricLew	0:80ee8f3b695e	1278	*/
EricLew	0:80ee8f3b695e	1279	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
EricLew	0:80ee8f3b695e	1280	{
EricLew	0:80ee8f3b695e	1281	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
EricLew	0:80ee8f3b695e	1282	}
EricLew	0:80ee8f3b695e	1283
EricLew	0:80ee8f3b695e	1284	/**
EricLew	0:80ee8f3b695e	1285	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
EricLew	0:80ee8f3b695e	1286	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
EricLew	0:80ee8f3b695e	1287	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1288	* @arg @ref LL_RCC_MSIRANGE_0
EricLew	0:80ee8f3b695e	1289	* @arg @ref LL_RCC_MSIRANGE_1
EricLew	0:80ee8f3b695e	1290	* @arg @ref LL_RCC_MSIRANGE_2
EricLew	0:80ee8f3b695e	1291	* @arg @ref LL_RCC_MSIRANGE_3
EricLew	0:80ee8f3b695e	1292	* @arg @ref LL_RCC_MSIRANGE_4
EricLew	0:80ee8f3b695e	1293	* @arg @ref LL_RCC_MSIRANGE_5
EricLew	0:80ee8f3b695e	1294	* @arg @ref LL_RCC_MSIRANGE_6
EricLew	0:80ee8f3b695e	1295	* @arg @ref LL_RCC_MSIRANGE_7
EricLew	0:80ee8f3b695e	1296	* @arg @ref LL_RCC_MSIRANGE_8
EricLew	0:80ee8f3b695e	1297	* @arg @ref LL_RCC_MSIRANGE_9
EricLew	0:80ee8f3b695e	1298	* @arg @ref LL_RCC_MSIRANGE_10
EricLew	0:80ee8f3b695e	1299	* @arg @ref LL_RCC_MSIRANGE_11
EricLew	0:80ee8f3b695e	1300	*/
EricLew	0:80ee8f3b695e	1301	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
EricLew	0:80ee8f3b695e	1302	{
EricLew	0:80ee8f3b695e	1303	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
EricLew	0:80ee8f3b695e	1304	}
EricLew	0:80ee8f3b695e	1305
EricLew	0:80ee8f3b695e	1306	/**
EricLew	0:80ee8f3b695e	1307	* @brief Configure MSI range used after standby
EricLew	0:80ee8f3b695e	1308	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
EricLew	0:80ee8f3b695e	1309	* @param Range This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1310	* @arg @ref LL_RCC_MSISRANGE_4
EricLew	0:80ee8f3b695e	1311	* @arg @ref LL_RCC_MSISRANGE_5
EricLew	0:80ee8f3b695e	1312	* @arg @ref LL_RCC_MSISRANGE_6
EricLew	0:80ee8f3b695e	1313	* @arg @ref LL_RCC_MSISRANGE_7
EricLew	0:80ee8f3b695e	1314	* @retval None
EricLew	0:80ee8f3b695e	1315	*/
EricLew	0:80ee8f3b695e	1316	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
EricLew	0:80ee8f3b695e	1317	{
EricLew	0:80ee8f3b695e	1318	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
EricLew	0:80ee8f3b695e	1319	}
EricLew	0:80ee8f3b695e	1320
EricLew	0:80ee8f3b695e	1321	/**
EricLew	0:80ee8f3b695e	1322	* @brief Get MSI range used after standby
EricLew	0:80ee8f3b695e	1323	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
EricLew	0:80ee8f3b695e	1324	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1325	* @arg @ref LL_RCC_MSISRANGE_4
EricLew	0:80ee8f3b695e	1326	* @arg @ref LL_RCC_MSISRANGE_5
EricLew	0:80ee8f3b695e	1327	* @arg @ref LL_RCC_MSISRANGE_6
EricLew	0:80ee8f3b695e	1328	* @arg @ref LL_RCC_MSISRANGE_7
EricLew	0:80ee8f3b695e	1329	*/
EricLew	0:80ee8f3b695e	1330	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
EricLew	0:80ee8f3b695e	1331	{
EricLew	0:80ee8f3b695e	1332	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
EricLew	0:80ee8f3b695e	1333	}
EricLew	0:80ee8f3b695e	1334
EricLew	0:80ee8f3b695e	1335	/**
EricLew	0:80ee8f3b695e	1336	* @brief Get MSI Calibration value
EricLew	0:80ee8f3b695e	1337	* @note When MSITRIM is written, MSICAL is updated with the sum of
EricLew	0:80ee8f3b695e	1338	* MSITRIM and the factory trim value
EricLew	0:80ee8f3b695e	1339	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
EricLew	0:80ee8f3b695e	1340	* @retval Between 0 and 255
EricLew	0:80ee8f3b695e	1341	*/
EricLew	0:80ee8f3b695e	1342	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
EricLew	0:80ee8f3b695e	1343	{
EricLew	0:80ee8f3b695e	1344	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_POSITION_MSICAL);
EricLew	0:80ee8f3b695e	1345	}
EricLew	0:80ee8f3b695e	1346
EricLew	0:80ee8f3b695e	1347	/**
EricLew	0:80ee8f3b695e	1348	* @brief Set MSI Calibration trimming
EricLew	0:80ee8f3b695e	1349	* @note user-programmable trimming value that is added to the MSICAL
EricLew	0:80ee8f3b695e	1350	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
EricLew	0:80ee8f3b695e	1351	* @param Value Between 0 and 255
EricLew	0:80ee8f3b695e	1352	* @retval None
EricLew	0:80ee8f3b695e	1353	*/
EricLew	0:80ee8f3b695e	1354	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
EricLew	0:80ee8f3b695e	1355	{
EricLew	0:80ee8f3b695e	1356	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_POSITION_MSITRIM);
EricLew	0:80ee8f3b695e	1357	}
EricLew	0:80ee8f3b695e	1358
EricLew	0:80ee8f3b695e	1359	/**
EricLew	0:80ee8f3b695e	1360	* @brief Get MSI Calibration trimming
EricLew	0:80ee8f3b695e	1361	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
EricLew	0:80ee8f3b695e	1362	* @retval Between 0 and 255
EricLew	0:80ee8f3b695e	1363	*/
EricLew	0:80ee8f3b695e	1364	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
EricLew	0:80ee8f3b695e	1365	{
EricLew	0:80ee8f3b695e	1366	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_POSITION_MSITRIM);
EricLew	0:80ee8f3b695e	1367	}
EricLew	0:80ee8f3b695e	1368
EricLew	0:80ee8f3b695e	1369	/**
EricLew	0:80ee8f3b695e	1370	* @}
EricLew	0:80ee8f3b695e	1371	*/
EricLew	0:80ee8f3b695e	1372
EricLew	0:80ee8f3b695e	1373	/** @defgroup RCC_LL_EF_LSCO LSCO
EricLew	0:80ee8f3b695e	1374	* @{
EricLew	0:80ee8f3b695e	1375	*/
EricLew	0:80ee8f3b695e	1376
EricLew	0:80ee8f3b695e	1377	/**
EricLew	0:80ee8f3b695e	1378	* @brief Enable Low speed clock
EricLew	0:80ee8f3b695e	1379	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
EricLew	0:80ee8f3b695e	1380	* @retval None
EricLew	0:80ee8f3b695e	1381	*/
EricLew	0:80ee8f3b695e	1382	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
EricLew	0:80ee8f3b695e	1383	{
EricLew	0:80ee8f3b695e	1384	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
EricLew	0:80ee8f3b695e	1385	}
EricLew	0:80ee8f3b695e	1386
EricLew	0:80ee8f3b695e	1387	/**
EricLew	0:80ee8f3b695e	1388	* @brief Disable Low speed clock
EricLew	0:80ee8f3b695e	1389	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
EricLew	0:80ee8f3b695e	1390	* @retval None
EricLew	0:80ee8f3b695e	1391	*/
EricLew	0:80ee8f3b695e	1392	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
EricLew	0:80ee8f3b695e	1393	{
EricLew	0:80ee8f3b695e	1394	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
EricLew	0:80ee8f3b695e	1395	}
EricLew	0:80ee8f3b695e	1396
EricLew	0:80ee8f3b695e	1397	/**
EricLew	0:80ee8f3b695e	1398	* @brief Configure Low speed clock selection
EricLew	0:80ee8f3b695e	1399	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
EricLew	0:80ee8f3b695e	1400	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1401	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1402	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1403	* @retval None
EricLew	0:80ee8f3b695e	1404	*/
EricLew	0:80ee8f3b695e	1405	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
EricLew	0:80ee8f3b695e	1406	{
EricLew	0:80ee8f3b695e	1407	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
EricLew	0:80ee8f3b695e	1408	}
EricLew	0:80ee8f3b695e	1409
EricLew	0:80ee8f3b695e	1410	/**
EricLew	0:80ee8f3b695e	1411	* @brief Get Low speed clock selection
EricLew	0:80ee8f3b695e	1412	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
EricLew	0:80ee8f3b695e	1413	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1414	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1415	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1416	*/
EricLew	0:80ee8f3b695e	1417	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
EricLew	0:80ee8f3b695e	1418	{
EricLew	0:80ee8f3b695e	1419	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
EricLew	0:80ee8f3b695e	1420	}
EricLew	0:80ee8f3b695e	1421
EricLew	0:80ee8f3b695e	1422	/**
EricLew	0:80ee8f3b695e	1423	* @}
EricLew	0:80ee8f3b695e	1424	*/
EricLew	0:80ee8f3b695e	1425
EricLew	0:80ee8f3b695e	1426	/** @defgroup RCC_LL_EF_System System
EricLew	0:80ee8f3b695e	1427	* @{
EricLew	0:80ee8f3b695e	1428	*/
EricLew	0:80ee8f3b695e	1429
EricLew	0:80ee8f3b695e	1430	/**
EricLew	0:80ee8f3b695e	1431	* @brief Configure the system clock source
EricLew	0:80ee8f3b695e	1432	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
EricLew	0:80ee8f3b695e	1433	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1434	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1435	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1436	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
EricLew	0:80ee8f3b695e	1437	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1438	* @retval None
EricLew	0:80ee8f3b695e	1439	*/
EricLew	0:80ee8f3b695e	1440	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
EricLew	0:80ee8f3b695e	1441	{
EricLew	0:80ee8f3b695e	1442	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
EricLew	0:80ee8f3b695e	1443	}
EricLew	0:80ee8f3b695e	1444
EricLew	0:80ee8f3b695e	1445	/**
EricLew	0:80ee8f3b695e	1446	* @brief Get the system clock source
EricLew	0:80ee8f3b695e	1447	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
EricLew	0:80ee8f3b695e	1448	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1449	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
EricLew	0:80ee8f3b695e	1450	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
EricLew	0:80ee8f3b695e	1451	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
EricLew	0:80ee8f3b695e	1452	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
EricLew	0:80ee8f3b695e	1453	*/
EricLew	0:80ee8f3b695e	1454	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
EricLew	0:80ee8f3b695e	1455	{
EricLew	0:80ee8f3b695e	1456	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
EricLew	0:80ee8f3b695e	1457	}
EricLew	0:80ee8f3b695e	1458
EricLew	0:80ee8f3b695e	1459	/**
EricLew	0:80ee8f3b695e	1460	* @brief Set AHB prescaler
EricLew	0:80ee8f3b695e	1461	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
EricLew	0:80ee8f3b695e	1462	* @param Prescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1463	* @arg @ref LL_RCC_SYSCLK_DIV_1
EricLew	0:80ee8f3b695e	1464	* @arg @ref LL_RCC_SYSCLK_DIV_2
EricLew	0:80ee8f3b695e	1465	* @arg @ref LL_RCC_SYSCLK_DIV_4
EricLew	0:80ee8f3b695e	1466	* @arg @ref LL_RCC_SYSCLK_DIV_8
EricLew	0:80ee8f3b695e	1467	* @arg @ref LL_RCC_SYSCLK_DIV_16
EricLew	0:80ee8f3b695e	1468	* @arg @ref LL_RCC_SYSCLK_DIV_64
EricLew	0:80ee8f3b695e	1469	* @arg @ref LL_RCC_SYSCLK_DIV_128
EricLew	0:80ee8f3b695e	1470	* @arg @ref LL_RCC_SYSCLK_DIV_256
EricLew	0:80ee8f3b695e	1471	* @arg @ref LL_RCC_SYSCLK_DIV_512
EricLew	0:80ee8f3b695e	1472	* @retval None
EricLew	0:80ee8f3b695e	1473	*/
EricLew	0:80ee8f3b695e	1474	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
EricLew	0:80ee8f3b695e	1475	{
EricLew	0:80ee8f3b695e	1476	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
EricLew	0:80ee8f3b695e	1477	}
EricLew	0:80ee8f3b695e	1478
EricLew	0:80ee8f3b695e	1479	/**
EricLew	0:80ee8f3b695e	1480	* @brief Set APB1 prescaler
EricLew	0:80ee8f3b695e	1481	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
EricLew	0:80ee8f3b695e	1482	* @param Prescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1483	* @arg @ref LL_RCC_APB1_DIV_1
EricLew	0:80ee8f3b695e	1484	* @arg @ref LL_RCC_APB1_DIV_2
EricLew	0:80ee8f3b695e	1485	* @arg @ref LL_RCC_APB1_DIV_4
EricLew	0:80ee8f3b695e	1486	* @arg @ref LL_RCC_APB1_DIV_8
EricLew	0:80ee8f3b695e	1487	* @arg @ref LL_RCC_APB1_DIV_16
EricLew	0:80ee8f3b695e	1488	* @retval None
EricLew	0:80ee8f3b695e	1489	*/
EricLew	0:80ee8f3b695e	1490	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
EricLew	0:80ee8f3b695e	1491	{
EricLew	0:80ee8f3b695e	1492	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
EricLew	0:80ee8f3b695e	1493	}
EricLew	0:80ee8f3b695e	1494
EricLew	0:80ee8f3b695e	1495	/**
EricLew	0:80ee8f3b695e	1496	* @brief Set APB2 prescaler
EricLew	0:80ee8f3b695e	1497	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
EricLew	0:80ee8f3b695e	1498	* @param Prescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1499	* @arg @ref LL_RCC_APB2_DIV_1
EricLew	0:80ee8f3b695e	1500	* @arg @ref LL_RCC_APB2_DIV_2
EricLew	0:80ee8f3b695e	1501	* @arg @ref LL_RCC_APB2_DIV_4
EricLew	0:80ee8f3b695e	1502	* @arg @ref LL_RCC_APB2_DIV_8
EricLew	0:80ee8f3b695e	1503	* @arg @ref LL_RCC_APB2_DIV_16
EricLew	0:80ee8f3b695e	1504	* @retval None
EricLew	0:80ee8f3b695e	1505	*/
EricLew	0:80ee8f3b695e	1506	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
EricLew	0:80ee8f3b695e	1507	{
EricLew	0:80ee8f3b695e	1508	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
EricLew	0:80ee8f3b695e	1509	}
EricLew	0:80ee8f3b695e	1510
EricLew	0:80ee8f3b695e	1511	/**
EricLew	0:80ee8f3b695e	1512	* @brief Get AHB prescaler
EricLew	0:80ee8f3b695e	1513	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
EricLew	0:80ee8f3b695e	1514	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1515	* @arg @ref LL_RCC_SYSCLK_DIV_1
EricLew	0:80ee8f3b695e	1516	* @arg @ref LL_RCC_SYSCLK_DIV_2
EricLew	0:80ee8f3b695e	1517	* @arg @ref LL_RCC_SYSCLK_DIV_4
EricLew	0:80ee8f3b695e	1518	* @arg @ref LL_RCC_SYSCLK_DIV_8
EricLew	0:80ee8f3b695e	1519	* @arg @ref LL_RCC_SYSCLK_DIV_16
EricLew	0:80ee8f3b695e	1520	* @arg @ref LL_RCC_SYSCLK_DIV_64
EricLew	0:80ee8f3b695e	1521	* @arg @ref LL_RCC_SYSCLK_DIV_128
EricLew	0:80ee8f3b695e	1522	* @arg @ref LL_RCC_SYSCLK_DIV_256
EricLew	0:80ee8f3b695e	1523	* @arg @ref LL_RCC_SYSCLK_DIV_512
EricLew	0:80ee8f3b695e	1524	*/
EricLew	0:80ee8f3b695e	1525	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
EricLew	0:80ee8f3b695e	1526	{
EricLew	0:80ee8f3b695e	1527	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
EricLew	0:80ee8f3b695e	1528	}
EricLew	0:80ee8f3b695e	1529
EricLew	0:80ee8f3b695e	1530	/**
EricLew	0:80ee8f3b695e	1531	* @brief Get APB1 prescaler
EricLew	0:80ee8f3b695e	1532	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
EricLew	0:80ee8f3b695e	1533	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1534	* @arg @ref LL_RCC_APB1_DIV_1
EricLew	0:80ee8f3b695e	1535	* @arg @ref LL_RCC_APB1_DIV_2
EricLew	0:80ee8f3b695e	1536	* @arg @ref LL_RCC_APB1_DIV_4
EricLew	0:80ee8f3b695e	1537	* @arg @ref LL_RCC_APB1_DIV_8
EricLew	0:80ee8f3b695e	1538	* @arg @ref LL_RCC_APB1_DIV_16
EricLew	0:80ee8f3b695e	1539	*/
EricLew	0:80ee8f3b695e	1540	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
EricLew	0:80ee8f3b695e	1541	{
EricLew	0:80ee8f3b695e	1542	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
EricLew	0:80ee8f3b695e	1543	}
EricLew	0:80ee8f3b695e	1544
EricLew	0:80ee8f3b695e	1545	/**
EricLew	0:80ee8f3b695e	1546	* @brief Get APB2 prescaler
EricLew	0:80ee8f3b695e	1547	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
EricLew	0:80ee8f3b695e	1548	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1549	* @arg @ref LL_RCC_APB2_DIV_1
EricLew	0:80ee8f3b695e	1550	* @arg @ref LL_RCC_APB2_DIV_2
EricLew	0:80ee8f3b695e	1551	* @arg @ref LL_RCC_APB2_DIV_4
EricLew	0:80ee8f3b695e	1552	* @arg @ref LL_RCC_APB2_DIV_8
EricLew	0:80ee8f3b695e	1553	* @arg @ref LL_RCC_APB2_DIV_16
EricLew	0:80ee8f3b695e	1554	*/
EricLew	0:80ee8f3b695e	1555	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
EricLew	0:80ee8f3b695e	1556	{
EricLew	0:80ee8f3b695e	1557	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
EricLew	0:80ee8f3b695e	1558	}
EricLew	0:80ee8f3b695e	1559
EricLew	0:80ee8f3b695e	1560	/**
EricLew	0:80ee8f3b695e	1561	* @brief Set Clock After Wake-Up From Stop mode
EricLew	0:80ee8f3b695e	1562	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
EricLew	0:80ee8f3b695e	1563	* @param Clock This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1564	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
EricLew	0:80ee8f3b695e	1565	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
EricLew	0:80ee8f3b695e	1566	* @retval None
EricLew	0:80ee8f3b695e	1567	*/
EricLew	0:80ee8f3b695e	1568	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
EricLew	0:80ee8f3b695e	1569	{
EricLew	0:80ee8f3b695e	1570	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
EricLew	0:80ee8f3b695e	1571	}
EricLew	0:80ee8f3b695e	1572
EricLew	0:80ee8f3b695e	1573	/**
EricLew	0:80ee8f3b695e	1574	* @brief Get Clock After Wake-Up From Stop mode
EricLew	0:80ee8f3b695e	1575	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
EricLew	0:80ee8f3b695e	1576	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1577	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
EricLew	0:80ee8f3b695e	1578	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
EricLew	0:80ee8f3b695e	1579	*/
EricLew	0:80ee8f3b695e	1580	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
EricLew	0:80ee8f3b695e	1581	{
EricLew	0:80ee8f3b695e	1582	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
EricLew	0:80ee8f3b695e	1583	}
EricLew	0:80ee8f3b695e	1584
EricLew	0:80ee8f3b695e	1585	/**
EricLew	0:80ee8f3b695e	1586	* @}
EricLew	0:80ee8f3b695e	1587	*/
EricLew	0:80ee8f3b695e	1588
EricLew	0:80ee8f3b695e	1589	/** @defgroup RCC_LL_EF_MCO MCO
EricLew	0:80ee8f3b695e	1590	* @{
EricLew	0:80ee8f3b695e	1591	*/
EricLew	0:80ee8f3b695e	1592
EricLew	0:80ee8f3b695e	1593	/**
EricLew	0:80ee8f3b695e	1594	* @brief Configure MCOx
EricLew	0:80ee8f3b695e	1595	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
EricLew	0:80ee8f3b695e	1596	* CFGR MCO_PRE LL_RCC_ConfigMCO
EricLew	0:80ee8f3b695e	1597	* @param MCOxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1598	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
EricLew	0:80ee8f3b695e	1599	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1600	* @arg @ref LL_RCC_MCO1SOURCE_MSI
EricLew	0:80ee8f3b695e	1601	* @arg @ref LL_RCC_MCO1SOURCE_HSI
EricLew	0:80ee8f3b695e	1602	* @arg @ref LL_RCC_MCO1SOURCE_HSE
EricLew	0:80ee8f3b695e	1603	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
EricLew	0:80ee8f3b695e	1604	* @arg @ref LL_RCC_MCO1SOURCE_LSI
EricLew	0:80ee8f3b695e	1605	* @arg @ref LL_RCC_MCO1SOURCE_LSE
EricLew	0:80ee8f3b695e	1606	* @param MCOxPrescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1607	* @arg @ref LL_RCC_MCO1_DIV_1
EricLew	0:80ee8f3b695e	1608	* @arg @ref LL_RCC_MCO1_DIV_2
EricLew	0:80ee8f3b695e	1609	* @arg @ref LL_RCC_MCO1_DIV_4
EricLew	0:80ee8f3b695e	1610	* @arg @ref LL_RCC_MCO1_DIV_8
EricLew	0:80ee8f3b695e	1611	* @arg @ref LL_RCC_MCO1_DIV_16
EricLew	0:80ee8f3b695e	1612	* @retval None
EricLew	0:80ee8f3b695e	1613	*/
EricLew	0:80ee8f3b695e	1614	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
EricLew	0:80ee8f3b695e	1615	{
EricLew	0:80ee8f3b695e	1616	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE, MCOxSource \| MCOxPrescaler);
EricLew	0:80ee8f3b695e	1617	}
EricLew	0:80ee8f3b695e	1618
EricLew	0:80ee8f3b695e	1619	/**
EricLew	0:80ee8f3b695e	1620	* @}
EricLew	0:80ee8f3b695e	1621	*/
EricLew	0:80ee8f3b695e	1622
EricLew	0:80ee8f3b695e	1623	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
EricLew	0:80ee8f3b695e	1624	* @{
EricLew	0:80ee8f3b695e	1625	*/
EricLew	0:80ee8f3b695e	1626
EricLew	0:80ee8f3b695e	1627	/**
EricLew	0:80ee8f3b695e	1628	* @brief Configure USARTx clock source
EricLew	0:80ee8f3b695e	1629	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
EricLew	0:80ee8f3b695e	1630	* @param USARTxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1631	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
EricLew	0:80ee8f3b695e	1632	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1633	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1634	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1635	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1636	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1637	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1638	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1639	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1640	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1641	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1642	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1643	* @retval None
EricLew	0:80ee8f3b695e	1644	*/
EricLew	0:80ee8f3b695e	1645	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
EricLew	0:80ee8f3b695e	1646	{
EricLew	0:80ee8f3b695e	1647	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
EricLew	0:80ee8f3b695e	1648	}
EricLew	0:80ee8f3b695e	1649
EricLew	0:80ee8f3b695e	1650	/**
EricLew	0:80ee8f3b695e	1651	* @brief Configure UARTx clock source
EricLew	0:80ee8f3b695e	1652	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
EricLew	0:80ee8f3b695e	1653	* @param UARTxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1654	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1655	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1656	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1657	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1658	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1659	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1660	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1661	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1662	* @retval None
EricLew	0:80ee8f3b695e	1663	*/
EricLew	0:80ee8f3b695e	1664	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
EricLew	0:80ee8f3b695e	1665	{
EricLew	0:80ee8f3b695e	1666	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
EricLew	0:80ee8f3b695e	1667	}
EricLew	0:80ee8f3b695e	1668
EricLew	0:80ee8f3b695e	1669	/**
EricLew	0:80ee8f3b695e	1670	* @brief Configure LPUART1x clock source
EricLew	0:80ee8f3b695e	1671	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
EricLew	0:80ee8f3b695e	1672	* @param LPUARTxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1673	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1674	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1675	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1676	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1677	* @retval None
EricLew	0:80ee8f3b695e	1678	*/
EricLew	0:80ee8f3b695e	1679	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
EricLew	0:80ee8f3b695e	1680	{
EricLew	0:80ee8f3b695e	1681	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
EricLew	0:80ee8f3b695e	1682	}
EricLew	0:80ee8f3b695e	1683
EricLew	0:80ee8f3b695e	1684	/**
EricLew	0:80ee8f3b695e	1685	* @brief Configure I2Cx clock source
EricLew	0:80ee8f3b695e	1686	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
EricLew	0:80ee8f3b695e	1687	* @param I2CxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1688	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1689	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1690	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1691	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1692	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1693	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1694	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1695	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1696	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1697	* @retval None
EricLew	0:80ee8f3b695e	1698	*/
EricLew	0:80ee8f3b695e	1699	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
EricLew	0:80ee8f3b695e	1700	{
EricLew	0:80ee8f3b695e	1701	MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000), ((I2CxSource << 4) & 0x000FF000));
EricLew	0:80ee8f3b695e	1702	}
EricLew	0:80ee8f3b695e	1703
EricLew	0:80ee8f3b695e	1704	/**
EricLew	0:80ee8f3b695e	1705	* @brief Configure LPTIMx clock source
EricLew	0:80ee8f3b695e	1706	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
EricLew	0:80ee8f3b695e	1707	* @param LPTIMxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1708	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1709	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1710	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1711	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1712	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1713	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1714	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1715	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1716	* @retval None
EricLew	0:80ee8f3b695e	1717	*/
EricLew	0:80ee8f3b695e	1718	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
EricLew	0:80ee8f3b695e	1719	{
EricLew	0:80ee8f3b695e	1720	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000), (LPTIMxSource << 16));
EricLew	0:80ee8f3b695e	1721	}
EricLew	0:80ee8f3b695e	1722
EricLew	0:80ee8f3b695e	1723	/**
EricLew	0:80ee8f3b695e	1724	* @brief Configure SAIx clock source
EricLew	0:80ee8f3b695e	1725	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
EricLew	0:80ee8f3b695e	1726	* @param SAIxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1727	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1728	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	1729	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1730	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
EricLew	0:80ee8f3b695e	1731	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1732	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	1733	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1734	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
EricLew	0:80ee8f3b695e	1735	* @retval None
EricLew	0:80ee8f3b695e	1736	*/
EricLew	0:80ee8f3b695e	1737	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
EricLew	0:80ee8f3b695e	1738	{
EricLew	0:80ee8f3b695e	1739	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000), (SAIxSource << 16));
EricLew	0:80ee8f3b695e	1740	}
EricLew	0:80ee8f3b695e	1741
EricLew	0:80ee8f3b695e	1742	/**
EricLew	0:80ee8f3b695e	1743	* @brief Configure SDMMC1 clock source
EricLew	0:80ee8f3b695e	1744	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
EricLew	0:80ee8f3b695e	1745	* @param SDMMCxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1746	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1747	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1748	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1749	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1750	* @retval None
EricLew	0:80ee8f3b695e	1751	*/
EricLew	0:80ee8f3b695e	1752	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
EricLew	0:80ee8f3b695e	1753	{
EricLew	0:80ee8f3b695e	1754	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
EricLew	0:80ee8f3b695e	1755	}
EricLew	0:80ee8f3b695e	1756
EricLew	0:80ee8f3b695e	1757	/**
EricLew	0:80ee8f3b695e	1758	* @brief Configure RNG clock source
EricLew	0:80ee8f3b695e	1759	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
EricLew	0:80ee8f3b695e	1760	* @param RNGxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1761	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1762	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1763	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1764	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1765	* @retval None
EricLew	0:80ee8f3b695e	1766	*/
EricLew	0:80ee8f3b695e	1767	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
EricLew	0:80ee8f3b695e	1768	{
EricLew	0:80ee8f3b695e	1769	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
EricLew	0:80ee8f3b695e	1770	}
EricLew	0:80ee8f3b695e	1771
EricLew	0:80ee8f3b695e	1772	#if defined(USB_OTG_FS)
EricLew	0:80ee8f3b695e	1773	/**
EricLew	0:80ee8f3b695e	1774	* @brief Configure USB clock source
EricLew	0:80ee8f3b695e	1775	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
EricLew	0:80ee8f3b695e	1776	* @param USBxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1777	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1778	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1779	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1780	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1781	* @retval None
EricLew	0:80ee8f3b695e	1782	*/
EricLew	0:80ee8f3b695e	1783	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
EricLew	0:80ee8f3b695e	1784	{
EricLew	0:80ee8f3b695e	1785	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
EricLew	0:80ee8f3b695e	1786	}
EricLew	0:80ee8f3b695e	1787	#endif /* USB_OTG_FS */
EricLew	0:80ee8f3b695e	1788
EricLew	0:80ee8f3b695e	1789	/**
EricLew	0:80ee8f3b695e	1790	* @brief Configure ADC clock source
EricLew	0:80ee8f3b695e	1791	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
EricLew	0:80ee8f3b695e	1792	* @param ADCxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1793	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1794	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1795	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	1796	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1797	* @retval None
EricLew	0:80ee8f3b695e	1798	*/
EricLew	0:80ee8f3b695e	1799	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
EricLew	0:80ee8f3b695e	1800	{
EricLew	0:80ee8f3b695e	1801	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
EricLew	0:80ee8f3b695e	1802	}
EricLew	0:80ee8f3b695e	1803
EricLew	0:80ee8f3b695e	1804	/**
EricLew	0:80ee8f3b695e	1805	* @brief Configure SWPMI clock source
EricLew	0:80ee8f3b695e	1806	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
EricLew	0:80ee8f3b695e	1807	* @param SWPMIxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1808	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
EricLew	0:80ee8f3b695e	1809	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1810	* @retval None
EricLew	0:80ee8f3b695e	1811	*/
EricLew	0:80ee8f3b695e	1812	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
EricLew	0:80ee8f3b695e	1813	{
EricLew	0:80ee8f3b695e	1814	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
EricLew	0:80ee8f3b695e	1815	}
EricLew	0:80ee8f3b695e	1816
EricLew	0:80ee8f3b695e	1817	/**
EricLew	0:80ee8f3b695e	1818	* @brief Configure DFSDM clock source
EricLew	0:80ee8f3b695e	1819	* @rmtoll CCIPR DFSDMSEL LL_RCC_SetDFSDMClockSource
EricLew	0:80ee8f3b695e	1820	* @param DFSDMxSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1821	* @arg @ref LL_RCC_DFSDM_CLKSOURCE_PCLK
EricLew	0:80ee8f3b695e	1822	* @arg @ref LL_RCC_DFSDM_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1823	* @retval None
EricLew	0:80ee8f3b695e	1824	*/
EricLew	0:80ee8f3b695e	1825	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
EricLew	0:80ee8f3b695e	1826	{
EricLew	0:80ee8f3b695e	1827	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, DFSDMxSource);
EricLew	0:80ee8f3b695e	1828	}
EricLew	0:80ee8f3b695e	1829
EricLew	0:80ee8f3b695e	1830	/**
EricLew	0:80ee8f3b695e	1831	* @brief Get USARTx clock source
EricLew	0:80ee8f3b695e	1832	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
EricLew	0:80ee8f3b695e	1833	* @param USARTx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1834	* @arg @ref LL_RCC_USART1_CLKSOURCE
EricLew	0:80ee8f3b695e	1835	* @arg @ref LL_RCC_USART2_CLKSOURCE
EricLew	0:80ee8f3b695e	1836	* @arg @ref LL_RCC_USART3_CLKSOURCE
EricLew	0:80ee8f3b695e	1837	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1838	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
EricLew	0:80ee8f3b695e	1839	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1840	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1841	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1842	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1843	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1844	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1845	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1846	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1847	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1848	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1849	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1850	*/
EricLew	0:80ee8f3b695e	1851	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
EricLew	0:80ee8f3b695e	1852	{
EricLew	0:80ee8f3b695e	1853	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16));
EricLew	0:80ee8f3b695e	1854	}
EricLew	0:80ee8f3b695e	1855
EricLew	0:80ee8f3b695e	1856	/**
EricLew	0:80ee8f3b695e	1857	* @brief Get UARTx clock source
EricLew	0:80ee8f3b695e	1858	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
EricLew	0:80ee8f3b695e	1859	* @param UARTx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1860	* @arg @ref LL_RCC_UART4_CLKSOURCE
EricLew	0:80ee8f3b695e	1861	* @arg @ref LL_RCC_UART5_CLKSOURCE
EricLew	0:80ee8f3b695e	1862	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1863	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1864	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1865	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1866	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1867	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1868	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1869	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1870	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1871	*/
EricLew	0:80ee8f3b695e	1872	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
EricLew	0:80ee8f3b695e	1873	{
EricLew	0:80ee8f3b695e	1874	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16));
EricLew	0:80ee8f3b695e	1875	}
EricLew	0:80ee8f3b695e	1876
EricLew	0:80ee8f3b695e	1877	/**
EricLew	0:80ee8f3b695e	1878	* @brief Get LPUARTx clock source
EricLew	0:80ee8f3b695e	1879	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
EricLew	0:80ee8f3b695e	1880	* @param LPUARTx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1881	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
EricLew	0:80ee8f3b695e	1882	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1883	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1884	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1885	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1886	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1887	*/
EricLew	0:80ee8f3b695e	1888	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
EricLew	0:80ee8f3b695e	1889	{
EricLew	0:80ee8f3b695e	1890	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
EricLew	0:80ee8f3b695e	1891	}
EricLew	0:80ee8f3b695e	1892
EricLew	0:80ee8f3b695e	1893	/**
EricLew	0:80ee8f3b695e	1894	* @brief Get I2Cx clock source
EricLew	0:80ee8f3b695e	1895	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
EricLew	0:80ee8f3b695e	1896	* @param I2Cx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1897	* @arg @ref LL_RCC_I2C1_CLKSOURCE
EricLew	0:80ee8f3b695e	1898	* @arg @ref LL_RCC_I2C2_CLKSOURCE
EricLew	0:80ee8f3b695e	1899	* @arg @ref LL_RCC_I2C3_CLKSOURCE
EricLew	0:80ee8f3b695e	1900	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1901	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1902	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1903	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1904	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1905	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1906	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1907	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1908	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	1909	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1910	*/
EricLew	0:80ee8f3b695e	1911	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
EricLew	0:80ee8f3b695e	1912	{
EricLew	0:80ee8f3b695e	1913	return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4) \| (I2Cx << 4));
EricLew	0:80ee8f3b695e	1914	}
EricLew	0:80ee8f3b695e	1915
EricLew	0:80ee8f3b695e	1916	/**
EricLew	0:80ee8f3b695e	1917	* @brief Get LPTIMx clock source
EricLew	0:80ee8f3b695e	1918	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
EricLew	0:80ee8f3b695e	1919	* @param LPTIMx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1920	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
EricLew	0:80ee8f3b695e	1921	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1922	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1923	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1924	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1925	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1926	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
EricLew	0:80ee8f3b695e	1927	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	1928	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	1929	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	1930	*/
EricLew	0:80ee8f3b695e	1931	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
EricLew	0:80ee8f3b695e	1932	{
EricLew	0:80ee8f3b695e	1933	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16 \| LPTIMx);
EricLew	0:80ee8f3b695e	1934	}
EricLew	0:80ee8f3b695e	1935
EricLew	0:80ee8f3b695e	1936	/**
EricLew	0:80ee8f3b695e	1937	* @brief Get SAIx clock source
EricLew	0:80ee8f3b695e	1938	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
EricLew	0:80ee8f3b695e	1939	* @param SAIx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1940	* @arg @ref LL_RCC_SAI1_CLKSOURCE
EricLew	0:80ee8f3b695e	1941	* @arg @ref LL_RCC_SAI2_CLKSOURCE
EricLew	0:80ee8f3b695e	1942	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1943	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1944	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	1945	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1946	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
EricLew	0:80ee8f3b695e	1947	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1948	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	1949	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1950	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
EricLew	0:80ee8f3b695e	1951	*/
EricLew	0:80ee8f3b695e	1952	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
EricLew	0:80ee8f3b695e	1953	{
EricLew	0:80ee8f3b695e	1954	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16 \| SAIx);
EricLew	0:80ee8f3b695e	1955	}
EricLew	0:80ee8f3b695e	1956
EricLew	0:80ee8f3b695e	1957	/**
EricLew	0:80ee8f3b695e	1958	* @brief Get SDMMCx clock source
EricLew	0:80ee8f3b695e	1959	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
EricLew	0:80ee8f3b695e	1960	* @param SDMMCx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1961	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
EricLew	0:80ee8f3b695e	1962	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1963	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1964	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1965	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1966	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1967	*/
EricLew	0:80ee8f3b695e	1968	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
EricLew	0:80ee8f3b695e	1969	{
EricLew	0:80ee8f3b695e	1970	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
EricLew	0:80ee8f3b695e	1971	}
EricLew	0:80ee8f3b695e	1972
EricLew	0:80ee8f3b695e	1973	/**
EricLew	0:80ee8f3b695e	1974	* @brief Get RNGx clock source
EricLew	0:80ee8f3b695e	1975	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
EricLew	0:80ee8f3b695e	1976	* @param RNGx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1977	* @arg @ref LL_RCC_RNG_CLKSOURCE
EricLew	0:80ee8f3b695e	1978	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1979	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1980	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1981	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1982	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	1983	*/
EricLew	0:80ee8f3b695e	1984	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
EricLew	0:80ee8f3b695e	1985	{
EricLew	0:80ee8f3b695e	1986	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
EricLew	0:80ee8f3b695e	1987	}
EricLew	0:80ee8f3b695e	1988
EricLew	0:80ee8f3b695e	1989	#if defined(USB_OTG_FS)
EricLew	0:80ee8f3b695e	1990	/**
EricLew	0:80ee8f3b695e	1991	* @brief Get USBx clock source
EricLew	0:80ee8f3b695e	1992	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
EricLew	0:80ee8f3b695e	1993	* @param USBx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1994	* @arg @ref LL_RCC_USB_CLKSOURCE
EricLew	0:80ee8f3b695e	1995	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1996	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	1997	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	1998	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
EricLew	0:80ee8f3b695e	1999	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
EricLew	0:80ee8f3b695e	2000	*/
EricLew	0:80ee8f3b695e	2001	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
EricLew	0:80ee8f3b695e	2002	{
EricLew	0:80ee8f3b695e	2003	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
EricLew	0:80ee8f3b695e	2004	}
EricLew	0:80ee8f3b695e	2005	#endif /* USB_OTG_FS */
EricLew	0:80ee8f3b695e	2006
EricLew	0:80ee8f3b695e	2007	/**
EricLew	0:80ee8f3b695e	2008	* @brief Get ADCx clock source
EricLew	0:80ee8f3b695e	2009	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
EricLew	0:80ee8f3b695e	2010	* @param ADCx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2011	* @arg @ref LL_RCC_ADC_CLKSOURCE
EricLew	0:80ee8f3b695e	2012	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2013	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	2014	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
EricLew	0:80ee8f3b695e	2015	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2
EricLew	0:80ee8f3b695e	2016	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	2017	*/
EricLew	0:80ee8f3b695e	2018	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
EricLew	0:80ee8f3b695e	2019	{
EricLew	0:80ee8f3b695e	2020	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
EricLew	0:80ee8f3b695e	2021	}
EricLew	0:80ee8f3b695e	2022
EricLew	0:80ee8f3b695e	2023	/**
EricLew	0:80ee8f3b695e	2024	* @brief Get SWPMIx clock source
EricLew	0:80ee8f3b695e	2025	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
EricLew	0:80ee8f3b695e	2026	* @param SPWMIx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2027	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
EricLew	0:80ee8f3b695e	2028	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2029	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK
EricLew	0:80ee8f3b695e	2030	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
EricLew	0:80ee8f3b695e	2031	*/
EricLew	0:80ee8f3b695e	2032	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
EricLew	0:80ee8f3b695e	2033	{
EricLew	0:80ee8f3b695e	2034	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
EricLew	0:80ee8f3b695e	2035	}
EricLew	0:80ee8f3b695e	2036
EricLew	0:80ee8f3b695e	2037	/**
EricLew	0:80ee8f3b695e	2038	* @brief Get DFSDMx clock source
EricLew	0:80ee8f3b695e	2039	* @rmtoll CCIPR DFSDMSEL LL_RCC_GetDFSDMClockSource
EricLew	0:80ee8f3b695e	2040	* @param DFSDMx This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2041	* @arg @ref LL_RCC_DFSDM_CLKSOURCE
EricLew	0:80ee8f3b695e	2042	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2043	* @arg @ref LL_RCC_DFSDM_CLKSOURCE_PCLK
EricLew	0:80ee8f3b695e	2044	* @arg @ref LL_RCC_DFSDM_CLKSOURCE_SYSCLK
EricLew	0:80ee8f3b695e	2045	*/
EricLew	0:80ee8f3b695e	2046	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
EricLew	0:80ee8f3b695e	2047	{
EricLew	0:80ee8f3b695e	2048	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
EricLew	0:80ee8f3b695e	2049	}
EricLew	0:80ee8f3b695e	2050
EricLew	0:80ee8f3b695e	2051	/**
EricLew	0:80ee8f3b695e	2052	* @}
EricLew	0:80ee8f3b695e	2053	*/
EricLew	0:80ee8f3b695e	2054
EricLew	0:80ee8f3b695e	2055	/** @defgroup RCC_LL_EF_RTC RTC
EricLew	0:80ee8f3b695e	2056	* @{
EricLew	0:80ee8f3b695e	2057	*/
EricLew	0:80ee8f3b695e	2058
EricLew	0:80ee8f3b695e	2059	/**
EricLew	0:80ee8f3b695e	2060	* @brief Set RTC Clock Source
EricLew	0:80ee8f3b695e	2061	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
EricLew	0:80ee8f3b695e	2062	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
EricLew	0:80ee8f3b695e	2063	* set). The BDRST bit can be used to reset them.
EricLew	0:80ee8f3b695e	2064	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
EricLew	0:80ee8f3b695e	2065	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2066	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	2067	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	2068	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	2069	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
EricLew	0:80ee8f3b695e	2070	* @retval None
EricLew	0:80ee8f3b695e	2071	*/
EricLew	0:80ee8f3b695e	2072	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
EricLew	0:80ee8f3b695e	2073	{
EricLew	0:80ee8f3b695e	2074	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
EricLew	0:80ee8f3b695e	2075	}
EricLew	0:80ee8f3b695e	2076
EricLew	0:80ee8f3b695e	2077	/**
EricLew	0:80ee8f3b695e	2078	* @brief Get RTC Clock Source
EricLew	0:80ee8f3b695e	2079	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
EricLew	0:80ee8f3b695e	2080	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2081	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
EricLew	0:80ee8f3b695e	2082	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
EricLew	0:80ee8f3b695e	2083	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
EricLew	0:80ee8f3b695e	2084	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
EricLew	0:80ee8f3b695e	2085	*/
EricLew	0:80ee8f3b695e	2086	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
EricLew	0:80ee8f3b695e	2087	{
EricLew	0:80ee8f3b695e	2088	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
EricLew	0:80ee8f3b695e	2089	}
EricLew	0:80ee8f3b695e	2090
EricLew	0:80ee8f3b695e	2091	/**
EricLew	0:80ee8f3b695e	2092	* @brief Enable RTC
EricLew	0:80ee8f3b695e	2093	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
EricLew	0:80ee8f3b695e	2094	* @retval None
EricLew	0:80ee8f3b695e	2095	*/
EricLew	0:80ee8f3b695e	2096	__STATIC_INLINE void LL_RCC_EnableRTC(void)
EricLew	0:80ee8f3b695e	2097	{
EricLew	0:80ee8f3b695e	2098	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
EricLew	0:80ee8f3b695e	2099	}
EricLew	0:80ee8f3b695e	2100
EricLew	0:80ee8f3b695e	2101	/**
EricLew	0:80ee8f3b695e	2102	* @brief Disable RTC
EricLew	0:80ee8f3b695e	2103	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
EricLew	0:80ee8f3b695e	2104	* @retval None
EricLew	0:80ee8f3b695e	2105	*/
EricLew	0:80ee8f3b695e	2106	__STATIC_INLINE void LL_RCC_DisableRTC(void)
EricLew	0:80ee8f3b695e	2107	{
EricLew	0:80ee8f3b695e	2108	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
EricLew	0:80ee8f3b695e	2109	}
EricLew	0:80ee8f3b695e	2110
EricLew	0:80ee8f3b695e	2111	/**
EricLew	0:80ee8f3b695e	2112	* @brief Check if RTC has been enabled or not
EricLew	0:80ee8f3b695e	2113	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
EricLew	0:80ee8f3b695e	2114	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	2115	*/
EricLew	0:80ee8f3b695e	2116	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
EricLew	0:80ee8f3b695e	2117	{
EricLew	0:80ee8f3b695e	2118	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
EricLew	0:80ee8f3b695e	2119	}
EricLew	0:80ee8f3b695e	2120
EricLew	0:80ee8f3b695e	2121	/**
EricLew	0:80ee8f3b695e	2122	* @brief Force the Backup domain reset
EricLew	0:80ee8f3b695e	2123	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
EricLew	0:80ee8f3b695e	2124	* @retval None
EricLew	0:80ee8f3b695e	2125	*/
EricLew	0:80ee8f3b695e	2126	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
EricLew	0:80ee8f3b695e	2127	{
EricLew	0:80ee8f3b695e	2128	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
EricLew	0:80ee8f3b695e	2129	}
EricLew	0:80ee8f3b695e	2130
EricLew	0:80ee8f3b695e	2131	/**
EricLew	0:80ee8f3b695e	2132	* @brief Release the Backup domain reset
EricLew	0:80ee8f3b695e	2133	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
EricLew	0:80ee8f3b695e	2134	* @retval None
EricLew	0:80ee8f3b695e	2135	*/
EricLew	0:80ee8f3b695e	2136	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
EricLew	0:80ee8f3b695e	2137	{
EricLew	0:80ee8f3b695e	2138	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
EricLew	0:80ee8f3b695e	2139	}
EricLew	0:80ee8f3b695e	2140
EricLew	0:80ee8f3b695e	2141	/**
EricLew	0:80ee8f3b695e	2142	* @}
EricLew	0:80ee8f3b695e	2143	*/
EricLew	0:80ee8f3b695e	2144
EricLew	0:80ee8f3b695e	2145	/** @defgroup RCC_LL_EF_PLL PLL
EricLew	0:80ee8f3b695e	2146	* @{
EricLew	0:80ee8f3b695e	2147	*/
EricLew	0:80ee8f3b695e	2148
EricLew	0:80ee8f3b695e	2149	/**
EricLew	0:80ee8f3b695e	2150	* @brief Enable PLL
EricLew	0:80ee8f3b695e	2151	* @rmtoll CR PLLON LL_RCC_PLL_Enable
EricLew	0:80ee8f3b695e	2152	* @retval None
EricLew	0:80ee8f3b695e	2153	*/
EricLew	0:80ee8f3b695e	2154	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
EricLew	0:80ee8f3b695e	2155	{
EricLew	0:80ee8f3b695e	2156	SET_BIT(RCC->CR, RCC_CR_PLLON);
EricLew	0:80ee8f3b695e	2157	}
EricLew	0:80ee8f3b695e	2158
EricLew	0:80ee8f3b695e	2159	/**
EricLew	0:80ee8f3b695e	2160	* @brief Disable PLL
EricLew	0:80ee8f3b695e	2161	* @note Cannot be disabled if the PLL clock is used as the system clock
EricLew	0:80ee8f3b695e	2162	* @rmtoll CR PLLON LL_RCC_PLL_Disable
EricLew	0:80ee8f3b695e	2163	* @retval None
EricLew	0:80ee8f3b695e	2164	*/
EricLew	0:80ee8f3b695e	2165	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
EricLew	0:80ee8f3b695e	2166	{
EricLew	0:80ee8f3b695e	2167	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
EricLew	0:80ee8f3b695e	2168	}
EricLew	0:80ee8f3b695e	2169
EricLew	0:80ee8f3b695e	2170	/**
EricLew	0:80ee8f3b695e	2171	* @brief Check if PLL Ready
EricLew	0:80ee8f3b695e	2172	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
EricLew	0:80ee8f3b695e	2173	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	2174	*/
EricLew	0:80ee8f3b695e	2175	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
EricLew	0:80ee8f3b695e	2176	{
EricLew	0:80ee8f3b695e	2177	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
EricLew	0:80ee8f3b695e	2178	}
EricLew	0:80ee8f3b695e	2179
EricLew	0:80ee8f3b695e	2180	/**
EricLew	0:80ee8f3b695e	2181	* @brief Configure PLL used for SYSCLK Domain
EricLew	0:80ee8f3b695e	2182	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2183	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2184	* @note PLLN/PLLR can be written only when PLL is disabled
EricLew	0:80ee8f3b695e	2185	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
EricLew	0:80ee8f3b695e	2186	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
EricLew	0:80ee8f3b695e	2187	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
EricLew	0:80ee8f3b695e	2188	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
EricLew	0:80ee8f3b695e	2189	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2190	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2191	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2192	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2193	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2194	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2195	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2196	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2197	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2198	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2199	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2200	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2201	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2202	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2203	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2204	* @param PLLR This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2205	* @arg @ref LL_RCC_PLLR_DIV_2
EricLew	0:80ee8f3b695e	2206	* @arg @ref LL_RCC_PLLR_DIV_4
EricLew	0:80ee8f3b695e	2207	* @arg @ref LL_RCC_PLLR_DIV_6
EricLew	0:80ee8f3b695e	2208	* @arg @ref LL_RCC_PLLR_DIV_8
EricLew	0:80ee8f3b695e	2209	* @retval None
EricLew	0:80ee8f3b695e	2210	*/
EricLew	0:80ee8f3b695e	2211	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
EricLew	0:80ee8f3b695e	2212	{
EricLew	0:80ee8f3b695e	2213	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
EricLew	0:80ee8f3b695e	2214	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLR);
EricLew	0:80ee8f3b695e	2215	}
EricLew	0:80ee8f3b695e	2216
EricLew	0:80ee8f3b695e	2217	/**
EricLew	0:80ee8f3b695e	2218	* @brief Configure PLL used for SAI domain clock
EricLew	0:80ee8f3b695e	2219	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2220	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2221	* @note PLLN/PLLP can be written only when PLL is disabled
EricLew	0:80ee8f3b695e	2222	* @note This can be selected for SAI1 or SAI2
EricLew	0:80ee8f3b695e	2223	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2224	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2225	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2226	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
EricLew	0:80ee8f3b695e	2227	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2228	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2229	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2230	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2231	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2232	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2233	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2234	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2235	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2236	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2237	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2238	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2239	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2240	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2241	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2242	* @param PLLP This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2243	* @arg @ref LL_RCC_PLLP_DIV_7
EricLew	0:80ee8f3b695e	2244	* @arg @ref LL_RCC_PLLP_DIV_17
EricLew	0:80ee8f3b695e	2245	* @retval None
EricLew	0:80ee8f3b695e	2246	*/
EricLew	0:80ee8f3b695e	2247	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
EricLew	0:80ee8f3b695e	2248	{
EricLew	0:80ee8f3b695e	2249	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
EricLew	0:80ee8f3b695e	2250	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLP);
EricLew	0:80ee8f3b695e	2251	}
EricLew	0:80ee8f3b695e	2252
EricLew	0:80ee8f3b695e	2253	/**
EricLew	0:80ee8f3b695e	2254	* @brief Configure PLL used for 48Mhz domain clock
EricLew	0:80ee8f3b695e	2255	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2256	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2257	* @note PLLN/PLLQ can be written only when PLL is disabled
EricLew	0:80ee8f3b695e	2258	* @note This can be selected for USB, RNG, SDMMC
EricLew	0:80ee8f3b695e	2259	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2260	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2261	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2262	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
EricLew	0:80ee8f3b695e	2263	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2264	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2265	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2266	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2267	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2268	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2269	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2270	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2271	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2272	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2273	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2274	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2275	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2276	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2277	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2278	* @param PLLQ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2279	* @arg @ref LL_RCC_PLLQ_DIV_2
EricLew	0:80ee8f3b695e	2280	* @arg @ref LL_RCC_PLLQ_DIV_4
EricLew	0:80ee8f3b695e	2281	* @arg @ref LL_RCC_PLLQ_DIV_6
EricLew	0:80ee8f3b695e	2282	* @arg @ref LL_RCC_PLLQ_DIV_8
EricLew	0:80ee8f3b695e	2283	* @retval None
EricLew	0:80ee8f3b695e	2284	*/
EricLew	0:80ee8f3b695e	2285	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
EricLew	0:80ee8f3b695e	2286	{
EricLew	0:80ee8f3b695e	2287	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
EricLew	0:80ee8f3b695e	2288	Source \| PLLM \| PLLN << RCC_POSITION_PLLN \| PLLQ);
EricLew	0:80ee8f3b695e	2289	}
EricLew	0:80ee8f3b695e	2290
EricLew	0:80ee8f3b695e	2291	/**
EricLew	0:80ee8f3b695e	2292	* @brief Get Main PLL multiplication factor for VCO
EricLew	0:80ee8f3b695e	2293	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
EricLew	0:80ee8f3b695e	2294	* @retval Between 8 and 86
EricLew	0:80ee8f3b695e	2295	*/
EricLew	0:80ee8f3b695e	2296	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
EricLew	0:80ee8f3b695e	2297	{
EricLew	0:80ee8f3b695e	2298	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_POSITION_PLLN);
EricLew	0:80ee8f3b695e	2299	}
EricLew	0:80ee8f3b695e	2300
EricLew	0:80ee8f3b695e	2301	/**
EricLew	0:80ee8f3b695e	2302	* @brief Get Main PLL division factor for PLLP
EricLew	0:80ee8f3b695e	2303	* @note used for PLLSAI3CLK (SAI1 and SAI2 clock)
EricLew	0:80ee8f3b695e	2304	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
EricLew	0:80ee8f3b695e	2305	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2306	* @arg @ref LL_RCC_PLLP_DIV_7
EricLew	0:80ee8f3b695e	2307	* @arg @ref LL_RCC_PLLP_DIV_17
EricLew	0:80ee8f3b695e	2308	*/
EricLew	0:80ee8f3b695e	2309	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
EricLew	0:80ee8f3b695e	2310	{
EricLew	0:80ee8f3b695e	2311	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
EricLew	0:80ee8f3b695e	2312	}
EricLew	0:80ee8f3b695e	2313
EricLew	0:80ee8f3b695e	2314	/**
EricLew	0:80ee8f3b695e	2315	* @brief Get Main PLL division factor for PLLQ
EricLew	0:80ee8f3b695e	2316	* @note used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
EricLew	0:80ee8f3b695e	2317	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
EricLew	0:80ee8f3b695e	2318	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2319	* @arg @ref LL_RCC_PLLQ_DIV_2
EricLew	0:80ee8f3b695e	2320	* @arg @ref LL_RCC_PLLQ_DIV_4
EricLew	0:80ee8f3b695e	2321	* @arg @ref LL_RCC_PLLQ_DIV_6
EricLew	0:80ee8f3b695e	2322	* @arg @ref LL_RCC_PLLQ_DIV_8
EricLew	0:80ee8f3b695e	2323	*/
EricLew	0:80ee8f3b695e	2324	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
EricLew	0:80ee8f3b695e	2325	{
EricLew	0:80ee8f3b695e	2326	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
EricLew	0:80ee8f3b695e	2327	}
EricLew	0:80ee8f3b695e	2328
EricLew	0:80ee8f3b695e	2329	/**
EricLew	0:80ee8f3b695e	2330	* @brief Get Main PLL division factor for PLLR
EricLew	0:80ee8f3b695e	2331	* @note used for PLLCLK (system clock)
EricLew	0:80ee8f3b695e	2332	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
EricLew	0:80ee8f3b695e	2333	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2334	* @arg @ref LL_RCC_PLLR_DIV_2
EricLew	0:80ee8f3b695e	2335	* @arg @ref LL_RCC_PLLR_DIV_4
EricLew	0:80ee8f3b695e	2336	* @arg @ref LL_RCC_PLLR_DIV_6
EricLew	0:80ee8f3b695e	2337	* @arg @ref LL_RCC_PLLR_DIV_8
EricLew	0:80ee8f3b695e	2338	*/
EricLew	0:80ee8f3b695e	2339	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
EricLew	0:80ee8f3b695e	2340	{
EricLew	0:80ee8f3b695e	2341	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
EricLew	0:80ee8f3b695e	2342	}
EricLew	0:80ee8f3b695e	2343
EricLew	0:80ee8f3b695e	2344	/**
EricLew	0:80ee8f3b695e	2345	* @brief Get the oscillator used as PLL clock source.
EricLew	0:80ee8f3b695e	2346	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
EricLew	0:80ee8f3b695e	2347	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2348	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2349	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2350	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2351	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2352	*/
EricLew	0:80ee8f3b695e	2353	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
EricLew	0:80ee8f3b695e	2354	{
EricLew	0:80ee8f3b695e	2355	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
EricLew	0:80ee8f3b695e	2356	}
EricLew	0:80ee8f3b695e	2357
EricLew	0:80ee8f3b695e	2358	/**
EricLew	0:80ee8f3b695e	2359	* @brief Get Division factor for the main PLL and other PLL
EricLew	0:80ee8f3b695e	2360	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
EricLew	0:80ee8f3b695e	2361	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2362	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2363	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2364	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2365	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2366	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2367	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2368	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2369	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2370	*/
EricLew	0:80ee8f3b695e	2371	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
EricLew	0:80ee8f3b695e	2372	{
EricLew	0:80ee8f3b695e	2373	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
EricLew	0:80ee8f3b695e	2374	}
EricLew	0:80ee8f3b695e	2375
EricLew	0:80ee8f3b695e	2376	/**
EricLew	0:80ee8f3b695e	2377	* @brief Enable PLL output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2378	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
EricLew	0:80ee8f3b695e	2379	* @retval None
EricLew	0:80ee8f3b695e	2380	*/
EricLew	0:80ee8f3b695e	2381	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2382	{
EricLew	0:80ee8f3b695e	2383	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
EricLew	0:80ee8f3b695e	2384	}
EricLew	0:80ee8f3b695e	2385
EricLew	0:80ee8f3b695e	2386	/**
EricLew	0:80ee8f3b695e	2387	* @brief Disable PLL output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2388	* @note Cannot be disabled if the PLL clock is used as the system
EricLew	0:80ee8f3b695e	2389	* clock
EricLew	0:80ee8f3b695e	2390	* @note In order to save power, when the PLLCLK of the PLL is
EricLew	0:80ee8f3b695e	2391	* not used, should be 0
EricLew	0:80ee8f3b695e	2392	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
EricLew	0:80ee8f3b695e	2393	* @retval None
EricLew	0:80ee8f3b695e	2394	*/
EricLew	0:80ee8f3b695e	2395	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2396	{
EricLew	0:80ee8f3b695e	2397	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
EricLew	0:80ee8f3b695e	2398	}
EricLew	0:80ee8f3b695e	2399
EricLew	0:80ee8f3b695e	2400	/**
EricLew	0:80ee8f3b695e	2401	* @brief Enable PLL output mapped on 48MHz domain clock
EricLew	0:80ee8f3b695e	2402	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
EricLew	0:80ee8f3b695e	2403	* @retval None
EricLew	0:80ee8f3b695e	2404	*/
EricLew	0:80ee8f3b695e	2405	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
EricLew	0:80ee8f3b695e	2406	{
EricLew	0:80ee8f3b695e	2407	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
EricLew	0:80ee8f3b695e	2408	}
EricLew	0:80ee8f3b695e	2409
EricLew	0:80ee8f3b695e	2410	/**
EricLew	0:80ee8f3b695e	2411	* @brief Disable PLL output mapped on 48MHz domain clock
EricLew	0:80ee8f3b695e	2412	* @note Cannot be disabled if the PLL clock is used as the system
EricLew	0:80ee8f3b695e	2413	* clock
EricLew	0:80ee8f3b695e	2414	* @note In order to save power, when the PLLCLK of the PLL is
EricLew	0:80ee8f3b695e	2415	* not used, should be 0
EricLew	0:80ee8f3b695e	2416	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
EricLew	0:80ee8f3b695e	2417	* @retval None
EricLew	0:80ee8f3b695e	2418	*/
EricLew	0:80ee8f3b695e	2419	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
EricLew	0:80ee8f3b695e	2420	{
EricLew	0:80ee8f3b695e	2421	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
EricLew	0:80ee8f3b695e	2422	}
EricLew	0:80ee8f3b695e	2423
EricLew	0:80ee8f3b695e	2424	/**
EricLew	0:80ee8f3b695e	2425	* @brief Enable PLL output mapped on SYSCLK domain
EricLew	0:80ee8f3b695e	2426	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
EricLew	0:80ee8f3b695e	2427	* @retval None
EricLew	0:80ee8f3b695e	2428	*/
EricLew	0:80ee8f3b695e	2429	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
EricLew	0:80ee8f3b695e	2430	{
EricLew	0:80ee8f3b695e	2431	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
EricLew	0:80ee8f3b695e	2432	}
EricLew	0:80ee8f3b695e	2433
EricLew	0:80ee8f3b695e	2434	/**
EricLew	0:80ee8f3b695e	2435	* @brief Disable PLL output mapped on SYSCLK domain
EricLew	0:80ee8f3b695e	2436	* @note Cannot be disabled if the PLL clock is used as the system
EricLew	0:80ee8f3b695e	2437	* clock
EricLew	0:80ee8f3b695e	2438	* @note In order to save power, when the PLLCLK of the PLL is
EricLew	0:80ee8f3b695e	2439	* not used, Main PLL should be 0
EricLew	0:80ee8f3b695e	2440	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
EricLew	0:80ee8f3b695e	2441	* @retval None
EricLew	0:80ee8f3b695e	2442	*/
EricLew	0:80ee8f3b695e	2443	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
EricLew	0:80ee8f3b695e	2444	{
EricLew	0:80ee8f3b695e	2445	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
EricLew	0:80ee8f3b695e	2446	}
EricLew	0:80ee8f3b695e	2447
EricLew	0:80ee8f3b695e	2448	/**
EricLew	0:80ee8f3b695e	2449	* @}
EricLew	0:80ee8f3b695e	2450	*/
EricLew	0:80ee8f3b695e	2451
EricLew	0:80ee8f3b695e	2452	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
EricLew	0:80ee8f3b695e	2453	* @{
EricLew	0:80ee8f3b695e	2454	*/
EricLew	0:80ee8f3b695e	2455
EricLew	0:80ee8f3b695e	2456	/**
EricLew	0:80ee8f3b695e	2457	* @brief Enable PLLSAI1
EricLew	0:80ee8f3b695e	2458	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
EricLew	0:80ee8f3b695e	2459	* @retval None
EricLew	0:80ee8f3b695e	2460	*/
EricLew	0:80ee8f3b695e	2461	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
EricLew	0:80ee8f3b695e	2462	{
EricLew	0:80ee8f3b695e	2463	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
EricLew	0:80ee8f3b695e	2464	}
EricLew	0:80ee8f3b695e	2465
EricLew	0:80ee8f3b695e	2466	/**
EricLew	0:80ee8f3b695e	2467	* @brief Disable PLLSAI1
EricLew	0:80ee8f3b695e	2468	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
EricLew	0:80ee8f3b695e	2469	* @retval None
EricLew	0:80ee8f3b695e	2470	*/
EricLew	0:80ee8f3b695e	2471	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
EricLew	0:80ee8f3b695e	2472	{
EricLew	0:80ee8f3b695e	2473	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
EricLew	0:80ee8f3b695e	2474	}
EricLew	0:80ee8f3b695e	2475
EricLew	0:80ee8f3b695e	2476	/**
EricLew	0:80ee8f3b695e	2477	* @brief Check if PLLSAI1 Ready
EricLew	0:80ee8f3b695e	2478	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
EricLew	0:80ee8f3b695e	2479	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	2480	*/
EricLew	0:80ee8f3b695e	2481	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
EricLew	0:80ee8f3b695e	2482	{
EricLew	0:80ee8f3b695e	2483	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
EricLew	0:80ee8f3b695e	2484	}
EricLew	0:80ee8f3b695e	2485
EricLew	0:80ee8f3b695e	2486	/**
EricLew	0:80ee8f3b695e	2487	* @brief Configure PLLSAI1 used for 48Mhz domain clock
EricLew	0:80ee8f3b695e	2488	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2489	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2490	* @note PLLN/PLLQ can be written only when PLLSAI1 is disabled
EricLew	0:80ee8f3b695e	2491	* @note This can be selected for USB, RNG, SDMMC
EricLew	0:80ee8f3b695e	2492	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2493	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2494	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
EricLew	0:80ee8f3b695e	2495	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
EricLew	0:80ee8f3b695e	2496	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2497	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2498	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2499	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2500	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2501	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2502	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2503	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2504	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2505	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2506	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2507	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2508	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2509	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2510	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2511	* @param PLLQ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2512	* @arg @ref LL_RCC_PLLSAI1Q_DIV2
EricLew	0:80ee8f3b695e	2513	* @arg @ref LL_RCC_PLLSAI1Q_DIV4
EricLew	0:80ee8f3b695e	2514	* @arg @ref LL_RCC_PLLSAI1Q_DIV6
EricLew	0:80ee8f3b695e	2515	* @arg @ref LL_RCC_PLLSAI1Q_DIV8
EricLew	0:80ee8f3b695e	2516	* @retval None
EricLew	0:80ee8f3b695e	2517	*/
EricLew	0:80ee8f3b695e	2518	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
EricLew	0:80ee8f3b695e	2519	{
EricLew	0:80ee8f3b695e	2520	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
EricLew	0:80ee8f3b695e	2521	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_POSITION_PLLSAI1N \| PLLQ);
EricLew	0:80ee8f3b695e	2522	}
EricLew	0:80ee8f3b695e	2523
EricLew	0:80ee8f3b695e	2524	/**
EricLew	0:80ee8f3b695e	2525	* @brief Configure PLLSAI1 used for SAI domain clock
EricLew	0:80ee8f3b695e	2526	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2527	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2528	* @note PLLN/PLLP can be written only when PLLSAI1 is disabled
EricLew	0:80ee8f3b695e	2529	* @note This can be selected for SAI1 or SAI2
EricLew	0:80ee8f3b695e	2530	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2531	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2532	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2533	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
EricLew	0:80ee8f3b695e	2534	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2535	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2536	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2537	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2538	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2539	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2540	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2541	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2542	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2543	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2544	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2545	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2546	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2547	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2548	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2549	* @param PLLP This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2550	* @arg @ref LL_RCC_PLLSAI1P_DIV7
EricLew	0:80ee8f3b695e	2551	* @arg @ref LL_RCC_PLLSAI1P_DIV17
EricLew	0:80ee8f3b695e	2552	* @retval None
EricLew	0:80ee8f3b695e	2553	*/
EricLew	0:80ee8f3b695e	2554	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
EricLew	0:80ee8f3b695e	2555	{
EricLew	0:80ee8f3b695e	2556	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
EricLew	0:80ee8f3b695e	2557	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_POSITION_PLLSAI1N \| PLLP);
EricLew	0:80ee8f3b695e	2558	}
EricLew	0:80ee8f3b695e	2559
EricLew	0:80ee8f3b695e	2560	/**
EricLew	0:80ee8f3b695e	2561	* @brief Configure PLLSAI1 used for ADC domain clock
EricLew	0:80ee8f3b695e	2562	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2563	* PLLSAI1 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2564	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled
EricLew	0:80ee8f3b695e	2565	* @note This can be selected for ADC
EricLew	0:80ee8f3b695e	2566	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2567	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2568	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2569	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
EricLew	0:80ee8f3b695e	2570	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2571	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2572	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2573	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2574	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2575	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2576	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2577	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2578	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2579	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2580	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2581	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2582	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2583	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2584	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2585	* @param PLLR This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2586	* @arg @ref LL_RCC_PLLSAI1R_DIV2
EricLew	0:80ee8f3b695e	2587	* @arg @ref LL_RCC_PLLSAI1R_DIV4
EricLew	0:80ee8f3b695e	2588	* @arg @ref LL_RCC_PLLSAI1R_DIV6
EricLew	0:80ee8f3b695e	2589	* @arg @ref LL_RCC_PLLSAI1R_DIV8
EricLew	0:80ee8f3b695e	2590	* @retval None
EricLew	0:80ee8f3b695e	2591	*/
EricLew	0:80ee8f3b695e	2592	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
EricLew	0:80ee8f3b695e	2593	{
EricLew	0:80ee8f3b695e	2594	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
EricLew	0:80ee8f3b695e	2595	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_POSITION_PLLSAI1N \| PLLR);
EricLew	0:80ee8f3b695e	2596	}
EricLew	0:80ee8f3b695e	2597
EricLew	0:80ee8f3b695e	2598	/**
EricLew	0:80ee8f3b695e	2599	* @brief Get SAI1PLL multiplication factor for VCO
EricLew	0:80ee8f3b695e	2600	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
EricLew	0:80ee8f3b695e	2601	* @retval Between 8 and 86
EricLew	0:80ee8f3b695e	2602	*/
EricLew	0:80ee8f3b695e	2603	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
EricLew	0:80ee8f3b695e	2604	{
EricLew	0:80ee8f3b695e	2605	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_POSITION_PLLSAI1N);
EricLew	0:80ee8f3b695e	2606	}
EricLew	0:80ee8f3b695e	2607
EricLew	0:80ee8f3b695e	2608	/**
EricLew	0:80ee8f3b695e	2609	* @brief Get SAI1PLL division factor for PLLSAI1P
EricLew	0:80ee8f3b695e	2610	* @note used for PLLSAI1CLK (SAI1 or SAI2 clock).
EricLew	0:80ee8f3b695e	2611	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
EricLew	0:80ee8f3b695e	2612	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2613	* @arg @ref LL_RCC_PLLSAI1P_DIV7
EricLew	0:80ee8f3b695e	2614	* @arg @ref LL_RCC_PLLSAI1P_DIV17
EricLew	0:80ee8f3b695e	2615	*/
EricLew	0:80ee8f3b695e	2616	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
EricLew	0:80ee8f3b695e	2617	{
EricLew	0:80ee8f3b695e	2618	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
EricLew	0:80ee8f3b695e	2619	}
EricLew	0:80ee8f3b695e	2620
EricLew	0:80ee8f3b695e	2621	/**
EricLew	0:80ee8f3b695e	2622	* @brief Get SAI1PLL division factor for PLLSAI1Q
EricLew	0:80ee8f3b695e	2623	* @note used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
EricLew	0:80ee8f3b695e	2624	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
EricLew	0:80ee8f3b695e	2625	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2626	* @arg @ref LL_RCC_PLLSAI1Q_DIV2
EricLew	0:80ee8f3b695e	2627	* @arg @ref LL_RCC_PLLSAI1Q_DIV4
EricLew	0:80ee8f3b695e	2628	* @arg @ref LL_RCC_PLLSAI1Q_DIV6
EricLew	0:80ee8f3b695e	2629	* @arg @ref LL_RCC_PLLSAI1Q_DIV8
EricLew	0:80ee8f3b695e	2630	*/
EricLew	0:80ee8f3b695e	2631	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
EricLew	0:80ee8f3b695e	2632	{
EricLew	0:80ee8f3b695e	2633	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
EricLew	0:80ee8f3b695e	2634	}
EricLew	0:80ee8f3b695e	2635
EricLew	0:80ee8f3b695e	2636	/**
EricLew	0:80ee8f3b695e	2637	* @brief Get PLLSAI1 division factor for PLLSAIR
EricLew	0:80ee8f3b695e	2638	* @note used for PLLADC1CLK (ADC clock)
EricLew	0:80ee8f3b695e	2639	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
EricLew	0:80ee8f3b695e	2640	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2641	* @arg @ref LL_RCC_PLLSAI1R_DIV2
EricLew	0:80ee8f3b695e	2642	* @arg @ref LL_RCC_PLLSAI1R_DIV4
EricLew	0:80ee8f3b695e	2643	* @arg @ref LL_RCC_PLLSAI1R_DIV6
EricLew	0:80ee8f3b695e	2644	* @arg @ref LL_RCC_PLLSAI1R_DIV8
EricLew	0:80ee8f3b695e	2645	*/
EricLew	0:80ee8f3b695e	2646	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
EricLew	0:80ee8f3b695e	2647	{
EricLew	0:80ee8f3b695e	2648	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
EricLew	0:80ee8f3b695e	2649	}
EricLew	0:80ee8f3b695e	2650
EricLew	0:80ee8f3b695e	2651	/**
EricLew	0:80ee8f3b695e	2652	* @brief Enable PLLSAI1 output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2653	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
EricLew	0:80ee8f3b695e	2654	* @retval None
EricLew	0:80ee8f3b695e	2655	*/
EricLew	0:80ee8f3b695e	2656	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2657	{
EricLew	0:80ee8f3b695e	2658	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
EricLew	0:80ee8f3b695e	2659	}
EricLew	0:80ee8f3b695e	2660
EricLew	0:80ee8f3b695e	2661	/**
EricLew	0:80ee8f3b695e	2662	* @brief Disable PLLSAI1 output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2663	* @note In order to save power, when of the PLLSAI1 is
EricLew	0:80ee8f3b695e	2664	* not used, should be 0
EricLew	0:80ee8f3b695e	2665	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
EricLew	0:80ee8f3b695e	2666	* @retval None
EricLew	0:80ee8f3b695e	2667	*/
EricLew	0:80ee8f3b695e	2668	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2669	{
EricLew	0:80ee8f3b695e	2670	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
EricLew	0:80ee8f3b695e	2671	}
EricLew	0:80ee8f3b695e	2672
EricLew	0:80ee8f3b695e	2673	/**
EricLew	0:80ee8f3b695e	2674	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
EricLew	0:80ee8f3b695e	2675	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
EricLew	0:80ee8f3b695e	2676	* @retval None
EricLew	0:80ee8f3b695e	2677	*/
EricLew	0:80ee8f3b695e	2678	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
EricLew	0:80ee8f3b695e	2679	{
EricLew	0:80ee8f3b695e	2680	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
EricLew	0:80ee8f3b695e	2681	}
EricLew	0:80ee8f3b695e	2682
EricLew	0:80ee8f3b695e	2683	/**
EricLew	0:80ee8f3b695e	2684	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
EricLew	0:80ee8f3b695e	2685	* @note In order to save power, when of the PLLSAI1 is
EricLew	0:80ee8f3b695e	2686	* not used, should be 0
EricLew	0:80ee8f3b695e	2687	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
EricLew	0:80ee8f3b695e	2688	* @retval None
EricLew	0:80ee8f3b695e	2689	*/
EricLew	0:80ee8f3b695e	2690	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
EricLew	0:80ee8f3b695e	2691	{
EricLew	0:80ee8f3b695e	2692	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
EricLew	0:80ee8f3b695e	2693	}
EricLew	0:80ee8f3b695e	2694
EricLew	0:80ee8f3b695e	2695	/**
EricLew	0:80ee8f3b695e	2696	* @brief Enable PLLSAI1 output mapped on ADC domain clock
EricLew	0:80ee8f3b695e	2697	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
EricLew	0:80ee8f3b695e	2698	* @retval None
EricLew	0:80ee8f3b695e	2699	*/
EricLew	0:80ee8f3b695e	2700	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
EricLew	0:80ee8f3b695e	2701	{
EricLew	0:80ee8f3b695e	2702	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
EricLew	0:80ee8f3b695e	2703	}
EricLew	0:80ee8f3b695e	2704
EricLew	0:80ee8f3b695e	2705	/**
EricLew	0:80ee8f3b695e	2706	* @brief Disable PLLSAI1 output mapped on ADC domain clock
EricLew	0:80ee8f3b695e	2707	* @note In order to save power, when of the PLLSAI1 is
EricLew	0:80ee8f3b695e	2708	* not used, Main PLLSAI1 should be 0
EricLew	0:80ee8f3b695e	2709	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
EricLew	0:80ee8f3b695e	2710	* @retval None
EricLew	0:80ee8f3b695e	2711	*/
EricLew	0:80ee8f3b695e	2712	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
EricLew	0:80ee8f3b695e	2713	{
EricLew	0:80ee8f3b695e	2714	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
EricLew	0:80ee8f3b695e	2715	}
EricLew	0:80ee8f3b695e	2716
EricLew	0:80ee8f3b695e	2717	/**
EricLew	0:80ee8f3b695e	2718	* @}
EricLew	0:80ee8f3b695e	2719	*/
EricLew	0:80ee8f3b695e	2720
EricLew	0:80ee8f3b695e	2721	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
EricLew	0:80ee8f3b695e	2722	* @{
EricLew	0:80ee8f3b695e	2723	*/
EricLew	0:80ee8f3b695e	2724
EricLew	0:80ee8f3b695e	2725	/**
EricLew	0:80ee8f3b695e	2726	* @brief Enable PLLSAI2
EricLew	0:80ee8f3b695e	2727	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
EricLew	0:80ee8f3b695e	2728	* @retval None
EricLew	0:80ee8f3b695e	2729	*/
EricLew	0:80ee8f3b695e	2730	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
EricLew	0:80ee8f3b695e	2731	{
EricLew	0:80ee8f3b695e	2732	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
EricLew	0:80ee8f3b695e	2733	}
EricLew	0:80ee8f3b695e	2734
EricLew	0:80ee8f3b695e	2735	/**
EricLew	0:80ee8f3b695e	2736	* @brief Disable PLLSAI2
EricLew	0:80ee8f3b695e	2737	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
EricLew	0:80ee8f3b695e	2738	* @retval None
EricLew	0:80ee8f3b695e	2739	*/
EricLew	0:80ee8f3b695e	2740	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
EricLew	0:80ee8f3b695e	2741	{
EricLew	0:80ee8f3b695e	2742	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
EricLew	0:80ee8f3b695e	2743	}
EricLew	0:80ee8f3b695e	2744
EricLew	0:80ee8f3b695e	2745	/**
EricLew	0:80ee8f3b695e	2746	* @brief Check if PLLSAI2 Ready
EricLew	0:80ee8f3b695e	2747	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
EricLew	0:80ee8f3b695e	2748	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	2749	*/
EricLew	0:80ee8f3b695e	2750	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
EricLew	0:80ee8f3b695e	2751	{
EricLew	0:80ee8f3b695e	2752	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
EricLew	0:80ee8f3b695e	2753	}
EricLew	0:80ee8f3b695e	2754
EricLew	0:80ee8f3b695e	2755	/**
EricLew	0:80ee8f3b695e	2756	* @brief Configure PLLSAI2 used for SAI domain clock
EricLew	0:80ee8f3b695e	2757	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2758	* PLLSAI2 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2759	* @note PLLN/PLLP can be written only when PLLSAI2 is disabled
EricLew	0:80ee8f3b695e	2760	* @note This can be selected for SAI1 or SAI2
EricLew	0:80ee8f3b695e	2761	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2762	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2763	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
EricLew	0:80ee8f3b695e	2764	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
EricLew	0:80ee8f3b695e	2765	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2766	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2767	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2768	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2769	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2770	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2771	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2772	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2773	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2774	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2775	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2776	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2777	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2778	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2779	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2780	* @param PLLP This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2781	* @arg @ref LL_RCC_PLLSAI2P_DIV7
EricLew	0:80ee8f3b695e	2782	* @arg @ref LL_RCC_PLLSAI2P_DIV17
EricLew	0:80ee8f3b695e	2783	* @retval None
EricLew	0:80ee8f3b695e	2784	*/
EricLew	0:80ee8f3b695e	2785	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
EricLew	0:80ee8f3b695e	2786	{
EricLew	0:80ee8f3b695e	2787	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
EricLew	0:80ee8f3b695e	2788	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_POSITION_PLLSAI2N \| PLLP);
EricLew	0:80ee8f3b695e	2789	}
EricLew	0:80ee8f3b695e	2790
EricLew	0:80ee8f3b695e	2791	/**
EricLew	0:80ee8f3b695e	2792	* @brief Configure PLLSAI2 used for ADC domain clock
EricLew	0:80ee8f3b695e	2793	* @note PLL Source and PLLM Divider can be written only when PLL,
EricLew	0:80ee8f3b695e	2794	* PLLSAI2 and PLLSAI2 are disabled
EricLew	0:80ee8f3b695e	2795	* @note PLLN/PLLR can be written only when PLLSAI2 is disabled
EricLew	0:80ee8f3b695e	2796	* @note This can be selected for ADC
EricLew	0:80ee8f3b695e	2797	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2798	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2799	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
EricLew	0:80ee8f3b695e	2800	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
EricLew	0:80ee8f3b695e	2801	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2802	* @arg @ref LL_RCC_PLLSOURCE_NONE
EricLew	0:80ee8f3b695e	2803	* @arg @ref LL_RCC_PLLSOURCE_MSI
EricLew	0:80ee8f3b695e	2804	* @arg @ref LL_RCC_PLLSOURCE_HSI
EricLew	0:80ee8f3b695e	2805	* @arg @ref LL_RCC_PLLSOURCE_HSE
EricLew	0:80ee8f3b695e	2806	* @param PLLM This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2807	* @arg @ref LL_RCC_PLLM_DIV_1
EricLew	0:80ee8f3b695e	2808	* @arg @ref LL_RCC_PLLM_DIV_2
EricLew	0:80ee8f3b695e	2809	* @arg @ref LL_RCC_PLLM_DIV_3
EricLew	0:80ee8f3b695e	2810	* @arg @ref LL_RCC_PLLM_DIV_4
EricLew	0:80ee8f3b695e	2811	* @arg @ref LL_RCC_PLLM_DIV_5
EricLew	0:80ee8f3b695e	2812	* @arg @ref LL_RCC_PLLM_DIV_6
EricLew	0:80ee8f3b695e	2813	* @arg @ref LL_RCC_PLLM_DIV_7
EricLew	0:80ee8f3b695e	2814	* @arg @ref LL_RCC_PLLM_DIV_8
EricLew	0:80ee8f3b695e	2815	* @param PLLN Between 8 and 86
EricLew	0:80ee8f3b695e	2816	* @param PLLR This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2817	* @arg @ref LL_RCC_PLLSAI2R_DIV2
EricLew	0:80ee8f3b695e	2818	* @arg @ref LL_RCC_PLLSAI2R_DIV4
EricLew	0:80ee8f3b695e	2819	* @arg @ref LL_RCC_PLLSAI2R_DIV6
EricLew	0:80ee8f3b695e	2820	* @arg @ref LL_RCC_PLLSAI2R_DIV8
EricLew	0:80ee8f3b695e	2821	* @retval None
EricLew	0:80ee8f3b695e	2822	*/
EricLew	0:80ee8f3b695e	2823	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
EricLew	0:80ee8f3b695e	2824	{
EricLew	0:80ee8f3b695e	2825	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
EricLew	0:80ee8f3b695e	2826	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_POSITION_PLLSAI2N \| PLLR);
EricLew	0:80ee8f3b695e	2827	}
EricLew	0:80ee8f3b695e	2828
EricLew	0:80ee8f3b695e	2829	/**
EricLew	0:80ee8f3b695e	2830	* @brief Get SAI2PLL multiplication factor for VCO
EricLew	0:80ee8f3b695e	2831	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
EricLew	0:80ee8f3b695e	2832	* @retval Between 8 and 86
EricLew	0:80ee8f3b695e	2833	*/
EricLew	0:80ee8f3b695e	2834	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
EricLew	0:80ee8f3b695e	2835	{
EricLew	0:80ee8f3b695e	2836	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_POSITION_PLLSAI2N);
EricLew	0:80ee8f3b695e	2837	}
EricLew	0:80ee8f3b695e	2838
EricLew	0:80ee8f3b695e	2839	/**
EricLew	0:80ee8f3b695e	2840	* @brief Get SAI2PLL division factor for PLLSAI2P
EricLew	0:80ee8f3b695e	2841	* @note used for PLLSAI2CLK (SAI1 or SAI2 clock).
EricLew	0:80ee8f3b695e	2842	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
EricLew	0:80ee8f3b695e	2843	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2844	* @arg @ref LL_RCC_PLLSAI2P_DIV7
EricLew	0:80ee8f3b695e	2845	* @arg @ref LL_RCC_PLLSAI2P_DIV17
EricLew	0:80ee8f3b695e	2846	*/
EricLew	0:80ee8f3b695e	2847	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
EricLew	0:80ee8f3b695e	2848	{
EricLew	0:80ee8f3b695e	2849	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
EricLew	0:80ee8f3b695e	2850	}
EricLew	0:80ee8f3b695e	2851
EricLew	0:80ee8f3b695e	2852	/**
EricLew	0:80ee8f3b695e	2853	* @brief Get SAI2PLL division factor for PLLSAI2R
EricLew	0:80ee8f3b695e	2854	* @note used for PLLADC2CLK (ADC clock)
EricLew	0:80ee8f3b695e	2855	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
EricLew	0:80ee8f3b695e	2856	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2857	* @arg @ref LL_RCC_PLLSAI2R_DIV2
EricLew	0:80ee8f3b695e	2858	* @arg @ref LL_RCC_PLLSAI2R_DIV4
EricLew	0:80ee8f3b695e	2859	* @arg @ref LL_RCC_PLLSAI2R_DIV6
EricLew	0:80ee8f3b695e	2860	* @arg @ref LL_RCC_PLLSAI2R_DIV8
EricLew	0:80ee8f3b695e	2861	*/
EricLew	0:80ee8f3b695e	2862	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
EricLew	0:80ee8f3b695e	2863	{
EricLew	0:80ee8f3b695e	2864	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
EricLew	0:80ee8f3b695e	2865	}
EricLew	0:80ee8f3b695e	2866
EricLew	0:80ee8f3b695e	2867	/**
EricLew	0:80ee8f3b695e	2868	* @brief Enable PLLSAI2 output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2869	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
EricLew	0:80ee8f3b695e	2870	* @retval None
EricLew	0:80ee8f3b695e	2871	*/
EricLew	0:80ee8f3b695e	2872	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2873	{
EricLew	0:80ee8f3b695e	2874	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
EricLew	0:80ee8f3b695e	2875	}
EricLew	0:80ee8f3b695e	2876
EricLew	0:80ee8f3b695e	2877	/**
EricLew	0:80ee8f3b695e	2878	* @brief Disable PLLSAI2 output mapped on SAI domain clock
EricLew	0:80ee8f3b695e	2879	* @note In order to save power, when of the PLLSAI2 is
EricLew	0:80ee8f3b695e	2880	* not used, should be 0
EricLew	0:80ee8f3b695e	2881	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
EricLew	0:80ee8f3b695e	2882	* @retval None
EricLew	0:80ee8f3b695e	2883	*/
EricLew	0:80ee8f3b695e	2884	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
EricLew	0:80ee8f3b695e	2885	{
EricLew	0:80ee8f3b695e	2886	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
EricLew	0:80ee8f3b695e	2887	}
EricLew	0:80ee8f3b695e	2888
EricLew	0:80ee8f3b695e	2889	/**
EricLew	0:80ee8f3b695e	2890	* @brief Enable PLLSAI2 output mapped on ADC domain clock
EricLew	0:80ee8f3b695e	2891	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
EricLew	0:80ee8f3b695e	2892	* @retval None
EricLew	0:80ee8f3b695e	2893	*/
EricLew	0:80ee8f3b695e	2894	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
EricLew	0:80ee8f3b695e	2895	{
EricLew	0:80ee8f3b695e	2896	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
EricLew	0:80ee8f3b695e	2897	}
EricLew	0:80ee8f3b695e	2898
EricLew	0:80ee8f3b695e	2899	/**
EricLew	0:80ee8f3b695e	2900	* @brief Disable PLLSAI2 output mapped on ADC domain clock
EricLew	0:80ee8f3b695e	2901	* @note In order to save power, when of the PLLSAI2 is
EricLew	0:80ee8f3b695e	2902	* not used, Main PLLSAI2 should be 0
EricLew	0:80ee8f3b695e	2903	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
EricLew	0:80ee8f3b695e	2904	* @retval None
EricLew	0:80ee8f3b695e	2905	*/
EricLew	0:80ee8f3b695e	2906	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
EricLew	0:80ee8f3b695e	2907	{
EricLew	0:80ee8f3b695e	2908	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
EricLew	0:80ee8f3b695e	2909	}
EricLew	0:80ee8f3b695e	2910
EricLew	0:80ee8f3b695e	2911	/**
EricLew	0:80ee8f3b695e	2912	* @}
EricLew	0:80ee8f3b695e	2913	*/
EricLew	0:80ee8f3b695e	2914
EricLew	0:80ee8f3b695e	2915	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
EricLew	0:80ee8f3b695e	2916	* @{
EricLew	0:80ee8f3b695e	2917	*/
EricLew	0:80ee8f3b695e	2918
EricLew	0:80ee8f3b695e	2919	/**
EricLew	0:80ee8f3b695e	2920	* @brief Clear LSI ready interrupt flag
EricLew	0:80ee8f3b695e	2921	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
EricLew	0:80ee8f3b695e	2922	* @retval None
EricLew	0:80ee8f3b695e	2923	*/
EricLew	0:80ee8f3b695e	2924	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
EricLew	0:80ee8f3b695e	2925	{
EricLew	0:80ee8f3b695e	2926	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
EricLew	0:80ee8f3b695e	2927	}
EricLew	0:80ee8f3b695e	2928
EricLew	0:80ee8f3b695e	2929	/**
EricLew	0:80ee8f3b695e	2930	* @brief Clear LSE ready interrupt flag
EricLew	0:80ee8f3b695e	2931	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
EricLew	0:80ee8f3b695e	2932	* @retval None
EricLew	0:80ee8f3b695e	2933	*/
EricLew	0:80ee8f3b695e	2934	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
EricLew	0:80ee8f3b695e	2935	{
EricLew	0:80ee8f3b695e	2936	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
EricLew	0:80ee8f3b695e	2937	}
EricLew	0:80ee8f3b695e	2938
EricLew	0:80ee8f3b695e	2939	/**
EricLew	0:80ee8f3b695e	2940	* @brief Clear MSI ready interrupt flag
EricLew	0:80ee8f3b695e	2941	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
EricLew	0:80ee8f3b695e	2942	* @retval None
EricLew	0:80ee8f3b695e	2943	*/
EricLew	0:80ee8f3b695e	2944	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
EricLew	0:80ee8f3b695e	2945	{
EricLew	0:80ee8f3b695e	2946	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
EricLew	0:80ee8f3b695e	2947	}
EricLew	0:80ee8f3b695e	2948
EricLew	0:80ee8f3b695e	2949	/**
EricLew	0:80ee8f3b695e	2950	* @brief Clear HSI ready interrupt flag
EricLew	0:80ee8f3b695e	2951	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
EricLew	0:80ee8f3b695e	2952	* @retval None
EricLew	0:80ee8f3b695e	2953	*/
EricLew	0:80ee8f3b695e	2954	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
EricLew	0:80ee8f3b695e	2955	{
EricLew	0:80ee8f3b695e	2956	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
EricLew	0:80ee8f3b695e	2957	}
EricLew	0:80ee8f3b695e	2958
EricLew	0:80ee8f3b695e	2959	/**
EricLew	0:80ee8f3b695e	2960	* @brief Clear HSE ready interrupt flag
EricLew	0:80ee8f3b695e	2961	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
EricLew	0:80ee8f3b695e	2962	* @retval None
EricLew	0:80ee8f3b695e	2963	*/
EricLew	0:80ee8f3b695e	2964	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
EricLew	0:80ee8f3b695e	2965	{
EricLew	0:80ee8f3b695e	2966	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
EricLew	0:80ee8f3b695e	2967	}
EricLew	0:80ee8f3b695e	2968
EricLew	0:80ee8f3b695e	2969	/**
EricLew	0:80ee8f3b695e	2970	* @brief Clear PLL ready interrupt flag
EricLew	0:80ee8f3b695e	2971	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
EricLew	0:80ee8f3b695e	2972	* @retval None
EricLew	0:80ee8f3b695e	2973	*/
EricLew	0:80ee8f3b695e	2974	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
EricLew	0:80ee8f3b695e	2975	{
EricLew	0:80ee8f3b695e	2976	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
EricLew	0:80ee8f3b695e	2977	}
EricLew	0:80ee8f3b695e	2978
EricLew	0:80ee8f3b695e	2979	/**
EricLew	0:80ee8f3b695e	2980	* @brief Clear PLLSAI1 ready interrupt flag
EricLew	0:80ee8f3b695e	2981	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
EricLew	0:80ee8f3b695e	2982	* @retval None
EricLew	0:80ee8f3b695e	2983	*/
EricLew	0:80ee8f3b695e	2984	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
EricLew	0:80ee8f3b695e	2985	{
EricLew	0:80ee8f3b695e	2986	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
EricLew	0:80ee8f3b695e	2987	}
EricLew	0:80ee8f3b695e	2988
EricLew	0:80ee8f3b695e	2989	/**
EricLew	0:80ee8f3b695e	2990	* @brief Clear PLLSAI1 ready interrupt flag
EricLew	0:80ee8f3b695e	2991	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
EricLew	0:80ee8f3b695e	2992	* @retval None
EricLew	0:80ee8f3b695e	2993	*/
EricLew	0:80ee8f3b695e	2994	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
EricLew	0:80ee8f3b695e	2995	{
EricLew	0:80ee8f3b695e	2996	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
EricLew	0:80ee8f3b695e	2997	}
EricLew	0:80ee8f3b695e	2998
EricLew	0:80ee8f3b695e	2999	/**
EricLew	0:80ee8f3b695e	3000	* @brief Clear Clock security system interrupt flag
EricLew	0:80ee8f3b695e	3001	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
EricLew	0:80ee8f3b695e	3002	* @retval None
EricLew	0:80ee8f3b695e	3003	*/
EricLew	0:80ee8f3b695e	3004	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
EricLew	0:80ee8f3b695e	3005	{
EricLew	0:80ee8f3b695e	3006	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
EricLew	0:80ee8f3b695e	3007	}
EricLew	0:80ee8f3b695e	3008
EricLew	0:80ee8f3b695e	3009	/**
EricLew	0:80ee8f3b695e	3010	* @brief Clear LSE Clock security system interrupt flag
EricLew	0:80ee8f3b695e	3011	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
EricLew	0:80ee8f3b695e	3012	* @retval None
EricLew	0:80ee8f3b695e	3013	*/
EricLew	0:80ee8f3b695e	3014	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
EricLew	0:80ee8f3b695e	3015	{
EricLew	0:80ee8f3b695e	3016	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
EricLew	0:80ee8f3b695e	3017	}
EricLew	0:80ee8f3b695e	3018
EricLew	0:80ee8f3b695e	3019	/**
EricLew	0:80ee8f3b695e	3020	* @brief Check if LSI ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3021	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
EricLew	0:80ee8f3b695e	3022	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3023	*/
EricLew	0:80ee8f3b695e	3024	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
EricLew	0:80ee8f3b695e	3025	{
EricLew	0:80ee8f3b695e	3026	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
EricLew	0:80ee8f3b695e	3027	}
EricLew	0:80ee8f3b695e	3028
EricLew	0:80ee8f3b695e	3029	/**
EricLew	0:80ee8f3b695e	3030	* @brief Check if LSE ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3031	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
EricLew	0:80ee8f3b695e	3032	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3033	*/
EricLew	0:80ee8f3b695e	3034	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
EricLew	0:80ee8f3b695e	3035	{
EricLew	0:80ee8f3b695e	3036	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
EricLew	0:80ee8f3b695e	3037	}
EricLew	0:80ee8f3b695e	3038
EricLew	0:80ee8f3b695e	3039	/**
EricLew	0:80ee8f3b695e	3040	* @brief Check if MSI ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3041	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
EricLew	0:80ee8f3b695e	3042	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3043	*/
EricLew	0:80ee8f3b695e	3044	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
EricLew	0:80ee8f3b695e	3045	{
EricLew	0:80ee8f3b695e	3046	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
EricLew	0:80ee8f3b695e	3047	}
EricLew	0:80ee8f3b695e	3048
EricLew	0:80ee8f3b695e	3049	/**
EricLew	0:80ee8f3b695e	3050	* @brief Check if HSI ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3051	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
EricLew	0:80ee8f3b695e	3052	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3053	*/
EricLew	0:80ee8f3b695e	3054	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
EricLew	0:80ee8f3b695e	3055	{
EricLew	0:80ee8f3b695e	3056	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
EricLew	0:80ee8f3b695e	3057	}
EricLew	0:80ee8f3b695e	3058
EricLew	0:80ee8f3b695e	3059	/**
EricLew	0:80ee8f3b695e	3060	* @brief Check if HSE ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3061	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
EricLew	0:80ee8f3b695e	3062	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3063	*/
EricLew	0:80ee8f3b695e	3064	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
EricLew	0:80ee8f3b695e	3065	{
EricLew	0:80ee8f3b695e	3066	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
EricLew	0:80ee8f3b695e	3067	}
EricLew	0:80ee8f3b695e	3068
EricLew	0:80ee8f3b695e	3069	/**
EricLew	0:80ee8f3b695e	3070	* @brief Check if PLL ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3071	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
EricLew	0:80ee8f3b695e	3072	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3073	*/
EricLew	0:80ee8f3b695e	3074	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
EricLew	0:80ee8f3b695e	3075	{
EricLew	0:80ee8f3b695e	3076	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
EricLew	0:80ee8f3b695e	3077	}
EricLew	0:80ee8f3b695e	3078
EricLew	0:80ee8f3b695e	3079	/**
EricLew	0:80ee8f3b695e	3080	* @brief Check if PLLSAI1 ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3081	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
EricLew	0:80ee8f3b695e	3082	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3083	*/
EricLew	0:80ee8f3b695e	3084	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
EricLew	0:80ee8f3b695e	3085	{
EricLew	0:80ee8f3b695e	3086	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
EricLew	0:80ee8f3b695e	3087	}
EricLew	0:80ee8f3b695e	3088
EricLew	0:80ee8f3b695e	3089	/**
EricLew	0:80ee8f3b695e	3090	* @brief Check if PLLSAI1 ready interrupt occurred or not
EricLew	0:80ee8f3b695e	3091	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
EricLew	0:80ee8f3b695e	3092	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3093	*/
EricLew	0:80ee8f3b695e	3094	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
EricLew	0:80ee8f3b695e	3095	{
EricLew	0:80ee8f3b695e	3096	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
EricLew	0:80ee8f3b695e	3097	}
EricLew	0:80ee8f3b695e	3098
EricLew	0:80ee8f3b695e	3099	/**
EricLew	0:80ee8f3b695e	3100	* @brief Check if Clock security system interrupt occurred or not
EricLew	0:80ee8f3b695e	3101	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
EricLew	0:80ee8f3b695e	3102	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3103	*/
EricLew	0:80ee8f3b695e	3104	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
EricLew	0:80ee8f3b695e	3105	{
EricLew	0:80ee8f3b695e	3106	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
EricLew	0:80ee8f3b695e	3107	}
EricLew	0:80ee8f3b695e	3108
EricLew	0:80ee8f3b695e	3109	/**
EricLew	0:80ee8f3b695e	3110	* @brief Check if LSE Clock security system interrupt occurred or not
EricLew	0:80ee8f3b695e	3111	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
EricLew	0:80ee8f3b695e	3112	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3113	*/
EricLew	0:80ee8f3b695e	3114	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
EricLew	0:80ee8f3b695e	3115	{
EricLew	0:80ee8f3b695e	3116	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
EricLew	0:80ee8f3b695e	3117	}
EricLew	0:80ee8f3b695e	3118
EricLew	0:80ee8f3b695e	3119	/**
EricLew	0:80ee8f3b695e	3120	* @brief Check if RCC flag FW reset is set or not.
EricLew	0:80ee8f3b695e	3121	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
EricLew	0:80ee8f3b695e	3122	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3123	*/
EricLew	0:80ee8f3b695e	3124	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
EricLew	0:80ee8f3b695e	3125	{
EricLew	0:80ee8f3b695e	3126	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
EricLew	0:80ee8f3b695e	3127	}
EricLew	0:80ee8f3b695e	3128
EricLew	0:80ee8f3b695e	3129	/**
EricLew	0:80ee8f3b695e	3130	* @brief Check if RCC flag Independent Watchdog reset is set or not.
EricLew	0:80ee8f3b695e	3131	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
EricLew	0:80ee8f3b695e	3132	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3133	*/
EricLew	0:80ee8f3b695e	3134	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
EricLew	0:80ee8f3b695e	3135	{
EricLew	0:80ee8f3b695e	3136	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
EricLew	0:80ee8f3b695e	3137	}
EricLew	0:80ee8f3b695e	3138
EricLew	0:80ee8f3b695e	3139	/**
EricLew	0:80ee8f3b695e	3140	* @brief Check if RCC flag Low Power reset is set or not.
EricLew	0:80ee8f3b695e	3141	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
EricLew	0:80ee8f3b695e	3142	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3143	*/
EricLew	0:80ee8f3b695e	3144	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
EricLew	0:80ee8f3b695e	3145	{
EricLew	0:80ee8f3b695e	3146	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
EricLew	0:80ee8f3b695e	3147	}
EricLew	0:80ee8f3b695e	3148
EricLew	0:80ee8f3b695e	3149	/**
EricLew	0:80ee8f3b695e	3150	* @brief Check if RCC flag is set or not.
EricLew	0:80ee8f3b695e	3151	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
EricLew	0:80ee8f3b695e	3152	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3153	*/
EricLew	0:80ee8f3b695e	3154	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
EricLew	0:80ee8f3b695e	3155	{
EricLew	0:80ee8f3b695e	3156	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
EricLew	0:80ee8f3b695e	3157	}
EricLew	0:80ee8f3b695e	3158
EricLew	0:80ee8f3b695e	3159	/**
EricLew	0:80ee8f3b695e	3160	* @brief Check if RCC flag Pin reset is set or not.
EricLew	0:80ee8f3b695e	3161	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
EricLew	0:80ee8f3b695e	3162	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3163	*/
EricLew	0:80ee8f3b695e	3164	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
EricLew	0:80ee8f3b695e	3165	{
EricLew	0:80ee8f3b695e	3166	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
EricLew	0:80ee8f3b695e	3167	}
EricLew	0:80ee8f3b695e	3168
EricLew	0:80ee8f3b695e	3169	/**
EricLew	0:80ee8f3b695e	3170	* @brief Check if RCC flag Software reset is set or not.
EricLew	0:80ee8f3b695e	3171	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
EricLew	0:80ee8f3b695e	3172	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3173	*/
EricLew	0:80ee8f3b695e	3174	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
EricLew	0:80ee8f3b695e	3175	{
EricLew	0:80ee8f3b695e	3176	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
EricLew	0:80ee8f3b695e	3177	}
EricLew	0:80ee8f3b695e	3178
EricLew	0:80ee8f3b695e	3179	/**
EricLew	0:80ee8f3b695e	3180	* @brief Check if RCC flag Window Watchdog reset is set or not.
EricLew	0:80ee8f3b695e	3181	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
EricLew	0:80ee8f3b695e	3182	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3183	*/
EricLew	0:80ee8f3b695e	3184	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
EricLew	0:80ee8f3b695e	3185	{
EricLew	0:80ee8f3b695e	3186	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
EricLew	0:80ee8f3b695e	3187	}
EricLew	0:80ee8f3b695e	3188
EricLew	0:80ee8f3b695e	3189	/**
EricLew	0:80ee8f3b695e	3190	* @brief Check if RCC flag BOR reset is set or not.
EricLew	0:80ee8f3b695e	3191	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
EricLew	0:80ee8f3b695e	3192	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3193	*/
EricLew	0:80ee8f3b695e	3194	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
EricLew	0:80ee8f3b695e	3195	{
EricLew	0:80ee8f3b695e	3196	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
EricLew	0:80ee8f3b695e	3197	}
EricLew	0:80ee8f3b695e	3198
EricLew	0:80ee8f3b695e	3199	/**
EricLew	0:80ee8f3b695e	3200	* @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST,
EricLew	0:80ee8f3b695e	3201	* RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST,
EricLew	0:80ee8f3b695e	3202	* RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST
EricLew	0:80ee8f3b695e	3203	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
EricLew	0:80ee8f3b695e	3204	* @retval None
EricLew	0:80ee8f3b695e	3205	*/
EricLew	0:80ee8f3b695e	3206	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
EricLew	0:80ee8f3b695e	3207	{
EricLew	0:80ee8f3b695e	3208	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
EricLew	0:80ee8f3b695e	3209	}
EricLew	0:80ee8f3b695e	3210
EricLew	0:80ee8f3b695e	3211	/**
EricLew	0:80ee8f3b695e	3212	* @}
EricLew	0:80ee8f3b695e	3213	*/
EricLew	0:80ee8f3b695e	3214
EricLew	0:80ee8f3b695e	3215	/** @defgroup RCC_LL_EF_IT_Management IT Management
EricLew	0:80ee8f3b695e	3216	* @{
EricLew	0:80ee8f3b695e	3217	*/
EricLew	0:80ee8f3b695e	3218
EricLew	0:80ee8f3b695e	3219	/**
EricLew	0:80ee8f3b695e	3220	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3221	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
EricLew	0:80ee8f3b695e	3222	* @retval None
EricLew	0:80ee8f3b695e	3223	*/
EricLew	0:80ee8f3b695e	3224	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
EricLew	0:80ee8f3b695e	3225	{
EricLew	0:80ee8f3b695e	3226	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
EricLew	0:80ee8f3b695e	3227	}
EricLew	0:80ee8f3b695e	3228
EricLew	0:80ee8f3b695e	3229	/**
EricLew	0:80ee8f3b695e	3230	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3231	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
EricLew	0:80ee8f3b695e	3232	* @retval None
EricLew	0:80ee8f3b695e	3233	*/
EricLew	0:80ee8f3b695e	3234	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
EricLew	0:80ee8f3b695e	3235	{
EricLew	0:80ee8f3b695e	3236	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
EricLew	0:80ee8f3b695e	3237	}
EricLew	0:80ee8f3b695e	3238
EricLew	0:80ee8f3b695e	3239	/**
EricLew	0:80ee8f3b695e	3240	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3241	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
EricLew	0:80ee8f3b695e	3242	* @retval None
EricLew	0:80ee8f3b695e	3243	*/
EricLew	0:80ee8f3b695e	3244	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
EricLew	0:80ee8f3b695e	3245	{
EricLew	0:80ee8f3b695e	3246	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
EricLew	0:80ee8f3b695e	3247	}
EricLew	0:80ee8f3b695e	3248
EricLew	0:80ee8f3b695e	3249	/**
EricLew	0:80ee8f3b695e	3250	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3251	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
EricLew	0:80ee8f3b695e	3252	* @retval None
EricLew	0:80ee8f3b695e	3253	*/
EricLew	0:80ee8f3b695e	3254	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
EricLew	0:80ee8f3b695e	3255	{
EricLew	0:80ee8f3b695e	3256	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
EricLew	0:80ee8f3b695e	3257	}
EricLew	0:80ee8f3b695e	3258
EricLew	0:80ee8f3b695e	3259	/**
EricLew	0:80ee8f3b695e	3260	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3261	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
EricLew	0:80ee8f3b695e	3262	* @retval None
EricLew	0:80ee8f3b695e	3263	*/
EricLew	0:80ee8f3b695e	3264	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
EricLew	0:80ee8f3b695e	3265	{
EricLew	0:80ee8f3b695e	3266	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
EricLew	0:80ee8f3b695e	3267	}
EricLew	0:80ee8f3b695e	3268
EricLew	0:80ee8f3b695e	3269	/**
EricLew	0:80ee8f3b695e	3270	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3271	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
EricLew	0:80ee8f3b695e	3272	* @retval None
EricLew	0:80ee8f3b695e	3273	*/
EricLew	0:80ee8f3b695e	3274	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
EricLew	0:80ee8f3b695e	3275	{
EricLew	0:80ee8f3b695e	3276	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
EricLew	0:80ee8f3b695e	3277	}
EricLew	0:80ee8f3b695e	3278
EricLew	0:80ee8f3b695e	3279	/**
EricLew	0:80ee8f3b695e	3280	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3281	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
EricLew	0:80ee8f3b695e	3282	* @retval None
EricLew	0:80ee8f3b695e	3283	*/
EricLew	0:80ee8f3b695e	3284	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
EricLew	0:80ee8f3b695e	3285	{
EricLew	0:80ee8f3b695e	3286	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
EricLew	0:80ee8f3b695e	3287	}
EricLew	0:80ee8f3b695e	3288
EricLew	0:80ee8f3b695e	3289	/**
EricLew	0:80ee8f3b695e	3290	* @brief Enable RCC interrupt
EricLew	0:80ee8f3b695e	3291	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
EricLew	0:80ee8f3b695e	3292	* @retval None
EricLew	0:80ee8f3b695e	3293	*/
EricLew	0:80ee8f3b695e	3294	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
EricLew	0:80ee8f3b695e	3295	{
EricLew	0:80ee8f3b695e	3296	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
EricLew	0:80ee8f3b695e	3297	}
EricLew	0:80ee8f3b695e	3298
EricLew	0:80ee8f3b695e	3299	/**
EricLew	0:80ee8f3b695e	3300	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3301	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
EricLew	0:80ee8f3b695e	3302	* @retval None
EricLew	0:80ee8f3b695e	3303	*/
EricLew	0:80ee8f3b695e	3304	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
EricLew	0:80ee8f3b695e	3305	{
EricLew	0:80ee8f3b695e	3306	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
EricLew	0:80ee8f3b695e	3307	}
EricLew	0:80ee8f3b695e	3308
EricLew	0:80ee8f3b695e	3309	/**
EricLew	0:80ee8f3b695e	3310	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3311	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
EricLew	0:80ee8f3b695e	3312	* @retval None
EricLew	0:80ee8f3b695e	3313	*/
EricLew	0:80ee8f3b695e	3314	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
EricLew	0:80ee8f3b695e	3315	{
EricLew	0:80ee8f3b695e	3316	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
EricLew	0:80ee8f3b695e	3317	}
EricLew	0:80ee8f3b695e	3318
EricLew	0:80ee8f3b695e	3319	/**
EricLew	0:80ee8f3b695e	3320	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3321	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
EricLew	0:80ee8f3b695e	3322	* @retval None
EricLew	0:80ee8f3b695e	3323	*/
EricLew	0:80ee8f3b695e	3324	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
EricLew	0:80ee8f3b695e	3325	{
EricLew	0:80ee8f3b695e	3326	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
EricLew	0:80ee8f3b695e	3327	}
EricLew	0:80ee8f3b695e	3328
EricLew	0:80ee8f3b695e	3329	/**
EricLew	0:80ee8f3b695e	3330	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3331	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
EricLew	0:80ee8f3b695e	3332	* @retval None
EricLew	0:80ee8f3b695e	3333	*/
EricLew	0:80ee8f3b695e	3334	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
EricLew	0:80ee8f3b695e	3335	{
EricLew	0:80ee8f3b695e	3336	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
EricLew	0:80ee8f3b695e	3337	}
EricLew	0:80ee8f3b695e	3338
EricLew	0:80ee8f3b695e	3339	/**
EricLew	0:80ee8f3b695e	3340	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3341	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
EricLew	0:80ee8f3b695e	3342	* @retval None
EricLew	0:80ee8f3b695e	3343	*/
EricLew	0:80ee8f3b695e	3344	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
EricLew	0:80ee8f3b695e	3345	{
EricLew	0:80ee8f3b695e	3346	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
EricLew	0:80ee8f3b695e	3347	}
EricLew	0:80ee8f3b695e	3348
EricLew	0:80ee8f3b695e	3349	/**
EricLew	0:80ee8f3b695e	3350	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3351	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
EricLew	0:80ee8f3b695e	3352	* @retval None
EricLew	0:80ee8f3b695e	3353	*/
EricLew	0:80ee8f3b695e	3354	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
EricLew	0:80ee8f3b695e	3355	{
EricLew	0:80ee8f3b695e	3356	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
EricLew	0:80ee8f3b695e	3357	}
EricLew	0:80ee8f3b695e	3358
EricLew	0:80ee8f3b695e	3359	/**
EricLew	0:80ee8f3b695e	3360	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3361	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
EricLew	0:80ee8f3b695e	3362	* @retval None
EricLew	0:80ee8f3b695e	3363	*/
EricLew	0:80ee8f3b695e	3364	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
EricLew	0:80ee8f3b695e	3365	{
EricLew	0:80ee8f3b695e	3366	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
EricLew	0:80ee8f3b695e	3367	}
EricLew	0:80ee8f3b695e	3368
EricLew	0:80ee8f3b695e	3369	/**
EricLew	0:80ee8f3b695e	3370	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3371	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
EricLew	0:80ee8f3b695e	3372	* @retval None
EricLew	0:80ee8f3b695e	3373	*/
EricLew	0:80ee8f3b695e	3374	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
EricLew	0:80ee8f3b695e	3375	{
EricLew	0:80ee8f3b695e	3376	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
EricLew	0:80ee8f3b695e	3377	}
EricLew	0:80ee8f3b695e	3378
EricLew	0:80ee8f3b695e	3379	/**
EricLew	0:80ee8f3b695e	3380	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3381	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
EricLew	0:80ee8f3b695e	3382	* @retval None
EricLew	0:80ee8f3b695e	3383	*/
EricLew	0:80ee8f3b695e	3384	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
EricLew	0:80ee8f3b695e	3385	{
EricLew	0:80ee8f3b695e	3386	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
EricLew	0:80ee8f3b695e	3387	}
EricLew	0:80ee8f3b695e	3388
EricLew	0:80ee8f3b695e	3389	/**
EricLew	0:80ee8f3b695e	3390	* @brief Disable RCC interrupt
EricLew	0:80ee8f3b695e	3391	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
EricLew	0:80ee8f3b695e	3392	* @retval None
EricLew	0:80ee8f3b695e	3393	*/
EricLew	0:80ee8f3b695e	3394	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
EricLew	0:80ee8f3b695e	3395	{
EricLew	0:80ee8f3b695e	3396	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
EricLew	0:80ee8f3b695e	3397	}
EricLew	0:80ee8f3b695e	3398
EricLew	0:80ee8f3b695e	3399	/**
EricLew	0:80ee8f3b695e	3400	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3401	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
EricLew	0:80ee8f3b695e	3402	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3403	*/
EricLew	0:80ee8f3b695e	3404	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
EricLew	0:80ee8f3b695e	3405	{
EricLew	0:80ee8f3b695e	3406	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
EricLew	0:80ee8f3b695e	3407	}
EricLew	0:80ee8f3b695e	3408
EricLew	0:80ee8f3b695e	3409	/**
EricLew	0:80ee8f3b695e	3410	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3411	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
EricLew	0:80ee8f3b695e	3412	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3413	*/
EricLew	0:80ee8f3b695e	3414	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
EricLew	0:80ee8f3b695e	3415	{
EricLew	0:80ee8f3b695e	3416	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
EricLew	0:80ee8f3b695e	3417	}
EricLew	0:80ee8f3b695e	3418
EricLew	0:80ee8f3b695e	3419	/**
EricLew	0:80ee8f3b695e	3420	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3421	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
EricLew	0:80ee8f3b695e	3422	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3423	*/
EricLew	0:80ee8f3b695e	3424	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
EricLew	0:80ee8f3b695e	3425	{
EricLew	0:80ee8f3b695e	3426	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
EricLew	0:80ee8f3b695e	3427	}
EricLew	0:80ee8f3b695e	3428
EricLew	0:80ee8f3b695e	3429	/**
EricLew	0:80ee8f3b695e	3430	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3431	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
EricLew	0:80ee8f3b695e	3432	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3433	*/
EricLew	0:80ee8f3b695e	3434	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
EricLew	0:80ee8f3b695e	3435	{
EricLew	0:80ee8f3b695e	3436	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
EricLew	0:80ee8f3b695e	3437	}
EricLew	0:80ee8f3b695e	3438
EricLew	0:80ee8f3b695e	3439	/**
EricLew	0:80ee8f3b695e	3440	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3441	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
EricLew	0:80ee8f3b695e	3442	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3443	*/
EricLew	0:80ee8f3b695e	3444	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
EricLew	0:80ee8f3b695e	3445	{
EricLew	0:80ee8f3b695e	3446	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
EricLew	0:80ee8f3b695e	3447	}
EricLew	0:80ee8f3b695e	3448
EricLew	0:80ee8f3b695e	3449	/**
EricLew	0:80ee8f3b695e	3450	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3451	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
EricLew	0:80ee8f3b695e	3452	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3453	*/
EricLew	0:80ee8f3b695e	3454	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
EricLew	0:80ee8f3b695e	3455	{
EricLew	0:80ee8f3b695e	3456	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
EricLew	0:80ee8f3b695e	3457	}
EricLew	0:80ee8f3b695e	3458
EricLew	0:80ee8f3b695e	3459	/**
EricLew	0:80ee8f3b695e	3460	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3461	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
EricLew	0:80ee8f3b695e	3462	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3463	*/
EricLew	0:80ee8f3b695e	3464	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
EricLew	0:80ee8f3b695e	3465	{
EricLew	0:80ee8f3b695e	3466	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
EricLew	0:80ee8f3b695e	3467	}
EricLew	0:80ee8f3b695e	3468
EricLew	0:80ee8f3b695e	3469	/**
EricLew	0:80ee8f3b695e	3470	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3471	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
EricLew	0:80ee8f3b695e	3472	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3473	*/
EricLew	0:80ee8f3b695e	3474	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
EricLew	0:80ee8f3b695e	3475	{
EricLew	0:80ee8f3b695e	3476	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
EricLew	0:80ee8f3b695e	3477	}
EricLew	0:80ee8f3b695e	3478
EricLew	0:80ee8f3b695e	3479	/**
EricLew	0:80ee8f3b695e	3480	* @brief Checks if the specified RCC interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	3481	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
EricLew	0:80ee8f3b695e	3482	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3483	*/
EricLew	0:80ee8f3b695e	3484	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
EricLew	0:80ee8f3b695e	3485	{
EricLew	0:80ee8f3b695e	3486	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
EricLew	0:80ee8f3b695e	3487	}
EricLew	0:80ee8f3b695e	3488
EricLew	0:80ee8f3b695e	3489	/**
EricLew	0:80ee8f3b695e	3490	* @}
EricLew	0:80ee8f3b695e	3491	*/
EricLew	0:80ee8f3b695e	3492
EricLew	0:80ee8f3b695e	3493
EricLew	0:80ee8f3b695e	3494	/**
EricLew	0:80ee8f3b695e	3495	* @}
EricLew	0:80ee8f3b695e	3496	*/
EricLew	0:80ee8f3b695e	3497
EricLew	0:80ee8f3b695e	3498	/**
EricLew	0:80ee8f3b695e	3499	* @}
EricLew	0:80ee8f3b695e	3500	*/
EricLew	0:80ee8f3b695e	3501
EricLew	0:80ee8f3b695e	3502	#endif /* defined(RCC) */
EricLew	0:80ee8f3b695e	3503
EricLew	0:80ee8f3b695e	3504	/**
EricLew	0:80ee8f3b695e	3505	* @}
EricLew	0:80ee8f3b695e	3506	*/
EricLew	0:80ee8f3b695e	3507
EricLew	0:80ee8f3b695e	3508	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	3509	}
EricLew	0:80ee8f3b695e	3510	#endif
EricLew	0:80ee8f3b695e	3511
EricLew	0:80ee8f3b695e	3512	#endif /* __STM32L4xx_LL_RCC_H */
EricLew	0:80ee8f3b695e	3513
EricLew	0:80ee8f3b695e	3514	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	3515

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_rcc.h@0:80ee8f3b695e, 2015-11-02 (annotated)

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