Eric Lewiston / STM32L4xx_HAL_Driver

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Dependents:   BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Src/stm32l4xx_hal_nor.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_nor.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief NOR HAL module driver.
EricLew 0:80ee8f3b695e 8 * This file provides a generic firmware to drive NOR memories mounted
EricLew 0:80ee8f3b695e 9 * as external device.
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 @verbatim
EricLew 0:80ee8f3b695e 12 ==============================================================================
EricLew 0:80ee8f3b695e 13 ##### How to use this driver #####
EricLew 0:80ee8f3b695e 14 ==============================================================================
EricLew 0:80ee8f3b695e 15 [..]
EricLew 0:80ee8f3b695e 16 This driver is a generic layered driver which contains a set of APIs used to
EricLew 0:80ee8f3b695e 17 control NOR flash memories. It uses the FMC layer functions to interface
EricLew 0:80ee8f3b695e 18 with NOR devices. This driver is used as follows:
EricLew 0:80ee8f3b695e 19
EricLew 0:80ee8f3b695e 20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
EricLew 0:80ee8f3b695e 21 with control and timing parameters for both normal and extended mode.
EricLew 0:80ee8f3b695e 22
EricLew 0:80ee8f3b695e 23 (+) Read NOR flash memory manufacturer code and device IDs using the function
EricLew 0:80ee8f3b695e 24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
EricLew 0:80ee8f3b695e 25 structure declared by the function caller.
EricLew 0:80ee8f3b695e 26
EricLew 0:80ee8f3b695e 27 (+) Access NOR flash memory by read/write data unit operations using the functions
EricLew 0:80ee8f3b695e 28 HAL_NOR_Read(), HAL_NOR_Program().
EricLew 0:80ee8f3b695e 29
EricLew 0:80ee8f3b695e 30 (+) Perform NOR flash erase block/chip operations using the functions
EricLew 0:80ee8f3b695e 31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
EricLew 0:80ee8f3b695e 32
EricLew 0:80ee8f3b695e 33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
EricLew 0:80ee8f3b695e 34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
EricLew 0:80ee8f3b695e 35 structure declared by the function caller.
EricLew 0:80ee8f3b695e 36
EricLew 0:80ee8f3b695e 37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
EricLew 0:80ee8f3b695e 38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
EricLew 0:80ee8f3b695e 39
EricLew 0:80ee8f3b695e 40 (+) You can monitor the NOR device HAL state by calling the function
EricLew 0:80ee8f3b695e 41 HAL_NOR_GetState()
EricLew 0:80ee8f3b695e 42 [..]
EricLew 0:80ee8f3b695e 43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
EricLew 0:80ee8f3b695e 44 If a NOR flash device contains different operations and/or implementations,
EricLew 0:80ee8f3b695e 45 it should be implemented separately.
EricLew 0:80ee8f3b695e 46
EricLew 0:80ee8f3b695e 47 *** NOR HAL driver macros list ***
EricLew 0:80ee8f3b695e 48 =============================================
EricLew 0:80ee8f3b695e 49 [..]
EricLew 0:80ee8f3b695e 50 Below the list of most used macros in NOR HAL driver.
EricLew 0:80ee8f3b695e 51
EricLew 0:80ee8f3b695e 52 (+) NOR_WRITE : NOR memory write data to specified address
EricLew 0:80ee8f3b695e 53
EricLew 0:80ee8f3b695e 54 @endverbatim
EricLew 0:80ee8f3b695e 55 ******************************************************************************
EricLew 0:80ee8f3b695e 56 * @attention
EricLew 0:80ee8f3b695e 57 *
EricLew 0:80ee8f3b695e 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 59 *
EricLew 0:80ee8f3b695e 60 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 61 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 62 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 63 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 65 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 66 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 68 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 69 * without specific prior written permission.
EricLew 0:80ee8f3b695e 70 *
EricLew 0:80ee8f3b695e 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 81 *
EricLew 0:80ee8f3b695e 82 ******************************************************************************
EricLew 0:80ee8f3b695e 83 */
EricLew 0:80ee8f3b695e 84
EricLew 0:80ee8f3b695e 85 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 86 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 87
EricLew 0:80ee8f3b695e 88 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 89 * @{
EricLew 0:80ee8f3b695e 90 */
EricLew 0:80ee8f3b695e 91
EricLew 0:80ee8f3b695e 92 #ifdef HAL_NOR_MODULE_ENABLED
EricLew 0:80ee8f3b695e 93
EricLew 0:80ee8f3b695e 94 /** @defgroup NOR NOR
EricLew 0:80ee8f3b695e 95 * @brief NOR HAL module driver
EricLew 0:80ee8f3b695e 96 * @{
EricLew 0:80ee8f3b695e 97 */
EricLew 0:80ee8f3b695e 98 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 99 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 100 /** @defgroup NOR_Private_Constants NOR Private Constants
EricLew 0:80ee8f3b695e 101 * @{
EricLew 0:80ee8f3b695e 102 */
EricLew 0:80ee8f3b695e 103
EricLew 0:80ee8f3b695e 104 /* Constants to define address to set to write a command */
EricLew 0:80ee8f3b695e 105 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555
EricLew 0:80ee8f3b695e 106 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055
EricLew 0:80ee8f3b695e 107 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA
EricLew 0:80ee8f3b695e 108 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555
EricLew 0:80ee8f3b695e 109 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555
EricLew 0:80ee8f3b695e 110 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA
EricLew 0:80ee8f3b695e 111 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555
EricLew 0:80ee8f3b695e 112
EricLew 0:80ee8f3b695e 113 /* Constants to define data to program a command */
EricLew 0:80ee8f3b695e 114 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0
EricLew 0:80ee8f3b695e 115 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AA
EricLew 0:80ee8f3b695e 116 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055
EricLew 0:80ee8f3b695e 117 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090
EricLew 0:80ee8f3b695e 118 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0
EricLew 0:80ee8f3b695e 119 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080
EricLew 0:80ee8f3b695e 120 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA
EricLew 0:80ee8f3b695e 121 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055
EricLew 0:80ee8f3b695e 122 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010
EricLew 0:80ee8f3b695e 123 #define NOR_CMD_DATA_CFI (uint16_t)0x0098
EricLew 0:80ee8f3b695e 124
EricLew 0:80ee8f3b695e 125 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25
EricLew 0:80ee8f3b695e 126 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
EricLew 0:80ee8f3b695e 127 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
EricLew 0:80ee8f3b695e 128
EricLew 0:80ee8f3b695e 129 /* Mask on NOR STATUS REGISTER */
EricLew 0:80ee8f3b695e 130 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
EricLew 0:80ee8f3b695e 131 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
EricLew 0:80ee8f3b695e 132
EricLew 0:80ee8f3b695e 133 /**
EricLew 0:80ee8f3b695e 134 * @}
EricLew 0:80ee8f3b695e 135 */
EricLew 0:80ee8f3b695e 136
EricLew 0:80ee8f3b695e 137 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 138 /** @defgroup NOR_Private_Macros NOR Private Macros
EricLew 0:80ee8f3b695e 139 * @{
EricLew 0:80ee8f3b695e 140 */
EricLew 0:80ee8f3b695e 141
EricLew 0:80ee8f3b695e 142 /**
EricLew 0:80ee8f3b695e 143 * @}
EricLew 0:80ee8f3b695e 144 */
EricLew 0:80ee8f3b695e 145
EricLew 0:80ee8f3b695e 146 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 147
EricLew 0:80ee8f3b695e 148 /** @defgroup NOR_Private_Variables NOR Private Variables
EricLew 0:80ee8f3b695e 149 * @{
EricLew 0:80ee8f3b695e 150 */
EricLew 0:80ee8f3b695e 151
EricLew 0:80ee8f3b695e 152 static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
EricLew 0:80ee8f3b695e 153
EricLew 0:80ee8f3b695e 154 /**
EricLew 0:80ee8f3b695e 155 * @}
EricLew 0:80ee8f3b695e 156 */
EricLew 0:80ee8f3b695e 157
EricLew 0:80ee8f3b695e 158 /* Exported functions ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 159
EricLew 0:80ee8f3b695e 160 /** @defgroup NOR_Exported_Functions NOR Exported Functions
EricLew 0:80ee8f3b695e 161 * @{
EricLew 0:80ee8f3b695e 162 */
EricLew 0:80ee8f3b695e 163
EricLew 0:80ee8f3b695e 164 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 165 * @brief Initialization and Configuration functions
EricLew 0:80ee8f3b695e 166 *
EricLew 0:80ee8f3b695e 167 @verbatim
EricLew 0:80ee8f3b695e 168 ==============================================================================
EricLew 0:80ee8f3b695e 169 ##### NOR Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 170 ==============================================================================
EricLew 0:80ee8f3b695e 171 [..]
EricLew 0:80ee8f3b695e 172 This section provides functions allowing to initialize/de-initialize
EricLew 0:80ee8f3b695e 173 the NOR memory
EricLew 0:80ee8f3b695e 174
EricLew 0:80ee8f3b695e 175 @endverbatim
EricLew 0:80ee8f3b695e 176 * @{
EricLew 0:80ee8f3b695e 177 */
EricLew 0:80ee8f3b695e 178
EricLew 0:80ee8f3b695e 179 /**
EricLew 0:80ee8f3b695e 180 * @brief Perform the NOR memory Initialization sequence.
EricLew 0:80ee8f3b695e 181 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 182 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 183 * @param Timing: pointer to NOR control timing structure
EricLew 0:80ee8f3b695e 184 * @param ExtTiming: pointer to NOR extended mode timing structure
EricLew 0:80ee8f3b695e 185 * @retval HAL status
EricLew 0:80ee8f3b695e 186 */
EricLew 0:80ee8f3b695e 187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
EricLew 0:80ee8f3b695e 188 {
EricLew 0:80ee8f3b695e 189 /* Check the NOR handle parameter */
EricLew 0:80ee8f3b695e 190 if(hnor == NULL)
EricLew 0:80ee8f3b695e 191 {
EricLew 0:80ee8f3b695e 192 return HAL_ERROR;
EricLew 0:80ee8f3b695e 193 }
EricLew 0:80ee8f3b695e 194
EricLew 0:80ee8f3b695e 195 if(hnor->State == HAL_NOR_STATE_RESET)
EricLew 0:80ee8f3b695e 196 {
EricLew 0:80ee8f3b695e 197 /* Allocate lock resource and initialize it */
EricLew 0:80ee8f3b695e 198 hnor->Lock = HAL_UNLOCKED;
EricLew 0:80ee8f3b695e 199
EricLew 0:80ee8f3b695e 200 /* Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 201 HAL_NOR_MspInit(hnor);
EricLew 0:80ee8f3b695e 202 }
EricLew 0:80ee8f3b695e 203
EricLew 0:80ee8f3b695e 204 /* Initialize NOR control Interface */
EricLew 0:80ee8f3b695e 205 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
EricLew 0:80ee8f3b695e 206
EricLew 0:80ee8f3b695e 207 /* Initialize NOR timing Interface */
EricLew 0:80ee8f3b695e 208 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
EricLew 0:80ee8f3b695e 209
EricLew 0:80ee8f3b695e 210 /* Initialize NOR extended mode timing Interface */
EricLew 0:80ee8f3b695e 211 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
EricLew 0:80ee8f3b695e 212
EricLew 0:80ee8f3b695e 213 /* Enable the NORSRAM device */
EricLew 0:80ee8f3b695e 214 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
EricLew 0:80ee8f3b695e 215
EricLew 0:80ee8f3b695e 216 /* Initialize NOR Memory Data Width*/
EricLew 0:80ee8f3b695e 217 if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
EricLew 0:80ee8f3b695e 218 {
EricLew 0:80ee8f3b695e 219 uwNORMemoryDataWidth = NOR_MEMORY_8B;
EricLew 0:80ee8f3b695e 220 }
EricLew 0:80ee8f3b695e 221 else
EricLew 0:80ee8f3b695e 222 {
EricLew 0:80ee8f3b695e 223 uwNORMemoryDataWidth = NOR_MEMORY_16B;
EricLew 0:80ee8f3b695e 224 }
EricLew 0:80ee8f3b695e 225
EricLew 0:80ee8f3b695e 226 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 227 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 228
EricLew 0:80ee8f3b695e 229 return HAL_OK;
EricLew 0:80ee8f3b695e 230 }
EricLew 0:80ee8f3b695e 231
EricLew 0:80ee8f3b695e 232 /**
EricLew 0:80ee8f3b695e 233 * @brief Perform NOR memory De-Initialization sequence.
EricLew 0:80ee8f3b695e 234 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 235 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 236 * @retval HAL status
EricLew 0:80ee8f3b695e 237 */
EricLew 0:80ee8f3b695e 238 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 239 {
EricLew 0:80ee8f3b695e 240 /* De-Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 241 HAL_NOR_MspDeInit(hnor);
EricLew 0:80ee8f3b695e 242
EricLew 0:80ee8f3b695e 243 /* Configure the NOR registers with their reset values */
EricLew 0:80ee8f3b695e 244 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
EricLew 0:80ee8f3b695e 245
EricLew 0:80ee8f3b695e 246 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 247 hnor->State = HAL_NOR_STATE_RESET;
EricLew 0:80ee8f3b695e 248
EricLew 0:80ee8f3b695e 249 /* Release Lock */
EricLew 0:80ee8f3b695e 250 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 251
EricLew 0:80ee8f3b695e 252 return HAL_OK;
EricLew 0:80ee8f3b695e 253 }
EricLew 0:80ee8f3b695e 254
EricLew 0:80ee8f3b695e 255 /**
EricLew 0:80ee8f3b695e 256 * @brief Initialize the NOR MSP.
EricLew 0:80ee8f3b695e 257 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 258 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 259 * @retval None
EricLew 0:80ee8f3b695e 260 */
EricLew 0:80ee8f3b695e 261 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 262 {
EricLew 0:80ee8f3b695e 263 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 264 the HAL_NOR_MspInit could be implemented in the user file
EricLew 0:80ee8f3b695e 265 */
EricLew 0:80ee8f3b695e 266 }
EricLew 0:80ee8f3b695e 267
EricLew 0:80ee8f3b695e 268 /**
EricLew 0:80ee8f3b695e 269 * @brief DeInitialize the NOR MSP.
EricLew 0:80ee8f3b695e 270 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 271 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 272 * @retval None
EricLew 0:80ee8f3b695e 273 */
EricLew 0:80ee8f3b695e 274 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 275 {
EricLew 0:80ee8f3b695e 276 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 277 the HAL_NOR_MspDeInit could be implemented in the user file
EricLew 0:80ee8f3b695e 278 */
EricLew 0:80ee8f3b695e 279 }
EricLew 0:80ee8f3b695e 280
EricLew 0:80ee8f3b695e 281 /**
EricLew 0:80ee8f3b695e 282 * @brief NOR MSP Wait for Ready/Busy signal.
EricLew 0:80ee8f3b695e 283 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 284 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 285 * @param Timeout: Maximum timeout value
EricLew 0:80ee8f3b695e 286 * @retval None
EricLew 0:80ee8f3b695e 287 */
EricLew 0:80ee8f3b695e 288 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
EricLew 0:80ee8f3b695e 289 {
EricLew 0:80ee8f3b695e 290 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 291 the HAL_NOR_MspWait could be implemented in the user file
EricLew 0:80ee8f3b695e 292 */
EricLew 0:80ee8f3b695e 293 }
EricLew 0:80ee8f3b695e 294
EricLew 0:80ee8f3b695e 295 /**
EricLew 0:80ee8f3b695e 296 * @}
EricLew 0:80ee8f3b695e 297 */
EricLew 0:80ee8f3b695e 298
EricLew 0:80ee8f3b695e 299 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
EricLew 0:80ee8f3b695e 300 * @brief Input Output and memory control functions
EricLew 0:80ee8f3b695e 301 *
EricLew 0:80ee8f3b695e 302 @verbatim
EricLew 0:80ee8f3b695e 303 ==============================================================================
EricLew 0:80ee8f3b695e 304 ##### NOR Input and Output functions #####
EricLew 0:80ee8f3b695e 305 ==============================================================================
EricLew 0:80ee8f3b695e 306 [..]
EricLew 0:80ee8f3b695e 307 This section provides functions allowing to use and control the NOR memory
EricLew 0:80ee8f3b695e 308
EricLew 0:80ee8f3b695e 309 @endverbatim
EricLew 0:80ee8f3b695e 310 * @{
EricLew 0:80ee8f3b695e 311 */
EricLew 0:80ee8f3b695e 312
EricLew 0:80ee8f3b695e 313 /**
EricLew 0:80ee8f3b695e 314 * @brief Read NOR flash IDs.
EricLew 0:80ee8f3b695e 315 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 316 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 317 * @param pNOR_ID : pointer to NOR ID structure
EricLew 0:80ee8f3b695e 318 * @retval HAL status
EricLew 0:80ee8f3b695e 319 */
EricLew 0:80ee8f3b695e 320 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
EricLew 0:80ee8f3b695e 321 {
EricLew 0:80ee8f3b695e 322 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 323
EricLew 0:80ee8f3b695e 324 /* Process Locked */
EricLew 0:80ee8f3b695e 325 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 326
EricLew 0:80ee8f3b695e 327 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 328 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 329 {
EricLew 0:80ee8f3b695e 330 return HAL_BUSY;
EricLew 0:80ee8f3b695e 331 }
EricLew 0:80ee8f3b695e 332
EricLew 0:80ee8f3b695e 333 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 334 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 335 {
EricLew 0:80ee8f3b695e 336 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 337 }
EricLew 0:80ee8f3b695e 338 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 339 {
EricLew 0:80ee8f3b695e 340 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 341 }
EricLew 0:80ee8f3b695e 342 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 343 {
EricLew 0:80ee8f3b695e 344 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 345 }
EricLew 0:80ee8f3b695e 346 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 347 {
EricLew 0:80ee8f3b695e 348 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 349 }
EricLew 0:80ee8f3b695e 350
EricLew 0:80ee8f3b695e 351 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 352 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 353
EricLew 0:80ee8f3b695e 354 /* Send read ID command */
EricLew 0:80ee8f3b695e 355 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 356 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 357 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
EricLew 0:80ee8f3b695e 358
EricLew 0:80ee8f3b695e 359 /* Read the NOR IDs */
EricLew 0:80ee8f3b695e 360 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
EricLew 0:80ee8f3b695e 361 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
EricLew 0:80ee8f3b695e 362 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
EricLew 0:80ee8f3b695e 363 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
EricLew 0:80ee8f3b695e 364
EricLew 0:80ee8f3b695e 365 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 366 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 367
EricLew 0:80ee8f3b695e 368 /* Process unlocked */
EricLew 0:80ee8f3b695e 369 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 370
EricLew 0:80ee8f3b695e 371 return HAL_OK;
EricLew 0:80ee8f3b695e 372 }
EricLew 0:80ee8f3b695e 373
EricLew 0:80ee8f3b695e 374 /**
EricLew 0:80ee8f3b695e 375 * @brief Return the NOR memory to Read mode.
EricLew 0:80ee8f3b695e 376 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 377 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 378 * @retval HAL status
EricLew 0:80ee8f3b695e 379 */
EricLew 0:80ee8f3b695e 380 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 381 {
EricLew 0:80ee8f3b695e 382 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 383
EricLew 0:80ee8f3b695e 384 /* Process Locked */
EricLew 0:80ee8f3b695e 385 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 386
EricLew 0:80ee8f3b695e 387 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 388 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 389 {
EricLew 0:80ee8f3b695e 390 return HAL_BUSY;
EricLew 0:80ee8f3b695e 391 }
EricLew 0:80ee8f3b695e 392
EricLew 0:80ee8f3b695e 393 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 394 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 395 {
EricLew 0:80ee8f3b695e 396 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 397 }
EricLew 0:80ee8f3b695e 398 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 399 {
EricLew 0:80ee8f3b695e 400 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 401 }
EricLew 0:80ee8f3b695e 402 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 403 {
EricLew 0:80ee8f3b695e 404 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 405 }
EricLew 0:80ee8f3b695e 406 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 407 {
EricLew 0:80ee8f3b695e 408 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 409 }
EricLew 0:80ee8f3b695e 410
EricLew 0:80ee8f3b695e 411 NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
EricLew 0:80ee8f3b695e 412
EricLew 0:80ee8f3b695e 413 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 414 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 415
EricLew 0:80ee8f3b695e 416 /* Process unlocked */
EricLew 0:80ee8f3b695e 417 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 418
EricLew 0:80ee8f3b695e 419 return HAL_OK;
EricLew 0:80ee8f3b695e 420 }
EricLew 0:80ee8f3b695e 421
EricLew 0:80ee8f3b695e 422 /**
EricLew 0:80ee8f3b695e 423 * @brief Read data from NOR memory.
EricLew 0:80ee8f3b695e 424 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 425 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 426 * @param pAddress: pointer to Device address
EricLew 0:80ee8f3b695e 427 * @param pData : pointer to read data
EricLew 0:80ee8f3b695e 428 * @retval HAL status
EricLew 0:80ee8f3b695e 429 */
EricLew 0:80ee8f3b695e 430 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
EricLew 0:80ee8f3b695e 431 {
EricLew 0:80ee8f3b695e 432 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 433
EricLew 0:80ee8f3b695e 434 /* Process Locked */
EricLew 0:80ee8f3b695e 435 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 436
EricLew 0:80ee8f3b695e 437 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 438 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 439 {
EricLew 0:80ee8f3b695e 440 return HAL_BUSY;
EricLew 0:80ee8f3b695e 441 }
EricLew 0:80ee8f3b695e 442
EricLew 0:80ee8f3b695e 443 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 444 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 445 {
EricLew 0:80ee8f3b695e 446 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 447 }
EricLew 0:80ee8f3b695e 448 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 449 {
EricLew 0:80ee8f3b695e 450 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 451 }
EricLew 0:80ee8f3b695e 452 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 453 {
EricLew 0:80ee8f3b695e 454 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 455 }
EricLew 0:80ee8f3b695e 456 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 457 {
EricLew 0:80ee8f3b695e 458 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 459 }
EricLew 0:80ee8f3b695e 460
EricLew 0:80ee8f3b695e 461 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 462 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 463
EricLew 0:80ee8f3b695e 464 /* Send read data command */
EricLew 0:80ee8f3b695e 465 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 466 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 467 NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
EricLew 0:80ee8f3b695e 468
EricLew 0:80ee8f3b695e 469 /* Read the data */
EricLew 0:80ee8f3b695e 470 *pData = *(__IO uint32_t *)(uint32_t)pAddress;
EricLew 0:80ee8f3b695e 471
EricLew 0:80ee8f3b695e 472 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 473 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 474
EricLew 0:80ee8f3b695e 475 /* Process unlocked */
EricLew 0:80ee8f3b695e 476 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 477
EricLew 0:80ee8f3b695e 478 return HAL_OK;
EricLew 0:80ee8f3b695e 479 }
EricLew 0:80ee8f3b695e 480
EricLew 0:80ee8f3b695e 481 /**
EricLew 0:80ee8f3b695e 482 * @brief Program data to NOR memory.
EricLew 0:80ee8f3b695e 483 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 484 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 485 * @param pAddress: Device address
EricLew 0:80ee8f3b695e 486 * @param pData : pointer to the data to write
EricLew 0:80ee8f3b695e 487 * @retval HAL status
EricLew 0:80ee8f3b695e 488 */
EricLew 0:80ee8f3b695e 489 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
EricLew 0:80ee8f3b695e 490 {
EricLew 0:80ee8f3b695e 491 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 492
EricLew 0:80ee8f3b695e 493 /* Process Locked */
EricLew 0:80ee8f3b695e 494 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 495
EricLew 0:80ee8f3b695e 496 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 497 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 498 {
EricLew 0:80ee8f3b695e 499 return HAL_BUSY;
EricLew 0:80ee8f3b695e 500 }
EricLew 0:80ee8f3b695e 501
EricLew 0:80ee8f3b695e 502 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 503 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 504 {
EricLew 0:80ee8f3b695e 505 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 506 }
EricLew 0:80ee8f3b695e 507 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 508 {
EricLew 0:80ee8f3b695e 509 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 510 }
EricLew 0:80ee8f3b695e 511 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 512 {
EricLew 0:80ee8f3b695e 513 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 514 }
EricLew 0:80ee8f3b695e 515 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 516 {
EricLew 0:80ee8f3b695e 517 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 518 }
EricLew 0:80ee8f3b695e 519
EricLew 0:80ee8f3b695e 520 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 521 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 522
EricLew 0:80ee8f3b695e 523 /* Send program data command */
EricLew 0:80ee8f3b695e 524 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 525 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 526 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
EricLew 0:80ee8f3b695e 527
EricLew 0:80ee8f3b695e 528 /* Write the data */
EricLew 0:80ee8f3b695e 529 NOR_WRITE(pAddress, *pData);
EricLew 0:80ee8f3b695e 530
EricLew 0:80ee8f3b695e 531 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 532 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 533
EricLew 0:80ee8f3b695e 534 /* Process unlocked */
EricLew 0:80ee8f3b695e 535 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 536
EricLew 0:80ee8f3b695e 537 return HAL_OK;
EricLew 0:80ee8f3b695e 538 }
EricLew 0:80ee8f3b695e 539
EricLew 0:80ee8f3b695e 540 /**
EricLew 0:80ee8f3b695e 541 * @brief Read a block of data from the FMC NOR memory.
EricLew 0:80ee8f3b695e 542 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 543 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 544 * @param uwAddress: NOR memory internal address to read from.
EricLew 0:80ee8f3b695e 545 * @param pData: pointer to the buffer that receives the data read from the
EricLew 0:80ee8f3b695e 546 * NOR memory.
EricLew 0:80ee8f3b695e 547 * @param uwBufferSize : number of Half word to read.
EricLew 0:80ee8f3b695e 548 * @retval HAL status
EricLew 0:80ee8f3b695e 549 */
EricLew 0:80ee8f3b695e 550 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
EricLew 0:80ee8f3b695e 551 {
EricLew 0:80ee8f3b695e 552 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 553
EricLew 0:80ee8f3b695e 554 /* Process Locked */
EricLew 0:80ee8f3b695e 555 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 556
EricLew 0:80ee8f3b695e 557 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 558 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 559 {
EricLew 0:80ee8f3b695e 560 return HAL_BUSY;
EricLew 0:80ee8f3b695e 561 }
EricLew 0:80ee8f3b695e 562
EricLew 0:80ee8f3b695e 563 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 564 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 565 {
EricLew 0:80ee8f3b695e 566 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 567 }
EricLew 0:80ee8f3b695e 568 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 569 {
EricLew 0:80ee8f3b695e 570 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 571 }
EricLew 0:80ee8f3b695e 572 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 573 {
EricLew 0:80ee8f3b695e 574 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 575 }
EricLew 0:80ee8f3b695e 576 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 577 {
EricLew 0:80ee8f3b695e 578 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 579 }
EricLew 0:80ee8f3b695e 580
EricLew 0:80ee8f3b695e 581 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 582 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 583
EricLew 0:80ee8f3b695e 584 /* Send read data command */
EricLew 0:80ee8f3b695e 585 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 586 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 587 NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
EricLew 0:80ee8f3b695e 588
EricLew 0:80ee8f3b695e 589 /* Read buffer */
EricLew 0:80ee8f3b695e 590 while( uwBufferSize > 0)
EricLew 0:80ee8f3b695e 591 {
EricLew 0:80ee8f3b695e 592 *pData++ = *(__IO uint16_t *)uwAddress;
EricLew 0:80ee8f3b695e 593 uwAddress += 2;
EricLew 0:80ee8f3b695e 594 uwBufferSize--;
EricLew 0:80ee8f3b695e 595 }
EricLew 0:80ee8f3b695e 596
EricLew 0:80ee8f3b695e 597 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 598 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 599
EricLew 0:80ee8f3b695e 600 /* Process unlocked */
EricLew 0:80ee8f3b695e 601 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 602
EricLew 0:80ee8f3b695e 603 return HAL_OK;
EricLew 0:80ee8f3b695e 604 }
EricLew 0:80ee8f3b695e 605
EricLew 0:80ee8f3b695e 606 /**
EricLew 0:80ee8f3b695e 607 * @brief Write a half-word buffer to the FMC NOR memory. This function
EricLew 0:80ee8f3b695e 608 * must be used only with S29GL128P NOR memory.
EricLew 0:80ee8f3b695e 609 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 610 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 611 * @param uwAddress: NOR memory internal address from which the data
EricLew 0:80ee8f3b695e 612 * @note Some NOR memory need Address aligned to xx bytes (can be aligned to
EricLew 0:80ee8f3b695e 613 * 64 bytes boundary for example).
EricLew 0:80ee8f3b695e 614 * @param pData: pointer to source data buffer.
EricLew 0:80ee8f3b695e 615 * @param uwBufferSize: number of Half words to write.
EricLew 0:80ee8f3b695e 616 * @note The maximum buffer size allowed is NOR memory dependent
EricLew 0:80ee8f3b695e 617 * (can be 64 Bytes max for example).
EricLew 0:80ee8f3b695e 618 * @retval HAL status
EricLew 0:80ee8f3b695e 619 */
EricLew 0:80ee8f3b695e 620 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
EricLew 0:80ee8f3b695e 621 {
EricLew 0:80ee8f3b695e 622 uint16_t * p_currentaddress = (uint16_t *)NULL;
EricLew 0:80ee8f3b695e 623 uint16_t * p_endaddress = (uint16_t *)NULL;
EricLew 0:80ee8f3b695e 624 uint32_t lastloadedaddress = 0, deviceaddress = 0;
EricLew 0:80ee8f3b695e 625
EricLew 0:80ee8f3b695e 626 /* Process Locked */
EricLew 0:80ee8f3b695e 627 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 628
EricLew 0:80ee8f3b695e 629 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 630 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 631 {
EricLew 0:80ee8f3b695e 632 return HAL_BUSY;
EricLew 0:80ee8f3b695e 633 }
EricLew 0:80ee8f3b695e 634
EricLew 0:80ee8f3b695e 635 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 636 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 637 {
EricLew 0:80ee8f3b695e 638 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 639 }
EricLew 0:80ee8f3b695e 640 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 641 {
EricLew 0:80ee8f3b695e 642 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 643 }
EricLew 0:80ee8f3b695e 644 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 645 {
EricLew 0:80ee8f3b695e 646 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 647 }
EricLew 0:80ee8f3b695e 648 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 649 {
EricLew 0:80ee8f3b695e 650 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 651 }
EricLew 0:80ee8f3b695e 652
EricLew 0:80ee8f3b695e 653 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 654 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 655
EricLew 0:80ee8f3b695e 656 /* Initialize variables */
EricLew 0:80ee8f3b695e 657 p_currentaddress = (uint16_t*)((uint32_t)(uwAddress));
EricLew 0:80ee8f3b695e 658 p_endaddress = p_currentaddress + (uwBufferSize-1);
EricLew 0:80ee8f3b695e 659 lastloadedaddress = (uint32_t)(uwAddress);
EricLew 0:80ee8f3b695e 660
EricLew 0:80ee8f3b695e 661 /* Issue unlock command sequence */
EricLew 0:80ee8f3b695e 662 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 663 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 664
EricLew 0:80ee8f3b695e 665 /* Write Buffer Load Command */
EricLew 0:80ee8f3b695e 666 NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
EricLew 0:80ee8f3b695e 667 NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
EricLew 0:80ee8f3b695e 668
EricLew 0:80ee8f3b695e 669 /* Load Data into NOR Buffer */
EricLew 0:80ee8f3b695e 670 while(p_currentaddress <= p_endaddress)
EricLew 0:80ee8f3b695e 671 {
EricLew 0:80ee8f3b695e 672 /* Store last loaded address & data value (for polling) */
EricLew 0:80ee8f3b695e 673 lastloadedaddress = (uint32_t)p_currentaddress;
EricLew 0:80ee8f3b695e 674
EricLew 0:80ee8f3b695e 675 NOR_WRITE(p_currentaddress, *pData++);
EricLew 0:80ee8f3b695e 676
EricLew 0:80ee8f3b695e 677 p_currentaddress++;
EricLew 0:80ee8f3b695e 678 }
EricLew 0:80ee8f3b695e 679
EricLew 0:80ee8f3b695e 680 NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
EricLew 0:80ee8f3b695e 681
EricLew 0:80ee8f3b695e 682 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 683 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 684
EricLew 0:80ee8f3b695e 685 /* Process unlocked */
EricLew 0:80ee8f3b695e 686 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 687
EricLew 0:80ee8f3b695e 688 return HAL_OK;
EricLew 0:80ee8f3b695e 689
EricLew 0:80ee8f3b695e 690 }
EricLew 0:80ee8f3b695e 691
EricLew 0:80ee8f3b695e 692 /**
EricLew 0:80ee8f3b695e 693 * @brief Erase the specified block of the NOR memory.
EricLew 0:80ee8f3b695e 694 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 695 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 696 * @param BlockAddress : Block to erase address
EricLew 0:80ee8f3b695e 697 * @param Address: Device address
EricLew 0:80ee8f3b695e 698 * @retval HAL status
EricLew 0:80ee8f3b695e 699 */
EricLew 0:80ee8f3b695e 700 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
EricLew 0:80ee8f3b695e 701 {
EricLew 0:80ee8f3b695e 702 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 703
EricLew 0:80ee8f3b695e 704 /* Process Locked */
EricLew 0:80ee8f3b695e 705 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 706
EricLew 0:80ee8f3b695e 707 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 708 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 709 {
EricLew 0:80ee8f3b695e 710 return HAL_BUSY;
EricLew 0:80ee8f3b695e 711 }
EricLew 0:80ee8f3b695e 712
EricLew 0:80ee8f3b695e 713 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 714 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 715 {
EricLew 0:80ee8f3b695e 716 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 717 }
EricLew 0:80ee8f3b695e 718 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 719 {
EricLew 0:80ee8f3b695e 720 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 721 }
EricLew 0:80ee8f3b695e 722 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 723 {
EricLew 0:80ee8f3b695e 724 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 725 }
EricLew 0:80ee8f3b695e 726 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 727 {
EricLew 0:80ee8f3b695e 728 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 729 }
EricLew 0:80ee8f3b695e 730
EricLew 0:80ee8f3b695e 731 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 732 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 733
EricLew 0:80ee8f3b695e 734 /* Send block erase command sequence */
EricLew 0:80ee8f3b695e 735 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 736 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 737 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
EricLew 0:80ee8f3b695e 738 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
EricLew 0:80ee8f3b695e 739 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
EricLew 0:80ee8f3b695e 740 NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
EricLew 0:80ee8f3b695e 741
EricLew 0:80ee8f3b695e 742 /* Check the NOR memory status and update the controller state */
EricLew 0:80ee8f3b695e 743 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 744
EricLew 0:80ee8f3b695e 745 /* Process unlocked */
EricLew 0:80ee8f3b695e 746 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 747
EricLew 0:80ee8f3b695e 748 return HAL_OK;
EricLew 0:80ee8f3b695e 749
EricLew 0:80ee8f3b695e 750 }
EricLew 0:80ee8f3b695e 751
EricLew 0:80ee8f3b695e 752 /**
EricLew 0:80ee8f3b695e 753 * @brief Erase the entire NOR chip.
EricLew 0:80ee8f3b695e 754 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 755 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 756 * @param Address : Device address
EricLew 0:80ee8f3b695e 757 * @retval HAL status
EricLew 0:80ee8f3b695e 758 */
EricLew 0:80ee8f3b695e 759 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
EricLew 0:80ee8f3b695e 760 {
EricLew 0:80ee8f3b695e 761 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 762
EricLew 0:80ee8f3b695e 763 /* Process Locked */
EricLew 0:80ee8f3b695e 764 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 765
EricLew 0:80ee8f3b695e 766 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 767 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 768 {
EricLew 0:80ee8f3b695e 769 return HAL_BUSY;
EricLew 0:80ee8f3b695e 770 }
EricLew 0:80ee8f3b695e 771
EricLew 0:80ee8f3b695e 772 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 773 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 774 {
EricLew 0:80ee8f3b695e 775 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 776 }
EricLew 0:80ee8f3b695e 777 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 778 {
EricLew 0:80ee8f3b695e 779 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 780 }
EricLew 0:80ee8f3b695e 781 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 782 {
EricLew 0:80ee8f3b695e 783 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 784 }
EricLew 0:80ee8f3b695e 785 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 786 {
EricLew 0:80ee8f3b695e 787 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 788 }
EricLew 0:80ee8f3b695e 789
EricLew 0:80ee8f3b695e 790 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 791 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 792
EricLew 0:80ee8f3b695e 793 /* Send NOR chip erase command sequence */
EricLew 0:80ee8f3b695e 794 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
EricLew 0:80ee8f3b695e 795 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
EricLew 0:80ee8f3b695e 796 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
EricLew 0:80ee8f3b695e 797 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
EricLew 0:80ee8f3b695e 798 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
EricLew 0:80ee8f3b695e 799 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
EricLew 0:80ee8f3b695e 800
EricLew 0:80ee8f3b695e 801 /* Check the NOR memory status and update the controller state */
EricLew 0:80ee8f3b695e 802 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 803
EricLew 0:80ee8f3b695e 804 /* Process unlocked */
EricLew 0:80ee8f3b695e 805 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 806
EricLew 0:80ee8f3b695e 807 return HAL_OK;
EricLew 0:80ee8f3b695e 808 }
EricLew 0:80ee8f3b695e 809
EricLew 0:80ee8f3b695e 810 /**
EricLew 0:80ee8f3b695e 811 * @brief Read NOR flash CFI IDs.
EricLew 0:80ee8f3b695e 812 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 813 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 814 * @param pNOR_CFI : pointer to NOR CFI IDs structure
EricLew 0:80ee8f3b695e 815 * @retval HAL status
EricLew 0:80ee8f3b695e 816 */
EricLew 0:80ee8f3b695e 817 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
EricLew 0:80ee8f3b695e 818 {
EricLew 0:80ee8f3b695e 819 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 820
EricLew 0:80ee8f3b695e 821 /* Process Locked */
EricLew 0:80ee8f3b695e 822 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 823
EricLew 0:80ee8f3b695e 824 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 825 if(hnor->State == HAL_NOR_STATE_BUSY)
EricLew 0:80ee8f3b695e 826 {
EricLew 0:80ee8f3b695e 827 return HAL_BUSY;
EricLew 0:80ee8f3b695e 828 }
EricLew 0:80ee8f3b695e 829
EricLew 0:80ee8f3b695e 830 /* Select the NOR device address */
EricLew 0:80ee8f3b695e 831 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
EricLew 0:80ee8f3b695e 832 {
EricLew 0:80ee8f3b695e 833 deviceaddress = NOR_MEMORY_ADRESS1;
EricLew 0:80ee8f3b695e 834 }
EricLew 0:80ee8f3b695e 835 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
EricLew 0:80ee8f3b695e 836 {
EricLew 0:80ee8f3b695e 837 deviceaddress = NOR_MEMORY_ADRESS2;
EricLew 0:80ee8f3b695e 838 }
EricLew 0:80ee8f3b695e 839 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
EricLew 0:80ee8f3b695e 840 {
EricLew 0:80ee8f3b695e 841 deviceaddress = NOR_MEMORY_ADRESS3;
EricLew 0:80ee8f3b695e 842 }
EricLew 0:80ee8f3b695e 843 else /* FMC_NORSRAM_BANK4 */
EricLew 0:80ee8f3b695e 844 {
EricLew 0:80ee8f3b695e 845 deviceaddress = NOR_MEMORY_ADRESS4;
EricLew 0:80ee8f3b695e 846 }
EricLew 0:80ee8f3b695e 847
EricLew 0:80ee8f3b695e 848 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 849 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 850
EricLew 0:80ee8f3b695e 851 /* Send read CFI query command */
EricLew 0:80ee8f3b695e 852 NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
EricLew 0:80ee8f3b695e 853
EricLew 0:80ee8f3b695e 854 /* read the NOR CFI information */
EricLew 0:80ee8f3b695e 855 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
EricLew 0:80ee8f3b695e 856 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
EricLew 0:80ee8f3b695e 857 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
EricLew 0:80ee8f3b695e 858 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
EricLew 0:80ee8f3b695e 859
EricLew 0:80ee8f3b695e 860 /* Check the NOR controller state */
EricLew 0:80ee8f3b695e 861 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 862
EricLew 0:80ee8f3b695e 863 /* Process unlocked */
EricLew 0:80ee8f3b695e 864 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 865
EricLew 0:80ee8f3b695e 866 return HAL_OK;
EricLew 0:80ee8f3b695e 867 }
EricLew 0:80ee8f3b695e 868
EricLew 0:80ee8f3b695e 869 /**
EricLew 0:80ee8f3b695e 870 * @}
EricLew 0:80ee8f3b695e 871 */
EricLew 0:80ee8f3b695e 872
EricLew 0:80ee8f3b695e 873 /** @defgroup NOR_Exported_Functions_Group3 Peripheral Control functions
EricLew 0:80ee8f3b695e 874 * @brief management functions
EricLew 0:80ee8f3b695e 875 *
EricLew 0:80ee8f3b695e 876 @verbatim
EricLew 0:80ee8f3b695e 877 ==============================================================================
EricLew 0:80ee8f3b695e 878 ##### NOR Control functions #####
EricLew 0:80ee8f3b695e 879 ==============================================================================
EricLew 0:80ee8f3b695e 880 [..]
EricLew 0:80ee8f3b695e 881 This subsection provides a set of functions allowing to control dynamically
EricLew 0:80ee8f3b695e 882 the NOR interface.
EricLew 0:80ee8f3b695e 883
EricLew 0:80ee8f3b695e 884 @endverbatim
EricLew 0:80ee8f3b695e 885 * @{
EricLew 0:80ee8f3b695e 886 */
EricLew 0:80ee8f3b695e 887
EricLew 0:80ee8f3b695e 888 /**
EricLew 0:80ee8f3b695e 889 * @brief Enable dynamically NOR write operation.
EricLew 0:80ee8f3b695e 890 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 891 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 892 * @retval HAL status
EricLew 0:80ee8f3b695e 893 */
EricLew 0:80ee8f3b695e 894 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 895 {
EricLew 0:80ee8f3b695e 896 /* Process Locked */
EricLew 0:80ee8f3b695e 897 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 898
EricLew 0:80ee8f3b695e 899 /* Enable write operation */
EricLew 0:80ee8f3b695e 900 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
EricLew 0:80ee8f3b695e 901
EricLew 0:80ee8f3b695e 902 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 903 hnor->State = HAL_NOR_STATE_READY;
EricLew 0:80ee8f3b695e 904
EricLew 0:80ee8f3b695e 905 /* Process unlocked */
EricLew 0:80ee8f3b695e 906 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 907
EricLew 0:80ee8f3b695e 908 return HAL_OK;
EricLew 0:80ee8f3b695e 909 }
EricLew 0:80ee8f3b695e 910
EricLew 0:80ee8f3b695e 911 /**
EricLew 0:80ee8f3b695e 912 * @brief Disable dynamically NOR write operation.
EricLew 0:80ee8f3b695e 913 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 914 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 915 * @retval HAL status
EricLew 0:80ee8f3b695e 916 */
EricLew 0:80ee8f3b695e 917 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 918 {
EricLew 0:80ee8f3b695e 919 /* Process Locked */
EricLew 0:80ee8f3b695e 920 __HAL_LOCK(hnor);
EricLew 0:80ee8f3b695e 921
EricLew 0:80ee8f3b695e 922 /* Update the SRAM controller state */
EricLew 0:80ee8f3b695e 923 hnor->State = HAL_NOR_STATE_BUSY;
EricLew 0:80ee8f3b695e 924
EricLew 0:80ee8f3b695e 925 /* Disable write operation */
EricLew 0:80ee8f3b695e 926 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
EricLew 0:80ee8f3b695e 927
EricLew 0:80ee8f3b695e 928 /* Update the NOR controller state */
EricLew 0:80ee8f3b695e 929 hnor->State = HAL_NOR_STATE_PROTECTED;
EricLew 0:80ee8f3b695e 930
EricLew 0:80ee8f3b695e 931 /* Process unlocked */
EricLew 0:80ee8f3b695e 932 __HAL_UNLOCK(hnor);
EricLew 0:80ee8f3b695e 933
EricLew 0:80ee8f3b695e 934 return HAL_OK;
EricLew 0:80ee8f3b695e 935 }
EricLew 0:80ee8f3b695e 936
EricLew 0:80ee8f3b695e 937 /**
EricLew 0:80ee8f3b695e 938 * @}
EricLew 0:80ee8f3b695e 939 */
EricLew 0:80ee8f3b695e 940
EricLew 0:80ee8f3b695e 941 /** @defgroup NOR_Exported_Functions_Group4 Peripheral State functions
EricLew 0:80ee8f3b695e 942 * @brief Peripheral State functions
EricLew 0:80ee8f3b695e 943 *
EricLew 0:80ee8f3b695e 944 @verbatim
EricLew 0:80ee8f3b695e 945 ==============================================================================
EricLew 0:80ee8f3b695e 946 ##### NOR State functions #####
EricLew 0:80ee8f3b695e 947 ==============================================================================
EricLew 0:80ee8f3b695e 948 [..]
EricLew 0:80ee8f3b695e 949 This subsection permits to get in run-time the status of the NOR controller
EricLew 0:80ee8f3b695e 950 and the data flow.
EricLew 0:80ee8f3b695e 951
EricLew 0:80ee8f3b695e 952 @endverbatim
EricLew 0:80ee8f3b695e 953 * @{
EricLew 0:80ee8f3b695e 954 */
EricLew 0:80ee8f3b695e 955
EricLew 0:80ee8f3b695e 956 /**
EricLew 0:80ee8f3b695e 957 * @brief Return the NOR controller handle state.
EricLew 0:80ee8f3b695e 958 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 959 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 960 * @retval NOR controller state
EricLew 0:80ee8f3b695e 961 */
EricLew 0:80ee8f3b695e 962 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
EricLew 0:80ee8f3b695e 963 {
EricLew 0:80ee8f3b695e 964 /* Return NOR handle state */
EricLew 0:80ee8f3b695e 965 return hnor->State;
EricLew 0:80ee8f3b695e 966 }
EricLew 0:80ee8f3b695e 967
EricLew 0:80ee8f3b695e 968 /**
EricLew 0:80ee8f3b695e 969 * @brief Return the NOR operation status.
EricLew 0:80ee8f3b695e 970 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 971 * the configuration information for NOR module.
EricLew 0:80ee8f3b695e 972 * @param Address: Device address
EricLew 0:80ee8f3b695e 973 * @param Timeout: NOR programming Timeout
EricLew 0:80ee8f3b695e 974 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
EricLew 0:80ee8f3b695e 975 * or HAL_NOR_STATUS_TIMEOUT
EricLew 0:80ee8f3b695e 976 */
EricLew 0:80ee8f3b695e 977 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
EricLew 0:80ee8f3b695e 978 {
EricLew 0:80ee8f3b695e 979 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
EricLew 0:80ee8f3b695e 980 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
EricLew 0:80ee8f3b695e 981 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 982
EricLew 0:80ee8f3b695e 983 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
EricLew 0:80ee8f3b695e 984 HAL_NOR_MspWait(hnor, Timeout);
EricLew 0:80ee8f3b695e 985
EricLew 0:80ee8f3b695e 986 /* Get tick */
EricLew 0:80ee8f3b695e 987 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 988 while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
EricLew 0:80ee8f3b695e 989 {
EricLew 0:80ee8f3b695e 990 /* Check for the Timeout */
EricLew 0:80ee8f3b695e 991 if(Timeout != HAL_MAX_DELAY)
EricLew 0:80ee8f3b695e 992 {
EricLew 0:80ee8f3b695e 993 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
EricLew 0:80ee8f3b695e 994 {
EricLew 0:80ee8f3b695e 995 status = HAL_NOR_STATUS_TIMEOUT;
EricLew 0:80ee8f3b695e 996 }
EricLew 0:80ee8f3b695e 997 }
EricLew 0:80ee8f3b695e 998
EricLew 0:80ee8f3b695e 999 /* Read NOR status register (DQ6 and DQ5) */
EricLew 0:80ee8f3b695e 1000 tmp_sr1 = *(__IO uint16_t *)Address;
EricLew 0:80ee8f3b695e 1001 tmp_sr2 = *(__IO uint16_t *)Address;
EricLew 0:80ee8f3b695e 1002
EricLew 0:80ee8f3b695e 1003 /* If DQ6 did not toggle between the two reads then return NOR_Success */
EricLew 0:80ee8f3b695e 1004 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
EricLew 0:80ee8f3b695e 1005 {
EricLew 0:80ee8f3b695e 1006 return HAL_NOR_STATUS_SUCCESS;
EricLew 0:80ee8f3b695e 1007 }
EricLew 0:80ee8f3b695e 1008
EricLew 0:80ee8f3b695e 1009 if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
EricLew 0:80ee8f3b695e 1010 {
EricLew 0:80ee8f3b695e 1011 status = HAL_NOR_STATUS_ONGOING;
EricLew 0:80ee8f3b695e 1012 }
EricLew 0:80ee8f3b695e 1013
EricLew 0:80ee8f3b695e 1014 tmp_sr1 = *(__IO uint16_t *)Address;
EricLew 0:80ee8f3b695e 1015 tmp_sr2 = *(__IO uint16_t *)Address;
EricLew 0:80ee8f3b695e 1016
EricLew 0:80ee8f3b695e 1017 /* If DQ6 did not toggle between the two reads then return NOR_Success */
EricLew 0:80ee8f3b695e 1018 if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
EricLew 0:80ee8f3b695e 1019 {
EricLew 0:80ee8f3b695e 1020 return HAL_NOR_STATUS_SUCCESS;
EricLew 0:80ee8f3b695e 1021 }
EricLew 0:80ee8f3b695e 1022 else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
EricLew 0:80ee8f3b695e 1023 {
EricLew 0:80ee8f3b695e 1024 return HAL_NOR_STATUS_ERROR;
EricLew 0:80ee8f3b695e 1025 }
EricLew 0:80ee8f3b695e 1026 }
EricLew 0:80ee8f3b695e 1027
EricLew 0:80ee8f3b695e 1028 /* Return the operation status */
EricLew 0:80ee8f3b695e 1029 return status;
EricLew 0:80ee8f3b695e 1030 }
EricLew 0:80ee8f3b695e 1031
EricLew 0:80ee8f3b695e 1032 /**
EricLew 0:80ee8f3b695e 1033 * @}
EricLew 0:80ee8f3b695e 1034 */
EricLew 0:80ee8f3b695e 1035
EricLew 0:80ee8f3b695e 1036 /**
EricLew 0:80ee8f3b695e 1037 * @}
EricLew 0:80ee8f3b695e 1038 */
EricLew 0:80ee8f3b695e 1039 /**
EricLew 0:80ee8f3b695e 1040 * @}
EricLew 0:80ee8f3b695e 1041 */
EricLew 0:80ee8f3b695e 1042 #endif /* HAL_NOR_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 1043
EricLew 0:80ee8f3b695e 1044 /**
EricLew 0:80ee8f3b695e 1045 * @}
EricLew 0:80ee8f3b695e 1046 */
EricLew 0:80ee8f3b695e 1047
EricLew 0:80ee8f3b695e 1048 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 1049