STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_hal_rcc_ex.h@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:: EricLew
Date:: Mon Nov 02 19:37:23 2015 +0000
Revision:: 0:80ee8f3b695e

Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_hal_rcc_ex.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of RCC HAL Extended module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_HAL_RCC_EX_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_HAL_RCC_EX_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx_hal_def.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_HAL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	/** @addtogroup RCCEx
EricLew	0:80ee8f3b695e	54	* @{
EricLew	0:80ee8f3b695e	55	*/
EricLew	0:80ee8f3b695e	56
EricLew	0:80ee8f3b695e	57	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
EricLew	0:80ee8f3b695e	60	* @{
EricLew	0:80ee8f3b695e	61	*/
EricLew	0:80ee8f3b695e	62
EricLew	0:80ee8f3b695e	63	/**
EricLew	0:80ee8f3b695e	64	* @brief PLLSAI1 Clock structure definition
EricLew	0:80ee8f3b695e	65	*/
EricLew	0:80ee8f3b695e	66	typedef struct
EricLew	0:80ee8f3b695e	67	{
EricLew	0:80ee8f3b695e	68
EricLew	0:80ee8f3b695e	69	uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock.
EricLew	0:80ee8f3b695e	70	This parameter must be a number between 8 and 86. */
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	73	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
EricLew	0:80ee8f3b695e	74
EricLew	0:80ee8f3b695e	75	uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock.
EricLew	0:80ee8f3b695e	76	This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
EricLew	0:80ee8f3b695e	77
EricLew	0:80ee8f3b695e	78	uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock.
EricLew	0:80ee8f3b695e	79	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
EricLew	0:80ee8f3b695e	80
EricLew	0:80ee8f3b695e	81	uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled.
EricLew	0:80ee8f3b695e	82	This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
EricLew	0:80ee8f3b695e	83	}RCC_PLLSAI1InitTypeDef;
EricLew	0:80ee8f3b695e	84
EricLew	0:80ee8f3b695e	85	/**
EricLew	0:80ee8f3b695e	86	* @brief PLLSAI2 Clock structure definition
EricLew	0:80ee8f3b695e	87	*/
EricLew	0:80ee8f3b695e	88	typedef struct
EricLew	0:80ee8f3b695e	89	{
EricLew	0:80ee8f3b695e	90
EricLew	0:80ee8f3b695e	91	uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock.
EricLew	0:80ee8f3b695e	92	This parameter must be a number between 8 and 86. */
EricLew	0:80ee8f3b695e	93
EricLew	0:80ee8f3b695e	94	uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	95	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
EricLew	0:80ee8f3b695e	96
EricLew	0:80ee8f3b695e	97	uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock.
EricLew	0:80ee8f3b695e	98	This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
EricLew	0:80ee8f3b695e	99
EricLew	0:80ee8f3b695e	100	uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled.
EricLew	0:80ee8f3b695e	101	This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */
EricLew	0:80ee8f3b695e	102	}RCC_PLLSAI2InitTypeDef;
EricLew	0:80ee8f3b695e	103
EricLew	0:80ee8f3b695e	104	/**
EricLew	0:80ee8f3b695e	105	* @brief RCC extended clocks structure definition
EricLew	0:80ee8f3b695e	106	*/
EricLew	0:80ee8f3b695e	107	typedef struct
EricLew	0:80ee8f3b695e	108	{
EricLew	0:80ee8f3b695e	109	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
EricLew	0:80ee8f3b695e	110	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
EricLew	0:80ee8f3b695e	111
EricLew	0:80ee8f3b695e	112	RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
EricLew	0:80ee8f3b695e	113	This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */
EricLew	0:80ee8f3b695e	114
EricLew	0:80ee8f3b695e	115	RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters.
EricLew	0:80ee8f3b695e	116	This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */
EricLew	0:80ee8f3b695e	117
EricLew	0:80ee8f3b695e	118	uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
EricLew	0:80ee8f3b695e	119	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
EricLew	0:80ee8f3b695e	120
EricLew	0:80ee8f3b695e	121	uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
EricLew	0:80ee8f3b695e	122	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
EricLew	0:80ee8f3b695e	123
EricLew	0:80ee8f3b695e	124	uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
EricLew	0:80ee8f3b695e	125	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
EricLew	0:80ee8f3b695e	126
EricLew	0:80ee8f3b695e	127	uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
EricLew	0:80ee8f3b695e	128	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
EricLew	0:80ee8f3b695e	129
EricLew	0:80ee8f3b695e	130	uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
EricLew	0:80ee8f3b695e	131	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
EricLew	0:80ee8f3b695e	132
EricLew	0:80ee8f3b695e	133	uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
EricLew	0:80ee8f3b695e	134	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
EricLew	0:80ee8f3b695e	135
EricLew	0:80ee8f3b695e	136	uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
EricLew	0:80ee8f3b695e	137	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
EricLew	0:80ee8f3b695e	138
EricLew	0:80ee8f3b695e	139	uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
EricLew	0:80ee8f3b695e	140	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
EricLew	0:80ee8f3b695e	141
EricLew	0:80ee8f3b695e	142	uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
EricLew	0:80ee8f3b695e	143	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
EricLew	0:80ee8f3b695e	144
EricLew	0:80ee8f3b695e	145	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
EricLew	0:80ee8f3b695e	146	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
EricLew	0:80ee8f3b695e	147
EricLew	0:80ee8f3b695e	148	uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
EricLew	0:80ee8f3b695e	149	This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
EricLew	0:80ee8f3b695e	150
EricLew	0:80ee8f3b695e	151	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
EricLew	0:80ee8f3b695e	152	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
EricLew	0:80ee8f3b695e	153
EricLew	0:80ee8f3b695e	154	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source.
EricLew	0:80ee8f3b695e	155	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
EricLew	0:80ee8f3b695e	156
EricLew	0:80ee8f3b695e	157	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	158
EricLew	0:80ee8f3b695e	159	uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG).
EricLew	0:80ee8f3b695e	160	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
EricLew	0:80ee8f3b695e	161
EricLew	0:80ee8f3b695e	162	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	163
EricLew	0:80ee8f3b695e	164	uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG).
EricLew	0:80ee8f3b695e	165	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
EricLew	0:80ee8f3b695e	166
EricLew	0:80ee8f3b695e	167	uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1).
EricLew	0:80ee8f3b695e	168	This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
EricLew	0:80ee8f3b695e	169
EricLew	0:80ee8f3b695e	170	uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source.
EricLew	0:80ee8f3b695e	171	This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
EricLew	0:80ee8f3b695e	172
EricLew	0:80ee8f3b695e	173	uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source.
EricLew	0:80ee8f3b695e	174	This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
EricLew	0:80ee8f3b695e	175
EricLew	0:80ee8f3b695e	176	uint32_t DfsdmClockSelection; /*!< Specifies DFSDM clock source.
EricLew	0:80ee8f3b695e	177	This parameter can be a value of @ref RCCEx_DFSDM_Clock_Source */
EricLew	0:80ee8f3b695e	178
EricLew	0:80ee8f3b695e	179	uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
EricLew	0:80ee8f3b695e	180	This parameter can be a value of @ref RCC_RTC_Clock_Source */
EricLew	0:80ee8f3b695e	181	}RCC_PeriphCLKInitTypeDef;
EricLew	0:80ee8f3b695e	182
EricLew	0:80ee8f3b695e	183	/**
EricLew	0:80ee8f3b695e	184	* @}
EricLew	0:80ee8f3b695e	185	*/
EricLew	0:80ee8f3b695e	186
EricLew	0:80ee8f3b695e	187	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	188	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
EricLew	0:80ee8f3b695e	189	* @{
EricLew	0:80ee8f3b695e	190	*/
EricLew	0:80ee8f3b695e	191
EricLew	0:80ee8f3b695e	192	/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
EricLew	0:80ee8f3b695e	193	* @{
EricLew	0:80ee8f3b695e	194	*/
EricLew	0:80ee8f3b695e	195	#define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000 /!< LSI selection for low speed clock output /
EricLew	0:80ee8f3b695e	196	#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock output /
EricLew	0:80ee8f3b695e	197	/**
EricLew	0:80ee8f3b695e	198	* @}
EricLew	0:80ee8f3b695e	199	*/
EricLew	0:80ee8f3b695e	200
EricLew	0:80ee8f3b695e	201	/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
EricLew	0:80ee8f3b695e	202	* @{
EricLew	0:80ee8f3b695e	203	*/
EricLew	0:80ee8f3b695e	204	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
EricLew	0:80ee8f3b695e	205	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
EricLew	0:80ee8f3b695e	206	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
EricLew	0:80ee8f3b695e	207	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
EricLew	0:80ee8f3b695e	208	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
EricLew	0:80ee8f3b695e	209	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020)
EricLew	0:80ee8f3b695e	210	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040)
EricLew	0:80ee8f3b695e	211	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080)
EricLew	0:80ee8f3b695e	212	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
EricLew	0:80ee8f3b695e	213	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200)
EricLew	0:80ee8f3b695e	214	#define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400)
EricLew	0:80ee8f3b695e	215	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800)
EricLew	0:80ee8f3b695e	216	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000)
EricLew	0:80ee8f3b695e	217	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	218	#define RCC_PERIPHCLK_USB ((uint32_t)0x00002000)
EricLew	0:80ee8f3b695e	219	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	220	#define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000)
EricLew	0:80ee8f3b695e	221	#define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000)
EricLew	0:80ee8f3b695e	222	#define RCC_PERIPHCLK_DFSDM ((uint32_t)0x00010000)
EricLew	0:80ee8f3b695e	223	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000)
EricLew	0:80ee8f3b695e	224	#define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000)
EricLew	0:80ee8f3b695e	225	#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000)
EricLew	0:80ee8f3b695e	226	/**
EricLew	0:80ee8f3b695e	227	* @}
EricLew	0:80ee8f3b695e	228	*/
EricLew	0:80ee8f3b695e	229
EricLew	0:80ee8f3b695e	230
EricLew	0:80ee8f3b695e	231	/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
EricLew	0:80ee8f3b695e	232	* @{
EricLew	0:80ee8f3b695e	233	*/
EricLew	0:80ee8f3b695e	234	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	235	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
EricLew	0:80ee8f3b695e	236	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
EricLew	0:80ee8f3b695e	237	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
EricLew	0:80ee8f3b695e	238	/**
EricLew	0:80ee8f3b695e	239	* @}
EricLew	0:80ee8f3b695e	240	*/
EricLew	0:80ee8f3b695e	241
EricLew	0:80ee8f3b695e	242	/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
EricLew	0:80ee8f3b695e	243	* @{
EricLew	0:80ee8f3b695e	244	*/
EricLew	0:80ee8f3b695e	245	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	246	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
EricLew	0:80ee8f3b695e	247	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
EricLew	0:80ee8f3b695e	248	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
EricLew	0:80ee8f3b695e	249	/**
EricLew	0:80ee8f3b695e	250	* @}
EricLew	0:80ee8f3b695e	251	*/
EricLew	0:80ee8f3b695e	252
EricLew	0:80ee8f3b695e	253	/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
EricLew	0:80ee8f3b695e	254	* @{
EricLew	0:80ee8f3b695e	255	*/
EricLew	0:80ee8f3b695e	256	#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	257	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
EricLew	0:80ee8f3b695e	258	#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
EricLew	0:80ee8f3b695e	259	#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 \| RCC_CCIPR_USART3SEL_1)
EricLew	0:80ee8f3b695e	260	/**
EricLew	0:80ee8f3b695e	261	* @}
EricLew	0:80ee8f3b695e	262	*/
EricLew	0:80ee8f3b695e	263
EricLew	0:80ee8f3b695e	264	/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
EricLew	0:80ee8f3b695e	265	* @{
EricLew	0:80ee8f3b695e	266	*/
EricLew	0:80ee8f3b695e	267	#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	268	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
EricLew	0:80ee8f3b695e	269	#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
EricLew	0:80ee8f3b695e	270	#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 \| RCC_CCIPR_UART4SEL_1)
EricLew	0:80ee8f3b695e	271	/**
EricLew	0:80ee8f3b695e	272	* @}
EricLew	0:80ee8f3b695e	273	*/
EricLew	0:80ee8f3b695e	274
EricLew	0:80ee8f3b695e	275	/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
EricLew	0:80ee8f3b695e	276	* @{
EricLew	0:80ee8f3b695e	277	*/
EricLew	0:80ee8f3b695e	278	#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	279	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
EricLew	0:80ee8f3b695e	280	#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
EricLew	0:80ee8f3b695e	281	#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 \| RCC_CCIPR_UART5SEL_1)
EricLew	0:80ee8f3b695e	282	/**
EricLew	0:80ee8f3b695e	283	* @}
EricLew	0:80ee8f3b695e	284	*/
EricLew	0:80ee8f3b695e	285
EricLew	0:80ee8f3b695e	286	/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
EricLew	0:80ee8f3b695e	287	* @{
EricLew	0:80ee8f3b695e	288	*/
EricLew	0:80ee8f3b695e	289	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	290	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
EricLew	0:80ee8f3b695e	291	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
EricLew	0:80ee8f3b695e	292	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
EricLew	0:80ee8f3b695e	293	/**
EricLew	0:80ee8f3b695e	294	* @}
EricLew	0:80ee8f3b695e	295	*/
EricLew	0:80ee8f3b695e	296
EricLew	0:80ee8f3b695e	297	/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
EricLew	0:80ee8f3b695e	298	* @{
EricLew	0:80ee8f3b695e	299	*/
EricLew	0:80ee8f3b695e	300	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	301	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
EricLew	0:80ee8f3b695e	302	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
EricLew	0:80ee8f3b695e	303	/**
EricLew	0:80ee8f3b695e	304	* @}
EricLew	0:80ee8f3b695e	305	*/
EricLew	0:80ee8f3b695e	306
EricLew	0:80ee8f3b695e	307	/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
EricLew	0:80ee8f3b695e	308	* @{
EricLew	0:80ee8f3b695e	309	*/
EricLew	0:80ee8f3b695e	310	#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	311	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
EricLew	0:80ee8f3b695e	312	#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
EricLew	0:80ee8f3b695e	313	/**
EricLew	0:80ee8f3b695e	314	* @}
EricLew	0:80ee8f3b695e	315	*/
EricLew	0:80ee8f3b695e	316
EricLew	0:80ee8f3b695e	317	/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
EricLew	0:80ee8f3b695e	318	* @{
EricLew	0:80ee8f3b695e	319	*/
EricLew	0:80ee8f3b695e	320	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	321	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
EricLew	0:80ee8f3b695e	322	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
EricLew	0:80ee8f3b695e	323	/**
EricLew	0:80ee8f3b695e	324	* @}
EricLew	0:80ee8f3b695e	325	*/
EricLew	0:80ee8f3b695e	326
EricLew	0:80ee8f3b695e	327	/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
EricLew	0:80ee8f3b695e	328	* @{
EricLew	0:80ee8f3b695e	329	*/
EricLew	0:80ee8f3b695e	330	#define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	331	#define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0
EricLew	0:80ee8f3b695e	332	#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1
EricLew	0:80ee8f3b695e	333	#define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL
EricLew	0:80ee8f3b695e	334	/**
EricLew	0:80ee8f3b695e	335	* @}
EricLew	0:80ee8f3b695e	336	*/
EricLew	0:80ee8f3b695e	337
EricLew	0:80ee8f3b695e	338	/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
EricLew	0:80ee8f3b695e	339	* @{
EricLew	0:80ee8f3b695e	340	*/
EricLew	0:80ee8f3b695e	341	#define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	342	#define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0
EricLew	0:80ee8f3b695e	343	#define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1
EricLew	0:80ee8f3b695e	344	#define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL
EricLew	0:80ee8f3b695e	345	/**
EricLew	0:80ee8f3b695e	346	* @}
EricLew	0:80ee8f3b695e	347	*/
EricLew	0:80ee8f3b695e	348
EricLew	0:80ee8f3b695e	349	/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
EricLew	0:80ee8f3b695e	350	* @{
EricLew	0:80ee8f3b695e	351	*/
EricLew	0:80ee8f3b695e	352	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	353	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
EricLew	0:80ee8f3b695e	354	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
EricLew	0:80ee8f3b695e	355	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
EricLew	0:80ee8f3b695e	356	/**
EricLew	0:80ee8f3b695e	357	* @}
EricLew	0:80ee8f3b695e	358	*/
EricLew	0:80ee8f3b695e	359
EricLew	0:80ee8f3b695e	360	/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
EricLew	0:80ee8f3b695e	361	* @{
EricLew	0:80ee8f3b695e	362	*/
EricLew	0:80ee8f3b695e	363	#define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	364	#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0
EricLew	0:80ee8f3b695e	365	#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1
EricLew	0:80ee8f3b695e	366	#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL
EricLew	0:80ee8f3b695e	367	/**
EricLew	0:80ee8f3b695e	368	* @}
EricLew	0:80ee8f3b695e	369	*/
EricLew	0:80ee8f3b695e	370
EricLew	0:80ee8f3b695e	371	/** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source
EricLew	0:80ee8f3b695e	372	* @{
EricLew	0:80ee8f3b695e	373	*/
EricLew	0:80ee8f3b695e	374	#define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	375	#define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
EricLew	0:80ee8f3b695e	376	#define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
EricLew	0:80ee8f3b695e	377	#define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	378	/**
EricLew	0:80ee8f3b695e	379	* @}
EricLew	0:80ee8f3b695e	380	*/
EricLew	0:80ee8f3b695e	381
EricLew	0:80ee8f3b695e	382	/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
EricLew	0:80ee8f3b695e	383	* @{
EricLew	0:80ee8f3b695e	384	*/
EricLew	0:80ee8f3b695e	385	#define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	386	#define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
EricLew	0:80ee8f3b695e	387	#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
EricLew	0:80ee8f3b695e	388	#define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	389	/**
EricLew	0:80ee8f3b695e	390	* @}
EricLew	0:80ee8f3b695e	391	*/
EricLew	0:80ee8f3b695e	392
EricLew	0:80ee8f3b695e	393	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	394	/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
EricLew	0:80ee8f3b695e	395	* @{
EricLew	0:80ee8f3b695e	396	*/
EricLew	0:80ee8f3b695e	397	#define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	398	#define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0
EricLew	0:80ee8f3b695e	399	#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
EricLew	0:80ee8f3b695e	400	#define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL
EricLew	0:80ee8f3b695e	401	/**
EricLew	0:80ee8f3b695e	402	* @}
EricLew	0:80ee8f3b695e	403	*/
EricLew	0:80ee8f3b695e	404	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	405
EricLew	0:80ee8f3b695e	406	/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
EricLew	0:80ee8f3b695e	407	* @{
EricLew	0:80ee8f3b695e	408	*/
EricLew	0:80ee8f3b695e	409	#define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	410	#define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0
EricLew	0:80ee8f3b695e	411	#define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1
EricLew	0:80ee8f3b695e	412	#define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL
EricLew	0:80ee8f3b695e	413	/**
EricLew	0:80ee8f3b695e	414	* @}
EricLew	0:80ee8f3b695e	415	*/
EricLew	0:80ee8f3b695e	416
EricLew	0:80ee8f3b695e	417	/** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source
EricLew	0:80ee8f3b695e	418	* @{
EricLew	0:80ee8f3b695e	419	*/
EricLew	0:80ee8f3b695e	420	#define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	421	#define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL
EricLew	0:80ee8f3b695e	422	/**
EricLew	0:80ee8f3b695e	423	* @}
EricLew	0:80ee8f3b695e	424	*/
EricLew	0:80ee8f3b695e	425
EricLew	0:80ee8f3b695e	426	/** @defgroup RCCEx_DFSDM_Clock_Source DFSDM Clock Source
EricLew	0:80ee8f3b695e	427	* @{
EricLew	0:80ee8f3b695e	428	*/
EricLew	0:80ee8f3b695e	429	#define RCC_DFSDMCLKSOURCE_PCLK ((uint32_t)0x00000000)
EricLew	0:80ee8f3b695e	430	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_CCIPR_DFSDMSEL
EricLew	0:80ee8f3b695e	431	/**
EricLew	0:80ee8f3b695e	432	* @}
EricLew	0:80ee8f3b695e	433	*/
EricLew	0:80ee8f3b695e	434
EricLew	0:80ee8f3b695e	435	/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
EricLew	0:80ee8f3b695e	436	* @{
EricLew	0:80ee8f3b695e	437	*/
EricLew	0:80ee8f3b695e	438	#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /!< External interrupt line 19 connected to the LSE CSS EXTI Line /
EricLew	0:80ee8f3b695e	439	/**
EricLew	0:80ee8f3b695e	440	* @}
EricLew	0:80ee8f3b695e	441	*/
EricLew	0:80ee8f3b695e	442
EricLew	0:80ee8f3b695e	443	/**
EricLew	0:80ee8f3b695e	444	* @}
EricLew	0:80ee8f3b695e	445	*/
EricLew	0:80ee8f3b695e	446
EricLew	0:80ee8f3b695e	447	/* Exported macros -----------------------------------------------------------*/
EricLew	0:80ee8f3b695e	448	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
EricLew	0:80ee8f3b695e	449	* @{
EricLew	0:80ee8f3b695e	450	*/
EricLew	0:80ee8f3b695e	451
EricLew	0:80ee8f3b695e	452
EricLew	0:80ee8f3b695e	453	/**
EricLew	0:80ee8f3b695e	454	* @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
EricLew	0:80ee8f3b695e	455	*
EricLew	0:80ee8f3b695e	456	* @note This function must be used only when the PLLSAI1 is disabled.
EricLew	0:80ee8f3b695e	457	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	458	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	459	*
EricLew	0:80ee8f3b695e	460	* @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
EricLew	0:80ee8f3b695e	461	* This parameter must be a number between 8 and 86.
EricLew	0:80ee8f3b695e	462	* @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
EricLew	0:80ee8f3b695e	463	* output frequency is between 64 and 344 MHz.
EricLew	0:80ee8f3b695e	464	* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
EricLew	0:80ee8f3b695e	465	*
EricLew	0:80ee8f3b695e	466	* @param __PLLSAI1P__ specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	467	* This parameter must be a number in the range (7 or 17).
EricLew	0:80ee8f3b695e	468	* SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
EricLew	0:80ee8f3b695e	469	*
EricLew	0:80ee8f3b695e	470	* @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
EricLew	0:80ee8f3b695e	471	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	472	* USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
EricLew	0:80ee8f3b695e	473	*
EricLew	0:80ee8f3b695e	474	* @param __PLLSAI1R__ specifies the division factor for SAR ADC clock.
EricLew	0:80ee8f3b695e	475	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	476	* ADC clock frequency = f(PLLSAI1) / PLLSAI1R
EricLew	0:80ee8f3b695e	477	*
EricLew	0:80ee8f3b695e	478	* @retval None
EricLew	0:80ee8f3b695e	479	*/
EricLew	0:80ee8f3b695e	480	#define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \
EricLew	0:80ee8f3b695e	481	WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << 8U) \| (((__PLLSAI1P__) >> 4U) << 17U) \| \
EricLew	0:80ee8f3b695e	482	((((__PLLSAI1Q__) >> 1U) - 1) << 21U) \| ((((__PLLSAI1R__) >> 1U) - 1) << 25U))
EricLew	0:80ee8f3b695e	483
EricLew	0:80ee8f3b695e	484	/**
EricLew	0:80ee8f3b695e	485	* @brief Macro to configure the PLLSAI1 clock multiplication factor N.
EricLew	0:80ee8f3b695e	486	*
EricLew	0:80ee8f3b695e	487	* @note This function must be used only when the PLLSAI1 is disabled.
EricLew	0:80ee8f3b695e	488	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	489	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	490	*
EricLew	0:80ee8f3b695e	491	* @param __PLLSAI1N__ specifies the multiplication factor for PLLSAI1 VCO output clock.
EricLew	0:80ee8f3b695e	492	* This parameter must be a number between 8 and 86.
EricLew	0:80ee8f3b695e	493	* @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO
EricLew	0:80ee8f3b695e	494	* output frequency is between 64 and 344 MHz.
EricLew	0:80ee8f3b695e	495	* Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N
EricLew	0:80ee8f3b695e	496	*
EricLew	0:80ee8f3b695e	497	* @retval None
EricLew	0:80ee8f3b695e	498	*/
EricLew	0:80ee8f3b695e	499	#define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \
EricLew	0:80ee8f3b695e	500	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << 8U)
EricLew	0:80ee8f3b695e	501
EricLew	0:80ee8f3b695e	502	/** @brief Macro to configure the PLLSAI1 clock division factor P.
EricLew	0:80ee8f3b695e	503	*
EricLew	0:80ee8f3b695e	504	* @note This function must be used only when the PLLSAI1 is disabled.
EricLew	0:80ee8f3b695e	505	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	506	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	507	*
EricLew	0:80ee8f3b695e	508	* @param __PLLSAI1P__ specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	509	* This parameter must be a number in the range (7 or 17).
EricLew	0:80ee8f3b695e	510	* Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P
EricLew	0:80ee8f3b695e	511	*
EricLew	0:80ee8f3b695e	512	* @retval None
EricLew	0:80ee8f3b695e	513	*/
EricLew	0:80ee8f3b695e	514	#define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \
EricLew	0:80ee8f3b695e	515	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << 17U)
EricLew	0:80ee8f3b695e	516
EricLew	0:80ee8f3b695e	517	/** @brief Macro to configure the PLLSAI1 clock division factor Q.
EricLew	0:80ee8f3b695e	518	*
EricLew	0:80ee8f3b695e	519	* @note This function must be used only when the PLLSAI1 is disabled.
EricLew	0:80ee8f3b695e	520	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	521	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	522	*
EricLew	0:80ee8f3b695e	523	* @param __PLLSAI1Q__ specifies the division factor for USB/RNG/SDMMC1 clock.
EricLew	0:80ee8f3b695e	524	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	525	* Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q
EricLew	0:80ee8f3b695e	526	*
EricLew	0:80ee8f3b695e	527	* @retval None
EricLew	0:80ee8f3b695e	528	*/
EricLew	0:80ee8f3b695e	529	#define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \
EricLew	0:80ee8f3b695e	530	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1) << 21U)
EricLew	0:80ee8f3b695e	531
EricLew	0:80ee8f3b695e	532	/** @brief Macro to configure the PLLSAI1 clock division factor R.
EricLew	0:80ee8f3b695e	533	*
EricLew	0:80ee8f3b695e	534	* @note This function must be used only when the PLLSAI1 is disabled.
EricLew	0:80ee8f3b695e	535	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	536	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	537	*
EricLew	0:80ee8f3b695e	538	* @param __PLLSAI1R__ specifies the division factor for ADC clock.
EricLew	0:80ee8f3b695e	539	* This parameter must be in the range (2, 4, 6 or 8)
EricLew	0:80ee8f3b695e	540	* Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R
EricLew	0:80ee8f3b695e	541	*
EricLew	0:80ee8f3b695e	542	* @retval None
EricLew	0:80ee8f3b695e	543	*/
EricLew	0:80ee8f3b695e	544	#define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \
EricLew	0:80ee8f3b695e	545	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1) << 25U)
EricLew	0:80ee8f3b695e	546
EricLew	0:80ee8f3b695e	547	/**
EricLew	0:80ee8f3b695e	548	* @brief Macros to enable or disable the PLLSAI1.
EricLew	0:80ee8f3b695e	549	* @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	550	* @retval None
EricLew	0:80ee8f3b695e	551	*/
EricLew	0:80ee8f3b695e	552
EricLew	0:80ee8f3b695e	553	#define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
EricLew	0:80ee8f3b695e	554
EricLew	0:80ee8f3b695e	555	#define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON)
EricLew	0:80ee8f3b695e	556
EricLew	0:80ee8f3b695e	557	/**
EricLew	0:80ee8f3b695e	558	* @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
EricLew	0:80ee8f3b695e	559	* @note Enabling and disabling those clocks can be done without the need to stop the PLL.
EricLew	0:80ee8f3b695e	560	* This is mainly used to save Power.
EricLew	0:80ee8f3b695e	561	* @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
EricLew	0:80ee8f3b695e	562	* This parameter can be one or a combination of the following values:
EricLew	0:80ee8f3b695e	563	* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	564	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	565	* @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	566	* the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
EricLew	0:80ee8f3b695e	567	* @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
EricLew	0:80ee8f3b695e	568	* @retval None
EricLew	0:80ee8f3b695e	569	*/
EricLew	0:80ee8f3b695e	570
EricLew	0:80ee8f3b695e	571	#define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
EricLew	0:80ee8f3b695e	572
EricLew	0:80ee8f3b695e	573	#define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
EricLew	0:80ee8f3b695e	574
EricLew	0:80ee8f3b695e	575	/**
EricLew	0:80ee8f3b695e	576	* @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1).
EricLew	0:80ee8f3b695e	577	* @param __PLLSAI1_CLOCKOUT__ specifies the PLLSAI1 clock to be output.
EricLew	0:80ee8f3b695e	578	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	579	* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	580	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	581	* @arg @ref RCC_PLLSAI1_48M2CLK This clock is used to generate the clock for the USB OTG FS (48 MHz),
EricLew	0:80ee8f3b695e	582	* the random number generator (<=48 MHz) and the SDIO (<= 48 MHz).
EricLew	0:80ee8f3b695e	583	* @arg @ref RCC_PLLSAI1_ADC1CLK Clock used to clock ADC peripheral.
EricLew	0:80ee8f3b695e	584	* @retval SET / RESET
EricLew	0:80ee8f3b695e	585	*/
EricLew	0:80ee8f3b695e	586	#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
EricLew	0:80ee8f3b695e	587
EricLew	0:80ee8f3b695e	588	/**
EricLew	0:80ee8f3b695e	589	* @brief Macro to configure the PLLSAI2 clock multiplication and division factors.
EricLew	0:80ee8f3b695e	590	*
EricLew	0:80ee8f3b695e	591	* @note This function must be used only when the PLLSAI2 is disabled.
EricLew	0:80ee8f3b695e	592	* @note PLLSAI2 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	593	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	594	*
EricLew	0:80ee8f3b695e	595	* @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
EricLew	0:80ee8f3b695e	596	* This parameter must be a number between 8 and 86.
EricLew	0:80ee8f3b695e	597	* @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
EricLew	0:80ee8f3b695e	598	* output frequency is between 64 and 344 MHz.
EricLew	0:80ee8f3b695e	599	*
EricLew	0:80ee8f3b695e	600	* @param __PLLSAI2P__ specifies the division factor for SAI clock.
EricLew	0:80ee8f3b695e	601	* This parameter must be a number in the range (7 or 17).
EricLew	0:80ee8f3b695e	602	*
EricLew	0:80ee8f3b695e	603	*
EricLew	0:80ee8f3b695e	604	* @param __PLLSAI2R__ specifies the division factor for SAR ADC clock.
EricLew	0:80ee8f3b695e	605	* This parameter must be in the range (2, 4, 6 or 8)
EricLew	0:80ee8f3b695e	606	*
EricLew	0:80ee8f3b695e	607	* @retval None
EricLew	0:80ee8f3b695e	608	*/
EricLew	0:80ee8f3b695e	609
EricLew	0:80ee8f3b695e	610	#define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \
EricLew	0:80ee8f3b695e	611	WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << 8U) \| (((__PLLSAI2P__) >> 4U) << 17U) \| \
EricLew	0:80ee8f3b695e	612	((((__PLLSAI2R__) >> 1U) - 1) << 25U))
EricLew	0:80ee8f3b695e	613
EricLew	0:80ee8f3b695e	614	/**
EricLew	0:80ee8f3b695e	615	* @brief Macro to configure the PLLSAI2 clock multiplication factor N.
EricLew	0:80ee8f3b695e	616	*
EricLew	0:80ee8f3b695e	617	* @note This function must be used only when the PLLSAI2 is disabled.
EricLew	0:80ee8f3b695e	618	* @note PLLSAI2 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	619	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	620	*
EricLew	0:80ee8f3b695e	621	* @param __PLLSAI2N__ specifies the multiplication factor for PLLSAI2 VCO output clock.
EricLew	0:80ee8f3b695e	622	* This parameter must be a number between 8 and 86.
EricLew	0:80ee8f3b695e	623	* @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO
EricLew	0:80ee8f3b695e	624	* output frequency is between 64 and 344 MHz.
EricLew	0:80ee8f3b695e	625	* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N
EricLew	0:80ee8f3b695e	626	*
EricLew	0:80ee8f3b695e	627	* @retval None
EricLew	0:80ee8f3b695e	628	*/
EricLew	0:80ee8f3b695e	629	#define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \
EricLew	0:80ee8f3b695e	630	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << 8U)
EricLew	0:80ee8f3b695e	631
EricLew	0:80ee8f3b695e	632	/** @brief Macro to configure the PLLSAI2 clock division factor P.
EricLew	0:80ee8f3b695e	633	*
EricLew	0:80ee8f3b695e	634	* @note This function must be used only when the PLLSAI2 is disabled.
EricLew	0:80ee8f3b695e	635	* @note PLLSAI2 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	636	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	637	*
EricLew	0:80ee8f3b695e	638	* @param __PLLSAI2P__ specifies the division factor.
EricLew	0:80ee8f3b695e	639	* This parameter must be a number in the range (7 or 17).
EricLew	0:80ee8f3b695e	640	* Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__
EricLew	0:80ee8f3b695e	641	*
EricLew	0:80ee8f3b695e	642	* @retval None
EricLew	0:80ee8f3b695e	643	*/
EricLew	0:80ee8f3b695e	644	#define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \
EricLew	0:80ee8f3b695e	645	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << 17U)
EricLew	0:80ee8f3b695e	646
EricLew	0:80ee8f3b695e	647	/** @brief Macro to configure the PLLSAI2 clock division factor R.
EricLew	0:80ee8f3b695e	648	*
EricLew	0:80ee8f3b695e	649	* @note This function must be used only when the PLLSAI2 is disabled.
EricLew	0:80ee8f3b695e	650	* @note PLLSAI1 clock source is common with the main PLL (configured through
EricLew	0:80ee8f3b695e	651	* __HAL_RCC_PLL_CONFIG() macro)
EricLew	0:80ee8f3b695e	652	*
EricLew	0:80ee8f3b695e	653	* @param __PLLSAI2R__ specifies the division factor.
EricLew	0:80ee8f3b695e	654	* This parameter must be in the range (2, 4, 6 or 8).
EricLew	0:80ee8f3b695e	655	* Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2Q__
EricLew	0:80ee8f3b695e	656	*
EricLew	0:80ee8f3b695e	657	* @retval None
EricLew	0:80ee8f3b695e	658	*/
EricLew	0:80ee8f3b695e	659	#define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \
EricLew	0:80ee8f3b695e	660	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1) << 25U)
EricLew	0:80ee8f3b695e	661
EricLew	0:80ee8f3b695e	662	/**
EricLew	0:80ee8f3b695e	663	* @brief Macros to enable or disable the PLLSAI2.
EricLew	0:80ee8f3b695e	664	* @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes.
EricLew	0:80ee8f3b695e	665	* @retval None
EricLew	0:80ee8f3b695e	666	*/
EricLew	0:80ee8f3b695e	667
EricLew	0:80ee8f3b695e	668	#define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
EricLew	0:80ee8f3b695e	669
EricLew	0:80ee8f3b695e	670	#define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON)
EricLew	0:80ee8f3b695e	671
EricLew	0:80ee8f3b695e	672	/**
EricLew	0:80ee8f3b695e	673	* @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2).
EricLew	0:80ee8f3b695e	674	* @note Enabling and disabling those clocks can be done without the need to stop the PLL.
EricLew	0:80ee8f3b695e	675	* This is mainly used to save Power.
EricLew	0:80ee8f3b695e	676	* @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
EricLew	0:80ee8f3b695e	677	* This parameter can be one or a combination of the following values:
EricLew	0:80ee8f3b695e	678	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	679	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	680	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
EricLew	0:80ee8f3b695e	681	* @retval None
EricLew	0:80ee8f3b695e	682	*/
EricLew	0:80ee8f3b695e	683
EricLew	0:80ee8f3b695e	684	#define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
EricLew	0:80ee8f3b695e	685
EricLew	0:80ee8f3b695e	686	#define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
EricLew	0:80ee8f3b695e	687
EricLew	0:80ee8f3b695e	688	/**
EricLew	0:80ee8f3b695e	689	* @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2).
EricLew	0:80ee8f3b695e	690	* @param __PLLSAI2_CLOCKOUT__ specifies the PLLSAI2 clock to be output.
EricLew	0:80ee8f3b695e	691	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	692	* @arg @ref RCC_PLLSAI2_SAI2CLK This clock is used to generate an accurate clock to achieve
EricLew	0:80ee8f3b695e	693	* high-quality audio performance on SAI interface in case.
EricLew	0:80ee8f3b695e	694	* @arg @ref RCC_PLLSAI2_ADC2CLK Clock used to clock ADC peripheral.
EricLew	0:80ee8f3b695e	695	* @retval SET / RESET
EricLew	0:80ee8f3b695e	696	*/
EricLew	0:80ee8f3b695e	697	#define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__))
EricLew	0:80ee8f3b695e	698
EricLew	0:80ee8f3b695e	699	/**
EricLew	0:80ee8f3b695e	700	* @brief Macro to configure the SAI1 clock source.
EricLew	0:80ee8f3b695e	701	* @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
EricLew	0:80ee8f3b695e	702	* from the PLLSAI1, system PLL or external clock (through a dedicated pin).
EricLew	0:80ee8f3b695e	703	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	704	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
EricLew	0:80ee8f3b695e	705	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
EricLew	0:80ee8f3b695e	706	* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK)
EricLew	0:80ee8f3b695e	707	* @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
EricLew	0:80ee8f3b695e	708	*
EricLew	0:80ee8f3b695e	709	* @retval None
EricLew	0:80ee8f3b695e	710	*/
EricLew	0:80ee8f3b695e	711	#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
EricLew	0:80ee8f3b695e	712	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	713
EricLew	0:80ee8f3b695e	714	/** @brief Macro to get the SAI1 clock source.
EricLew	0:80ee8f3b695e	715	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	716	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI1 SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
EricLew	0:80ee8f3b695e	717	* @arg @ref RCC_SAI1CLKSOURCE_PLLSAI2 SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
EricLew	0:80ee8f3b695e	718	* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "P" clock (PLLSAI3CLK)
EricLew	0:80ee8f3b695e	719	* @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK)
EricLew	0:80ee8f3b695e	720	*/
EricLew	0:80ee8f3b695e	721	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL)))
EricLew	0:80ee8f3b695e	722
EricLew	0:80ee8f3b695e	723	/**
EricLew	0:80ee8f3b695e	724	* @brief Macro to configure the SAI2 clock source.
EricLew	0:80ee8f3b695e	725	* @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived
EricLew	0:80ee8f3b695e	726	* from the PLLSAI2, system PLL or external clock (through a dedicated pin).
EricLew	0:80ee8f3b695e	727	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	728	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
EricLew	0:80ee8f3b695e	729	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
EricLew	0:80ee8f3b695e	730	* @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
EricLew	0:80ee8f3b695e	731	* @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
EricLew	0:80ee8f3b695e	732	* @retval None
EricLew	0:80ee8f3b695e	733	*/
EricLew	0:80ee8f3b695e	734	#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\
EricLew	0:80ee8f3b695e	735	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__))
EricLew	0:80ee8f3b695e	736
EricLew	0:80ee8f3b695e	737	/** @brief Macro to get the SAI2 clock source.
EricLew	0:80ee8f3b695e	738	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	739	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI1 SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK)
EricLew	0:80ee8f3b695e	740	* @arg @ref RCC_SAI2CLKSOURCE_PLLSAI2 SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK)
EricLew	0:80ee8f3b695e	741	* @arg @ref RCC_SAI2CLKSOURCE_PLL SAI2 clock = PLL "P" clock (PLLSAI3CLK)
EricLew	0:80ee8f3b695e	742	* @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK)
EricLew	0:80ee8f3b695e	743	*/
EricLew	0:80ee8f3b695e	744	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL)))
EricLew	0:80ee8f3b695e	745
EricLew	0:80ee8f3b695e	746	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
EricLew	0:80ee8f3b695e	747	*
EricLew	0:80ee8f3b695e	748	* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
EricLew	0:80ee8f3b695e	749	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	750	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
EricLew	0:80ee8f3b695e	751	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
EricLew	0:80ee8f3b695e	752	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
EricLew	0:80ee8f3b695e	753	* @retval None
EricLew	0:80ee8f3b695e	754	*/
EricLew	0:80ee8f3b695e	755	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	756	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	757
EricLew	0:80ee8f3b695e	758	/** @brief Macro to get the I2C1 clock source.
EricLew	0:80ee8f3b695e	759	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	760	* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
EricLew	0:80ee8f3b695e	761	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
EricLew	0:80ee8f3b695e	762	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
EricLew	0:80ee8f3b695e	763	*/
EricLew	0:80ee8f3b695e	764	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
EricLew	0:80ee8f3b695e	765
EricLew	0:80ee8f3b695e	766	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
EricLew	0:80ee8f3b695e	767	*
EricLew	0:80ee8f3b695e	768	* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
EricLew	0:80ee8f3b695e	769	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	770	* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
EricLew	0:80ee8f3b695e	771	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
EricLew	0:80ee8f3b695e	772	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
EricLew	0:80ee8f3b695e	773	* @retval None
EricLew	0:80ee8f3b695e	774	*/
EricLew	0:80ee8f3b695e	775	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	776	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
EricLew	0:80ee8f3b695e	777
EricLew	0:80ee8f3b695e	778	/** @brief Macro to get the I2C2 clock source.
EricLew	0:80ee8f3b695e	779	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	780	* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
EricLew	0:80ee8f3b695e	781	* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
EricLew	0:80ee8f3b695e	782	* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
EricLew	0:80ee8f3b695e	783	*/
EricLew	0:80ee8f3b695e	784	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL)))
EricLew	0:80ee8f3b695e	785
EricLew	0:80ee8f3b695e	786	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
EricLew	0:80ee8f3b695e	787	*
EricLew	0:80ee8f3b695e	788	* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
EricLew	0:80ee8f3b695e	789	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	790	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
EricLew	0:80ee8f3b695e	791	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
EricLew	0:80ee8f3b695e	792	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
EricLew	0:80ee8f3b695e	793	* @retval None
EricLew	0:80ee8f3b695e	794	*/
EricLew	0:80ee8f3b695e	795	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	796	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
EricLew	0:80ee8f3b695e	797
EricLew	0:80ee8f3b695e	798	/** @brief Macro to get the I2C3 clock source.
EricLew	0:80ee8f3b695e	799	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	800	* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
EricLew	0:80ee8f3b695e	801	* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
EricLew	0:80ee8f3b695e	802	* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
EricLew	0:80ee8f3b695e	803	*/
EricLew	0:80ee8f3b695e	804	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
EricLew	0:80ee8f3b695e	805
EricLew	0:80ee8f3b695e	806	/** @brief Macro to configure the USART1 clock (USART1CLK).
EricLew	0:80ee8f3b695e	807	*
EricLew	0:80ee8f3b695e	808	* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
EricLew	0:80ee8f3b695e	809	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	810	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
EricLew	0:80ee8f3b695e	811	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
EricLew	0:80ee8f3b695e	812	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
EricLew	0:80ee8f3b695e	813	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
EricLew	0:80ee8f3b695e	814	* @retval None
EricLew	0:80ee8f3b695e	815	*/
EricLew	0:80ee8f3b695e	816	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	817	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	818
EricLew	0:80ee8f3b695e	819	/** @brief Macro to get the USART1 clock source.
EricLew	0:80ee8f3b695e	820	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	821	* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
EricLew	0:80ee8f3b695e	822	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
EricLew	0:80ee8f3b695e	823	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
EricLew	0:80ee8f3b695e	824	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
EricLew	0:80ee8f3b695e	825	*/
EricLew	0:80ee8f3b695e	826	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
EricLew	0:80ee8f3b695e	827
EricLew	0:80ee8f3b695e	828	/** @brief Macro to configure the USART2 clock (USART2CLK).
EricLew	0:80ee8f3b695e	829	*
EricLew	0:80ee8f3b695e	830	* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
EricLew	0:80ee8f3b695e	831	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	832	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
EricLew	0:80ee8f3b695e	833	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
EricLew	0:80ee8f3b695e	834	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
EricLew	0:80ee8f3b695e	835	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
EricLew	0:80ee8f3b695e	836	* @retval None
EricLew	0:80ee8f3b695e	837	*/
EricLew	0:80ee8f3b695e	838	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	839	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
EricLew	0:80ee8f3b695e	840
EricLew	0:80ee8f3b695e	841	/** @brief Macro to get the USART2 clock source.
EricLew	0:80ee8f3b695e	842	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	843	* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
EricLew	0:80ee8f3b695e	844	* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
EricLew	0:80ee8f3b695e	845	* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
EricLew	0:80ee8f3b695e	846	* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
EricLew	0:80ee8f3b695e	847	*/
EricLew	0:80ee8f3b695e	848	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
EricLew	0:80ee8f3b695e	849
EricLew	0:80ee8f3b695e	850	/** @brief Macro to configure the USART3 clock (USART3CLK).
EricLew	0:80ee8f3b695e	851	*
EricLew	0:80ee8f3b695e	852	* @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
EricLew	0:80ee8f3b695e	853	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	854	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
EricLew	0:80ee8f3b695e	855	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
EricLew	0:80ee8f3b695e	856	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
EricLew	0:80ee8f3b695e	857	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
EricLew	0:80ee8f3b695e	858	* @retval None
EricLew	0:80ee8f3b695e	859	*/
EricLew	0:80ee8f3b695e	860	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	861	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
EricLew	0:80ee8f3b695e	862
EricLew	0:80ee8f3b695e	863	/** @brief Macro to get the USART3 clock source.
EricLew	0:80ee8f3b695e	864	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	865	* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
EricLew	0:80ee8f3b695e	866	* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
EricLew	0:80ee8f3b695e	867	* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
EricLew	0:80ee8f3b695e	868	* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
EricLew	0:80ee8f3b695e	869	*/
EricLew	0:80ee8f3b695e	870	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL)))
EricLew	0:80ee8f3b695e	871
EricLew	0:80ee8f3b695e	872	/** @brief Macro to configure the UART4 clock (UART4CLK).
EricLew	0:80ee8f3b695e	873	*
EricLew	0:80ee8f3b695e	874	* @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
EricLew	0:80ee8f3b695e	875	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	876	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
EricLew	0:80ee8f3b695e	877	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
EricLew	0:80ee8f3b695e	878	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
EricLew	0:80ee8f3b695e	879	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
EricLew	0:80ee8f3b695e	880	* @retval None
EricLew	0:80ee8f3b695e	881	*/
EricLew	0:80ee8f3b695e	882	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	883	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
EricLew	0:80ee8f3b695e	884
EricLew	0:80ee8f3b695e	885	/** @brief Macro to get the UART4 clock source.
EricLew	0:80ee8f3b695e	886	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	887	* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
EricLew	0:80ee8f3b695e	888	* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
EricLew	0:80ee8f3b695e	889	* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
EricLew	0:80ee8f3b695e	890	* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
EricLew	0:80ee8f3b695e	891	*/
EricLew	0:80ee8f3b695e	892	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL)))
EricLew	0:80ee8f3b695e	893
EricLew	0:80ee8f3b695e	894	/** @brief Macro to configure the UART5 clock (UART5CLK).
EricLew	0:80ee8f3b695e	895	*
EricLew	0:80ee8f3b695e	896	* @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
EricLew	0:80ee8f3b695e	897	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	898	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
EricLew	0:80ee8f3b695e	899	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
EricLew	0:80ee8f3b695e	900	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
EricLew	0:80ee8f3b695e	901	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
EricLew	0:80ee8f3b695e	902	* @retval None
EricLew	0:80ee8f3b695e	903	*/
EricLew	0:80ee8f3b695e	904	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	905	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
EricLew	0:80ee8f3b695e	906
EricLew	0:80ee8f3b695e	907	/** @brief Macro to get the UART5 clock source.
EricLew	0:80ee8f3b695e	908	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	909	* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
EricLew	0:80ee8f3b695e	910	* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
EricLew	0:80ee8f3b695e	911	* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
EricLew	0:80ee8f3b695e	912	* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
EricLew	0:80ee8f3b695e	913	*/
EricLew	0:80ee8f3b695e	914	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL)))
EricLew	0:80ee8f3b695e	915
EricLew	0:80ee8f3b695e	916	/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
EricLew	0:80ee8f3b695e	917	*
EricLew	0:80ee8f3b695e	918	* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
EricLew	0:80ee8f3b695e	919	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	920	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
EricLew	0:80ee8f3b695e	921	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
EricLew	0:80ee8f3b695e	922	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
EricLew	0:80ee8f3b695e	923	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
EricLew	0:80ee8f3b695e	924	* @retval None
EricLew	0:80ee8f3b695e	925	*/
EricLew	0:80ee8f3b695e	926	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	927	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	928
EricLew	0:80ee8f3b695e	929	/** @brief Macro to get the LPUART1 clock source.
EricLew	0:80ee8f3b695e	930	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	931	* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
EricLew	0:80ee8f3b695e	932	* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
EricLew	0:80ee8f3b695e	933	* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
EricLew	0:80ee8f3b695e	934	* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
EricLew	0:80ee8f3b695e	935	*/
EricLew	0:80ee8f3b695e	936	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
EricLew	0:80ee8f3b695e	937
EricLew	0:80ee8f3b695e	938	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
EricLew	0:80ee8f3b695e	939	*
EricLew	0:80ee8f3b695e	940	* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
EricLew	0:80ee8f3b695e	941	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	942	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPTIM1 clock
EricLew	0:80ee8f3b695e	943	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
EricLew	0:80ee8f3b695e	944	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
EricLew	0:80ee8f3b695e	945	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
EricLew	0:80ee8f3b695e	946	* @retval None
EricLew	0:80ee8f3b695e	947	*/
EricLew	0:80ee8f3b695e	948	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	949	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	950
EricLew	0:80ee8f3b695e	951	/** @brief Macro to get the LPTIM1 clock source.
EricLew	0:80ee8f3b695e	952	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	953	* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK PCLK selected as LPUART1 clock
EricLew	0:80ee8f3b695e	954	* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
EricLew	0:80ee8f3b695e	955	* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
EricLew	0:80ee8f3b695e	956	* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
EricLew	0:80ee8f3b695e	957	*/
EricLew	0:80ee8f3b695e	958	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
EricLew	0:80ee8f3b695e	959
EricLew	0:80ee8f3b695e	960	/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK).
EricLew	0:80ee8f3b695e	961	*
EricLew	0:80ee8f3b695e	962	* @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
EricLew	0:80ee8f3b695e	963	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	964	* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPTIM2 clock
EricLew	0:80ee8f3b695e	965	* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock
EricLew	0:80ee8f3b695e	966	* @arg @ref RCC_LPTIM2CLKSOURCE_HSI LSI selected as LPTIM2 clock
EricLew	0:80ee8f3b695e	967	* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock
EricLew	0:80ee8f3b695e	968	* @retval None
EricLew	0:80ee8f3b695e	969	*/
EricLew	0:80ee8f3b695e	970	#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	971	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__))
EricLew	0:80ee8f3b695e	972
EricLew	0:80ee8f3b695e	973	/** @brief Macro to get the LPTIM2 clock source.
EricLew	0:80ee8f3b695e	974	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	975	* @arg @ref RCC_LPTIM2CLKSOURCE_PCLK PCLK selected as LPUART1 clock
EricLew	0:80ee8f3b695e	976	* @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPUART1 clock
EricLew	0:80ee8f3b695e	977	* @arg @ref RCC_LPTIM2CLKSOURCE_HSI System Clock selected as LPUART1 clock
EricLew	0:80ee8f3b695e	978	* @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPUART1 clock
EricLew	0:80ee8f3b695e	979	*/
EricLew	0:80ee8f3b695e	980	#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL)))
EricLew	0:80ee8f3b695e	981
EricLew	0:80ee8f3b695e	982	/** @brief Macro to configure the SDMMC1 clock.
EricLew	0:80ee8f3b695e	983	*
EricLew	0:80ee8f3b695e	984	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
EricLew	0:80ee8f3b695e	985	*
EricLew	0:80ee8f3b695e	986	* @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
EricLew	0:80ee8f3b695e	987	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	988	* @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	989	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	990	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	991	* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL Clock selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	992	* @retval None
EricLew	0:80ee8f3b695e	993	*/
EricLew	0:80ee8f3b695e	994	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	995	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	996
EricLew	0:80ee8f3b695e	997	/** @brief Macro to get the SDMMC1 clock.
EricLew	0:80ee8f3b695e	998	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	999	* @arg @ref RCC_SDMMC1CLKSOURCE_NONE No clock selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	1000	* @arg @ref RCC_SDMMC1CLKSOURCE_MSI MSI selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	1001	* @arg @ref RCC_SDMMC1CLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	1002	* @arg @ref RCC_SDMMC1CLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock
EricLew	0:80ee8f3b695e	1003	*/
EricLew	0:80ee8f3b695e	1004	#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
EricLew	0:80ee8f3b695e	1005
EricLew	0:80ee8f3b695e	1006	/** @brief Macro to configure the RNG clock.
EricLew	0:80ee8f3b695e	1007	*
EricLew	0:80ee8f3b695e	1008	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
EricLew	0:80ee8f3b695e	1009	*
EricLew	0:80ee8f3b695e	1010	* @param __RNG_CLKSOURCE__ specifies the RNG clock source.
EricLew	0:80ee8f3b695e	1011	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1012	* @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock
EricLew	0:80ee8f3b695e	1013	* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
EricLew	0:80ee8f3b695e	1014	* @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as RNG clock
EricLew	0:80ee8f3b695e	1015	* @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
EricLew	0:80ee8f3b695e	1016	* @retval None
EricLew	0:80ee8f3b695e	1017	*/
EricLew	0:80ee8f3b695e	1018	#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	1019	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__))
EricLew	0:80ee8f3b695e	1020
EricLew	0:80ee8f3b695e	1021	/** @brief Macro to get the RNG clock.
EricLew	0:80ee8f3b695e	1022	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	1023	* @arg @ref RCC_RNGCLKSOURCE_NONE No clock selected as RNG clock
EricLew	0:80ee8f3b695e	1024	* @arg @ref RCC_RNGCLKSOURCE_MSI MSI selected as RNG clock
EricLew	0:80ee8f3b695e	1025	* @arg @ref RCC_RNGCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock
EricLew	0:80ee8f3b695e	1026	* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as RNG clock
EricLew	0:80ee8f3b695e	1027	*/
EricLew	0:80ee8f3b695e	1028	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
EricLew	0:80ee8f3b695e	1029
EricLew	0:80ee8f3b695e	1030	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1031	/** @brief Macro to configure the USB clock (USBCLK).
EricLew	0:80ee8f3b695e	1032	*
EricLew	0:80ee8f3b695e	1033	* @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source.
EricLew	0:80ee8f3b695e	1034	*
EricLew	0:80ee8f3b695e	1035	* @param __USB_CLKSOURCE__ specifies the USB clock source.
EricLew	0:80ee8f3b695e	1036	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1037	* @arg @ref RCC_USBCLKSOURCE_NONE No clock selected
EricLew	0:80ee8f3b695e	1038	* @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
EricLew	0:80ee8f3b695e	1039	* @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
EricLew	0:80ee8f3b695e	1040	* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
EricLew	0:80ee8f3b695e	1041	* @retval None
EricLew	0:80ee8f3b695e	1042	*/
EricLew	0:80ee8f3b695e	1043	#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	1044	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__))
EricLew	0:80ee8f3b695e	1045
EricLew	0:80ee8f3b695e	1046	/** @brief Macro to get the USB clock source.
EricLew	0:80ee8f3b695e	1047	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	1048	* @arg @ref RCC_USBCLKSOURCE_NONE No clock selected
EricLew	0:80ee8f3b695e	1049	* @arg @ref RCC_USBCLKSOURCE_MSI MSI selected as USB clock
EricLew	0:80ee8f3b695e	1050	* @arg @ref RCC_USBCLKSOURCE_PLLSAI1 PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock
EricLew	0:80ee8f3b695e	1051	* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
EricLew	0:80ee8f3b695e	1052	*/
EricLew	0:80ee8f3b695e	1053	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL)))
EricLew	0:80ee8f3b695e	1054
EricLew	0:80ee8f3b695e	1055	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1056
EricLew	0:80ee8f3b695e	1057	/** @brief Macro to configure the ADC interface clock.
EricLew	0:80ee8f3b695e	1058	* @param __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
EricLew	0:80ee8f3b695e	1059	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1060	* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
EricLew	0:80ee8f3b695e	1061	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1062	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1063	* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1064	* @retval None
EricLew	0:80ee8f3b695e	1065	*/
EricLew	0:80ee8f3b695e	1066	#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	1067	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__))
EricLew	0:80ee8f3b695e	1068
EricLew	0:80ee8f3b695e	1069	/** @brief Macro to get the ADC clock source.
EricLew	0:80ee8f3b695e	1070	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	1071	* @arg @ref RCC_ADCCLKSOURCE_NONE No clock selected as ADC clock
EricLew	0:80ee8f3b695e	1072	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI1 PLLSAI1 Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1073	* @arg @ref RCC_ADCCLKSOURCE_PLLSAI2 PLLSAI2 Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1074	* @arg @ref RCC_ADCCLKSOURCE_SYSCLK System Clock selected as ADC clock
EricLew	0:80ee8f3b695e	1075	*/
EricLew	0:80ee8f3b695e	1076	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL)))
EricLew	0:80ee8f3b695e	1077
EricLew	0:80ee8f3b695e	1078	/** @brief Macro to configure the SWPMI1 clock.
EricLew	0:80ee8f3b695e	1079	* @param __SWPMI1_CLKSOURCE__ specifies the SWPMI1 clock source.
EricLew	0:80ee8f3b695e	1080	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1081	* @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
EricLew	0:80ee8f3b695e	1082	* @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
EricLew	0:80ee8f3b695e	1083	* @retval None
EricLew	0:80ee8f3b695e	1084	*/
EricLew	0:80ee8f3b695e	1085	#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	1086	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__))
EricLew	0:80ee8f3b695e	1087
EricLew	0:80ee8f3b695e	1088	/** @brief Macro to get the SWPMI1 clock source.
EricLew	0:80ee8f3b695e	1089	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	1090	* @arg @ref RCC_SWPMI1CLKSOURCE_PCLK PCLK Clock selected as SWPMI1 clock
EricLew	0:80ee8f3b695e	1091	* @arg @ref RCC_SWPMI1CLKSOURCE_HSI HSI Clock selected as SWPMI1 clock
EricLew	0:80ee8f3b695e	1092	*/
EricLew	0:80ee8f3b695e	1093	#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL)))
EricLew	0:80ee8f3b695e	1094
EricLew	0:80ee8f3b695e	1095	/** @brief Macro to configure the DFSDM clock.
EricLew	0:80ee8f3b695e	1096	* @param __DFSDM_CLKSOURCE__ specifies the DFSDM clock source.
EricLew	0:80ee8f3b695e	1097	* This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1098	* @arg @ref RCC_DFSDMCLKSOURCE_PCLK PCLK Clock selected as DFSDM clock
EricLew	0:80ee8f3b695e	1099	* @arg @ref RCC_DFSDMCLKSOURCE_SYSCLK System Clock selected as DFSDM clock
EricLew	0:80ee8f3b695e	1100	* @retval None
EricLew	0:80ee8f3b695e	1101	*/
EricLew	0:80ee8f3b695e	1102	#define __HAL_RCC_DFSDM_CONFIG(__DFSDM_CLKSOURCE__) \
EricLew	0:80ee8f3b695e	1103	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, (uint32_t)(__DFSDM_CLKSOURCE__))
EricLew	0:80ee8f3b695e	1104
EricLew	0:80ee8f3b695e	1105	/** @brief Macro to get the DFSDM clock source.
EricLew	0:80ee8f3b695e	1106	* @retval The clock source can be one of the following values:
EricLew	0:80ee8f3b695e	1107	* @arg @ref RCC_DFSDMCLKSOURCE_PCLK PCLK Clock selected as DFSDM clock
EricLew	0:80ee8f3b695e	1108	* @arg @ref RCC_DFSDMCLKSOURCE_SYSCLK System Clock selected as DFSDM clock
EricLew	0:80ee8f3b695e	1109	*/
EricLew	0:80ee8f3b695e	1110	#define __HAL_RCC_GET_DFSDM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDMSEL)))
EricLew	0:80ee8f3b695e	1111
EricLew	0:80ee8f3b695e	1112	/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
EricLew	0:80ee8f3b695e	1113	* @brief macros to manage the specified RCC Flags and interrupts.
EricLew	0:80ee8f3b695e	1114	* @{
EricLew	0:80ee8f3b695e	1115	*/
EricLew	0:80ee8f3b695e	1116
EricLew	0:80ee8f3b695e	1117	/** @brief Enable PLLSAI1RDY interrupt.
EricLew	0:80ee8f3b695e	1118	* @retval None
EricLew	0:80ee8f3b695e	1119	*/
EricLew	0:80ee8f3b695e	1120	#define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
EricLew	0:80ee8f3b695e	1121
EricLew	0:80ee8f3b695e	1122	/** @brief Disable PLLSAI1RDY interrupt.
EricLew	0:80ee8f3b695e	1123	* @retval None
EricLew	0:80ee8f3b695e	1124	*/
EricLew	0:80ee8f3b695e	1125	#define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE)
EricLew	0:80ee8f3b695e	1126
EricLew	0:80ee8f3b695e	1127	/** @brief Clear the PLLSAI1RDY interrupt pending bit.
EricLew	0:80ee8f3b695e	1128	* @retval None
EricLew	0:80ee8f3b695e	1129	*/
EricLew	0:80ee8f3b695e	1130	#define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC)
EricLew	0:80ee8f3b695e	1131
EricLew	0:80ee8f3b695e	1132	/** @brief Check whether PLLSAI1RDY interrupt has occurred or not.
EricLew	0:80ee8f3b695e	1133	* @retval TRUE or FALSE.
EricLew	0:80ee8f3b695e	1134	*/
EricLew	0:80ee8f3b695e	1135	#define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF)
EricLew	0:80ee8f3b695e	1136
EricLew	0:80ee8f3b695e	1137	/** @brief Check whether the PLLSAI1RDY flag is set or not.
EricLew	0:80ee8f3b695e	1138	* @retval TRUE or FALSE.
EricLew	0:80ee8f3b695e	1139	*/
EricLew	0:80ee8f3b695e	1140	#define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY))
EricLew	0:80ee8f3b695e	1141
EricLew	0:80ee8f3b695e	1142	/** @brief Enable PLLSAI2RDY interrupt.
EricLew	0:80ee8f3b695e	1143	* @retval None
EricLew	0:80ee8f3b695e	1144	*/
EricLew	0:80ee8f3b695e	1145	#define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
EricLew	0:80ee8f3b695e	1146
EricLew	0:80ee8f3b695e	1147	/** @brief Disable PLLSAI2RDY interrupt.
EricLew	0:80ee8f3b695e	1148	* @retval None
EricLew	0:80ee8f3b695e	1149	*/
EricLew	0:80ee8f3b695e	1150	#define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE)
EricLew	0:80ee8f3b695e	1151
EricLew	0:80ee8f3b695e	1152	/** @brief Clear the PLLSAI2RDY interrupt pending bit.
EricLew	0:80ee8f3b695e	1153	* @retval None
EricLew	0:80ee8f3b695e	1154	*/
EricLew	0:80ee8f3b695e	1155	#define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC)
EricLew	0:80ee8f3b695e	1156
EricLew	0:80ee8f3b695e	1157	/** @brief Check whether the PLLSAI2RDY interrupt has occurred or not.
EricLew	0:80ee8f3b695e	1158	* @retval TRUE or FALSE.
EricLew	0:80ee8f3b695e	1159	*/
EricLew	0:80ee8f3b695e	1160	#define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF)
EricLew	0:80ee8f3b695e	1161
EricLew	0:80ee8f3b695e	1162	/** @brief Check whether the PLLSAI2RDY flag is set or not.
EricLew	0:80ee8f3b695e	1163	* @retval TRUE or FALSE.
EricLew	0:80ee8f3b695e	1164	*/
EricLew	0:80ee8f3b695e	1165	#define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY))
EricLew	0:80ee8f3b695e	1166
EricLew	0:80ee8f3b695e	1167
EricLew	0:80ee8f3b695e	1168	/**
EricLew	0:80ee8f3b695e	1169	* @brief Enable the RCC LSE CSS Extended Interrupt Line.
EricLew	0:80ee8f3b695e	1170	* @retval None
EricLew	0:80ee8f3b695e	1171	*/
EricLew	0:80ee8f3b695e	1172	#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1173
EricLew	0:80ee8f3b695e	1174	/**
EricLew	0:80ee8f3b695e	1175	* @brief Disable the RCC LSE CSS Extended Interrupt Line.
EricLew	0:80ee8f3b695e	1176	* @retval None
EricLew	0:80ee8f3b695e	1177	*/
EricLew	0:80ee8f3b695e	1178	#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1179
EricLew	0:80ee8f3b695e	1180	/**
EricLew	0:80ee8f3b695e	1181	* @brief Enable the RCC LSE CSS Event Line.
EricLew	0:80ee8f3b695e	1182	* @retval None.
EricLew	0:80ee8f3b695e	1183	*/
EricLew	0:80ee8f3b695e	1184	#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1185
EricLew	0:80ee8f3b695e	1186	/**
EricLew	0:80ee8f3b695e	1187	* @brief Disable the RCC LSE CSS Event Line.
EricLew	0:80ee8f3b695e	1188	* @retval None.
EricLew	0:80ee8f3b695e	1189	*/
EricLew	0:80ee8f3b695e	1190	#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1191
EricLew	0:80ee8f3b695e	1192
EricLew	0:80ee8f3b695e	1193	/**
EricLew	0:80ee8f3b695e	1194	* @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
EricLew	0:80ee8f3b695e	1195	* @retval None.
EricLew	0:80ee8f3b695e	1196	*/
EricLew	0:80ee8f3b695e	1197	#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1198
EricLew	0:80ee8f3b695e	1199
EricLew	0:80ee8f3b695e	1200	/**
EricLew	0:80ee8f3b695e	1201	* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
EricLew	0:80ee8f3b695e	1202	* @retval None.
EricLew	0:80ee8f3b695e	1203	*/
EricLew	0:80ee8f3b695e	1204	#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1205
EricLew	0:80ee8f3b695e	1206
EricLew	0:80ee8f3b695e	1207	/**
EricLew	0:80ee8f3b695e	1208	* @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
EricLew	0:80ee8f3b695e	1209	* @retval None.
EricLew	0:80ee8f3b695e	1210	*/
EricLew	0:80ee8f3b695e	1211	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1212
EricLew	0:80ee8f3b695e	1213	/**
EricLew	0:80ee8f3b695e	1214	* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
EricLew	0:80ee8f3b695e	1215	* @retval None.
EricLew	0:80ee8f3b695e	1216	*/
EricLew	0:80ee8f3b695e	1217	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1218
EricLew	0:80ee8f3b695e	1219	/**
EricLew	0:80ee8f3b695e	1220	* @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
EricLew	0:80ee8f3b695e	1221	* @retval None.
EricLew	0:80ee8f3b695e	1222	*/
EricLew	0:80ee8f3b695e	1223	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
EricLew	0:80ee8f3b695e	1224	do { \
EricLew	0:80ee8f3b695e	1225	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
EricLew	0:80ee8f3b695e	1226	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
EricLew	0:80ee8f3b695e	1227	} while(0)
EricLew	0:80ee8f3b695e	1228
EricLew	0:80ee8f3b695e	1229	/**
EricLew	0:80ee8f3b695e	1230	* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
EricLew	0:80ee8f3b695e	1231	* @retval None.
EricLew	0:80ee8f3b695e	1232	*/
EricLew	0:80ee8f3b695e	1233	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
EricLew	0:80ee8f3b695e	1234	do { \
EricLew	0:80ee8f3b695e	1235	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
EricLew	0:80ee8f3b695e	1236	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
EricLew	0:80ee8f3b695e	1237	} while(0)
EricLew	0:80ee8f3b695e	1238
EricLew	0:80ee8f3b695e	1239	/**
EricLew	0:80ee8f3b695e	1240	* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
EricLew	0:80ee8f3b695e	1241	* @retval EXTI RCC LSE CSS Line Status.
EricLew	0:80ee8f3b695e	1242	*/
EricLew	0:80ee8f3b695e	1243	#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1244
EricLew	0:80ee8f3b695e	1245	/**
EricLew	0:80ee8f3b695e	1246	* @brief Clear the RCC LSE CSS EXTI flag.
EricLew	0:80ee8f3b695e	1247	* @retval None.
EricLew	0:80ee8f3b695e	1248	*/
EricLew	0:80ee8f3b695e	1249	#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1250
EricLew	0:80ee8f3b695e	1251	/**
EricLew	0:80ee8f3b695e	1252	* @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
EricLew	0:80ee8f3b695e	1253	* @retval None.
EricLew	0:80ee8f3b695e	1254	*/
EricLew	0:80ee8f3b695e	1255	#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
EricLew	0:80ee8f3b695e	1256
EricLew	0:80ee8f3b695e	1257	/**
EricLew	0:80ee8f3b695e	1258	* @}
EricLew	0:80ee8f3b695e	1259	*/
EricLew	0:80ee8f3b695e	1260
EricLew	0:80ee8f3b695e	1261	/**
EricLew	0:80ee8f3b695e	1262	* @}
EricLew	0:80ee8f3b695e	1263	*/
EricLew	0:80ee8f3b695e	1264
EricLew	0:80ee8f3b695e	1265	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	1266	/** @addtogroup RCCEx_Exported_Functions
EricLew	0:80ee8f3b695e	1267	* @{
EricLew	0:80ee8f3b695e	1268	*/
EricLew	0:80ee8f3b695e	1269
EricLew	0:80ee8f3b695e	1270	/** @addtogroup RCCEx_Exported_Functions_Group1
EricLew	0:80ee8f3b695e	1271	* @{
EricLew	0:80ee8f3b695e	1272	*/
EricLew	0:80ee8f3b695e	1273
EricLew	0:80ee8f3b695e	1274	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
EricLew	0:80ee8f3b695e	1275	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
EricLew	0:80ee8f3b695e	1276	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
EricLew	0:80ee8f3b695e	1277
EricLew	0:80ee8f3b695e	1278	/**
EricLew	0:80ee8f3b695e	1279	* @}
EricLew	0:80ee8f3b695e	1280	*/
EricLew	0:80ee8f3b695e	1281
EricLew	0:80ee8f3b695e	1282	/** @addtogroup RCCEx_Exported_Functions_Group2
EricLew	0:80ee8f3b695e	1283	* @{
EricLew	0:80ee8f3b695e	1284	*/
EricLew	0:80ee8f3b695e	1285
EricLew	0:80ee8f3b695e	1286	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
EricLew	0:80ee8f3b695e	1287	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
EricLew	0:80ee8f3b695e	1288
EricLew	0:80ee8f3b695e	1289	#if defined(STM32L471xx) \|\| defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1290
EricLew	0:80ee8f3b695e	1291	HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init);
EricLew	0:80ee8f3b695e	1292	HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void);
EricLew	0:80ee8f3b695e	1293
EricLew	0:80ee8f3b695e	1294	#endif /* STM32L471xx \|\| STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1295
EricLew	0:80ee8f3b695e	1296	void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
EricLew	0:80ee8f3b695e	1297	void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange);
EricLew	0:80ee8f3b695e	1298	void HAL_RCCEx_EnableLSECSS(void);
EricLew	0:80ee8f3b695e	1299	void HAL_RCCEx_DisableLSECSS(void);
EricLew	0:80ee8f3b695e	1300	void HAL_RCCEx_EnableLSECSS_IT(void);
EricLew	0:80ee8f3b695e	1301	void HAL_RCCEx_LSECSS_IRQHandler(void);
EricLew	0:80ee8f3b695e	1302	void HAL_RCCEx_LSECSS_Callback(void);
EricLew	0:80ee8f3b695e	1303	void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
EricLew	0:80ee8f3b695e	1304	void HAL_RCCEx_DisableLSCO(void);
EricLew	0:80ee8f3b695e	1305	void HAL_RCCEx_EnableMSIPLLMode(void);
EricLew	0:80ee8f3b695e	1306	void HAL_RCCEx_DisableMSIPLLMode(void);
EricLew	0:80ee8f3b695e	1307
EricLew	0:80ee8f3b695e	1308	/**
EricLew	0:80ee8f3b695e	1309	* @}
EricLew	0:80ee8f3b695e	1310	*/
EricLew	0:80ee8f3b695e	1311
EricLew	0:80ee8f3b695e	1312	/**
EricLew	0:80ee8f3b695e	1313	* @}
EricLew	0:80ee8f3b695e	1314	*/
EricLew	0:80ee8f3b695e	1315
EricLew	0:80ee8f3b695e	1316	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	1317	/** @addtogroup RCCEx_Private_Macros
EricLew	0:80ee8f3b695e	1318	* @{
EricLew	0:80ee8f3b695e	1319	*/
EricLew	0:80ee8f3b695e	1320
EricLew	0:80ee8f3b695e	1321	#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) \|\| \
EricLew	0:80ee8f3b695e	1322	((__SOURCE__) == RCC_LSCOSOURCE_LSE))
EricLew	0:80ee8f3b695e	1323
EricLew	0:80ee8f3b695e	1324	#if defined(STM32L471xx)
EricLew	0:80ee8f3b695e	1325
EricLew	0:80ee8f3b695e	1326	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
EricLew	0:80ee8f3b695e	1327	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
EricLew	0:80ee8f3b695e	1328	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
EricLew	0:80ee8f3b695e	1329	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
EricLew	0:80ee8f3b695e	1330	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
EricLew	0:80ee8f3b695e	1331	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
EricLew	0:80ee8f3b695e	1332	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
EricLew	0:80ee8f3b695e	1333	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
EricLew	0:80ee8f3b695e	1334	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
EricLew	0:80ee8f3b695e	1335	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
EricLew	0:80ee8f3b695e	1336	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
EricLew	0:80ee8f3b695e	1337	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
EricLew	0:80ee8f3b695e	1338	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
EricLew	0:80ee8f3b695e	1339	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
EricLew	0:80ee8f3b695e	1340	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
EricLew	0:80ee8f3b695e	1341	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
EricLew	0:80ee8f3b695e	1342	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) \|\| \
EricLew	0:80ee8f3b695e	1343	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
EricLew	0:80ee8f3b695e	1344	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
EricLew	0:80ee8f3b695e	1345	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
EricLew	0:80ee8f3b695e	1346
EricLew	0:80ee8f3b695e	1347	#else /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1348
EricLew	0:80ee8f3b695e	1349	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
EricLew	0:80ee8f3b695e	1350	((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
EricLew	0:80ee8f3b695e	1351	(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
EricLew	0:80ee8f3b695e	1352	(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
EricLew	0:80ee8f3b695e	1353	(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
EricLew	0:80ee8f3b695e	1354	(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
EricLew	0:80ee8f3b695e	1355	(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) \|\| \
EricLew	0:80ee8f3b695e	1356	(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
EricLew	0:80ee8f3b695e	1357	(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
EricLew	0:80ee8f3b695e	1358	(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
EricLew	0:80ee8f3b695e	1359	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
EricLew	0:80ee8f3b695e	1360	(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) \|\| \
EricLew	0:80ee8f3b695e	1361	(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
EricLew	0:80ee8f3b695e	1362	(((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
EricLew	0:80ee8f3b695e	1363	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) \|\| \
EricLew	0:80ee8f3b695e	1364	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
EricLew	0:80ee8f3b695e	1365	(((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) \|\| \
EricLew	0:80ee8f3b695e	1366	(((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) \|\| \
EricLew	0:80ee8f3b695e	1367	(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
EricLew	0:80ee8f3b695e	1368	(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) \|\| \
EricLew	0:80ee8f3b695e	1369	(((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1))
EricLew	0:80ee8f3b695e	1370
EricLew	0:80ee8f3b695e	1371	#endif /* STM32L471xx */
EricLew	0:80ee8f3b695e	1372
EricLew	0:80ee8f3b695e	1373	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1374	(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
EricLew	0:80ee8f3b695e	1375	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1376	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1377	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1378
EricLew	0:80ee8f3b695e	1379	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1380	(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1381	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1382	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1383	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1384
EricLew	0:80ee8f3b695e	1385	#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1386	(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1387	((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1388	((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1389	((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1390
EricLew	0:80ee8f3b695e	1391	#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1392	(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1393	((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1394	((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1395	((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1396
EricLew	0:80ee8f3b695e	1397	#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1398	(((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1399	((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1400	((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1401	((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1402
EricLew	0:80ee8f3b695e	1403	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1404	(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1405	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
EricLew	0:80ee8f3b695e	1406	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
EricLew	0:80ee8f3b695e	1407	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1408
EricLew	0:80ee8f3b695e	1409	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1410	(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1411	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
EricLew	0:80ee8f3b695e	1412	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1413
EricLew	0:80ee8f3b695e	1414	#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1415	(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1416	((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
EricLew	0:80ee8f3b695e	1417	((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1418
EricLew	0:80ee8f3b695e	1419	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1420	(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
EricLew	0:80ee8f3b695e	1421	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
EricLew	0:80ee8f3b695e	1422	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1423
EricLew	0:80ee8f3b695e	1424	#define IS_RCC_SAI1CLK(__SOURCE__) \
EricLew	0:80ee8f3b695e	1425	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1426	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) \|\| \
EricLew	0:80ee8f3b695e	1427	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
EricLew	0:80ee8f3b695e	1428	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
EricLew	0:80ee8f3b695e	1429
EricLew	0:80ee8f3b695e	1430	#define IS_RCC_SAI2CLK(__SOURCE__) \
EricLew	0:80ee8f3b695e	1431	(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1432	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) \|\| \
EricLew	0:80ee8f3b695e	1433	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) \|\| \
EricLew	0:80ee8f3b695e	1434	((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
EricLew	0:80ee8f3b695e	1435
EricLew	0:80ee8f3b695e	1436	#define IS_RCC_LPTIM1CLK(__SOURCE__) \
EricLew	0:80ee8f3b695e	1437	(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
EricLew	0:80ee8f3b695e	1438	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
EricLew	0:80ee8f3b695e	1439	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
EricLew	0:80ee8f3b695e	1440	((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
EricLew	0:80ee8f3b695e	1441
EricLew	0:80ee8f3b695e	1442	#define IS_RCC_LPTIM2CLK(__SOURCE__) \
EricLew	0:80ee8f3b695e	1443	(((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) \|\| \
EricLew	0:80ee8f3b695e	1444	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) \|\| \
EricLew	0:80ee8f3b695e	1445	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) \|\| \
EricLew	0:80ee8f3b695e	1446	((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
EricLew	0:80ee8f3b695e	1447
EricLew	0:80ee8f3b695e	1448	#define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1449	(((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) \|\| \
EricLew	0:80ee8f3b695e	1450	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1451	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) \|\| \
EricLew	0:80ee8f3b695e	1452	((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI))
EricLew	0:80ee8f3b695e	1453
EricLew	0:80ee8f3b695e	1454	#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1455	(((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) \|\| \
EricLew	0:80ee8f3b695e	1456	((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1457	((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) \|\| \
EricLew	0:80ee8f3b695e	1458	((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
EricLew	0:80ee8f3b695e	1459
EricLew	0:80ee8f3b695e	1460	#if defined(STM32L475xx) \|\| defined(STM32L476xx) \|\| defined(STM32L485xx) \|\| defined(STM32L486xx)
EricLew	0:80ee8f3b695e	1461
EricLew	0:80ee8f3b695e	1462	#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1463	(((__SOURCE__) == RCC_USBCLKSOURCE_NONE) \|\| \
EricLew	0:80ee8f3b695e	1464	((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1465	((__SOURCE__) == RCC_USBCLKSOURCE_PLL) \|\| \
EricLew	0:80ee8f3b695e	1466	((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
EricLew	0:80ee8f3b695e	1467
EricLew	0:80ee8f3b695e	1468	#endif /* STM32L475xx \|\| STM32L476xx \|\| STM32L485xx \|\| STM32L486xx */
EricLew	0:80ee8f3b695e	1469
EricLew	0:80ee8f3b695e	1470	#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1471	(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) \|\| \
EricLew	0:80ee8f3b695e	1472	((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) \|\| \
EricLew	0:80ee8f3b695e	1473	((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) \|\| \
EricLew	0:80ee8f3b695e	1474	((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
EricLew	0:80ee8f3b695e	1475
EricLew	0:80ee8f3b695e	1476	#define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1477	(((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) \|\| \
EricLew	0:80ee8f3b695e	1478	((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI))
EricLew	0:80ee8f3b695e	1479
EricLew	0:80ee8f3b695e	1480	#define IS_RCC_DFSDMCLKSOURCE(__SOURCE__) \
EricLew	0:80ee8f3b695e	1481	(((__SOURCE__) == RCC_DFSDMCLKSOURCE_PCLK) \|\| \
EricLew	0:80ee8f3b695e	1482	((__SOURCE__) == RCC_DFSDMCLKSOURCE_SYSCLK))
EricLew	0:80ee8f3b695e	1483
EricLew	0:80ee8f3b695e	1484	#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
EricLew	0:80ee8f3b695e	1485
EricLew	0:80ee8f3b695e	1486	#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17))
EricLew	0:80ee8f3b695e	1487
EricLew	0:80ee8f3b695e	1488	#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
EricLew	0:80ee8f3b695e	1489	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
EricLew	0:80ee8f3b695e	1490
EricLew	0:80ee8f3b695e	1491	#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
EricLew	0:80ee8f3b695e	1492	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
EricLew	0:80ee8f3b695e	1493
EricLew	0:80ee8f3b695e	1494	#define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86))
EricLew	0:80ee8f3b695e	1495
EricLew	0:80ee8f3b695e	1496	#define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7) \|\| ((__VALUE__) == 17))
EricLew	0:80ee8f3b695e	1497
EricLew	0:80ee8f3b695e	1498	#define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2 ) \|\| ((__VALUE__) == 4) \|\| \
EricLew	0:80ee8f3b695e	1499	((__VALUE__) == 6) \|\| ((__VALUE__) == 8))
EricLew	0:80ee8f3b695e	1500
EricLew	0:80ee8f3b695e	1501
EricLew	0:80ee8f3b695e	1502	/**
EricLew	0:80ee8f3b695e	1503	* @}
EricLew	0:80ee8f3b695e	1504	*/
EricLew	0:80ee8f3b695e	1505
EricLew	0:80ee8f3b695e	1506	/**
EricLew	0:80ee8f3b695e	1507	* @}
EricLew	0:80ee8f3b695e	1508	*/
EricLew	0:80ee8f3b695e	1509
EricLew	0:80ee8f3b695e	1510	/**
EricLew	0:80ee8f3b695e	1511	* @}
EricLew	0:80ee8f3b695e	1512	*/
EricLew	0:80ee8f3b695e	1513
EricLew	0:80ee8f3b695e	1514	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	1515	}
EricLew	0:80ee8f3b695e	1516	#endif
EricLew	0:80ee8f3b695e	1517
EricLew	0:80ee8f3b695e	1518	#endif /* __STM32L4xx_HAL_RCC_EX_H */
EricLew	0:80ee8f3b695e	1519
EricLew	0:80ee8f3b695e	1520	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	1521

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_hal_rcc_ex.h@0:80ee8f3b695e, 2015-11-02 (annotated)

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