STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_tim.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

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User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_tim.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of TIM LL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_LL_TIM_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_LL_TIM_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	#if defined (TIM1) \|\| defined (TIM8) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM4) \|\| defined (TIM5) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	/** @defgroup TIM_LL TIM
EricLew	0:80ee8f3b695e	56	* @{
EricLew	0:80ee8f3b695e	57	*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	61	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
EricLew	0:80ee8f3b695e	62	* @{
EricLew	0:80ee8f3b695e	63	*/
EricLew	0:80ee8f3b695e	64	static const uint8_t OFFSET_TAB_CCMRx[] =
EricLew	0:80ee8f3b695e	65	{
EricLew	0:80ee8f3b695e	66	0x00, /* 0: TIMx_CH1 */
EricLew	0:80ee8f3b695e	67	0x00, /* 1: TIMx_CH1N */
EricLew	0:80ee8f3b695e	68	0x00, /* 2: TIMx_CH2 */
EricLew	0:80ee8f3b695e	69	0x00, /* 3: TIMx_CH2N */
EricLew	0:80ee8f3b695e	70	0x04, /* 4: TIMx_CH3 */
EricLew	0:80ee8f3b695e	71	0x04, /* 5: TIMx_CH3N */
EricLew	0:80ee8f3b695e	72	0x04, /* 6: TIMx_CH4 */
EricLew	0:80ee8f3b695e	73	0x3C, /* 7: TIMx_CH5 */
EricLew	0:80ee8f3b695e	74	0x3C /* 8: TIMx_CH6 */
EricLew	0:80ee8f3b695e	75	};
EricLew	0:80ee8f3b695e	76
EricLew	0:80ee8f3b695e	77	static const uint8_t SHIFT_TAB_OCxx[] =
EricLew	0:80ee8f3b695e	78	{
EricLew	0:80ee8f3b695e	79	0, /* 0: OC1M, OC1FE, OC1PE */
EricLew	0:80ee8f3b695e	80	0, /* 1: - NA */
EricLew	0:80ee8f3b695e	81	8, /* 2: OC2M, OC2FE, OC2PE */
EricLew	0:80ee8f3b695e	82	0, /* 3: - NA */
EricLew	0:80ee8f3b695e	83	0, /* 4: OC3M, OC3FE, OC3PE */
EricLew	0:80ee8f3b695e	84	0, /* 5: - NA */
EricLew	0:80ee8f3b695e	85	8, /* 6: OC4M, OC4FE, OC4PE */
EricLew	0:80ee8f3b695e	86	0, /* 7: OC5M, OC5FE, OC5PE */
EricLew	0:80ee8f3b695e	87	8 /* 8: OC6M, OC6FE, OC6PE */
EricLew	0:80ee8f3b695e	88	};
EricLew	0:80ee8f3b695e	89
EricLew	0:80ee8f3b695e	90	static const uint8_t SHIFT_TAB_ICxx[] =
EricLew	0:80ee8f3b695e	91	{
EricLew	0:80ee8f3b695e	92	0, /* 0: CC1S, IC1PSC, IC1F */
EricLew	0:80ee8f3b695e	93	0, /* 1: - NA */
EricLew	0:80ee8f3b695e	94	8, /* 2: CC2S, IC2PSC, IC2F */
EricLew	0:80ee8f3b695e	95	0, /* 3: - NA */
EricLew	0:80ee8f3b695e	96	0, /* 4: CC3S, IC3PSC, IC3F */
EricLew	0:80ee8f3b695e	97	0, /* 5: - NA */
EricLew	0:80ee8f3b695e	98	8, /* 6: CC4S, IC4PSC, IC4F */
EricLew	0:80ee8f3b695e	99	0, /* 7: - NA */
EricLew	0:80ee8f3b695e	100	0 /* 8: - NA */
EricLew	0:80ee8f3b695e	101	};
EricLew	0:80ee8f3b695e	102
EricLew	0:80ee8f3b695e	103	static const uint8_t SHIFT_TAB_CCxP[] =
EricLew	0:80ee8f3b695e	104	{
EricLew	0:80ee8f3b695e	105	0, /* 0: CC1P */
EricLew	0:80ee8f3b695e	106	2, /* 1: CC1NP */
EricLew	0:80ee8f3b695e	107	4, /* 2: CC2P */
EricLew	0:80ee8f3b695e	108	6, /* 3: CC2NP */
EricLew	0:80ee8f3b695e	109	8, /* 4: CC3P */
EricLew	0:80ee8f3b695e	110	10, /* 5: CC3NP */
EricLew	0:80ee8f3b695e	111	12, /* 6: CC4P */
EricLew	0:80ee8f3b695e	112	16, /* 7: CC5P */
EricLew	0:80ee8f3b695e	113	20 /* 8: CC6P */
EricLew	0:80ee8f3b695e	114	};
EricLew	0:80ee8f3b695e	115
EricLew	0:80ee8f3b695e	116	static const uint8_t SHIFT_TAB_OISx[] =
EricLew	0:80ee8f3b695e	117	{
EricLew	0:80ee8f3b695e	118	0, /* 0: OIS1 */
EricLew	0:80ee8f3b695e	119	1, /* 1: OIS1N */
EricLew	0:80ee8f3b695e	120	2, /* 2: OIS2 */
EricLew	0:80ee8f3b695e	121	3, /* 3: OIS2N */
EricLew	0:80ee8f3b695e	122	4, /* 4: OIS3 */
EricLew	0:80ee8f3b695e	123	5, /* 5: OIS3N */
EricLew	0:80ee8f3b695e	124	6, /* 6: OIS4 */
EricLew	0:80ee8f3b695e	125	8, /* 7: OIS5 */
EricLew	0:80ee8f3b695e	126	10 /* 8: OIS6 */
EricLew	0:80ee8f3b695e	127	};
EricLew	0:80ee8f3b695e	128	/**
EricLew	0:80ee8f3b695e	129	* @}
EricLew	0:80ee8f3b695e	130	*/
EricLew	0:80ee8f3b695e	131
EricLew	0:80ee8f3b695e	132
EricLew	0:80ee8f3b695e	133	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	134	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
EricLew	0:80ee8f3b695e	135	* @{
EricLew	0:80ee8f3b695e	136	*/
EricLew	0:80ee8f3b695e	137	/* Generic bit definitions for TIMx_OR2 register */
EricLew	0:80ee8f3b695e	138	#define TIMx_OR2_BKINE TIM1_OR2_BKINE /!< BRK BKIN input enable /
EricLew	0:80ee8f3b695e	139	#define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /!< BRK COMP1 enable /
EricLew	0:80ee8f3b695e	140	#define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /!< BRK COMP2 enable /
EricLew	0:80ee8f3b695e	141	#define TIMx_OR2_BKDFBK0E TIM1_OR2_BKDFBK0E /!< BRK DFSDM_BREAK[0] enable /
EricLew	0:80ee8f3b695e	142	#define TIMx_OR2_BKINP TIM1_OR2_BKINP /!< BRK BKIN input polarity /
EricLew	0:80ee8f3b695e	143	#define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /!< BRK COMP1 input polarity /
EricLew	0:80ee8f3b695e	144	#define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /!< BRK COMP2 input polarity /
EricLew	0:80ee8f3b695e	145	#define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /!< TIMx ETR source selection /
EricLew	0:80ee8f3b695e	146
EricLew	0:80ee8f3b695e	147	/* Generic bit definitions for TIMx_OR3 register */
EricLew	0:80ee8f3b695e	148	#define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /!< BRK2 BKIN2 input enable /
EricLew	0:80ee8f3b695e	149	#define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /!< BRK2 COMP1 enable /
EricLew	0:80ee8f3b695e	150	#define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /!< BRK2 COMP2 enable /
EricLew	0:80ee8f3b695e	151	#define TIMx_OR3_BK2DFBK1E TIM1_OR3_BK2DFBK1E /!< BRK2 DFSDM_BREAK[1] enable /
EricLew	0:80ee8f3b695e	152	#define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /!< BRK2 BKIN2 input polarity /
EricLew	0:80ee8f3b695e	153	#define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /!< BRK2 COMP1 input polarity /
EricLew	0:80ee8f3b695e	154	#define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /!< BRK2 COMP2 input polarity /
EricLew	0:80ee8f3b695e	155
EricLew	0:80ee8f3b695e	156	/* Remap mask definitions */
EricLew	0:80ee8f3b695e	157	#define TIMx_OR1_RMP_SHIFT ((uint32_t)16)
EricLew	0:80ee8f3b695e	158	#define TIMx_OR1_RMP_MASK ((uint32_t)0x0000FFFF)
EricLew	0:80ee8f3b695e	159	#define TIM1_OR1_RMP_MASK ((uint32_t)((TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	160	#define TIM2_OR1_RMP_MASK ((uint32_t)((TIM2_OR1_TI4_RMP \| TIM2_OR1_ETR1_RMP \| TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	161	#define TIM3_OR1_RMP_MASK ((uint32_t)(TIM3_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT)
EricLew	0:80ee8f3b695e	162	#define TIM8_OR1_RMP_MASK ((uint32_t)((TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	163	#define TIM15_OR1_RMP_MASK ((uint32_t)((TIM15_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	164	#define TIM16_OR1_RMP_MASK ((uint32_t)((TIM16_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	165	#define TIM17_OR1_RMP_MASK ((uint32_t)((TIM17_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT))
EricLew	0:80ee8f3b695e	166
EricLew	0:80ee8f3b695e	167	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
EricLew	0:80ee8f3b695e	168	#define DT_DELAY_1 ((uint8_t)0x7F)
EricLew	0:80ee8f3b695e	169	#define DT_DELAY_2 ((uint8_t)0x3F)
EricLew	0:80ee8f3b695e	170	#define DT_DELAY_3 ((uint8_t)0x1F)
EricLew	0:80ee8f3b695e	171	#define DT_DELAY_4 ((uint8_t)0x1F)
EricLew	0:80ee8f3b695e	172
EricLew	0:80ee8f3b695e	173	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
EricLew	0:80ee8f3b695e	174	#define DT_RANGE_1 ((uint8_t)0x00)
EricLew	0:80ee8f3b695e	175	#define DT_RANGE_2 ((uint8_t)0x80)
EricLew	0:80ee8f3b695e	176	#define DT_RANGE_3 ((uint8_t)0xC0)
EricLew	0:80ee8f3b695e	177	#define DT_RANGE_4 ((uint8_t)0xE0)
EricLew	0:80ee8f3b695e	178	/**
EricLew	0:80ee8f3b695e	179	* @}
EricLew	0:80ee8f3b695e	180	*/
EricLew	0:80ee8f3b695e	181
EricLew	0:80ee8f3b695e	182
EricLew	0:80ee8f3b695e	183	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	184	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
EricLew	0:80ee8f3b695e	185	* @{
EricLew	0:80ee8f3b695e	186	*/
EricLew	0:80ee8f3b695e	187	/** @brief Convert channel id into channel index
EricLew	0:80ee8f3b695e	188	* @param __CHANNEL__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	189	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	190	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	191	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	192	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	193	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	194	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	195	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	196	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	197	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	198	* @retval none
EricLew	0:80ee8f3b695e	199	*/
EricLew	0:80ee8f3b695e	200	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
EricLew	0:80ee8f3b695e	201	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0 :\
EricLew	0:80ee8f3b695e	202	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1 :\
EricLew	0:80ee8f3b695e	203	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2 :\
EricLew	0:80ee8f3b695e	204	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3 :\
EricLew	0:80ee8f3b695e	205	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4 :\
EricLew	0:80ee8f3b695e	206	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5 :\
EricLew	0:80ee8f3b695e	207	((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6 :\
EricLew	0:80ee8f3b695e	208	((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7 : 8)
EricLew	0:80ee8f3b695e	209
EricLew	0:80ee8f3b695e	210	/** @brief Calculate the deadtime sampling period(in ps)
EricLew	0:80ee8f3b695e	211	* @param __TIMCLK__: timer input clock frequency (in Hz).
EricLew	0:80ee8f3b695e	212	* @param __CKD__: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	213	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
EricLew	0:80ee8f3b695e	214	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
EricLew	0:80ee8f3b695e	215	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
EricLew	0:80ee8f3b695e	216	* @retval none
EricLew	0:80ee8f3b695e	217	*/
EricLew	0:80ee8f3b695e	218	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
EricLew	0:80ee8f3b695e	219	(((int)(__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000/(__TIMCLK__)) : \
EricLew	0:80ee8f3b695e	220	((int)(__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000/((__TIMCLK__) >> 1)) : \
EricLew	0:80ee8f3b695e	221	((uint64_t)1000000000000/((__TIMCLK__) >> 2)))
EricLew	0:80ee8f3b695e	222	/**
EricLew	0:80ee8f3b695e	223	* @}
EricLew	0:80ee8f3b695e	224	*/
EricLew	0:80ee8f3b695e	225
EricLew	0:80ee8f3b695e	226
EricLew	0:80ee8f3b695e	227	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	228	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	229	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
EricLew	0:80ee8f3b695e	230	* @{
EricLew	0:80ee8f3b695e	231	*/
EricLew	0:80ee8f3b695e	232
EricLew	0:80ee8f3b695e	233	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
EricLew	0:80ee8f3b695e	234	* @brief Flags defines which can be used with LL_TIM_ReadReg function
EricLew	0:80ee8f3b695e	235	* @{
EricLew	0:80ee8f3b695e	236	*/
EricLew	0:80ee8f3b695e	237	#define LL_TIM_SR_UIF TIM_SR_UIF
EricLew	0:80ee8f3b695e	238	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF
EricLew	0:80ee8f3b695e	239	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF
EricLew	0:80ee8f3b695e	240	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF
EricLew	0:80ee8f3b695e	241	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF
EricLew	0:80ee8f3b695e	242	#define LL_TIM_SR_CC5IF TIM_SR_CC5IF
EricLew	0:80ee8f3b695e	243	#define LL_TIM_SR_CC6IF TIM_SR_CC6IF
EricLew	0:80ee8f3b695e	244	#define LL_TIM_SR_COMIF TIM_SR_COMIF
EricLew	0:80ee8f3b695e	245	#define LL_TIM_SR_TIF TIM_SR_TIF
EricLew	0:80ee8f3b695e	246	#define LL_TIM_SR_BIF TIM_SR_BIF
EricLew	0:80ee8f3b695e	247	#define LL_TIM_SR_B2IF TIM_SR_B2IF
EricLew	0:80ee8f3b695e	248	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF
EricLew	0:80ee8f3b695e	249	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF
EricLew	0:80ee8f3b695e	250	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF
EricLew	0:80ee8f3b695e	251	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF
EricLew	0:80ee8f3b695e	252	#define LL_TIM_SR_SBIF TIM_SR_SBIF
EricLew	0:80ee8f3b695e	253	/**
EricLew	0:80ee8f3b695e	254	* @}
EricLew	0:80ee8f3b695e	255	*/
EricLew	0:80ee8f3b695e	256
EricLew	0:80ee8f3b695e	257	/** @defgroup TIM_LL_EC_IT IT Defines
EricLew	0:80ee8f3b695e	258	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions
EricLew	0:80ee8f3b695e	259	* @{
EricLew	0:80ee8f3b695e	260	*/
EricLew	0:80ee8f3b695e	261	#define LL_TIM_DIER_UIE TIM_DIER_UIE
EricLew	0:80ee8f3b695e	262	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE
EricLew	0:80ee8f3b695e	263	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE
EricLew	0:80ee8f3b695e	264	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE
EricLew	0:80ee8f3b695e	265	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE
EricLew	0:80ee8f3b695e	266	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE
EricLew	0:80ee8f3b695e	267	#define LL_TIM_DIER_TIE TIM_DIER_TIE
EricLew	0:80ee8f3b695e	268	#define LL_TIM_DIER_BIE TIM_DIER_BIE
EricLew	0:80ee8f3b695e	269	/**
EricLew	0:80ee8f3b695e	270	* @}
EricLew	0:80ee8f3b695e	271	*/
EricLew	0:80ee8f3b695e	272
EricLew	0:80ee8f3b695e	273	/** @defgroup TIM_LL_EC_UPDATESOURCE UPDATESOURCE
EricLew	0:80ee8f3b695e	274	* @{
EricLew	0:80ee8f3b695e	275	*/
EricLew	0:80ee8f3b695e	276	#define LL_TIM_UPDATESOURCE_REGULAR ((uint32_t)0x00000000) /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
EricLew	0:80ee8f3b695e	277	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
EricLew	0:80ee8f3b695e	278	/**
EricLew	0:80ee8f3b695e	279	* @}
EricLew	0:80ee8f3b695e	280	*/
EricLew	0:80ee8f3b695e	281
EricLew	0:80ee8f3b695e	282	/** @defgroup TIM_LL_EC_ONEPULSEMODE ONEPULSEMODE
EricLew	0:80ee8f3b695e	283	* @{
EricLew	0:80ee8f3b695e	284	*/
EricLew	0:80ee8f3b695e	285	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
EricLew	0:80ee8f3b695e	286	#define LL_TIM_ONEPULSEMODE_REPETITIVE ((uint32_t)0x00000000) /!< Counter stops counting at the next update event /
EricLew	0:80ee8f3b695e	287	/**
EricLew	0:80ee8f3b695e	288	* @}
EricLew	0:80ee8f3b695e	289	*/
EricLew	0:80ee8f3b695e	290
EricLew	0:80ee8f3b695e	291	/** @defgroup TIM_LL_EC_COUNTERMODE COUNTERMODE
EricLew	0:80ee8f3b695e	292	* @{
EricLew	0:80ee8f3b695e	293	*/
EricLew	0:80ee8f3b695e	294	#define LL_TIM_COUNTERMODE_UP ((uint32_t)0x00000000)/!<Counter used as upcounter /
EricLew	0:80ee8f3b695e	295	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
EricLew	0:80ee8f3b695e	296	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
EricLew	0:80ee8f3b695e	297	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
EricLew	0:80ee8f3b695e	298	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
EricLew	0:80ee8f3b695e	299	/**
EricLew	0:80ee8f3b695e	300	* @}
EricLew	0:80ee8f3b695e	301	*/
EricLew	0:80ee8f3b695e	302
EricLew	0:80ee8f3b695e	303	/** @defgroup TIM_LL_EC_CLOCKDIVISION CLOCKDIVISION
EricLew	0:80ee8f3b695e	304	* @{
EricLew	0:80ee8f3b695e	305	*/
EricLew	0:80ee8f3b695e	306	#define LL_TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x00000000) /!< tDTS=tCK_INT /
EricLew	0:80ee8f3b695e	307	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
EricLew	0:80ee8f3b695e	308	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
EricLew	0:80ee8f3b695e	309	/**
EricLew	0:80ee8f3b695e	310	* @}
EricLew	0:80ee8f3b695e	311	*/
EricLew	0:80ee8f3b695e	312
EricLew	0:80ee8f3b695e	313	/** @defgroup TIM_LL_EC_COUNTERDIRECTION COUNTERDIRECTION
EricLew	0:80ee8f3b695e	314	* @{
EricLew	0:80ee8f3b695e	315	*/
EricLew	0:80ee8f3b695e	316	#define LL_TIM_COUNTERDIRECTION_UP ((uint32_t)0x00000000) /!< Timer counter counts up /
EricLew	0:80ee8f3b695e	317	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
EricLew	0:80ee8f3b695e	318	/**
EricLew	0:80ee8f3b695e	319	* @}
EricLew	0:80ee8f3b695e	320	*/
EricLew	0:80ee8f3b695e	321
EricLew	0:80ee8f3b695e	322	/** @defgroup TIM_LL_EC_CCUPDATESOURCE CCUPDATESOURCE
EricLew	0:80ee8f3b695e	323	* @{
EricLew	0:80ee8f3b695e	324	*/
EricLew	0:80ee8f3b695e	325	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY ((uint32_t)0x00000000) /!< Capture/compare control bits are updated by setting the COMG bit only /
EricLew	0:80ee8f3b695e	326	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
EricLew	0:80ee8f3b695e	327	/**
EricLew	0:80ee8f3b695e	328	* @}
EricLew	0:80ee8f3b695e	329	*/
EricLew	0:80ee8f3b695e	330
EricLew	0:80ee8f3b695e	331	/** @defgroup TIM_LL_EC_CCDMAREQUEST CCDMAREQUEST
EricLew	0:80ee8f3b695e	332	* @{
EricLew	0:80ee8f3b695e	333	*/
EricLew	0:80ee8f3b695e	334	#define LL_TIM_CCDMAREQUEST_CC ((uint32_t)0x00000000) /!< CCx DMA request sent when CCx event occurs /
EricLew	0:80ee8f3b695e	335	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
EricLew	0:80ee8f3b695e	336	/**
EricLew	0:80ee8f3b695e	337	* @}
EricLew	0:80ee8f3b695e	338	*/
EricLew	0:80ee8f3b695e	339
EricLew	0:80ee8f3b695e	340	/** @defgroup TIM_LL_EC_LOCKLEVEL LOCKLEVEL
EricLew	0:80ee8f3b695e	341	* @{
EricLew	0:80ee8f3b695e	342	*/
EricLew	0:80ee8f3b695e	343	#define LL_TIM_LOCKLEVEL_OFF ((uint32_t)0x00000000) /!< LOCK OFF - No bit is write protected /
EricLew	0:80ee8f3b695e	344	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
EricLew	0:80ee8f3b695e	345	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
EricLew	0:80ee8f3b695e	346	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
EricLew	0:80ee8f3b695e	347	/**
EricLew	0:80ee8f3b695e	348	* @}
EricLew	0:80ee8f3b695e	349	*/
EricLew	0:80ee8f3b695e	350
EricLew	0:80ee8f3b695e	351	/** @defgroup TIM_LL_EC_CHANNEL CHANNEL
EricLew	0:80ee8f3b695e	352	* @{
EricLew	0:80ee8f3b695e	353	*/
EricLew	0:80ee8f3b695e	354	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
EricLew	0:80ee8f3b695e	355	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
EricLew	0:80ee8f3b695e	356	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
EricLew	0:80ee8f3b695e	357	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
EricLew	0:80ee8f3b695e	358	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
EricLew	0:80ee8f3b695e	359	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
EricLew	0:80ee8f3b695e	360	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
EricLew	0:80ee8f3b695e	361	#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /!< Timer output channel 5 /
EricLew	0:80ee8f3b695e	362	#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /!< Timer output channel 6 /
EricLew	0:80ee8f3b695e	363	/**
EricLew	0:80ee8f3b695e	364	* @}
EricLew	0:80ee8f3b695e	365	*/
EricLew	0:80ee8f3b695e	366
EricLew	0:80ee8f3b695e	367	/** @defgroup TIM_LL_EC_OCMODE OCMODE
EricLew	0:80ee8f3b695e	368	* @{
EricLew	0:80ee8f3b695e	369	*/
EricLew	0:80ee8f3b695e	370	#define LL_TIM_OCMODE_FROZEN ((uint32_t)0x00000000) /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
EricLew	0:80ee8f3b695e	371	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
EricLew	0:80ee8f3b695e	372	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
EricLew	0:80ee8f3b695e	373	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
EricLew	0:80ee8f3b695e	374	#define LL_TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) /!<OCyREF is forced low/
EricLew	0:80ee8f3b695e	375	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
EricLew	0:80ee8f3b695e	376	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
EricLew	0:80ee8f3b695e	377	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
EricLew	0:80ee8f3b695e	378	#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /!<Retrigerrable OPM mode 1/
EricLew	0:80ee8f3b695e	379	#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0) /!<Retrigerrable OPM mode 2/
EricLew	0:80ee8f3b695e	380	#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 1/
EricLew	0:80ee8f3b695e	381	#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2) /!<Combined PWM mode 2/
EricLew	0:80ee8f3b695e	382	#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2) /!<Asymmetric PWM mode 1/
EricLew	0:80ee8f3b695e	383	#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 \| TIM_CCMR1_OC1M) /!<Asymmetric PWM mode 2/
EricLew	0:80ee8f3b695e	384	/**
EricLew	0:80ee8f3b695e	385	* @}
EricLew	0:80ee8f3b695e	386	*/
EricLew	0:80ee8f3b695e	387
EricLew	0:80ee8f3b695e	388	/** @defgroup TIM_LL_EC_OCPOLARITY OCPOLARITY
EricLew	0:80ee8f3b695e	389	* @{
EricLew	0:80ee8f3b695e	390	*/
EricLew	0:80ee8f3b695e	391	#define LL_TIM_OCPOLARITY_HIGH ((uint32_t)0x00000000) /!< OCx active high/
EricLew	0:80ee8f3b695e	392	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!<OCxactive low/
EricLew	0:80ee8f3b695e	393	/**
EricLew	0:80ee8f3b695e	394	* @}
EricLew	0:80ee8f3b695e	395	*/
EricLew	0:80ee8f3b695e	396
EricLew	0:80ee8f3b695e	397	/** @defgroup TIM_LL_EC_OCIDLESTATE OCIDLESTATE
EricLew	0:80ee8f3b695e	398	* @{
EricLew	0:80ee8f3b695e	399	*/
EricLew	0:80ee8f3b695e	400	#define LL_TIM_OCIDLESTATE_LOW ((uint32_t)0x00000000) /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
EricLew	0:80ee8f3b695e	401	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
EricLew	0:80ee8f3b695e	402	/**
EricLew	0:80ee8f3b695e	403	* @}
EricLew	0:80ee8f3b695e	404	*/
EricLew	0:80ee8f3b695e	405
EricLew	0:80ee8f3b695e	406	/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
EricLew	0:80ee8f3b695e	407	* @{
EricLew	0:80ee8f3b695e	408	*/
EricLew	0:80ee8f3b695e	409	#define LL_TIM_GROUPCH5_NONE (uint32_t)0x00000000 /!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC /
EricLew	0:80ee8f3b695e	410	#define LL_TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /!< OC1REFC is the logical AND of OC1REFC and OC5REF /
EricLew	0:80ee8f3b695e	411	#define LL_TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /!< OC2REFC is the logical AND of OC2REFC and OC5REF /
EricLew	0:80ee8f3b695e	412	#define LL_TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /!< OC3REFC is the logical AND of OC3REFC and OC5REF /
EricLew	0:80ee8f3b695e	413	/**
EricLew	0:80ee8f3b695e	414	* @}
EricLew	0:80ee8f3b695e	415	*/
EricLew	0:80ee8f3b695e	416
EricLew	0:80ee8f3b695e	417	/** @defgroup TIM_LL_EC_ACTIVEINPUT ACTIVEINPUT
EricLew	0:80ee8f3b695e	418	* @{
EricLew	0:80ee8f3b695e	419	*/
EricLew	0:80ee8f3b695e	420	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16) /!< ICx is mapped on TIx /
EricLew	0:80ee8f3b695e	421	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16) /!< ICx is mapped on TIy /
EricLew	0:80ee8f3b695e	422	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16) /!< ICx is mapped on TRC /
EricLew	0:80ee8f3b695e	423	/**
EricLew	0:80ee8f3b695e	424	* @}
EricLew	0:80ee8f3b695e	425	*/
EricLew	0:80ee8f3b695e	426
EricLew	0:80ee8f3b695e	427	/** @defgroup TIM_LL_EC_ICPSC ICPSC
EricLew	0:80ee8f3b695e	428	* @{
EricLew	0:80ee8f3b695e	429	*/
EricLew	0:80ee8f3b695e	430	#define LL_TIM_ICPSC_DIV1 ((uint32_t)0x00000000) /!< No prescaler, capture is done each time an edge is detected on the capture input /
EricLew	0:80ee8f3b695e	431	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16) /!< Capture is done once every 2 events /
EricLew	0:80ee8f3b695e	432	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16) /!< Capture is done once every 4 events /
EricLew	0:80ee8f3b695e	433	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16) /!< Capture is done once every 8 events /
EricLew	0:80ee8f3b695e	434	/**
EricLew	0:80ee8f3b695e	435	* @}
EricLew	0:80ee8f3b695e	436	*/
EricLew	0:80ee8f3b695e	437
EricLew	0:80ee8f3b695e	438	/** @defgroup TIM_LL_EC_IC_FILTER IC FILTER
EricLew	0:80ee8f3b695e	439	* @{
EricLew	0:80ee8f3b695e	440	*/
EricLew	0:80ee8f3b695e	441	#define LL_TIM_IC_FILTER_FDIV1 ((uint32_t)0x00000000) /!< No filter, sampling is done at fDTS /
EricLew	0:80ee8f3b695e	442	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16) /!< fSAMPLING=fCK_INT, N=2 /
EricLew	0:80ee8f3b695e	443	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16) /!< fSAMPLING=fCK_INT, N=4 /
EricLew	0:80ee8f3b695e	444	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fCK_INT, N=8 /
EricLew	0:80ee8f3b695e	445	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16) /!< fSAMPLING=fDTS/2, N=6 /
EricLew	0:80ee8f3b695e	446	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fDTS/2, N=8 /
EricLew	0:80ee8f3b695e	447	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16) /!< fSAMPLING=fDTS/4, N=6 /
EricLew	0:80ee8f3b695e	448	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fDTS/4, N=8 /
EricLew	0:80ee8f3b695e	449	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16) /!< fSAMPLING=fDTS/8, N=6 /
EricLew	0:80ee8f3b695e	450	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fDTS/8, N=8 /
EricLew	0:80ee8f3b695e	451	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16) /!< fSAMPLING=fDTS/16, N=5 /
EricLew	0:80ee8f3b695e	452	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fDTS/16, N=6 /
EricLew	0:80ee8f3b695e	453	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16) /!< fSAMPLING=fDTS/16, N=8 /
EricLew	0:80ee8f3b695e	454	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16) /!< fSAMPLING=fDTS/32, N=5 /
EricLew	0:80ee8f3b695e	455	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16) /!< fSAMPLING=fDTS/32, N=6 /
EricLew	0:80ee8f3b695e	456	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16) /!< fSAMPLING=fDTS/32, N=8 /
EricLew	0:80ee8f3b695e	457	/**
EricLew	0:80ee8f3b695e	458	* @}
EricLew	0:80ee8f3b695e	459	*/
EricLew	0:80ee8f3b695e	460
EricLew	0:80ee8f3b695e	461	/** @defgroup TIM_LL_EC_IC_POLARITY IC POLARITY
EricLew	0:80ee8f3b695e	462	* @{
EricLew	0:80ee8f3b695e	463	*/
EricLew	0:80ee8f3b695e	464	#define LL_TIM_IC_POLARITY_RISING ((uint32_t)0x00000000) /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
EricLew	0:80ee8f3b695e	465	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
EricLew	0:80ee8f3b695e	466	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
EricLew	0:80ee8f3b695e	467	/**
EricLew	0:80ee8f3b695e	468	* @}
EricLew	0:80ee8f3b695e	469	*/
EricLew	0:80ee8f3b695e	470
EricLew	0:80ee8f3b695e	471	/** @defgroup TIM_LL_EC_CLOCKSOURCE CLOCKSOURCE
EricLew	0:80ee8f3b695e	472	* @{
EricLew	0:80ee8f3b695e	473	*/
EricLew	0:80ee8f3b695e	474	#define LL_TIM_CLOCKSOURCE_INTERNAL ((uint32_t)0x00000000) /!< The timer is clocked by the internal clock provided from the RCC /
EricLew	0:80ee8f3b695e	475	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0 ) /!< Counter counts at each rising or falling edge on a selected inpu t/
EricLew	0:80ee8f3b695e	476	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
EricLew	0:80ee8f3b695e	477	/**
EricLew	0:80ee8f3b695e	478	* @}
EricLew	0:80ee8f3b695e	479	*/
EricLew	0:80ee8f3b695e	480
EricLew	0:80ee8f3b695e	481	/** @defgroup TIM_LL_EC_ENCODERMODE_X2 ENCODERMODE X2
EricLew	0:80ee8f3b695e	482	* @{
EricLew	0:80ee8f3b695e	483	*/
EricLew	0:80ee8f3b695e	484	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
EricLew	0:80ee8f3b695e	485	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
EricLew	0:80ee8f3b695e	486	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
EricLew	0:80ee8f3b695e	487	/**
EricLew	0:80ee8f3b695e	488	* @}
EricLew	0:80ee8f3b695e	489	*/
EricLew	0:80ee8f3b695e	490
EricLew	0:80ee8f3b695e	491	/** @defgroup TIM_LL_EC_TRGO TRGO
EricLew	0:80ee8f3b695e	492	* @{
EricLew	0:80ee8f3b695e	493	*/
EricLew	0:80ee8f3b695e	494	#define LL_TIM_TRGO_RESET ((uint32_t)0x00000000) /!< UG bit from the TIMx_EGR register is used as trigger output /
EricLew	0:80ee8f3b695e	495	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
EricLew	0:80ee8f3b695e	496	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
EricLew	0:80ee8f3b695e	497	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is usd as trigger output /
EricLew	0:80ee8f3b695e	498	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
EricLew	0:80ee8f3b695e	499	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
EricLew	0:80ee8f3b695e	500	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
EricLew	0:80ee8f3b695e	501	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
EricLew	0:80ee8f3b695e	502	/**
EricLew	0:80ee8f3b695e	503	* @}
EricLew	0:80ee8f3b695e	504	*/
EricLew	0:80ee8f3b695e	505
EricLew	0:80ee8f3b695e	506	/** @defgroup TIM_LL_EC_TRGO2 TRGO2
EricLew	0:80ee8f3b695e	507	* @{
EricLew	0:80ee8f3b695e	508	*/
EricLew	0:80ee8f3b695e	509	#define LL_TIM_TRGO2_RESET ((uint32_t)0x00000000) /!< UG bit from the TIMx_EGR register is used as trigger output 2 /
EricLew	0:80ee8f3b695e	510	#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /!< Counter Enable signal (CNT_EN) is used as trigger output 2 /
EricLew	0:80ee8f3b695e	511	#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /!< Update event is used as trigger output 2 /
EricLew	0:80ee8f3b695e	512	#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< CC1 capture or a compare match is used as trigger output 2 /
EricLew	0:80ee8f3b695e	513	#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /!< OC1REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	514	#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC2REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	515	#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1) /!< OC3REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	516	#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC4REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	517	#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /!< OC5REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	518	#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_0) /!< OC6REF signal is used as trigger output 2 /
EricLew	0:80ee8f3b695e	519	#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1) /!< OC4REF rising or falling edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	520	#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC6REF rising or falling edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	521	#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2) /!< OC4REF or OC6REF rising edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	522	#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_0) /!< OC4REF rising or OC6REF falling edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	523	#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \|TIM_CR2_MMS2_1) /!< OC5REF or OC6REF rising edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	524	#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 \| TIM_CR2_MMS2_2 \| TIM_CR2_MMS2_1 \| TIM_CR2_MMS2_0) /!< OC5REF rising or OC6REF falling edges are used as trigger output 2 /
EricLew	0:80ee8f3b695e	525	/**
EricLew	0:80ee8f3b695e	526	* @}
EricLew	0:80ee8f3b695e	527	*/
EricLew	0:80ee8f3b695e	528
EricLew	0:80ee8f3b695e	529	/** @defgroup TIM_LL_EC_SLAVEMODE SLAVEMODE
EricLew	0:80ee8f3b695e	530	* @{
EricLew	0:80ee8f3b695e	531	*/
EricLew	0:80ee8f3b695e	532	#define LL_TIM_SLAVEMODE_DISABLED ((uint32_t)0x00000000) /!< Slave mode disabled /
EricLew	0:80ee8f3b695e	533	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
EricLew	0:80ee8f3b695e	534	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
EricLew	0:80ee8f3b695e	535	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
EricLew	0:80ee8f3b695e	536	#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter /
EricLew	0:80ee8f3b695e	537	/**
EricLew	0:80ee8f3b695e	538	* @}
EricLew	0:80ee8f3b695e	539	*/
EricLew	0:80ee8f3b695e	540
EricLew	0:80ee8f3b695e	541	/** @defgroup TIM_LL_EC_TS TS
EricLew	0:80ee8f3b695e	542	* @{
EricLew	0:80ee8f3b695e	543	*/
EricLew	0:80ee8f3b695e	544	#define LL_TIM_TS_ITR0 ((uint32_t)0x00000000) /!< Internal Trigger 0 (ITR0) is used as trigger input /
EricLew	0:80ee8f3b695e	545	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
EricLew	0:80ee8f3b695e	546	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
EricLew	0:80ee8f3b695e	547	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
EricLew	0:80ee8f3b695e	548	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
EricLew	0:80ee8f3b695e	549	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
EricLew	0:80ee8f3b695e	550	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
EricLew	0:80ee8f3b695e	551	#define LL_TIM_TS_ETRF TIM_SMCR_TS /!< Filtered external Trigger (ETRF) is used as trigger input /
EricLew	0:80ee8f3b695e	552	/**
EricLew	0:80ee8f3b695e	553	* @}
EricLew	0:80ee8f3b695e	554	*/
EricLew	0:80ee8f3b695e	555
EricLew	0:80ee8f3b695e	556	/** @defgroup TIM_LL_EC_ETR_POLARITY ETR POLARITY
EricLew	0:80ee8f3b695e	557	* @{
EricLew	0:80ee8f3b695e	558	*/
EricLew	0:80ee8f3b695e	559	#define LL_TIM_ETR_POLARITY_NONINVERTED ((uint32_t)0x00000000) /!< ETR is non-inverted, active at high level or rising edge /
EricLew	0:80ee8f3b695e	560	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
EricLew	0:80ee8f3b695e	561	/**
EricLew	0:80ee8f3b695e	562	* @}
EricLew	0:80ee8f3b695e	563	*/
EricLew	0:80ee8f3b695e	564
EricLew	0:80ee8f3b695e	565	/** @defgroup TIM_LL_EC_ETR_PRESCALER ETR PRESCALER
EricLew	0:80ee8f3b695e	566	* @{
EricLew	0:80ee8f3b695e	567	*/
EricLew	0:80ee8f3b695e	568	#define LL_TIM_ETR_PRESCALER_DIV1 ((uint32_t)0x00000000) /!< ETR prescaler OFF /
EricLew	0:80ee8f3b695e	569	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
EricLew	0:80ee8f3b695e	570	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
EricLew	0:80ee8f3b695e	571	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
EricLew	0:80ee8f3b695e	572	/**
EricLew	0:80ee8f3b695e	573	* @}
EricLew	0:80ee8f3b695e	574	*/
EricLew	0:80ee8f3b695e	575
EricLew	0:80ee8f3b695e	576	/** @defgroup TIM_LL_EC_ETR_FILTER ETR FILTER
EricLew	0:80ee8f3b695e	577	* @{
EricLew	0:80ee8f3b695e	578	*/
EricLew	0:80ee8f3b695e	579	#define LL_TIM_ETR_FILTER_FDIV1 ((uint32_t)0x00000000) /!< No filter, sampling is done at fDTS /
EricLew	0:80ee8f3b695e	580	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
EricLew	0:80ee8f3b695e	581	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
EricLew	0:80ee8f3b695e	582	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
EricLew	0:80ee8f3b695e	583	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
EricLew	0:80ee8f3b695e	584	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
EricLew	0:80ee8f3b695e	585	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/4, N=6 /
EricLew	0:80ee8f3b695e	586	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
EricLew	0:80ee8f3b695e	587	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
EricLew	0:80ee8f3b695e	588	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
EricLew	0:80ee8f3b695e	589	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 ) /!< fSAMPLING=fDTS/16, N=6 /
EricLew	0:80ee8f3b695e	590	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
EricLew	0:80ee8f3b695e	591	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 ) /!< fSAMPLING=fDTS/16, N=5 /
EricLew	0:80ee8f3b695e	592	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
EricLew	0:80ee8f3b695e	593	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
EricLew	0:80ee8f3b695e	594	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
EricLew	0:80ee8f3b695e	595	/**
EricLew	0:80ee8f3b695e	596	* @}
EricLew	0:80ee8f3b695e	597	*/
EricLew	0:80ee8f3b695e	598
EricLew	0:80ee8f3b695e	599	/** @defgroup TIM_LL_EC_ETRSOURCE ETRSOURCE
EricLew	0:80ee8f3b695e	600	* @{
EricLew	0:80ee8f3b695e	601	*/
EricLew	0:80ee8f3b695e	602	#define LL_TIM_ETRSOURCE_LEGACY ((uint32_t)(0x00000000)) /!< ETR legacy mode /
EricLew	0:80ee8f3b695e	603	#define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /!< COMP1 output connected to ETR input /
EricLew	0:80ee8f3b695e	604	#define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /!< COMP2 output connected to ETR input /
EricLew	0:80ee8f3b695e	605	/**
EricLew	0:80ee8f3b695e	606	* @}
EricLew	0:80ee8f3b695e	607	*/
EricLew	0:80ee8f3b695e	608
EricLew	0:80ee8f3b695e	609	/** @defgroup TIM_LL_EC_BREAK_POLARITY BREAK POLARITY
EricLew	0:80ee8f3b695e	610	* @{
EricLew	0:80ee8f3b695e	611	*/
EricLew	0:80ee8f3b695e	612	#define LL_TIM_BREAK_POLARITY_LOW ((uint32_t)0x00000000) /!< Break input BRK is active low /
EricLew	0:80ee8f3b695e	613	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
EricLew	0:80ee8f3b695e	614	/**
EricLew	0:80ee8f3b695e	615	* @}
EricLew	0:80ee8f3b695e	616	*/
EricLew	0:80ee8f3b695e	617
EricLew	0:80ee8f3b695e	618	/** @defgroup TIM_LL_EC_BREAK_FILTER BREAK FILTER
EricLew	0:80ee8f3b695e	619	* @{
EricLew	0:80ee8f3b695e	620	*/
EricLew	0:80ee8f3b695e	621	#define LL_TIM_BREAK_FILTER_FDIV1 ((uint32_t)0x00000000) /!< No filter, BRK acts asynchronously /
EricLew	0:80ee8f3b695e	622	#define LL_TIM_BREAK_FILTER_FDIV1_N2 ((uint32_t)0x00010000) /!< fSAMPLING=fCK_INT, N=2 /
EricLew	0:80ee8f3b695e	623	#define LL_TIM_BREAK_FILTER_FDIV1_N4 ((uint32_t)0x00020000) /!< fSAMPLING=fCK_INT, N=4 /
EricLew	0:80ee8f3b695e	624	#define LL_TIM_BREAK_FILTER_FDIV1_N8 ((uint32_t)0x00030000) /!< fSAMPLING=fCK_INT, N=8 /
EricLew	0:80ee8f3b695e	625	#define LL_TIM_BREAK_FILTER_FDIV2_N6 ((uint32_t)0x00040000) /!< fSAMPLING=fDTS/2, N=6 /
EricLew	0:80ee8f3b695e	626	#define LL_TIM_BREAK_FILTER_FDIV2_N8 ((uint32_t)0x00050000) /!< fSAMPLING=fDTS/2, N=8 /
EricLew	0:80ee8f3b695e	627	#define LL_TIM_BREAK_FILTER_FDIV4_N6 ((uint32_t)0x00060000) /!< fSAMPLING=fDTS/4, N=6 /
EricLew	0:80ee8f3b695e	628	#define LL_TIM_BREAK_FILTER_FDIV4_N8 ((uint32_t)0x00070000) /!< fSAMPLING=fDTS/4, N=8 /
EricLew	0:80ee8f3b695e	629	#define LL_TIM_BREAK_FILTER_FDIV8_N6 ((uint32_t)0x00080000) /!< fSAMPLING=fDTS/8, N=6 /
EricLew	0:80ee8f3b695e	630	#define LL_TIM_BREAK_FILTER_FDIV8_N8 ((uint32_t)0x00090000) /!< fSAMPLING=fDTS/8, N=8 /
EricLew	0:80ee8f3b695e	631	#define LL_TIM_BREAK_FILTER_FDIV16_N5 ((uint32_t)0x000A0000) /!< fSAMPLING=fDTS/16, N=5 /
EricLew	0:80ee8f3b695e	632	#define LL_TIM_BREAK_FILTER_FDIV16_N6 ((uint32_t)0x000B0000) /!< fSAMPLING=fDTS/16, N=6 /
EricLew	0:80ee8f3b695e	633	#define LL_TIM_BREAK_FILTER_FDIV16_N8 ((uint32_t)0x000C0000) /!< fSAMPLING=fDTS/16, N=8 /
EricLew	0:80ee8f3b695e	634	#define LL_TIM_BREAK_FILTER_FDIV32_N5 ((uint32_t)0x000D0000) /!< fSAMPLING=fDTS/32, N=5 /
EricLew	0:80ee8f3b695e	635	#define LL_TIM_BREAK_FILTER_FDIV32_N6 ((uint32_t)0x000E0000) /!< fSAMPLING=fDTS/32, N=6 /
EricLew	0:80ee8f3b695e	636	#define LL_TIM_BREAK_FILTER_FDIV32_N8 ((uint32_t)0x000F0000) /!< fSAMPLING=fDTS/32, N=8 /
EricLew	0:80ee8f3b695e	637	/**
EricLew	0:80ee8f3b695e	638	* @}
EricLew	0:80ee8f3b695e	639	*/
EricLew	0:80ee8f3b695e	640
EricLew	0:80ee8f3b695e	641	/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
EricLew	0:80ee8f3b695e	642	* @{
EricLew	0:80ee8f3b695e	643	*/
EricLew	0:80ee8f3b695e	644	#define LL_TIM_BREAK2_POLARITY_LOW ((uint32_t)0x00000000) /!< Break input BRK2 is active low /
EricLew	0:80ee8f3b695e	645	#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /!< Break input BRK2 is active high /
EricLew	0:80ee8f3b695e	646	/**
EricLew	0:80ee8f3b695e	647	* @}
EricLew	0:80ee8f3b695e	648	*/
EricLew	0:80ee8f3b695e	649
EricLew	0:80ee8f3b695e	650	/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
EricLew	0:80ee8f3b695e	651	* @{
EricLew	0:80ee8f3b695e	652	*/
EricLew	0:80ee8f3b695e	653	#define LL_TIM_BREAK2_FILTER_FDIV1 ((uint32_t)0x00000000) /!< No filter, BRK acts asynchronously /
EricLew	0:80ee8f3b695e	654	#define LL_TIM_BREAK2_FILTER_FDIV1_N2 ((uint32_t)0x00100000) /!< fSAMPLING=fCK_INT, N=2 /
EricLew	0:80ee8f3b695e	655	#define LL_TIM_BREAK2_FILTER_FDIV1_N4 ((uint32_t)0x00200000) /!< fSAMPLING=fCK_INT, N=4 /
EricLew	0:80ee8f3b695e	656	#define LL_TIM_BREAK2_FILTER_FDIV1_N8 ((uint32_t)0x00300000) /!< fSAMPLING=fCK_INT, N=8 /
EricLew	0:80ee8f3b695e	657	#define LL_TIM_BREAK2_FILTER_FDIV2_N6 ((uint32_t)0x00400000) /!< fSAMPLING=fDTS/2, N=6 /
EricLew	0:80ee8f3b695e	658	#define LL_TIM_BREAK2_FILTER_FDIV2_N8 ((uint32_t)0x00500000) /!< fSAMPLING=fDTS/2, N=8 /
EricLew	0:80ee8f3b695e	659	#define LL_TIM_BREAK2_FILTER_FDIV4_N6 ((uint32_t)0x00600000) /!< fSAMPLING=fDTS/4, N=6 /
EricLew	0:80ee8f3b695e	660	#define LL_TIM_BREAK2_FILTER_FDIV4_N8 ((uint32_t)0x00700000) /!< fSAMPLING=fDTS/4, N=8 /
EricLew	0:80ee8f3b695e	661	#define LL_TIM_BREAK2_FILTER_FDIV8_N6 ((uint32_t)0x00800000) /!< fSAMPLING=fDTS/8, N=6 /
EricLew	0:80ee8f3b695e	662	#define LL_TIM_BREAK2_FILTER_FDIV8_N8 ((uint32_t)0x00900000) /!< fSAMPLING=fDTS/8, N=8 /
EricLew	0:80ee8f3b695e	663	#define LL_TIM_BREAK2_FILTER_FDIV16_N5 ((uint32_t)0x00A00000) /!< fSAMPLING=fDTS/16, N=5 /
EricLew	0:80ee8f3b695e	664	#define LL_TIM_BREAK2_FILTER_FDIV16_N6 ((uint32_t)0x00B00000) /!< fSAMPLING=fDTS/16, N=6 /
EricLew	0:80ee8f3b695e	665	#define LL_TIM_BREAK2_FILTER_FDIV16_N8 ((uint32_t)0x00C00000) /!< fSAMPLING=fDTS/16, N=8 /
EricLew	0:80ee8f3b695e	666	#define LL_TIM_BREAK2_FILTER_FDIV32_N5 ((uint32_t)0x00D00000) /!< fSAMPLING=fDTS/32, N=5 /
EricLew	0:80ee8f3b695e	667	#define LL_TIM_BREAK2_FILTER_FDIV32_N6 ((uint32_t)0x00E00000) /!< fSAMPLING=fDTS/32, N=6 /
EricLew	0:80ee8f3b695e	668	#define LL_TIM_BREAK2_FILTER_FDIV32_N8 ((uint32_t)0x00F00000) /!< fSAMPLING=fDTS/32, N=8 /
EricLew	0:80ee8f3b695e	669	/**
EricLew	0:80ee8f3b695e	670	* @}
EricLew	0:80ee8f3b695e	671	*/
EricLew	0:80ee8f3b695e	672
EricLew	0:80ee8f3b695e	673	/** @defgroup TIM_LL_EC_OSSI OSSI
EricLew	0:80ee8f3b695e	674	* @{
EricLew	0:80ee8f3b695e	675	*/
EricLew	0:80ee8f3b695e	676	#define LL_TIM_OSSI_DISABLE ((uint32_t)0x00000000) /!< When inactive, OCx/OCxN outputs are disabled /
EricLew	0:80ee8f3b695e	677	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
EricLew	0:80ee8f3b695e	678	/**
EricLew	0:80ee8f3b695e	679	* @}
EricLew	0:80ee8f3b695e	680	*/
EricLew	0:80ee8f3b695e	681
EricLew	0:80ee8f3b695e	682	/** @defgroup TIM_LL_EC_OSSR OSSR
EricLew	0:80ee8f3b695e	683	* @{
EricLew	0:80ee8f3b695e	684	*/
EricLew	0:80ee8f3b695e	685	#define LL_TIM_OSSR_DISABLE ((uint32_t)0x00000000) /!< When inactive, OCx/OCxN outputs are disabled /
EricLew	0:80ee8f3b695e	686	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
EricLew	0:80ee8f3b695e	687	/**
EricLew	0:80ee8f3b695e	688	* @}
EricLew	0:80ee8f3b695e	689	*/
EricLew	0:80ee8f3b695e	690
EricLew	0:80ee8f3b695e	691	/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
EricLew	0:80ee8f3b695e	692	* @{
EricLew	0:80ee8f3b695e	693	*/
EricLew	0:80ee8f3b695e	694	#define LL_TIM_BREAK_INPUT_BKIN ((uint32_t)0x00000000) /!< TIMx_BKIN input /
EricLew	0:80ee8f3b695e	695	#define LL_TIM_BREAK_INPUT_BKIN2 ((uint32_t)0x00000004) /!< TIMx_BKIN2 input /
EricLew	0:80ee8f3b695e	696	/**
EricLew	0:80ee8f3b695e	697	* @}
EricLew	0:80ee8f3b695e	698	*/
EricLew	0:80ee8f3b695e	699
EricLew	0:80ee8f3b695e	700	/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
EricLew	0:80ee8f3b695e	701	* @{
EricLew	0:80ee8f3b695e	702	*/
EricLew	0:80ee8f3b695e	703	#define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /!< BKIN input from AF controller /
EricLew	0:80ee8f3b695e	704	#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /!< internal signal: COMP1 output /
EricLew	0:80ee8f3b695e	705	#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /!< internal signal: COMP2 output /
EricLew	0:80ee8f3b695e	706	#define LL_TIM_BKIN_SOURCE_DFBK TIM1_OR2_BKDFBK0E /!< internal signal: DFSDM break output /
EricLew	0:80ee8f3b695e	707	/**
EricLew	0:80ee8f3b695e	708	* @}
EricLew	0:80ee8f3b695e	709	*/
EricLew	0:80ee8f3b695e	710
EricLew	0:80ee8f3b695e	711	/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
EricLew	0:80ee8f3b695e	712	* @{
EricLew	0:80ee8f3b695e	713	*/
EricLew	0:80ee8f3b695e	714	#define LL_TIM_BKIN_POLARITY_LOW ((uint32_t)0x00000000) /!< BRK BKIN input is active low /
EricLew	0:80ee8f3b695e	715	#define LL_TIM_BKIN_POLARITY_HIGH TIM1_OR2_BKINP /!< BRK BKIN input is active high /
EricLew	0:80ee8f3b695e	716	/**
EricLew	0:80ee8f3b695e	717	* @}
EricLew	0:80ee8f3b695e	718	*/
EricLew	0:80ee8f3b695e	719
EricLew	0:80ee8f3b695e	720	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMABURST BASEADDR
EricLew	0:80ee8f3b695e	721	* @{
EricLew	0:80ee8f3b695e	722	*/
EricLew	0:80ee8f3b695e	723	#define LL_TIM_DMABURST_BASEADDR_CR1 ((uint32_t)0x00000000) /!< TIMx_CR1 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	724	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	725	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	726	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	727	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	728	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	729	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	730	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	731	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	732	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	733	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	734	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	735	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	736	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	737	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	738	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	739	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	740	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	741	#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1) /!< TIMx_CCMR3 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	742	#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR5 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	743	#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2) /!< TIMx_CCR6 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	744	#define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_OR1 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	745	#define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_OR2 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	746	#define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_OR3 register is the DMA base address for DMA burst /
EricLew	0:80ee8f3b695e	747	/**
EricLew	0:80ee8f3b695e	748	* @}
EricLew	0:80ee8f3b695e	749	*/
EricLew	0:80ee8f3b695e	750
EricLew	0:80ee8f3b695e	751	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMABURST LENGTH
EricLew	0:80ee8f3b695e	752	* @{
EricLew	0:80ee8f3b695e	753	*/
EricLew	0:80ee8f3b695e	754	#define LL_TIM_DMABURST_LENGTH_1TRANSFER ((uint32_t)0x00000000) /!< Transfer is done to 1 register starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	755	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	756	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	757	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	758	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	759	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	760	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	761	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	762	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	763	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	764	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	765	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	766	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	767	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	768	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	769	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	770	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	771	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA busrt base address /
EricLew	0:80ee8f3b695e	772	/**
EricLew	0:80ee8f3b695e	773	* @}
EricLew	0:80ee8f3b695e	774	*/
EricLew	0:80ee8f3b695e	775
EricLew	0:80ee8f3b695e	776	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 ETR ADC1 RMP
EricLew	0:80ee8f3b695e	777	* @{
EricLew	0:80ee8f3b695e	778	*/
EricLew	0:80ee8f3b695e	779	#define LL_TIM_TIM1_ETR_ADC1_RMP_NC ((uint32_t)0x00000000 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is not connected to ADC1 analog watchdog x /
EricLew	0:80ee8f3b695e	780	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 1 /
EricLew	0:80ee8f3b695e	781	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 2 /
EricLew	0:80ee8f3b695e	782	#define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC1 analog watchdog 3 /
EricLew	0:80ee8f3b695e	783	/**
EricLew	0:80ee8f3b695e	784	* @}
EricLew	0:80ee8f3b695e	785	*/
EricLew	0:80ee8f3b695e	786
EricLew	0:80ee8f3b695e	787	/** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 ETR ADC3 RMP
EricLew	0:80ee8f3b695e	788	* @{
EricLew	0:80ee8f3b695e	789	*/
EricLew	0:80ee8f3b695e	790	#define LL_TIM_TIM1_ETR_ADC3_RMP_NC ((uint32_t)0x00000000 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is not connected to ADC3 analog watchdog x/
EricLew	0:80ee8f3b695e	791	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 1 /
EricLew	0:80ee8f3b695e	792	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 2 /
EricLew	0:80ee8f3b695e	793	#define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1_ETR is connected to ADC3 analog watchdog 3 /
EricLew	0:80ee8f3b695e	794	/**
EricLew	0:80ee8f3b695e	795	* @}
EricLew	0:80ee8f3b695e	796	*/
EricLew	0:80ee8f3b695e	797
EricLew	0:80ee8f3b695e	798	/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 TI1 RMP
EricLew	0:80ee8f3b695e	799	* @{
EricLew	0:80ee8f3b695e	800	*/
EricLew	0:80ee8f3b695e	801	#define LL_TIM_TIM1_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	802	#define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP \| TIM1_OR1_RMP_MASK) /!< TIM1 input capture 1 is connected to COMP1 output /
EricLew	0:80ee8f3b695e	803	/**
EricLew	0:80ee8f3b695e	804	* @}
EricLew	0:80ee8f3b695e	805	*/
EricLew	0:80ee8f3b695e	806
EricLew	0:80ee8f3b695e	807	/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 ITR1 RMP TIM8
EricLew	0:80ee8f3b695e	808	* @{
EricLew	0:80ee8f3b695e	809	*/
EricLew	0:80ee8f3b695e	810	#define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO ((uint32_t)0x00000000 \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to TIM8_TRGO /
EricLew	0:80ee8f3b695e	811	#define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ITR1 is connected to OTG_FS SOF /
EricLew	0:80ee8f3b695e	812	#define LL_TIM_TIM2_ETR_RMP_GPIO ((uint32_t)0x00000000 \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to GPIO /
EricLew	0:80ee8f3b695e	813	#define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2_ETR is connected to LSE /
EricLew	0:80ee8f3b695e	814	/**
EricLew	0:80ee8f3b695e	815	* @}
EricLew	0:80ee8f3b695e	816	*/
EricLew	0:80ee8f3b695e	817
EricLew	0:80ee8f3b695e	818	/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 TI4 RMP
EricLew	0:80ee8f3b695e	819	* @{
EricLew	0:80ee8f3b695e	820	*/
EricLew	0:80ee8f3b695e	821	#define LL_TIM_TIM2_TI4_RMP_GPIO ((uint32_t)0x00000000 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to GPIO /
EricLew	0:80ee8f3b695e	822	#define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP1_OUT /
EricLew	0:80ee8f3b695e	823	#define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to COMP2_OUT /
EricLew	0:80ee8f3b695e	824	#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP \| TIM2_OR1_RMP_MASK) /!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT /
EricLew	0:80ee8f3b695e	825	/**
EricLew	0:80ee8f3b695e	826	* @}
EricLew	0:80ee8f3b695e	827	*/
EricLew	0:80ee8f3b695e	828
EricLew	0:80ee8f3b695e	829	/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 TI1 RMP
EricLew	0:80ee8f3b695e	830	* @{
EricLew	0:80ee8f3b695e	831	*/
EricLew	0:80ee8f3b695e	832	#define LL_TIM_TIM3_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	833	#define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP1_OUT /
EricLew	0:80ee8f3b695e	834	#define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to COMP2_OUT /
EricLew	0:80ee8f3b695e	835	#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP \| TIM3_OR1_RMP_MASK) /!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT /
EricLew	0:80ee8f3b695e	836	/**
EricLew	0:80ee8f3b695e	837	* @}
EricLew	0:80ee8f3b695e	838	*/
EricLew	0:80ee8f3b695e	839
EricLew	0:80ee8f3b695e	840	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 ETR ADC2 RMP
EricLew	0:80ee8f3b695e	841	* @{
EricLew	0:80ee8f3b695e	842	*/
EricLew	0:80ee8f3b695e	843	#define LL_TIM_TIM8_ETR_ADC2_RMP_NC ((uint32_t)0x00000000 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is not connected to ADC2 analog watchdog x /
EricLew	0:80ee8f3b695e	844	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog /
EricLew	0:80ee8f3b695e	845	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 2 /
EricLew	0:80ee8f3b695e	846	#define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC2 analog watchdog 3 /
EricLew	0:80ee8f3b695e	847	/**
EricLew	0:80ee8f3b695e	848	* @}
EricLew	0:80ee8f3b695e	849	*/
EricLew	0:80ee8f3b695e	850
EricLew	0:80ee8f3b695e	851	/** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 ETR ADC3 RMP
EricLew	0:80ee8f3b695e	852	* @{
EricLew	0:80ee8f3b695e	853	*/
EricLew	0:80ee8f3b695e	854	#define LL_TIM_TIM8_ETR_ADC3_RMP_NC ((uint32_t)0x00000000 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is not connected to ADC3 analog watchdog x /
EricLew	0:80ee8f3b695e	855	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 1 /
EricLew	0:80ee8f3b695e	856	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 2 /
EricLew	0:80ee8f3b695e	857	#define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8_ETR is connected to ADC3 analog watchdog 3 /
EricLew	0:80ee8f3b695e	858	/**
EricLew	0:80ee8f3b695e	859	* @}
EricLew	0:80ee8f3b695e	860	*/
EricLew	0:80ee8f3b695e	861
EricLew	0:80ee8f3b695e	862	/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 TI1 RMP
EricLew	0:80ee8f3b695e	863	* @{
EricLew	0:80ee8f3b695e	864	*/
EricLew	0:80ee8f3b695e	865	#define LL_TIM_TIM8_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	866	#define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP \| TIM8_OR1_RMP_MASK) /!< TIM8 input capture 1 is connected to COMP2 output /
EricLew	0:80ee8f3b695e	867	/**
EricLew	0:80ee8f3b695e	868	* @}
EricLew	0:80ee8f3b695e	869	*/
EricLew	0:80ee8f3b695e	870
EricLew	0:80ee8f3b695e	871	/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 TI1 RMP
EricLew	0:80ee8f3b695e	872	* @{
EricLew	0:80ee8f3b695e	873	*/
EricLew	0:80ee8f3b695e	874	#define LL_TIM_TIM15_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	875	#define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP \| TIM15_OR1_RMP_MASK) /!< TIM15 input capture 1 is connected to LSE /
EricLew	0:80ee8f3b695e	876	/**
EricLew	0:80ee8f3b695e	877	* @}
EricLew	0:80ee8f3b695e	878	*/
EricLew	0:80ee8f3b695e	879
EricLew	0:80ee8f3b695e	880	/** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE
EricLew	0:80ee8f3b695e	881	* @{
EricLew	0:80ee8f3b695e	882	*/
EricLew	0:80ee8f3b695e	883	#define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION ((uint32_t)0x00000000 \| TIM15_OR1_RMP_MASK) /!< No redirection/
EricLew	0:80ee8f3b695e	884	#define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 \| TIM15_OR1_RMP_MASK) /!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
EricLew	0:80ee8f3b695e	885	#define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 \| TIM15_OR1_RMP_MASK) /!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y/
EricLew	0:80ee8f3b695e	886	#define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE \| TIM15_OR1_RMP_MASK) /!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively /
EricLew	0:80ee8f3b695e	887	/**
EricLew	0:80ee8f3b695e	888	* @}
EricLew	0:80ee8f3b695e	889	*/
EricLew	0:80ee8f3b695e	890
EricLew	0:80ee8f3b695e	891	/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 TI1 RMP
EricLew	0:80ee8f3b695e	892	* @{
EricLew	0:80ee8f3b695e	893	*/
EricLew	0:80ee8f3b695e	894	#define LL_TIM_TIM16_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	895	#define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSI /
EricLew	0:80ee8f3b695e	896	#define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to LSE /
EricLew	0:80ee8f3b695e	897	#define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP \| TIM16_OR1_RMP_MASK) /!< TIM16 input capture 1 is connected to RTC wakeup iterrupt /
EricLew	0:80ee8f3b695e	898	/**
EricLew	0:80ee8f3b695e	899	* @}
EricLew	0:80ee8f3b695e	900	*/
EricLew	0:80ee8f3b695e	901
EricLew	0:80ee8f3b695e	902	/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 TI1 RMP
EricLew	0:80ee8f3b695e	903	* @{
EricLew	0:80ee8f3b695e	904	*/
EricLew	0:80ee8f3b695e	905	#define LL_TIM_TIM17_TI1_RMP_GPIO ((uint32_t)0x00000000 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to GPIO /
EricLew	0:80ee8f3b695e	906	#define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MSI /
EricLew	0:80ee8f3b695e	907	#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to HSE/32 /
EricLew	0:80ee8f3b695e	908	#define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP \| TIM17_OR1_RMP_MASK) /!< TIM17 input capture 1 is connected to MCO /
EricLew	0:80ee8f3b695e	909	/**
EricLew	0:80ee8f3b695e	910	* @}
EricLew	0:80ee8f3b695e	911	*/
EricLew	0:80ee8f3b695e	912
EricLew	0:80ee8f3b695e	913	/**
EricLew	0:80ee8f3b695e	914	* @}
EricLew	0:80ee8f3b695e	915	*/
EricLew	0:80ee8f3b695e	916
EricLew	0:80ee8f3b695e	917	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	918	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
EricLew	0:80ee8f3b695e	919	* @{
EricLew	0:80ee8f3b695e	920	*/
EricLew	0:80ee8f3b695e	921
EricLew	0:80ee8f3b695e	922	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
EricLew	0:80ee8f3b695e	923	* @{
EricLew	0:80ee8f3b695e	924	*/
EricLew	0:80ee8f3b695e	925	/**
EricLew	0:80ee8f3b695e	926	* @brief Write a value in TIM register
EricLew	0:80ee8f3b695e	927	* @param __INSTANCE__ TIM Instance
EricLew	0:80ee8f3b695e	928	* @param __REG__ Register to be written
EricLew	0:80ee8f3b695e	929	* @param __VALUE__ Value to be written in the register
EricLew	0:80ee8f3b695e	930	* @retval None
EricLew	0:80ee8f3b695e	931	*/
EricLew	0:80ee8f3b695e	932	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
EricLew	0:80ee8f3b695e	933
EricLew	0:80ee8f3b695e	934	/**
EricLew	0:80ee8f3b695e	935	* @brief Read a value in TIM register
EricLew	0:80ee8f3b695e	936	* @param __INSTANCE__ TIM Instance
EricLew	0:80ee8f3b695e	937	* @param __REG__ Register to be read
EricLew	0:80ee8f3b695e	938	* @retval Register value
EricLew	0:80ee8f3b695e	939	*/
EricLew	0:80ee8f3b695e	940	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
EricLew	0:80ee8f3b695e	941	/**
EricLew	0:80ee8f3b695e	942	* @}
EricLew	0:80ee8f3b695e	943	*/
EricLew	0:80ee8f3b695e	944
EricLew	0:80ee8f3b695e	945	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
EricLew	0:80ee8f3b695e	946	* @{
EricLew	0:80ee8f3b695e	947	*/
EricLew	0:80ee8f3b695e	948	/**
EricLew	0:80ee8f3b695e	949	* @brief HELPER macro retrieving the UIFCPY flag from the counter value
EricLew	0:80ee8f3b695e	950	* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
EricLew	0:80ee8f3b695e	951	* to TIMx_CNT register bit 31)
EricLew	0:80ee8f3b695e	952	* @param __CNT__ Counter value
EricLew	0:80ee8f3b695e	953	* @retval UIF status bit
EricLew	0:80ee8f3b695e	954	*/
EricLew	0:80ee8f3b695e	955	#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
EricLew	0:80ee8f3b695e	956	(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> POSITION_VAL(TIM_CNT_UIFCPY))
EricLew	0:80ee8f3b695e	957
EricLew	0:80ee8f3b695e	958	/**
EricLew	0:80ee8f3b695e	959	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to
EricLew	0:80ee8f3b695e	960	* achieve the requested dead time duration
EricLew	0:80ee8f3b695e	961	* @param __TIMCLK__ timer input clock frequency (in Hz)
EricLew	0:80ee8f3b695e	962	* @param __CKD__ This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	963	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
EricLew	0:80ee8f3b695e	964	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
EricLew	0:80ee8f3b695e	965	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
EricLew	0:80ee8f3b695e	966	* @param __DT__ deadtime duration (in us)
EricLew	0:80ee8f3b695e	967	* @retval DTG[0:7]
EricLew	0:80ee8f3b695e	968	*/
EricLew	0:80ee8f3b695e	969	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
EricLew	0:80ee8f3b695e	970	( (((uint64_t)((__DT__)1000)) < ((DT_DELAY_1+1) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? ((uint8_t)(((uint64_t)((__DT__)*1000)) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
EricLew	0:80ee8f3b695e	971	(((uint64_t)((__DT__)1000)) < (64 + (DT_DELAY_2+1)) 2 * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (DT_RANGE_2 \| ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1) - 64) & DT_DELAY_2)) :\
EricLew	0:80ee8f3b695e	972	(((uint64_t)((__DT__)1000)) < (32 + (DT_DELAY_3+1)) 8 * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (DT_RANGE_3 \| ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3) - 32) & DT_DELAY_3)) :\
EricLew	0:80ee8f3b695e	973	(((uint64_t)((__DT__)1000)) < (32 + (DT_DELAY_4+1)) 16 * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (DT_RANGE_4 \| ((uint8_t)(((((uint64_t)((__DT__)*1000))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4) - 32) & DT_DELAY_4)) :\
EricLew	0:80ee8f3b695e	974	0)
EricLew	0:80ee8f3b695e	975
EricLew	0:80ee8f3b695e	976	/**
EricLew	0:80ee8f3b695e	977	* @brief HELPER macro calculating the prescaler value to achieve the required
EricLew	0:80ee8f3b695e	978	* counter clock frequency
EricLew	0:80ee8f3b695e	979	* @param __TIMCLK__ timer input clock frequency (in Hz)
EricLew	0:80ee8f3b695e	980	* @param __CNTCLK__ counter clock frequency (in Hz)
EricLew	0:80ee8f3b695e	981	* @retval Prescaler value
EricLew	0:80ee8f3b695e	982	*/
EricLew	0:80ee8f3b695e	983	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
EricLew	0:80ee8f3b695e	984	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1) : 0
EricLew	0:80ee8f3b695e	985
EricLew	0:80ee8f3b695e	986	/**
EricLew	0:80ee8f3b695e	987	* @brief HELPER macro calculating the auto-reload value to achieve the
EricLew	0:80ee8f3b695e	988	* required output signal frequency
EricLew	0:80ee8f3b695e	989	* @param __TIMCLK__ timer input clock frequency (in Hz)
EricLew	0:80ee8f3b695e	990	* @param __PSC__ prescaler
EricLew	0:80ee8f3b695e	991	* @param __FREQ__ output signal frequency (in Hz)
EricLew	0:80ee8f3b695e	992	* @retval Auto-reload value
EricLew	0:80ee8f3b695e	993	*/
EricLew	0:80ee8f3b695e	994	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
EricLew	0:80ee8f3b695e	995	(((__TIMCLK__)/((__PSC__) + 1)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1)) - 1) : 0
EricLew	0:80ee8f3b695e	996
EricLew	0:80ee8f3b695e	997	/**
EricLew	0:80ee8f3b695e	998	* @brief HELPER macro calculating the compare value required to achieve the
EricLew	0:80ee8f3b695e	999	* required timer output compare active/inactive delay
EricLew	0:80ee8f3b695e	1000	* @param __TIMCLK__ timer input clock frequency (in Hz)
EricLew	0:80ee8f3b695e	1001	* @param __PSC__ prescaler
EricLew	0:80ee8f3b695e	1002	* @param __DELAY__ timer output compare active/inactive delay (in us)
EricLew	0:80ee8f3b695e	1003	* @retval Compare value
EricLew	0:80ee8f3b695e	1004	*/
EricLew	0:80ee8f3b695e	1005	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
EricLew	0:80ee8f3b695e	1006	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
EricLew	0:80ee8f3b695e	1007	/ ((uint64_t)1000000 * (uint64_t)((__PSC__) + 1))))
EricLew	0:80ee8f3b695e	1008
EricLew	0:80ee8f3b695e	1009	/**
EricLew	0:80ee8f3b695e	1010	* @brief HELPER macro calculating the auto-reload value to achieve the
EricLew	0:80ee8f3b695e	1011	* * required pulse duration (when the timer operates in one pulse mode)
EricLew	0:80ee8f3b695e	1012	* @param __TIMCLK__ timer input clock frequency (in Hz)
EricLew	0:80ee8f3b695e	1013	* @param __PSC__ prescaler
EricLew	0:80ee8f3b695e	1014	* @param __DELAY__ timer output compare active/inactive delay (in us)
EricLew	0:80ee8f3b695e	1015	* @param __PULSE__ pulse duration (in us)
EricLew	0:80ee8f3b695e	1016	* @retval Auto-reload value
EricLew	0:80ee8f3b695e	1017	*/
EricLew	0:80ee8f3b695e	1018	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
EricLew	0:80ee8f3b695e	1019	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
EricLew	0:80ee8f3b695e	1020	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
EricLew	0:80ee8f3b695e	1021
EricLew	0:80ee8f3b695e	1022	/**
EricLew	0:80ee8f3b695e	1023	* @brief HELPER macro retrieving the ratio of the input capture prescaler
EricLew	0:80ee8f3b695e	1024	* @param __ICPSC__ Input capture prescaler value
EricLew	0:80ee8f3b695e	1025	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
EricLew	0:80ee8f3b695e	1026	*/
EricLew	0:80ee8f3b695e	1027	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
EricLew	0:80ee8f3b695e	1028	((uint32_t)(0x01 << (((__ICPSC__) >> 16) >> POSITION_VAL(TIM_CCMR1_IC1PSC))))
EricLew	0:80ee8f3b695e	1029
EricLew	0:80ee8f3b695e	1030	/**
EricLew	0:80ee8f3b695e	1031	* @}
EricLew	0:80ee8f3b695e	1032	*/
EricLew	0:80ee8f3b695e	1033
EricLew	0:80ee8f3b695e	1034
EricLew	0:80ee8f3b695e	1035	/**
EricLew	0:80ee8f3b695e	1036	* @}
EricLew	0:80ee8f3b695e	1037	*/
EricLew	0:80ee8f3b695e	1038
EricLew	0:80ee8f3b695e	1039	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	1040	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
EricLew	0:80ee8f3b695e	1041	* @{
EricLew	0:80ee8f3b695e	1042	*/
EricLew	0:80ee8f3b695e	1043	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
EricLew	0:80ee8f3b695e	1044	* @{
EricLew	0:80ee8f3b695e	1045	*/
EricLew	0:80ee8f3b695e	1046	/**
EricLew	0:80ee8f3b695e	1047	* @brief Enable timer counter.
EricLew	0:80ee8f3b695e	1048	* @rmtoll CR1 CEN LL_TIM_EnableCounter
EricLew	0:80ee8f3b695e	1049	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1050	* @retval None
EricLew	0:80ee8f3b695e	1051	*/
EricLew	0:80ee8f3b695e	1052	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1053	{
EricLew	0:80ee8f3b695e	1054	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
EricLew	0:80ee8f3b695e	1055	}
EricLew	0:80ee8f3b695e	1056
EricLew	0:80ee8f3b695e	1057	/**
EricLew	0:80ee8f3b695e	1058	* @brief Disable timer counter.
EricLew	0:80ee8f3b695e	1059	* @rmtoll CR1 CEN LL_TIM_DisableCounter
EricLew	0:80ee8f3b695e	1060	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1061	* @retval None
EricLew	0:80ee8f3b695e	1062	*/
EricLew	0:80ee8f3b695e	1063	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1064	{
EricLew	0:80ee8f3b695e	1065	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
EricLew	0:80ee8f3b695e	1066	}
EricLew	0:80ee8f3b695e	1067
EricLew	0:80ee8f3b695e	1068	/**
EricLew	0:80ee8f3b695e	1069	* @brief Indicates whether the timer counter is enabled.
EricLew	0:80ee8f3b695e	1070	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
EricLew	0:80ee8f3b695e	1071	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1072	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1073	*/
EricLew	0:80ee8f3b695e	1074	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1075	{
EricLew	0:80ee8f3b695e	1076	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
EricLew	0:80ee8f3b695e	1077	}
EricLew	0:80ee8f3b695e	1078
EricLew	0:80ee8f3b695e	1079	/**
EricLew	0:80ee8f3b695e	1080	* @brief Enable update event generation.
EricLew	0:80ee8f3b695e	1081	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
EricLew	0:80ee8f3b695e	1082	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1083	* @retval None
EricLew	0:80ee8f3b695e	1084	*/
EricLew	0:80ee8f3b695e	1085	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1086	{
EricLew	0:80ee8f3b695e	1087	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
EricLew	0:80ee8f3b695e	1088	}
EricLew	0:80ee8f3b695e	1089
EricLew	0:80ee8f3b695e	1090	/**
EricLew	0:80ee8f3b695e	1091	* @brief Disable update event generation.
EricLew	0:80ee8f3b695e	1092	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
EricLew	0:80ee8f3b695e	1093	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1094	* @retval None
EricLew	0:80ee8f3b695e	1095	*/
EricLew	0:80ee8f3b695e	1096	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1097	{
EricLew	0:80ee8f3b695e	1098	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
EricLew	0:80ee8f3b695e	1099	}
EricLew	0:80ee8f3b695e	1100
EricLew	0:80ee8f3b695e	1101	/**
EricLew	0:80ee8f3b695e	1102	* @brief Indicates whether update event generation is enabled.
EricLew	0:80ee8f3b695e	1103	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
EricLew	0:80ee8f3b695e	1104	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1105	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1106	*/
EricLew	0:80ee8f3b695e	1107	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1108	{
EricLew	0:80ee8f3b695e	1109	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
EricLew	0:80ee8f3b695e	1110	}
EricLew	0:80ee8f3b695e	1111
EricLew	0:80ee8f3b695e	1112	/**
EricLew	0:80ee8f3b695e	1113	* @brief Set update event source
EricLew	0:80ee8f3b695e	1114	* @note
EricLew	0:80ee8f3b695e	1115	* Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
EricLew	0:80ee8f3b695e	1116	* generate an update interrupt or DMA request if enabled:
EricLew	0:80ee8f3b695e	1117	* Counter overflow/underflow
EricLew	0:80ee8f3b695e	1118	* Setting the UG bit
EricLew	0:80ee8f3b695e	1119	* Update generation through the slave mode controller
EricLew	0:80ee8f3b695e	1120	* Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
EricLew	0:80ee8f3b695e	1121	* overflow/underflow generates an update interrupt or DMA request if enabled.
EricLew	0:80ee8f3b695e	1122	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
EricLew	0:80ee8f3b695e	1123	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1124	* @param UpdateSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1125	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
EricLew	0:80ee8f3b695e	1126	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
EricLew	0:80ee8f3b695e	1127	* @retval None
EricLew	0:80ee8f3b695e	1128	*/
EricLew	0:80ee8f3b695e	1129	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx, uint32_t UpdateSource)
EricLew	0:80ee8f3b695e	1130	{
EricLew	0:80ee8f3b695e	1131	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
EricLew	0:80ee8f3b695e	1132	}
EricLew	0:80ee8f3b695e	1133
EricLew	0:80ee8f3b695e	1134	/**
EricLew	0:80ee8f3b695e	1135	* @brief Get actual event update source
EricLew	0:80ee8f3b695e	1136	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
EricLew	0:80ee8f3b695e	1137	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1138	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1139	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
EricLew	0:80ee8f3b695e	1140	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
EricLew	0:80ee8f3b695e	1141	*/
EricLew	0:80ee8f3b695e	1142	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1143	{
EricLew	0:80ee8f3b695e	1144	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
EricLew	0:80ee8f3b695e	1145	}
EricLew	0:80ee8f3b695e	1146
EricLew	0:80ee8f3b695e	1147	/**
EricLew	0:80ee8f3b695e	1148	* @brief Set one pulse mode (one shot v.s. repetitive).
EricLew	0:80ee8f3b695e	1149	* @rmtoll CR1 OPM LL_TIM_GetUpdateSource
EricLew	0:80ee8f3b695e	1150	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1151	* @param OnePulseMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1152	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
EricLew	0:80ee8f3b695e	1153	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
EricLew	0:80ee8f3b695e	1154	* @retval None
EricLew	0:80ee8f3b695e	1155	*/
EricLew	0:80ee8f3b695e	1156	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx, uint32_t OnePulseMode)
EricLew	0:80ee8f3b695e	1157	{
EricLew	0:80ee8f3b695e	1158	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
EricLew	0:80ee8f3b695e	1159	}
EricLew	0:80ee8f3b695e	1160
EricLew	0:80ee8f3b695e	1161	/**
EricLew	0:80ee8f3b695e	1162	* @brief Get actual one pulse mode.
EricLew	0:80ee8f3b695e	1163	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
EricLew	0:80ee8f3b695e	1164	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1165	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1166	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
EricLew	0:80ee8f3b695e	1167	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
EricLew	0:80ee8f3b695e	1168	*/
EricLew	0:80ee8f3b695e	1169	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1170	{
EricLew	0:80ee8f3b695e	1171	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
EricLew	0:80ee8f3b695e	1172	}
EricLew	0:80ee8f3b695e	1173
EricLew	0:80ee8f3b695e	1174	/**
EricLew	0:80ee8f3b695e	1175	* @brief Set the timer counter counting mode.
EricLew	0:80ee8f3b695e	1176	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	1177	* the counter mode selection feature is supported by a timer instance.
EricLew	0:80ee8f3b695e	1178	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
EricLew	0:80ee8f3b695e	1179	* CR1 CMS LL_TIM_SetCounterMode
EricLew	0:80ee8f3b695e	1180	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1181	* @param CounterMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1182	* @arg @ref LL_TIM_COUNTERMODE_UP
EricLew	0:80ee8f3b695e	1183	* @arg @ref LL_TIM_COUNTERMODE_DOWN
EricLew	0:80ee8f3b695e	1184	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
EricLew	0:80ee8f3b695e	1185	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
EricLew	0:80ee8f3b695e	1186	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
EricLew	0:80ee8f3b695e	1187	* @retval None
EricLew	0:80ee8f3b695e	1188	*/
EricLew	0:80ee8f3b695e	1189	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef * TIMx, uint32_t CounterMode)
EricLew	0:80ee8f3b695e	1190	{
EricLew	0:80ee8f3b695e	1191	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
EricLew	0:80ee8f3b695e	1192	}
EricLew	0:80ee8f3b695e	1193
EricLew	0:80ee8f3b695e	1194	/**
EricLew	0:80ee8f3b695e	1195	* @brief Get actual counter mode.
EricLew	0:80ee8f3b695e	1196	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	1197	* the counter mode selection feature is supported by a timer instance.
EricLew	0:80ee8f3b695e	1198	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
EricLew	0:80ee8f3b695e	1199	* CR1 CMS LL_TIM_GetCounterMode
EricLew	0:80ee8f3b695e	1200	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1201	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1202	* @arg @ref LL_TIM_COUNTERMODE_UP
EricLew	0:80ee8f3b695e	1203	* @arg @ref LL_TIM_COUNTERMODE_DOWN
EricLew	0:80ee8f3b695e	1204	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
EricLew	0:80ee8f3b695e	1205	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
EricLew	0:80ee8f3b695e	1206	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
EricLew	0:80ee8f3b695e	1207	*/
EricLew	0:80ee8f3b695e	1208	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1209	{
EricLew	0:80ee8f3b695e	1210	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
EricLew	0:80ee8f3b695e	1211	}
EricLew	0:80ee8f3b695e	1212
EricLew	0:80ee8f3b695e	1213	/**
EricLew	0:80ee8f3b695e	1214	* @brief Enable auto-reload (ARR) preload.
EricLew	0:80ee8f3b695e	1215	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
EricLew	0:80ee8f3b695e	1216	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1217	* @retval None
EricLew	0:80ee8f3b695e	1218	*/
EricLew	0:80ee8f3b695e	1219	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1220	{
EricLew	0:80ee8f3b695e	1221	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
EricLew	0:80ee8f3b695e	1222	}
EricLew	0:80ee8f3b695e	1223
EricLew	0:80ee8f3b695e	1224	/**
EricLew	0:80ee8f3b695e	1225	* @brief Disable auto-reload (ARR) preload.
EricLew	0:80ee8f3b695e	1226	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
EricLew	0:80ee8f3b695e	1227	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1228	* @retval None
EricLew	0:80ee8f3b695e	1229	*/
EricLew	0:80ee8f3b695e	1230	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1231	{
EricLew	0:80ee8f3b695e	1232	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
EricLew	0:80ee8f3b695e	1233	}
EricLew	0:80ee8f3b695e	1234
EricLew	0:80ee8f3b695e	1235	/**
EricLew	0:80ee8f3b695e	1236	* @brief Indicates whether auto-reload (ARR) preload is enabled.
EricLew	0:80ee8f3b695e	1237	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
EricLew	0:80ee8f3b695e	1238	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1239	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1240	*/
EricLew	0:80ee8f3b695e	1241	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1242	{
EricLew	0:80ee8f3b695e	1243	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
EricLew	0:80ee8f3b695e	1244	}
EricLew	0:80ee8f3b695e	1245
EricLew	0:80ee8f3b695e	1246	/**
EricLew	0:80ee8f3b695e	1247	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
EricLew	0:80ee8f3b695e	1248	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1249	* whether or not the clock division feature is supported by the a timer
EricLew	0:80ee8f3b695e	1250	* instance.
EricLew	0:80ee8f3b695e	1251	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
EricLew	0:80ee8f3b695e	1252	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1253	* @param ClockDivision This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1254	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
EricLew	0:80ee8f3b695e	1255	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
EricLew	0:80ee8f3b695e	1256	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
EricLew	0:80ee8f3b695e	1257	* @retval None
EricLew	0:80ee8f3b695e	1258	*/
EricLew	0:80ee8f3b695e	1259	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef * TIMx, uint32_t ClockDivision)
EricLew	0:80ee8f3b695e	1260	{
EricLew	0:80ee8f3b695e	1261	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
EricLew	0:80ee8f3b695e	1262	}
EricLew	0:80ee8f3b695e	1263
EricLew	0:80ee8f3b695e	1264	/**
EricLew	0:80ee8f3b695e	1265	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
EricLew	0:80ee8f3b695e	1266	* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1267	* whether or not the clock division feature is supported by the a timer
EricLew	0:80ee8f3b695e	1268	* instance.
EricLew	0:80ee8f3b695e	1269	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
EricLew	0:80ee8f3b695e	1270	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1271	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1272	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
EricLew	0:80ee8f3b695e	1273	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
EricLew	0:80ee8f3b695e	1274	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
EricLew	0:80ee8f3b695e	1275	*/
EricLew	0:80ee8f3b695e	1276	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1277	{
EricLew	0:80ee8f3b695e	1278	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
EricLew	0:80ee8f3b695e	1279	}
EricLew	0:80ee8f3b695e	1280
EricLew	0:80ee8f3b695e	1281	/**
EricLew	0:80ee8f3b695e	1282	* @brief Set the counter value.
EricLew	0:80ee8f3b695e	1283	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1284	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	1285	* @rmtoll CNT CNT LL_TIM_SetCounter
EricLew	0:80ee8f3b695e	1286	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1287	* @param Counter Counter value
EricLew	0:80ee8f3b695e	1288	* @retval None
EricLew	0:80ee8f3b695e	1289	*/
EricLew	0:80ee8f3b695e	1290	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef * TIMx, uint32_t Counter)
EricLew	0:80ee8f3b695e	1291	{
EricLew	0:80ee8f3b695e	1292	WRITE_REG(TIMx->CNT, Counter);
EricLew	0:80ee8f3b695e	1293	}
EricLew	0:80ee8f3b695e	1294
EricLew	0:80ee8f3b695e	1295	/**
EricLew	0:80ee8f3b695e	1296	* @brief Get the counter value.
EricLew	0:80ee8f3b695e	1297	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1298	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	1299	* counter.
EricLew	0:80ee8f3b695e	1300	* @rmtoll CNT CNT LL_TIM_GetCounter
EricLew	0:80ee8f3b695e	1301	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1302	* @retval Counter value
EricLew	0:80ee8f3b695e	1303	*/
EricLew	0:80ee8f3b695e	1304	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1305	{
EricLew	0:80ee8f3b695e	1306	return (uint32_t)(READ_REG(TIMx->CNT));
EricLew	0:80ee8f3b695e	1307	}
EricLew	0:80ee8f3b695e	1308
EricLew	0:80ee8f3b695e	1309	/**
EricLew	0:80ee8f3b695e	1310	* @brief Get the current direction of the counter
EricLew	0:80ee8f3b695e	1311	* @rmtoll CR1 DIR LL_TIM_GetDirection
EricLew	0:80ee8f3b695e	1312	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1313	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1314	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
EricLew	0:80ee8f3b695e	1315	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
EricLew	0:80ee8f3b695e	1316	*/
EricLew	0:80ee8f3b695e	1317	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1318	{
EricLew	0:80ee8f3b695e	1319	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
EricLew	0:80ee8f3b695e	1320	}
EricLew	0:80ee8f3b695e	1321
EricLew	0:80ee8f3b695e	1322	/**
EricLew	0:80ee8f3b695e	1323	* @brief Set the prescaler value.
EricLew	0:80ee8f3b695e	1324	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
EricLew	0:80ee8f3b695e	1325	* @note The prescaler can be changed on the fly as this control register is buffered. The new
EricLew	0:80ee8f3b695e	1326	* prescaler ratio is taken into account at the next update event.
EricLew	0:80ee8f3b695e	1327	* @rmtoll PSC PSC LL_TIM_SetPrescaler
EricLew	0:80ee8f3b695e	1328	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1329	* @param Prescaler Between 0 and 65535
EricLew	0:80ee8f3b695e	1330	* @retval None
EricLew	0:80ee8f3b695e	1331	*/
EricLew	0:80ee8f3b695e	1332	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Prescaler)
EricLew	0:80ee8f3b695e	1333	{
EricLew	0:80ee8f3b695e	1334	WRITE_REG(TIMx->PSC, Prescaler);
EricLew	0:80ee8f3b695e	1335	}
EricLew	0:80ee8f3b695e	1336
EricLew	0:80ee8f3b695e	1337	/**
EricLew	0:80ee8f3b695e	1338	* @brief Get the prescaler value.
EricLew	0:80ee8f3b695e	1339	* @rmtoll PSC PSC LL_TIM_GetPrescaler
EricLew	0:80ee8f3b695e	1340	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1341	* @retval Prescaler value
EricLew	0:80ee8f3b695e	1342	*/
EricLew	0:80ee8f3b695e	1343	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1344	{
EricLew	0:80ee8f3b695e	1345	return (uint32_t)(READ_REG(TIMx->PSC));
EricLew	0:80ee8f3b695e	1346	}
EricLew	0:80ee8f3b695e	1347
EricLew	0:80ee8f3b695e	1348	/**
EricLew	0:80ee8f3b695e	1349	* @brief Set the auto-reload value.
EricLew	0:80ee8f3b695e	1350	* @note The counter is blocked while the auto-reload value is null.
EricLew	0:80ee8f3b695e	1351	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1352	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	1353	* @rmtoll ARR ARR LL_TIM_SetAutoReload
EricLew	0:80ee8f3b695e	1354	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1355	* @param AutoReload Between 0 and 65535
EricLew	0:80ee8f3b695e	1356	* @retval None
EricLew	0:80ee8f3b695e	1357	*/
EricLew	0:80ee8f3b695e	1358	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef * TIMx, uint32_t AutoReload)
EricLew	0:80ee8f3b695e	1359	{
EricLew	0:80ee8f3b695e	1360	WRITE_REG(TIMx->ARR, AutoReload);
EricLew	0:80ee8f3b695e	1361	}
EricLew	0:80ee8f3b695e	1362
EricLew	0:80ee8f3b695e	1363	/**
EricLew	0:80ee8f3b695e	1364	* @brief Get the auto-reload value.
EricLew	0:80ee8f3b695e	1365	* @rmtoll ARR ARR LL_TIM_GetAutoReload
EricLew	0:80ee8f3b695e	1366	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1367	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	1368	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1369	* @retval Auto-reload value
EricLew	0:80ee8f3b695e	1370	*/
EricLew	0:80ee8f3b695e	1371	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1372	{
EricLew	0:80ee8f3b695e	1373	return (uint32_t)(READ_REG(TIMx->ARR));
EricLew	0:80ee8f3b695e	1374	}
EricLew	0:80ee8f3b695e	1375
EricLew	0:80ee8f3b695e	1376	/**
EricLew	0:80ee8f3b695e	1377	* @brief Set the repetition counter value.
EricLew	0:80ee8f3b695e	1378	* @note For advanced timer instances RepetitionCounter can be up to 65535.
EricLew	0:80ee8f3b695e	1379	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1380	* whether or not a timer instance supports a repetition counter.
EricLew	0:80ee8f3b695e	1381	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
EricLew	0:80ee8f3b695e	1382	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1383	* @param RepetitionCounter Between 0 and 255
EricLew	0:80ee8f3b695e	1384	* @retval None
EricLew	0:80ee8f3b695e	1385	*/
EricLew	0:80ee8f3b695e	1386	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx, uint32_t RepetitionCounter)
EricLew	0:80ee8f3b695e	1387	{
EricLew	0:80ee8f3b695e	1388	WRITE_REG(TIMx->RCR, RepetitionCounter);
EricLew	0:80ee8f3b695e	1389	}
EricLew	0:80ee8f3b695e	1390
EricLew	0:80ee8f3b695e	1391	/**
EricLew	0:80ee8f3b695e	1392	* @brief Get the repetition counter value.
EricLew	0:80ee8f3b695e	1393	* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1394	* whether or not a timer instance supports a repetition counter.
EricLew	0:80ee8f3b695e	1395	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
EricLew	0:80ee8f3b695e	1396	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1397	* @retval Repetition counter value
EricLew	0:80ee8f3b695e	1398	*/
EricLew	0:80ee8f3b695e	1399	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1400	{
EricLew	0:80ee8f3b695e	1401	return (uint32_t)(READ_REG(TIMx->RCR));
EricLew	0:80ee8f3b695e	1402	}
EricLew	0:80ee8f3b695e	1403
EricLew	0:80ee8f3b695e	1404	/**
EricLew	0:80ee8f3b695e	1405	* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
EricLew	0:80ee8f3b695e	1406	* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
EricLew	0:80ee8f3b695e	1407	* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
EricLew	0:80ee8f3b695e	1408	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1409	* @retval None
EricLew	0:80ee8f3b695e	1410	*/
EricLew	0:80ee8f3b695e	1411	__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1412	{
EricLew	0:80ee8f3b695e	1413	SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
EricLew	0:80ee8f3b695e	1414	}
EricLew	0:80ee8f3b695e	1415
EricLew	0:80ee8f3b695e	1416	/**
EricLew	0:80ee8f3b695e	1417	* @brief Disable update interrupt flag (UIF) remapping.
EricLew	0:80ee8f3b695e	1418	* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
EricLew	0:80ee8f3b695e	1419	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1420	* @retval None
EricLew	0:80ee8f3b695e	1421	*/
EricLew	0:80ee8f3b695e	1422	__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1423	{
EricLew	0:80ee8f3b695e	1424	CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
EricLew	0:80ee8f3b695e	1425	}
EricLew	0:80ee8f3b695e	1426
EricLew	0:80ee8f3b695e	1427	/**
EricLew	0:80ee8f3b695e	1428	* @}
EricLew	0:80ee8f3b695e	1429	*/
EricLew	0:80ee8f3b695e	1430
EricLew	0:80ee8f3b695e	1431	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
EricLew	0:80ee8f3b695e	1432	* @{
EricLew	0:80ee8f3b695e	1433	*/
EricLew	0:80ee8f3b695e	1434	/**
EricLew	0:80ee8f3b695e	1435	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
EricLew	0:80ee8f3b695e	1436	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
EricLew	0:80ee8f3b695e	1437	* they are updated only when a commutation event (COM) occurs.
EricLew	0:80ee8f3b695e	1438	* @note Only on channels that have a complementary output.
EricLew	0:80ee8f3b695e	1439	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1440	* whether or not a timer instance is able to generate a commutation event.
EricLew	0:80ee8f3b695e	1441	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
EricLew	0:80ee8f3b695e	1442	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1443	* @retval None
EricLew	0:80ee8f3b695e	1444	*/
EricLew	0:80ee8f3b695e	1445	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1446	{
EricLew	0:80ee8f3b695e	1447	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
EricLew	0:80ee8f3b695e	1448	}
EricLew	0:80ee8f3b695e	1449
EricLew	0:80ee8f3b695e	1450	/**
EricLew	0:80ee8f3b695e	1451	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
EricLew	0:80ee8f3b695e	1452	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1453	* whether or not a timer instance is able to generate a commutation event.
EricLew	0:80ee8f3b695e	1454	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
EricLew	0:80ee8f3b695e	1455	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1456	* @retval None
EricLew	0:80ee8f3b695e	1457	*/
EricLew	0:80ee8f3b695e	1458	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	1459	{
EricLew	0:80ee8f3b695e	1460	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
EricLew	0:80ee8f3b695e	1461	}
EricLew	0:80ee8f3b695e	1462
EricLew	0:80ee8f3b695e	1463	/**
EricLew	0:80ee8f3b695e	1464	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
EricLew	0:80ee8f3b695e	1465	* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	1466	* whether or not a timer instance is able to generate a commutation event.
EricLew	0:80ee8f3b695e	1467	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
EricLew	0:80ee8f3b695e	1468	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1469	* @param CCUpdateSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1470	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
EricLew	0:80ee8f3b695e	1471	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
EricLew	0:80ee8f3b695e	1472	* @retval None
EricLew	0:80ee8f3b695e	1473	*/
EricLew	0:80ee8f3b695e	1474	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx, uint32_t CCUpdateSource)
EricLew	0:80ee8f3b695e	1475	{
EricLew	0:80ee8f3b695e	1476	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
EricLew	0:80ee8f3b695e	1477	}
EricLew	0:80ee8f3b695e	1478
EricLew	0:80ee8f3b695e	1479	/**
EricLew	0:80ee8f3b695e	1480	* @brief Set the trigger of the capture/compare DMA request.
EricLew	0:80ee8f3b695e	1481	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
EricLew	0:80ee8f3b695e	1482	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1483	* @param DMAReqTrigger This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1484	* @arg @ref LL_TIM_CCDMAREQUEST_CC
EricLew	0:80ee8f3b695e	1485	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
EricLew	0:80ee8f3b695e	1486	* @retval None
EricLew	0:80ee8f3b695e	1487	*/
EricLew	0:80ee8f3b695e	1488	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx, uint32_t DMAReqTrigger)
EricLew	0:80ee8f3b695e	1489	{
EricLew	0:80ee8f3b695e	1490	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
EricLew	0:80ee8f3b695e	1491	}
EricLew	0:80ee8f3b695e	1492
EricLew	0:80ee8f3b695e	1493	/**
EricLew	0:80ee8f3b695e	1494	* @brief Set the lock level to freeze the
EricLew	0:80ee8f3b695e	1495	* configuration of several capture/compare parameters.
EricLew	0:80ee8f3b695e	1496	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	1497	* the lock mechanism is supported by a timer instance.
EricLew	0:80ee8f3b695e	1498	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
EricLew	0:80ee8f3b695e	1499	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1500	* @param LockLevel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1501	* @arg @ref LL_TIM_LOCKLEVEL_OFF
EricLew	0:80ee8f3b695e	1502	* @arg @ref LL_TIM_LOCKLEVEL_1
EricLew	0:80ee8f3b695e	1503	* @arg @ref LL_TIM_LOCKLEVEL_2
EricLew	0:80ee8f3b695e	1504	* @arg @ref LL_TIM_LOCKLEVEL_3
EricLew	0:80ee8f3b695e	1505	* @retval None
EricLew	0:80ee8f3b695e	1506	*/
EricLew	0:80ee8f3b695e	1507	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx, uint32_t LockLevel)
EricLew	0:80ee8f3b695e	1508	{
EricLew	0:80ee8f3b695e	1509	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
EricLew	0:80ee8f3b695e	1510	}
EricLew	0:80ee8f3b695e	1511
EricLew	0:80ee8f3b695e	1512	/**
EricLew	0:80ee8f3b695e	1513	* @brief Enable capture/compare channels.
EricLew	0:80ee8f3b695e	1514	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1515	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1516	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1517	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1518	* CCER CC1NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1519	* CCER CC2E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1520	* CCER CC2NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1521	* CCER CC3E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1522	* CCER CC3NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1523	* CCER CC4E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1524	* CCER CC5E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1525	* CCER CC6E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1526	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1527	* @param Channels This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1528	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1529	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1530	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1531	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1532	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1533	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1534	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1535	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1536	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1537	* @retval None
EricLew	0:80ee8f3b695e	1538	*/
EricLew	0:80ee8f3b695e	1539	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
EricLew	0:80ee8f3b695e	1540	{
EricLew	0:80ee8f3b695e	1541	SET_BIT(TIMx->CCER, Channels);
EricLew	0:80ee8f3b695e	1542	}
EricLew	0:80ee8f3b695e	1543
EricLew	0:80ee8f3b695e	1544	/**
EricLew	0:80ee8f3b695e	1545	* @brief Disable capture/compare channels.
EricLew	0:80ee8f3b695e	1546	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1547	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1548	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1549	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1550	* CCER CC1NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1551	* CCER CC2E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1552	* CCER CC2NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1553	* CCER CC3E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1554	* CCER CC3NE LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1555	* CCER CC4E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1556	* CCER CC5E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1557	* CCER CC6E LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1558	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1559	* @param Channels This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1560	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1561	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1562	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1563	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1564	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1565	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1566	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1567	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1568	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1569	* @retval None
EricLew	0:80ee8f3b695e	1570	*/
EricLew	0:80ee8f3b695e	1571	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx, uint32_t Channels)
EricLew	0:80ee8f3b695e	1572	{
EricLew	0:80ee8f3b695e	1573	CLEAR_BIT(TIMx->CCER, Channels);
EricLew	0:80ee8f3b695e	1574	}
EricLew	0:80ee8f3b695e	1575
EricLew	0:80ee8f3b695e	1576	/**
EricLew	0:80ee8f3b695e	1577	* @}
EricLew	0:80ee8f3b695e	1578	*/
EricLew	0:80ee8f3b695e	1579
EricLew	0:80ee8f3b695e	1580	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
EricLew	0:80ee8f3b695e	1581	* @{
EricLew	0:80ee8f3b695e	1582	*/
EricLew	0:80ee8f3b695e	1583	/**
EricLew	0:80ee8f3b695e	1584	* @brief Configure an output channel.
EricLew	0:80ee8f3b695e	1585	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1586	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1587	* @rmtoll CCMR1 OC1M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1588	* CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1589	* CCMR1 OC2M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1590	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1591	* CCMR2 OC3M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1592	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1593	* CCMR2 OC4M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1594	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1595	* CCMR3 OC5M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1596	* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1597	* CCMR3 OC6M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1598	* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1599	* CCER OC1P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1600	* CCER OC2P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1601	* CCER OC3P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1602	* CCER OC4P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1603	* CCER OC5P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1604	* CCER OC6P LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1605	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1606	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1607	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1608	* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1609	* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1610	* CR2 OIS6 LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1611	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1612	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1613	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1614	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1615	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1616	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1617	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1618	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1619	* @param Configuration This parameter must be a combination of all the following values:
EricLew	0:80ee8f3b695e	1620	* @arg @ref LL_TIM_OCMODE_FROZEN or ... or @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
EricLew	0:80ee8f3b695e	1621	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
EricLew	0:80ee8f3b695e	1622	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
EricLew	0:80ee8f3b695e	1623	* @retval None
EricLew	0:80ee8f3b695e	1624	*/
EricLew	0:80ee8f3b695e	1625	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
EricLew	0:80ee8f3b695e	1626	{
EricLew	0:80ee8f3b695e	1627	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1628	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1629	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), (Configuration & (TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S)) << SHIFT_TAB_OCxx[iChannel]);
EricLew	0:80ee8f3b695e	1630	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	1631	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
EricLew	0:80ee8f3b695e	1632	}
EricLew	0:80ee8f3b695e	1633
EricLew	0:80ee8f3b695e	1634	/**
EricLew	0:80ee8f3b695e	1635	* @brief Configure a complementary output channel.
EricLew	0:80ee8f3b695e	1636	* @note Macro IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1637	* or not a complementary channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1638	* @rmtoll CCER CC1NP LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1639	* CCER CC2NP LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1640	* CCER CC3NP LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1641	* CR2 OIS1N LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1642	* CR2 OIS2N LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1643	* CR2 OIS3N LL_TIM_OC_ConfigOutputN\n
EricLew	0:80ee8f3b695e	1644	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1645	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1646	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1647	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1648	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1649	* @param Polarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1650	* @arg @ref LL_TIM_OCPOLARITY_HIGH
EricLew	0:80ee8f3b695e	1651	* @arg @ref LL_TIM_OCPOLARITY_LOW
EricLew	0:80ee8f3b695e	1652	* @param IdleState This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1653	* @arg @ref LL_TIM_OCIDLESTATE_LOW
EricLew	0:80ee8f3b695e	1654	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
EricLew	0:80ee8f3b695e	1655	* @retval None
EricLew	0:80ee8f3b695e	1656	*/
EricLew	0:80ee8f3b695e	1657	__STATIC_INLINE void LL_TIM_OC_ConfigOutputN(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity, uint32_t IdleState)
EricLew	0:80ee8f3b695e	1658	{
EricLew	0:80ee8f3b695e	1659	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1660	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	1661	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
EricLew	0:80ee8f3b695e	1662	}
EricLew	0:80ee8f3b695e	1663
EricLew	0:80ee8f3b695e	1664	/**
EricLew	0:80ee8f3b695e	1665	* @brief Set the output compare mode of an output channel.
EricLew	0:80ee8f3b695e	1666	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1667	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1668	* @rmtoll CCMR1 OC1M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1669	* CCMR1 OC2M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1670	* CCMR2 OC3M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1671	* CCMR2 OC4M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1672	* CCMR3 OC5M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1673	* CCMR3 OC6M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1674	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1675	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1676	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1677	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1678	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1679	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1680	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1681	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1682	* @param Mode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1683	* @arg @ref LL_TIM_OCMODE_FROZEN
EricLew	0:80ee8f3b695e	1684	* @arg @ref LL_TIM_OCMODE_ACTIVE
EricLew	0:80ee8f3b695e	1685	* @arg @ref LL_TIM_OCMODE_INACTIVE
EricLew	0:80ee8f3b695e	1686	* @arg @ref LL_TIM_OCMODE_TOGGLE
EricLew	0:80ee8f3b695e	1687	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
EricLew	0:80ee8f3b695e	1688	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
EricLew	0:80ee8f3b695e	1689	* @arg @ref LL_TIM_OCMODE_PWM1
EricLew	0:80ee8f3b695e	1690	* @arg @ref LL_TIM_OCMODE_PWM2
EricLew	0:80ee8f3b695e	1691	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
EricLew	0:80ee8f3b695e	1692	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
EricLew	0:80ee8f3b695e	1693	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
EricLew	0:80ee8f3b695e	1694	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
EricLew	0:80ee8f3b695e	1695	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
EricLew	0:80ee8f3b695e	1696	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
EricLew	0:80ee8f3b695e	1697	* @retval None
EricLew	0:80ee8f3b695e	1698	*/
EricLew	0:80ee8f3b695e	1699	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Mode)
EricLew	0:80ee8f3b695e	1700	{
EricLew	0:80ee8f3b695e	1701	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1702	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1703	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
EricLew	0:80ee8f3b695e	1704	}
EricLew	0:80ee8f3b695e	1705
EricLew	0:80ee8f3b695e	1706	/**
EricLew	0:80ee8f3b695e	1707	* @brief Get the output compare mode of an output channel.
EricLew	0:80ee8f3b695e	1708	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1709	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1710	* @rmtoll CCMR1 OC1M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1711	* CCMR1 OC2M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1712	* CCMR2 OC3M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1713	* CCMR2 OC4M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1714	* CCMR3 OC5M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1715	* CCMR3 OC6M LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1716	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1717	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1718	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1719	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1720	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1721	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1722	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1723	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1724	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1725	* @arg @ref LL_TIM_OCMODE_FROZEN
EricLew	0:80ee8f3b695e	1726	* @arg @ref LL_TIM_OCMODE_ACTIVE
EricLew	0:80ee8f3b695e	1727	* @arg @ref LL_TIM_OCMODE_INACTIVE
EricLew	0:80ee8f3b695e	1728	* @arg @ref LL_TIM_OCMODE_TOGGLE
EricLew	0:80ee8f3b695e	1729	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
EricLew	0:80ee8f3b695e	1730	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
EricLew	0:80ee8f3b695e	1731	* @arg @ref LL_TIM_OCMODE_PWM1
EricLew	0:80ee8f3b695e	1732	* @arg @ref LL_TIM_OCMODE_PWM2
EricLew	0:80ee8f3b695e	1733	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
EricLew	0:80ee8f3b695e	1734	* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
EricLew	0:80ee8f3b695e	1735	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
EricLew	0:80ee8f3b695e	1736	* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
EricLew	0:80ee8f3b695e	1737	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
EricLew	0:80ee8f3b695e	1738	* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
EricLew	0:80ee8f3b695e	1739	*/
EricLew	0:80ee8f3b695e	1740	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1741	{
EricLew	0:80ee8f3b695e	1742	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1743	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1744	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
EricLew	0:80ee8f3b695e	1745	}
EricLew	0:80ee8f3b695e	1746
EricLew	0:80ee8f3b695e	1747	/**
EricLew	0:80ee8f3b695e	1748	* @brief Set the polarity of an output channel.
EricLew	0:80ee8f3b695e	1749	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1750	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1751	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1752	* @rmtoll CCER CC1P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1753	* CCER CC1NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1754	* CCER CC2P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1755	* CCER CC2NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1756	* CCER CC3P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1757	* CCER CC3NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1758	* CCER CC4P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1759	* CCER CC5P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1760	* CCER CC6P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1761	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1762	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1763	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1764	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1765	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1766	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1767	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1768	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1769	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1770	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1771	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1772	* @param Polarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1773	* @arg @ref LL_TIM_OCPOLARITY_HIGH
EricLew	0:80ee8f3b695e	1774	* @arg @ref LL_TIM_OCPOLARITY_LOW
EricLew	0:80ee8f3b695e	1775	* @retval None
EricLew	0:80ee8f3b695e	1776	*/
EricLew	0:80ee8f3b695e	1777	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Polarity)
EricLew	0:80ee8f3b695e	1778	{
EricLew	0:80ee8f3b695e	1779	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1780	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	1781	}
EricLew	0:80ee8f3b695e	1782
EricLew	0:80ee8f3b695e	1783	/**
EricLew	0:80ee8f3b695e	1784	* @brief Get the polarity of an output channel.
EricLew	0:80ee8f3b695e	1785	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1786	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1787	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1788	* @rmtoll CCER CC1P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1789	* CCER CC1NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1790	* CCER CC2P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1791	* CCER CC2NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1792	* CCER CC3P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1793	* CCER CC3NP LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1794	* CCER CC4P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1795	* CCER CC5P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1796	* CCER CC6P LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1797	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1798	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1799	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1800	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1801	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1802	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1803	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1804	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1805	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1806	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1807	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1808	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1809	* @arg @ref LL_TIM_OCPOLARITY_HIGH
EricLew	0:80ee8f3b695e	1810	* @arg @ref LL_TIM_OCPOLARITY_LOW
EricLew	0:80ee8f3b695e	1811	*/
EricLew	0:80ee8f3b695e	1812	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1813	{
EricLew	0:80ee8f3b695e	1814	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1815	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	1816	}
EricLew	0:80ee8f3b695e	1817
EricLew	0:80ee8f3b695e	1818	/**
EricLew	0:80ee8f3b695e	1819	* @brief Set the IDLE state of an output channel
EricLew	0:80ee8f3b695e	1820	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1821	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1822	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1823	* @rmtoll CR2 OIS1 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1824	* CR2 OIS2N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1825	* CR2 OIS2 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1826	* CR2 OIS2N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1827	* CR2 OIS3 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1828	* CR2 OIS3N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1829	* CR2 OIS4 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1830	* CR2 OIS5 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1831	* CR2 OIS6 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1832	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1833	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1834	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1835	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1836	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1837	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1838	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1839	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1840	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1841	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1842	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1843	* @param IdleState This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1844	* @arg @ref LL_TIM_OCIDLESTATE_LOW
EricLew	0:80ee8f3b695e	1845	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
EricLew	0:80ee8f3b695e	1846	* @retval None
EricLew	0:80ee8f3b695e	1847	*/
EricLew	0:80ee8f3b695e	1848	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t IdleState)
EricLew	0:80ee8f3b695e	1849	{
EricLew	0:80ee8f3b695e	1850	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1851	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
EricLew	0:80ee8f3b695e	1852	}
EricLew	0:80ee8f3b695e	1853
EricLew	0:80ee8f3b695e	1854	/**
EricLew	0:80ee8f3b695e	1855	* @brief Get the IDLE state of an output channel
EricLew	0:80ee8f3b695e	1856	* @note Macros IS_TIM_CCX_INSTANCE(TIMx, Channel) or
EricLew	0:80ee8f3b695e	1857	* IS_TIM_CCXN_INSTANCE(TIMx, Channel) can be used to check whether or not
EricLew	0:80ee8f3b695e	1858	* a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1859	* @rmtoll CR2 OIS1 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1860	* CR2 OIS2N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1861	* CR2 OIS2 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1862	* CR2 OIS2N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1863	* CR2 OIS3 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1864	* CR2 OIS3N LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1865	* CR2 OIS4 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1866	* CR2 OIS5 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1867	* CR2 OIS6 LL_TIM_CC_EnableChannel\n
EricLew	0:80ee8f3b695e	1868	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1869	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1870	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1871	* @arg @ref LL_TIM_CHANNEL_CH1N
EricLew	0:80ee8f3b695e	1872	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1873	* @arg @ref LL_TIM_CHANNEL_CH2N
EricLew	0:80ee8f3b695e	1874	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1875	* @arg @ref LL_TIM_CHANNEL_CH3N
EricLew	0:80ee8f3b695e	1876	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1877	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1878	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1879	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1880	* @arg @ref LL_TIM_OCIDLESTATE_LOW
EricLew	0:80ee8f3b695e	1881	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
EricLew	0:80ee8f3b695e	1882	*/
EricLew	0:80ee8f3b695e	1883	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1884	{
EricLew	0:80ee8f3b695e	1885	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1886	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
EricLew	0:80ee8f3b695e	1887	}
EricLew	0:80ee8f3b695e	1888
EricLew	0:80ee8f3b695e	1889	/**
EricLew	0:80ee8f3b695e	1890	* @brief Enable fast mode for the output channel.
EricLew	0:80ee8f3b695e	1891	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
EricLew	0:80ee8f3b695e	1892	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1893	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1894	* @rmtoll CCMR1 OC1FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1895	* CCMR1 OC2FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1896	* CCMR2 OC3FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1897	* CCMR2 OC4FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1898	* CCMR3 OC5FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1899	* CCMR3 OC6FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1900	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1901	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1902	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1903	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1904	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1905	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1906	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1907	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1908	* @retval None
EricLew	0:80ee8f3b695e	1909	*/
EricLew	0:80ee8f3b695e	1910	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1911	{
EricLew	0:80ee8f3b695e	1912	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1913	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1914	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	1915
EricLew	0:80ee8f3b695e	1916	}
EricLew	0:80ee8f3b695e	1917
EricLew	0:80ee8f3b695e	1918	/**
EricLew	0:80ee8f3b695e	1919	* @brief Disable fast mode for the output channel.
EricLew	0:80ee8f3b695e	1920	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1921	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1922	* @rmtoll CCMR1 OC1FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1923	* CCMR1 OC2FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1924	* CCMR2 OC3FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1925	* CCMR2 OC4FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1926	* CCMR3 OC5FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1927	* CCMR3 OC6FE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1928	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1929	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1930	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1931	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1932	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1933	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1934	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1935	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1936	* @retval None
EricLew	0:80ee8f3b695e	1937	*/
EricLew	0:80ee8f3b695e	1938	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1939	{
EricLew	0:80ee8f3b695e	1940	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1941	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1942	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	1943
EricLew	0:80ee8f3b695e	1944	}
EricLew	0:80ee8f3b695e	1945
EricLew	0:80ee8f3b695e	1946	/**
EricLew	0:80ee8f3b695e	1947	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
EricLew	0:80ee8f3b695e	1948	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1949	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1950	* @rmtoll CCMR1 OC1PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1951	* CCMR1 OC2PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1952	* CCMR2 OC3PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1953	* CCMR2 OC4PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1954	* CCMR3 OC5PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1955	* CCMR3 OC6PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1956	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1957	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1958	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1959	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1960	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1961	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1962	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1963	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1964	* @retval None
EricLew	0:80ee8f3b695e	1965	*/
EricLew	0:80ee8f3b695e	1966	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1967	{
EricLew	0:80ee8f3b695e	1968	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1969	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1970	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	1971	}
EricLew	0:80ee8f3b695e	1972
EricLew	0:80ee8f3b695e	1973	/**
EricLew	0:80ee8f3b695e	1974	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
EricLew	0:80ee8f3b695e	1975	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	1976	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	1977	* @rmtoll CCMR1 OC1PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1978	* CCMR1 OC2PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1979	* CCMR2 OC3PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1980	* CCMR2 OC4PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1981	* CCMR3 OC5PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1982	* CCMR3 OC6PE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	1983	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	1984	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1985	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	1986	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	1987	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	1988	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	1989	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	1990	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	1991	* @retval None
EricLew	0:80ee8f3b695e	1992	*/
EricLew	0:80ee8f3b695e	1993	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	1994	{
EricLew	0:80ee8f3b695e	1995	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	1996	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	1997	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	1998
EricLew	0:80ee8f3b695e	1999	}
EricLew	0:80ee8f3b695e	2000
EricLew	0:80ee8f3b695e	2001	/**
EricLew	0:80ee8f3b695e	2002	* @brief Enable clearing the output channel on an external event.
EricLew	0:80ee8f3b695e	2003	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
EricLew	0:80ee8f3b695e	2004	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
EricLew	0:80ee8f3b695e	2005	* or not a timer instance can clear the OCxREF signal on an external event.
EricLew	0:80ee8f3b695e	2006	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2007	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2008	* @rmtoll CCMR1 OC1CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2009	* CCMR1 OC2CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2010	* CCMR2 OC3CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2011	* CCMR2 OC4CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2012	* CCMR3 OC5CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2013	* CCMR3 OC6CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2014	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2015	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2016	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2017	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2018	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2019	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2020	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	2021	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	2022	* @retval None
EricLew	0:80ee8f3b695e	2023	*/
EricLew	0:80ee8f3b695e	2024	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2025	{
EricLew	0:80ee8f3b695e	2026	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2027	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2028	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	2029	}
EricLew	0:80ee8f3b695e	2030
EricLew	0:80ee8f3b695e	2031	/**
EricLew	0:80ee8f3b695e	2032	* @brief Disable clearing the output channel on an external event.
EricLew	0:80ee8f3b695e	2033	* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
EricLew	0:80ee8f3b695e	2034	* or not a timer instance can clear the OCxREF signal on an external event.
EricLew	0:80ee8f3b695e	2035	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2036	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2037	* @rmtoll CCMR1 OC1CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2038	* CCMR1 OC2CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2039	* CCMR2 OC3CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2040	* CCMR2 OC4CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2041	* CCMR3 OC5CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2042	* CCMR3 OC6CE LL_TIM_OC_ConfigOutput\n
EricLew	0:80ee8f3b695e	2043	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2044	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2045	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2046	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2047	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2048	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2049	* @arg @ref LL_TIM_CHANNEL_CH5
EricLew	0:80ee8f3b695e	2050	* @arg @ref LL_TIM_CHANNEL_CH6
EricLew	0:80ee8f3b695e	2051	* @retval None
EricLew	0:80ee8f3b695e	2052	*/
EricLew	0:80ee8f3b695e	2053	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2054	{
EricLew	0:80ee8f3b695e	2055	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2056	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2057	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
EricLew	0:80ee8f3b695e	2058	}
EricLew	0:80ee8f3b695e	2059
EricLew	0:80ee8f3b695e	2060	/**
EricLew	0:80ee8f3b695e	2061	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
EricLew	0:80ee8f3b695e	2062	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2063	* dead-time insertion feature is supported by a timer instance.
EricLew	0:80ee8f3b695e	2064	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
EricLew	0:80ee8f3b695e	2065	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2066	* @param DeadTime Between 0 and 255
EricLew	0:80ee8f3b695e	2067	* @retval None
EricLew	0:80ee8f3b695e	2068	*/
EricLew	0:80ee8f3b695e	2069	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx, uint32_t DeadTime)
EricLew	0:80ee8f3b695e	2070	{
EricLew	0:80ee8f3b695e	2071	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
EricLew	0:80ee8f3b695e	2072	}
EricLew	0:80ee8f3b695e	2073
EricLew	0:80ee8f3b695e	2074	/**
EricLew	0:80ee8f3b695e	2075	* @brief Set compare value for output channel 1 (TIMx_CCR1)
EricLew	0:80ee8f3b695e	2076	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2077	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2078	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2079	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2080	* output channel 1 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2081	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
EricLew	0:80ee8f3b695e	2082	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2083	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2084	* @retval None
EricLew	0:80ee8f3b695e	2085	*/
EricLew	0:80ee8f3b695e	2086	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2087	{
EricLew	0:80ee8f3b695e	2088	WRITE_REG(TIMx->CCR1, CompareValue);
EricLew	0:80ee8f3b695e	2089	}
EricLew	0:80ee8f3b695e	2090
EricLew	0:80ee8f3b695e	2091	/**
EricLew	0:80ee8f3b695e	2092	* @brief Set compare value for output channel 2 (TIMx_CCR2)
EricLew	0:80ee8f3b695e	2093	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2094	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2095	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2096	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2097	* output channel 2 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2098	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
EricLew	0:80ee8f3b695e	2099	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2100	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2101	* @retval None
EricLew	0:80ee8f3b695e	2102	*/
EricLew	0:80ee8f3b695e	2103	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2104	{
EricLew	0:80ee8f3b695e	2105	WRITE_REG(TIMx->CCR2, CompareValue);
EricLew	0:80ee8f3b695e	2106	}
EricLew	0:80ee8f3b695e	2107
EricLew	0:80ee8f3b695e	2108	/**
EricLew	0:80ee8f3b695e	2109	* @brief Set compare value for output channel 3 (TIMx_CCR3)
EricLew	0:80ee8f3b695e	2110	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2111	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2112	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2113	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2114	* output channel is supported by a timer instance.
EricLew	0:80ee8f3b695e	2115	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
EricLew	0:80ee8f3b695e	2116	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2117	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2118	* @retval None
EricLew	0:80ee8f3b695e	2119	*/
EricLew	0:80ee8f3b695e	2120	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2121	{
EricLew	0:80ee8f3b695e	2122	WRITE_REG(TIMx->CCR3, CompareValue);
EricLew	0:80ee8f3b695e	2123	}
EricLew	0:80ee8f3b695e	2124
EricLew	0:80ee8f3b695e	2125	/**
EricLew	0:80ee8f3b695e	2126	* @brief Set compare value for output channel 4 (TIMx_CCR4)
EricLew	0:80ee8f3b695e	2127	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2128	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2129	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2130	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2131	* output channel 4 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2132	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
EricLew	0:80ee8f3b695e	2133	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2134	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2135	* @retval None
EricLew	0:80ee8f3b695e	2136	*/
EricLew	0:80ee8f3b695e	2137	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2138	{
EricLew	0:80ee8f3b695e	2139	WRITE_REG(TIMx->CCR4, CompareValue);
EricLew	0:80ee8f3b695e	2140	}
EricLew	0:80ee8f3b695e	2141
EricLew	0:80ee8f3b695e	2142	/**
EricLew	0:80ee8f3b695e	2143	* @brief Set compare value for output channel 5 (TIMx_CCR5)
EricLew	0:80ee8f3b695e	2144	* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2145	* output channel 5 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2146	* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
EricLew	0:80ee8f3b695e	2147	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2148	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2149	* @retval None
EricLew	0:80ee8f3b695e	2150	*/
EricLew	0:80ee8f3b695e	2151	__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2152	{
EricLew	0:80ee8f3b695e	2153	WRITE_REG(TIMx->CCR5, CompareValue);
EricLew	0:80ee8f3b695e	2154	}
EricLew	0:80ee8f3b695e	2155
EricLew	0:80ee8f3b695e	2156	/**
EricLew	0:80ee8f3b695e	2157	* @brief Set compare value for output channel 6 (TIMx_CCR6)
EricLew	0:80ee8f3b695e	2158	* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2159	* output channel 6 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2160	* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
EricLew	0:80ee8f3b695e	2161	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2162	* @param CompareValue Between 0 and 65535
EricLew	0:80ee8f3b695e	2163	* @retval None
EricLew	0:80ee8f3b695e	2164	*/
EricLew	0:80ee8f3b695e	2165	__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef * TIMx, uint32_t CompareValue)
EricLew	0:80ee8f3b695e	2166	{
EricLew	0:80ee8f3b695e	2167	WRITE_REG(TIMx->CCR6, CompareValue);
EricLew	0:80ee8f3b695e	2168	}
EricLew	0:80ee8f3b695e	2169
EricLew	0:80ee8f3b695e	2170	/**
EricLew	0:80ee8f3b695e	2171	* @brief Get compare value (TIMx_CCR1) set for output channel 1
EricLew	0:80ee8f3b695e	2172	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2173	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2174	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2175	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2176	* output channel 1 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2177	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
EricLew	0:80ee8f3b695e	2178	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2179	* @retval CompareValue
EricLew	0:80ee8f3b695e	2180	*/
EricLew	0:80ee8f3b695e	2181	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2182	{
EricLew	0:80ee8f3b695e	2183	return (uint32_t)(READ_REG(TIMx->CCR1));
EricLew	0:80ee8f3b695e	2184	}
EricLew	0:80ee8f3b695e	2185
EricLew	0:80ee8f3b695e	2186	/**
EricLew	0:80ee8f3b695e	2187	* @brief Get compare value (TIMx_CCR2) set for output channel 2
EricLew	0:80ee8f3b695e	2188	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2189	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2190	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2191	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2192	* output channel 2 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2193	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
EricLew	0:80ee8f3b695e	2194	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2195	* @retval CompareValue
EricLew	0:80ee8f3b695e	2196	*/
EricLew	0:80ee8f3b695e	2197	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2198	{
EricLew	0:80ee8f3b695e	2199	return (uint32_t)(READ_REG(TIMx->CCR2));
EricLew	0:80ee8f3b695e	2200	}
EricLew	0:80ee8f3b695e	2201
EricLew	0:80ee8f3b695e	2202	/**
EricLew	0:80ee8f3b695e	2203	* @brief Get compare value (TIMx_CCR3) set for output channel 3
EricLew	0:80ee8f3b695e	2204	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2205	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2206	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2207	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2208	* output channel 3 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2209	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
EricLew	0:80ee8f3b695e	2210	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2211	* @retval CompareValue
EricLew	0:80ee8f3b695e	2212	*/
EricLew	0:80ee8f3b695e	2213	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2214	{
EricLew	0:80ee8f3b695e	2215	return (uint32_t)(READ_REG(TIMx->CCR3));
EricLew	0:80ee8f3b695e	2216	}
EricLew	0:80ee8f3b695e	2217
EricLew	0:80ee8f3b695e	2218	/**
EricLew	0:80ee8f3b695e	2219	* @brief Get compare value (TIMx_CCR4) set for output channel 4
EricLew	0:80ee8f3b695e	2220	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2221	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2222	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2223	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2224	* output channel 4 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2225	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
EricLew	0:80ee8f3b695e	2226	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2227	* @retval CompareValue
EricLew	0:80ee8f3b695e	2228	*/
EricLew	0:80ee8f3b695e	2229	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2230	{
EricLew	0:80ee8f3b695e	2231	return (uint32_t)(READ_REG(TIMx->CCR4));
EricLew	0:80ee8f3b695e	2232	}
EricLew	0:80ee8f3b695e	2233
EricLew	0:80ee8f3b695e	2234	/**
EricLew	0:80ee8f3b695e	2235	* @brief Get compare value (TIMx_CCR5) set for output channel 5
EricLew	0:80ee8f3b695e	2236	* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2237	* output channel 5 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2238	* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
EricLew	0:80ee8f3b695e	2239	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2240	* @retval CompareValue
EricLew	0:80ee8f3b695e	2241	*/
EricLew	0:80ee8f3b695e	2242	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2243	{
EricLew	0:80ee8f3b695e	2244	return (uint32_t)(READ_REG(TIMx->CCR5));
EricLew	0:80ee8f3b695e	2245	}
EricLew	0:80ee8f3b695e	2246
EricLew	0:80ee8f3b695e	2247	/**
EricLew	0:80ee8f3b695e	2248	* @brief Get compare value (TIMx_CCR6) set for output channel 6
EricLew	0:80ee8f3b695e	2249	* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2250	* output channel 6 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2251	* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
EricLew	0:80ee8f3b695e	2252	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2253	* @retval CompareValue
EricLew	0:80ee8f3b695e	2254	*/
EricLew	0:80ee8f3b695e	2255	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2256	{
EricLew	0:80ee8f3b695e	2257	return (uint32_t)(READ_REG(TIMx->CCR6));
EricLew	0:80ee8f3b695e	2258	}
EricLew	0:80ee8f3b695e	2259
EricLew	0:80ee8f3b695e	2260	/**
EricLew	0:80ee8f3b695e	2261	* @brief Select on which reference signal the OC5REF is combined to.
EricLew	0:80ee8f3b695e	2262	* @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2263	* whether or not a timer instance supports the combined 3-phase PWM mode.
EricLew	0:80ee8f3b695e	2264	* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
EricLew	0:80ee8f3b695e	2265	* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
EricLew	0:80ee8f3b695e	2266	* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels\n
EricLew	0:80ee8f3b695e	2267	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2268	* @param GroupCH5 This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2269	* @arg @ref LL_TIM_GROUPCH5_NONE
EricLew	0:80ee8f3b695e	2270	* @arg @ref LL_TIM_GROUPCH5_OC1REFC
EricLew	0:80ee8f3b695e	2271	* @arg @ref LL_TIM_GROUPCH5_OC2REFC
EricLew	0:80ee8f3b695e	2272	* @arg @ref LL_TIM_GROUPCH5_OC3REFC
EricLew	0:80ee8f3b695e	2273	* @retval None
EricLew	0:80ee8f3b695e	2274	*/
EricLew	0:80ee8f3b695e	2275	__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef * TIMx, uint32_t GroupCH5)
EricLew	0:80ee8f3b695e	2276	{
EricLew	0:80ee8f3b695e	2277	MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
EricLew	0:80ee8f3b695e	2278	}
EricLew	0:80ee8f3b695e	2279
EricLew	0:80ee8f3b695e	2280	/**
EricLew	0:80ee8f3b695e	2281	* @}
EricLew	0:80ee8f3b695e	2282	*/
EricLew	0:80ee8f3b695e	2283
EricLew	0:80ee8f3b695e	2284	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
EricLew	0:80ee8f3b695e	2285	* @{
EricLew	0:80ee8f3b695e	2286	*/
EricLew	0:80ee8f3b695e	2287	/**
EricLew	0:80ee8f3b695e	2288	* @brief Configure input channel.
EricLew	0:80ee8f3b695e	2289	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2290	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2291	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2292	* CCMR1 IC1PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2293	* CCMR1 IC1F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2294	* CCMR1 CC2S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2295	* CCMR1 IC2PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2296	* CCMR1 IC2F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2297	* CCMR2 CC3S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2298	* CCMR2 IC3PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2299	* CCMR2 IC3F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2300	* CCMR2 CC4S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2301	* CCMR2 IC4PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2302	* CCMR2 IC4F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2303	* CCER CC1P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2304	* CCER CC1NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2305	* CCER CC2P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2306	* CCER CC2NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2307	* CCER CC3P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2308	* CCER CC3NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2309	* CCER CC4P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2310	* CCER CC4NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2311	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2312	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2313	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2314	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2315	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2316	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2317	* @param Configuration This parameter must be a combination of all the following values:
EricLew	0:80ee8f3b695e	2318	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
EricLew	0:80ee8f3b695e	2319	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
EricLew	0:80ee8f3b695e	2320	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	2321	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
EricLew	0:80ee8f3b695e	2322	* @retval None
EricLew	0:80ee8f3b695e	2323	*/
EricLew	0:80ee8f3b695e	2324	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t Configuration)
EricLew	0:80ee8f3b695e	2325	{
EricLew	0:80ee8f3b695e	2326	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2327	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2328	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
EricLew	0:80ee8f3b695e	2329	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	2330	}
EricLew	0:80ee8f3b695e	2331
EricLew	0:80ee8f3b695e	2332	/**
EricLew	0:80ee8f3b695e	2333	* @brief Set the active input
EricLew	0:80ee8f3b695e	2334	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2335	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2336	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2337	* CCMR1 CC2S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2338	* CCMR2 CC3S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2339	* CCMR2 CC4S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2340	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2341	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2342	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2343	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2344	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2345	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2346	* @param ICActiveInput This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2347	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
EricLew	0:80ee8f3b695e	2348	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
EricLew	0:80ee8f3b695e	2349	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
EricLew	0:80ee8f3b695e	2350	* @retval None
EricLew	0:80ee8f3b695e	2351	*/
EricLew	0:80ee8f3b695e	2352	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICActiveInput)
EricLew	0:80ee8f3b695e	2353	{
EricLew	0:80ee8f3b695e	2354	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2355	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2356	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16) << SHIFT_TAB_ICxx[iChannel]);
EricLew	0:80ee8f3b695e	2357	}
EricLew	0:80ee8f3b695e	2358
EricLew	0:80ee8f3b695e	2359	/**
EricLew	0:80ee8f3b695e	2360	* @brief Get the current active input
EricLew	0:80ee8f3b695e	2361	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2362	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2363	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2364	* CCMR1 CC2S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2365	* CCMR2 CC3S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2366	* CCMR2 CC4S LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2367	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2368	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2369	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2370	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2371	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2372	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2373	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2374	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
EricLew	0:80ee8f3b695e	2375	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
EricLew	0:80ee8f3b695e	2376	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
EricLew	0:80ee8f3b695e	2377	*/
EricLew	0:80ee8f3b695e	2378	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2379	{
EricLew	0:80ee8f3b695e	2380	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2381	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2382	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16);
EricLew	0:80ee8f3b695e	2383	}
EricLew	0:80ee8f3b695e	2384
EricLew	0:80ee8f3b695e	2385	/**
EricLew	0:80ee8f3b695e	2386	* @brief Set the prescaler of input channel
EricLew	0:80ee8f3b695e	2387	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2388	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2389	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2390	* CCMR1 IC2PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2391	* CCMR2 IC3PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2392	* CCMR2 IC4PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2393	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2394	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2395	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2396	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2397	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2398	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2399	* @param ICPrescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2400	* @arg @ref LL_TIM_ICPSC_DIV1
EricLew	0:80ee8f3b695e	2401	* @arg @ref LL_TIM_ICPSC_DIV2
EricLew	0:80ee8f3b695e	2402	* @arg @ref LL_TIM_ICPSC_DIV4
EricLew	0:80ee8f3b695e	2403	* @arg @ref LL_TIM_ICPSC_DIV8
EricLew	0:80ee8f3b695e	2404	* @retval None
EricLew	0:80ee8f3b695e	2405	*/
EricLew	0:80ee8f3b695e	2406	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPrescaler)
EricLew	0:80ee8f3b695e	2407	{
EricLew	0:80ee8f3b695e	2408	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2409	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2410	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16) << SHIFT_TAB_ICxx[iChannel]);
EricLew	0:80ee8f3b695e	2411	}
EricLew	0:80ee8f3b695e	2412
EricLew	0:80ee8f3b695e	2413	/**
EricLew	0:80ee8f3b695e	2414	* @brief Get the current prescaler value acting on an input channel
EricLew	0:80ee8f3b695e	2415	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2416	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2417	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2418	* CCMR1 IC2PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2419	* CCMR2 IC3PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2420	* CCMR2 IC4PSC LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2421	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2422	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2423	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2424	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2425	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2426	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2427	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2428	* @arg @ref LL_TIM_ICPSC_DIV1
EricLew	0:80ee8f3b695e	2429	* @arg @ref LL_TIM_ICPSC_DIV2
EricLew	0:80ee8f3b695e	2430	* @arg @ref LL_TIM_ICPSC_DIV4
EricLew	0:80ee8f3b695e	2431	* @arg @ref LL_TIM_ICPSC_DIV8
EricLew	0:80ee8f3b695e	2432	*/
EricLew	0:80ee8f3b695e	2433	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2434	{
EricLew	0:80ee8f3b695e	2435	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2436	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2437	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16);
EricLew	0:80ee8f3b695e	2438	}
EricLew	0:80ee8f3b695e	2439
EricLew	0:80ee8f3b695e	2440	/**
EricLew	0:80ee8f3b695e	2441	* @brief Set the input filter duration
EricLew	0:80ee8f3b695e	2442	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2443	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2444	* @rmtoll CCMR1 IC1F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2445	* CCMR1 IC2F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2446	* CCMR2 IC3F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2447	* CCMR2 IC4F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2448	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2449	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2450	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2451	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2452	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2453	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2454	* @param ICFilter This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2455	* @arg @ref LL_TIM_IC_FILTER_FDIV1
EricLew	0:80ee8f3b695e	2456	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
EricLew	0:80ee8f3b695e	2457	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
EricLew	0:80ee8f3b695e	2458	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
EricLew	0:80ee8f3b695e	2459	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
EricLew	0:80ee8f3b695e	2460	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
EricLew	0:80ee8f3b695e	2461	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
EricLew	0:80ee8f3b695e	2462	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
EricLew	0:80ee8f3b695e	2463	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
EricLew	0:80ee8f3b695e	2464	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
EricLew	0:80ee8f3b695e	2465	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
EricLew	0:80ee8f3b695e	2466	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
EricLew	0:80ee8f3b695e	2467	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
EricLew	0:80ee8f3b695e	2468	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
EricLew	0:80ee8f3b695e	2469	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
EricLew	0:80ee8f3b695e	2470	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	2471	* @retval None
EricLew	0:80ee8f3b695e	2472	*/
EricLew	0:80ee8f3b695e	2473	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICFilter)
EricLew	0:80ee8f3b695e	2474	{
EricLew	0:80ee8f3b695e	2475	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2476	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2477	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16) << SHIFT_TAB_ICxx[iChannel]);
EricLew	0:80ee8f3b695e	2478	}
EricLew	0:80ee8f3b695e	2479
EricLew	0:80ee8f3b695e	2480	/**
EricLew	0:80ee8f3b695e	2481	* @brief Get the input filter duration
EricLew	0:80ee8f3b695e	2482	* @rmtoll CCMR1 IC1F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2483	* CCMR1 IC2F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2484	* CCMR2 IC3F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2485	* CCMR2 IC4F LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2486	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2487	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2488	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2489	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2490	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2491	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2492	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2493	* @arg @ref LL_TIM_IC_FILTER_FDIV1
EricLew	0:80ee8f3b695e	2494	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
EricLew	0:80ee8f3b695e	2495	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
EricLew	0:80ee8f3b695e	2496	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
EricLew	0:80ee8f3b695e	2497	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
EricLew	0:80ee8f3b695e	2498	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
EricLew	0:80ee8f3b695e	2499	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
EricLew	0:80ee8f3b695e	2500	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
EricLew	0:80ee8f3b695e	2501	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
EricLew	0:80ee8f3b695e	2502	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
EricLew	0:80ee8f3b695e	2503	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
EricLew	0:80ee8f3b695e	2504	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
EricLew	0:80ee8f3b695e	2505	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
EricLew	0:80ee8f3b695e	2506	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
EricLew	0:80ee8f3b695e	2507	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
EricLew	0:80ee8f3b695e	2508	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	2509	*/
EricLew	0:80ee8f3b695e	2510	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2511	{
EricLew	0:80ee8f3b695e	2512	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2513	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1)+ OFFSET_TAB_CCMRx[iChannel]));
EricLew	0:80ee8f3b695e	2514	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16 );
EricLew	0:80ee8f3b695e	2515	}
EricLew	0:80ee8f3b695e	2516
EricLew	0:80ee8f3b695e	2517	/**
EricLew	0:80ee8f3b695e	2518	* @brief Set the input channel polarity
EricLew	0:80ee8f3b695e	2519	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2520	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2521	* @rmtoll CCER CC1P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2522	* CCER CC1NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2523	* CCER CC2P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2524	* CCER CC2NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2525	* CCER CC3P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2526	* CCER CC3NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2527	* CCER CC4P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2528	* CCER CC4NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2529	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2530	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2531	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2532	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2533	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2534	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2535	* @param ICPolarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2536	* @arg @ref LL_TIM_IC_POLARITY_RISING
EricLew	0:80ee8f3b695e	2537	* @arg @ref LL_TIM_IC_POLARITY_FALLING
EricLew	0:80ee8f3b695e	2538	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
EricLew	0:80ee8f3b695e	2539	* @retval None
EricLew	0:80ee8f3b695e	2540	*/
EricLew	0:80ee8f3b695e	2541	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx, uint32_t Channel, uint32_t ICPolarity)
EricLew	0:80ee8f3b695e	2542	{
EricLew	0:80ee8f3b695e	2543	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2544	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	2545	}
EricLew	0:80ee8f3b695e	2546
EricLew	0:80ee8f3b695e	2547	/**
EricLew	0:80ee8f3b695e	2548	* @brief Get the current input channel polarity
EricLew	0:80ee8f3b695e	2549	* @note Macro IS_TIM_CCX_INSTANCE(TIMx, Channel) can be used to check whether
EricLew	0:80ee8f3b695e	2550	* or not a channel is supported by the a timer instance.
EricLew	0:80ee8f3b695e	2551	* @rmtoll CCER CC1P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2552	* CCER CC1NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2553	* CCER CC2P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2554	* CCER CC2NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2555	* CCER CC3P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2556	* CCER CC3NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2557	* CCER CC4P LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2558	* CCER CC4NP LL_TIM_IC_Config\n
EricLew	0:80ee8f3b695e	2559	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2560	* @param Channel This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2561	* @arg @ref LL_TIM_CHANNEL_CH1
EricLew	0:80ee8f3b695e	2562	* @arg @ref LL_TIM_CHANNEL_CH2
EricLew	0:80ee8f3b695e	2563	* @arg @ref LL_TIM_CHANNEL_CH3
EricLew	0:80ee8f3b695e	2564	* @arg @ref LL_TIM_CHANNEL_CH4
EricLew	0:80ee8f3b695e	2565	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	2566	* @arg @ref LL_TIM_IC_POLARITY_RISING
EricLew	0:80ee8f3b695e	2567	* @arg @ref LL_TIM_IC_POLARITY_FALLING
EricLew	0:80ee8f3b695e	2568	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
EricLew	0:80ee8f3b695e	2569	*/
EricLew	0:80ee8f3b695e	2570	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx, uint32_t Channel)
EricLew	0:80ee8f3b695e	2571	{
EricLew	0:80ee8f3b695e	2572	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
EricLew	0:80ee8f3b695e	2573	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
EricLew	0:80ee8f3b695e	2574	}
EricLew	0:80ee8f3b695e	2575
EricLew	0:80ee8f3b695e	2576	/**
EricLew	0:80ee8f3b695e	2577	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
EricLew	0:80ee8f3b695e	2578	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2579	* a timer instance provides an XOR input.
EricLew	0:80ee8f3b695e	2580	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
EricLew	0:80ee8f3b695e	2581	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2582	* @retval None
EricLew	0:80ee8f3b695e	2583	*/
EricLew	0:80ee8f3b695e	2584	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2585	{
EricLew	0:80ee8f3b695e	2586	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
EricLew	0:80ee8f3b695e	2587	}
EricLew	0:80ee8f3b695e	2588
EricLew	0:80ee8f3b695e	2589	/**
EricLew	0:80ee8f3b695e	2590	* @brief Connect the TIMx_CH1 pin to TI1 input.
EricLew	0:80ee8f3b695e	2591	* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2592	* a timer instance provides an XOR input.
EricLew	0:80ee8f3b695e	2593	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
EricLew	0:80ee8f3b695e	2594	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2595	* @retval None
EricLew	0:80ee8f3b695e	2596	*/
EricLew	0:80ee8f3b695e	2597	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2598	{
EricLew	0:80ee8f3b695e	2599	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
EricLew	0:80ee8f3b695e	2600	}
EricLew	0:80ee8f3b695e	2601
EricLew	0:80ee8f3b695e	2602	/**
EricLew	0:80ee8f3b695e	2603	* @brief Get captured value for input channel 1.
EricLew	0:80ee8f3b695e	2604	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2605	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2606	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2607	* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2608	* input channel 1 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2609	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
EricLew	0:80ee8f3b695e	2610	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2611	* @retval CapturedValue
EricLew	0:80ee8f3b695e	2612	*/
EricLew	0:80ee8f3b695e	2613	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2614	{
EricLew	0:80ee8f3b695e	2615	return (uint32_t)(READ_REG(TIMx->CCR1));
EricLew	0:80ee8f3b695e	2616	}
EricLew	0:80ee8f3b695e	2617
EricLew	0:80ee8f3b695e	2618	/**
EricLew	0:80ee8f3b695e	2619	* @brief Get captured value for input channel 2.
EricLew	0:80ee8f3b695e	2620	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2621	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2622	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2623	* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2624	* input channel 2 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2625	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
EricLew	0:80ee8f3b695e	2626	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2627	* @retval CapturedValue
EricLew	0:80ee8f3b695e	2628	*/
EricLew	0:80ee8f3b695e	2629	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2630	{
EricLew	0:80ee8f3b695e	2631	return (uint32_t)(READ_REG(TIMx->CCR2));
EricLew	0:80ee8f3b695e	2632	}
EricLew	0:80ee8f3b695e	2633
EricLew	0:80ee8f3b695e	2634	/**
EricLew	0:80ee8f3b695e	2635	* @brief Get captured value for input channel 3.
EricLew	0:80ee8f3b695e	2636	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2637	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2638	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2639	* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2640	* input channel 3 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2641	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
EricLew	0:80ee8f3b695e	2642	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2643	* @retval CapturedValue
EricLew	0:80ee8f3b695e	2644	*/
EricLew	0:80ee8f3b695e	2645	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2646	{
EricLew	0:80ee8f3b695e	2647	return (uint32_t)(READ_REG(TIMx->CCR3));
EricLew	0:80ee8f3b695e	2648	}
EricLew	0:80ee8f3b695e	2649
EricLew	0:80ee8f3b695e	2650	/**
EricLew	0:80ee8f3b695e	2651	* @brief Get captured value for input channel 4.
EricLew	0:80ee8f3b695e	2652	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	2653	* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2654	* whether or not a timer instance supports a 32 bits counter.
EricLew	0:80ee8f3b695e	2655	* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2656	* input channel 4 is supported by a timer instance.
EricLew	0:80ee8f3b695e	2657	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
EricLew	0:80ee8f3b695e	2658	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2659	* @retval CapturedValue
EricLew	0:80ee8f3b695e	2660	*/
EricLew	0:80ee8f3b695e	2661	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2662	{
EricLew	0:80ee8f3b695e	2663	return (uint32_t)(READ_REG(TIMx->CCR4));
EricLew	0:80ee8f3b695e	2664	}
EricLew	0:80ee8f3b695e	2665
EricLew	0:80ee8f3b695e	2666	/**
EricLew	0:80ee8f3b695e	2667	* @}
EricLew	0:80ee8f3b695e	2668	*/
EricLew	0:80ee8f3b695e	2669
EricLew	0:80ee8f3b695e	2670	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
EricLew	0:80ee8f3b695e	2671	* @{
EricLew	0:80ee8f3b695e	2672	*/
EricLew	0:80ee8f3b695e	2673	/**
EricLew	0:80ee8f3b695e	2674	* @brief Set the clock source of the counter clock.
EricLew	0:80ee8f3b695e	2675	* @ when selected clock source is external clock mode 1, the timer input the external clock is applied is selected by calling the LL_TIM_SetTriggerInput() function. This timer input must be configured by calling the LL_TIM_IC_Config() function.
EricLew	0:80ee8f3b695e	2676	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2677	* whether or not a timer instance supports external clock mode1.
EricLew	0:80ee8f3b695e	2678	* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2679	* whether or not a timer instance supports external clock mode2.
EricLew	0:80ee8f3b695e	2680	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
EricLew	0:80ee8f3b695e	2681	* SMCR ECE LL_TIM_SetClockSource\n
EricLew	0:80ee8f3b695e	2682	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2683	* @param ClockSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2684	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
EricLew	0:80ee8f3b695e	2685	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
EricLew	0:80ee8f3b695e	2686	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
EricLew	0:80ee8f3b695e	2687	* @retval None
EricLew	0:80ee8f3b695e	2688	*/
EricLew	0:80ee8f3b695e	2689	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef * TIMx, uint32_t ClockSource)
EricLew	0:80ee8f3b695e	2690	{
EricLew	0:80ee8f3b695e	2691	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
EricLew	0:80ee8f3b695e	2692	}
EricLew	0:80ee8f3b695e	2693
EricLew	0:80ee8f3b695e	2694	/**
EricLew	0:80ee8f3b695e	2695	* @brief Set the encoder interface mode.
EricLew	0:80ee8f3b695e	2696	* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2697	* whether or not a timer instance supports the encoder mode.
EricLew	0:80ee8f3b695e	2698	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
EricLew	0:80ee8f3b695e	2699	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2700	* @param EncoderMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2701	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
EricLew	0:80ee8f3b695e	2702	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
EricLew	0:80ee8f3b695e	2703	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
EricLew	0:80ee8f3b695e	2704	* @retval None
EricLew	0:80ee8f3b695e	2705	*/
EricLew	0:80ee8f3b695e	2706	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx, uint32_t EncoderMode)
EricLew	0:80ee8f3b695e	2707	{
EricLew	0:80ee8f3b695e	2708	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
EricLew	0:80ee8f3b695e	2709	}
EricLew	0:80ee8f3b695e	2710
EricLew	0:80ee8f3b695e	2711	/**
EricLew	0:80ee8f3b695e	2712	* @}
EricLew	0:80ee8f3b695e	2713	*/
EricLew	0:80ee8f3b695e	2714
EricLew	0:80ee8f3b695e	2715	/** @defgroup TIM_LL_EF_Timer_Synchronization timer synchronisation configuration
EricLew	0:80ee8f3b695e	2716	* @{
EricLew	0:80ee8f3b695e	2717	*/
EricLew	0:80ee8f3b695e	2718	/**
EricLew	0:80ee8f3b695e	2719	* @brief Set the trigger output (TRGO) used for timer synchronization .
EricLew	0:80ee8f3b695e	2720	* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2721	* whether or not a timer instance can operate as a master timer.
EricLew	0:80ee8f3b695e	2722	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
EricLew	0:80ee8f3b695e	2723	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2724	* @param TimerSynchronization This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2725	* @arg @ref LL_TIM_TRGO_RESET
EricLew	0:80ee8f3b695e	2726	* @arg @ref LL_TIM_TRGO_ENABLE
EricLew	0:80ee8f3b695e	2727	* @arg @ref LL_TIM_TRGO_UPDATE
EricLew	0:80ee8f3b695e	2728	* @arg @ref LL_TIM_TRGO_CC1IF
EricLew	0:80ee8f3b695e	2729	* @arg @ref LL_TIM_TRGO_OC1REF
EricLew	0:80ee8f3b695e	2730	* @arg @ref LL_TIM_TRGO_OC2REF
EricLew	0:80ee8f3b695e	2731	* @arg @ref LL_TIM_TRGO_OC3REF
EricLew	0:80ee8f3b695e	2732	* @arg @ref LL_TIM_TRGO_OC4REF
EricLew	0:80ee8f3b695e	2733	* @retval None
EricLew	0:80ee8f3b695e	2734	*/
EricLew	0:80ee8f3b695e	2735	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx, uint32_t TimerSynchronization)
EricLew	0:80ee8f3b695e	2736	{
EricLew	0:80ee8f3b695e	2737	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
EricLew	0:80ee8f3b695e	2738	}
EricLew	0:80ee8f3b695e	2739
EricLew	0:80ee8f3b695e	2740	/**
EricLew	0:80ee8f3b695e	2741	* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
EricLew	0:80ee8f3b695e	2742	* @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
EricLew	0:80ee8f3b695e	2743	* whether or not a timer instance can be used for ADC synchronization.
EricLew	0:80ee8f3b695e	2744	* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
EricLew	0:80ee8f3b695e	2745	* @param TIMx Timer Instance
EricLew	0:80ee8f3b695e	2746	* @param ADCSynchronization This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2747	* @arg @ref LL_TIM_TRGO2_RESET
EricLew	0:80ee8f3b695e	2748	* @arg @ref LL_TIM_TRGO2_ENABLE
EricLew	0:80ee8f3b695e	2749	* @arg @ref LL_TIM_TRGO2_UPDATE
EricLew	0:80ee8f3b695e	2750	* @arg @ref LL_TIM_TRGO2_CC1F
EricLew	0:80ee8f3b695e	2751	* @arg @ref LL_TIM_TRGO2_OC1
EricLew	0:80ee8f3b695e	2752	* @arg @ref LL_TIM_TRGO2_OC2
EricLew	0:80ee8f3b695e	2753	* @arg @ref LL_TIM_TRGO2_OC3
EricLew	0:80ee8f3b695e	2754	* @arg @ref LL_TIM_TRGO2_OC4
EricLew	0:80ee8f3b695e	2755	* @arg @ref LL_TIM_TRGO2_OC5
EricLew	0:80ee8f3b695e	2756	* @arg @ref LL_TIM_TRGO2_OC6
EricLew	0:80ee8f3b695e	2757	* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
EricLew	0:80ee8f3b695e	2758	* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
EricLew	0:80ee8f3b695e	2759	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
EricLew	0:80ee8f3b695e	2760	* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
EricLew	0:80ee8f3b695e	2761	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
EricLew	0:80ee8f3b695e	2762	* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
EricLew	0:80ee8f3b695e	2763	* @retval None
EricLew	0:80ee8f3b695e	2764	*/
EricLew	0:80ee8f3b695e	2765	__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef * TIMx, uint32_t ADCSynchronization)
EricLew	0:80ee8f3b695e	2766	{
EricLew	0:80ee8f3b695e	2767	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
EricLew	0:80ee8f3b695e	2768	}
EricLew	0:80ee8f3b695e	2769
EricLew	0:80ee8f3b695e	2770	/**
EricLew	0:80ee8f3b695e	2771	* @brief Set the synchronization mode of a slave timer.
EricLew	0:80ee8f3b695e	2772	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2773	* a timer instance can operate as a slave timer.
EricLew	0:80ee8f3b695e	2774	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
EricLew	0:80ee8f3b695e	2775	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2776	* @param SlaveMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2777	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
EricLew	0:80ee8f3b695e	2778	* @arg @ref LL_TIM_SLAVEMODE_RESET
EricLew	0:80ee8f3b695e	2779	* @arg @ref LL_TIM_SLAVEMODE_GATED
EricLew	0:80ee8f3b695e	2780	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
EricLew	0:80ee8f3b695e	2781	* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER (not supported by STM32F373xC and STM32F378xx devices)
EricLew	0:80ee8f3b695e	2782	* @retval None
EricLew	0:80ee8f3b695e	2783	*/
EricLew	0:80ee8f3b695e	2784	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx, uint32_t SlaveMode)
EricLew	0:80ee8f3b695e	2785	{
EricLew	0:80ee8f3b695e	2786	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
EricLew	0:80ee8f3b695e	2787	}
EricLew	0:80ee8f3b695e	2788
EricLew	0:80ee8f3b695e	2789	/**
EricLew	0:80ee8f3b695e	2790	* @brief Set the selects the trigger input to be used to synchronize the counter.
EricLew	0:80ee8f3b695e	2791	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2792	* a timer instance can operate as a slave timer.
EricLew	0:80ee8f3b695e	2793	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
EricLew	0:80ee8f3b695e	2794	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2795	* @param TriggerInput This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2796	* @arg @ref LL_TIM_TS_ITR0
EricLew	0:80ee8f3b695e	2797	* @arg @ref LL_TIM_TS_ITR1
EricLew	0:80ee8f3b695e	2798	* @arg @ref LL_TIM_TS_ITR2
EricLew	0:80ee8f3b695e	2799	* @arg @ref LL_TIM_TS_ITR3
EricLew	0:80ee8f3b695e	2800	* @arg @ref LL_TIM_TS_TI1F_ED
EricLew	0:80ee8f3b695e	2801	* @arg @ref LL_TIM_TS_TI1FP1
EricLew	0:80ee8f3b695e	2802	* @arg @ref LL_TIM_TS_TI2FP2
EricLew	0:80ee8f3b695e	2803	* @arg @ref LL_TIM_TS_ETRF
EricLew	0:80ee8f3b695e	2804	* @retval None
EricLew	0:80ee8f3b695e	2805	*/
EricLew	0:80ee8f3b695e	2806	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx, uint32_t TriggerInput)
EricLew	0:80ee8f3b695e	2807	{
EricLew	0:80ee8f3b695e	2808	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
EricLew	0:80ee8f3b695e	2809	}
EricLew	0:80ee8f3b695e	2810
EricLew	0:80ee8f3b695e	2811	/**
EricLew	0:80ee8f3b695e	2812	* @brief Enable the Master/Slave mode.
EricLew	0:80ee8f3b695e	2813	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2814	* a timer instance can operate as a slave timer.
EricLew	0:80ee8f3b695e	2815	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
EricLew	0:80ee8f3b695e	2816	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2817	* @retval None
EricLew	0:80ee8f3b695e	2818	*/
EricLew	0:80ee8f3b695e	2819	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2820	{
EricLew	0:80ee8f3b695e	2821	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
EricLew	0:80ee8f3b695e	2822	}
EricLew	0:80ee8f3b695e	2823
EricLew	0:80ee8f3b695e	2824	/**
EricLew	0:80ee8f3b695e	2825	* @brief Disable the Master/Slave mode.
EricLew	0:80ee8f3b695e	2826	* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2827	* a timer instance can operate as a slave timer.
EricLew	0:80ee8f3b695e	2828	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
EricLew	0:80ee8f3b695e	2829	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2830	* @retval None
EricLew	0:80ee8f3b695e	2831	*/
EricLew	0:80ee8f3b695e	2832	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2833	{
EricLew	0:80ee8f3b695e	2834	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
EricLew	0:80ee8f3b695e	2835	}
EricLew	0:80ee8f3b695e	2836
EricLew	0:80ee8f3b695e	2837	/**
EricLew	0:80ee8f3b695e	2838	* @brief Configure the external trigger (ETR) input.
EricLew	0:80ee8f3b695e	2839	* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2840	* a timer instance provides an external trigger input.
EricLew	0:80ee8f3b695e	2841	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
EricLew	0:80ee8f3b695e	2842	* SMCR ETPS LL_TIM_ConfigETR\n
EricLew	0:80ee8f3b695e	2843	* SMCR ETF LL_TIM_ConfigETR
EricLew	0:80ee8f3b695e	2844	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2845	* @param ETRPolarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2846	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
EricLew	0:80ee8f3b695e	2847	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
EricLew	0:80ee8f3b695e	2848	* @param ETRPrescaler This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2849	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
EricLew	0:80ee8f3b695e	2850	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
EricLew	0:80ee8f3b695e	2851	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
EricLew	0:80ee8f3b695e	2852	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
EricLew	0:80ee8f3b695e	2853	* @param ETRFilter This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2854	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
EricLew	0:80ee8f3b695e	2855	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
EricLew	0:80ee8f3b695e	2856	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
EricLew	0:80ee8f3b695e	2857	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
EricLew	0:80ee8f3b695e	2858	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
EricLew	0:80ee8f3b695e	2859	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
EricLew	0:80ee8f3b695e	2860	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
EricLew	0:80ee8f3b695e	2861	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
EricLew	0:80ee8f3b695e	2862	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
EricLew	0:80ee8f3b695e	2863	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
EricLew	0:80ee8f3b695e	2864	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
EricLew	0:80ee8f3b695e	2865	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
EricLew	0:80ee8f3b695e	2866	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
EricLew	0:80ee8f3b695e	2867	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
EricLew	0:80ee8f3b695e	2868	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
EricLew	0:80ee8f3b695e	2869	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	2870	* @retval None
EricLew	0:80ee8f3b695e	2871	*/
EricLew	0:80ee8f3b695e	2872	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef * TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter)
EricLew	0:80ee8f3b695e	2873	{
EricLew	0:80ee8f3b695e	2874	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
EricLew	0:80ee8f3b695e	2875	}
EricLew	0:80ee8f3b695e	2876
EricLew	0:80ee8f3b695e	2877	/**
EricLew	0:80ee8f3b695e	2878	* @brief Select the external trigger (ETR) input source.
EricLew	0:80ee8f3b695e	2879	* @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
EricLew	0:80ee8f3b695e	2880	* not a timer instance supports ETR source selection.
EricLew	0:80ee8f3b695e	2881	* @rmtoll OR2 ETRSEL LL_TIM_SetETRSource
EricLew	0:80ee8f3b695e	2882	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2883	* @param ETRSource This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2884	* @arg @ref LL_TIM_ETRSOURCE_LEGACY
EricLew	0:80ee8f3b695e	2885	* @arg @ref LL_TIM_ETRSOURCE_COMP1
EricLew	0:80ee8f3b695e	2886	* @arg @ref LL_TIM_ETRSOURCE_COMP2
EricLew	0:80ee8f3b695e	2887	* @retval None
EricLew	0:80ee8f3b695e	2888	*/
EricLew	0:80ee8f3b695e	2889	__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef * TIMx, uint32_t ETRSource)
EricLew	0:80ee8f3b695e	2890	{
EricLew	0:80ee8f3b695e	2891
EricLew	0:80ee8f3b695e	2892	MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource);
EricLew	0:80ee8f3b695e	2893	}
EricLew	0:80ee8f3b695e	2894
EricLew	0:80ee8f3b695e	2895	/**
EricLew	0:80ee8f3b695e	2896	* @}
EricLew	0:80ee8f3b695e	2897	*/
EricLew	0:80ee8f3b695e	2898
EricLew	0:80ee8f3b695e	2899	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
EricLew	0:80ee8f3b695e	2900	* @{
EricLew	0:80ee8f3b695e	2901	*/
EricLew	0:80ee8f3b695e	2902	/**
EricLew	0:80ee8f3b695e	2903	* @brief Enable the break function.
EricLew	0:80ee8f3b695e	2904	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2905	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	2906	* @rmtoll BDTR BKE LL_TIM_EnableBRK
EricLew	0:80ee8f3b695e	2907	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2908	* @retval None
EricLew	0:80ee8f3b695e	2909	*/
EricLew	0:80ee8f3b695e	2910	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2911	{
EricLew	0:80ee8f3b695e	2912	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
EricLew	0:80ee8f3b695e	2913	}
EricLew	0:80ee8f3b695e	2914
EricLew	0:80ee8f3b695e	2915	/**
EricLew	0:80ee8f3b695e	2916	* @brief Disable the break function.
EricLew	0:80ee8f3b695e	2917	* @rmtoll BDTR BKE LL_TIM_DisableBRK
EricLew	0:80ee8f3b695e	2918	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2919	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2920	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	2921	* @retval None
EricLew	0:80ee8f3b695e	2922	*/
EricLew	0:80ee8f3b695e	2923	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2924	{
EricLew	0:80ee8f3b695e	2925	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
EricLew	0:80ee8f3b695e	2926	}
EricLew	0:80ee8f3b695e	2927
EricLew	0:80ee8f3b695e	2928	/**
EricLew	0:80ee8f3b695e	2929	* @brief Configure the break input.
EricLew	0:80ee8f3b695e	2930	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2931	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	2932	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2933	* @param BreakPolarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2934	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
EricLew	0:80ee8f3b695e	2935	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
EricLew	0:80ee8f3b695e	2936	* @param BreakFilter This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2937	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
EricLew	0:80ee8f3b695e	2938	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
EricLew	0:80ee8f3b695e	2939	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
EricLew	0:80ee8f3b695e	2940	* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
EricLew	0:80ee8f3b695e	2941	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
EricLew	0:80ee8f3b695e	2942	* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
EricLew	0:80ee8f3b695e	2943	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
EricLew	0:80ee8f3b695e	2944	* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
EricLew	0:80ee8f3b695e	2945	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
EricLew	0:80ee8f3b695e	2946	* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
EricLew	0:80ee8f3b695e	2947	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
EricLew	0:80ee8f3b695e	2948	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
EricLew	0:80ee8f3b695e	2949	* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
EricLew	0:80ee8f3b695e	2950	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
EricLew	0:80ee8f3b695e	2951	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
EricLew	0:80ee8f3b695e	2952	* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	2953	* @retval None
EricLew	0:80ee8f3b695e	2954	*/
EricLew	0:80ee8f3b695e	2955	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef * TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
EricLew	0:80ee8f3b695e	2956	{
EricLew	0:80ee8f3b695e	2957	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP \| TIM_BDTR_BKF, BreakPolarity \| BreakFilter);
EricLew	0:80ee8f3b695e	2958	}
EricLew	0:80ee8f3b695e	2959
EricLew	0:80ee8f3b695e	2960	/**
EricLew	0:80ee8f3b695e	2961	* @brief Enable the break 2 function.
EricLew	0:80ee8f3b695e	2962	* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2963	* a timer instance provides a second break input.
EricLew	0:80ee8f3b695e	2964	* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
EricLew	0:80ee8f3b695e	2965	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2966	* @retval None
EricLew	0:80ee8f3b695e	2967	*/
EricLew	0:80ee8f3b695e	2968	__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2969	{
EricLew	0:80ee8f3b695e	2970	SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
EricLew	0:80ee8f3b695e	2971	}
EricLew	0:80ee8f3b695e	2972
EricLew	0:80ee8f3b695e	2973	/**
EricLew	0:80ee8f3b695e	2974	* @brief Disable the break 2 function.
EricLew	0:80ee8f3b695e	2975	* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2976	* a timer instance provides a second break input.
EricLew	0:80ee8f3b695e	2977	* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
EricLew	0:80ee8f3b695e	2978	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2979	* @retval None
EricLew	0:80ee8f3b695e	2980	*/
EricLew	0:80ee8f3b695e	2981	__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	2982	{
EricLew	0:80ee8f3b695e	2983	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
EricLew	0:80ee8f3b695e	2984	}
EricLew	0:80ee8f3b695e	2985
EricLew	0:80ee8f3b695e	2986	/**
EricLew	0:80ee8f3b695e	2987	* @brief Configure the break 2 input.
EricLew	0:80ee8f3b695e	2988	* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	2989	* a timer instance provides a second break input.
EricLew	0:80ee8f3b695e	2990	* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
EricLew	0:80ee8f3b695e	2991	* BDTR BK2F LL_TIM_ConfigBRK2
EricLew	0:80ee8f3b695e	2992	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	2993	* @param Break2Polarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2994	* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
EricLew	0:80ee8f3b695e	2995	* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
EricLew	0:80ee8f3b695e	2996	* @param Break2Filter This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	2997	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
EricLew	0:80ee8f3b695e	2998	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
EricLew	0:80ee8f3b695e	2999	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
EricLew	0:80ee8f3b695e	3000	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
EricLew	0:80ee8f3b695e	3001	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
EricLew	0:80ee8f3b695e	3002	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
EricLew	0:80ee8f3b695e	3003	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
EricLew	0:80ee8f3b695e	3004	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
EricLew	0:80ee8f3b695e	3005	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
EricLew	0:80ee8f3b695e	3006	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
EricLew	0:80ee8f3b695e	3007	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
EricLew	0:80ee8f3b695e	3008	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
EricLew	0:80ee8f3b695e	3009	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
EricLew	0:80ee8f3b695e	3010	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
EricLew	0:80ee8f3b695e	3011	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
EricLew	0:80ee8f3b695e	3012	* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
EricLew	0:80ee8f3b695e	3013	* @retval None
EricLew	0:80ee8f3b695e	3014	*/
EricLew	0:80ee8f3b695e	3015	__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef * TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
EricLew	0:80ee8f3b695e	3016	{
EricLew	0:80ee8f3b695e	3017	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P \| TIM_BDTR_BK2F, Break2Polarity \| Break2Filter);
EricLew	0:80ee8f3b695e	3018	}
EricLew	0:80ee8f3b695e	3019
EricLew	0:80ee8f3b695e	3020	/**
EricLew	0:80ee8f3b695e	3021	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
EricLew	0:80ee8f3b695e	3022	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3023	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3024	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
EricLew	0:80ee8f3b695e	3025	* BDTR OSSR LL_TIM_SetOffStates
EricLew	0:80ee8f3b695e	3026	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3027	* @param OffStateIdle This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3028	* @arg @ref LL_TIM_OSSI_DISABLE
EricLew	0:80ee8f3b695e	3029	* @arg @ref LL_TIM_OSSI_ENABLE
EricLew	0:80ee8f3b695e	3030	* @param OffStateRun This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3031	* @arg @ref LL_TIM_OSSR_DISABLE
EricLew	0:80ee8f3b695e	3032	* @arg @ref LL_TIM_OSSR_ENABLE
EricLew	0:80ee8f3b695e	3033	* @retval None
EricLew	0:80ee8f3b695e	3034	*/
EricLew	0:80ee8f3b695e	3035	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef * TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
EricLew	0:80ee8f3b695e	3036	{
EricLew	0:80ee8f3b695e	3037	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
EricLew	0:80ee8f3b695e	3038	}
EricLew	0:80ee8f3b695e	3039
EricLew	0:80ee8f3b695e	3040	/**
EricLew	0:80ee8f3b695e	3041	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
EricLew	0:80ee8f3b695e	3042	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3043	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3044	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
EricLew	0:80ee8f3b695e	3045	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3046	* @retval None
EricLew	0:80ee8f3b695e	3047	*/
EricLew	0:80ee8f3b695e	3048	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3049	{
EricLew	0:80ee8f3b695e	3050	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
EricLew	0:80ee8f3b695e	3051	}
EricLew	0:80ee8f3b695e	3052
EricLew	0:80ee8f3b695e	3053	/**
EricLew	0:80ee8f3b695e	3054	* @brief Disable automatic output (MOE can be set only by software).
EricLew	0:80ee8f3b695e	3055	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3056	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3057	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
EricLew	0:80ee8f3b695e	3058	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3059	* @retval None
EricLew	0:80ee8f3b695e	3060	*/
EricLew	0:80ee8f3b695e	3061	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3062	{
EricLew	0:80ee8f3b695e	3063	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
EricLew	0:80ee8f3b695e	3064	}
EricLew	0:80ee8f3b695e	3065
EricLew	0:80ee8f3b695e	3066	/**
EricLew	0:80ee8f3b695e	3067	* @brief Indicate whether automatic output is enabled.
EricLew	0:80ee8f3b695e	3068	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3069	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3070	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
EricLew	0:80ee8f3b695e	3071	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3072	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3073	*/
EricLew	0:80ee8f3b695e	3074	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3075	{
EricLew	0:80ee8f3b695e	3076	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
EricLew	0:80ee8f3b695e	3077	}
EricLew	0:80ee8f3b695e	3078
EricLew	0:80ee8f3b695e	3079	/**
EricLew	0:80ee8f3b695e	3080	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
EricLew	0:80ee8f3b695e	3081	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
EricLew	0:80ee8f3b695e	3082	* software and is reset in case of break or break2 event
EricLew	0:80ee8f3b695e	3083	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3084	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3085	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
EricLew	0:80ee8f3b695e	3086	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3087	* @retval None
EricLew	0:80ee8f3b695e	3088	*/
EricLew	0:80ee8f3b695e	3089	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3090	{
EricLew	0:80ee8f3b695e	3091	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
EricLew	0:80ee8f3b695e	3092	}
EricLew	0:80ee8f3b695e	3093
EricLew	0:80ee8f3b695e	3094	/**
EricLew	0:80ee8f3b695e	3095	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
EricLew	0:80ee8f3b695e	3096	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
EricLew	0:80ee8f3b695e	3097	* software and is reset in case of break or break2 event.
EricLew	0:80ee8f3b695e	3098	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3099	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3100	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
EricLew	0:80ee8f3b695e	3101	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3102	* @retval None
EricLew	0:80ee8f3b695e	3103	*/
EricLew	0:80ee8f3b695e	3104	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3105	{
EricLew	0:80ee8f3b695e	3106	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
EricLew	0:80ee8f3b695e	3107	}
EricLew	0:80ee8f3b695e	3108
EricLew	0:80ee8f3b695e	3109	/**
EricLew	0:80ee8f3b695e	3110	* @brief Indicates whether outputs are enabled.
EricLew	0:80ee8f3b695e	3111	* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3112	* a timer instance provides a break input.
EricLew	0:80ee8f3b695e	3113	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
EricLew	0:80ee8f3b695e	3114	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3115	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3116	*/
EricLew	0:80ee8f3b695e	3117	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3118	{
EricLew	0:80ee8f3b695e	3119	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
EricLew	0:80ee8f3b695e	3120	}
EricLew	0:80ee8f3b695e	3121
EricLew	0:80ee8f3b695e	3122	/**
EricLew	0:80ee8f3b695e	3123	* @brief Enable the signals connected to the designated timer break input.
EricLew	0:80ee8f3b695e	3124	* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
EricLew	0:80ee8f3b695e	3125	* or not a timer instance allows for break input selection.
EricLew	0:80ee8f3b695e	3126	* @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3127	* OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3128	* OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3129	* OR2 BKDFBK0E LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3130	* OR3 BKINE LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3131	* OR3 BKCMP1E LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3132	* OR3 BKCMP2E LL_TIM_EnableBreakInputSource\n
EricLew	0:80ee8f3b695e	3133	* OR3 BKDFBK0E LL_TIM_EnableBreakInputSource
EricLew	0:80ee8f3b695e	3134	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3135	* @param BreakInput This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3136	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
EricLew	0:80ee8f3b695e	3137	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
EricLew	0:80ee8f3b695e	3138	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3139	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
EricLew	0:80ee8f3b695e	3140	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
EricLew	0:80ee8f3b695e	3141	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
EricLew	0:80ee8f3b695e	3142	* @arg @ref LL_TIM_BKIN_SOURCE_DFBK
EricLew	0:80ee8f3b695e	3143	* @retval None
EricLew	0:80ee8f3b695e	3144	*/
EricLew	0:80ee8f3b695e	3145	__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
EricLew	0:80ee8f3b695e	3146	{
EricLew	0:80ee8f3b695e	3147	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
EricLew	0:80ee8f3b695e	3148	SET_BIT(*pReg , Source);
EricLew	0:80ee8f3b695e	3149	}
EricLew	0:80ee8f3b695e	3150
EricLew	0:80ee8f3b695e	3151	/**
EricLew	0:80ee8f3b695e	3152	* @brief Disable the signals connected to the designated timer break input.
EricLew	0:80ee8f3b695e	3153	* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
EricLew	0:80ee8f3b695e	3154	* or not a timer instance allows for break input selection.
EricLew	0:80ee8f3b695e	3155	* @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3156	* OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3157	* OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3158	* OR2 BKDFBK0E LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3159	* OR3 BKINE LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3160	* OR3 BKCMP1E LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3161	* OR3 BKCMP2E LL_TIM_DisableBreakInputSource\n
EricLew	0:80ee8f3b695e	3162	* OR3 BKDFBK0E LL_TIM_DisableBreakInputSource
EricLew	0:80ee8f3b695e	3163	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3164	* @param BreakInput This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3165	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
EricLew	0:80ee8f3b695e	3166	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
EricLew	0:80ee8f3b695e	3167	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3168	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
EricLew	0:80ee8f3b695e	3169	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
EricLew	0:80ee8f3b695e	3170	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
EricLew	0:80ee8f3b695e	3171	* @arg @ref LL_TIM_BKIN_SOURCE_DFBK
EricLew	0:80ee8f3b695e	3172	* @retval None
EricLew	0:80ee8f3b695e	3173	*/
EricLew	0:80ee8f3b695e	3174	__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source)
EricLew	0:80ee8f3b695e	3175	{
EricLew	0:80ee8f3b695e	3176	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
EricLew	0:80ee8f3b695e	3177	CLEAR_BIT(*pReg, Source);
EricLew	0:80ee8f3b695e	3178	}
EricLew	0:80ee8f3b695e	3179
EricLew	0:80ee8f3b695e	3180	/**
EricLew	0:80ee8f3b695e	3181	* @brief Set the polarity of the break signal for the timer break input.
EricLew	0:80ee8f3b695e	3182	* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
EricLew	0:80ee8f3b695e	3183	* or not a timer instance allows for break input selection.
EricLew	0:80ee8f3b695e	3184	* @rmtoll OR2 BKINE LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3185	* OR2 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3186	* OR2 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3187	* OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3188	* OR3 BKINE LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3189	* OR3 BKCMP1E LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3190	* OR3 BKCMP2E LL_TIM_SetBreakInputSourcePolarity\n
EricLew	0:80ee8f3b695e	3191	* OR3 BKINP LL_TIM_SetBreakInputSourcePolarity
EricLew	0:80ee8f3b695e	3192	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3193	* @param BreakInput This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3194	* @arg @ref LL_TIM_BREAK_INPUT_BKIN
EricLew	0:80ee8f3b695e	3195	* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
EricLew	0:80ee8f3b695e	3196	* @param Source This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3197	* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
EricLew	0:80ee8f3b695e	3198	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
EricLew	0:80ee8f3b695e	3199	* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
EricLew	0:80ee8f3b695e	3200	* @param Polarity This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3201	* @arg @ref LL_TIM_BKIN_POLARITY_LOW
EricLew	0:80ee8f3b695e	3202	* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
EricLew	0:80ee8f3b695e	3203	* @retval None
EricLew	0:80ee8f3b695e	3204	*/
EricLew	0:80ee8f3b695e	3205	__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef * TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity)
EricLew	0:80ee8f3b695e	3206	{
EricLew	0:80ee8f3b695e	3207	register uint32_t * pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2)+ BreakInput));
EricLew	0:80ee8f3b695e	3208	MODIFY_REG(*pReg, (TIMx_OR2_BKINP << (POSITION_VAL(Source))) , (Polarity << (POSITION_VAL(Source))));
EricLew	0:80ee8f3b695e	3209	}
EricLew	0:80ee8f3b695e	3210
EricLew	0:80ee8f3b695e	3211	/**
EricLew	0:80ee8f3b695e	3212	* @}
EricLew	0:80ee8f3b695e	3213	*/
EricLew	0:80ee8f3b695e	3214
EricLew	0:80ee8f3b695e	3215	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burs mode configuration
EricLew	0:80ee8f3b695e	3216	* @{
EricLew	0:80ee8f3b695e	3217	*/
EricLew	0:80ee8f3b695e	3218	/**
EricLew	0:80ee8f3b695e	3219	* @brief Configures the timer DMA burst feature.
EricLew	0:80ee8f3b695e	3220	* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
EricLew	0:80ee8f3b695e	3221	* not a timer instance supports the DMA burst mode.
EricLew	0:80ee8f3b695e	3222	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
EricLew	0:80ee8f3b695e	3223	* DCR DBA LL_TIM_ConfigDMABurst
EricLew	0:80ee8f3b695e	3224	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3225	* @param DMABurstBaseAddress This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3226	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
EricLew	0:80ee8f3b695e	3227	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
EricLew	0:80ee8f3b695e	3228	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
EricLew	0:80ee8f3b695e	3229	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
EricLew	0:80ee8f3b695e	3230	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
EricLew	0:80ee8f3b695e	3231	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
EricLew	0:80ee8f3b695e	3232	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
EricLew	0:80ee8f3b695e	3233	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
EricLew	0:80ee8f3b695e	3234	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
EricLew	0:80ee8f3b695e	3235	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
EricLew	0:80ee8f3b695e	3236	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
EricLew	0:80ee8f3b695e	3237	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
EricLew	0:80ee8f3b695e	3238	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
EricLew	0:80ee8f3b695e	3239	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
EricLew	0:80ee8f3b695e	3240	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
EricLew	0:80ee8f3b695e	3241	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
EricLew	0:80ee8f3b695e	3242	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
EricLew	0:80ee8f3b695e	3243	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
EricLew	0:80ee8f3b695e	3244	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
EricLew	0:80ee8f3b695e	3245	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
EricLew	0:80ee8f3b695e	3246	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
EricLew	0:80ee8f3b695e	3247	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
EricLew	0:80ee8f3b695e	3248	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR2
EricLew	0:80ee8f3b695e	3249	* @arg @ref LL_TIM_DMABURST_BASEADDR_OR3
EricLew	0:80ee8f3b695e	3250	* @param DMABurstLength This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3251	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
EricLew	0:80ee8f3b695e	3252	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
EricLew	0:80ee8f3b695e	3253	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
EricLew	0:80ee8f3b695e	3254	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
EricLew	0:80ee8f3b695e	3255	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
EricLew	0:80ee8f3b695e	3256	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
EricLew	0:80ee8f3b695e	3257	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
EricLew	0:80ee8f3b695e	3258	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
EricLew	0:80ee8f3b695e	3259	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
EricLew	0:80ee8f3b695e	3260	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
EricLew	0:80ee8f3b695e	3261	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
EricLew	0:80ee8f3b695e	3262	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
EricLew	0:80ee8f3b695e	3263	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
EricLew	0:80ee8f3b695e	3264	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
EricLew	0:80ee8f3b695e	3265	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
EricLew	0:80ee8f3b695e	3266	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
EricLew	0:80ee8f3b695e	3267	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
EricLew	0:80ee8f3b695e	3268	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
EricLew	0:80ee8f3b695e	3269	* @retval None
EricLew	0:80ee8f3b695e	3270	*/
EricLew	0:80ee8f3b695e	3271	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
EricLew	0:80ee8f3b695e	3272	{
EricLew	0:80ee8f3b695e	3273	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
EricLew	0:80ee8f3b695e	3274	}
EricLew	0:80ee8f3b695e	3275
EricLew	0:80ee8f3b695e	3276	/**
EricLew	0:80ee8f3b695e	3277	* @}
EricLew	0:80ee8f3b695e	3278	*/
EricLew	0:80ee8f3b695e	3279
EricLew	0:80ee8f3b695e	3280	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
EricLew	0:80ee8f3b695e	3281	* @{
EricLew	0:80ee8f3b695e	3282	*/
EricLew	0:80ee8f3b695e	3283	/**
EricLew	0:80ee8f3b695e	3284	* @brief Remap TIM inputs (input channel, internal/external triggers).
EricLew	0:80ee8f3b695e	3285	* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
EricLew	0:80ee8f3b695e	3286	* a some timer inputs can be remapped.
EricLew	0:80ee8f3b695e	3287	* @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3288	* @rmtoll TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3289	* @rmtoll TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3290	* @rmtoll TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3291	* @rmtoll TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3292	* @rmtoll TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3293	* @rmtoll TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3294	* @rmtoll TIM2_OR1 ETR1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3295	* @rmtoll TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3296	* @rmtoll TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3297	* @rmtoll TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3298	* @rmtoll TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3299	* @rmtoll TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n
EricLew	0:80ee8f3b695e	3300	* @rmtoll TIM17_OR1 TI1_RMP LL_TIM_SetRemap
EricLew	0:80ee8f3b695e	3301	* @param TIMx: Timer instance
EricLew	0:80ee8f3b695e	3302	* @param Remap: This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	3303	*
EricLew	0:80ee8f3b695e	3304	* TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
EricLew	0:80ee8f3b695e	3305	* ADC1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3306	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC
EricLew	0:80ee8f3b695e	3307	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1
EricLew	0:80ee8f3b695e	3308	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2
EricLew	0:80ee8f3b695e	3309	* @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3
EricLew	0:80ee8f3b695e	3310	* ADC3_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3311	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC
EricLew	0:80ee8f3b695e	3312	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1
EricLew	0:80ee8f3b695e	3313	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2
EricLew	0:80ee8f3b695e	3314	* @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3
EricLew	0:80ee8f3b695e	3315	* TI1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3316	* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3317	* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
EricLew	0:80ee8f3b695e	3318	*
EricLew	0:80ee8f3b695e	3319	* TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where
EricLew	0:80ee8f3b695e	3320	* ITR1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3321	* @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
EricLew	0:80ee8f3b695e	3322	* @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
EricLew	0:80ee8f3b695e	3323	* ETR1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3324	* @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO
EricLew	0:80ee8f3b695e	3325	* @arg @ref LL_TIM_TIM2_ETR_RMP_LSE
EricLew	0:80ee8f3b695e	3326	* TI4_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3327	* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
EricLew	0:80ee8f3b695e	3328	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
EricLew	0:80ee8f3b695e	3329	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
EricLew	0:80ee8f3b695e	3330	* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2
EricLew	0:80ee8f3b695e	3331	*
EricLew	0:80ee8f3b695e	3332	* TIM3: one of the following values
EricLew	0:80ee8f3b695e	3333	* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3334	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
EricLew	0:80ee8f3b695e	3335	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
EricLew	0:80ee8f3b695e	3336	* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2
EricLew	0:80ee8f3b695e	3337	*
EricLew	0:80ee8f3b695e	3338	* TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where
EricLew	0:80ee8f3b695e	3339	* ADC1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3340	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC
EricLew	0:80ee8f3b695e	3341	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1
EricLew	0:80ee8f3b695e	3342	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2
EricLew	0:80ee8f3b695e	3343	* @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3
EricLew	0:80ee8f3b695e	3344	* ADC3_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3345	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC
EricLew	0:80ee8f3b695e	3346	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1
EricLew	0:80ee8f3b695e	3347	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2
EricLew	0:80ee8f3b695e	3348	* @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3
EricLew	0:80ee8f3b695e	3349	* TI1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3350	* @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3351	* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
EricLew	0:80ee8f3b695e	3352	*
EricLew	0:80ee8f3b695e	3353	* TIM15: any combination of TI1_RMP, ENCODER_MODE where
EricLew	0:80ee8f3b695e	3354	* TI1_RMP can be one of the following values
EricLew	0:80ee8f3b695e	3355	* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3356	* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
EricLew	0:80ee8f3b695e	3357	* ENCODER_MODE can be one of the following values
EricLew	0:80ee8f3b695e	3358	* @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION
EricLew	0:80ee8f3b695e	3359	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2
EricLew	0:80ee8f3b695e	3360	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3
EricLew	0:80ee8f3b695e	3361	* @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4
EricLew	0:80ee8f3b695e	3362	*
EricLew	0:80ee8f3b695e	3363	* TIM16: one of the following values
EricLew	0:80ee8f3b695e	3364	* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3365	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
EricLew	0:80ee8f3b695e	3366	* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
EricLew	0:80ee8f3b695e	3367	* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC
EricLew	0:80ee8f3b695e	3368	*
EricLew	0:80ee8f3b695e	3369	* TIM17: one of the following values
EricLew	0:80ee8f3b695e	3370	* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
EricLew	0:80ee8f3b695e	3371	* @arg @ref LL_TIM_TIM17_TI1_RMP_MSI
EricLew	0:80ee8f3b695e	3372	* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
EricLew	0:80ee8f3b695e	3373	* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
EricLew	0:80ee8f3b695e	3374	* @retval None
EricLew	0:80ee8f3b695e	3375	*/
EricLew	0:80ee8f3b695e	3376	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef * TIMx, uint32_t Remap)
EricLew	0:80ee8f3b695e	3377	{
EricLew	0:80ee8f3b695e	3378	MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK));
EricLew	0:80ee8f3b695e	3379	}
EricLew	0:80ee8f3b695e	3380
EricLew	0:80ee8f3b695e	3381	/**
EricLew	0:80ee8f3b695e	3382	* @}
EricLew	0:80ee8f3b695e	3383	*/
EricLew	0:80ee8f3b695e	3384
EricLew	0:80ee8f3b695e	3385	/** @defgroup TIM_LL_EF_FLAG_Management FLAG_Management
EricLew	0:80ee8f3b695e	3386	* @{
EricLew	0:80ee8f3b695e	3387	*/
EricLew	0:80ee8f3b695e	3388	/**
EricLew	0:80ee8f3b695e	3389	* @brief Clear the update interrupt flag (UIF).
EricLew	0:80ee8f3b695e	3390	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
EricLew	0:80ee8f3b695e	3391	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3392	* @retval None
EricLew	0:80ee8f3b695e	3393	*/
EricLew	0:80ee8f3b695e	3394	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3395	{
EricLew	0:80ee8f3b695e	3396	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
EricLew	0:80ee8f3b695e	3397	}
EricLew	0:80ee8f3b695e	3398
EricLew	0:80ee8f3b695e	3399	/**
EricLew	0:80ee8f3b695e	3400	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
EricLew	0:80ee8f3b695e	3401	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
EricLew	0:80ee8f3b695e	3402	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3403	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3404	*/
EricLew	0:80ee8f3b695e	3405	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3406	{
EricLew	0:80ee8f3b695e	3407	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
EricLew	0:80ee8f3b695e	3408	}
EricLew	0:80ee8f3b695e	3409
EricLew	0:80ee8f3b695e	3410	/**
EricLew	0:80ee8f3b695e	3411	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
EricLew	0:80ee8f3b695e	3412	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
EricLew	0:80ee8f3b695e	3413	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3414	* @retval None
EricLew	0:80ee8f3b695e	3415	*/
EricLew	0:80ee8f3b695e	3416	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3417	{
EricLew	0:80ee8f3b695e	3418	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
EricLew	0:80ee8f3b695e	3419	}
EricLew	0:80ee8f3b695e	3420
EricLew	0:80ee8f3b695e	3421	/**
EricLew	0:80ee8f3b695e	3422	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
EricLew	0:80ee8f3b695e	3423	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
EricLew	0:80ee8f3b695e	3424	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3425	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3426	*/
EricLew	0:80ee8f3b695e	3427	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3428	{
EricLew	0:80ee8f3b695e	3429	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
EricLew	0:80ee8f3b695e	3430	}
EricLew	0:80ee8f3b695e	3431
EricLew	0:80ee8f3b695e	3432	/**
EricLew	0:80ee8f3b695e	3433	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
EricLew	0:80ee8f3b695e	3434	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
EricLew	0:80ee8f3b695e	3435	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3436	* @retval None
EricLew	0:80ee8f3b695e	3437	*/
EricLew	0:80ee8f3b695e	3438	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3439	{
EricLew	0:80ee8f3b695e	3440	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
EricLew	0:80ee8f3b695e	3441	}
EricLew	0:80ee8f3b695e	3442
EricLew	0:80ee8f3b695e	3443	/**
EricLew	0:80ee8f3b695e	3444	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
EricLew	0:80ee8f3b695e	3445	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
EricLew	0:80ee8f3b695e	3446	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3447	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3448	*/
EricLew	0:80ee8f3b695e	3449	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3450	{
EricLew	0:80ee8f3b695e	3451	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
EricLew	0:80ee8f3b695e	3452	}
EricLew	0:80ee8f3b695e	3453
EricLew	0:80ee8f3b695e	3454	/**
EricLew	0:80ee8f3b695e	3455	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
EricLew	0:80ee8f3b695e	3456	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
EricLew	0:80ee8f3b695e	3457	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3458	* @retval None
EricLew	0:80ee8f3b695e	3459	*/
EricLew	0:80ee8f3b695e	3460	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3461	{
EricLew	0:80ee8f3b695e	3462	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
EricLew	0:80ee8f3b695e	3463	}
EricLew	0:80ee8f3b695e	3464
EricLew	0:80ee8f3b695e	3465	/**
EricLew	0:80ee8f3b695e	3466	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
EricLew	0:80ee8f3b695e	3467	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
EricLew	0:80ee8f3b695e	3468	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3469	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3470	*/
EricLew	0:80ee8f3b695e	3471	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3472	{
EricLew	0:80ee8f3b695e	3473	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
EricLew	0:80ee8f3b695e	3474	}
EricLew	0:80ee8f3b695e	3475
EricLew	0:80ee8f3b695e	3476	/**
EricLew	0:80ee8f3b695e	3477	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
EricLew	0:80ee8f3b695e	3478	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
EricLew	0:80ee8f3b695e	3479	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3480	* @retval None
EricLew	0:80ee8f3b695e	3481	*/
EricLew	0:80ee8f3b695e	3482	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3483	{
EricLew	0:80ee8f3b695e	3484	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
EricLew	0:80ee8f3b695e	3485	}
EricLew	0:80ee8f3b695e	3486
EricLew	0:80ee8f3b695e	3487	/**
EricLew	0:80ee8f3b695e	3488	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
EricLew	0:80ee8f3b695e	3489	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
EricLew	0:80ee8f3b695e	3490	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3491	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3492	*/
EricLew	0:80ee8f3b695e	3493	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3494	{
EricLew	0:80ee8f3b695e	3495	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
EricLew	0:80ee8f3b695e	3496	}
EricLew	0:80ee8f3b695e	3497
EricLew	0:80ee8f3b695e	3498	/**
EricLew	0:80ee8f3b695e	3499	* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
EricLew	0:80ee8f3b695e	3500	* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
EricLew	0:80ee8f3b695e	3501	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3502	* @retval None
EricLew	0:80ee8f3b695e	3503	*/
EricLew	0:80ee8f3b695e	3504	__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3505	{
EricLew	0:80ee8f3b695e	3506	WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
EricLew	0:80ee8f3b695e	3507	}
EricLew	0:80ee8f3b695e	3508
EricLew	0:80ee8f3b695e	3509	/**
EricLew	0:80ee8f3b695e	3510	* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
EricLew	0:80ee8f3b695e	3511	* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
EricLew	0:80ee8f3b695e	3512	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3513	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3514	*/
EricLew	0:80ee8f3b695e	3515	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3516	{
EricLew	0:80ee8f3b695e	3517	return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
EricLew	0:80ee8f3b695e	3518	}
EricLew	0:80ee8f3b695e	3519	/**
EricLew	0:80ee8f3b695e	3520	* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
EricLew	0:80ee8f3b695e	3521	* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
EricLew	0:80ee8f3b695e	3522	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3523	* @retval None
EricLew	0:80ee8f3b695e	3524	*/
EricLew	0:80ee8f3b695e	3525	__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3526	{
EricLew	0:80ee8f3b695e	3527	WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
EricLew	0:80ee8f3b695e	3528	}
EricLew	0:80ee8f3b695e	3529
EricLew	0:80ee8f3b695e	3530	/**
EricLew	0:80ee8f3b695e	3531	* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
EricLew	0:80ee8f3b695e	3532	* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
EricLew	0:80ee8f3b695e	3533	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3534	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3535	*/
EricLew	0:80ee8f3b695e	3536	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3537	{
EricLew	0:80ee8f3b695e	3538	return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
EricLew	0:80ee8f3b695e	3539	}
EricLew	0:80ee8f3b695e	3540
EricLew	0:80ee8f3b695e	3541	/**
EricLew	0:80ee8f3b695e	3542	* @brief Clear the commutation interrupt flag (COMIF).
EricLew	0:80ee8f3b695e	3543	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
EricLew	0:80ee8f3b695e	3544	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3545	* @retval None
EricLew	0:80ee8f3b695e	3546	*/
EricLew	0:80ee8f3b695e	3547	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3548	{
EricLew	0:80ee8f3b695e	3549	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
EricLew	0:80ee8f3b695e	3550	}
EricLew	0:80ee8f3b695e	3551
EricLew	0:80ee8f3b695e	3552	/**
EricLew	0:80ee8f3b695e	3553	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
EricLew	0:80ee8f3b695e	3554	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
EricLew	0:80ee8f3b695e	3555	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3556	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3557	*/
EricLew	0:80ee8f3b695e	3558	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3559	{
EricLew	0:80ee8f3b695e	3560	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
EricLew	0:80ee8f3b695e	3561	}
EricLew	0:80ee8f3b695e	3562
EricLew	0:80ee8f3b695e	3563	/**
EricLew	0:80ee8f3b695e	3564	* @brief Clear the trigger interrupt flag (TIF).
EricLew	0:80ee8f3b695e	3565	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
EricLew	0:80ee8f3b695e	3566	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3567	* @retval None
EricLew	0:80ee8f3b695e	3568	*/
EricLew	0:80ee8f3b695e	3569	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3570	{
EricLew	0:80ee8f3b695e	3571	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
EricLew	0:80ee8f3b695e	3572	}
EricLew	0:80ee8f3b695e	3573
EricLew	0:80ee8f3b695e	3574	/**
EricLew	0:80ee8f3b695e	3575	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
EricLew	0:80ee8f3b695e	3576	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
EricLew	0:80ee8f3b695e	3577	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3578	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3579	*/
EricLew	0:80ee8f3b695e	3580	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3581	{
EricLew	0:80ee8f3b695e	3582	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
EricLew	0:80ee8f3b695e	3583	}
EricLew	0:80ee8f3b695e	3584
EricLew	0:80ee8f3b695e	3585	/**
EricLew	0:80ee8f3b695e	3586	* @brief Clear the break interrupt flag (BIF).
EricLew	0:80ee8f3b695e	3587	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
EricLew	0:80ee8f3b695e	3588	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3589	* @retval None
EricLew	0:80ee8f3b695e	3590	*/
EricLew	0:80ee8f3b695e	3591	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3592	{
EricLew	0:80ee8f3b695e	3593	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
EricLew	0:80ee8f3b695e	3594	}
EricLew	0:80ee8f3b695e	3595
EricLew	0:80ee8f3b695e	3596	/**
EricLew	0:80ee8f3b695e	3597	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
EricLew	0:80ee8f3b695e	3598	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
EricLew	0:80ee8f3b695e	3599	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3600	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3601	*/
EricLew	0:80ee8f3b695e	3602	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3603	{
EricLew	0:80ee8f3b695e	3604	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
EricLew	0:80ee8f3b695e	3605	}
EricLew	0:80ee8f3b695e	3606
EricLew	0:80ee8f3b695e	3607	/**
EricLew	0:80ee8f3b695e	3608	* @brief Clear the break 2 interrupt flag (B2IF).
EricLew	0:80ee8f3b695e	3609	* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
EricLew	0:80ee8f3b695e	3610	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3611	* @retval None
EricLew	0:80ee8f3b695e	3612	*/
EricLew	0:80ee8f3b695e	3613	__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3614	{
EricLew	0:80ee8f3b695e	3615	WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
EricLew	0:80ee8f3b695e	3616	}
EricLew	0:80ee8f3b695e	3617
EricLew	0:80ee8f3b695e	3618	/**
EricLew	0:80ee8f3b695e	3619	* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
EricLew	0:80ee8f3b695e	3620	* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
EricLew	0:80ee8f3b695e	3621	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3622	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3623	*/
EricLew	0:80ee8f3b695e	3624	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3625	{
EricLew	0:80ee8f3b695e	3626	return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
EricLew	0:80ee8f3b695e	3627	}
EricLew	0:80ee8f3b695e	3628
EricLew	0:80ee8f3b695e	3629	/**
EricLew	0:80ee8f3b695e	3630	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
EricLew	0:80ee8f3b695e	3631	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
EricLew	0:80ee8f3b695e	3632	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3633	* @retval None
EricLew	0:80ee8f3b695e	3634	*/
EricLew	0:80ee8f3b695e	3635	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3636	{
EricLew	0:80ee8f3b695e	3637	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
EricLew	0:80ee8f3b695e	3638	}
EricLew	0:80ee8f3b695e	3639
EricLew	0:80ee8f3b695e	3640	/**
EricLew	0:80ee8f3b695e	3641	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
EricLew	0:80ee8f3b695e	3642	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
EricLew	0:80ee8f3b695e	3643	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3644	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3645	*/
EricLew	0:80ee8f3b695e	3646	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3647	{
EricLew	0:80ee8f3b695e	3648	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
EricLew	0:80ee8f3b695e	3649	}
EricLew	0:80ee8f3b695e	3650
EricLew	0:80ee8f3b695e	3651	/**
EricLew	0:80ee8f3b695e	3652	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
EricLew	0:80ee8f3b695e	3653	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
EricLew	0:80ee8f3b695e	3654	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3655	* @retval None
EricLew	0:80ee8f3b695e	3656	*/
EricLew	0:80ee8f3b695e	3657	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3658	{
EricLew	0:80ee8f3b695e	3659	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
EricLew	0:80ee8f3b695e	3660	}
EricLew	0:80ee8f3b695e	3661
EricLew	0:80ee8f3b695e	3662	/**
EricLew	0:80ee8f3b695e	3663	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
EricLew	0:80ee8f3b695e	3664	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
EricLew	0:80ee8f3b695e	3665	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3666	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3667	*/
EricLew	0:80ee8f3b695e	3668	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3669	{
EricLew	0:80ee8f3b695e	3670	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
EricLew	0:80ee8f3b695e	3671	}
EricLew	0:80ee8f3b695e	3672
EricLew	0:80ee8f3b695e	3673	/**
EricLew	0:80ee8f3b695e	3674	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
EricLew	0:80ee8f3b695e	3675	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
EricLew	0:80ee8f3b695e	3676	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3677	* @retval None
EricLew	0:80ee8f3b695e	3678	*/
EricLew	0:80ee8f3b695e	3679	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3680	{
EricLew	0:80ee8f3b695e	3681	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
EricLew	0:80ee8f3b695e	3682	}
EricLew	0:80ee8f3b695e	3683
EricLew	0:80ee8f3b695e	3684	/**
EricLew	0:80ee8f3b695e	3685	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
EricLew	0:80ee8f3b695e	3686	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
EricLew	0:80ee8f3b695e	3687	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3688	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3689	*/
EricLew	0:80ee8f3b695e	3690	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3691	{
EricLew	0:80ee8f3b695e	3692	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
EricLew	0:80ee8f3b695e	3693	}
EricLew	0:80ee8f3b695e	3694
EricLew	0:80ee8f3b695e	3695	/**
EricLew	0:80ee8f3b695e	3696	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
EricLew	0:80ee8f3b695e	3697	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
EricLew	0:80ee8f3b695e	3698	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3699	* @retval None
EricLew	0:80ee8f3b695e	3700	*/
EricLew	0:80ee8f3b695e	3701	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3702	{
EricLew	0:80ee8f3b695e	3703	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
EricLew	0:80ee8f3b695e	3704	}
EricLew	0:80ee8f3b695e	3705
EricLew	0:80ee8f3b695e	3706	/**
EricLew	0:80ee8f3b695e	3707	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
EricLew	0:80ee8f3b695e	3708	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
EricLew	0:80ee8f3b695e	3709	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3710	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3711	*/
EricLew	0:80ee8f3b695e	3712	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3713	{
EricLew	0:80ee8f3b695e	3714	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
EricLew	0:80ee8f3b695e	3715	}
EricLew	0:80ee8f3b695e	3716
EricLew	0:80ee8f3b695e	3717	/**
EricLew	0:80ee8f3b695e	3718	* @brief Clear the system break interrupt flag (SBIF).
EricLew	0:80ee8f3b695e	3719	* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
EricLew	0:80ee8f3b695e	3720	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3721	* @retval None
EricLew	0:80ee8f3b695e	3722	*/
EricLew	0:80ee8f3b695e	3723	__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3724	{
EricLew	0:80ee8f3b695e	3725	WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
EricLew	0:80ee8f3b695e	3726	}
EricLew	0:80ee8f3b695e	3727
EricLew	0:80ee8f3b695e	3728	/**
EricLew	0:80ee8f3b695e	3729	* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
EricLew	0:80ee8f3b695e	3730	* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
EricLew	0:80ee8f3b695e	3731	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3732	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3733	*/
EricLew	0:80ee8f3b695e	3734	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3735	{
EricLew	0:80ee8f3b695e	3736	return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
EricLew	0:80ee8f3b695e	3737	}
EricLew	0:80ee8f3b695e	3738
EricLew	0:80ee8f3b695e	3739	/**
EricLew	0:80ee8f3b695e	3740	* @}
EricLew	0:80ee8f3b695e	3741	*/
EricLew	0:80ee8f3b695e	3742
EricLew	0:80ee8f3b695e	3743	/** @defgroup TIM_LL_EF_IT_Management IT_Management
EricLew	0:80ee8f3b695e	3744	* @{
EricLew	0:80ee8f3b695e	3745	*/
EricLew	0:80ee8f3b695e	3746	/**
EricLew	0:80ee8f3b695e	3747	* @brief Enable update interrupt (UIE).
EricLew	0:80ee8f3b695e	3748	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
EricLew	0:80ee8f3b695e	3749	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3750	* @retval None
EricLew	0:80ee8f3b695e	3751	*/
EricLew	0:80ee8f3b695e	3752	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3753	{
EricLew	0:80ee8f3b695e	3754	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
EricLew	0:80ee8f3b695e	3755	}
EricLew	0:80ee8f3b695e	3756
EricLew	0:80ee8f3b695e	3757	/**
EricLew	0:80ee8f3b695e	3758	* @brief Disable update interrupt (UIE).
EricLew	0:80ee8f3b695e	3759	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
EricLew	0:80ee8f3b695e	3760	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3761	* @retval None
EricLew	0:80ee8f3b695e	3762	*/
EricLew	0:80ee8f3b695e	3763	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3764	{
EricLew	0:80ee8f3b695e	3765	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
EricLew	0:80ee8f3b695e	3766	}
EricLew	0:80ee8f3b695e	3767
EricLew	0:80ee8f3b695e	3768	/**
EricLew	0:80ee8f3b695e	3769	* @brief Indicates whether the update interrupt (UIE) is enabled.
EricLew	0:80ee8f3b695e	3770	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
EricLew	0:80ee8f3b695e	3771	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3772	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3773	*/
EricLew	0:80ee8f3b695e	3774	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3775	{
EricLew	0:80ee8f3b695e	3776	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
EricLew	0:80ee8f3b695e	3777	}
EricLew	0:80ee8f3b695e	3778
EricLew	0:80ee8f3b695e	3779	/**
EricLew	0:80ee8f3b695e	3780	* @brief Enable capture/compare 1 interrupt (CC1IE).
EricLew	0:80ee8f3b695e	3781	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
EricLew	0:80ee8f3b695e	3782	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3783	* @retval None
EricLew	0:80ee8f3b695e	3784	*/
EricLew	0:80ee8f3b695e	3785	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3786	{
EricLew	0:80ee8f3b695e	3787	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
EricLew	0:80ee8f3b695e	3788	}
EricLew	0:80ee8f3b695e	3789
EricLew	0:80ee8f3b695e	3790	/**
EricLew	0:80ee8f3b695e	3791	* @brief Disable capture/compare 1 interrupt (CC1IE).
EricLew	0:80ee8f3b695e	3792	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
EricLew	0:80ee8f3b695e	3793	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3794	* @retval None
EricLew	0:80ee8f3b695e	3795	*/
EricLew	0:80ee8f3b695e	3796	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3797	{
EricLew	0:80ee8f3b695e	3798	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
EricLew	0:80ee8f3b695e	3799	}
EricLew	0:80ee8f3b695e	3800
EricLew	0:80ee8f3b695e	3801	/**
EricLew	0:80ee8f3b695e	3802	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
EricLew	0:80ee8f3b695e	3803	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
EricLew	0:80ee8f3b695e	3804	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3805	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3806	*/
EricLew	0:80ee8f3b695e	3807	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3808	{
EricLew	0:80ee8f3b695e	3809	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
EricLew	0:80ee8f3b695e	3810	}
EricLew	0:80ee8f3b695e	3811
EricLew	0:80ee8f3b695e	3812	/**
EricLew	0:80ee8f3b695e	3813	* @brief Enable capture/compare 2 interrupt (CC2IE).
EricLew	0:80ee8f3b695e	3814	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
EricLew	0:80ee8f3b695e	3815	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3816	* @retval None
EricLew	0:80ee8f3b695e	3817	*/
EricLew	0:80ee8f3b695e	3818	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3819	{
EricLew	0:80ee8f3b695e	3820	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
EricLew	0:80ee8f3b695e	3821	}
EricLew	0:80ee8f3b695e	3822
EricLew	0:80ee8f3b695e	3823	/**
EricLew	0:80ee8f3b695e	3824	* @brief Disable capture/compare 2 interrupt (CC2IE).
EricLew	0:80ee8f3b695e	3825	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
EricLew	0:80ee8f3b695e	3826	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3827	* @retval None
EricLew	0:80ee8f3b695e	3828	*/
EricLew	0:80ee8f3b695e	3829	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3830	{
EricLew	0:80ee8f3b695e	3831	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
EricLew	0:80ee8f3b695e	3832	}
EricLew	0:80ee8f3b695e	3833
EricLew	0:80ee8f3b695e	3834	/**
EricLew	0:80ee8f3b695e	3835	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
EricLew	0:80ee8f3b695e	3836	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
EricLew	0:80ee8f3b695e	3837	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3838	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3839	*/
EricLew	0:80ee8f3b695e	3840	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3841	{
EricLew	0:80ee8f3b695e	3842	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
EricLew	0:80ee8f3b695e	3843	}
EricLew	0:80ee8f3b695e	3844
EricLew	0:80ee8f3b695e	3845	/**
EricLew	0:80ee8f3b695e	3846	* @brief Enable capture/compare 3 interrupt (CC3IE).
EricLew	0:80ee8f3b695e	3847	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
EricLew	0:80ee8f3b695e	3848	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3849	* @retval None
EricLew	0:80ee8f3b695e	3850	*/
EricLew	0:80ee8f3b695e	3851	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3852	{
EricLew	0:80ee8f3b695e	3853	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
EricLew	0:80ee8f3b695e	3854	}
EricLew	0:80ee8f3b695e	3855
EricLew	0:80ee8f3b695e	3856	/**
EricLew	0:80ee8f3b695e	3857	* @brief Disable capture/compare 3 interrupt (CC3IE).
EricLew	0:80ee8f3b695e	3858	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
EricLew	0:80ee8f3b695e	3859	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3860	* @retval None
EricLew	0:80ee8f3b695e	3861	*/
EricLew	0:80ee8f3b695e	3862	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3863	{
EricLew	0:80ee8f3b695e	3864	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
EricLew	0:80ee8f3b695e	3865	}
EricLew	0:80ee8f3b695e	3866
EricLew	0:80ee8f3b695e	3867	/**
EricLew	0:80ee8f3b695e	3868	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
EricLew	0:80ee8f3b695e	3869	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
EricLew	0:80ee8f3b695e	3870	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3871	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3872	*/
EricLew	0:80ee8f3b695e	3873	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3874	{
EricLew	0:80ee8f3b695e	3875	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
EricLew	0:80ee8f3b695e	3876	}
EricLew	0:80ee8f3b695e	3877
EricLew	0:80ee8f3b695e	3878	/**
EricLew	0:80ee8f3b695e	3879	* @brief Enable capture/compare 4 interrupt (CC4IE).
EricLew	0:80ee8f3b695e	3880	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
EricLew	0:80ee8f3b695e	3881	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3882	* @retval None
EricLew	0:80ee8f3b695e	3883	*/
EricLew	0:80ee8f3b695e	3884	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3885	{
EricLew	0:80ee8f3b695e	3886	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
EricLew	0:80ee8f3b695e	3887	}
EricLew	0:80ee8f3b695e	3888
EricLew	0:80ee8f3b695e	3889	/**
EricLew	0:80ee8f3b695e	3890	* @brief Disable capture/compare 4 interrupt (CC4IE).
EricLew	0:80ee8f3b695e	3891	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
EricLew	0:80ee8f3b695e	3892	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3893	* @retval None
EricLew	0:80ee8f3b695e	3894	*/
EricLew	0:80ee8f3b695e	3895	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3896	{
EricLew	0:80ee8f3b695e	3897	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
EricLew	0:80ee8f3b695e	3898	}
EricLew	0:80ee8f3b695e	3899
EricLew	0:80ee8f3b695e	3900	/**
EricLew	0:80ee8f3b695e	3901	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
EricLew	0:80ee8f3b695e	3902	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
EricLew	0:80ee8f3b695e	3903	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3904	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3905	*/
EricLew	0:80ee8f3b695e	3906	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3907	{
EricLew	0:80ee8f3b695e	3908	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
EricLew	0:80ee8f3b695e	3909	}
EricLew	0:80ee8f3b695e	3910
EricLew	0:80ee8f3b695e	3911	/**
EricLew	0:80ee8f3b695e	3912	* @brief Enable commutation interrupt (COMIE).
EricLew	0:80ee8f3b695e	3913	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
EricLew	0:80ee8f3b695e	3914	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3915	* @retval None
EricLew	0:80ee8f3b695e	3916	*/
EricLew	0:80ee8f3b695e	3917	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3918	{
EricLew	0:80ee8f3b695e	3919	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
EricLew	0:80ee8f3b695e	3920	}
EricLew	0:80ee8f3b695e	3921
EricLew	0:80ee8f3b695e	3922	/**
EricLew	0:80ee8f3b695e	3923	* @brief Disable commutation interrupt (COMIE).
EricLew	0:80ee8f3b695e	3924	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
EricLew	0:80ee8f3b695e	3925	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3926	* @retval None
EricLew	0:80ee8f3b695e	3927	*/
EricLew	0:80ee8f3b695e	3928	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3929	{
EricLew	0:80ee8f3b695e	3930	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
EricLew	0:80ee8f3b695e	3931	}
EricLew	0:80ee8f3b695e	3932
EricLew	0:80ee8f3b695e	3933	/**
EricLew	0:80ee8f3b695e	3934	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
EricLew	0:80ee8f3b695e	3935	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
EricLew	0:80ee8f3b695e	3936	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3937	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3938	*/
EricLew	0:80ee8f3b695e	3939	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3940	{
EricLew	0:80ee8f3b695e	3941	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
EricLew	0:80ee8f3b695e	3942	}
EricLew	0:80ee8f3b695e	3943
EricLew	0:80ee8f3b695e	3944	/**
EricLew	0:80ee8f3b695e	3945	* @brief Enable trigger interrupt (TIE).
EricLew	0:80ee8f3b695e	3946	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
EricLew	0:80ee8f3b695e	3947	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3948	* @retval None
EricLew	0:80ee8f3b695e	3949	*/
EricLew	0:80ee8f3b695e	3950	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3951	{
EricLew	0:80ee8f3b695e	3952	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
EricLew	0:80ee8f3b695e	3953	}
EricLew	0:80ee8f3b695e	3954
EricLew	0:80ee8f3b695e	3955	/**
EricLew	0:80ee8f3b695e	3956	* @brief Disable trigger interrupt (TIE).
EricLew	0:80ee8f3b695e	3957	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
EricLew	0:80ee8f3b695e	3958	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3959	* @retval None
EricLew	0:80ee8f3b695e	3960	*/
EricLew	0:80ee8f3b695e	3961	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3962	{
EricLew	0:80ee8f3b695e	3963	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
EricLew	0:80ee8f3b695e	3964	}
EricLew	0:80ee8f3b695e	3965
EricLew	0:80ee8f3b695e	3966	/**
EricLew	0:80ee8f3b695e	3967	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
EricLew	0:80ee8f3b695e	3968	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
EricLew	0:80ee8f3b695e	3969	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3970	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	3971	*/
EricLew	0:80ee8f3b695e	3972	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3973	{
EricLew	0:80ee8f3b695e	3974	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
EricLew	0:80ee8f3b695e	3975	}
EricLew	0:80ee8f3b695e	3976
EricLew	0:80ee8f3b695e	3977	/**
EricLew	0:80ee8f3b695e	3978	* @brief Enable break interrupt (BIE).
EricLew	0:80ee8f3b695e	3979	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
EricLew	0:80ee8f3b695e	3980	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3981	* @retval None
EricLew	0:80ee8f3b695e	3982	*/
EricLew	0:80ee8f3b695e	3983	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3984	{
EricLew	0:80ee8f3b695e	3985	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
EricLew	0:80ee8f3b695e	3986	}
EricLew	0:80ee8f3b695e	3987
EricLew	0:80ee8f3b695e	3988	/**
EricLew	0:80ee8f3b695e	3989	* @brief Disable break interrupt (BIE).
EricLew	0:80ee8f3b695e	3990	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
EricLew	0:80ee8f3b695e	3991	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	3992	* @retval None
EricLew	0:80ee8f3b695e	3993	*/
EricLew	0:80ee8f3b695e	3994	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	3995	{
EricLew	0:80ee8f3b695e	3996	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
EricLew	0:80ee8f3b695e	3997	}
EricLew	0:80ee8f3b695e	3998
EricLew	0:80ee8f3b695e	3999	/**
EricLew	0:80ee8f3b695e	4000	* @brief Indicates whether the break interrupt (BIE) is enabled.
EricLew	0:80ee8f3b695e	4001	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
EricLew	0:80ee8f3b695e	4002	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4003	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4004	*/
EricLew	0:80ee8f3b695e	4005	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4006	{
EricLew	0:80ee8f3b695e	4007	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
EricLew	0:80ee8f3b695e	4008	}
EricLew	0:80ee8f3b695e	4009
EricLew	0:80ee8f3b695e	4010	/**
EricLew	0:80ee8f3b695e	4011	* @}
EricLew	0:80ee8f3b695e	4012	*/
EricLew	0:80ee8f3b695e	4013
EricLew	0:80ee8f3b695e	4014	/** @defgroup TIM_LL_EF_DMA_Management DMA_Management
EricLew	0:80ee8f3b695e	4015	* @{
EricLew	0:80ee8f3b695e	4016	*/
EricLew	0:80ee8f3b695e	4017	/**
EricLew	0:80ee8f3b695e	4018	* @brief Enable update DMA request (UDE).
EricLew	0:80ee8f3b695e	4019	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
EricLew	0:80ee8f3b695e	4020	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4021	* @retval None
EricLew	0:80ee8f3b695e	4022	*/
EricLew	0:80ee8f3b695e	4023	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4024	{
EricLew	0:80ee8f3b695e	4025	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
EricLew	0:80ee8f3b695e	4026	}
EricLew	0:80ee8f3b695e	4027
EricLew	0:80ee8f3b695e	4028	/**
EricLew	0:80ee8f3b695e	4029	* @brief Disable update DMA request (UDE).
EricLew	0:80ee8f3b695e	4030	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
EricLew	0:80ee8f3b695e	4031	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4032	* @retval None
EricLew	0:80ee8f3b695e	4033	*/
EricLew	0:80ee8f3b695e	4034	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4035	{
EricLew	0:80ee8f3b695e	4036	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
EricLew	0:80ee8f3b695e	4037	}
EricLew	0:80ee8f3b695e	4038
EricLew	0:80ee8f3b695e	4039	/**
EricLew	0:80ee8f3b695e	4040	* @brief Indicates whether the update DMA request (UDE) is enabled.
EricLew	0:80ee8f3b695e	4041	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
EricLew	0:80ee8f3b695e	4042	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4043	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4044	*/
EricLew	0:80ee8f3b695e	4045	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4046	{
EricLew	0:80ee8f3b695e	4047	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
EricLew	0:80ee8f3b695e	4048	}
EricLew	0:80ee8f3b695e	4049
EricLew	0:80ee8f3b695e	4050	/**
EricLew	0:80ee8f3b695e	4051	* @brief Enable capture/compare 1 DMA request (CC1DE).
EricLew	0:80ee8f3b695e	4052	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
EricLew	0:80ee8f3b695e	4053	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4054	* @retval None
EricLew	0:80ee8f3b695e	4055	*/
EricLew	0:80ee8f3b695e	4056	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4057	{
EricLew	0:80ee8f3b695e	4058	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
EricLew	0:80ee8f3b695e	4059	}
EricLew	0:80ee8f3b695e	4060
EricLew	0:80ee8f3b695e	4061	/**
EricLew	0:80ee8f3b695e	4062	* @brief Disable capture/compare 1 DMA request (CC1DE).
EricLew	0:80ee8f3b695e	4063	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
EricLew	0:80ee8f3b695e	4064	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4065	* @retval None
EricLew	0:80ee8f3b695e	4066	*/
EricLew	0:80ee8f3b695e	4067	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4068	{
EricLew	0:80ee8f3b695e	4069	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
EricLew	0:80ee8f3b695e	4070	}
EricLew	0:80ee8f3b695e	4071
EricLew	0:80ee8f3b695e	4072	/**
EricLew	0:80ee8f3b695e	4073	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
EricLew	0:80ee8f3b695e	4074	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
EricLew	0:80ee8f3b695e	4075	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4076	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4077	*/
EricLew	0:80ee8f3b695e	4078	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4079	{
EricLew	0:80ee8f3b695e	4080	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
EricLew	0:80ee8f3b695e	4081	}
EricLew	0:80ee8f3b695e	4082
EricLew	0:80ee8f3b695e	4083	/**
EricLew	0:80ee8f3b695e	4084	* @brief Enable capture/compare 2 DMA request (CC2DE).
EricLew	0:80ee8f3b695e	4085	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
EricLew	0:80ee8f3b695e	4086	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4087	* @retval None
EricLew	0:80ee8f3b695e	4088	*/
EricLew	0:80ee8f3b695e	4089	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4090	{
EricLew	0:80ee8f3b695e	4091	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
EricLew	0:80ee8f3b695e	4092	}
EricLew	0:80ee8f3b695e	4093
EricLew	0:80ee8f3b695e	4094	/**
EricLew	0:80ee8f3b695e	4095	* @brief Disable capture/compare 2 DMA request (CC2DE).
EricLew	0:80ee8f3b695e	4096	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
EricLew	0:80ee8f3b695e	4097	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4098	* @retval None
EricLew	0:80ee8f3b695e	4099	*/
EricLew	0:80ee8f3b695e	4100	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4101	{
EricLew	0:80ee8f3b695e	4102	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
EricLew	0:80ee8f3b695e	4103	}
EricLew	0:80ee8f3b695e	4104
EricLew	0:80ee8f3b695e	4105	/**
EricLew	0:80ee8f3b695e	4106	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
EricLew	0:80ee8f3b695e	4107	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
EricLew	0:80ee8f3b695e	4108	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4109	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4110	*/
EricLew	0:80ee8f3b695e	4111	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4112	{
EricLew	0:80ee8f3b695e	4113	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
EricLew	0:80ee8f3b695e	4114	}
EricLew	0:80ee8f3b695e	4115
EricLew	0:80ee8f3b695e	4116	/**
EricLew	0:80ee8f3b695e	4117	* @brief Enable capture/compare 3 DMA request (CC3DE).
EricLew	0:80ee8f3b695e	4118	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
EricLew	0:80ee8f3b695e	4119	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4120	* @retval None
EricLew	0:80ee8f3b695e	4121	*/
EricLew	0:80ee8f3b695e	4122	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4123	{
EricLew	0:80ee8f3b695e	4124	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
EricLew	0:80ee8f3b695e	4125	}
EricLew	0:80ee8f3b695e	4126
EricLew	0:80ee8f3b695e	4127	/**
EricLew	0:80ee8f3b695e	4128	* @brief Disable capture/compare 3 DMA request (CC3DE).
EricLew	0:80ee8f3b695e	4129	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
EricLew	0:80ee8f3b695e	4130	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4131	* @retval None
EricLew	0:80ee8f3b695e	4132	*/
EricLew	0:80ee8f3b695e	4133	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4134	{
EricLew	0:80ee8f3b695e	4135	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
EricLew	0:80ee8f3b695e	4136	}
EricLew	0:80ee8f3b695e	4137
EricLew	0:80ee8f3b695e	4138	/**
EricLew	0:80ee8f3b695e	4139	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
EricLew	0:80ee8f3b695e	4140	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
EricLew	0:80ee8f3b695e	4141	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4142	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4143	*/
EricLew	0:80ee8f3b695e	4144	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4145	{
EricLew	0:80ee8f3b695e	4146	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
EricLew	0:80ee8f3b695e	4147	}
EricLew	0:80ee8f3b695e	4148
EricLew	0:80ee8f3b695e	4149	/**
EricLew	0:80ee8f3b695e	4150	* @brief Enable capture/compare 4 DMA request (CC4DE).
EricLew	0:80ee8f3b695e	4151	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
EricLew	0:80ee8f3b695e	4152	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4153	* @retval None
EricLew	0:80ee8f3b695e	4154	*/
EricLew	0:80ee8f3b695e	4155	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4156	{
EricLew	0:80ee8f3b695e	4157	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
EricLew	0:80ee8f3b695e	4158	}
EricLew	0:80ee8f3b695e	4159
EricLew	0:80ee8f3b695e	4160	/**
EricLew	0:80ee8f3b695e	4161	* @brief Disable capture/compare 4 DMA request (CC4DE).
EricLew	0:80ee8f3b695e	4162	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
EricLew	0:80ee8f3b695e	4163	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4164	* @retval None
EricLew	0:80ee8f3b695e	4165	*/
EricLew	0:80ee8f3b695e	4166	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4167	{
EricLew	0:80ee8f3b695e	4168	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
EricLew	0:80ee8f3b695e	4169	}
EricLew	0:80ee8f3b695e	4170
EricLew	0:80ee8f3b695e	4171	/**
EricLew	0:80ee8f3b695e	4172	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
EricLew	0:80ee8f3b695e	4173	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
EricLew	0:80ee8f3b695e	4174	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4175	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4176	*/
EricLew	0:80ee8f3b695e	4177	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4178	{
EricLew	0:80ee8f3b695e	4179	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
EricLew	0:80ee8f3b695e	4180	}
EricLew	0:80ee8f3b695e	4181
EricLew	0:80ee8f3b695e	4182	/**
EricLew	0:80ee8f3b695e	4183	* @brief Enable commutation DMA request (COMDE).
EricLew	0:80ee8f3b695e	4184	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
EricLew	0:80ee8f3b695e	4185	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4186	* @retval None
EricLew	0:80ee8f3b695e	4187	*/
EricLew	0:80ee8f3b695e	4188	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4189	{
EricLew	0:80ee8f3b695e	4190	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
EricLew	0:80ee8f3b695e	4191	}
EricLew	0:80ee8f3b695e	4192
EricLew	0:80ee8f3b695e	4193	/**
EricLew	0:80ee8f3b695e	4194	* @brief Disable commutation DMA request (COMDE).
EricLew	0:80ee8f3b695e	4195	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
EricLew	0:80ee8f3b695e	4196	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4197	* @retval None
EricLew	0:80ee8f3b695e	4198	*/
EricLew	0:80ee8f3b695e	4199	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4200	{
EricLew	0:80ee8f3b695e	4201	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
EricLew	0:80ee8f3b695e	4202	}
EricLew	0:80ee8f3b695e	4203
EricLew	0:80ee8f3b695e	4204	/**
EricLew	0:80ee8f3b695e	4205	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
EricLew	0:80ee8f3b695e	4206	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
EricLew	0:80ee8f3b695e	4207	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4208	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4209	*/
EricLew	0:80ee8f3b695e	4210	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4211	{
EricLew	0:80ee8f3b695e	4212	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
EricLew	0:80ee8f3b695e	4213	}
EricLew	0:80ee8f3b695e	4214
EricLew	0:80ee8f3b695e	4215	/**
EricLew	0:80ee8f3b695e	4216	* @brief Enable trigger interrupt (TDE).
EricLew	0:80ee8f3b695e	4217	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
EricLew	0:80ee8f3b695e	4218	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4219	* @retval None
EricLew	0:80ee8f3b695e	4220	*/
EricLew	0:80ee8f3b695e	4221	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4222	{
EricLew	0:80ee8f3b695e	4223	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
EricLew	0:80ee8f3b695e	4224	}
EricLew	0:80ee8f3b695e	4225
EricLew	0:80ee8f3b695e	4226	/**
EricLew	0:80ee8f3b695e	4227	* @brief Disable trigger interrupt (TDE).
EricLew	0:80ee8f3b695e	4228	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
EricLew	0:80ee8f3b695e	4229	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4230	* @retval None
EricLew	0:80ee8f3b695e	4231	*/
EricLew	0:80ee8f3b695e	4232	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4233	{
EricLew	0:80ee8f3b695e	4234	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
EricLew	0:80ee8f3b695e	4235	}
EricLew	0:80ee8f3b695e	4236
EricLew	0:80ee8f3b695e	4237	/**
EricLew	0:80ee8f3b695e	4238	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
EricLew	0:80ee8f3b695e	4239	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
EricLew	0:80ee8f3b695e	4240	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4241	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	4242	*/
EricLew	0:80ee8f3b695e	4243	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4244	{
EricLew	0:80ee8f3b695e	4245	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
EricLew	0:80ee8f3b695e	4246	}
EricLew	0:80ee8f3b695e	4247
EricLew	0:80ee8f3b695e	4248	/**
EricLew	0:80ee8f3b695e	4249	* @}
EricLew	0:80ee8f3b695e	4250	*/
EricLew	0:80ee8f3b695e	4251
EricLew	0:80ee8f3b695e	4252	/** @defgroup TIM_LL_EF_EVENT_Management EVENT_Management
EricLew	0:80ee8f3b695e	4253	* @{
EricLew	0:80ee8f3b695e	4254	*/
EricLew	0:80ee8f3b695e	4255	/**
EricLew	0:80ee8f3b695e	4256	* @brief Generate an update event.
EricLew	0:80ee8f3b695e	4257	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
EricLew	0:80ee8f3b695e	4258	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4259	* @retval None
EricLew	0:80ee8f3b695e	4260	*/
EricLew	0:80ee8f3b695e	4261	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4262	{
EricLew	0:80ee8f3b695e	4263	SET_BIT(TIMx->EGR, TIM_EGR_UG);
EricLew	0:80ee8f3b695e	4264	}
EricLew	0:80ee8f3b695e	4265
EricLew	0:80ee8f3b695e	4266	/**
EricLew	0:80ee8f3b695e	4267	* @brief Generate Capture/Compare 1 event.
EricLew	0:80ee8f3b695e	4268	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
EricLew	0:80ee8f3b695e	4269	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4270	* @retval None
EricLew	0:80ee8f3b695e	4271	*/
EricLew	0:80ee8f3b695e	4272	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4273	{
EricLew	0:80ee8f3b695e	4274	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
EricLew	0:80ee8f3b695e	4275	}
EricLew	0:80ee8f3b695e	4276
EricLew	0:80ee8f3b695e	4277	/**
EricLew	0:80ee8f3b695e	4278	* @brief Generate Capture/Compare 2 event.
EricLew	0:80ee8f3b695e	4279	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
EricLew	0:80ee8f3b695e	4280	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4281	* @retval None
EricLew	0:80ee8f3b695e	4282	*/
EricLew	0:80ee8f3b695e	4283	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4284	{
EricLew	0:80ee8f3b695e	4285	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
EricLew	0:80ee8f3b695e	4286	}
EricLew	0:80ee8f3b695e	4287
EricLew	0:80ee8f3b695e	4288	/**
EricLew	0:80ee8f3b695e	4289	* @brief Generate Capture/Compare 3 event.
EricLew	0:80ee8f3b695e	4290	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
EricLew	0:80ee8f3b695e	4291	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4292	* @retval None
EricLew	0:80ee8f3b695e	4293	*/
EricLew	0:80ee8f3b695e	4294	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4295	{
EricLew	0:80ee8f3b695e	4296	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
EricLew	0:80ee8f3b695e	4297	}
EricLew	0:80ee8f3b695e	4298
EricLew	0:80ee8f3b695e	4299	/**
EricLew	0:80ee8f3b695e	4300	* @brief Generate Capture/Compare 4 event.
EricLew	0:80ee8f3b695e	4301	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
EricLew	0:80ee8f3b695e	4302	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4303	* @retval None
EricLew	0:80ee8f3b695e	4304	*/
EricLew	0:80ee8f3b695e	4305	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4306	{
EricLew	0:80ee8f3b695e	4307	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
EricLew	0:80ee8f3b695e	4308	}
EricLew	0:80ee8f3b695e	4309
EricLew	0:80ee8f3b695e	4310	/**
EricLew	0:80ee8f3b695e	4311	* @brief Generate commutation event.
EricLew	0:80ee8f3b695e	4312	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
EricLew	0:80ee8f3b695e	4313	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4314	* @retval None
EricLew	0:80ee8f3b695e	4315	*/
EricLew	0:80ee8f3b695e	4316	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4317	{
EricLew	0:80ee8f3b695e	4318	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
EricLew	0:80ee8f3b695e	4319	}
EricLew	0:80ee8f3b695e	4320
EricLew	0:80ee8f3b695e	4321	/**
EricLew	0:80ee8f3b695e	4322	* @brief Generate trigger event.
EricLew	0:80ee8f3b695e	4323	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
EricLew	0:80ee8f3b695e	4324	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4325	* @retval None
EricLew	0:80ee8f3b695e	4326	*/
EricLew	0:80ee8f3b695e	4327	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4328	{
EricLew	0:80ee8f3b695e	4329	SET_BIT(TIMx->EGR, TIM_EGR_TG);
EricLew	0:80ee8f3b695e	4330	}
EricLew	0:80ee8f3b695e	4331
EricLew	0:80ee8f3b695e	4332	/**
EricLew	0:80ee8f3b695e	4333	* @brief Generate break event.
EricLew	0:80ee8f3b695e	4334	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
EricLew	0:80ee8f3b695e	4335	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4336	* @retval None
EricLew	0:80ee8f3b695e	4337	*/
EricLew	0:80ee8f3b695e	4338	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4339	{
EricLew	0:80ee8f3b695e	4340	SET_BIT(TIMx->EGR, TIM_EGR_BG);
EricLew	0:80ee8f3b695e	4341	}
EricLew	0:80ee8f3b695e	4342
EricLew	0:80ee8f3b695e	4343	/**
EricLew	0:80ee8f3b695e	4344	* @brief Generate break 2 event.
EricLew	0:80ee8f3b695e	4345	* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
EricLew	0:80ee8f3b695e	4346	* @param TIMx Timer instance
EricLew	0:80ee8f3b695e	4347	* @retval None
EricLew	0:80ee8f3b695e	4348	*/
EricLew	0:80ee8f3b695e	4349	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef * TIMx)
EricLew	0:80ee8f3b695e	4350	{
EricLew	0:80ee8f3b695e	4351	SET_BIT(TIMx->EGR, TIM_EGR_B2G);
EricLew	0:80ee8f3b695e	4352	}
EricLew	0:80ee8f3b695e	4353
EricLew	0:80ee8f3b695e	4354	/**
EricLew	0:80ee8f3b695e	4355	* @}
EricLew	0:80ee8f3b695e	4356	*/
EricLew	0:80ee8f3b695e	4357
EricLew	0:80ee8f3b695e	4358	/**
EricLew	0:80ee8f3b695e	4359	* @}
EricLew	0:80ee8f3b695e	4360	*/
EricLew	0:80ee8f3b695e	4361
EricLew	0:80ee8f3b695e	4362	/**
EricLew	0:80ee8f3b695e	4363	* @}
EricLew	0:80ee8f3b695e	4364	*/
EricLew	0:80ee8f3b695e	4365
EricLew	0:80ee8f3b695e	4366	#endif /* TIM1 \|\| TIM8 \|\| TIM2 \|\| TIM3 \|\| TIM4 \|\| TIM5 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
EricLew	0:80ee8f3b695e	4367
EricLew	0:80ee8f3b695e	4368	/**
EricLew	0:80ee8f3b695e	4369	* @}
EricLew	0:80ee8f3b695e	4370	*/
EricLew	0:80ee8f3b695e	4371
EricLew	0:80ee8f3b695e	4372	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	4373	}
EricLew	0:80ee8f3b695e	4374	#endif
EricLew	0:80ee8f3b695e	4375
EricLew	0:80ee8f3b695e	4376	#endif /* __STM32L4xx_LL_TIM_H */
EricLew	0:80ee8f3b695e	4377
EricLew	0:80ee8f3b695e	4378	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	4379

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_tim.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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