STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_system.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

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User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_system.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of SYSTEM LL module.
EricLew	0:80ee8f3b695e	8	@verbatim
EricLew	0:80ee8f3b695e	9	==============================================================================
EricLew	0:80ee8f3b695e	10	##### How to use this driver #####
EricLew	0:80ee8f3b695e	11	==============================================================================
EricLew	0:80ee8f3b695e	12	[..]
EricLew	0:80ee8f3b695e	13	The LL SYSTEM driver contains a set of generic APIs that can be
EricLew	0:80ee8f3b695e	14	used by user:
EricLew	0:80ee8f3b695e	15	(+) Some of the FLASH features need to be handled in the SYSTEM file.
EricLew	0:80ee8f3b695e	16	(+) Access to DBGCMU registers
EricLew	0:80ee8f3b695e	17	(+) Access to SYSCFG registers
EricLew	0:80ee8f3b695e	18	(+) Access to VREFBUF registers
EricLew	0:80ee8f3b695e	19
EricLew	0:80ee8f3b695e	20	@endverbatim
EricLew	0:80ee8f3b695e	21	******************************************************************************
EricLew	0:80ee8f3b695e	22	* @attention
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	25	*
EricLew	0:80ee8f3b695e	26	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	27	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	28	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	29	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	30	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	31	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	32	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	33	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	34	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	35	* without specific prior written permission.
EricLew	0:80ee8f3b695e	36	*
EricLew	0:80ee8f3b695e	37	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	38	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	39	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	40	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	41	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	42	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	43	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	44	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	45	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	46	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	47	*
EricLew	0:80ee8f3b695e	48	******************************************************************************
EricLew	0:80ee8f3b695e	49	*/
EricLew	0:80ee8f3b695e	50
EricLew	0:80ee8f3b695e	51	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	52	#ifndef __STM32L4xx_LL_SYSTEM_H
EricLew	0:80ee8f3b695e	53	#define __STM32L4xx_LL_SYSTEM_H
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	56	extern "C" {
EricLew	0:80ee8f3b695e	57	#endif
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	61
EricLew	0:80ee8f3b695e	62	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	63	* @{
EricLew	0:80ee8f3b695e	64	*/
EricLew	0:80ee8f3b695e	65
EricLew	0:80ee8f3b695e	66	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF)
EricLew	0:80ee8f3b695e	67
EricLew	0:80ee8f3b695e	68	/** @defgroup SYSTEM_LL SYSTEM
EricLew	0:80ee8f3b695e	69	* @{
EricLew	0:80ee8f3b695e	70	*/
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	73	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	74
EricLew	0:80ee8f3b695e	75	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	76	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
EricLew	0:80ee8f3b695e	77	* @{
EricLew	0:80ee8f3b695e	78	*/
EricLew	0:80ee8f3b695e	79
EricLew	0:80ee8f3b695e	80	/* Defines used for position in the register */
EricLew	0:80ee8f3b695e	81	#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
EricLew	0:80ee8f3b695e	82
EricLew	0:80ee8f3b695e	83	/**
EricLew	0:80ee8f3b695e	84	* @brief Power-down in Run mode Flash key
EricLew	0:80ee8f3b695e	85	*/
EricLew	0:80ee8f3b695e	86	#define FLASH_PDKEY1 ((uint32_t)0x04152637) /!< Flash power down key1 /
EricLew	0:80ee8f3b695e	87	#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
EricLew	0:80ee8f3b695e	88	to unlock the RUN_PD bit in FLASH_ACR */
EricLew	0:80ee8f3b695e	89
EricLew	0:80ee8f3b695e	90	/**
EricLew	0:80ee8f3b695e	91	* @}
EricLew	0:80ee8f3b695e	92	*/
EricLew	0:80ee8f3b695e	93
EricLew	0:80ee8f3b695e	94	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	95
EricLew	0:80ee8f3b695e	96	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	97	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	98	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
EricLew	0:80ee8f3b695e	99	* @{
EricLew	0:80ee8f3b695e	100	*/
EricLew	0:80ee8f3b695e	101
EricLew	0:80ee8f3b695e	102	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
EricLew	0:80ee8f3b695e	103	* @{
EricLew	0:80ee8f3b695e	104	*/
EricLew	0:80ee8f3b695e	105	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /!< Main Flash memory mapped at 0x00000000 /
EricLew	0:80ee8f3b695e	106	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
EricLew	0:80ee8f3b695e	107	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 \| SYSCFG_MEMRMP_MEM_MODE_0) /!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 /
EricLew	0:80ee8f3b695e	108	#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /!< SRAM1 mapped at 0x00000000 /
EricLew	0:80ee8f3b695e	109	#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 \| SYSCFG_MEMRMP_MEM_MODE_1) /!< QUADSPI memory mapped at 0x00000000 /
EricLew	0:80ee8f3b695e	110	/**
EricLew	0:80ee8f3b695e	111	* @}
EricLew	0:80ee8f3b695e	112	*/
EricLew	0:80ee8f3b695e	113
EricLew	0:80ee8f3b695e	114	/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
EricLew	0:80ee8f3b695e	115	* @{
EricLew	0:80ee8f3b695e	116	*/
EricLew	0:80ee8f3b695e	117	#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000 /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
EricLew	0:80ee8f3b695e	118	and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
EricLew	0:80ee8f3b695e	119	#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
EricLew	0:80ee8f3b695e	120	and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
EricLew	0:80ee8f3b695e	121	/**
EricLew	0:80ee8f3b695e	122	* @}
EricLew	0:80ee8f3b695e	123	*/
EricLew	0:80ee8f3b695e	124
EricLew	0:80ee8f3b695e	125	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
EricLew	0:80ee8f3b695e	126	* @{
EricLew	0:80ee8f3b695e	127	*/
EricLew	0:80ee8f3b695e	128	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /!< Enable Fast Mode Plus on PB6 /
EricLew	0:80ee8f3b695e	129	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /!< Enable Fast Mode Plus on PB7 /
EricLew	0:80ee8f3b695e	130	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /!< Enable Fast Mode Plus on PB8 /
EricLew	0:80ee8f3b695e	131	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /!< Enable Fast Mode Plus on PB9 /
EricLew	0:80ee8f3b695e	132	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /!< Enable Fast Mode Plus on I2C1 pins /
EricLew	0:80ee8f3b695e	133	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /!< Enable Fast Mode Plus on I2C2 pins /
EricLew	0:80ee8f3b695e	134	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /!< Enable Fast Mode Plus on I2C3 pins /
EricLew	0:80ee8f3b695e	135	/**
EricLew	0:80ee8f3b695e	136	* @}
EricLew	0:80ee8f3b695e	137	*/
EricLew	0:80ee8f3b695e	138
EricLew	0:80ee8f3b695e	139	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
EricLew	0:80ee8f3b695e	140	* @{
EricLew	0:80ee8f3b695e	141	*/
EricLew	0:80ee8f3b695e	142	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0 /!< EXTI PORT A /
EricLew	0:80ee8f3b695e	143	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1 /!< EXTI PORT B /
EricLew	0:80ee8f3b695e	144	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2 /!< EXTI PORT C /
EricLew	0:80ee8f3b695e	145	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3 /!< EXTI PORT D /
EricLew	0:80ee8f3b695e	146	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4 /!< EXTI PORT E /
EricLew	0:80ee8f3b695e	147	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5 /!< EXTI PORT F /
EricLew	0:80ee8f3b695e	148	#define LL_SYSCFG_EXTI_PORTG (uint32_t)6 /!< EXTI PORT G /
EricLew	0:80ee8f3b695e	149	#define LL_SYSCFG_EXTI_PORTH (uint32_t)7 /!< EXTI PORT H /
EricLew	0:80ee8f3b695e	150	/**
EricLew	0:80ee8f3b695e	151	* @}
EricLew	0:80ee8f3b695e	152	*/
EricLew	0:80ee8f3b695e	153
EricLew	0:80ee8f3b695e	154	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
EricLew	0:80ee8f3b695e	155	* @{
EricLew	0:80ee8f3b695e	156	*/
EricLew	0:80ee8f3b695e	157	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 \| 0) /* !< EXTI_POSITION_0 \| EXTICR[0] */
EricLew	0:80ee8f3b695e	158	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 \| 0) /* !< EXTI_POSITION_4 \| EXTICR[0] */
EricLew	0:80ee8f3b695e	159	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 \| 0) /* !< EXTI_POSITION_8 \| EXTICR[0] */
EricLew	0:80ee8f3b695e	160	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 \| 0) /* !< EXTI_POSITION_12 \| EXTICR[0] */
EricLew	0:80ee8f3b695e	161	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 \| 1) /* !< EXTI_POSITION_0 \| EXTICR[1] */
EricLew	0:80ee8f3b695e	162	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 \| 1) /* !< EXTI_POSITION_4 \| EXTICR[1] */
EricLew	0:80ee8f3b695e	163	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 \| 1) /* !< EXTI_POSITION_8 \| EXTICR[1] */
EricLew	0:80ee8f3b695e	164	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 \| 1) /* !< EXTI_POSITION_12 \| EXTICR[1] */
EricLew	0:80ee8f3b695e	165	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 \| 2) /* !< EXTI_POSITION_0 \| EXTICR[2] */
EricLew	0:80ee8f3b695e	166	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 \| 2) /* !< EXTI_POSITION_4 \| EXTICR[2] */
EricLew	0:80ee8f3b695e	167	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 \| 2) /* !< EXTI_POSITION_8 \| EXTICR[2] */
EricLew	0:80ee8f3b695e	168	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 \| 2) /* !< EXTI_POSITION_12 \| EXTICR[2] */
EricLew	0:80ee8f3b695e	169	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 \| 3) /* !< EXTI_POSITION_0 \| EXTICR[3] */
EricLew	0:80ee8f3b695e	170	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 \| 3) /* !< EXTI_POSITION_4 \| EXTICR[3] */
EricLew	0:80ee8f3b695e	171	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 \| 3) /* !< EXTI_POSITION_8 \| EXTICR[3] */
EricLew	0:80ee8f3b695e	172	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 \| 3) /* !< EXTI_POSITION_12 \| EXTICR[3] */
EricLew	0:80ee8f3b695e	173	/**
EricLew	0:80ee8f3b695e	174	* @}
EricLew	0:80ee8f3b695e	175	*/
EricLew	0:80ee8f3b695e	176
EricLew	0:80ee8f3b695e	177	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
EricLew	0:80ee8f3b695e	178	* @{
EricLew	0:80ee8f3b695e	179	*/
EricLew	0:80ee8f3b695e	180	#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
EricLew	0:80ee8f3b695e	181	with Break Input of TIM1/8/15/16/17 */
EricLew	0:80ee8f3b695e	182	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
EricLew	0:80ee8f3b695e	183	with TIM1/8/15/16/17 Break Input
EricLew	0:80ee8f3b695e	184	and also the PVDE and PLS bits of the Power Control Interface */
EricLew	0:80ee8f3b695e	185	#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
EricLew	0:80ee8f3b695e	186	with Break Input of TIM1/8/15/16/17 */
EricLew	0:80ee8f3b695e	187	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
EricLew	0:80ee8f3b695e	188	with Break Input of TIM1/15/16/17 */
EricLew	0:80ee8f3b695e	189	/**
EricLew	0:80ee8f3b695e	190	* @}
EricLew	0:80ee8f3b695e	191	*/
EricLew	0:80ee8f3b695e	192
EricLew	0:80ee8f3b695e	193	/** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
EricLew	0:80ee8f3b695e	194	* @{
EricLew	0:80ee8f3b695e	195	*/
EricLew	0:80ee8f3b695e	196	#define LL_SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /!< SRAM2 Write protection page 0 /
EricLew	0:80ee8f3b695e	197	#define LL_SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /!< SRAM2 Write protection page 1 /
EricLew	0:80ee8f3b695e	198	#define LL_SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /!< SRAM2 Write protection page 2 /
EricLew	0:80ee8f3b695e	199	#define LL_SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /!< SRAM2 Write protection page 3 /
EricLew	0:80ee8f3b695e	200	#define LL_SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /!< SRAM2 Write protection page 4 /
EricLew	0:80ee8f3b695e	201	#define LL_SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /!< SRAM2 Write protection page 5 /
EricLew	0:80ee8f3b695e	202	#define LL_SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /!< SRAM2 Write protection page 6 /
EricLew	0:80ee8f3b695e	203	#define LL_SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /!< SRAM2 Write protection page 7 /
EricLew	0:80ee8f3b695e	204	#define LL_SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /!< SRAM2 Write protection page 8 /
EricLew	0:80ee8f3b695e	205	#define LL_SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /!< SRAM2 Write protection page 9 /
EricLew	0:80ee8f3b695e	206	#define LL_SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /!< SRAM2 Write protection page 10 /
EricLew	0:80ee8f3b695e	207	#define LL_SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /!< SRAM2 Write protection page 11 /
EricLew	0:80ee8f3b695e	208	#define LL_SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /!< SRAM2 Write protection page 12 /
EricLew	0:80ee8f3b695e	209	#define LL_SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /!< SRAM2 Write protection page 13 /
EricLew	0:80ee8f3b695e	210	#define LL_SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /!< SRAM2 Write protection page 14 /
EricLew	0:80ee8f3b695e	211	#define LL_SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /!< SRAM2 Write protection page 15 /
EricLew	0:80ee8f3b695e	212	#define LL_SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /!< SRAM2 Write protection page 16 /
EricLew	0:80ee8f3b695e	213	#define LL_SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /!< SRAM2 Write protection page 17 /
EricLew	0:80ee8f3b695e	214	#define LL_SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /!< SRAM2 Write protection page 18 /
EricLew	0:80ee8f3b695e	215	#define LL_SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /!< SRAM2 Write protection page 19 /
EricLew	0:80ee8f3b695e	216	#define LL_SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /!< SRAM2 Write protection page 20 /
EricLew	0:80ee8f3b695e	217	#define LL_SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /!< SRAM2 Write protection page 21 /
EricLew	0:80ee8f3b695e	218	#define LL_SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /!< SRAM2 Write protection page 22 /
EricLew	0:80ee8f3b695e	219	#define LL_SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /!< SRAM2 Write protection page 23 /
EricLew	0:80ee8f3b695e	220	#define LL_SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /!< SRAM2 Write protection page 24 /
EricLew	0:80ee8f3b695e	221	#define LL_SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /!< SRAM2 Write protection page 25 /
EricLew	0:80ee8f3b695e	222	#define LL_SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /!< SRAM2 Write protection page 26 /
EricLew	0:80ee8f3b695e	223	#define LL_SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /!< SRAM2 Write protection page 27 /
EricLew	0:80ee8f3b695e	224	#define LL_SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /!< SRAM2 Write protection page 28 /
EricLew	0:80ee8f3b695e	225	#define LL_SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /!< SRAM2 Write protection page 29 /
EricLew	0:80ee8f3b695e	226	#define LL_SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /!< SRAM2 Write protection page 30 /
EricLew	0:80ee8f3b695e	227	#define LL_SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /!< SRAM2 Write protection page 31 /
EricLew	0:80ee8f3b695e	228	/**
EricLew	0:80ee8f3b695e	229	* @}
EricLew	0:80ee8f3b695e	230	*/
EricLew	0:80ee8f3b695e	231
EricLew	0:80ee8f3b695e	232	/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
EricLew	0:80ee8f3b695e	233	* @{
EricLew	0:80ee8f3b695e	234	*/
EricLew	0:80ee8f3b695e	235	#define LL_DBGMCU_TRACE_NONE (uint32_t)0x00000000 /!< TRACE pins not assigned (default state) /
EricLew	0:80ee8f3b695e	236	#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /!< TRACE pin assignment for Asynchronous Mode /
EricLew	0:80ee8f3b695e	237	#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_0) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 /
EricLew	0:80ee8f3b695e	238	#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE_1) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 /
EricLew	0:80ee8f3b695e	239	#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE) /!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 /
EricLew	0:80ee8f3b695e	240	/**
EricLew	0:80ee8f3b695e	241	* @}
EricLew	0:80ee8f3b695e	242	*/
EricLew	0:80ee8f3b695e	243
EricLew	0:80ee8f3b695e	244	/** @defgroup SYSTEM_LL_EC_ABP1_GRP1_STOP_IP DBGMCU ABP1 GRP1 STOP IP
EricLew	0:80ee8f3b695e	245	* @{
EricLew	0:80ee8f3b695e	246	*/
EricLew	0:80ee8f3b695e	247	#define LL_DBGMCU_ABP1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /!< The counter clock of TIM2 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	248	#define LL_DBGMCU_ABP1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /!< The counter clock of TIM3 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	249	#define LL_DBGMCU_ABP1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /!< The counter clock of TIM4 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	250	#define LL_DBGMCU_ABP1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /!< The counter clock of TIM5 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	251	#define LL_DBGMCU_ABP1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /!< The counter clock of TIM6 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	252	#define LL_DBGMCU_ABP1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /!< The counter clock of TIM7 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	253	#define LL_DBGMCU_ABP1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /!< The clock of the RTC counter is stopped when the core is halted/
EricLew	0:80ee8f3b695e	254	#define LL_DBGMCU_ABP1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /!< The window watchdog counter clock is stopped when the core is halted/
EricLew	0:80ee8f3b695e	255	#define LL_DBGMCU_ABP1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /!< The independent watchdog counter clock is stopped when the core is halted/
EricLew	0:80ee8f3b695e	256	#define LL_DBGMCU_ABP1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /!< The I2C1 SMBus timeout is frozen/
EricLew	0:80ee8f3b695e	257	#define LL_DBGMCU_ABP1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /!< The I2C2 SMBus timeout is frozen/
EricLew	0:80ee8f3b695e	258	#define LL_DBGMCU_ABP1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /!< The I2C3 SMBus timeout is frozen/
EricLew	0:80ee8f3b695e	259	#define LL_DBGMCU_ABP1_GRP1_CAN_STOP DBGMCU_APB1FZR1_DBG_CAN_STOP /!< The bxCAN receive registers are frozen/
EricLew	0:80ee8f3b695e	260	#define LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /!< The counter clock of LPTIM1 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	261	/**
EricLew	0:80ee8f3b695e	262	* @}
EricLew	0:80ee8f3b695e	263	*/
EricLew	0:80ee8f3b695e	264
EricLew	0:80ee8f3b695e	265	/** @defgroup SYSTEM_LL_EC_ABP1_GRP2_STOP_IP DBGMCU ABP1 GRP2 STOP IP
EricLew	0:80ee8f3b695e	266	* @{
EricLew	0:80ee8f3b695e	267	*/
EricLew	0:80ee8f3b695e	268	#define LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /!< The counter clock of LPTIM2 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	269	/**
EricLew	0:80ee8f3b695e	270	* @}
EricLew	0:80ee8f3b695e	271	*/
EricLew	0:80ee8f3b695e	272
EricLew	0:80ee8f3b695e	273	/** @defgroup SYSTEM_LL_EC_ABP2_GRP1_STOP_IP DBGMCU ABP2 GRP1 STOP IP
EricLew	0:80ee8f3b695e	274	* @{
EricLew	0:80ee8f3b695e	275	*/
EricLew	0:80ee8f3b695e	276	#define LL_DBGMCU_ABP2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /!< The counter clock of TIM1 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	277	#define LL_DBGMCU_ABP2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /!< The counter clock of TIM8 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	278	#define LL_DBGMCU_ABP2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /!< The counter clock of TIM15 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	279	#define LL_DBGMCU_ABP2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /!< The counter clock of TIM16 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	280	#define LL_DBGMCU_ABP2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /!< The counter clock of TIM17 is stopped when the core is halted/
EricLew	0:80ee8f3b695e	281	/**
EricLew	0:80ee8f3b695e	282	* @}
EricLew	0:80ee8f3b695e	283	*/
EricLew	0:80ee8f3b695e	284
EricLew	0:80ee8f3b695e	285	/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
EricLew	0:80ee8f3b695e	286	* @{
EricLew	0:80ee8f3b695e	287	*/
EricLew	0:80ee8f3b695e	288	#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /!< Voltage reference scale 0 (VREF_OUT1) /
EricLew	0:80ee8f3b695e	289	#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /!< Voltage reference scale 1 (VREF_OUT2) /
EricLew	0:80ee8f3b695e	290	/**
EricLew	0:80ee8f3b695e	291	* @}
EricLew	0:80ee8f3b695e	292	*/
EricLew	0:80ee8f3b695e	293
EricLew	0:80ee8f3b695e	294	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
EricLew	0:80ee8f3b695e	295	* @{
EricLew	0:80ee8f3b695e	296	*/
EricLew	0:80ee8f3b695e	297	#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /!< FLASH Zero wait state /
EricLew	0:80ee8f3b695e	298	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /!< FLASH One wait state /
EricLew	0:80ee8f3b695e	299	#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /!< FLASH Two wait states /
EricLew	0:80ee8f3b695e	300	#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /!< FLASH Three wait states /
EricLew	0:80ee8f3b695e	301	#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /!< FLASH Four wait states /
EricLew	0:80ee8f3b695e	302	/**
EricLew	0:80ee8f3b695e	303	* @}
EricLew	0:80ee8f3b695e	304	*/
EricLew	0:80ee8f3b695e	305
EricLew	0:80ee8f3b695e	306	/**
EricLew	0:80ee8f3b695e	307	* @}
EricLew	0:80ee8f3b695e	308	*/
EricLew	0:80ee8f3b695e	309
EricLew	0:80ee8f3b695e	310	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	311
EricLew	0:80ee8f3b695e	312	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	313	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
EricLew	0:80ee8f3b695e	314	* @{
EricLew	0:80ee8f3b695e	315	*/
EricLew	0:80ee8f3b695e	316
EricLew	0:80ee8f3b695e	317	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
EricLew	0:80ee8f3b695e	318	* @{
EricLew	0:80ee8f3b695e	319	*/
EricLew	0:80ee8f3b695e	320
EricLew	0:80ee8f3b695e	321	/**
EricLew	0:80ee8f3b695e	322	* @brief Set memory mapping at address 0x00000000
EricLew	0:80ee8f3b695e	323	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
EricLew	0:80ee8f3b695e	324	* @param Memory This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	325	* @arg @ref LL_SYSCFG_REMAP_FLASH
EricLew	0:80ee8f3b695e	326	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
EricLew	0:80ee8f3b695e	327	* @arg @ref LL_SYSCFG_REMAP_SRAM
EricLew	0:80ee8f3b695e	328	* @arg @ref LL_SYSCFG_REMAP_FMC
EricLew	0:80ee8f3b695e	329	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
EricLew	0:80ee8f3b695e	330	* @retval None
EricLew	0:80ee8f3b695e	331	*/
EricLew	0:80ee8f3b695e	332	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
EricLew	0:80ee8f3b695e	333	{
EricLew	0:80ee8f3b695e	334	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
EricLew	0:80ee8f3b695e	335	}
EricLew	0:80ee8f3b695e	336
EricLew	0:80ee8f3b695e	337	/**
EricLew	0:80ee8f3b695e	338	* @brief Get memory mapping at address 0x00000000
EricLew	0:80ee8f3b695e	339	* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
EricLew	0:80ee8f3b695e	340	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	341	* @arg @ref LL_SYSCFG_REMAP_FLASH
EricLew	0:80ee8f3b695e	342	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
EricLew	0:80ee8f3b695e	343	* @arg @ref LL_SYSCFG_REMAP_SRAM
EricLew	0:80ee8f3b695e	344	* @arg @ref LL_SYSCFG_REMAP_FMC
EricLew	0:80ee8f3b695e	345	* @arg @ref LL_SYSCFG_REMAP_QUADSPI
EricLew	0:80ee8f3b695e	346	*/
EricLew	0:80ee8f3b695e	347	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
EricLew	0:80ee8f3b695e	348	{
EricLew	0:80ee8f3b695e	349	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
EricLew	0:80ee8f3b695e	350	}
EricLew	0:80ee8f3b695e	351
EricLew	0:80ee8f3b695e	352	/**
EricLew	0:80ee8f3b695e	353	* @brief Select Flash bank mode (Bank flashed at 0x08000000)
EricLew	0:80ee8f3b695e	354	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
EricLew	0:80ee8f3b695e	355	* @param Bank This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	356	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
EricLew	0:80ee8f3b695e	357	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
EricLew	0:80ee8f3b695e	358	* @retval None
EricLew	0:80ee8f3b695e	359	*/
EricLew	0:80ee8f3b695e	360	__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
EricLew	0:80ee8f3b695e	361	{
EricLew	0:80ee8f3b695e	362	MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
EricLew	0:80ee8f3b695e	363	}
EricLew	0:80ee8f3b695e	364
EricLew	0:80ee8f3b695e	365	/**
EricLew	0:80ee8f3b695e	366	* @brief Get Flash bank mode (Bank flashed at 0x08000000)
EricLew	0:80ee8f3b695e	367	* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
EricLew	0:80ee8f3b695e	368	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	369	* @arg @ref LL_SYSCFG_BANKMODE_BANK1
EricLew	0:80ee8f3b695e	370	* @arg @ref LL_SYSCFG_BANKMODE_BANK2
EricLew	0:80ee8f3b695e	371	*/
EricLew	0:80ee8f3b695e	372	__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
EricLew	0:80ee8f3b695e	373	{
EricLew	0:80ee8f3b695e	374	return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
EricLew	0:80ee8f3b695e	375	}
EricLew	0:80ee8f3b695e	376
EricLew	0:80ee8f3b695e	377	/**
EricLew	0:80ee8f3b695e	378	* @brief Firewall protection enabled
EricLew	0:80ee8f3b695e	379	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_EnableFirewall
EricLew	0:80ee8f3b695e	380	* @retval None
EricLew	0:80ee8f3b695e	381	*/
EricLew	0:80ee8f3b695e	382	__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
EricLew	0:80ee8f3b695e	383	{
EricLew	0:80ee8f3b695e	384	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
EricLew	0:80ee8f3b695e	385	}
EricLew	0:80ee8f3b695e	386
EricLew	0:80ee8f3b695e	387	/**
EricLew	0:80ee8f3b695e	388	* @brief Check if Firewall protection is enabled or not
EricLew	0:80ee8f3b695e	389	* @rmtoll SYSCFG_CFGR1 FWDIS LL_SYSCFG_IsEnabledFirewall
EricLew	0:80ee8f3b695e	390	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	391	*/
EricLew	0:80ee8f3b695e	392	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
EricLew	0:80ee8f3b695e	393	{
EricLew	0:80ee8f3b695e	394	return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
EricLew	0:80ee8f3b695e	395	}
EricLew	0:80ee8f3b695e	396
EricLew	0:80ee8f3b695e	397	/**
EricLew	0:80ee8f3b695e	398	* @brief Enable I/O analog switch voltage booster (I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is
EricLew	0:80ee8f3b695e	399	* the recommended configuration when using the ADC in low VDDAvoltage operation)
EricLew	0:80ee8f3b695e	400	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
EricLew	0:80ee8f3b695e	401	* @retval None
EricLew	0:80ee8f3b695e	402	*/
EricLew	0:80ee8f3b695e	403	__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
EricLew	0:80ee8f3b695e	404	{
EricLew	0:80ee8f3b695e	405	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
EricLew	0:80ee8f3b695e	406	}
EricLew	0:80ee8f3b695e	407
EricLew	0:80ee8f3b695e	408	/**
EricLew	0:80ee8f3b695e	409	* @brief Disable I/O analog switch voltage booster (I/O analog switches are supplied by VDDAvoltage. This is the recommended configuration
EricLew	0:80ee8f3b695e	410	* when using the ADC in high VDDAvoltage operation)
EricLew	0:80ee8f3b695e	411	* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
EricLew	0:80ee8f3b695e	412	* @retval None
EricLew	0:80ee8f3b695e	413	*/
EricLew	0:80ee8f3b695e	414	__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
EricLew	0:80ee8f3b695e	415	{
EricLew	0:80ee8f3b695e	416	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
EricLew	0:80ee8f3b695e	417	}
EricLew	0:80ee8f3b695e	418
EricLew	0:80ee8f3b695e	419	/**
EricLew	0:80ee8f3b695e	420	* @brief Enable the I2C fast mode plus driving capability.
EricLew	0:80ee8f3b695e	421	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
EricLew	0:80ee8f3b695e	422	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
EricLew	0:80ee8f3b695e	423	* @param ConfigFastModePlus This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	424	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
EricLew	0:80ee8f3b695e	425	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
EricLew	0:80ee8f3b695e	426	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
EricLew	0:80ee8f3b695e	427	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
EricLew	0:80ee8f3b695e	428	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
EricLew	0:80ee8f3b695e	429	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
EricLew	0:80ee8f3b695e	430	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
EricLew	0:80ee8f3b695e	431	* @retval None
EricLew	0:80ee8f3b695e	432	*/
EricLew	0:80ee8f3b695e	433	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
EricLew	0:80ee8f3b695e	434	{
EricLew	0:80ee8f3b695e	435	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
EricLew	0:80ee8f3b695e	436	}
EricLew	0:80ee8f3b695e	437
EricLew	0:80ee8f3b695e	438	/**
EricLew	0:80ee8f3b695e	439	* @brief Disable the I2C fast mode plus driving capability.
EricLew	0:80ee8f3b695e	440	* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
EricLew	0:80ee8f3b695e	441	* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
EricLew	0:80ee8f3b695e	442	* @param ConfigFastModePlus This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	443	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
EricLew	0:80ee8f3b695e	444	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
EricLew	0:80ee8f3b695e	445	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
EricLew	0:80ee8f3b695e	446	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
EricLew	0:80ee8f3b695e	447	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
EricLew	0:80ee8f3b695e	448	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2
EricLew	0:80ee8f3b695e	449	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
EricLew	0:80ee8f3b695e	450	* @retval None
EricLew	0:80ee8f3b695e	451	*/
EricLew	0:80ee8f3b695e	452	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
EricLew	0:80ee8f3b695e	453	{
EricLew	0:80ee8f3b695e	454	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
EricLew	0:80ee8f3b695e	455	}
EricLew	0:80ee8f3b695e	456
EricLew	0:80ee8f3b695e	457	/**
EricLew	0:80ee8f3b695e	458	* @brief Enable Floating Point Unit Invalid operation Interrupt
EricLew	0:80ee8f3b695e	459	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
EricLew	0:80ee8f3b695e	460	* @retval None
EricLew	0:80ee8f3b695e	461	*/
EricLew	0:80ee8f3b695e	462	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
EricLew	0:80ee8f3b695e	463	{
EricLew	0:80ee8f3b695e	464	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
EricLew	0:80ee8f3b695e	465	}
EricLew	0:80ee8f3b695e	466
EricLew	0:80ee8f3b695e	467	/**
EricLew	0:80ee8f3b695e	468	* @brief Enable Floating Point Unit Divide-by-zero Interrupt
EricLew	0:80ee8f3b695e	469	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
EricLew	0:80ee8f3b695e	470	* @retval None
EricLew	0:80ee8f3b695e	471	*/
EricLew	0:80ee8f3b695e	472	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
EricLew	0:80ee8f3b695e	473	{
EricLew	0:80ee8f3b695e	474	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
EricLew	0:80ee8f3b695e	475	}
EricLew	0:80ee8f3b695e	476
EricLew	0:80ee8f3b695e	477	/**
EricLew	0:80ee8f3b695e	478	* @brief Enable Floating Point Unit Underflow Interrupt
EricLew	0:80ee8f3b695e	479	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
EricLew	0:80ee8f3b695e	480	* @retval None
EricLew	0:80ee8f3b695e	481	*/
EricLew	0:80ee8f3b695e	482	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
EricLew	0:80ee8f3b695e	483	{
EricLew	0:80ee8f3b695e	484	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
EricLew	0:80ee8f3b695e	485	}
EricLew	0:80ee8f3b695e	486
EricLew	0:80ee8f3b695e	487	/**
EricLew	0:80ee8f3b695e	488	* @brief Enable Floating Point Unit Overflow Interrupt
EricLew	0:80ee8f3b695e	489	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
EricLew	0:80ee8f3b695e	490	* @retval None
EricLew	0:80ee8f3b695e	491	*/
EricLew	0:80ee8f3b695e	492	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
EricLew	0:80ee8f3b695e	493	{
EricLew	0:80ee8f3b695e	494	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
EricLew	0:80ee8f3b695e	495	}
EricLew	0:80ee8f3b695e	496
EricLew	0:80ee8f3b695e	497	/**
EricLew	0:80ee8f3b695e	498	* @brief Enable Floating Point Unit Input denormal Interrupt
EricLew	0:80ee8f3b695e	499	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
EricLew	0:80ee8f3b695e	500	* @retval None
EricLew	0:80ee8f3b695e	501	*/
EricLew	0:80ee8f3b695e	502	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
EricLew	0:80ee8f3b695e	503	{
EricLew	0:80ee8f3b695e	504	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
EricLew	0:80ee8f3b695e	505	}
EricLew	0:80ee8f3b695e	506
EricLew	0:80ee8f3b695e	507	/**
EricLew	0:80ee8f3b695e	508	* @brief Enable Floating Point Unit Inexact Interrupt
EricLew	0:80ee8f3b695e	509	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
EricLew	0:80ee8f3b695e	510	* @retval None
EricLew	0:80ee8f3b695e	511	*/
EricLew	0:80ee8f3b695e	512	__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
EricLew	0:80ee8f3b695e	513	{
EricLew	0:80ee8f3b695e	514	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
EricLew	0:80ee8f3b695e	515	}
EricLew	0:80ee8f3b695e	516
EricLew	0:80ee8f3b695e	517	/**
EricLew	0:80ee8f3b695e	518	* @brief Disable Floating Point Unit Invalid operation Interrupt
EricLew	0:80ee8f3b695e	519	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
EricLew	0:80ee8f3b695e	520	* @retval None
EricLew	0:80ee8f3b695e	521	*/
EricLew	0:80ee8f3b695e	522	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
EricLew	0:80ee8f3b695e	523	{
EricLew	0:80ee8f3b695e	524	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
EricLew	0:80ee8f3b695e	525	}
EricLew	0:80ee8f3b695e	526
EricLew	0:80ee8f3b695e	527	/**
EricLew	0:80ee8f3b695e	528	* @brief Disable Floating Point Unit Divide-by-zero Interrupt
EricLew	0:80ee8f3b695e	529	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
EricLew	0:80ee8f3b695e	530	* @retval None
EricLew	0:80ee8f3b695e	531	*/
EricLew	0:80ee8f3b695e	532	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
EricLew	0:80ee8f3b695e	533	{
EricLew	0:80ee8f3b695e	534	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
EricLew	0:80ee8f3b695e	535	}
EricLew	0:80ee8f3b695e	536
EricLew	0:80ee8f3b695e	537	/**
EricLew	0:80ee8f3b695e	538	* @brief Disable Floating Point Unit Underflow Interrupt
EricLew	0:80ee8f3b695e	539	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
EricLew	0:80ee8f3b695e	540	* @retval None
EricLew	0:80ee8f3b695e	541	*/
EricLew	0:80ee8f3b695e	542	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
EricLew	0:80ee8f3b695e	543	{
EricLew	0:80ee8f3b695e	544	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
EricLew	0:80ee8f3b695e	545	}
EricLew	0:80ee8f3b695e	546
EricLew	0:80ee8f3b695e	547	/**
EricLew	0:80ee8f3b695e	548	* @brief Disable Floating Point Unit Overflow Interrupt
EricLew	0:80ee8f3b695e	549	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
EricLew	0:80ee8f3b695e	550	* @retval None
EricLew	0:80ee8f3b695e	551	*/
EricLew	0:80ee8f3b695e	552	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
EricLew	0:80ee8f3b695e	553	{
EricLew	0:80ee8f3b695e	554	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
EricLew	0:80ee8f3b695e	555	}
EricLew	0:80ee8f3b695e	556
EricLew	0:80ee8f3b695e	557	/**
EricLew	0:80ee8f3b695e	558	* @brief Disable Floating Point Unit Input denormal Interrupt
EricLew	0:80ee8f3b695e	559	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
EricLew	0:80ee8f3b695e	560	* @retval None
EricLew	0:80ee8f3b695e	561	*/
EricLew	0:80ee8f3b695e	562	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
EricLew	0:80ee8f3b695e	563	{
EricLew	0:80ee8f3b695e	564	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
EricLew	0:80ee8f3b695e	565	}
EricLew	0:80ee8f3b695e	566
EricLew	0:80ee8f3b695e	567	/**
EricLew	0:80ee8f3b695e	568	* @brief Disable Floating Point Unit Inexact Interrupt
EricLew	0:80ee8f3b695e	569	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
EricLew	0:80ee8f3b695e	570	* @retval None
EricLew	0:80ee8f3b695e	571	*/
EricLew	0:80ee8f3b695e	572	__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
EricLew	0:80ee8f3b695e	573	{
EricLew	0:80ee8f3b695e	574	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
EricLew	0:80ee8f3b695e	575	}
EricLew	0:80ee8f3b695e	576
EricLew	0:80ee8f3b695e	577	/**
EricLew	0:80ee8f3b695e	578	* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	579	* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
EricLew	0:80ee8f3b695e	580	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	581	*/
EricLew	0:80ee8f3b695e	582	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
EricLew	0:80ee8f3b695e	583	{
EricLew	0:80ee8f3b695e	584	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
EricLew	0:80ee8f3b695e	585	}
EricLew	0:80ee8f3b695e	586
EricLew	0:80ee8f3b695e	587	/**
EricLew	0:80ee8f3b695e	588	* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	589	* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
EricLew	0:80ee8f3b695e	590	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	591	*/
EricLew	0:80ee8f3b695e	592	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
EricLew	0:80ee8f3b695e	593	{
EricLew	0:80ee8f3b695e	594	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
EricLew	0:80ee8f3b695e	595	}
EricLew	0:80ee8f3b695e	596
EricLew	0:80ee8f3b695e	597	/**
EricLew	0:80ee8f3b695e	598	* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	599	* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
EricLew	0:80ee8f3b695e	600	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	601	*/
EricLew	0:80ee8f3b695e	602	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
EricLew	0:80ee8f3b695e	603	{
EricLew	0:80ee8f3b695e	604	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
EricLew	0:80ee8f3b695e	605	}
EricLew	0:80ee8f3b695e	606
EricLew	0:80ee8f3b695e	607	/**
EricLew	0:80ee8f3b695e	608	* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	609	* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
EricLew	0:80ee8f3b695e	610	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	611	*/
EricLew	0:80ee8f3b695e	612	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
EricLew	0:80ee8f3b695e	613	{
EricLew	0:80ee8f3b695e	614	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
EricLew	0:80ee8f3b695e	615	}
EricLew	0:80ee8f3b695e	616
EricLew	0:80ee8f3b695e	617	/**
EricLew	0:80ee8f3b695e	618	* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	619	* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
EricLew	0:80ee8f3b695e	620	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	621	*/
EricLew	0:80ee8f3b695e	622	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
EricLew	0:80ee8f3b695e	623	{
EricLew	0:80ee8f3b695e	624	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
EricLew	0:80ee8f3b695e	625	}
EricLew	0:80ee8f3b695e	626
EricLew	0:80ee8f3b695e	627	/**
EricLew	0:80ee8f3b695e	628	* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
EricLew	0:80ee8f3b695e	629	* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
EricLew	0:80ee8f3b695e	630	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	631	*/
EricLew	0:80ee8f3b695e	632	__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
EricLew	0:80ee8f3b695e	633	{
EricLew	0:80ee8f3b695e	634	return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
EricLew	0:80ee8f3b695e	635	}
EricLew	0:80ee8f3b695e	636
EricLew	0:80ee8f3b695e	637	/**
EricLew	0:80ee8f3b695e	638	* @brief Configure source input for the EXTI external interrupt.
EricLew	0:80ee8f3b695e	639	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
EricLew	0:80ee8f3b695e	640	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
EricLew	0:80ee8f3b695e	641	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
EricLew	0:80ee8f3b695e	642	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
EricLew	0:80ee8f3b695e	643	* @param Port This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	644	* @arg @ref LL_SYSCFG_EXTI_PORTA
EricLew	0:80ee8f3b695e	645	* @arg @ref LL_SYSCFG_EXTI_PORTB
EricLew	0:80ee8f3b695e	646	* @arg @ref LL_SYSCFG_EXTI_PORTC
EricLew	0:80ee8f3b695e	647	* @arg @ref LL_SYSCFG_EXTI_PORTD
EricLew	0:80ee8f3b695e	648	* @arg @ref LL_SYSCFG_EXTI_PORTE
EricLew	0:80ee8f3b695e	649	* @arg @ref LL_SYSCFG_EXTI_PORTF
EricLew	0:80ee8f3b695e	650	* @arg @ref LL_SYSCFG_EXTI_PORTG
EricLew	0:80ee8f3b695e	651	* @arg @ref LL_SYSCFG_EXTI_PORTH
EricLew	0:80ee8f3b695e	652	* @param Line This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	653	* @arg @ref LL_SYSCFG_EXTI_LINE0
EricLew	0:80ee8f3b695e	654	* @arg @ref LL_SYSCFG_EXTI_LINE1
EricLew	0:80ee8f3b695e	655	* @arg @ref LL_SYSCFG_EXTI_LINE2
EricLew	0:80ee8f3b695e	656	* @arg @ref LL_SYSCFG_EXTI_LINE3
EricLew	0:80ee8f3b695e	657	* @arg @ref LL_SYSCFG_EXTI_LINE4
EricLew	0:80ee8f3b695e	658	* @arg @ref LL_SYSCFG_EXTI_LINE5
EricLew	0:80ee8f3b695e	659	* @arg @ref LL_SYSCFG_EXTI_LINE6
EricLew	0:80ee8f3b695e	660	* @arg @ref LL_SYSCFG_EXTI_LINE7
EricLew	0:80ee8f3b695e	661	* @arg @ref LL_SYSCFG_EXTI_LINE8
EricLew	0:80ee8f3b695e	662	* @arg @ref LL_SYSCFG_EXTI_LINE9
EricLew	0:80ee8f3b695e	663	* @arg @ref LL_SYSCFG_EXTI_LINE10
EricLew	0:80ee8f3b695e	664	* @arg @ref LL_SYSCFG_EXTI_LINE11
EricLew	0:80ee8f3b695e	665	* @arg @ref LL_SYSCFG_EXTI_LINE12
EricLew	0:80ee8f3b695e	666	* @arg @ref LL_SYSCFG_EXTI_LINE13
EricLew	0:80ee8f3b695e	667	* @arg @ref LL_SYSCFG_EXTI_LINE14
EricLew	0:80ee8f3b695e	668	* @arg @ref LL_SYSCFG_EXTI_LINE15
EricLew	0:80ee8f3b695e	669	* @retval None
EricLew	0:80ee8f3b695e	670	*/
EricLew	0:80ee8f3b695e	671	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
EricLew	0:80ee8f3b695e	672	{
EricLew	0:80ee8f3b695e	673	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
EricLew	0:80ee8f3b695e	674	}
EricLew	0:80ee8f3b695e	675
EricLew	0:80ee8f3b695e	676	/**
EricLew	0:80ee8f3b695e	677	* @brief Get the configured defined for specific EXTI Line
EricLew	0:80ee8f3b695e	678	* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
EricLew	0:80ee8f3b695e	679	* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
EricLew	0:80ee8f3b695e	680	* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
EricLew	0:80ee8f3b695e	681	* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
EricLew	0:80ee8f3b695e	682	* @param Line This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	683	* @arg @ref LL_SYSCFG_EXTI_LINE0
EricLew	0:80ee8f3b695e	684	* @arg @ref LL_SYSCFG_EXTI_LINE1
EricLew	0:80ee8f3b695e	685	* @arg @ref LL_SYSCFG_EXTI_LINE2
EricLew	0:80ee8f3b695e	686	* @arg @ref LL_SYSCFG_EXTI_LINE3
EricLew	0:80ee8f3b695e	687	* @arg @ref LL_SYSCFG_EXTI_LINE4
EricLew	0:80ee8f3b695e	688	* @arg @ref LL_SYSCFG_EXTI_LINE5
EricLew	0:80ee8f3b695e	689	* @arg @ref LL_SYSCFG_EXTI_LINE6
EricLew	0:80ee8f3b695e	690	* @arg @ref LL_SYSCFG_EXTI_LINE7
EricLew	0:80ee8f3b695e	691	* @arg @ref LL_SYSCFG_EXTI_LINE8
EricLew	0:80ee8f3b695e	692	* @arg @ref LL_SYSCFG_EXTI_LINE9
EricLew	0:80ee8f3b695e	693	* @arg @ref LL_SYSCFG_EXTI_LINE10
EricLew	0:80ee8f3b695e	694	* @arg @ref LL_SYSCFG_EXTI_LINE11
EricLew	0:80ee8f3b695e	695	* @arg @ref LL_SYSCFG_EXTI_LINE12
EricLew	0:80ee8f3b695e	696	* @arg @ref LL_SYSCFG_EXTI_LINE13
EricLew	0:80ee8f3b695e	697	* @arg @ref LL_SYSCFG_EXTI_LINE14
EricLew	0:80ee8f3b695e	698	* @arg @ref LL_SYSCFG_EXTI_LINE15
EricLew	0:80ee8f3b695e	699	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	700	* @arg @ref LL_SYSCFG_EXTI_PORTA
EricLew	0:80ee8f3b695e	701	* @arg @ref LL_SYSCFG_EXTI_PORTB
EricLew	0:80ee8f3b695e	702	* @arg @ref LL_SYSCFG_EXTI_PORTC
EricLew	0:80ee8f3b695e	703	* @arg @ref LL_SYSCFG_EXTI_PORTD
EricLew	0:80ee8f3b695e	704	* @arg @ref LL_SYSCFG_EXTI_PORTE
EricLew	0:80ee8f3b695e	705	* @arg @ref LL_SYSCFG_EXTI_PORTF
EricLew	0:80ee8f3b695e	706	* @arg @ref LL_SYSCFG_EXTI_PORTG
EricLew	0:80ee8f3b695e	707	* @arg @ref LL_SYSCFG_EXTI_PORTH
EricLew	0:80ee8f3b695e	708	*/
EricLew	0:80ee8f3b695e	709	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
EricLew	0:80ee8f3b695e	710	{
EricLew	0:80ee8f3b695e	711	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
EricLew	0:80ee8f3b695e	712	}
EricLew	0:80ee8f3b695e	713
EricLew	0:80ee8f3b695e	714	/**
EricLew	0:80ee8f3b695e	715	* @brief Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
EricLew	0:80ee8f3b695e	716	* automatically cleared at the end of the SRAM2 erase operation.)
EricLew	0:80ee8f3b695e	717	* @note This bit is write-protected: setting this bit is possible only after the
EricLew	0:80ee8f3b695e	718	* correct key sequence is written in the SYSCFG_SKR register.
EricLew	0:80ee8f3b695e	719	* @rmtoll SYSCFG_SCSR SRAM2ER LL_SYSCFG_EnableSRAM2Erase
EricLew	0:80ee8f3b695e	720	* @retval None
EricLew	0:80ee8f3b695e	721	*/
EricLew	0:80ee8f3b695e	722	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
EricLew	0:80ee8f3b695e	723	{
EricLew	0:80ee8f3b695e	724	/* unlock the write protection of the SRAM2ER bit */
EricLew	0:80ee8f3b695e	725	WRITE_REG(SYSCFG->SKR, 0xCA);
EricLew	0:80ee8f3b695e	726	WRITE_REG(SYSCFG->SKR, 0x53);
EricLew	0:80ee8f3b695e	727
EricLew	0:80ee8f3b695e	728	/* Starts a hardware SRAM2 erase operation*/
EricLew	0:80ee8f3b695e	729	SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
EricLew	0:80ee8f3b695e	730	}
EricLew	0:80ee8f3b695e	731
EricLew	0:80ee8f3b695e	732	/**
EricLew	0:80ee8f3b695e	733	* @brief Check if SRAM2 erase operation is on going
EricLew	0:80ee8f3b695e	734	* @rmtoll SYSCFG_SCSR SRAM2BSY LL_SYSCFG_IsSRAM2EraseOngoing
EricLew	0:80ee8f3b695e	735	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	736	*/
EricLew	0:80ee8f3b695e	737	__STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
EricLew	0:80ee8f3b695e	738	{
EricLew	0:80ee8f3b695e	739	return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
EricLew	0:80ee8f3b695e	740	}
EricLew	0:80ee8f3b695e	741
EricLew	0:80ee8f3b695e	742	/**
EricLew	0:80ee8f3b695e	743	* @brief Set connections to TIM1/8/15/16/17 Break inputs
EricLew	0:80ee8f3b695e	744	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	745	* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	746	* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	747	* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
EricLew	0:80ee8f3b695e	748	* @param Break This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	749	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
EricLew	0:80ee8f3b695e	750	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
EricLew	0:80ee8f3b695e	751	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
EricLew	0:80ee8f3b695e	752	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
EricLew	0:80ee8f3b695e	753	* @retval None
EricLew	0:80ee8f3b695e	754	*/
EricLew	0:80ee8f3b695e	755	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
EricLew	0:80ee8f3b695e	756	{
EricLew	0:80ee8f3b695e	757	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL, Break);
EricLew	0:80ee8f3b695e	758	}
EricLew	0:80ee8f3b695e	759
EricLew	0:80ee8f3b695e	760	/**
EricLew	0:80ee8f3b695e	761	* @brief Get connections to TIM1/8/15/16/17 Break inputs
EricLew	0:80ee8f3b695e	762	* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	763	* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	764	* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
EricLew	0:80ee8f3b695e	765	* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
EricLew	0:80ee8f3b695e	766	* @retval Returned value can be can be a combination of the following values:
EricLew	0:80ee8f3b695e	767	* @arg @ref LL_SYSCFG_TIMBREAK_ECC
EricLew	0:80ee8f3b695e	768	* @arg @ref LL_SYSCFG_TIMBREAK_PVD
EricLew	0:80ee8f3b695e	769	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
EricLew	0:80ee8f3b695e	770	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
EricLew	0:80ee8f3b695e	771	*/
EricLew	0:80ee8f3b695e	772	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
EricLew	0:80ee8f3b695e	773	{
EricLew	0:80ee8f3b695e	774	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL \| SYSCFG_CFGR2_SPL \| SYSCFG_CFGR2_PVDL \| SYSCFG_CFGR2_ECCL));
EricLew	0:80ee8f3b695e	775	}
EricLew	0:80ee8f3b695e	776
EricLew	0:80ee8f3b695e	777	/**
EricLew	0:80ee8f3b695e	778	* @brief Check if SRAM2 parity error detected
EricLew	0:80ee8f3b695e	779	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
EricLew	0:80ee8f3b695e	780	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	781	*/
EricLew	0:80ee8f3b695e	782	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
EricLew	0:80ee8f3b695e	783	{
EricLew	0:80ee8f3b695e	784	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
EricLew	0:80ee8f3b695e	785	}
EricLew	0:80ee8f3b695e	786
EricLew	0:80ee8f3b695e	787	/**
EricLew	0:80ee8f3b695e	788	* @brief Clear SRAM2 parity error flag
EricLew	0:80ee8f3b695e	789	* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
EricLew	0:80ee8f3b695e	790	* @retval None
EricLew	0:80ee8f3b695e	791	*/
EricLew	0:80ee8f3b695e	792	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
EricLew	0:80ee8f3b695e	793	{
EricLew	0:80ee8f3b695e	794	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
EricLew	0:80ee8f3b695e	795	}
EricLew	0:80ee8f3b695e	796
EricLew	0:80ee8f3b695e	797	/**
EricLew	0:80ee8f3b695e	798	* @brief Enable SRAM2 page write protection
EricLew	0:80ee8f3b695e	799	* @note Write protection is cleared only by a system reset
EricLew	0:80ee8f3b695e	800	* @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableSRAM2PageWRP
EricLew	0:80ee8f3b695e	801	* @param SRAM2WRP This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	802	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
EricLew	0:80ee8f3b695e	803	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
EricLew	0:80ee8f3b695e	804	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
EricLew	0:80ee8f3b695e	805	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
EricLew	0:80ee8f3b695e	806	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
EricLew	0:80ee8f3b695e	807	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
EricLew	0:80ee8f3b695e	808	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
EricLew	0:80ee8f3b695e	809	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
EricLew	0:80ee8f3b695e	810	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
EricLew	0:80ee8f3b695e	811	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
EricLew	0:80ee8f3b695e	812	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
EricLew	0:80ee8f3b695e	813	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
EricLew	0:80ee8f3b695e	814	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
EricLew	0:80ee8f3b695e	815	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
EricLew	0:80ee8f3b695e	816	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
EricLew	0:80ee8f3b695e	817	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
EricLew	0:80ee8f3b695e	818	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16
EricLew	0:80ee8f3b695e	819	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17
EricLew	0:80ee8f3b695e	820	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18
EricLew	0:80ee8f3b695e	821	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19
EricLew	0:80ee8f3b695e	822	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20
EricLew	0:80ee8f3b695e	823	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21
EricLew	0:80ee8f3b695e	824	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22
EricLew	0:80ee8f3b695e	825	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23
EricLew	0:80ee8f3b695e	826	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24
EricLew	0:80ee8f3b695e	827	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25
EricLew	0:80ee8f3b695e	828	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26
EricLew	0:80ee8f3b695e	829	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27
EricLew	0:80ee8f3b695e	830	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28
EricLew	0:80ee8f3b695e	831	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29
EricLew	0:80ee8f3b695e	832	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30
EricLew	0:80ee8f3b695e	833	* @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31
EricLew	0:80ee8f3b695e	834	* @retval None
EricLew	0:80ee8f3b695e	835	*/
EricLew	0:80ee8f3b695e	836	__STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP(uint32_t SRAM2WRP)
EricLew	0:80ee8f3b695e	837	{
EricLew	0:80ee8f3b695e	838	SET_BIT(SYSCFG->SWPR, SRAM2WRP);
EricLew	0:80ee8f3b695e	839	}
EricLew	0:80ee8f3b695e	840
EricLew	0:80ee8f3b695e	841	/**
EricLew	0:80ee8f3b695e	842	* @brief SRAM2 page write protection lock prior to erase
EricLew	0:80ee8f3b695e	843	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockSRAM2WRP
EricLew	0:80ee8f3b695e	844	* @retval None
EricLew	0:80ee8f3b695e	845	*/
EricLew	0:80ee8f3b695e	846	__STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
EricLew	0:80ee8f3b695e	847	{
EricLew	0:80ee8f3b695e	848	/* Writing a wrong key reactivates the write protection */
EricLew	0:80ee8f3b695e	849	WRITE_REG(SYSCFG->SKR, 0x00);
EricLew	0:80ee8f3b695e	850	}
EricLew	0:80ee8f3b695e	851
EricLew	0:80ee8f3b695e	852	/**
EricLew	0:80ee8f3b695e	853	* @brief SRAM2 page write protection unlock prior to erase
EricLew	0:80ee8f3b695e	854	* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockSRAM2WRP
EricLew	0:80ee8f3b695e	855	* @retval None
EricLew	0:80ee8f3b695e	856	*/
EricLew	0:80ee8f3b695e	857	__STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
EricLew	0:80ee8f3b695e	858	{
EricLew	0:80ee8f3b695e	859	/* unlock the write protection of the SRAM2ER bit */
EricLew	0:80ee8f3b695e	860	WRITE_REG(SYSCFG->SKR, 0xCA);
EricLew	0:80ee8f3b695e	861	WRITE_REG(SYSCFG->SKR, 0x53);
EricLew	0:80ee8f3b695e	862	}
EricLew	0:80ee8f3b695e	863
EricLew	0:80ee8f3b695e	864	/**
EricLew	0:80ee8f3b695e	865	* @}
EricLew	0:80ee8f3b695e	866	*/
EricLew	0:80ee8f3b695e	867
EricLew	0:80ee8f3b695e	868
EricLew	0:80ee8f3b695e	869	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
EricLew	0:80ee8f3b695e	870	* @{
EricLew	0:80ee8f3b695e	871	*/
EricLew	0:80ee8f3b695e	872
EricLew	0:80ee8f3b695e	873	/**
EricLew	0:80ee8f3b695e	874	* @brief Returns the device identifier
EricLew	0:80ee8f3b695e	875	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
EricLew	0:80ee8f3b695e	876	* @retval Values between 0x00 and 0xFFFF (ex: device ID is 0x6415)
EricLew	0:80ee8f3b695e	877	*/
EricLew	0:80ee8f3b695e	878	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
EricLew	0:80ee8f3b695e	879	{
EricLew	0:80ee8f3b695e	880	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
EricLew	0:80ee8f3b695e	881	}
EricLew	0:80ee8f3b695e	882
EricLew	0:80ee8f3b695e	883	/**
EricLew	0:80ee8f3b695e	884	* @brief Returns the device revision identifier
EricLew	0:80ee8f3b695e	885	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
EricLew	0:80ee8f3b695e	886	* @retval Values between 0x00 and 0xFFFF (ex: This field indicates the revision of the device.
EricLew	0:80ee8f3b695e	887	*/
EricLew	0:80ee8f3b695e	888	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
EricLew	0:80ee8f3b695e	889	{
EricLew	0:80ee8f3b695e	890	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
EricLew	0:80ee8f3b695e	891	}
EricLew	0:80ee8f3b695e	892
EricLew	0:80ee8f3b695e	893	/**
EricLew	0:80ee8f3b695e	894	* @brief Enable the Debug Module during SLEEP mode
EricLew	0:80ee8f3b695e	895	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
EricLew	0:80ee8f3b695e	896	* @retval None
EricLew	0:80ee8f3b695e	897	*/
EricLew	0:80ee8f3b695e	898	__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
EricLew	0:80ee8f3b695e	899	{
EricLew	0:80ee8f3b695e	900	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
EricLew	0:80ee8f3b695e	901	}
EricLew	0:80ee8f3b695e	902
EricLew	0:80ee8f3b695e	903	/**
EricLew	0:80ee8f3b695e	904	* @brief Disable the Debug Module during SLEEP mode
EricLew	0:80ee8f3b695e	905	* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
EricLew	0:80ee8f3b695e	906	* @retval None
EricLew	0:80ee8f3b695e	907	*/
EricLew	0:80ee8f3b695e	908	__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
EricLew	0:80ee8f3b695e	909	{
EricLew	0:80ee8f3b695e	910	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
EricLew	0:80ee8f3b695e	911	}
EricLew	0:80ee8f3b695e	912
EricLew	0:80ee8f3b695e	913	/**
EricLew	0:80ee8f3b695e	914	* @brief Enable the Debug Module during STOP mode
EricLew	0:80ee8f3b695e	915	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
EricLew	0:80ee8f3b695e	916	* @retval None
EricLew	0:80ee8f3b695e	917	*/
EricLew	0:80ee8f3b695e	918	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
EricLew	0:80ee8f3b695e	919	{
EricLew	0:80ee8f3b695e	920	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
EricLew	0:80ee8f3b695e	921	}
EricLew	0:80ee8f3b695e	922
EricLew	0:80ee8f3b695e	923	/**
EricLew	0:80ee8f3b695e	924	* @brief Disable the Debug Module during STOP mode
EricLew	0:80ee8f3b695e	925	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
EricLew	0:80ee8f3b695e	926	* @retval None
EricLew	0:80ee8f3b695e	927	*/
EricLew	0:80ee8f3b695e	928	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
EricLew	0:80ee8f3b695e	929	{
EricLew	0:80ee8f3b695e	930	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
EricLew	0:80ee8f3b695e	931	}
EricLew	0:80ee8f3b695e	932
EricLew	0:80ee8f3b695e	933	/**
EricLew	0:80ee8f3b695e	934	* @brief Enable the Debug Module during STANDBY mode
EricLew	0:80ee8f3b695e	935	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
EricLew	0:80ee8f3b695e	936	* @retval None
EricLew	0:80ee8f3b695e	937	*/
EricLew	0:80ee8f3b695e	938	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
EricLew	0:80ee8f3b695e	939	{
EricLew	0:80ee8f3b695e	940	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
EricLew	0:80ee8f3b695e	941	}
EricLew	0:80ee8f3b695e	942
EricLew	0:80ee8f3b695e	943	/**
EricLew	0:80ee8f3b695e	944	* @brief Disable the Debug Module during STANDBY mode
EricLew	0:80ee8f3b695e	945	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
EricLew	0:80ee8f3b695e	946	* @retval None
EricLew	0:80ee8f3b695e	947	*/
EricLew	0:80ee8f3b695e	948	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
EricLew	0:80ee8f3b695e	949	{
EricLew	0:80ee8f3b695e	950	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
EricLew	0:80ee8f3b695e	951	}
EricLew	0:80ee8f3b695e	952
EricLew	0:80ee8f3b695e	953	/**
EricLew	0:80ee8f3b695e	954	* @brief Set Trace pin assignment control
EricLew	0:80ee8f3b695e	955	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
EricLew	0:80ee8f3b695e	956	* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
EricLew	0:80ee8f3b695e	957	* @param PinAssignment This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	958	* @arg @ref LL_DBGMCU_TRACE_NONE
EricLew	0:80ee8f3b695e	959	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
EricLew	0:80ee8f3b695e	960	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
EricLew	0:80ee8f3b695e	961	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
EricLew	0:80ee8f3b695e	962	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
EricLew	0:80ee8f3b695e	963	* @retval None
EricLew	0:80ee8f3b695e	964	*/
EricLew	0:80ee8f3b695e	965	__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
EricLew	0:80ee8f3b695e	966	{
EricLew	0:80ee8f3b695e	967	MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE, PinAssignment);
EricLew	0:80ee8f3b695e	968	}
EricLew	0:80ee8f3b695e	969
EricLew	0:80ee8f3b695e	970	/**
EricLew	0:80ee8f3b695e	971	* @brief Get Trace pin assignment control
EricLew	0:80ee8f3b695e	972	* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
EricLew	0:80ee8f3b695e	973	* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
EricLew	0:80ee8f3b695e	974	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	975	* @arg @ref LL_DBGMCU_TRACE_NONE
EricLew	0:80ee8f3b695e	976	* @arg @ref LL_DBGMCU_TRACE_ASYNCH
EricLew	0:80ee8f3b695e	977	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
EricLew	0:80ee8f3b695e	978	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
EricLew	0:80ee8f3b695e	979	* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
EricLew	0:80ee8f3b695e	980	*/
EricLew	0:80ee8f3b695e	981	__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
EricLew	0:80ee8f3b695e	982	{
EricLew	0:80ee8f3b695e	983	return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN \| DBGMCU_CR_TRACE_MODE));
EricLew	0:80ee8f3b695e	984	}
EricLew	0:80ee8f3b695e	985
EricLew	0:80ee8f3b695e	986	/**
EricLew	0:80ee8f3b695e	987	* @brief Freeze APB1 peripherals (group1 peripherals)
EricLew	0:80ee8f3b695e	988	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP1_FreezePeriph
EricLew	0:80ee8f3b695e	989	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	990	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP
EricLew	0:80ee8f3b695e	991	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP
EricLew	0:80ee8f3b695e	992	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM4_STOP
EricLew	0:80ee8f3b695e	993	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM5_STOP
EricLew	0:80ee8f3b695e	994	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP
EricLew	0:80ee8f3b695e	995	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP
EricLew	0:80ee8f3b695e	996	* @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP
EricLew	0:80ee8f3b695e	997	* @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP
EricLew	0:80ee8f3b695e	998	* @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP
EricLew	0:80ee8f3b695e	999	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP
EricLew	0:80ee8f3b695e	1000	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP
EricLew	0:80ee8f3b695e	1001	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP
EricLew	0:80ee8f3b695e	1002	* @arg @ref LL_DBGMCU_ABP1_GRP1_CAN_STOP
EricLew	0:80ee8f3b695e	1003	* @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP
EricLew	0:80ee8f3b695e	1004	* @retval None
EricLew	0:80ee8f3b695e	1005	*/
EricLew	0:80ee8f3b695e	1006	__STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_FreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1007	{
EricLew	0:80ee8f3b695e	1008	SET_BIT(DBGMCU->APB1FZR1, Periphs);
EricLew	0:80ee8f3b695e	1009	}
EricLew	0:80ee8f3b695e	1010
EricLew	0:80ee8f3b695e	1011	/**
EricLew	0:80ee8f3b695e	1012	* @brief Freeze APB1 peripherals (group2 peripherals)
EricLew	0:80ee8f3b695e	1013	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP2_FreezePeriph
EricLew	0:80ee8f3b695e	1014	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1015	* @arg @ref LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP
EricLew	0:80ee8f3b695e	1016	* @retval None
EricLew	0:80ee8f3b695e	1017	*/
EricLew	0:80ee8f3b695e	1018	__STATIC_INLINE void LL_DBGMCU_ABP1_GRP2_FreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1019	{
EricLew	0:80ee8f3b695e	1020	SET_BIT(DBGMCU->APB1FZR2, Periphs);
EricLew	0:80ee8f3b695e	1021	}
EricLew	0:80ee8f3b695e	1022
EricLew	0:80ee8f3b695e	1023	/**
EricLew	0:80ee8f3b695e	1024	* @brief Unfreeze APB1 peripherals (group1 peripherals)
EricLew	0:80ee8f3b695e	1025	* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP1_UnFreezePeriph
EricLew	0:80ee8f3b695e	1026	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1027	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM2_STOP
EricLew	0:80ee8f3b695e	1028	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM3_STOP
EricLew	0:80ee8f3b695e	1029	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM4_STOP
EricLew	0:80ee8f3b695e	1030	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM5_STOP
EricLew	0:80ee8f3b695e	1031	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM6_STOP
EricLew	0:80ee8f3b695e	1032	* @arg @ref LL_DBGMCU_ABP1_GRP1_TIM7_STOP
EricLew	0:80ee8f3b695e	1033	* @arg @ref LL_DBGMCU_ABP1_GRP1_RTC_STOP
EricLew	0:80ee8f3b695e	1034	* @arg @ref LL_DBGMCU_ABP1_GRP1_WWDG_STOP
EricLew	0:80ee8f3b695e	1035	* @arg @ref LL_DBGMCU_ABP1_GRP1_IWDG_STOP
EricLew	0:80ee8f3b695e	1036	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C1_STOP
EricLew	0:80ee8f3b695e	1037	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C2_STOP
EricLew	0:80ee8f3b695e	1038	* @arg @ref LL_DBGMCU_ABP1_GRP1_I2C3_STOP
EricLew	0:80ee8f3b695e	1039	* @arg @ref LL_DBGMCU_ABP1_GRP1_CAN_STOP
EricLew	0:80ee8f3b695e	1040	* @arg @ref LL_DBGMCU_ABP1_GRP1_LPTIM1_STOP
EricLew	0:80ee8f3b695e	1041	* @retval None
EricLew	0:80ee8f3b695e	1042	*/
EricLew	0:80ee8f3b695e	1043	__STATIC_INLINE void LL_DBGMCU_ABP1_GRP1_UnFreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1044	{
EricLew	0:80ee8f3b695e	1045	CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
EricLew	0:80ee8f3b695e	1046	}
EricLew	0:80ee8f3b695e	1047
EricLew	0:80ee8f3b695e	1048	/**
EricLew	0:80ee8f3b695e	1049	* @brief Unfreeze APB1 peripherals (group2 peripherals)
EricLew	0:80ee8f3b695e	1050	* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_ABP1_GRP2_UnFreezePeriph
EricLew	0:80ee8f3b695e	1051	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1052	* @arg @ref LL_DBGMCU_ABP1_GRP2_LPTIM2_STOP
EricLew	0:80ee8f3b695e	1053	* @retval None
EricLew	0:80ee8f3b695e	1054	*/
EricLew	0:80ee8f3b695e	1055	__STATIC_INLINE void LL_DBGMCU_ABP1_GRP2_UnFreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1056	{
EricLew	0:80ee8f3b695e	1057	CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
EricLew	0:80ee8f3b695e	1058	}
EricLew	0:80ee8f3b695e	1059
EricLew	0:80ee8f3b695e	1060	/**
EricLew	0:80ee8f3b695e	1061	* @brief Freeze APB2 peripherals
EricLew	0:80ee8f3b695e	1062	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_ABP2_GRP1_FreezePeriph
EricLew	0:80ee8f3b695e	1063	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1064	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM1_STOP
EricLew	0:80ee8f3b695e	1065	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM8_STOP
EricLew	0:80ee8f3b695e	1066	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM15_STOP
EricLew	0:80ee8f3b695e	1067	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM16_STOP
EricLew	0:80ee8f3b695e	1068	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM17_STOP
EricLew	0:80ee8f3b695e	1069	* @retval None
EricLew	0:80ee8f3b695e	1070	*/
EricLew	0:80ee8f3b695e	1071	__STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_FreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1072	{
EricLew	0:80ee8f3b695e	1073	SET_BIT(DBGMCU->APB2FZ, Periphs);
EricLew	0:80ee8f3b695e	1074	}
EricLew	0:80ee8f3b695e	1075
EricLew	0:80ee8f3b695e	1076	/**
EricLew	0:80ee8f3b695e	1077	* @brief Unfreeze APB2 peripherals
EricLew	0:80ee8f3b695e	1078	* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_ABP2_GRP1_UnFreezePeriph
EricLew	0:80ee8f3b695e	1079	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1080	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM1_STOP
EricLew	0:80ee8f3b695e	1081	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM8_STOP
EricLew	0:80ee8f3b695e	1082	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM15_STOP
EricLew	0:80ee8f3b695e	1083	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM16_STOP
EricLew	0:80ee8f3b695e	1084	* @arg @ref LL_DBGMCU_ABP2_GRP1_TIM17_STOP
EricLew	0:80ee8f3b695e	1085	* @retval None
EricLew	0:80ee8f3b695e	1086	*/
EricLew	0:80ee8f3b695e	1087	__STATIC_INLINE void LL_DBGMCU_ABP2_GRP1_UnFreezePeriph(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1088	{
EricLew	0:80ee8f3b695e	1089	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
EricLew	0:80ee8f3b695e	1090	}
EricLew	0:80ee8f3b695e	1091
EricLew	0:80ee8f3b695e	1092	/**
EricLew	0:80ee8f3b695e	1093	* @}
EricLew	0:80ee8f3b695e	1094	*/
EricLew	0:80ee8f3b695e	1095
EricLew	0:80ee8f3b695e	1096
EricLew	0:80ee8f3b695e	1097	/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
EricLew	0:80ee8f3b695e	1098	* @{
EricLew	0:80ee8f3b695e	1099	*/
EricLew	0:80ee8f3b695e	1100
EricLew	0:80ee8f3b695e	1101	/**
EricLew	0:80ee8f3b695e	1102	* @brief Enable Internal voltage reference
EricLew	0:80ee8f3b695e	1103	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
EricLew	0:80ee8f3b695e	1104	* @retval None
EricLew	0:80ee8f3b695e	1105	*/
EricLew	0:80ee8f3b695e	1106	__STATIC_INLINE void LL_VREFBUF_Enable(void)
EricLew	0:80ee8f3b695e	1107	{
EricLew	0:80ee8f3b695e	1108	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
EricLew	0:80ee8f3b695e	1109	}
EricLew	0:80ee8f3b695e	1110
EricLew	0:80ee8f3b695e	1111	/**
EricLew	0:80ee8f3b695e	1112	* @brief Disable Internal voltage reference
EricLew	0:80ee8f3b695e	1113	* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
EricLew	0:80ee8f3b695e	1114	* @retval None
EricLew	0:80ee8f3b695e	1115	*/
EricLew	0:80ee8f3b695e	1116	__STATIC_INLINE void LL_VREFBUF_Disable(void)
EricLew	0:80ee8f3b695e	1117	{
EricLew	0:80ee8f3b695e	1118	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
EricLew	0:80ee8f3b695e	1119	}
EricLew	0:80ee8f3b695e	1120
EricLew	0:80ee8f3b695e	1121	/**
EricLew	0:80ee8f3b695e	1122	* @brief Enable high impedance (VREF+pin is high impedance)
EricLew	0:80ee8f3b695e	1123	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
EricLew	0:80ee8f3b695e	1124	* @retval None
EricLew	0:80ee8f3b695e	1125	*/
EricLew	0:80ee8f3b695e	1126	__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
EricLew	0:80ee8f3b695e	1127	{
EricLew	0:80ee8f3b695e	1128	SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
EricLew	0:80ee8f3b695e	1129	}
EricLew	0:80ee8f3b695e	1130
EricLew	0:80ee8f3b695e	1131	/**
EricLew	0:80ee8f3b695e	1132	* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
EricLew	0:80ee8f3b695e	1133	* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
EricLew	0:80ee8f3b695e	1134	* @retval None
EricLew	0:80ee8f3b695e	1135	*/
EricLew	0:80ee8f3b695e	1136	__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
EricLew	0:80ee8f3b695e	1137	{
EricLew	0:80ee8f3b695e	1138	CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
EricLew	0:80ee8f3b695e	1139	}
EricLew	0:80ee8f3b695e	1140
EricLew	0:80ee8f3b695e	1141	/**
EricLew	0:80ee8f3b695e	1142	* @brief Set the Voltage reference scale
EricLew	0:80ee8f3b695e	1143	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
EricLew	0:80ee8f3b695e	1144	* @param Scale This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1145	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
EricLew	0:80ee8f3b695e	1146	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
EricLew	0:80ee8f3b695e	1147	* @retval None
EricLew	0:80ee8f3b695e	1148	*/
EricLew	0:80ee8f3b695e	1149	__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
EricLew	0:80ee8f3b695e	1150	{
EricLew	0:80ee8f3b695e	1151	MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
EricLew	0:80ee8f3b695e	1152	}
EricLew	0:80ee8f3b695e	1153
EricLew	0:80ee8f3b695e	1154	/**
EricLew	0:80ee8f3b695e	1155	* @brief Get the Voltage reference scale
EricLew	0:80ee8f3b695e	1156	* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
EricLew	0:80ee8f3b695e	1157	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1158	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
EricLew	0:80ee8f3b695e	1159	* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
EricLew	0:80ee8f3b695e	1160	*/
EricLew	0:80ee8f3b695e	1161	__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
EricLew	0:80ee8f3b695e	1162	{
EricLew	0:80ee8f3b695e	1163	return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
EricLew	0:80ee8f3b695e	1164	}
EricLew	0:80ee8f3b695e	1165
EricLew	0:80ee8f3b695e	1166	/**
EricLew	0:80ee8f3b695e	1167	* @brief Check if Voltage reference buffer is ready
EricLew	0:80ee8f3b695e	1168	* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
EricLew	0:80ee8f3b695e	1169	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1170	*/
EricLew	0:80ee8f3b695e	1171	__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
EricLew	0:80ee8f3b695e	1172	{
EricLew	0:80ee8f3b695e	1173	return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
EricLew	0:80ee8f3b695e	1174	}
EricLew	0:80ee8f3b695e	1175
EricLew	0:80ee8f3b695e	1176	/**
EricLew	0:80ee8f3b695e	1177	* @brief Get the trimming code for VREFBUF calibration
EricLew	0:80ee8f3b695e	1178	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
EricLew	0:80ee8f3b695e	1179	* @retval Between 0 and 0x3F
EricLew	0:80ee8f3b695e	1180	*/
EricLew	0:80ee8f3b695e	1181	__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
EricLew	0:80ee8f3b695e	1182	{
EricLew	0:80ee8f3b695e	1183	return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
EricLew	0:80ee8f3b695e	1184	}
EricLew	0:80ee8f3b695e	1185
EricLew	0:80ee8f3b695e	1186	/**
EricLew	0:80ee8f3b695e	1187	* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
EricLew	0:80ee8f3b695e	1188	* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
EricLew	0:80ee8f3b695e	1189	* @param Value Between 0 and 0x3F
EricLew	0:80ee8f3b695e	1190	* @retval None
EricLew	0:80ee8f3b695e	1191	*/
EricLew	0:80ee8f3b695e	1192	__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
EricLew	0:80ee8f3b695e	1193	{
EricLew	0:80ee8f3b695e	1194	WRITE_REG(VREFBUF->CCR, Value);
EricLew	0:80ee8f3b695e	1195	}
EricLew	0:80ee8f3b695e	1196
EricLew	0:80ee8f3b695e	1197	/**
EricLew	0:80ee8f3b695e	1198	* @}
EricLew	0:80ee8f3b695e	1199	*/
EricLew	0:80ee8f3b695e	1200
EricLew	0:80ee8f3b695e	1201
EricLew	0:80ee8f3b695e	1202	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
EricLew	0:80ee8f3b695e	1203	* @{
EricLew	0:80ee8f3b695e	1204	*/
EricLew	0:80ee8f3b695e	1205
EricLew	0:80ee8f3b695e	1206	/**
EricLew	0:80ee8f3b695e	1207	* @brief Set FLASH Latency
EricLew	0:80ee8f3b695e	1208	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
EricLew	0:80ee8f3b695e	1209	* @param Latency This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1210	* @arg @ref LL_FLASH_LATENCY_0
EricLew	0:80ee8f3b695e	1211	* @arg @ref LL_FLASH_LATENCY_1
EricLew	0:80ee8f3b695e	1212	* @arg @ref LL_FLASH_LATENCY_2
EricLew	0:80ee8f3b695e	1213	* @arg @ref LL_FLASH_LATENCY_3
EricLew	0:80ee8f3b695e	1214	* @arg @ref LL_FLASH_LATENCY_4
EricLew	0:80ee8f3b695e	1215	* @retval None
EricLew	0:80ee8f3b695e	1216	*/
EricLew	0:80ee8f3b695e	1217	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
EricLew	0:80ee8f3b695e	1218	{
EricLew	0:80ee8f3b695e	1219	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
EricLew	0:80ee8f3b695e	1220	}
EricLew	0:80ee8f3b695e	1221
EricLew	0:80ee8f3b695e	1222	/**
EricLew	0:80ee8f3b695e	1223	* @brief Get FLASH Latency
EricLew	0:80ee8f3b695e	1224	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
EricLew	0:80ee8f3b695e	1225	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1226	* @arg @ref LL_FLASH_LATENCY_0
EricLew	0:80ee8f3b695e	1227	* @arg @ref LL_FLASH_LATENCY_1
EricLew	0:80ee8f3b695e	1228	* @arg @ref LL_FLASH_LATENCY_2
EricLew	0:80ee8f3b695e	1229	* @arg @ref LL_FLASH_LATENCY_3
EricLew	0:80ee8f3b695e	1230	* @arg @ref LL_FLASH_LATENCY_4
EricLew	0:80ee8f3b695e	1231	*/
EricLew	0:80ee8f3b695e	1232	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
EricLew	0:80ee8f3b695e	1233	{
EricLew	0:80ee8f3b695e	1234	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
EricLew	0:80ee8f3b695e	1235	}
EricLew	0:80ee8f3b695e	1236
EricLew	0:80ee8f3b695e	1237	/**
EricLew	0:80ee8f3b695e	1238	* @brief Enable Prefetch
EricLew	0:80ee8f3b695e	1239	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
EricLew	0:80ee8f3b695e	1240	* @retval None
EricLew	0:80ee8f3b695e	1241	*/
EricLew	0:80ee8f3b695e	1242	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
EricLew	0:80ee8f3b695e	1243	{
EricLew	0:80ee8f3b695e	1244	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
EricLew	0:80ee8f3b695e	1245	}
EricLew	0:80ee8f3b695e	1246
EricLew	0:80ee8f3b695e	1247	/**
EricLew	0:80ee8f3b695e	1248	* @brief Disable Prefetch
EricLew	0:80ee8f3b695e	1249	* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
EricLew	0:80ee8f3b695e	1250	* @retval None
EricLew	0:80ee8f3b695e	1251	*/
EricLew	0:80ee8f3b695e	1252	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
EricLew	0:80ee8f3b695e	1253	{
EricLew	0:80ee8f3b695e	1254	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
EricLew	0:80ee8f3b695e	1255	}
EricLew	0:80ee8f3b695e	1256
EricLew	0:80ee8f3b695e	1257	/**
EricLew	0:80ee8f3b695e	1258	* @brief Enable Instruction cache
EricLew	0:80ee8f3b695e	1259	* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
EricLew	0:80ee8f3b695e	1260	* @retval None
EricLew	0:80ee8f3b695e	1261	*/
EricLew	0:80ee8f3b695e	1262	__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
EricLew	0:80ee8f3b695e	1263	{
EricLew	0:80ee8f3b695e	1264	SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
EricLew	0:80ee8f3b695e	1265	}
EricLew	0:80ee8f3b695e	1266
EricLew	0:80ee8f3b695e	1267	/**
EricLew	0:80ee8f3b695e	1268	* @brief Disable Instruction cache
EricLew	0:80ee8f3b695e	1269	* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
EricLew	0:80ee8f3b695e	1270	* @retval None
EricLew	0:80ee8f3b695e	1271	*/
EricLew	0:80ee8f3b695e	1272	__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
EricLew	0:80ee8f3b695e	1273	{
EricLew	0:80ee8f3b695e	1274	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
EricLew	0:80ee8f3b695e	1275	}
EricLew	0:80ee8f3b695e	1276
EricLew	0:80ee8f3b695e	1277	/**
EricLew	0:80ee8f3b695e	1278	* @brief Enable Data cache
EricLew	0:80ee8f3b695e	1279	* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
EricLew	0:80ee8f3b695e	1280	* @retval None
EricLew	0:80ee8f3b695e	1281	*/
EricLew	0:80ee8f3b695e	1282	__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
EricLew	0:80ee8f3b695e	1283	{
EricLew	0:80ee8f3b695e	1284	SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
EricLew	0:80ee8f3b695e	1285	}
EricLew	0:80ee8f3b695e	1286
EricLew	0:80ee8f3b695e	1287	/**
EricLew	0:80ee8f3b695e	1288	* @brief Disable Data cache
EricLew	0:80ee8f3b695e	1289	* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
EricLew	0:80ee8f3b695e	1290	* @retval None
EricLew	0:80ee8f3b695e	1291	*/
EricLew	0:80ee8f3b695e	1292	__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
EricLew	0:80ee8f3b695e	1293	{
EricLew	0:80ee8f3b695e	1294	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
EricLew	0:80ee8f3b695e	1295	}
EricLew	0:80ee8f3b695e	1296
EricLew	0:80ee8f3b695e	1297	/**
EricLew	0:80ee8f3b695e	1298	* @brief Enable Instruction cache reset
EricLew	0:80ee8f3b695e	1299	* @note bit can be written only when the instruction cache is disabled
EricLew	0:80ee8f3b695e	1300	* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
EricLew	0:80ee8f3b695e	1301	* @retval None
EricLew	0:80ee8f3b695e	1302	*/
EricLew	0:80ee8f3b695e	1303	__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
EricLew	0:80ee8f3b695e	1304	{
EricLew	0:80ee8f3b695e	1305	SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
EricLew	0:80ee8f3b695e	1306	}
EricLew	0:80ee8f3b695e	1307
EricLew	0:80ee8f3b695e	1308	/**
EricLew	0:80ee8f3b695e	1309	* @brief Disable Instruction cache reset
EricLew	0:80ee8f3b695e	1310	* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
EricLew	0:80ee8f3b695e	1311	* @retval None
EricLew	0:80ee8f3b695e	1312	*/
EricLew	0:80ee8f3b695e	1313	__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
EricLew	0:80ee8f3b695e	1314	{
EricLew	0:80ee8f3b695e	1315	CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
EricLew	0:80ee8f3b695e	1316	}
EricLew	0:80ee8f3b695e	1317
EricLew	0:80ee8f3b695e	1318	/**
EricLew	0:80ee8f3b695e	1319	* @brief Enable Data cache reset
EricLew	0:80ee8f3b695e	1320	* @note bit can be written only when the data cache is disabled
EricLew	0:80ee8f3b695e	1321	* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
EricLew	0:80ee8f3b695e	1322	* @retval None
EricLew	0:80ee8f3b695e	1323	*/
EricLew	0:80ee8f3b695e	1324	__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
EricLew	0:80ee8f3b695e	1325	{
EricLew	0:80ee8f3b695e	1326	SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
EricLew	0:80ee8f3b695e	1327	}
EricLew	0:80ee8f3b695e	1328
EricLew	0:80ee8f3b695e	1329	/**
EricLew	0:80ee8f3b695e	1330	* @brief Disable Data cache reset
EricLew	0:80ee8f3b695e	1331	* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
EricLew	0:80ee8f3b695e	1332	* @retval None
EricLew	0:80ee8f3b695e	1333	*/
EricLew	0:80ee8f3b695e	1334	__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
EricLew	0:80ee8f3b695e	1335	{
EricLew	0:80ee8f3b695e	1336	CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
EricLew	0:80ee8f3b695e	1337	}
EricLew	0:80ee8f3b695e	1338
EricLew	0:80ee8f3b695e	1339	/**
EricLew	0:80ee8f3b695e	1340	* @brief Enable Flash Power-down mode during run mode or Low-power run mode
EricLew	0:80ee8f3b695e	1341	* @note Flash memory can be put in power-down mode only when the code is executed
EricLew	0:80ee8f3b695e	1342	* from RAM
EricLew	0:80ee8f3b695e	1343	* @note Flash must not be accessed when power down is enabled
EricLew	0:80ee8f3b695e	1344	* @note Flash must not be put in power-down while a program or an erase operation
EricLew	0:80ee8f3b695e	1345	* is on-going
EricLew	0:80ee8f3b695e	1346	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
EricLew	0:80ee8f3b695e	1347	* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
EricLew	0:80ee8f3b695e	1348	* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
EricLew	0:80ee8f3b695e	1349	* @retval None
EricLew	0:80ee8f3b695e	1350	*/
EricLew	0:80ee8f3b695e	1351	__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
EricLew	0:80ee8f3b695e	1352	{
EricLew	0:80ee8f3b695e	1353	/* Following values must be written consecutively to unlock the RUN_PD bit in
EricLew	0:80ee8f3b695e	1354	FLASH_ACR */
EricLew	0:80ee8f3b695e	1355	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
EricLew	0:80ee8f3b695e	1356	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
EricLew	0:80ee8f3b695e	1357	SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
EricLew	0:80ee8f3b695e	1358	}
EricLew	0:80ee8f3b695e	1359
EricLew	0:80ee8f3b695e	1360	/**
EricLew	0:80ee8f3b695e	1361	* @brief Disable Flash Power-down mode during run mode or Low-power run mode
EricLew	0:80ee8f3b695e	1362	* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
EricLew	0:80ee8f3b695e	1363	* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
EricLew	0:80ee8f3b695e	1364	* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
EricLew	0:80ee8f3b695e	1365	* @retval None
EricLew	0:80ee8f3b695e	1366	*/
EricLew	0:80ee8f3b695e	1367	__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
EricLew	0:80ee8f3b695e	1368	{
EricLew	0:80ee8f3b695e	1369	/* Following values must be written consecutively to unlock the RUN_PD bit in
EricLew	0:80ee8f3b695e	1370	FLASH_ACR */
EricLew	0:80ee8f3b695e	1371	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
EricLew	0:80ee8f3b695e	1372	WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
EricLew	0:80ee8f3b695e	1373	CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
EricLew	0:80ee8f3b695e	1374	}
EricLew	0:80ee8f3b695e	1375
EricLew	0:80ee8f3b695e	1376	/**
EricLew	0:80ee8f3b695e	1377	* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
EricLew	0:80ee8f3b695e	1378	* @note Flash must not be put in power-down while a program or an erase operation
EricLew	0:80ee8f3b695e	1379	* is on-going
EricLew	0:80ee8f3b695e	1380	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
EricLew	0:80ee8f3b695e	1381	* @retval None
EricLew	0:80ee8f3b695e	1382	*/
EricLew	0:80ee8f3b695e	1383	__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
EricLew	0:80ee8f3b695e	1384	{
EricLew	0:80ee8f3b695e	1385	SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
EricLew	0:80ee8f3b695e	1386	}
EricLew	0:80ee8f3b695e	1387
EricLew	0:80ee8f3b695e	1388	/**
EricLew	0:80ee8f3b695e	1389	* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
EricLew	0:80ee8f3b695e	1390	* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
EricLew	0:80ee8f3b695e	1391	* @retval None
EricLew	0:80ee8f3b695e	1392	*/
EricLew	0:80ee8f3b695e	1393	__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
EricLew	0:80ee8f3b695e	1394	{
EricLew	0:80ee8f3b695e	1395	CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
EricLew	0:80ee8f3b695e	1396	}
EricLew	0:80ee8f3b695e	1397
EricLew	0:80ee8f3b695e	1398	/**
EricLew	0:80ee8f3b695e	1399	* @}
EricLew	0:80ee8f3b695e	1400	*/
EricLew	0:80ee8f3b695e	1401
EricLew	0:80ee8f3b695e	1402	/**
EricLew	0:80ee8f3b695e	1403	* @}
EricLew	0:80ee8f3b695e	1404	*/
EricLew	0:80ee8f3b695e	1405
EricLew	0:80ee8f3b695e	1406	/**
EricLew	0:80ee8f3b695e	1407	* @}
EricLew	0:80ee8f3b695e	1408	*/
EricLew	0:80ee8f3b695e	1409
EricLew	0:80ee8f3b695e	1410	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) \|\| defined (VREFBUF) */
EricLew	0:80ee8f3b695e	1411
EricLew	0:80ee8f3b695e	1412	/**
EricLew	0:80ee8f3b695e	1413	* @}
EricLew	0:80ee8f3b695e	1414	*/
EricLew	0:80ee8f3b695e	1415
EricLew	0:80ee8f3b695e	1416	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	1417	}
EricLew	0:80ee8f3b695e	1418	#endif
EricLew	0:80ee8f3b695e	1419
EricLew	0:80ee8f3b695e	1420	#endif /* __STM32L4xx_LL_SYSTEM_H */
EricLew	0:80ee8f3b695e	1421
EricLew	0:80ee8f3b695e	1422	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	1423

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_system.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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