STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_i2c.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

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User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_i2c.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of I2C LL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_LL_I2C_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_LL_I2C_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3)
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	/** @defgroup I2C_LL I2C
EricLew	0:80ee8f3b695e	56	* @{
EricLew	0:80ee8f3b695e	57	*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	61
EricLew	0:80ee8f3b695e	62	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	63
EricLew	0:80ee8f3b695e	64	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	65
EricLew	0:80ee8f3b695e	66	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	67	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	68	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
EricLew	0:80ee8f3b695e	69	* @{
EricLew	0:80ee8f3b695e	70	*/
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
EricLew	0:80ee8f3b695e	73	* @brief Flags defines which can be used with LL_I2C_WriteReg function
EricLew	0:80ee8f3b695e	74	* @{
EricLew	0:80ee8f3b695e	75	*/
EricLew	0:80ee8f3b695e	76	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF
EricLew	0:80ee8f3b695e	77	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF
EricLew	0:80ee8f3b695e	78	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF
EricLew	0:80ee8f3b695e	79	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF
EricLew	0:80ee8f3b695e	80	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF
EricLew	0:80ee8f3b695e	81	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF
EricLew	0:80ee8f3b695e	82	/**
EricLew	0:80ee8f3b695e	83	* @}
EricLew	0:80ee8f3b695e	84	*/
EricLew	0:80ee8f3b695e	85
EricLew	0:80ee8f3b695e	86	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
EricLew	0:80ee8f3b695e	87	* @brief Flags defines which can be used with LL_I2C_ReadReg function
EricLew	0:80ee8f3b695e	88	* @{
EricLew	0:80ee8f3b695e	89	*/
EricLew	0:80ee8f3b695e	90	#define LL_I2C_ISR_TXE I2C_ISR_TXE
EricLew	0:80ee8f3b695e	91	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS
EricLew	0:80ee8f3b695e	92	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE
EricLew	0:80ee8f3b695e	93	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR
EricLew	0:80ee8f3b695e	94	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF
EricLew	0:80ee8f3b695e	95	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF
EricLew	0:80ee8f3b695e	96	#define LL_I2C_ISR_TC I2C_ISR_TC
EricLew	0:80ee8f3b695e	97	#define LL_I2C_ISR_TCR I2C_ISR_TCR
EricLew	0:80ee8f3b695e	98	#define LL_I2C_ISR_BERR I2C_ISR_BERR
EricLew	0:80ee8f3b695e	99	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO
EricLew	0:80ee8f3b695e	100	#define LL_I2C_ISR_OVR I2C_ISR_OVR
EricLew	0:80ee8f3b695e	101	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY
EricLew	0:80ee8f3b695e	102	/**
EricLew	0:80ee8f3b695e	103	* @}
EricLew	0:80ee8f3b695e	104	*/
EricLew	0:80ee8f3b695e	105
EricLew	0:80ee8f3b695e	106	/** @defgroup I2C_LL_EC_IT IT Defines
EricLew	0:80ee8f3b695e	107	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
EricLew	0:80ee8f3b695e	108	* @{
EricLew	0:80ee8f3b695e	109	*/
EricLew	0:80ee8f3b695e	110	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE
EricLew	0:80ee8f3b695e	111	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE
EricLew	0:80ee8f3b695e	112	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE
EricLew	0:80ee8f3b695e	113	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE
EricLew	0:80ee8f3b695e	114	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE
EricLew	0:80ee8f3b695e	115	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE
EricLew	0:80ee8f3b695e	116	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE
EricLew	0:80ee8f3b695e	117	/**
EricLew	0:80ee8f3b695e	118	* @}
EricLew	0:80ee8f3b695e	119	*/
EricLew	0:80ee8f3b695e	120
EricLew	0:80ee8f3b695e	121	/** @defgroup I2C_LL_EC_ADDRESSING_MODE ADDRESSING MODE
EricLew	0:80ee8f3b695e	122	* @{
EricLew	0:80ee8f3b695e	123	*/
EricLew	0:80ee8f3b695e	124	#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000) /!<Master operates in 7-bit addressing mode. /
EricLew	0:80ee8f3b695e	125	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!<Master operates in 10-bit addressing mode./
EricLew	0:80ee8f3b695e	126	/**
EricLew	0:80ee8f3b695e	127	* @}
EricLew	0:80ee8f3b695e	128	*/
EricLew	0:80ee8f3b695e	129
EricLew	0:80ee8f3b695e	130	/** @defgroup I2C_LL_EC_OWNADDRESS1 OWNADDRESS1
EricLew	0:80ee8f3b695e	131	* @{
EricLew	0:80ee8f3b695e	132	*/
EricLew	0:80ee8f3b695e	133	#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000) /!<Own address 1 is a 7-bit address. /
EricLew	0:80ee8f3b695e	134	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!<Own address 1 is a 10-bit address./
EricLew	0:80ee8f3b695e	135	/**
EricLew	0:80ee8f3b695e	136	* @}
EricLew	0:80ee8f3b695e	137	*/
EricLew	0:80ee8f3b695e	138
EricLew	0:80ee8f3b695e	139	/** @defgroup I2C_LL_EC_OWNADDRESS2 OWNADDRESS2
EricLew	0:80ee8f3b695e	140	* @{
EricLew	0:80ee8f3b695e	141	*/
EricLew	0:80ee8f3b695e	142	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!<Own Address2 No mask. /
EricLew	0:80ee8f3b695e	143	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!<Only Address2 bits[7:2] are compared. /
EricLew	0:80ee8f3b695e	144	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!<Only Address2 bits[7:3] are compared. /
EricLew	0:80ee8f3b695e	145	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!<Only Address2 bits[7:4] are compared. /
EricLew	0:80ee8f3b695e	146	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!<Only Address2 bits[7:5] are compared. /
EricLew	0:80ee8f3b695e	147	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!<Only Address2 bits[7:6] are compared. /
EricLew	0:80ee8f3b695e	148	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!<Only Address2 bits[7] are compared. /
EricLew	0:80ee8f3b695e	149	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!<No comparison is done. All Address2 are acknowledged./
EricLew	0:80ee8f3b695e	150	/**
EricLew	0:80ee8f3b695e	151	* @}
EricLew	0:80ee8f3b695e	152	*/
EricLew	0:80ee8f3b695e	153
EricLew	0:80ee8f3b695e	154	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE ACKNOWLEDGE
EricLew	0:80ee8f3b695e	155	* @{
EricLew	0:80ee8f3b695e	156	*/
EricLew	0:80ee8f3b695e	157	#define LL_I2C_ACK ((uint32_t) 0x00000000) /!<ACK is sent after current received byte. /
EricLew	0:80ee8f3b695e	158	#define LL_I2C_NACK I2C_CR2_NACK /!<NACK is sent after current received byte./
EricLew	0:80ee8f3b695e	159	/**
EricLew	0:80ee8f3b695e	160	* @}
EricLew	0:80ee8f3b695e	161	*/
EricLew	0:80ee8f3b695e	162
EricLew	0:80ee8f3b695e	163	/** @defgroup I2C_LL_EC_ADDRSLAVE ADDRSLAVE
EricLew	0:80ee8f3b695e	164	* @{
EricLew	0:80ee8f3b695e	165	*/
EricLew	0:80ee8f3b695e	166	#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000) /!<Slave Address in 7-bit. /
EricLew	0:80ee8f3b695e	167	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!<Slave Address in 10-bit./
EricLew	0:80ee8f3b695e	168	/**
EricLew	0:80ee8f3b695e	169	* @}
EricLew	0:80ee8f3b695e	170	*/
EricLew	0:80ee8f3b695e	171
EricLew	0:80ee8f3b695e	172	/** @defgroup I2C_LL_EC_MODE MODE
EricLew	0:80ee8f3b695e	173	* @{
EricLew	0:80ee8f3b695e	174	*/
EricLew	0:80ee8f3b695e	175	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!<Enable Reload mode. /
EricLew	0:80ee8f3b695e	176	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!<Enable Automatic end mode./
EricLew	0:80ee8f3b695e	177	#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000) /!<Enable Software end mode. /
EricLew	0:80ee8f3b695e	178	/**
EricLew	0:80ee8f3b695e	179	* @}
EricLew	0:80ee8f3b695e	180	*/
EricLew	0:80ee8f3b695e	181
EricLew	0:80ee8f3b695e	182	/** @defgroup I2C_LL_EC_GENERATE GENERATE
EricLew	0:80ee8f3b695e	183	* @{
EricLew	0:80ee8f3b695e	184	*/
EricLew	0:80ee8f3b695e	185	#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000) /!<Don't Generate Stop and Start condition. /
EricLew	0:80ee8f3b695e	186	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!<Generate Stop condition (Size should be set to 0). /
EricLew	0:80ee8f3b695e	187	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!<Generate Start for read request. /
EricLew	0:80ee8f3b695e	188	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!<Generate Start for write request. /
EricLew	0:80ee8f3b695e	189	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!<Generate Restart for read request, slave 7Bit address. /
EricLew	0:80ee8f3b695e	190	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!<Generate Restart for write request, slave 7Bit address. /
EricLew	0:80ee8f3b695e	191	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!<Generate Restart for read request, slave 10Bit address. /
EricLew	0:80ee8f3b695e	192	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!<Generate Restart for write request, slave 10Bit address./
EricLew	0:80ee8f3b695e	193	/**
EricLew	0:80ee8f3b695e	194	* @}
EricLew	0:80ee8f3b695e	195	*/
EricLew	0:80ee8f3b695e	196
EricLew	0:80ee8f3b695e	197	/** @defgroup I2C_LL_EC_DIRECTION DIRECTION
EricLew	0:80ee8f3b695e	198	* @{
EricLew	0:80ee8f3b695e	199	*/
EricLew	0:80ee8f3b695e	200	#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000) /!<Write transfer, slave enters receiver mode. /
EricLew	0:80ee8f3b695e	201	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!<Read transfer, slave enters transmitter mode./
EricLew	0:80ee8f3b695e	202	/**
EricLew	0:80ee8f3b695e	203	* @}
EricLew	0:80ee8f3b695e	204	*/
EricLew	0:80ee8f3b695e	205
EricLew	0:80ee8f3b695e	206	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA register data
EricLew	0:80ee8f3b695e	207	* @{
EricLew	0:80ee8f3b695e	208	*/
EricLew	0:80ee8f3b695e	209	#define LL_I2C_DMA_REG_DATA_TRANSMIT (uint32_t)0 /!<Get address of data register used for transmission /
EricLew	0:80ee8f3b695e	210	#define LL_I2C_DMA_REG_DATA_RECEIVE (uint32_t)1 /!<Get address of data register used for reception /
EricLew	0:80ee8f3b695e	211	/**
EricLew	0:80ee8f3b695e	212	* @}
EricLew	0:80ee8f3b695e	213	*/
EricLew	0:80ee8f3b695e	214
EricLew	0:80ee8f3b695e	215	/**
EricLew	0:80ee8f3b695e	216	* @}
EricLew	0:80ee8f3b695e	217	*/
EricLew	0:80ee8f3b695e	218
EricLew	0:80ee8f3b695e	219	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	220	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
EricLew	0:80ee8f3b695e	221	* @{
EricLew	0:80ee8f3b695e	222	*/
EricLew	0:80ee8f3b695e	223
EricLew	0:80ee8f3b695e	224	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
EricLew	0:80ee8f3b695e	225	* @{
EricLew	0:80ee8f3b695e	226	*/
EricLew	0:80ee8f3b695e	227
EricLew	0:80ee8f3b695e	228	/**
EricLew	0:80ee8f3b695e	229	* @brief Write a value in I2C register
EricLew	0:80ee8f3b695e	230	* @param __INSTANCE__ I2C Instance
EricLew	0:80ee8f3b695e	231	* @param __REG__ Register to be written
EricLew	0:80ee8f3b695e	232	* @param __VALUE__ Value to be written in the register
EricLew	0:80ee8f3b695e	233	* @retval None
EricLew	0:80ee8f3b695e	234	*/
EricLew	0:80ee8f3b695e	235	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
EricLew	0:80ee8f3b695e	236
EricLew	0:80ee8f3b695e	237	/**
EricLew	0:80ee8f3b695e	238	* @brief Read a value in I2C register
EricLew	0:80ee8f3b695e	239	* @param __INSTANCE__ I2C Instance
EricLew	0:80ee8f3b695e	240	* @param __REG__ Register to be read
EricLew	0:80ee8f3b695e	241	* @retval Register value
EricLew	0:80ee8f3b695e	242	*/
EricLew	0:80ee8f3b695e	243	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
EricLew	0:80ee8f3b695e	244	/**
EricLew	0:80ee8f3b695e	245	* @}
EricLew	0:80ee8f3b695e	246	*/
EricLew	0:80ee8f3b695e	247
EricLew	0:80ee8f3b695e	248	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
EricLew	0:80ee8f3b695e	249	* @{
EricLew	0:80ee8f3b695e	250	*/
EricLew	0:80ee8f3b695e	251	/**
EricLew	0:80ee8f3b695e	252	* @brief Configure the SDA setup, hold time and the SCL high, low period.
EricLew	0:80ee8f3b695e	253	* @param __PRESCALER__ This parameter must be a value between 0 and 0xF.
EricLew	0:80ee8f3b695e	254	* @param __DATA_SETUP_TIME__ This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
EricLew	0:80ee8f3b695e	255	* @param __DATA_HOLD_TIME__ This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
EricLew	0:80ee8f3b695e	256	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
EricLew	0:80ee8f3b695e	257	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between 0 and 0xFF. (tscll = (SCLL+1)xtpresc)
EricLew	0:80ee8f3b695e	258	* @retval Value between 0 and 0xFFFFFFFF
EricLew	0:80ee8f3b695e	259	*/
EricLew	0:80ee8f3b695e	260	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
EricLew	0:80ee8f3b695e	261	((((uint32_t)(__PRESCALER__) << (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)) & I2C_TIMINGR_PRESC) \| \
EricLew	0:80ee8f3b695e	262	(((uint32_t)(__DATA_SETUP_TIME__) << (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)) & I2C_TIMINGR_SCLDEL) \| \
EricLew	0:80ee8f3b695e	263	(((uint32_t)(__DATA_HOLD_TIME__) << (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)) & I2C_TIMINGR_SDADEL) \| \
EricLew	0:80ee8f3b695e	264	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)) & I2C_TIMINGR_SCLH) \| \
EricLew	0:80ee8f3b695e	265	(((uint32_t)(__CLOCK_LOW_PERIOD__) << (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)) & I2C_TIMINGR_SCLL))
EricLew	0:80ee8f3b695e	266	/**
EricLew	0:80ee8f3b695e	267	* @}
EricLew	0:80ee8f3b695e	268	*/
EricLew	0:80ee8f3b695e	269
EricLew	0:80ee8f3b695e	270	/**
EricLew	0:80ee8f3b695e	271	* @}
EricLew	0:80ee8f3b695e	272	*/
EricLew	0:80ee8f3b695e	273
EricLew	0:80ee8f3b695e	274	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	275	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
EricLew	0:80ee8f3b695e	276	* @{
EricLew	0:80ee8f3b695e	277	*/
EricLew	0:80ee8f3b695e	278
EricLew	0:80ee8f3b695e	279	/** @defgroup I2C_LL_EF_Configuration Configuration
EricLew	0:80ee8f3b695e	280	* @{
EricLew	0:80ee8f3b695e	281	*/
EricLew	0:80ee8f3b695e	282
EricLew	0:80ee8f3b695e	283	/**
EricLew	0:80ee8f3b695e	284	* @brief Enable I2C peripheral (PE = 1).
EricLew	0:80ee8f3b695e	285	* @rmtoll CR1 PE LL_I2C_Enable
EricLew	0:80ee8f3b695e	286	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	287	* @retval None
EricLew	0:80ee8f3b695e	288	*/
EricLew	0:80ee8f3b695e	289	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	290	{
EricLew	0:80ee8f3b695e	291	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
EricLew	0:80ee8f3b695e	292	}
EricLew	0:80ee8f3b695e	293
EricLew	0:80ee8f3b695e	294	/**
EricLew	0:80ee8f3b695e	295	* @brief Disable I2C peripheral (PE = 0).
EricLew	0:80ee8f3b695e	296	* @note When PE = 0, the I2C SCL and SDA lines are released.
EricLew	0:80ee8f3b695e	297	* Internal state machines and status bits are put back to their reset value.
EricLew	0:80ee8f3b695e	298	* When cleared, PE must be kept low for at least 3 APB clock cycles.
EricLew	0:80ee8f3b695e	299	* @rmtoll CR1 PE LL_I2C_Disable
EricLew	0:80ee8f3b695e	300	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	301	* @retval None
EricLew	0:80ee8f3b695e	302	*/
EricLew	0:80ee8f3b695e	303	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	304	{
EricLew	0:80ee8f3b695e	305	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
EricLew	0:80ee8f3b695e	306	}
EricLew	0:80ee8f3b695e	307
EricLew	0:80ee8f3b695e	308	/**
EricLew	0:80ee8f3b695e	309	* @brief Check if the I2C peripheral is enabled or disabled.
EricLew	0:80ee8f3b695e	310	* @rmtoll CR1 PE LL_I2C_IsEnabled
EricLew	0:80ee8f3b695e	311	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	312	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	313	*/
EricLew	0:80ee8f3b695e	314	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	315	{
EricLew	0:80ee8f3b695e	316	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
EricLew	0:80ee8f3b695e	317	}
EricLew	0:80ee8f3b695e	318
EricLew	0:80ee8f3b695e	319	/**
EricLew	0:80ee8f3b695e	320	* @brief Configure Digital Noise Filter.
EricLew	0:80ee8f3b695e	321	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
EricLew	0:80ee8f3b695e	322	* This filter can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	323	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
EricLew	0:80ee8f3b695e	324	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	325	* @param DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15ti2cclk). This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0]ti2cclk.
EricLew	0:80ee8f3b695e	326	* @retval None
EricLew	0:80ee8f3b695e	327	*/
EricLew	0:80ee8f3b695e	328	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef* I2Cx, uint32_t DigitalFilter)
EricLew	0:80ee8f3b695e	329	{
EricLew	0:80ee8f3b695e	330	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << POSITION_VAL(I2C_CR1_DNF));
EricLew	0:80ee8f3b695e	331	}
EricLew	0:80ee8f3b695e	332
EricLew	0:80ee8f3b695e	333	/**
EricLew	0:80ee8f3b695e	334	* @brief Get the current Digital Noise Filter configuration.
EricLew	0:80ee8f3b695e	335	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
EricLew	0:80ee8f3b695e	336	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	337	* @retval 0..0xF
EricLew	0:80ee8f3b695e	338	*/
EricLew	0:80ee8f3b695e	339	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	340	{
EricLew	0:80ee8f3b695e	341	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> POSITION_VAL(I2C_CR1_DNF));
EricLew	0:80ee8f3b695e	342	}
EricLew	0:80ee8f3b695e	343
EricLew	0:80ee8f3b695e	344	/**
EricLew	0:80ee8f3b695e	345	* @brief Enable Analog Noise Filter.
EricLew	0:80ee8f3b695e	346	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	347	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
EricLew	0:80ee8f3b695e	348	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	349	* @retval None
EricLew	0:80ee8f3b695e	350	*/
EricLew	0:80ee8f3b695e	351	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	352	{
EricLew	0:80ee8f3b695e	353	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
EricLew	0:80ee8f3b695e	354	}
EricLew	0:80ee8f3b695e	355
EricLew	0:80ee8f3b695e	356	/**
EricLew	0:80ee8f3b695e	357	* @brief Disable Analog Noise Filter.
EricLew	0:80ee8f3b695e	358	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	359	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
EricLew	0:80ee8f3b695e	360	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	361	* @retval None
EricLew	0:80ee8f3b695e	362	*/
EricLew	0:80ee8f3b695e	363	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	364	{
EricLew	0:80ee8f3b695e	365	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
EricLew	0:80ee8f3b695e	366	}
EricLew	0:80ee8f3b695e	367
EricLew	0:80ee8f3b695e	368	/**
EricLew	0:80ee8f3b695e	369	* @brief Check if Analog Noise Filter is enabled or disabled.
EricLew	0:80ee8f3b695e	370	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
EricLew	0:80ee8f3b695e	371	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	372	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	373	*/
EricLew	0:80ee8f3b695e	374	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	375	{
EricLew	0:80ee8f3b695e	376	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
EricLew	0:80ee8f3b695e	377	}
EricLew	0:80ee8f3b695e	378
EricLew	0:80ee8f3b695e	379	/**
EricLew	0:80ee8f3b695e	380	* @brief Enable DMA transmission requests.
EricLew	0:80ee8f3b695e	381	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
EricLew	0:80ee8f3b695e	382	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	383	* @retval None
EricLew	0:80ee8f3b695e	384	*/
EricLew	0:80ee8f3b695e	385	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	386	{
EricLew	0:80ee8f3b695e	387	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
EricLew	0:80ee8f3b695e	388	}
EricLew	0:80ee8f3b695e	389
EricLew	0:80ee8f3b695e	390	/**
EricLew	0:80ee8f3b695e	391	* @brief Disable DMA transmission requests.
EricLew	0:80ee8f3b695e	392	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
EricLew	0:80ee8f3b695e	393	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	394	* @retval None
EricLew	0:80ee8f3b695e	395	*/
EricLew	0:80ee8f3b695e	396	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	397	{
EricLew	0:80ee8f3b695e	398	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
EricLew	0:80ee8f3b695e	399	}
EricLew	0:80ee8f3b695e	400
EricLew	0:80ee8f3b695e	401	/**
EricLew	0:80ee8f3b695e	402	* @brief Check if DMA transmission requests are enabled or disabled.
EricLew	0:80ee8f3b695e	403	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
EricLew	0:80ee8f3b695e	404	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	405	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	406	*/
EricLew	0:80ee8f3b695e	407	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	408	{
EricLew	0:80ee8f3b695e	409	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
EricLew	0:80ee8f3b695e	410	}
EricLew	0:80ee8f3b695e	411
EricLew	0:80ee8f3b695e	412	/**
EricLew	0:80ee8f3b695e	413	* @brief Enable DMA reception requests.
EricLew	0:80ee8f3b695e	414	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
EricLew	0:80ee8f3b695e	415	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	416	* @retval None
EricLew	0:80ee8f3b695e	417	*/
EricLew	0:80ee8f3b695e	418	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	419	{
EricLew	0:80ee8f3b695e	420	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
EricLew	0:80ee8f3b695e	421	}
EricLew	0:80ee8f3b695e	422
EricLew	0:80ee8f3b695e	423	/**
EricLew	0:80ee8f3b695e	424	* @brief Disable DMA reception requests.
EricLew	0:80ee8f3b695e	425	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
EricLew	0:80ee8f3b695e	426	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	427	* @retval None
EricLew	0:80ee8f3b695e	428	*/
EricLew	0:80ee8f3b695e	429	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	430	{
EricLew	0:80ee8f3b695e	431	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
EricLew	0:80ee8f3b695e	432	}
EricLew	0:80ee8f3b695e	433
EricLew	0:80ee8f3b695e	434	/**
EricLew	0:80ee8f3b695e	435	* @brief Check if DMA reception requests are enabled or disabled.
EricLew	0:80ee8f3b695e	436	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
EricLew	0:80ee8f3b695e	437	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	438	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	439	*/
EricLew	0:80ee8f3b695e	440	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	441	{
EricLew	0:80ee8f3b695e	442	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
EricLew	0:80ee8f3b695e	443	}
EricLew	0:80ee8f3b695e	444
EricLew	0:80ee8f3b695e	445	/**
EricLew	0:80ee8f3b695e	446	* @brief Get the data register address used for DMA transfer
EricLew	0:80ee8f3b695e	447	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
EricLew	0:80ee8f3b695e	448	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
EricLew	0:80ee8f3b695e	449	* @param I2Cx I2C Instance
EricLew	0:80ee8f3b695e	450	* @param Direction This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	451	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
EricLew	0:80ee8f3b695e	452	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
EricLew	0:80ee8f3b695e	453	* @retval Address of data register
EricLew	0:80ee8f3b695e	454	*/
EricLew	0:80ee8f3b695e	455	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef * I2Cx, uint32_t Direction)
EricLew	0:80ee8f3b695e	456	{
EricLew	0:80ee8f3b695e	457	register uint32_t data_reg_addr = 0;
EricLew	0:80ee8f3b695e	458
EricLew	0:80ee8f3b695e	459	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
EricLew	0:80ee8f3b695e	460	{
EricLew	0:80ee8f3b695e	461	/* return address of TXDR register */
EricLew	0:80ee8f3b695e	462	data_reg_addr = (uint32_t)&(I2Cx->TXDR);
EricLew	0:80ee8f3b695e	463	}
EricLew	0:80ee8f3b695e	464	else
EricLew	0:80ee8f3b695e	465	{
EricLew	0:80ee8f3b695e	466	/* return address of RXDR register */
EricLew	0:80ee8f3b695e	467	data_reg_addr = (uint32_t)&(I2Cx->RXDR);
EricLew	0:80ee8f3b695e	468	}
EricLew	0:80ee8f3b695e	469
EricLew	0:80ee8f3b695e	470	return data_reg_addr;
EricLew	0:80ee8f3b695e	471	}
EricLew	0:80ee8f3b695e	472
EricLew	0:80ee8f3b695e	473	/**
EricLew	0:80ee8f3b695e	474	* @brief Enable Clock stretching.
EricLew	0:80ee8f3b695e	475	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	476	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
EricLew	0:80ee8f3b695e	477	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	478	* @retval None
EricLew	0:80ee8f3b695e	479	*/
EricLew	0:80ee8f3b695e	480	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	481	{
EricLew	0:80ee8f3b695e	482	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
EricLew	0:80ee8f3b695e	483	}
EricLew	0:80ee8f3b695e	484
EricLew	0:80ee8f3b695e	485	/**
EricLew	0:80ee8f3b695e	486	* @brief Disable Clock stretching.
EricLew	0:80ee8f3b695e	487	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	488	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
EricLew	0:80ee8f3b695e	489	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	490	* @retval None
EricLew	0:80ee8f3b695e	491	*/
EricLew	0:80ee8f3b695e	492	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	493	{
EricLew	0:80ee8f3b695e	494	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
EricLew	0:80ee8f3b695e	495	}
EricLew	0:80ee8f3b695e	496
EricLew	0:80ee8f3b695e	497	/**
EricLew	0:80ee8f3b695e	498	* @brief Check if Clock stretching is enabled or disabled.
EricLew	0:80ee8f3b695e	499	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
EricLew	0:80ee8f3b695e	500	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	501	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	502	*/
EricLew	0:80ee8f3b695e	503	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	504	{
EricLew	0:80ee8f3b695e	505	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
EricLew	0:80ee8f3b695e	506	}
EricLew	0:80ee8f3b695e	507
EricLew	0:80ee8f3b695e	508	/**
EricLew	0:80ee8f3b695e	509	* @brief Enable Wakeup from STOP.
EricLew	0:80ee8f3b695e	510	* @note This bit can only be programmed when Digital Filter is disabled.
EricLew	0:80ee8f3b695e	511	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
EricLew	0:80ee8f3b695e	512	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	513	* @retval None
EricLew	0:80ee8f3b695e	514	*/
EricLew	0:80ee8f3b695e	515	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	516	{
EricLew	0:80ee8f3b695e	517	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
EricLew	0:80ee8f3b695e	518	}
EricLew	0:80ee8f3b695e	519
EricLew	0:80ee8f3b695e	520	/**
EricLew	0:80ee8f3b695e	521	* @brief Disable Wakeup from STOP.
EricLew	0:80ee8f3b695e	522	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
EricLew	0:80ee8f3b695e	523	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	524	* @retval None
EricLew	0:80ee8f3b695e	525	*/
EricLew	0:80ee8f3b695e	526	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	527	{
EricLew	0:80ee8f3b695e	528	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
EricLew	0:80ee8f3b695e	529	}
EricLew	0:80ee8f3b695e	530
EricLew	0:80ee8f3b695e	531	/**
EricLew	0:80ee8f3b695e	532	* @brief Check if Wakeup from STOP is enabled or disabled.
EricLew	0:80ee8f3b695e	533	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
EricLew	0:80ee8f3b695e	534	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	535	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	536	*/
EricLew	0:80ee8f3b695e	537	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	538	{
EricLew	0:80ee8f3b695e	539	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
EricLew	0:80ee8f3b695e	540	}
EricLew	0:80ee8f3b695e	541
EricLew	0:80ee8f3b695e	542	/**
EricLew	0:80ee8f3b695e	543	* @brief Enable General Call.
EricLew	0:80ee8f3b695e	544	* @note When enabled the Address 0x00 is ACKed.
EricLew	0:80ee8f3b695e	545	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
EricLew	0:80ee8f3b695e	546	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	547	* @retval None
EricLew	0:80ee8f3b695e	548	*/
EricLew	0:80ee8f3b695e	549	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	550	{
EricLew	0:80ee8f3b695e	551	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
EricLew	0:80ee8f3b695e	552	}
EricLew	0:80ee8f3b695e	553
EricLew	0:80ee8f3b695e	554	/**
EricLew	0:80ee8f3b695e	555	* @brief Disable General Call.
EricLew	0:80ee8f3b695e	556	* @note When disabled the Address 0x00 is NACKed.
EricLew	0:80ee8f3b695e	557	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
EricLew	0:80ee8f3b695e	558	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	559	* @retval None
EricLew	0:80ee8f3b695e	560	*/
EricLew	0:80ee8f3b695e	561	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	562	{
EricLew	0:80ee8f3b695e	563	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
EricLew	0:80ee8f3b695e	564	}
EricLew	0:80ee8f3b695e	565
EricLew	0:80ee8f3b695e	566	/**
EricLew	0:80ee8f3b695e	567	* @brief Check if General Call is enabled or disabled.
EricLew	0:80ee8f3b695e	568	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
EricLew	0:80ee8f3b695e	569	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	570	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	571	*/
EricLew	0:80ee8f3b695e	572	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	573	{
EricLew	0:80ee8f3b695e	574	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
EricLew	0:80ee8f3b695e	575	}
EricLew	0:80ee8f3b695e	576
EricLew	0:80ee8f3b695e	577	/**
EricLew	0:80ee8f3b695e	578	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
EricLew	0:80ee8f3b695e	579	* @note Changing this bit is not allowed, when the START bit is set.
EricLew	0:80ee8f3b695e	580	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
EricLew	0:80ee8f3b695e	581	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	582	* @param AddressingMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	583	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
EricLew	0:80ee8f3b695e	584	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
EricLew	0:80ee8f3b695e	585	* @retval None
EricLew	0:80ee8f3b695e	586	*/
EricLew	0:80ee8f3b695e	587	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef* I2Cx, uint32_t AddressingMode)
EricLew	0:80ee8f3b695e	588	{
EricLew	0:80ee8f3b695e	589	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
EricLew	0:80ee8f3b695e	590	}
EricLew	0:80ee8f3b695e	591
EricLew	0:80ee8f3b695e	592	/**
EricLew	0:80ee8f3b695e	593	* @brief Get the Master addressing mode.
EricLew	0:80ee8f3b695e	594	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
EricLew	0:80ee8f3b695e	595	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	596	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	597	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
EricLew	0:80ee8f3b695e	598	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
EricLew	0:80ee8f3b695e	599	*/
EricLew	0:80ee8f3b695e	600	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	601	{
EricLew	0:80ee8f3b695e	602	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
EricLew	0:80ee8f3b695e	603	}
EricLew	0:80ee8f3b695e	604
EricLew	0:80ee8f3b695e	605	/**
EricLew	0:80ee8f3b695e	606	* @brief Set the Own Address1.
EricLew	0:80ee8f3b695e	607	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
EricLew	0:80ee8f3b695e	608	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
EricLew	0:80ee8f3b695e	609	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	610	* @param OwnAddr This parameter must be a value between 0 and 0x7F.
EricLew	0:80ee8f3b695e	611	* @param OwnAddrSize This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	612	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
EricLew	0:80ee8f3b695e	613	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
EricLew	0:80ee8f3b695e	614	* @retval None
EricLew	0:80ee8f3b695e	615	*/
EricLew	0:80ee8f3b695e	616	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef* I2Cx, uint32_t OwnAddr, uint32_t OwnAddrSize)
EricLew	0:80ee8f3b695e	617	{
EricLew	0:80ee8f3b695e	618	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddr \| OwnAddrSize);
EricLew	0:80ee8f3b695e	619	}
EricLew	0:80ee8f3b695e	620
EricLew	0:80ee8f3b695e	621	/**
EricLew	0:80ee8f3b695e	622	* @brief Enable acknowledge on Own Address1 match address.
EricLew	0:80ee8f3b695e	623	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
EricLew	0:80ee8f3b695e	624	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	625	* @retval None
EricLew	0:80ee8f3b695e	626	*/
EricLew	0:80ee8f3b695e	627	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	628	{
EricLew	0:80ee8f3b695e	629	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
EricLew	0:80ee8f3b695e	630	}
EricLew	0:80ee8f3b695e	631
EricLew	0:80ee8f3b695e	632	/**
EricLew	0:80ee8f3b695e	633	* @brief Disable acknowledge on Own Address1 match address.
EricLew	0:80ee8f3b695e	634	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
EricLew	0:80ee8f3b695e	635	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	636	* @retval None
EricLew	0:80ee8f3b695e	637	*/
EricLew	0:80ee8f3b695e	638	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	639	{
EricLew	0:80ee8f3b695e	640	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
EricLew	0:80ee8f3b695e	641	}
EricLew	0:80ee8f3b695e	642
EricLew	0:80ee8f3b695e	643	/**
EricLew	0:80ee8f3b695e	644	* @brief Check if Own Address1 acknowledge is enabled or disabled.
EricLew	0:80ee8f3b695e	645	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
EricLew	0:80ee8f3b695e	646	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	647	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	648	*/
EricLew	0:80ee8f3b695e	649	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	650	{
EricLew	0:80ee8f3b695e	651	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
EricLew	0:80ee8f3b695e	652	}
EricLew	0:80ee8f3b695e	653
EricLew	0:80ee8f3b695e	654	/**
EricLew	0:80ee8f3b695e	655	* @brief Set the 7bits Own Address2.
EricLew	0:80ee8f3b695e	656	* @note This action has no effect if own address2 is enabled.
EricLew	0:80ee8f3b695e	657	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
EricLew	0:80ee8f3b695e	658	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
EricLew	0:80ee8f3b695e	659	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	660	* @param OwnAddr Value between 0 and 0x7F.
EricLew	0:80ee8f3b695e	661	* @param OwnAddrMask This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	662	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
EricLew	0:80ee8f3b695e	663	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
EricLew	0:80ee8f3b695e	664	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
EricLew	0:80ee8f3b695e	665	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
EricLew	0:80ee8f3b695e	666	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
EricLew	0:80ee8f3b695e	667	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
EricLew	0:80ee8f3b695e	668	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
EricLew	0:80ee8f3b695e	669	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
EricLew	0:80ee8f3b695e	670	* @retval None
EricLew	0:80ee8f3b695e	671	*/
EricLew	0:80ee8f3b695e	672	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef* I2Cx, uint32_t OwnAddr, uint32_t OwnAddrMask)
EricLew	0:80ee8f3b695e	673	{
EricLew	0:80ee8f3b695e	674	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddr \| OwnAddrMask);
EricLew	0:80ee8f3b695e	675	}
EricLew	0:80ee8f3b695e	676
EricLew	0:80ee8f3b695e	677	/**
EricLew	0:80ee8f3b695e	678	* @brief Enable acknowledge on Own Address2 match address.
EricLew	0:80ee8f3b695e	679	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
EricLew	0:80ee8f3b695e	680	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	681	* @retval None
EricLew	0:80ee8f3b695e	682	*/
EricLew	0:80ee8f3b695e	683	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	684	{
EricLew	0:80ee8f3b695e	685	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
EricLew	0:80ee8f3b695e	686	}
EricLew	0:80ee8f3b695e	687
EricLew	0:80ee8f3b695e	688	/**
EricLew	0:80ee8f3b695e	689	* @brief Disable acknowledge on Own Address2 match address.
EricLew	0:80ee8f3b695e	690	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
EricLew	0:80ee8f3b695e	691	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	692	* @retval None
EricLew	0:80ee8f3b695e	693	*/
EricLew	0:80ee8f3b695e	694	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	695	{
EricLew	0:80ee8f3b695e	696	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
EricLew	0:80ee8f3b695e	697	}
EricLew	0:80ee8f3b695e	698
EricLew	0:80ee8f3b695e	699	/**
EricLew	0:80ee8f3b695e	700	* @brief Check if Own Address1 acknowledge is enabled or disabled.
EricLew	0:80ee8f3b695e	701	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
EricLew	0:80ee8f3b695e	702	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	703	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	704	*/
EricLew	0:80ee8f3b695e	705	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	706	{
EricLew	0:80ee8f3b695e	707	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
EricLew	0:80ee8f3b695e	708	}
EricLew	0:80ee8f3b695e	709
EricLew	0:80ee8f3b695e	710	/**
EricLew	0:80ee8f3b695e	711	* @brief Configure the SDA setup, hold time and the SCL high, low period.
EricLew	0:80ee8f3b695e	712	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
EricLew	0:80ee8f3b695e	713	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
EricLew	0:80ee8f3b695e	714	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	715	* @param TimingValue This parameter must be a value between 0 and 0xFFFFFFFF.
EricLew	0:80ee8f3b695e	716	* @note This parameter is computed with the STM32CubeMX Tool.
EricLew	0:80ee8f3b695e	717	* @retval None
EricLew	0:80ee8f3b695e	718	*/
EricLew	0:80ee8f3b695e	719	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef* I2Cx, uint32_t TimingValue)
EricLew	0:80ee8f3b695e	720	{
EricLew	0:80ee8f3b695e	721	WRITE_REG(I2Cx->TIMINGR, TimingValue);
EricLew	0:80ee8f3b695e	722	}
EricLew	0:80ee8f3b695e	723
EricLew	0:80ee8f3b695e	724	/**
EricLew	0:80ee8f3b695e	725	* @brief Get the Timing Prescaler setting.
EricLew	0:80ee8f3b695e	726	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
EricLew	0:80ee8f3b695e	727	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	728	* @retval 0..0xF
EricLew	0:80ee8f3b695e	729	*/
EricLew	0:80ee8f3b695e	730	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	731	{
EricLew	0:80ee8f3b695e	732	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> POSITION_VAL(I2C_TIMINGR_PRESC));
EricLew	0:80ee8f3b695e	733	}
EricLew	0:80ee8f3b695e	734
EricLew	0:80ee8f3b695e	735	/**
EricLew	0:80ee8f3b695e	736	* @brief Get the SCL low period setting.
EricLew	0:80ee8f3b695e	737	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
EricLew	0:80ee8f3b695e	738	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	739	* @retval 0..0xFF
EricLew	0:80ee8f3b695e	740	*/
EricLew	0:80ee8f3b695e	741	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	742	{
EricLew	0:80ee8f3b695e	743	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> POSITION_VAL(I2C_TIMINGR_SCLL));
EricLew	0:80ee8f3b695e	744	}
EricLew	0:80ee8f3b695e	745
EricLew	0:80ee8f3b695e	746	/**
EricLew	0:80ee8f3b695e	747	* @brief Get the SCL high period setting.
EricLew	0:80ee8f3b695e	748	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
EricLew	0:80ee8f3b695e	749	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	750	* @retval 0..0xFF
EricLew	0:80ee8f3b695e	751	*/
EricLew	0:80ee8f3b695e	752	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	753	{
EricLew	0:80ee8f3b695e	754	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> POSITION_VAL(I2C_TIMINGR_SCLH));
EricLew	0:80ee8f3b695e	755	}
EricLew	0:80ee8f3b695e	756
EricLew	0:80ee8f3b695e	757	/**
EricLew	0:80ee8f3b695e	758	* @brief Get the SDA hold time.
EricLew	0:80ee8f3b695e	759	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
EricLew	0:80ee8f3b695e	760	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	761	* @retval 0..0xF
EricLew	0:80ee8f3b695e	762	*/
EricLew	0:80ee8f3b695e	763	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	764	{
EricLew	0:80ee8f3b695e	765	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> POSITION_VAL(I2C_TIMINGR_SDADEL));
EricLew	0:80ee8f3b695e	766	}
EricLew	0:80ee8f3b695e	767
EricLew	0:80ee8f3b695e	768	/**
EricLew	0:80ee8f3b695e	769	* @brief Get the SDA setup time.
EricLew	0:80ee8f3b695e	770	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
EricLew	0:80ee8f3b695e	771	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	772	* @retval 0..0xF
EricLew	0:80ee8f3b695e	773	*/
EricLew	0:80ee8f3b695e	774	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	775	{
EricLew	0:80ee8f3b695e	776	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> POSITION_VAL(I2C_TIMINGR_SCLDEL));
EricLew	0:80ee8f3b695e	777	}
EricLew	0:80ee8f3b695e	778
EricLew	0:80ee8f3b695e	779	/**
EricLew	0:80ee8f3b695e	780	* @}
EricLew	0:80ee8f3b695e	781	*/
EricLew	0:80ee8f3b695e	782
EricLew	0:80ee8f3b695e	783	/** @defgroup I2C_LL_EF_IT_Management IT_Management
EricLew	0:80ee8f3b695e	784	* @{
EricLew	0:80ee8f3b695e	785	*/
EricLew	0:80ee8f3b695e	786
EricLew	0:80ee8f3b695e	787	/**
EricLew	0:80ee8f3b695e	788	* @brief Enable TXIS interrupt.
EricLew	0:80ee8f3b695e	789	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
EricLew	0:80ee8f3b695e	790	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	791	* @retval None
EricLew	0:80ee8f3b695e	792	*/
EricLew	0:80ee8f3b695e	793	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	794	{
EricLew	0:80ee8f3b695e	795	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
EricLew	0:80ee8f3b695e	796	}
EricLew	0:80ee8f3b695e	797
EricLew	0:80ee8f3b695e	798	/**
EricLew	0:80ee8f3b695e	799	* @brief Disable TXIS interrupt.
EricLew	0:80ee8f3b695e	800	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
EricLew	0:80ee8f3b695e	801	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	802	* @retval None
EricLew	0:80ee8f3b695e	803	*/
EricLew	0:80ee8f3b695e	804	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	805	{
EricLew	0:80ee8f3b695e	806	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
EricLew	0:80ee8f3b695e	807	}
EricLew	0:80ee8f3b695e	808
EricLew	0:80ee8f3b695e	809	/**
EricLew	0:80ee8f3b695e	810	* @brief Check if the TXIS Interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	811	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
EricLew	0:80ee8f3b695e	812	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	813	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	814	*/
EricLew	0:80ee8f3b695e	815	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	816	{
EricLew	0:80ee8f3b695e	817	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
EricLew	0:80ee8f3b695e	818	}
EricLew	0:80ee8f3b695e	819
EricLew	0:80ee8f3b695e	820	/**
EricLew	0:80ee8f3b695e	821	* @brief Enable RXNE interrupt.
EricLew	0:80ee8f3b695e	822	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
EricLew	0:80ee8f3b695e	823	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	824	* @retval None
EricLew	0:80ee8f3b695e	825	*/
EricLew	0:80ee8f3b695e	826	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	827	{
EricLew	0:80ee8f3b695e	828	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
EricLew	0:80ee8f3b695e	829	}
EricLew	0:80ee8f3b695e	830
EricLew	0:80ee8f3b695e	831	/**
EricLew	0:80ee8f3b695e	832	* @brief Disable RXNE interrupt.
EricLew	0:80ee8f3b695e	833	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
EricLew	0:80ee8f3b695e	834	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	835	* @retval None
EricLew	0:80ee8f3b695e	836	*/
EricLew	0:80ee8f3b695e	837	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	838	{
EricLew	0:80ee8f3b695e	839	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
EricLew	0:80ee8f3b695e	840	}
EricLew	0:80ee8f3b695e	841
EricLew	0:80ee8f3b695e	842	/**
EricLew	0:80ee8f3b695e	843	* @brief Check if the RXNE Interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	844	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
EricLew	0:80ee8f3b695e	845	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	846	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	847	*/
EricLew	0:80ee8f3b695e	848	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	849	{
EricLew	0:80ee8f3b695e	850	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
EricLew	0:80ee8f3b695e	851	}
EricLew	0:80ee8f3b695e	852
EricLew	0:80ee8f3b695e	853	/**
EricLew	0:80ee8f3b695e	854	* @brief Enable Address match interrupt (slave mode only).
EricLew	0:80ee8f3b695e	855	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
EricLew	0:80ee8f3b695e	856	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	857	* @retval None
EricLew	0:80ee8f3b695e	858	*/
EricLew	0:80ee8f3b695e	859	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	860	{
EricLew	0:80ee8f3b695e	861	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
EricLew	0:80ee8f3b695e	862	}
EricLew	0:80ee8f3b695e	863
EricLew	0:80ee8f3b695e	864	/**
EricLew	0:80ee8f3b695e	865	* @brief Disable Address match interrupt (slave mode only).
EricLew	0:80ee8f3b695e	866	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
EricLew	0:80ee8f3b695e	867	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	868	* @retval None
EricLew	0:80ee8f3b695e	869	*/
EricLew	0:80ee8f3b695e	870	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	871	{
EricLew	0:80ee8f3b695e	872	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
EricLew	0:80ee8f3b695e	873	}
EricLew	0:80ee8f3b695e	874
EricLew	0:80ee8f3b695e	875	/**
EricLew	0:80ee8f3b695e	876	* @brief Check if Address match interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	877	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
EricLew	0:80ee8f3b695e	878	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	879	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	880	*/
EricLew	0:80ee8f3b695e	881	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	882	{
EricLew	0:80ee8f3b695e	883	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
EricLew	0:80ee8f3b695e	884	}
EricLew	0:80ee8f3b695e	885
EricLew	0:80ee8f3b695e	886	/**
EricLew	0:80ee8f3b695e	887	* @brief Enable Not acknowledge received interrupt.
EricLew	0:80ee8f3b695e	888	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
EricLew	0:80ee8f3b695e	889	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	890	* @retval None
EricLew	0:80ee8f3b695e	891	*/
EricLew	0:80ee8f3b695e	892	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	893	{
EricLew	0:80ee8f3b695e	894	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
EricLew	0:80ee8f3b695e	895	}
EricLew	0:80ee8f3b695e	896
EricLew	0:80ee8f3b695e	897	/**
EricLew	0:80ee8f3b695e	898	* @brief Disable Not acknowledge received interrupt.
EricLew	0:80ee8f3b695e	899	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
EricLew	0:80ee8f3b695e	900	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	901	* @retval None
EricLew	0:80ee8f3b695e	902	*/
EricLew	0:80ee8f3b695e	903	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	904	{
EricLew	0:80ee8f3b695e	905	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
EricLew	0:80ee8f3b695e	906	}
EricLew	0:80ee8f3b695e	907
EricLew	0:80ee8f3b695e	908	/**
EricLew	0:80ee8f3b695e	909	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	910	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
EricLew	0:80ee8f3b695e	911	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	912	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	913	*/
EricLew	0:80ee8f3b695e	914	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	915	{
EricLew	0:80ee8f3b695e	916	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
EricLew	0:80ee8f3b695e	917	}
EricLew	0:80ee8f3b695e	918
EricLew	0:80ee8f3b695e	919	/**
EricLew	0:80ee8f3b695e	920	* @brief Enable STOP detection interrupt.
EricLew	0:80ee8f3b695e	921	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
EricLew	0:80ee8f3b695e	922	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	923	* @retval None
EricLew	0:80ee8f3b695e	924	*/
EricLew	0:80ee8f3b695e	925	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	926	{
EricLew	0:80ee8f3b695e	927	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
EricLew	0:80ee8f3b695e	928	}
EricLew	0:80ee8f3b695e	929
EricLew	0:80ee8f3b695e	930	/**
EricLew	0:80ee8f3b695e	931	* @brief Disable STOP detection interrupt.
EricLew	0:80ee8f3b695e	932	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
EricLew	0:80ee8f3b695e	933	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	934	* @retval None
EricLew	0:80ee8f3b695e	935	*/
EricLew	0:80ee8f3b695e	936	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	937	{
EricLew	0:80ee8f3b695e	938	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
EricLew	0:80ee8f3b695e	939	}
EricLew	0:80ee8f3b695e	940
EricLew	0:80ee8f3b695e	941	/**
EricLew	0:80ee8f3b695e	942	* @brief Check if STOP detection interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	943	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
EricLew	0:80ee8f3b695e	944	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	945	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	946	*/
EricLew	0:80ee8f3b695e	947	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	948	{
EricLew	0:80ee8f3b695e	949	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
EricLew	0:80ee8f3b695e	950	}
EricLew	0:80ee8f3b695e	951
EricLew	0:80ee8f3b695e	952	/**
EricLew	0:80ee8f3b695e	953	* @brief Enable Transfer Complete interrupt.
EricLew	0:80ee8f3b695e	954	* @note Any of these events will generate interrupt :
EricLew	0:80ee8f3b695e	955	* Transfer Complete (TC)
EricLew	0:80ee8f3b695e	956	* Transfer Complete Reload (TCR)
EricLew	0:80ee8f3b695e	957	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
EricLew	0:80ee8f3b695e	958	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	959	* @retval None
EricLew	0:80ee8f3b695e	960	*/
EricLew	0:80ee8f3b695e	961	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	962	{
EricLew	0:80ee8f3b695e	963	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
EricLew	0:80ee8f3b695e	964	}
EricLew	0:80ee8f3b695e	965
EricLew	0:80ee8f3b695e	966	/**
EricLew	0:80ee8f3b695e	967	* @brief Disable Transfer Complete interrupt.
EricLew	0:80ee8f3b695e	968	* @note Any of these events will generate interrupt :
EricLew	0:80ee8f3b695e	969	* Transfer Complete (TC)
EricLew	0:80ee8f3b695e	970	* Transfer Complete Reload (TCR)
EricLew	0:80ee8f3b695e	971	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
EricLew	0:80ee8f3b695e	972	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	973	* @retval None
EricLew	0:80ee8f3b695e	974	*/
EricLew	0:80ee8f3b695e	975	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	976	{
EricLew	0:80ee8f3b695e	977	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
EricLew	0:80ee8f3b695e	978	}
EricLew	0:80ee8f3b695e	979
EricLew	0:80ee8f3b695e	980	/**
EricLew	0:80ee8f3b695e	981	* @brief Check if Transfer Complete interrupt is enabled or disabled.
EricLew	0:80ee8f3b695e	982	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
EricLew	0:80ee8f3b695e	983	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	984	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	985	*/
EricLew	0:80ee8f3b695e	986	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	987	{
EricLew	0:80ee8f3b695e	988	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
EricLew	0:80ee8f3b695e	989	}
EricLew	0:80ee8f3b695e	990
EricLew	0:80ee8f3b695e	991	/**
EricLew	0:80ee8f3b695e	992	* @brief Enable Error interrupts.
EricLew	0:80ee8f3b695e	993	* @note Any of these errors will generate interrupt :
EricLew	0:80ee8f3b695e	994	* Arbitration Loss (ARLO)
EricLew	0:80ee8f3b695e	995	* Bus Error detection (BERR)
EricLew	0:80ee8f3b695e	996	* Overrun/Underrun (OVR)
EricLew	0:80ee8f3b695e	997	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
EricLew	0:80ee8f3b695e	998	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	999	* @retval None
EricLew	0:80ee8f3b695e	1000	*/
EricLew	0:80ee8f3b695e	1001	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1002	{
EricLew	0:80ee8f3b695e	1003	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
EricLew	0:80ee8f3b695e	1004	}
EricLew	0:80ee8f3b695e	1005
EricLew	0:80ee8f3b695e	1006	/**
EricLew	0:80ee8f3b695e	1007	* @brief Disable Error interrupts.
EricLew	0:80ee8f3b695e	1008	* @note Any of these errors will generate interrupt :
EricLew	0:80ee8f3b695e	1009	* Arbitration Loss (ARLO)
EricLew	0:80ee8f3b695e	1010	* Bus Error detection (BERR)
EricLew	0:80ee8f3b695e	1011	* Overrun/Underrun (OVR)
EricLew	0:80ee8f3b695e	1012	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
EricLew	0:80ee8f3b695e	1013	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1014	* @retval None
EricLew	0:80ee8f3b695e	1015	*/
EricLew	0:80ee8f3b695e	1016	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1017	{
EricLew	0:80ee8f3b695e	1018	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
EricLew	0:80ee8f3b695e	1019	}
EricLew	0:80ee8f3b695e	1020
EricLew	0:80ee8f3b695e	1021	/**
EricLew	0:80ee8f3b695e	1022	* @brief Check if Error interrupts is enabled of disabled.
EricLew	0:80ee8f3b695e	1023	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
EricLew	0:80ee8f3b695e	1024	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1025	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1026	*/
EricLew	0:80ee8f3b695e	1027	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1028	{
EricLew	0:80ee8f3b695e	1029	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
EricLew	0:80ee8f3b695e	1030	}
EricLew	0:80ee8f3b695e	1031
EricLew	0:80ee8f3b695e	1032	/**
EricLew	0:80ee8f3b695e	1033	* @}
EricLew	0:80ee8f3b695e	1034	*/
EricLew	0:80ee8f3b695e	1035
EricLew	0:80ee8f3b695e	1036	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
EricLew	0:80ee8f3b695e	1037	* @{
EricLew	0:80ee8f3b695e	1038	*/
EricLew	0:80ee8f3b695e	1039
EricLew	0:80ee8f3b695e	1040	/**
EricLew	0:80ee8f3b695e	1041	* @brief Indicate the status of Transmit data register empty flag.
EricLew	0:80ee8f3b695e	1042	* RESET: When next data is written in Transmit data register.
EricLew	0:80ee8f3b695e	1043	* SET: When Transmit data register is empty.
EricLew	0:80ee8f3b695e	1044	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
EricLew	0:80ee8f3b695e	1045	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1046	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1047	*/
EricLew	0:80ee8f3b695e	1048	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1049	{
EricLew	0:80ee8f3b695e	1050	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
EricLew	0:80ee8f3b695e	1051	}
EricLew	0:80ee8f3b695e	1052
EricLew	0:80ee8f3b695e	1053	/**
EricLew	0:80ee8f3b695e	1054	* @brief Indicate the status of Transmit interrupt flag.
EricLew	0:80ee8f3b695e	1055	* RESET: When next data is written in Transmit data register.
EricLew	0:80ee8f3b695e	1056	* SET: When Transmit data register is empty.
EricLew	0:80ee8f3b695e	1057	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
EricLew	0:80ee8f3b695e	1058	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1059	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1060	*/
EricLew	0:80ee8f3b695e	1061	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1062	{
EricLew	0:80ee8f3b695e	1063	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
EricLew	0:80ee8f3b695e	1064	}
EricLew	0:80ee8f3b695e	1065
EricLew	0:80ee8f3b695e	1066	/**
EricLew	0:80ee8f3b695e	1067	* @brief Indicate the status of Receive data register not empty flag.
EricLew	0:80ee8f3b695e	1068	* RESET: When Receive data register is read.
EricLew	0:80ee8f3b695e	1069	* SET: When the received data is copied in Receive data register.
EricLew	0:80ee8f3b695e	1070	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
EricLew	0:80ee8f3b695e	1071	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1072	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1073	*/
EricLew	0:80ee8f3b695e	1074	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1075	{
EricLew	0:80ee8f3b695e	1076	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
EricLew	0:80ee8f3b695e	1077	}
EricLew	0:80ee8f3b695e	1078
EricLew	0:80ee8f3b695e	1079	/**
EricLew	0:80ee8f3b695e	1080	* @brief Indicate the status of Address matched flag (slave mode).
EricLew	0:80ee8f3b695e	1081	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1082	* SET: When the received slave address matched with one of the enabled slave address.
EricLew	0:80ee8f3b695e	1083	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
EricLew	0:80ee8f3b695e	1084	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1085	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1086	*/
EricLew	0:80ee8f3b695e	1087	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1088	{
EricLew	0:80ee8f3b695e	1089	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
EricLew	0:80ee8f3b695e	1090	}
EricLew	0:80ee8f3b695e	1091
EricLew	0:80ee8f3b695e	1092	/**
EricLew	0:80ee8f3b695e	1093	* @brief Indicate the status of Not Acknowledge received flag.
EricLew	0:80ee8f3b695e	1094	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1095	* SET: When a NACK is received after a byte transmission.
EricLew	0:80ee8f3b695e	1096	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
EricLew	0:80ee8f3b695e	1097	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1098	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1099	*/
EricLew	0:80ee8f3b695e	1100	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1101	{
EricLew	0:80ee8f3b695e	1102	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
EricLew	0:80ee8f3b695e	1103	}
EricLew	0:80ee8f3b695e	1104
EricLew	0:80ee8f3b695e	1105	/**
EricLew	0:80ee8f3b695e	1106	* @brief Indicate the status of Stop detection flag.
EricLew	0:80ee8f3b695e	1107	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1108	* SET: When a Stop condition is detected.
EricLew	0:80ee8f3b695e	1109	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
EricLew	0:80ee8f3b695e	1110	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1111	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1112	*/
EricLew	0:80ee8f3b695e	1113	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1114	{
EricLew	0:80ee8f3b695e	1115	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
EricLew	0:80ee8f3b695e	1116	}
EricLew	0:80ee8f3b695e	1117
EricLew	0:80ee8f3b695e	1118	/**
EricLew	0:80ee8f3b695e	1119	* @brief Indicate the status of Transfer complete flag (master mode).
EricLew	0:80ee8f3b695e	1120	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1121	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
EricLew	0:80ee8f3b695e	1122	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
EricLew	0:80ee8f3b695e	1123	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1124	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1125	*/
EricLew	0:80ee8f3b695e	1126	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1127	{
EricLew	0:80ee8f3b695e	1128	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
EricLew	0:80ee8f3b695e	1129	}
EricLew	0:80ee8f3b695e	1130
EricLew	0:80ee8f3b695e	1131	/**
EricLew	0:80ee8f3b695e	1132	* @brief Indicate the status of Transfer complete flag (master mode).
EricLew	0:80ee8f3b695e	1133	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1134	* SET: When RELOAD=1 and NBYTES date have been transferred.
EricLew	0:80ee8f3b695e	1135	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
EricLew	0:80ee8f3b695e	1136	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1137	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1138	*/
EricLew	0:80ee8f3b695e	1139	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1140	{
EricLew	0:80ee8f3b695e	1141	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
EricLew	0:80ee8f3b695e	1142	}
EricLew	0:80ee8f3b695e	1143
EricLew	0:80ee8f3b695e	1144	/**
EricLew	0:80ee8f3b695e	1145	* @brief Indicate the status of Bus error flag.
EricLew	0:80ee8f3b695e	1146	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1147	* SET: When a misplaced Start or Stop condition is detected.
EricLew	0:80ee8f3b695e	1148	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
EricLew	0:80ee8f3b695e	1149	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1150	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1151	*/
EricLew	0:80ee8f3b695e	1152	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1153	{
EricLew	0:80ee8f3b695e	1154	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
EricLew	0:80ee8f3b695e	1155	}
EricLew	0:80ee8f3b695e	1156
EricLew	0:80ee8f3b695e	1157	/**
EricLew	0:80ee8f3b695e	1158	* @brief Indicate the status of Arbitration lost flag.
EricLew	0:80ee8f3b695e	1159	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1160	* SET: When arbitration lost.
EricLew	0:80ee8f3b695e	1161	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
EricLew	0:80ee8f3b695e	1162	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1163	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1164	*/
EricLew	0:80ee8f3b695e	1165	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1166	{
EricLew	0:80ee8f3b695e	1167	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
EricLew	0:80ee8f3b695e	1168	}
EricLew	0:80ee8f3b695e	1169
EricLew	0:80ee8f3b695e	1170	/**
EricLew	0:80ee8f3b695e	1171	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
EricLew	0:80ee8f3b695e	1172	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1173	* SET: When an overrun/underrun error occures (Clock Stretching Disabled).
EricLew	0:80ee8f3b695e	1174	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
EricLew	0:80ee8f3b695e	1175	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1176	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1177	*/
EricLew	0:80ee8f3b695e	1178	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1179	{
EricLew	0:80ee8f3b695e	1180	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
EricLew	0:80ee8f3b695e	1181	}
EricLew	0:80ee8f3b695e	1182
EricLew	0:80ee8f3b695e	1183	/**
EricLew	0:80ee8f3b695e	1184	* @brief Indicate the status of Bus Busy flag.
EricLew	0:80ee8f3b695e	1185	* RESET: Clear default value.
EricLew	0:80ee8f3b695e	1186	* SET: When a Start condition is detected.
EricLew	0:80ee8f3b695e	1187	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
EricLew	0:80ee8f3b695e	1188	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1189	* @retval State of bit (1 or 0).
EricLew	0:80ee8f3b695e	1190	*/
EricLew	0:80ee8f3b695e	1191	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1192	{
EricLew	0:80ee8f3b695e	1193	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
EricLew	0:80ee8f3b695e	1194	}
EricLew	0:80ee8f3b695e	1195
EricLew	0:80ee8f3b695e	1196	/**
EricLew	0:80ee8f3b695e	1197	* @brief Clear Address Matched flag.
EricLew	0:80ee8f3b695e	1198	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
EricLew	0:80ee8f3b695e	1199	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1200	* @retval None
EricLew	0:80ee8f3b695e	1201	*/
EricLew	0:80ee8f3b695e	1202	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1203	{
EricLew	0:80ee8f3b695e	1204	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
EricLew	0:80ee8f3b695e	1205	}
EricLew	0:80ee8f3b695e	1206
EricLew	0:80ee8f3b695e	1207	/**
EricLew	0:80ee8f3b695e	1208	* @brief Clear Not Acknowledge flag.
EricLew	0:80ee8f3b695e	1209	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
EricLew	0:80ee8f3b695e	1210	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1211	* @retval None
EricLew	0:80ee8f3b695e	1212	*/
EricLew	0:80ee8f3b695e	1213	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1214	{
EricLew	0:80ee8f3b695e	1215	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
EricLew	0:80ee8f3b695e	1216	}
EricLew	0:80ee8f3b695e	1217
EricLew	0:80ee8f3b695e	1218	/**
EricLew	0:80ee8f3b695e	1219	* @brief Clear Stop detection flag.
EricLew	0:80ee8f3b695e	1220	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
EricLew	0:80ee8f3b695e	1221	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1222	* @retval None
EricLew	0:80ee8f3b695e	1223	*/
EricLew	0:80ee8f3b695e	1224	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1225	{
EricLew	0:80ee8f3b695e	1226	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
EricLew	0:80ee8f3b695e	1227	}
EricLew	0:80ee8f3b695e	1228
EricLew	0:80ee8f3b695e	1229	/**
EricLew	0:80ee8f3b695e	1230	* @brief Clear Transmit data register empty flag (TXE).
EricLew	0:80ee8f3b695e	1231	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
EricLew	0:80ee8f3b695e	1232	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
EricLew	0:80ee8f3b695e	1233	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1234	* @retval None
EricLew	0:80ee8f3b695e	1235	*/
EricLew	0:80ee8f3b695e	1236	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1237	{
EricLew	0:80ee8f3b695e	1238	I2Cx->ISR = I2C_ISR_TXE;
EricLew	0:80ee8f3b695e	1239	}
EricLew	0:80ee8f3b695e	1240
EricLew	0:80ee8f3b695e	1241	/**
EricLew	0:80ee8f3b695e	1242	* @brief Clear Bus error flag.
EricLew	0:80ee8f3b695e	1243	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
EricLew	0:80ee8f3b695e	1244	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1245	* @retval None
EricLew	0:80ee8f3b695e	1246	*/
EricLew	0:80ee8f3b695e	1247	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1248	{
EricLew	0:80ee8f3b695e	1249	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
EricLew	0:80ee8f3b695e	1250	}
EricLew	0:80ee8f3b695e	1251
EricLew	0:80ee8f3b695e	1252	/**
EricLew	0:80ee8f3b695e	1253	* @brief Clear Arbitration lost flag.
EricLew	0:80ee8f3b695e	1254	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
EricLew	0:80ee8f3b695e	1255	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1256	* @retval None
EricLew	0:80ee8f3b695e	1257	*/
EricLew	0:80ee8f3b695e	1258	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1259	{
EricLew	0:80ee8f3b695e	1260	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
EricLew	0:80ee8f3b695e	1261	}
EricLew	0:80ee8f3b695e	1262
EricLew	0:80ee8f3b695e	1263	/**
EricLew	0:80ee8f3b695e	1264	* @brief Clear Overrun/Underrun flag.
EricLew	0:80ee8f3b695e	1265	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
EricLew	0:80ee8f3b695e	1266	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1267	* @retval None
EricLew	0:80ee8f3b695e	1268	*/
EricLew	0:80ee8f3b695e	1269	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1270	{
EricLew	0:80ee8f3b695e	1271	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
EricLew	0:80ee8f3b695e	1272	}
EricLew	0:80ee8f3b695e	1273
EricLew	0:80ee8f3b695e	1274	/**
EricLew	0:80ee8f3b695e	1275	* @}
EricLew	0:80ee8f3b695e	1276	*/
EricLew	0:80ee8f3b695e	1277
EricLew	0:80ee8f3b695e	1278	/** @defgroup I2C_LL_EF_Data_Management Data_Management
EricLew	0:80ee8f3b695e	1279	* @{
EricLew	0:80ee8f3b695e	1280	*/
EricLew	0:80ee8f3b695e	1281
EricLew	0:80ee8f3b695e	1282	/**
EricLew	0:80ee8f3b695e	1283	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
EricLew	0:80ee8f3b695e	1284	* @note Usage in Slave mode only.
EricLew	0:80ee8f3b695e	1285	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
EricLew	0:80ee8f3b695e	1286	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1287	* @param TypeAcknowledge This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1288	* @arg @ref LL_I2C_ACK
EricLew	0:80ee8f3b695e	1289	* @arg @ref LL_I2C_NACK
EricLew	0:80ee8f3b695e	1290	* @retval None
EricLew	0:80ee8f3b695e	1291	*/
EricLew	0:80ee8f3b695e	1292	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef* I2Cx, uint32_t TypeAcknowledge)
EricLew	0:80ee8f3b695e	1293	{
EricLew	0:80ee8f3b695e	1294	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
EricLew	0:80ee8f3b695e	1295	}
EricLew	0:80ee8f3b695e	1296
EricLew	0:80ee8f3b695e	1297	/**
EricLew	0:80ee8f3b695e	1298	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
EricLew	0:80ee8f3b695e	1299	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1300	* CR2 ADD10 LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1301	* CR2 RD_WRN LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1302	* CR2 START LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1303	* CR2 STOP LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1304	* CR2 RELOAD LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1305	* CR2 NBYTES LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1306	* CR2 AUTOEND LL_I2C_HandleTransfer\n
EricLew	0:80ee8f3b695e	1307	* CR2 HEAD10R LL_I2C_HandleTransfer
EricLew	0:80ee8f3b695e	1308	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1309	* @param SlaveAddr Specifies the slave address to be programmed.
EricLew	0:80ee8f3b695e	1310	* @param SlaveAddrSize This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1311	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
EricLew	0:80ee8f3b695e	1312	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
EricLew	0:80ee8f3b695e	1313	* @param TransferSize Specifies the number of bytes to be programmed. This parameter must be a value between 0 and 255.
EricLew	0:80ee8f3b695e	1314	* @param EndMode This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1315	* @arg @ref LL_I2C_MODE_RELOAD
EricLew	0:80ee8f3b695e	1316	* @arg @ref LL_I2C_MODE_AUTOEND
EricLew	0:80ee8f3b695e	1317	* @arg @ref LL_I2C_MODE_SOFTEND
EricLew	0:80ee8f3b695e	1318	* @param Request This parameter can be one of the following values:
EricLew	0:80ee8f3b695e	1319	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
EricLew	0:80ee8f3b695e	1320	* @arg @ref LL_I2C_GENERATE_STOP
EricLew	0:80ee8f3b695e	1321	* @arg @ref LL_I2C_GENERATE_START_READ
EricLew	0:80ee8f3b695e	1322	* @arg @ref LL_I2C_GENERATE_START_WRITE
EricLew	0:80ee8f3b695e	1323	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
EricLew	0:80ee8f3b695e	1324	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
EricLew	0:80ee8f3b695e	1325	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
EricLew	0:80ee8f3b695e	1326	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
EricLew	0:80ee8f3b695e	1327	* @retval None
EricLew	0:80ee8f3b695e	1328	*/
EricLew	0:80ee8f3b695e	1329	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef* I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
EricLew	0:80ee8f3b695e	1330	{
EricLew	0:80ee8f3b695e	1331	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \| I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
EricLew	0:80ee8f3b695e	1332	SlaveAddr \| SlaveAddrSize \| TransferSize << POSITION_VAL(I2C_CR2_NBYTES) \| EndMode \| Request);
EricLew	0:80ee8f3b695e	1333	}
EricLew	0:80ee8f3b695e	1334
EricLew	0:80ee8f3b695e	1335	/**
EricLew	0:80ee8f3b695e	1336	* @brief Indicate the value of transfer direction (slave mode).
EricLew	0:80ee8f3b695e	1337	* RESET: Write transfer, Slave enters in receiver mode.
EricLew	0:80ee8f3b695e	1338	* SET: Read transfer, Slave enters in transmitter mode.
EricLew	0:80ee8f3b695e	1339	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
EricLew	0:80ee8f3b695e	1340	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1341	* @retval Returned value can be one of the following values:
EricLew	0:80ee8f3b695e	1342	* @arg @ref LL_I2C_DIRECTION_WRITE
EricLew	0:80ee8f3b695e	1343	* @arg @ref LL_I2C_DIRECTION_READ
EricLew	0:80ee8f3b695e	1344	*/
EricLew	0:80ee8f3b695e	1345	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1346	{
EricLew	0:80ee8f3b695e	1347	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
EricLew	0:80ee8f3b695e	1348	}
EricLew	0:80ee8f3b695e	1349
EricLew	0:80ee8f3b695e	1350	/**
EricLew	0:80ee8f3b695e	1351	* @brief Return the slave matched address.
EricLew	0:80ee8f3b695e	1352	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
EricLew	0:80ee8f3b695e	1353	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1354	* @retval 0..0x3F
EricLew	0:80ee8f3b695e	1355	*/
EricLew	0:80ee8f3b695e	1356	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1357	{
EricLew	0:80ee8f3b695e	1358	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> POSITION_VAL(I2C_ISR_ADDCODE) << 1);
EricLew	0:80ee8f3b695e	1359	}
EricLew	0:80ee8f3b695e	1360
EricLew	0:80ee8f3b695e	1361	/**
EricLew	0:80ee8f3b695e	1362	* @brief Read Receive Data register.
EricLew	0:80ee8f3b695e	1363	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
EricLew	0:80ee8f3b695e	1364	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1365	* @retval 0..0xFF
EricLew	0:80ee8f3b695e	1366	*/
EricLew	0:80ee8f3b695e	1367	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef* I2Cx)
EricLew	0:80ee8f3b695e	1368	{
EricLew	0:80ee8f3b695e	1369	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
EricLew	0:80ee8f3b695e	1370	}
EricLew	0:80ee8f3b695e	1371
EricLew	0:80ee8f3b695e	1372	/**
EricLew	0:80ee8f3b695e	1373	* @brief Write in Transmit Data Register .
EricLew	0:80ee8f3b695e	1374	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
EricLew	0:80ee8f3b695e	1375	* @param I2Cx I2C Instance.
EricLew	0:80ee8f3b695e	1376	* @param Data 0..0xFF
EricLew	0:80ee8f3b695e	1377	* @retval None
EricLew	0:80ee8f3b695e	1378	*/
EricLew	0:80ee8f3b695e	1379	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef* I2Cx, uint8_t Data)
EricLew	0:80ee8f3b695e	1380	{
EricLew	0:80ee8f3b695e	1381	WRITE_REG(I2Cx->TXDR, Data);
EricLew	0:80ee8f3b695e	1382	}
EricLew	0:80ee8f3b695e	1383
EricLew	0:80ee8f3b695e	1384	/**
EricLew	0:80ee8f3b695e	1385	* @}
EricLew	0:80ee8f3b695e	1386	*/
EricLew	0:80ee8f3b695e	1387
EricLew	0:80ee8f3b695e	1388
EricLew	0:80ee8f3b695e	1389	/**
EricLew	0:80ee8f3b695e	1390	* @}
EricLew	0:80ee8f3b695e	1391	*/
EricLew	0:80ee8f3b695e	1392
EricLew	0:80ee8f3b695e	1393	/**
EricLew	0:80ee8f3b695e	1394	* @}
EricLew	0:80ee8f3b695e	1395	*/
EricLew	0:80ee8f3b695e	1396
EricLew	0:80ee8f3b695e	1397	#endif /* I2C1 \|\| I2C2 \|\| I2C3 */
EricLew	0:80ee8f3b695e	1398
EricLew	0:80ee8f3b695e	1399	/**
EricLew	0:80ee8f3b695e	1400	* @}
EricLew	0:80ee8f3b695e	1401	*/
EricLew	0:80ee8f3b695e	1402
EricLew	0:80ee8f3b695e	1403	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	1404	}
EricLew	0:80ee8f3b695e	1405	#endif
EricLew	0:80ee8f3b695e	1406
EricLew	0:80ee8f3b695e	1407	#endif /* __STM32L4xx_LL_I2C_H */
EricLew	0:80ee8f3b695e	1408
EricLew	0:80ee8f3b695e	1409	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	1410

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_i2c.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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