STM32L4xx_HAL_Driver - Hal Drivers for L4

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Hal Drivers for L4

Dependents: BSP OneHopeOnePrayer FINAL_AUDIO_RECORD AudioDemo

Fork of STM32L4xx_HAL_Driver by Senior Design: Sound Monitor

Inc/stm32l4xx_ll_bus.h@2:7aef7655b0a8, 2015-11-25 (annotated)

Committer:: EricLew
Date:: Wed Nov 25 17:30:43 2015 +0000
Revision:: 2:7aef7655b0a8
Parent:: 0:80ee8f3b695e

commit;

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User	Revision	Line number	New contents of line
EricLew	0:80ee8f3b695e	1	/**
EricLew	0:80ee8f3b695e	2	******************************************************************************
EricLew	0:80ee8f3b695e	3	* @file stm32l4xx_ll_bus.h
EricLew	0:80ee8f3b695e	4	* @author MCD Application Team
EricLew	0:80ee8f3b695e	5	* @version V1.1.0
EricLew	0:80ee8f3b695e	6	* @date 16-September-2015
EricLew	0:80ee8f3b695e	7	* @brief Header file of BUS LL module.
EricLew	0:80ee8f3b695e	8	******************************************************************************
EricLew	0:80ee8f3b695e	9	* @attention
EricLew	0:80ee8f3b695e	10	*
EricLew	0:80ee8f3b695e	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:80ee8f3b695e	12	*
EricLew	0:80ee8f3b695e	13	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:80ee8f3b695e	14	* are permitted provided that the following conditions are met:
EricLew	0:80ee8f3b695e	15	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:80ee8f3b695e	16	* this list of conditions and the following disclaimer.
EricLew	0:80ee8f3b695e	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:80ee8f3b695e	18	* this list of conditions and the following disclaimer in the documentation
EricLew	0:80ee8f3b695e	19	* and/or other materials provided with the distribution.
EricLew	0:80ee8f3b695e	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:80ee8f3b695e	21	* may be used to endorse or promote products derived from this software
EricLew	0:80ee8f3b695e	22	* without specific prior written permission.
EricLew	0:80ee8f3b695e	23	*
EricLew	0:80ee8f3b695e	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:80ee8f3b695e	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:80ee8f3b695e	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:80ee8f3b695e	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:80ee8f3b695e	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:80ee8f3b695e	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:80ee8f3b695e	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:80ee8f3b695e	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:80ee8f3b695e	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:80ee8f3b695e	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:80ee8f3b695e	34	*
EricLew	0:80ee8f3b695e	35	******************************************************************************
EricLew	0:80ee8f3b695e	36	*/
EricLew	0:80ee8f3b695e	37
EricLew	0:80ee8f3b695e	38	/* Define to prevent recursive inclusion -------------------------------------*/
EricLew	0:80ee8f3b695e	39	#ifndef __STM32L4xx_LL_BUS_H
EricLew	0:80ee8f3b695e	40	#define __STM32L4xx_LL_BUS_H
EricLew	0:80ee8f3b695e	41
EricLew	0:80ee8f3b695e	42	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	43	extern "C" {
EricLew	0:80ee8f3b695e	44	#endif
EricLew	0:80ee8f3b695e	45
EricLew	0:80ee8f3b695e	46	/* Includes ------------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	47	#include "stm32l4xx.h"
EricLew	0:80ee8f3b695e	48
EricLew	0:80ee8f3b695e	49	/** @addtogroup STM32L4xx_LL_Driver
EricLew	0:80ee8f3b695e	50	* @{
EricLew	0:80ee8f3b695e	51	*/
EricLew	0:80ee8f3b695e	52
EricLew	0:80ee8f3b695e	53	#if defined(RCC)
EricLew	0:80ee8f3b695e	54
EricLew	0:80ee8f3b695e	55	/** @defgroup BUS_LL BUS
EricLew	0:80ee8f3b695e	56	* @{
EricLew	0:80ee8f3b695e	57	*/
EricLew	0:80ee8f3b695e	58
EricLew	0:80ee8f3b695e	59	/* Private types -------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	60	/* Private variables ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	61
EricLew	0:80ee8f3b695e	62	/* Private constants ---------------------------------------------------------*/
EricLew	0:80ee8f3b695e	63
EricLew	0:80ee8f3b695e	64	/* Private macros ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	65
EricLew	0:80ee8f3b695e	66	/* Exported types ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	67	/* Exported constants --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	68	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
EricLew	0:80ee8f3b695e	69	* @{
EricLew	0:80ee8f3b695e	70	*/
EricLew	0:80ee8f3b695e	71
EricLew	0:80ee8f3b695e	72	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
EricLew	0:80ee8f3b695e	73	* @{
EricLew	0:80ee8f3b695e	74	*/
EricLew	0:80ee8f3b695e	75	#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	76	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
EricLew	0:80ee8f3b695e	77	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
EricLew	0:80ee8f3b695e	78	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
EricLew	0:80ee8f3b695e	79	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
EricLew	0:80ee8f3b695e	80	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
EricLew	0:80ee8f3b695e	81	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
EricLew	0:80ee8f3b695e	82	/**
EricLew	0:80ee8f3b695e	83	* @}
EricLew	0:80ee8f3b695e	84	*/
EricLew	0:80ee8f3b695e	85
EricLew	0:80ee8f3b695e	86	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
EricLew	0:80ee8f3b695e	87	* @{
EricLew	0:80ee8f3b695e	88	*/
EricLew	0:80ee8f3b695e	89	#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
EricLew	0:80ee8f3b695e	90	#define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	91	#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
EricLew	0:80ee8f3b695e	92	#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
EricLew	0:80ee8f3b695e	93	#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
EricLew	0:80ee8f3b695e	94	#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
EricLew	0:80ee8f3b695e	95	#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
EricLew	0:80ee8f3b695e	96	#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
EricLew	0:80ee8f3b695e	97	#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
EricLew	0:80ee8f3b695e	98	#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
EricLew	0:80ee8f3b695e	99	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
EricLew	0:80ee8f3b695e	100	#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
EricLew	0:80ee8f3b695e	101	#if defined(AES)
EricLew	0:80ee8f3b695e	102	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
EricLew	0:80ee8f3b695e	103	#endif
EricLew	0:80ee8f3b695e	104	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
EricLew	0:80ee8f3b695e	105	/**
EricLew	0:80ee8f3b695e	106	* @}
EricLew	0:80ee8f3b695e	107	*/
EricLew	0:80ee8f3b695e	108
EricLew	0:80ee8f3b695e	109	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
EricLew	0:80ee8f3b695e	110	* @{
EricLew	0:80ee8f3b695e	111	*/
EricLew	0:80ee8f3b695e	112	#define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	113	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
EricLew	0:80ee8f3b695e	114	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
EricLew	0:80ee8f3b695e	115	/**
EricLew	0:80ee8f3b695e	116	* @}
EricLew	0:80ee8f3b695e	117	*/
EricLew	0:80ee8f3b695e	118
EricLew	0:80ee8f3b695e	119	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
EricLew	0:80ee8f3b695e	120	* @{
EricLew	0:80ee8f3b695e	121	*/
EricLew	0:80ee8f3b695e	122	#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	123	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
EricLew	0:80ee8f3b695e	124	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
EricLew	0:80ee8f3b695e	125	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
EricLew	0:80ee8f3b695e	126	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
EricLew	0:80ee8f3b695e	127	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
EricLew	0:80ee8f3b695e	128	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
EricLew	0:80ee8f3b695e	129	#if defined(LCD)
EricLew	0:80ee8f3b695e	130	#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
EricLew	0:80ee8f3b695e	131	#endif
EricLew	0:80ee8f3b695e	132	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
EricLew	0:80ee8f3b695e	133	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
EricLew	0:80ee8f3b695e	134	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
EricLew	0:80ee8f3b695e	135	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
EricLew	0:80ee8f3b695e	136	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
EricLew	0:80ee8f3b695e	137	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
EricLew	0:80ee8f3b695e	138	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
EricLew	0:80ee8f3b695e	139	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
EricLew	0:80ee8f3b695e	140	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
EricLew	0:80ee8f3b695e	141	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
EricLew	0:80ee8f3b695e	142	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
EricLew	0:80ee8f3b695e	143	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
EricLew	0:80ee8f3b695e	144	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
EricLew	0:80ee8f3b695e	145	#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
EricLew	0:80ee8f3b695e	146	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
EricLew	0:80ee8f3b695e	147	/**
EricLew	0:80ee8f3b695e	148	* @}
EricLew	0:80ee8f3b695e	149	*/
EricLew	0:80ee8f3b695e	150
EricLew	0:80ee8f3b695e	151
EricLew	0:80ee8f3b695e	152	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
EricLew	0:80ee8f3b695e	153	* @{
EricLew	0:80ee8f3b695e	154	*/
EricLew	0:80ee8f3b695e	155	#define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	156	#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
EricLew	0:80ee8f3b695e	157	#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
EricLew	0:80ee8f3b695e	158	#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
EricLew	0:80ee8f3b695e	159	/**
EricLew	0:80ee8f3b695e	160	* @}
EricLew	0:80ee8f3b695e	161	*/
EricLew	0:80ee8f3b695e	162
EricLew	0:80ee8f3b695e	163	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
EricLew	0:80ee8f3b695e	164	* @{
EricLew	0:80ee8f3b695e	165	*/
EricLew	0:80ee8f3b695e	166	#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFF
EricLew	0:80ee8f3b695e	167	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
EricLew	0:80ee8f3b695e	168	#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
EricLew	0:80ee8f3b695e	169	#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
EricLew	0:80ee8f3b695e	170	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
EricLew	0:80ee8f3b695e	171	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
EricLew	0:80ee8f3b695e	172	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
EricLew	0:80ee8f3b695e	173	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
EricLew	0:80ee8f3b695e	174	#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
EricLew	0:80ee8f3b695e	175	#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
EricLew	0:80ee8f3b695e	176	#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
EricLew	0:80ee8f3b695e	177	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
EricLew	0:80ee8f3b695e	178	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
EricLew	0:80ee8f3b695e	179	#define LL_APB2_GRP1_PERIPH_DFSDM RCC_APB2ENR_DFSDMEN
EricLew	0:80ee8f3b695e	180	/**
EricLew	0:80ee8f3b695e	181	* @}
EricLew	0:80ee8f3b695e	182	*/
EricLew	0:80ee8f3b695e	183
EricLew	0:80ee8f3b695e	184	/**
EricLew	0:80ee8f3b695e	185	* @}
EricLew	0:80ee8f3b695e	186	*/
EricLew	0:80ee8f3b695e	187
EricLew	0:80ee8f3b695e	188	/* Exported macro ------------------------------------------------------------*/
EricLew	0:80ee8f3b695e	189	/* Exported functions --------------------------------------------------------*/
EricLew	0:80ee8f3b695e	190	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
EricLew	0:80ee8f3b695e	191	* @{
EricLew	0:80ee8f3b695e	192	*/
EricLew	0:80ee8f3b695e	193
EricLew	0:80ee8f3b695e	194	/** @defgroup BUS_LL_EF_AHB1 AHB1
EricLew	0:80ee8f3b695e	195	* @{
EricLew	0:80ee8f3b695e	196	*/
EricLew	0:80ee8f3b695e	197
EricLew	0:80ee8f3b695e	198	/**
EricLew	0:80ee8f3b695e	199	* @brief Enable AHB1 peripherals clock.
EricLew	0:80ee8f3b695e	200	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	201	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	202	* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	203	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	204	* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock
EricLew	0:80ee8f3b695e	205	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	206	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	207	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	208	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	209	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	210	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	211	* @retval None
EricLew	0:80ee8f3b695e	212	*/
EricLew	0:80ee8f3b695e	213	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	214	{
EricLew	0:80ee8f3b695e	215	SET_BIT(RCC->AHB1ENR, Periphs);
EricLew	0:80ee8f3b695e	216	}
EricLew	0:80ee8f3b695e	217
EricLew	0:80ee8f3b695e	218	/**
EricLew	0:80ee8f3b695e	219	* @brief Check if AHB1 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	220	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	221	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	222	* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	223	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	224	* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock
EricLew	0:80ee8f3b695e	225	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	226	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	227	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	228	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	229	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	230	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	231	* @retval uint32_t
EricLew	0:80ee8f3b695e	232	*/
EricLew	0:80ee8f3b695e	233	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	234	{
EricLew	0:80ee8f3b695e	235	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	236	}
EricLew	0:80ee8f3b695e	237
EricLew	0:80ee8f3b695e	238	/**
EricLew	0:80ee8f3b695e	239	* @brief Disable AHB1 peripherals clock.
EricLew	0:80ee8f3b695e	240	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	241	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	242	* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	243	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	244	* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock
EricLew	0:80ee8f3b695e	245	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	246	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	247	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	248	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	249	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	250	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	251	* @retval None
EricLew	0:80ee8f3b695e	252	*/
EricLew	0:80ee8f3b695e	253	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	254	{
EricLew	0:80ee8f3b695e	255	CLEAR_BIT(RCC->AHB1ENR, Periphs);
EricLew	0:80ee8f3b695e	256	}
EricLew	0:80ee8f3b695e	257
EricLew	0:80ee8f3b695e	258	/**
EricLew	0:80ee8f3b695e	259	* @brief Force AHB1 peripherals reset.
EricLew	0:80ee8f3b695e	260	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	261	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	262	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	263	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	264	* AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset
EricLew	0:80ee8f3b695e	265	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	266	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	267	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	268	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	269	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	270	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	271	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	272	* @retval None
EricLew	0:80ee8f3b695e	273	*/
EricLew	0:80ee8f3b695e	274	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	275	{
EricLew	0:80ee8f3b695e	276	SET_BIT(RCC->AHB1RSTR, Periphs);
EricLew	0:80ee8f3b695e	277	}
EricLew	0:80ee8f3b695e	278
EricLew	0:80ee8f3b695e	279	/**
EricLew	0:80ee8f3b695e	280	* @brief Release AHB1 peripherals reset.
EricLew	0:80ee8f3b695e	281	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	282	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	283	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	284	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	285	* AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset
EricLew	0:80ee8f3b695e	286	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	287	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	288	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	289	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	290	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	291	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	292	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	293	* @retval None
EricLew	0:80ee8f3b695e	294	*/
EricLew	0:80ee8f3b695e	295	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	296	{
EricLew	0:80ee8f3b695e	297	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
EricLew	0:80ee8f3b695e	298	}
EricLew	0:80ee8f3b695e	299
EricLew	0:80ee8f3b695e	300	/**
EricLew	0:80ee8f3b695e	301	* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	302	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	303	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	304	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	305	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	306	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	307	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep
EricLew	0:80ee8f3b695e	308	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	309	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	310	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	311	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	312	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
EricLew	0:80ee8f3b695e	313	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	314	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	315	* @retval None
EricLew	0:80ee8f3b695e	316	*/
EricLew	0:80ee8f3b695e	317	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	318	{
EricLew	0:80ee8f3b695e	319	SET_BIT(RCC->AHB1SMENR, Periphs);
EricLew	0:80ee8f3b695e	320	}
EricLew	0:80ee8f3b695e	321
EricLew	0:80ee8f3b695e	322	/**
EricLew	0:80ee8f3b695e	323	* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	324	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	325	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	326	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	327	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	328	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	329	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep
EricLew	0:80ee8f3b695e	330	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	331	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
EricLew	0:80ee8f3b695e	332	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
EricLew	0:80ee8f3b695e	333	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
EricLew	0:80ee8f3b695e	334	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
EricLew	0:80ee8f3b695e	335	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
EricLew	0:80ee8f3b695e	336	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
EricLew	0:80ee8f3b695e	337	* @retval None
EricLew	0:80ee8f3b695e	338	*/
EricLew	0:80ee8f3b695e	339	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	340	{
EricLew	0:80ee8f3b695e	341	CLEAR_BIT(RCC->AHB1SMENR, Periphs);
EricLew	0:80ee8f3b695e	342	}
EricLew	0:80ee8f3b695e	343
EricLew	0:80ee8f3b695e	344	/**
EricLew	0:80ee8f3b695e	345	* @}
EricLew	0:80ee8f3b695e	346	*/
EricLew	0:80ee8f3b695e	347
EricLew	0:80ee8f3b695e	348	/** @defgroup BUS_LL_EF_AHB2 AHB2
EricLew	0:80ee8f3b695e	349	* @{
EricLew	0:80ee8f3b695e	350	*/
EricLew	0:80ee8f3b695e	351
EricLew	0:80ee8f3b695e	352	/**
EricLew	0:80ee8f3b695e	353	* @brief Enable AHB2 peripherals clock.
EricLew	0:80ee8f3b695e	354	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	355	* AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	356	* AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	357	* AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	358	* AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	359	* AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	360	* AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	361	* AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	362	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	363	* AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	364	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	365	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
EricLew	0:80ee8f3b695e	366	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	367	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	368	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	369	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	370	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	371	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	372	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	373	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	374	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	375	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	376	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	377	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	378	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	379	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	380	* @retval None
EricLew	0:80ee8f3b695e	381	*/
EricLew	0:80ee8f3b695e	382	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	383	{
EricLew	0:80ee8f3b695e	384	SET_BIT(RCC->AHB2ENR, Periphs);
EricLew	0:80ee8f3b695e	385	}
EricLew	0:80ee8f3b695e	386
EricLew	0:80ee8f3b695e	387	/**
EricLew	0:80ee8f3b695e	388	* @brief Check if AHB2 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	389	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	390	* AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	391	* AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	392	* AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	393	* AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	394	* AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	395	* AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	396	* AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	397	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	398	* AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	399	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	400	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
EricLew	0:80ee8f3b695e	401	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	402	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	403	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	404	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	405	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	406	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	407	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	408	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	409	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	410	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	411	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	412	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	413	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	414	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	415	* @retval uint32_t
EricLew	0:80ee8f3b695e	416	*/
EricLew	0:80ee8f3b695e	417	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	418	{
EricLew	0:80ee8f3b695e	419	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	420	}
EricLew	0:80ee8f3b695e	421
EricLew	0:80ee8f3b695e	422	/**
EricLew	0:80ee8f3b695e	423	* @brief Disable AHB2 peripherals clock.
EricLew	0:80ee8f3b695e	424	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	425	* AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	426	* AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	427	* AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	428	* AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	429	* AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	430	* AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	431	* AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	432	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	433	* AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	434	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	435	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
EricLew	0:80ee8f3b695e	436	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	437	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	438	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	439	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	440	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	441	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	442	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	443	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	444	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	445	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	446	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	447	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	448	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	449	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	450	* @retval None
EricLew	0:80ee8f3b695e	451	*/
EricLew	0:80ee8f3b695e	452	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	453	{
EricLew	0:80ee8f3b695e	454	CLEAR_BIT(RCC->AHB2ENR, Periphs);
EricLew	0:80ee8f3b695e	455	}
EricLew	0:80ee8f3b695e	456
EricLew	0:80ee8f3b695e	457	/**
EricLew	0:80ee8f3b695e	458	* @brief Force AHB2 peripherals reset.
EricLew	0:80ee8f3b695e	459	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	460	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	461	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	462	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	463	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	464	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	465	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	466	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	467	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	468	* AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	469	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	470	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
EricLew	0:80ee8f3b695e	471	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	472	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	473	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	474	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	475	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	476	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	477	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	478	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	479	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	480	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	481	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	482	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	483	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	484	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	485	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	486	* @retval None
EricLew	0:80ee8f3b695e	487	*/
EricLew	0:80ee8f3b695e	488	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	489	{
EricLew	0:80ee8f3b695e	490	SET_BIT(RCC->AHB2RSTR, Periphs);
EricLew	0:80ee8f3b695e	491	}
EricLew	0:80ee8f3b695e	492
EricLew	0:80ee8f3b695e	493	/**
EricLew	0:80ee8f3b695e	494	* @brief Release AHB2 peripherals reset.
EricLew	0:80ee8f3b695e	495	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	496	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	497	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	498	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	499	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	500	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	501	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	502	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	503	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	504	* AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	505	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	506	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
EricLew	0:80ee8f3b695e	507	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	508	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	509	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	510	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	511	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	512	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	513	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	514	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	515	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	516	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	517	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	518	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	519	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	520	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	521	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	522	* @retval None
EricLew	0:80ee8f3b695e	523	*/
EricLew	0:80ee8f3b695e	524	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	525	{
EricLew	0:80ee8f3b695e	526	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
EricLew	0:80ee8f3b695e	527	}
EricLew	0:80ee8f3b695e	528
EricLew	0:80ee8f3b695e	529	/**
EricLew	0:80ee8f3b695e	530	* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	531	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	532	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	533	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	534	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	535	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	536	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	537	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	538	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	539	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	540	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	541	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	542	* AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	543	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
EricLew	0:80ee8f3b695e	544	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	545	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	546	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	547	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	548	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	549	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	550	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	551	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	552	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	553	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
EricLew	0:80ee8f3b695e	554	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	555	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	556	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	557	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	558	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	559	* @retval None
EricLew	0:80ee8f3b695e	560	*/
EricLew	0:80ee8f3b695e	561	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	562	{
EricLew	0:80ee8f3b695e	563	SET_BIT(RCC->AHB2SMENR, Periphs);
EricLew	0:80ee8f3b695e	564	}
EricLew	0:80ee8f3b695e	565
EricLew	0:80ee8f3b695e	566	/**
EricLew	0:80ee8f3b695e	567	* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	568	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	569	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	570	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	571	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	572	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	573	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	574	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	575	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	576	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	577	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	578	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	579	* AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	580	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
EricLew	0:80ee8f3b695e	581	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	582	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
EricLew	0:80ee8f3b695e	583	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
EricLew	0:80ee8f3b695e	584	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
EricLew	0:80ee8f3b695e	585	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
EricLew	0:80ee8f3b695e	586	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
EricLew	0:80ee8f3b695e	587	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
EricLew	0:80ee8f3b695e	588	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
EricLew	0:80ee8f3b695e	589	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
EricLew	0:80ee8f3b695e	590	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
EricLew	0:80ee8f3b695e	591	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
EricLew	0:80ee8f3b695e	592	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
EricLew	0:80ee8f3b695e	593	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
EricLew	0:80ee8f3b695e	594	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
EricLew	0:80ee8f3b695e	595	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	596	* @retval None
EricLew	0:80ee8f3b695e	597	*/
EricLew	0:80ee8f3b695e	598	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	599	{
EricLew	0:80ee8f3b695e	600	CLEAR_BIT(RCC->AHB2SMENR, Periphs);
EricLew	0:80ee8f3b695e	601	}
EricLew	0:80ee8f3b695e	602
EricLew	0:80ee8f3b695e	603	/**
EricLew	0:80ee8f3b695e	604	* @}
EricLew	0:80ee8f3b695e	605	*/
EricLew	0:80ee8f3b695e	606
EricLew	0:80ee8f3b695e	607	/** @defgroup BUS_LL_EF_AHB3 AHB3
EricLew	0:80ee8f3b695e	608	* @{
EricLew	0:80ee8f3b695e	609	*/
EricLew	0:80ee8f3b695e	610
EricLew	0:80ee8f3b695e	611	/**
EricLew	0:80ee8f3b695e	612	* @brief Enable AHB3 peripherals clock.
EricLew	0:80ee8f3b695e	613	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	614	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
EricLew	0:80ee8f3b695e	615	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	616	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	617	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	618	* @retval None
EricLew	0:80ee8f3b695e	619	*/
EricLew	0:80ee8f3b695e	620	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	621	{
EricLew	0:80ee8f3b695e	622	SET_BIT(RCC->AHB3ENR, Periphs);
EricLew	0:80ee8f3b695e	623	}
EricLew	0:80ee8f3b695e	624
EricLew	0:80ee8f3b695e	625	/**
EricLew	0:80ee8f3b695e	626	* @brief Check if AHB3 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	627	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	628	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
EricLew	0:80ee8f3b695e	629	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	630	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	631	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	632	* @retval uint32_t
EricLew	0:80ee8f3b695e	633	*/
EricLew	0:80ee8f3b695e	634	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	635	{
EricLew	0:80ee8f3b695e	636	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	637	}
EricLew	0:80ee8f3b695e	638
EricLew	0:80ee8f3b695e	639	/**
EricLew	0:80ee8f3b695e	640	* @brief Disable AHB3 peripherals clock.
EricLew	0:80ee8f3b695e	641	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	642	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
EricLew	0:80ee8f3b695e	643	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	644	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	645	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	646	* @retval None
EricLew	0:80ee8f3b695e	647	*/
EricLew	0:80ee8f3b695e	648	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	649	{
EricLew	0:80ee8f3b695e	650	CLEAR_BIT(RCC->AHB3ENR, Periphs);
EricLew	0:80ee8f3b695e	651	}
EricLew	0:80ee8f3b695e	652
EricLew	0:80ee8f3b695e	653	/**
EricLew	0:80ee8f3b695e	654	* @brief Force AHB3 peripherals reset.
EricLew	0:80ee8f3b695e	655	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	656	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
EricLew	0:80ee8f3b695e	657	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	658	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	659	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	660	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	661	* @retval None
EricLew	0:80ee8f3b695e	662	*/
EricLew	0:80ee8f3b695e	663	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	664	{
EricLew	0:80ee8f3b695e	665	SET_BIT(RCC->AHB3RSTR, Periphs);
EricLew	0:80ee8f3b695e	666	}
EricLew	0:80ee8f3b695e	667
EricLew	0:80ee8f3b695e	668	/**
EricLew	0:80ee8f3b695e	669	* @brief Release AHB3 peripherals reset.
EricLew	0:80ee8f3b695e	670	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	671	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
EricLew	0:80ee8f3b695e	672	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	673	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	674	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	675	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	676	* @retval None
EricLew	0:80ee8f3b695e	677	*/
EricLew	0:80ee8f3b695e	678	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	679	{
EricLew	0:80ee8f3b695e	680	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
EricLew	0:80ee8f3b695e	681	}
EricLew	0:80ee8f3b695e	682
EricLew	0:80ee8f3b695e	683	/**
EricLew	0:80ee8f3b695e	684	* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	685	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	686	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
EricLew	0:80ee8f3b695e	687	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	688	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	689	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	690	* @retval None
EricLew	0:80ee8f3b695e	691	*/
EricLew	0:80ee8f3b695e	692	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	693	{
EricLew	0:80ee8f3b695e	694	SET_BIT(RCC->AHB3SMENR, Periphs);
EricLew	0:80ee8f3b695e	695	}
EricLew	0:80ee8f3b695e	696
EricLew	0:80ee8f3b695e	697	/**
EricLew	0:80ee8f3b695e	698	* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	699	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	700	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
EricLew	0:80ee8f3b695e	701	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	702	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC
EricLew	0:80ee8f3b695e	703	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
EricLew	0:80ee8f3b695e	704	* @retval None
EricLew	0:80ee8f3b695e	705	*/
EricLew	0:80ee8f3b695e	706	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	707	{
EricLew	0:80ee8f3b695e	708	CLEAR_BIT(RCC->AHB3SMENR, Periphs);
EricLew	0:80ee8f3b695e	709	}
EricLew	0:80ee8f3b695e	710
EricLew	0:80ee8f3b695e	711	/**
EricLew	0:80ee8f3b695e	712	* @}
EricLew	0:80ee8f3b695e	713	*/
EricLew	0:80ee8f3b695e	714
EricLew	0:80ee8f3b695e	715	/** @defgroup BUS_LL_EF_APB1 APB1
EricLew	0:80ee8f3b695e	716	* @{
EricLew	0:80ee8f3b695e	717	*/
EricLew	0:80ee8f3b695e	718
EricLew	0:80ee8f3b695e	719	/**
EricLew	0:80ee8f3b695e	720	* @brief Enable APB1 peripherals clock.
EricLew	0:80ee8f3b695e	721	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	722	* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	723	* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	724	* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	725	* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	726	* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	727	* APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	728	* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	729	* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	730	* APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	731	* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	732	* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	733	* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	734	* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	735	* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	736	* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	737	* APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	738	* APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	739	* APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	740	* APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	741	* APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	742	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
EricLew	0:80ee8f3b695e	743	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	744	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	745	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	746	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	747	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	748	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	749	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	750	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	751	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
EricLew	0:80ee8f3b695e	752	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	753	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	754	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	755	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	756	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	757	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	758	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	759	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	760	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	761	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	762	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	763	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	764	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	765	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	766	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	767	* @retval None
EricLew	0:80ee8f3b695e	768	*/
EricLew	0:80ee8f3b695e	769	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	770	{
EricLew	0:80ee8f3b695e	771	SET_BIT(RCC->APB1ENR1, Periphs);
EricLew	0:80ee8f3b695e	772	}
EricLew	0:80ee8f3b695e	773
EricLew	0:80ee8f3b695e	774	/**
EricLew	0:80ee8f3b695e	775	* @brief Enable APB1 peripherals clock.
EricLew	0:80ee8f3b695e	776	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
EricLew	0:80ee8f3b695e	777	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
EricLew	0:80ee8f3b695e	778	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
EricLew	0:80ee8f3b695e	779	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	780	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	781	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	782	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	783	* @retval None
EricLew	0:80ee8f3b695e	784	*/
EricLew	0:80ee8f3b695e	785	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	786	{
EricLew	0:80ee8f3b695e	787	SET_BIT(RCC->APB1ENR2, Periphs);
EricLew	0:80ee8f3b695e	788	}
EricLew	0:80ee8f3b695e	789
EricLew	0:80ee8f3b695e	790	/**
EricLew	0:80ee8f3b695e	791	* @brief Check if APB1 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	792	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	793	* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	794	* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	795	* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	796	* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	797	* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	798	* APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	799	* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	800	* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	801	* APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	802	* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	803	* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	804	* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	805	* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	806	* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	807	* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	808	* APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	809	* APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	810	* APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	811	* APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	812	* APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	813	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
EricLew	0:80ee8f3b695e	814	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	815	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	816	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	817	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	818	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	819	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	820	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	821	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	822	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
EricLew	0:80ee8f3b695e	823	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	824	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	825	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	826	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	827	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	828	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	829	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	830	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	831	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	832	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	833	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	834	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	835	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	836	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	837	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	838	* @retval uint32_t
EricLew	0:80ee8f3b695e	839	*/
EricLew	0:80ee8f3b695e	840	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	841	{
EricLew	0:80ee8f3b695e	842	return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	843	}
EricLew	0:80ee8f3b695e	844
EricLew	0:80ee8f3b695e	845	/**
EricLew	0:80ee8f3b695e	846	* @brief Check if APB1 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	847	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
EricLew	0:80ee8f3b695e	848	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
EricLew	0:80ee8f3b695e	849	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
EricLew	0:80ee8f3b695e	850	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	851	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	852	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	853	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	854	* @retval uint32_t
EricLew	0:80ee8f3b695e	855	*/
EricLew	0:80ee8f3b695e	856	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	857	{
EricLew	0:80ee8f3b695e	858	return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	859	}
EricLew	0:80ee8f3b695e	860
EricLew	0:80ee8f3b695e	861	/**
EricLew	0:80ee8f3b695e	862	* @brief Disable APB1 peripherals clock.
EricLew	0:80ee8f3b695e	863	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	864	* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	865	* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	866	* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	867	* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	868	* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	869	* APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	870	* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	871	* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	872	* APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	873	* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	874	* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	875	* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	876	* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	877	* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	878	* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	879	* APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	880	* APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	881	* APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	882	* APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	883	* APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	884	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
EricLew	0:80ee8f3b695e	885	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	886	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	887	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	888	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	889	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	890	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	891	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	892	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	893	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
EricLew	0:80ee8f3b695e	894	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	895	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	896	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	897	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	898	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	899	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	900	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	901	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	902	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	903	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	904	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	905	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	906	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	907	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	908	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	909	* @retval None
EricLew	0:80ee8f3b695e	910	*/
EricLew	0:80ee8f3b695e	911	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	912	{
EricLew	0:80ee8f3b695e	913	CLEAR_BIT(RCC->APB1ENR1, Periphs);
EricLew	0:80ee8f3b695e	914	}
EricLew	0:80ee8f3b695e	915
EricLew	0:80ee8f3b695e	916	/**
EricLew	0:80ee8f3b695e	917	* @brief Disable APB1 peripherals clock.
EricLew	0:80ee8f3b695e	918	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
EricLew	0:80ee8f3b695e	919	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
EricLew	0:80ee8f3b695e	920	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
EricLew	0:80ee8f3b695e	921	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	922	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	923	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	924	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	925	* @retval None
EricLew	0:80ee8f3b695e	926	*/
EricLew	0:80ee8f3b695e	927	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	928	{
EricLew	0:80ee8f3b695e	929	CLEAR_BIT(RCC->APB1ENR2, Periphs);
EricLew	0:80ee8f3b695e	930	}
EricLew	0:80ee8f3b695e	931
EricLew	0:80ee8f3b695e	932	/**
EricLew	0:80ee8f3b695e	933	* @brief Force APB1 peripherals reset.
EricLew	0:80ee8f3b695e	934	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	935	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	936	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	937	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	938	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	939	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	940	* APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	941	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	942	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	943	* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	944	* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	945	* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	946	* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	947	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	948	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	949	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	950	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	951	* APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	952	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	953	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	954	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
EricLew	0:80ee8f3b695e	955	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	956	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	957	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	958	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	959	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	960	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	961	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	962	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	963	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	964	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	965	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	966	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	967	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	968	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	969	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	970	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	971	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	972	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	973	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	974	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	975	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	976	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	977	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	978	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	979	* @retval None
EricLew	0:80ee8f3b695e	980	*/
EricLew	0:80ee8f3b695e	981	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	982	{
EricLew	0:80ee8f3b695e	983	SET_BIT(RCC->APB1RSTR1, Periphs);
EricLew	0:80ee8f3b695e	984	}
EricLew	0:80ee8f3b695e	985
EricLew	0:80ee8f3b695e	986	/**
EricLew	0:80ee8f3b695e	987	* @brief Force APB1 peripherals reset.
EricLew	0:80ee8f3b695e	988	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
EricLew	0:80ee8f3b695e	989	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
EricLew	0:80ee8f3b695e	990	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
EricLew	0:80ee8f3b695e	991	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	992	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
EricLew	0:80ee8f3b695e	993	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	994	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	995	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	996	* @retval None
EricLew	0:80ee8f3b695e	997	*/
EricLew	0:80ee8f3b695e	998	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	999	{
EricLew	0:80ee8f3b695e	1000	SET_BIT(RCC->APB1RSTR2, Periphs);
EricLew	0:80ee8f3b695e	1001	}
EricLew	0:80ee8f3b695e	1002
EricLew	0:80ee8f3b695e	1003	/**
EricLew	0:80ee8f3b695e	1004	* @brief Release APB1 peripherals reset.
EricLew	0:80ee8f3b695e	1005	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1006	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1007	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1008	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1009	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1010	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1011	* APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1012	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1013	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1014	* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1015	* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1016	* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1017	* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1018	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1019	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1020	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1021	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1022	* APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1023	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1024	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1025	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
EricLew	0:80ee8f3b695e	1026	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1027	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	1028	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	1029	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	1030	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	1031	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	1032	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	1033	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	1034	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	1035	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	1036	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	1037	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	1038	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	1039	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	1040	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	1041	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	1042	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	1043	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	1044	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	1045	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	1046	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	1047	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	1048	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	1049	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	1050	* @retval None
EricLew	0:80ee8f3b695e	1051	*/
EricLew	0:80ee8f3b695e	1052	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1053	{
EricLew	0:80ee8f3b695e	1054	CLEAR_BIT(RCC->APB1RSTR1, Periphs);
EricLew	0:80ee8f3b695e	1055	}
EricLew	0:80ee8f3b695e	1056
EricLew	0:80ee8f3b695e	1057	/**
EricLew	0:80ee8f3b695e	1058	* @brief Release APB1 peripherals reset.
EricLew	0:80ee8f3b695e	1059	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
EricLew	0:80ee8f3b695e	1060	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
EricLew	0:80ee8f3b695e	1061	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
EricLew	0:80ee8f3b695e	1062	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1063	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
EricLew	0:80ee8f3b695e	1064	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	1065	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	1066	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	1067	* @retval None
EricLew	0:80ee8f3b695e	1068	*/
EricLew	0:80ee8f3b695e	1069	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1070	{
EricLew	0:80ee8f3b695e	1071	CLEAR_BIT(RCC->APB1RSTR2, Periphs);
EricLew	0:80ee8f3b695e	1072	}
EricLew	0:80ee8f3b695e	1073
EricLew	0:80ee8f3b695e	1074	/**
EricLew	0:80ee8f3b695e	1075	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1076	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1077	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1078	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1079	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1080	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1081	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1082	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1083	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1084	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1085	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1086	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1087	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1088	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1089	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1090	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1091	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1092	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1093	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1094	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1095	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1096	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1097	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
EricLew	0:80ee8f3b695e	1098	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1099	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	1100	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	1101	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	1102	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	1103	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	1104	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	1105	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	1106	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
EricLew	0:80ee8f3b695e	1107	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	1108	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	1109	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	1110	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	1111	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	1112	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	1113	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	1114	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	1115	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	1116	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	1117	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	1118	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	1119	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	1120	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	1121	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	1122	* @retval None
EricLew	0:80ee8f3b695e	1123	*/
EricLew	0:80ee8f3b695e	1124	__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1125	{
EricLew	0:80ee8f3b695e	1126	SET_BIT(RCC->APB1SMENR1, Periphs);
EricLew	0:80ee8f3b695e	1127	}
EricLew	0:80ee8f3b695e	1128
EricLew	0:80ee8f3b695e	1129	/**
EricLew	0:80ee8f3b695e	1130	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1131	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1132	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1133	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
EricLew	0:80ee8f3b695e	1134	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1135	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	1136	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	1137	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	1138	* @retval None
EricLew	0:80ee8f3b695e	1139	*/
EricLew	0:80ee8f3b695e	1140	__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1141	{
EricLew	0:80ee8f3b695e	1142	SET_BIT(RCC->APB1SMENR2, Periphs);
EricLew	0:80ee8f3b695e	1143	}
EricLew	0:80ee8f3b695e	1144
EricLew	0:80ee8f3b695e	1145	/**
EricLew	0:80ee8f3b695e	1146	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1147	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1148	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1149	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1150	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1151	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1152	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1153	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1154	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1155	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1156	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1157	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1158	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1159	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1160	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1161	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1162	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1163	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1164	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1165	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1166	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1167	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1168	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
EricLew	0:80ee8f3b695e	1169	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1170	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
EricLew	0:80ee8f3b695e	1171	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
EricLew	0:80ee8f3b695e	1172	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
EricLew	0:80ee8f3b695e	1173	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5
EricLew	0:80ee8f3b695e	1174	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
EricLew	0:80ee8f3b695e	1175	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
EricLew	0:80ee8f3b695e	1176	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
EricLew	0:80ee8f3b695e	1177	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
EricLew	0:80ee8f3b695e	1178	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
EricLew	0:80ee8f3b695e	1179	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
EricLew	0:80ee8f3b695e	1180	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
EricLew	0:80ee8f3b695e	1181	* @arg @ref LL_APB1_GRP1_PERIPH_USART3
EricLew	0:80ee8f3b695e	1182	* @arg @ref LL_APB1_GRP1_PERIPH_UART4
EricLew	0:80ee8f3b695e	1183	* @arg @ref LL_APB1_GRP1_PERIPH_UART5
EricLew	0:80ee8f3b695e	1184	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
EricLew	0:80ee8f3b695e	1185	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
EricLew	0:80ee8f3b695e	1186	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
EricLew	0:80ee8f3b695e	1187	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
EricLew	0:80ee8f3b695e	1188	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
EricLew	0:80ee8f3b695e	1189	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
EricLew	0:80ee8f3b695e	1190	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
EricLew	0:80ee8f3b695e	1191	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
EricLew	0:80ee8f3b695e	1192	* (*) value not defined in all devices.
EricLew	0:80ee8f3b695e	1193	* @retval None
EricLew	0:80ee8f3b695e	1194	*/
EricLew	0:80ee8f3b695e	1195	__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1196	{
EricLew	0:80ee8f3b695e	1197	CLEAR_BIT(RCC->APB1SMENR1, Periphs);
EricLew	0:80ee8f3b695e	1198	}
EricLew	0:80ee8f3b695e	1199
EricLew	0:80ee8f3b695e	1200	/**
EricLew	0:80ee8f3b695e	1201	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1202	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1203	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1204	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
EricLew	0:80ee8f3b695e	1205	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1206	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
EricLew	0:80ee8f3b695e	1207	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1
EricLew	0:80ee8f3b695e	1208	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
EricLew	0:80ee8f3b695e	1209	* @retval None
EricLew	0:80ee8f3b695e	1210	*/
EricLew	0:80ee8f3b695e	1211	__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1212	{
EricLew	0:80ee8f3b695e	1213	CLEAR_BIT(RCC->APB1SMENR2, Periphs);
EricLew	0:80ee8f3b695e	1214	}
EricLew	0:80ee8f3b695e	1215
EricLew	0:80ee8f3b695e	1216	/**
EricLew	0:80ee8f3b695e	1217	* @}
EricLew	0:80ee8f3b695e	1218	*/
EricLew	0:80ee8f3b695e	1219
EricLew	0:80ee8f3b695e	1220	/** @defgroup BUS_LL_EF_APB2 APB2
EricLew	0:80ee8f3b695e	1221	* @{
EricLew	0:80ee8f3b695e	1222	*/
EricLew	0:80ee8f3b695e	1223
EricLew	0:80ee8f3b695e	1224	/**
EricLew	0:80ee8f3b695e	1225	* @brief Enable APB2 peripherals clock.
EricLew	0:80ee8f3b695e	1226	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1227	* APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1228	* APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1229	* APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1230	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1231	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1232	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1233	* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1234	* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1235	* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1236	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1237	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
EricLew	0:80ee8f3b695e	1238	* APB2ENR DFSDMEN LL_APB2_GRP1_EnableClock
EricLew	0:80ee8f3b695e	1239	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1240	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1241	* @arg @ref LL_APB2_GRP1_PERIPH_FW
EricLew	0:80ee8f3b695e	1242	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1243	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1244	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1245	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1246	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1247	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1248	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1249	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1250	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1251	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1252	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1253	* @retval None
EricLew	0:80ee8f3b695e	1254	*/
EricLew	0:80ee8f3b695e	1255	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1256	{
EricLew	0:80ee8f3b695e	1257	SET_BIT(RCC->APB2ENR, Periphs);
EricLew	0:80ee8f3b695e	1258	}
EricLew	0:80ee8f3b695e	1259
EricLew	0:80ee8f3b695e	1260	/**
EricLew	0:80ee8f3b695e	1261	* @brief Check if APB2 peripheral clock is enabled or not
EricLew	0:80ee8f3b695e	1262	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1263	* APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1264	* APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1265	* APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1266	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1267	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1268	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1269	* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1270	* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1271	* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1272	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1273	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
EricLew	0:80ee8f3b695e	1274	* APB2ENR DFSDMEN LL_APB2_GRP1_IsEnabledClock
EricLew	0:80ee8f3b695e	1275	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1276	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1277	* @arg @ref LL_APB2_GRP1_PERIPH_FW
EricLew	0:80ee8f3b695e	1278	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1279	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1280	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1281	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1282	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1283	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1284	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1285	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1286	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1287	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1288	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1289	* @retval uint32_t
EricLew	0:80ee8f3b695e	1290	*/
EricLew	0:80ee8f3b695e	1291	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1292	{
EricLew	0:80ee8f3b695e	1293	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
EricLew	0:80ee8f3b695e	1294	}
EricLew	0:80ee8f3b695e	1295
EricLew	0:80ee8f3b695e	1296	/**
EricLew	0:80ee8f3b695e	1297	* @brief Disable APB2 peripherals clock.
EricLew	0:80ee8f3b695e	1298	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1299	* APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1300	* APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1301	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1302	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1303	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1304	* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1305	* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1306	* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1307	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1308	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
EricLew	0:80ee8f3b695e	1309	* APB2ENR DFSDMEN LL_APB2_GRP1_DisableClock
EricLew	0:80ee8f3b695e	1310	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1311	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1312	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1313	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1314	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1315	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1316	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1317	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1318	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1319	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1320	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1321	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1322	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1323	* @retval None
EricLew	0:80ee8f3b695e	1324	*/
EricLew	0:80ee8f3b695e	1325	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1326	{
EricLew	0:80ee8f3b695e	1327	CLEAR_BIT(RCC->APB2ENR, Periphs);
EricLew	0:80ee8f3b695e	1328	}
EricLew	0:80ee8f3b695e	1329
EricLew	0:80ee8f3b695e	1330	/**
EricLew	0:80ee8f3b695e	1331	* @brief Force APB2 peripherals reset.
EricLew	0:80ee8f3b695e	1332	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1333	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1334	* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1335	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1336	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1337	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1338	* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1339	* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1340	* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1341	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1342	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
EricLew	0:80ee8f3b695e	1343	* APB2RSTR DFSDMRST LL_APB2_GRP1_ForceReset
EricLew	0:80ee8f3b695e	1344	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1345	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	1346	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1347	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1348	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1349	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1350	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1351	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1352	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1353	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1354	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1355	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1356	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1357	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1358	* @retval None
EricLew	0:80ee8f3b695e	1359	*/
EricLew	0:80ee8f3b695e	1360	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1361	{
EricLew	0:80ee8f3b695e	1362	SET_BIT(RCC->APB2RSTR, Periphs);
EricLew	0:80ee8f3b695e	1363	}
EricLew	0:80ee8f3b695e	1364
EricLew	0:80ee8f3b695e	1365	/**
EricLew	0:80ee8f3b695e	1366	* @brief Release APB2 peripherals reset.
EricLew	0:80ee8f3b695e	1367	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1368	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1369	* APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1370	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1371	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1372	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1373	* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1374	* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1375	* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1376	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1377	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
EricLew	0:80ee8f3b695e	1378	* APB2RSTR DFSDMRST LL_APB2_GRP1_ReleaseReset
EricLew	0:80ee8f3b695e	1379	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1380	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
EricLew	0:80ee8f3b695e	1381	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1382	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1383	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1384	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1385	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1386	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1387	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1388	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1389	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1390	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1391	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1392	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1393	* @retval None
EricLew	0:80ee8f3b695e	1394	*/
EricLew	0:80ee8f3b695e	1395	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1396	{
EricLew	0:80ee8f3b695e	1397	CLEAR_BIT(RCC->APB2RSTR, Periphs);
EricLew	0:80ee8f3b695e	1398	}
EricLew	0:80ee8f3b695e	1399
EricLew	0:80ee8f3b695e	1400	/**
EricLew	0:80ee8f3b695e	1401	* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1402	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1403	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1404	* APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1405	* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1406	* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1407	* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1408	* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1409	* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1410	* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1411	* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1412	* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
EricLew	0:80ee8f3b695e	1413	* APB2SMENR DFSDMSMEN LL_APB2_GRP1_EnableClockStopSleep
EricLew	0:80ee8f3b695e	1414	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1415	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1416	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1417	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1418	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1419	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1420	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1421	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1422	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1423	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1424	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1425	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1426	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1427	* @retval None
EricLew	0:80ee8f3b695e	1428	*/
EricLew	0:80ee8f3b695e	1429	__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1430	{
EricLew	0:80ee8f3b695e	1431	SET_BIT(RCC->APB2SMENR, Periphs);
EricLew	0:80ee8f3b695e	1432	}
EricLew	0:80ee8f3b695e	1433
EricLew	0:80ee8f3b695e	1434	/**
EricLew	0:80ee8f3b695e	1435	* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
EricLew	0:80ee8f3b695e	1436	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1437	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1438	* APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1439	* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1440	* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1441	* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1442	* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1443	* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1444	* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1445	* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1446	* APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
EricLew	0:80ee8f3b695e	1447	* APB2SMENR DFSDMSMEN LL_APB2_GRP1_DisableClockStopSleep
EricLew	0:80ee8f3b695e	1448	* @param Periphs This parameter can be a combination of the following values:
EricLew	0:80ee8f3b695e	1449	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
EricLew	0:80ee8f3b695e	1450	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
EricLew	0:80ee8f3b695e	1451	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
EricLew	0:80ee8f3b695e	1452	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
EricLew	0:80ee8f3b695e	1453	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
EricLew	0:80ee8f3b695e	1454	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
EricLew	0:80ee8f3b695e	1455	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
EricLew	0:80ee8f3b695e	1456	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
EricLew	0:80ee8f3b695e	1457	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
EricLew	0:80ee8f3b695e	1458	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
EricLew	0:80ee8f3b695e	1459	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2
EricLew	0:80ee8f3b695e	1460	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM
EricLew	0:80ee8f3b695e	1461	* @retval None
EricLew	0:80ee8f3b695e	1462	*/
EricLew	0:80ee8f3b695e	1463	__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
EricLew	0:80ee8f3b695e	1464	{
EricLew	0:80ee8f3b695e	1465	CLEAR_BIT(RCC->APB2SMENR, Periphs);
EricLew	0:80ee8f3b695e	1466	}
EricLew	0:80ee8f3b695e	1467
EricLew	0:80ee8f3b695e	1468	/**
EricLew	0:80ee8f3b695e	1469	* @}
EricLew	0:80ee8f3b695e	1470	*/
EricLew	0:80ee8f3b695e	1471
EricLew	0:80ee8f3b695e	1472
EricLew	0:80ee8f3b695e	1473	/**
EricLew	0:80ee8f3b695e	1474	* @}
EricLew	0:80ee8f3b695e	1475	*/
EricLew	0:80ee8f3b695e	1476
EricLew	0:80ee8f3b695e	1477	/**
EricLew	0:80ee8f3b695e	1478	* @}
EricLew	0:80ee8f3b695e	1479	*/
EricLew	0:80ee8f3b695e	1480
EricLew	0:80ee8f3b695e	1481	#endif /* defined(RCC) */
EricLew	0:80ee8f3b695e	1482
EricLew	0:80ee8f3b695e	1483	/**
EricLew	0:80ee8f3b695e	1484	* @}
EricLew	0:80ee8f3b695e	1485	*/
EricLew	0:80ee8f3b695e	1486
EricLew	0:80ee8f3b695e	1487	#ifdef __cplusplus
EricLew	0:80ee8f3b695e	1488	}
EricLew	0:80ee8f3b695e	1489	#endif
EricLew	0:80ee8f3b695e	1490
EricLew	0:80ee8f3b695e	1491	#endif /* __STM32L4xx_LL_BUS_H */
EricLew	0:80ee8f3b695e	1492
EricLew	0:80ee8f3b695e	1493	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:80ee8f3b695e	1494

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Type:	Library
Created:	12 Nov 2015
Imports:	198
Forks:	0
Commits:	3
Dependents:	4
Dependencies:	0
Followers:	14

Inc/stm32l4xx_ll_bus.h@2:7aef7655b0a8, 2015-11-25 (annotated)

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